1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #ifndef _SIW_H 7 #define _SIW_H 8 9 #include <rdma/ib_verbs.h> 10 #include <rdma/restrack.h> 11 #include <linux/socket.h> 12 #include <linux/skbuff.h> 13 #include <crypto/hash.h> 14 #include <linux/crc32.h> 15 #include <linux/crc32c.h> 16 17 #include <rdma/siw-abi.h> 18 #include "iwarp.h" 19 20 #define SIW_VENDOR_ID 0x626d74 /* ascii 'bmt' for now */ 21 #define SIW_VENDORT_PART_ID 0 22 #define SIW_MAX_QP (1024 * 100) 23 #define SIW_MAX_QP_WR (1024 * 32) 24 #define SIW_MAX_ORD_QP 128 25 #define SIW_MAX_IRD_QP 128 26 #define SIW_MAX_SGE_PBL 256 /* max num sge's for PBL */ 27 #define SIW_MAX_SGE_RD 1 /* iwarp limitation. we could relax */ 28 #define SIW_MAX_CQ (1024 * 100) 29 #define SIW_MAX_CQE (SIW_MAX_QP_WR * 100) 30 #define SIW_MAX_MR (SIW_MAX_QP * 10) 31 #define SIW_MAX_PD SIW_MAX_QP 32 #define SIW_MAX_MW 0 /* to be set if MW's are supported */ 33 #define SIW_MAX_SRQ SIW_MAX_QP 34 #define SIW_MAX_SRQ_WR (SIW_MAX_QP_WR * 10) 35 #define SIW_MAX_CONTEXT SIW_MAX_PD 36 37 /* Min number of bytes for using zero copy transmit */ 38 #define SENDPAGE_THRESH PAGE_SIZE 39 40 /* Maximum number of frames which can be send in one SQ processing */ 41 #define SQ_USER_MAXBURST 100 42 43 /* Maximum number of consecutive IRQ elements which get served 44 * if SQ has pending work. Prevents starving local SQ processing 45 * by serving peer Read Requests. 46 */ 47 #define SIW_IRQ_MAXBURST_SQ_ACTIVE 4 48 49 struct siw_dev_cap { 50 int max_qp; 51 int max_qp_wr; 52 int max_ord; /* max. outbound read queue depth */ 53 int max_ird; /* max. inbound read queue depth */ 54 int max_sge; 55 int max_sge_rd; 56 int max_cq; 57 int max_cqe; 58 int max_mr; 59 int max_pd; 60 int max_mw; 61 int max_srq; 62 int max_srq_wr; 63 int max_srq_sge; 64 }; 65 66 struct siw_pd { 67 struct ib_pd base_pd; 68 }; 69 70 struct siw_device { 71 struct ib_device base_dev; 72 struct net_device *netdev; 73 struct siw_dev_cap attrs; 74 75 u32 vendor_part_id; 76 int numa_node; 77 char raw_gid[ETH_ALEN]; 78 79 /* physical port state (only one port per device) */ 80 enum ib_port_state state; 81 82 spinlock_t lock; 83 84 struct xarray qp_xa; 85 struct xarray mem_xa; 86 87 struct list_head cep_list; 88 struct list_head qp_list; 89 90 /* active objects statistics to enforce limits */ 91 atomic_t num_qp; 92 atomic_t num_cq; 93 atomic_t num_pd; 94 atomic_t num_mr; 95 atomic_t num_srq; 96 atomic_t num_ctx; 97 }; 98 99 struct siw_ucontext { 100 struct ib_ucontext base_ucontext; 101 struct siw_device *sdev; 102 }; 103 104 /* 105 * The RDMA core does not define LOCAL_READ access, which is always 106 * enabled implictely. 107 */ 108 #define IWARP_ACCESS_MASK \ 109 (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | \ 110 IB_ACCESS_REMOTE_READ) 111 112 /* 113 * siw presentation of user memory registered as source 114 * or target of RDMA operations. 115 */ 116 117 struct siw_page_chunk { 118 struct page **plist; 119 }; 120 121 struct siw_umem { 122 struct ib_umem *base_mem; 123 struct siw_page_chunk *page_chunk; 124 int num_pages; 125 u64 fp_addr; /* First page base address */ 126 }; 127 128 struct siw_pble { 129 dma_addr_t addr; /* Address of assigned buffer */ 130 unsigned int size; /* Size of this entry */ 131 unsigned long pbl_off; /* Total offset from start of PBL */ 132 }; 133 134 struct siw_pbl { 135 unsigned int num_buf; 136 unsigned int max_buf; 137 struct siw_pble pbe[] __counted_by(max_buf); 138 }; 139 140 /* 141 * Generic memory representation for registered siw memory. 142 * Memory lookup always via higher 24 bit of STag (STag index). 143 */ 144 struct siw_mem { 145 struct siw_device *sdev; 146 struct kref ref; 147 u64 va; /* VA of memory */ 148 u64 len; /* length of the memory buffer in bytes */ 149 u32 stag; /* iWarp memory access steering tag */ 150 u8 stag_valid; /* VALID or INVALID */ 151 u8 is_pbl; /* PBL or user space mem */ 152 u8 is_mw; /* Memory Region or Memory Window */ 153 enum ib_access_flags perms; /* local/remote READ & WRITE */ 154 union { 155 struct siw_umem *umem; 156 struct siw_pbl *pbl; 157 void *mem_obj; 158 }; 159 struct ib_pd *pd; 160 }; 161 162 struct siw_mr { 163 struct ib_mr base_mr; 164 struct siw_mem *mem; 165 struct rcu_head rcu; 166 }; 167 168 /* 169 * Error codes for local or remote 170 * access to registered memory 171 */ 172 enum siw_access_state { 173 E_ACCESS_OK, 174 E_STAG_INVALID, 175 E_BASE_BOUNDS, 176 E_ACCESS_PERM, 177 E_PD_MISMATCH 178 }; 179 180 enum siw_wr_state { 181 SIW_WR_IDLE, 182 SIW_WR_QUEUED, /* processing has not started yet */ 183 SIW_WR_INPROGRESS /* initiated processing of the WR */ 184 }; 185 186 /* The WQE currently being processed (RX or TX) */ 187 struct siw_wqe { 188 /* Copy of applications SQE or RQE */ 189 union { 190 struct siw_sqe sqe; 191 struct siw_rqe rqe; 192 }; 193 struct siw_mem *mem[SIW_MAX_SGE]; /* per sge's resolved mem */ 194 enum siw_wr_state wr_status; 195 enum siw_wc_status wc_status; 196 u32 bytes; /* total bytes to process */ 197 u32 processed; /* bytes processed */ 198 }; 199 200 struct siw_cq { 201 struct ib_cq base_cq; 202 spinlock_t lock; 203 struct siw_cq_ctrl *notify; 204 struct siw_cqe *queue; 205 u32 cq_put; 206 u32 cq_get; 207 u32 num_cqe; 208 struct rdma_user_mmap_entry *cq_entry; /* mmap info for CQE array */ 209 u32 id; /* For debugging only */ 210 }; 211 212 enum siw_qp_state { 213 SIW_QP_STATE_IDLE, 214 SIW_QP_STATE_RTR, 215 SIW_QP_STATE_RTS, 216 SIW_QP_STATE_CLOSING, 217 SIW_QP_STATE_TERMINATE, 218 SIW_QP_STATE_ERROR, 219 SIW_QP_STATE_COUNT 220 }; 221 222 enum siw_qp_flags { 223 SIW_RDMA_BIND_ENABLED = (1 << 0), 224 SIW_RDMA_WRITE_ENABLED = (1 << 1), 225 SIW_RDMA_READ_ENABLED = (1 << 2), 226 SIW_SIGNAL_ALL_WR = (1 << 3), 227 SIW_MPA_CRC = (1 << 4), 228 SIW_QP_IN_DESTROY = (1 << 5) 229 }; 230 231 enum siw_qp_attr_mask { 232 SIW_QP_ATTR_STATE = (1 << 0), 233 SIW_QP_ATTR_ACCESS_FLAGS = (1 << 1), 234 SIW_QP_ATTR_LLP_HANDLE = (1 << 2), 235 SIW_QP_ATTR_ORD = (1 << 3), 236 SIW_QP_ATTR_IRD = (1 << 4), 237 SIW_QP_ATTR_SQ_SIZE = (1 << 5), 238 SIW_QP_ATTR_RQ_SIZE = (1 << 6), 239 SIW_QP_ATTR_MPA = (1 << 7) 240 }; 241 242 struct siw_srq { 243 struct ib_srq base_srq; 244 spinlock_t lock; 245 u32 max_sge; 246 u32 limit; /* low watermark for async event */ 247 struct siw_rqe *recvq; 248 u32 rq_put; 249 u32 rq_get; 250 u32 num_rqe; /* max # of wqe's allowed */ 251 struct rdma_user_mmap_entry *srq_entry; /* mmap info for SRQ array */ 252 bool armed:1; /* inform user if limit hit */ 253 bool is_kernel_res:1; /* true if kernel client */ 254 }; 255 256 struct siw_qp_attrs { 257 enum siw_qp_state state; 258 u32 sq_size; 259 u32 rq_size; 260 u32 orq_size; 261 u32 irq_size; 262 u32 sq_max_sges; 263 u32 rq_max_sges; 264 enum siw_qp_flags flags; 265 266 struct socket *sk; 267 }; 268 269 enum siw_tx_ctx { 270 SIW_SEND_HDR, /* start or continue sending HDR */ 271 SIW_SEND_DATA, /* start or continue sending DDP payload */ 272 SIW_SEND_TRAILER, /* start or continue sending TRAILER */ 273 SIW_SEND_SHORT_FPDU/* send whole FPDU hdr|data|trailer at once */ 274 }; 275 276 enum siw_rx_state { 277 SIW_GET_HDR, /* await new hdr or within hdr */ 278 SIW_GET_DATA_START, /* start of inbound DDP payload */ 279 SIW_GET_DATA_MORE, /* continuation of (misaligned) DDP payload */ 280 SIW_GET_TRAILER/* await new trailer or within trailer */ 281 }; 282 283 struct siw_rx_stream { 284 struct sk_buff *skb; 285 int skb_new; /* pending unread bytes in skb */ 286 int skb_offset; /* offset in skb */ 287 int skb_copied; /* processed bytes in skb */ 288 289 enum siw_rx_state state; 290 291 union iwarp_hdr hdr; 292 struct mpa_trailer trailer; 293 struct shash_desc *mpa_crc_hd; 294 295 /* 296 * For each FPDU, main RX loop runs through 3 stages: 297 * Receiving protocol headers, placing DDP payload and receiving 298 * trailer information (CRC + possibly padding). 299 * Next two variables keep state on receive status of the 300 * current FPDU part (hdr, data, trailer). 301 */ 302 int fpdu_part_rcvd; /* bytes in pkt part copied */ 303 int fpdu_part_rem; /* bytes in pkt part not seen */ 304 305 /* 306 * Next expected DDP MSN for each QN + 307 * expected steering tag + 308 * expected DDP tagget offset (all HBO) 309 */ 310 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 311 u32 ddp_stag; 312 u64 ddp_to; 313 u32 inval_stag; /* Stag to be invalidated */ 314 315 u8 rx_suspend : 1; 316 u8 pad : 2; /* # of pad bytes expected */ 317 u8 rdmap_op : 4; /* opcode of current frame */ 318 }; 319 320 struct siw_rx_fpdu { 321 /* 322 * Local destination memory of inbound RDMA operation. 323 * Valid, according to wqe->wr_status 324 */ 325 struct siw_wqe wqe_active; 326 327 unsigned int pbl_idx; /* Index into current PBL */ 328 unsigned int sge_idx; /* current sge in rx */ 329 unsigned int sge_off; /* already rcvd in curr. sge */ 330 331 char first_ddp_seg; /* this is the first DDP seg */ 332 char more_ddp_segs; /* more DDP segs expected */ 333 u8 prev_rdmap_op : 4; /* opcode of prev frame */ 334 }; 335 336 /* 337 * Shorthands for short packets w/o payload 338 * to be transmitted more efficient. 339 */ 340 struct siw_send_pkt { 341 struct iwarp_send send; 342 __be32 crc; 343 }; 344 345 struct siw_write_pkt { 346 struct iwarp_rdma_write write; 347 __be32 crc; 348 }; 349 350 struct siw_rreq_pkt { 351 struct iwarp_rdma_rreq rreq; 352 __be32 crc; 353 }; 354 355 struct siw_rresp_pkt { 356 struct iwarp_rdma_rresp rresp; 357 __be32 crc; 358 }; 359 360 struct siw_iwarp_tx { 361 union { 362 union iwarp_hdr hdr; 363 364 /* Generic part of FPDU header */ 365 struct iwarp_ctrl ctrl; 366 struct iwarp_ctrl_untagged c_untagged; 367 struct iwarp_ctrl_tagged c_tagged; 368 369 /* FPDU headers */ 370 struct iwarp_rdma_write rwrite; 371 struct iwarp_rdma_rreq rreq; 372 struct iwarp_rdma_rresp rresp; 373 struct iwarp_terminate terminate; 374 struct iwarp_send send; 375 struct iwarp_send_inv send_inv; 376 377 /* complete short FPDUs */ 378 struct siw_send_pkt send_pkt; 379 struct siw_write_pkt write_pkt; 380 struct siw_rreq_pkt rreq_pkt; 381 struct siw_rresp_pkt rresp_pkt; 382 } pkt; 383 384 struct mpa_trailer trailer; 385 /* DDP MSN for untagged messages */ 386 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 387 388 enum siw_tx_ctx state; 389 u16 ctrl_len; /* ddp+rdmap hdr */ 390 u16 ctrl_sent; 391 int burst; 392 int bytes_unsent; /* ddp payload bytes */ 393 394 struct shash_desc *mpa_crc_hd; 395 396 u8 do_crc : 1; /* do crc for segment */ 397 u8 use_sendpage : 1; /* send w/o copy */ 398 u8 tx_suspend : 1; /* stop sending DDP segs. */ 399 u8 pad : 2; /* # pad in current fpdu */ 400 u8 orq_fence : 1; /* ORQ full or Send fenced */ 401 u8 in_syscall : 1; /* TX out of user context */ 402 u8 zcopy_tx : 1; /* Use TCP_SENDPAGE if possible */ 403 u8 gso_seg_limit; /* Maximum segments for GSO, 0 = unbound */ 404 405 u16 fpdu_len; /* len of FPDU to tx */ 406 unsigned int tcp_seglen; /* remaining tcp seg space */ 407 408 struct siw_wqe wqe_active; 409 410 int pbl_idx; /* Index into current PBL */ 411 int sge_idx; /* current sge in tx */ 412 u32 sge_off; /* already sent in curr. sge */ 413 }; 414 415 struct siw_qp { 416 struct ib_qp base_qp; 417 struct siw_device *sdev; 418 int tx_cpu; 419 struct kref ref; 420 struct completion qp_free; 421 struct list_head devq; 422 struct siw_qp_attrs attrs; 423 424 struct siw_cep *cep; 425 struct rw_semaphore state_lock; 426 427 struct ib_pd *pd; 428 struct siw_cq *scq; 429 struct siw_cq *rcq; 430 struct siw_srq *srq; 431 432 struct siw_iwarp_tx tx_ctx; /* Transmit context */ 433 spinlock_t sq_lock; 434 struct siw_sqe *sendq; /* send queue element array */ 435 uint32_t sq_get; /* consumer index into sq array */ 436 uint32_t sq_put; /* kernel prod. index into sq array */ 437 struct llist_node tx_list; 438 439 struct siw_sqe *orq; /* outbound read queue element array */ 440 spinlock_t orq_lock; 441 uint32_t orq_get; /* consumer index into orq array */ 442 uint32_t orq_put; /* shared producer index for ORQ */ 443 444 struct siw_rx_stream rx_stream; 445 struct siw_rx_fpdu *rx_fpdu; 446 struct siw_rx_fpdu rx_tagged; 447 struct siw_rx_fpdu rx_untagged; 448 spinlock_t rq_lock; 449 struct siw_rqe *recvq; /* recv queue element array */ 450 uint32_t rq_get; /* consumer index into rq array */ 451 uint32_t rq_put; /* kernel prod. index into rq array */ 452 453 struct siw_sqe *irq; /* inbound read queue element array */ 454 uint32_t irq_get; /* consumer index into irq array */ 455 uint32_t irq_put; /* producer index into irq array */ 456 int irq_burst; 457 458 struct { /* information to be carried in TERMINATE pkt, if valid */ 459 u8 valid; 460 u8 in_tx; 461 u8 layer : 4, etype : 4; 462 u8 ecode; 463 } term_info; 464 struct rdma_user_mmap_entry *sq_entry; /* mmap info for SQE array */ 465 struct rdma_user_mmap_entry *rq_entry; /* mmap info for RQE array */ 466 }; 467 468 /* helper macros */ 469 #define rx_qp(rx) container_of(rx, struct siw_qp, rx_stream) 470 #define tx_qp(tx) container_of(tx, struct siw_qp, tx_ctx) 471 #define tx_wqe(qp) (&(qp)->tx_ctx.wqe_active) 472 #define rx_wqe(rctx) (&(rctx)->wqe_active) 473 #define rx_mem(rctx) ((rctx)->wqe_active.mem[0]) 474 #define tx_type(wqe) ((wqe)->sqe.opcode) 475 #define rx_type(wqe) ((wqe)->rqe.opcode) 476 #define tx_flags(wqe) ((wqe)->sqe.flags) 477 478 struct iwarp_msg_info { 479 int hdr_len; 480 struct iwarp_ctrl ctrl; 481 int (*rx_data)(struct siw_qp *qp); 482 }; 483 484 struct siw_user_mmap_entry { 485 struct rdma_user_mmap_entry rdma_entry; 486 void *address; 487 }; 488 489 /* Global siw parameters. Currently set in siw_main.c */ 490 extern const bool zcopy_tx; 491 extern const bool try_gso; 492 extern const bool loopback_enabled; 493 extern const bool mpa_crc_required; 494 extern const bool mpa_crc_strict; 495 extern const bool siw_tcp_nagle; 496 extern u_char mpa_version; 497 extern const bool peer_to_peer; 498 extern struct task_struct *siw_tx_thread[]; 499 500 extern struct crypto_shash *siw_crypto_shash; 501 extern struct iwarp_msg_info iwarp_pktinfo[RDMAP_TERMINATE + 1]; 502 503 /* QP general functions */ 504 int siw_qp_modify(struct siw_qp *qp, struct siw_qp_attrs *attr, 505 enum siw_qp_attr_mask mask); 506 int siw_qp_mpa_rts(struct siw_qp *qp, enum mpa_v2_ctrl ctrl); 507 void siw_qp_llp_close(struct siw_qp *qp); 508 void siw_qp_cm_drop(struct siw_qp *qp, int schedule); 509 void siw_send_terminate(struct siw_qp *qp); 510 511 void siw_qp_get_ref(struct ib_qp *qp); 512 void siw_qp_put_ref(struct ib_qp *qp); 513 int siw_qp_add(struct siw_device *sdev, struct siw_qp *qp); 514 void siw_free_qp(struct kref *ref); 515 516 void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer, 517 u8 etype, u8 ecode, int in_tx); 518 enum ddp_ecode siw_tagged_error(enum siw_access_state state); 519 enum rdmap_ecode siw_rdmap_error(enum siw_access_state state); 520 521 void siw_read_to_orq(struct siw_sqe *rreq, struct siw_sqe *sqe); 522 int siw_sqe_complete(struct siw_qp *qp, struct siw_sqe *sqe, u32 bytes, 523 enum siw_wc_status status); 524 int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes, 525 u32 inval_stag, enum siw_wc_status status); 526 void siw_qp_llp_data_ready(struct sock *sk); 527 void siw_qp_llp_write_space(struct sock *sk); 528 529 /* QP TX path functions */ 530 int siw_create_tx_threads(void); 531 void siw_stop_tx_threads(void); 532 int siw_run_sq(void *arg); 533 int siw_qp_sq_process(struct siw_qp *qp); 534 int siw_sq_start(struct siw_qp *qp); 535 int siw_activate_tx(struct siw_qp *qp); 536 int siw_get_tx_cpu(struct siw_device *sdev); 537 void siw_put_tx_cpu(int cpu); 538 539 /* QP RX path functions */ 540 int siw_proc_send(struct siw_qp *qp); 541 int siw_proc_rreq(struct siw_qp *qp); 542 int siw_proc_rresp(struct siw_qp *qp); 543 int siw_proc_write(struct siw_qp *qp); 544 int siw_proc_terminate(struct siw_qp *qp); 545 546 int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb, 547 unsigned int off, size_t len); 548 549 static inline void set_rx_fpdu_context(struct siw_qp *qp, u8 opcode) 550 { 551 if (opcode == RDMAP_RDMA_WRITE || opcode == RDMAP_RDMA_READ_RESP) 552 qp->rx_fpdu = &qp->rx_tagged; 553 else 554 qp->rx_fpdu = &qp->rx_untagged; 555 556 qp->rx_stream.rdmap_op = opcode; 557 } 558 559 static inline struct siw_ucontext *to_siw_ctx(struct ib_ucontext *base_ctx) 560 { 561 return container_of(base_ctx, struct siw_ucontext, base_ucontext); 562 } 563 564 static inline struct siw_qp *to_siw_qp(struct ib_qp *base_qp) 565 { 566 return container_of(base_qp, struct siw_qp, base_qp); 567 } 568 569 static inline struct siw_cq *to_siw_cq(struct ib_cq *base_cq) 570 { 571 return container_of(base_cq, struct siw_cq, base_cq); 572 } 573 574 static inline struct siw_srq *to_siw_srq(struct ib_srq *base_srq) 575 { 576 return container_of(base_srq, struct siw_srq, base_srq); 577 } 578 579 static inline struct siw_device *to_siw_dev(struct ib_device *base_dev) 580 { 581 return container_of(base_dev, struct siw_device, base_dev); 582 } 583 584 static inline struct siw_mr *to_siw_mr(struct ib_mr *base_mr) 585 { 586 return container_of(base_mr, struct siw_mr, base_mr); 587 } 588 589 static inline struct siw_user_mmap_entry * 590 to_siw_mmap_entry(struct rdma_user_mmap_entry *rdma_mmap) 591 { 592 return container_of(rdma_mmap, struct siw_user_mmap_entry, rdma_entry); 593 } 594 595 static inline struct siw_qp *siw_qp_id2obj(struct siw_device *sdev, int id) 596 { 597 struct siw_qp *qp; 598 599 rcu_read_lock(); 600 qp = xa_load(&sdev->qp_xa, id); 601 if (likely(qp && kref_get_unless_zero(&qp->ref))) { 602 rcu_read_unlock(); 603 return qp; 604 } 605 rcu_read_unlock(); 606 return NULL; 607 } 608 609 static inline u32 qp_id(struct siw_qp *qp) 610 { 611 return qp->base_qp.qp_num; 612 } 613 614 static inline void siw_qp_get(struct siw_qp *qp) 615 { 616 kref_get(&qp->ref); 617 } 618 619 static inline void siw_qp_put(struct siw_qp *qp) 620 { 621 kref_put(&qp->ref, siw_free_qp); 622 } 623 624 static inline int siw_sq_empty(struct siw_qp *qp) 625 { 626 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 627 628 return READ_ONCE(sqe->flags) == 0; 629 } 630 631 static inline struct siw_sqe *sq_get_next(struct siw_qp *qp) 632 { 633 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 634 635 if (READ_ONCE(sqe->flags) & SIW_WQE_VALID) 636 return sqe; 637 638 return NULL; 639 } 640 641 static inline struct siw_sqe *orq_get_current(struct siw_qp *qp) 642 { 643 return &qp->orq[qp->orq_get % qp->attrs.orq_size]; 644 } 645 646 static inline struct siw_sqe *orq_get_free(struct siw_qp *qp) 647 { 648 struct siw_sqe *orq_e = &qp->orq[qp->orq_put % qp->attrs.orq_size]; 649 650 if (READ_ONCE(orq_e->flags) == 0) 651 return orq_e; 652 653 return NULL; 654 } 655 656 static inline int siw_orq_empty(struct siw_qp *qp) 657 { 658 return orq_get_current(qp)->flags == 0 ? 1 : 0; 659 } 660 661 static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp) 662 { 663 struct siw_sqe *irq_e = &qp->irq[qp->irq_put % qp->attrs.irq_size]; 664 665 if (READ_ONCE(irq_e->flags) == 0) { 666 qp->irq_put++; 667 return irq_e; 668 } 669 return NULL; 670 } 671 672 static inline __wsum siw_csum_update(const void *buff, int len, __wsum sum) 673 { 674 return (__force __wsum)crc32c((__force __u32)sum, buff, len); 675 } 676 677 static inline __wsum siw_csum_combine(__wsum csum, __wsum csum2, int offset, 678 int len) 679 { 680 return (__force __wsum)__crc32c_le_combine((__force __u32)csum, 681 (__force __u32)csum2, len); 682 } 683 684 static inline void siw_crc_skb(struct siw_rx_stream *srx, unsigned int len) 685 { 686 const struct skb_checksum_ops siw_cs_ops = { 687 .update = siw_csum_update, 688 .combine = siw_csum_combine, 689 }; 690 __wsum crc = *(u32 *)shash_desc_ctx(srx->mpa_crc_hd); 691 692 crc = __skb_checksum(srx->skb, srx->skb_offset, len, crc, 693 &siw_cs_ops); 694 *(u32 *)shash_desc_ctx(srx->mpa_crc_hd) = crc; 695 } 696 697 #define siw_dbg(ibdev, fmt, ...) \ 698 ibdev_dbg(ibdev, "%s: " fmt, __func__, ##__VA_ARGS__) 699 700 #define siw_dbg_qp(qp, fmt, ...) \ 701 ibdev_dbg(&qp->sdev->base_dev, "QP[%u] %s: " fmt, qp_id(qp), __func__, \ 702 ##__VA_ARGS__) 703 704 #define siw_dbg_cq(cq, fmt, ...) \ 705 ibdev_dbg(cq->base_cq.device, "CQ[%u] %s: " fmt, cq->id, __func__, \ 706 ##__VA_ARGS__) 707 708 #define siw_dbg_pd(pd, fmt, ...) \ 709 ibdev_dbg(pd->device, "PD[%u] %s: " fmt, pd->res.id, __func__, \ 710 ##__VA_ARGS__) 711 712 #define siw_dbg_mem(mem, fmt, ...) \ 713 ibdev_dbg(&mem->sdev->base_dev, \ 714 "MEM[0x%08x] %s: " fmt, mem->stag, __func__, ##__VA_ARGS__) 715 716 #define siw_dbg_cep(cep, fmt, ...) \ 717 ibdev_dbg(&cep->sdev->base_dev, "CEP[0x%pK] %s: " fmt, \ 718 cep, __func__, ##__VA_ARGS__) 719 720 void siw_cq_flush(struct siw_cq *cq); 721 void siw_sq_flush(struct siw_qp *qp); 722 void siw_rq_flush(struct siw_qp *qp); 723 int siw_reap_cqe(struct siw_cq *cq, struct ib_wc *wc); 724 725 #endif 726