1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 4 * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 5 */ 6 7 #ifndef RXE_OPCODE_H 8 #define RXE_OPCODE_H 9 10 /* 11 * contains header bit mask definitions and header lengths 12 * declaration of the rxe_opcode_info struct and 13 * rxe_wr_opcode_info struct 14 */ 15 16 enum rxe_wr_mask { 17 WR_INLINE_MASK = BIT(0), 18 WR_ATOMIC_MASK = BIT(1), 19 WR_SEND_MASK = BIT(2), 20 WR_READ_MASK = BIT(3), 21 WR_WRITE_MASK = BIT(4), 22 WR_LOCAL_OP_MASK = BIT(5), 23 24 WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 25 WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 26 WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 27 }; 28 29 #define WR_MAX_QPT (8) 30 31 struct rxe_wr_opcode_info { 32 char *name; 33 enum rxe_wr_mask mask[WR_MAX_QPT]; 34 }; 35 36 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 37 38 enum rxe_hdr_type { 39 RXE_LRH, 40 RXE_GRH, 41 RXE_BTH, 42 RXE_RETH, 43 RXE_AETH, 44 RXE_ATMETH, 45 RXE_ATMACK, 46 RXE_IETH, 47 RXE_RDETH, 48 RXE_DETH, 49 RXE_IMMDT, 50 RXE_PAYLOAD, 51 NUM_HDR_TYPES 52 }; 53 54 enum rxe_hdr_mask { 55 RXE_LRH_MASK = BIT(RXE_LRH), 56 RXE_GRH_MASK = BIT(RXE_GRH), 57 RXE_BTH_MASK = BIT(RXE_BTH), 58 RXE_IMMDT_MASK = BIT(RXE_IMMDT), 59 RXE_RETH_MASK = BIT(RXE_RETH), 60 RXE_AETH_MASK = BIT(RXE_AETH), 61 RXE_ATMETH_MASK = BIT(RXE_ATMETH), 62 RXE_ATMACK_MASK = BIT(RXE_ATMACK), 63 RXE_IETH_MASK = BIT(RXE_IETH), 64 RXE_RDETH_MASK = BIT(RXE_RDETH), 65 RXE_DETH_MASK = BIT(RXE_DETH), 66 RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 67 68 RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 69 RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 70 RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 71 RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 72 RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 73 RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 74 75 RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), 76 RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), 77 78 RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), 79 RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), 80 RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), 81 82 RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 83 84 RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK), 85 RXE_WRITE_OR_SEND_MASK = (RXE_WRITE_MASK | RXE_SEND_MASK), 86 RXE_READ_OR_WRITE_MASK = (RXE_READ_MASK | RXE_WRITE_MASK), 87 }; 88 89 #define OPCODE_NONE (-1) 90 #define RXE_NUM_OPCODE 256 91 92 struct rxe_opcode_info { 93 char *name; 94 enum rxe_hdr_mask mask; 95 int length; 96 int offset[NUM_HDR_TYPES]; 97 }; 98 99 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 100 101 #endif /* RXE_OPCODE_H */ 102