1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 4 * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 5 */ 6 7 #ifndef RXE_OPCODE_H 8 #define RXE_OPCODE_H 9 10 /* 11 * contains header bit mask definitions and header lengths 12 * declaration of the rxe_opcode_info struct and 13 * rxe_wr_opcode_info struct 14 */ 15 16 enum rxe_wr_mask { 17 WR_INLINE_MASK = BIT(0), 18 WR_ATOMIC_MASK = BIT(1), 19 WR_SEND_MASK = BIT(2), 20 WR_READ_MASK = BIT(3), 21 WR_WRITE_MASK = BIT(4), 22 WR_LOCAL_OP_MASK = BIT(5), 23 WR_FLUSH_MASK = BIT(6), 24 WR_ATOMIC_WRITE_MASK = BIT(7), 25 26 WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 27 WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 28 WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 29 }; 30 31 #define WR_MAX_QPT (8) 32 33 struct rxe_wr_opcode_info { 34 char *name; 35 enum rxe_wr_mask mask[WR_MAX_QPT]; 36 }; 37 38 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 39 40 enum rxe_hdr_type { 41 RXE_LRH, 42 RXE_GRH, 43 RXE_BTH, 44 RXE_RETH, 45 RXE_AETH, 46 RXE_ATMETH, 47 RXE_ATMACK, 48 RXE_IETH, 49 RXE_RDETH, 50 RXE_DETH, 51 RXE_IMMDT, 52 RXE_FETH, 53 RXE_PAYLOAD, 54 NUM_HDR_TYPES 55 }; 56 57 enum rxe_hdr_mask { 58 RXE_LRH_MASK = BIT(RXE_LRH), 59 RXE_GRH_MASK = BIT(RXE_GRH), 60 RXE_BTH_MASK = BIT(RXE_BTH), 61 RXE_IMMDT_MASK = BIT(RXE_IMMDT), 62 RXE_RETH_MASK = BIT(RXE_RETH), 63 RXE_AETH_MASK = BIT(RXE_AETH), 64 RXE_ATMETH_MASK = BIT(RXE_ATMETH), 65 RXE_ATMACK_MASK = BIT(RXE_ATMACK), 66 RXE_IETH_MASK = BIT(RXE_IETH), 67 RXE_RDETH_MASK = BIT(RXE_RDETH), 68 RXE_DETH_MASK = BIT(RXE_DETH), 69 RXE_FETH_MASK = BIT(RXE_FETH), 70 RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 71 72 RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 73 RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 74 RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 75 RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 76 RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 77 RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 78 RXE_FLUSH_MASK = BIT(NUM_HDR_TYPES + 6), 79 80 RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 7), 81 RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 8), 82 83 RXE_START_MASK = BIT(NUM_HDR_TYPES + 9), 84 RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 10), 85 RXE_END_MASK = BIT(NUM_HDR_TYPES + 11), 86 87 RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 88 89 RXE_ATOMIC_WRITE_MASK = BIT(NUM_HDR_TYPES + 14), 90 91 RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK), 92 RXE_WRITE_OR_SEND_MASK = (RXE_WRITE_MASK | RXE_SEND_MASK), 93 RXE_READ_OR_WRITE_MASK = (RXE_READ_MASK | RXE_WRITE_MASK), 94 RXE_RDMA_OP_MASK = (RXE_READ_MASK | RXE_WRITE_MASK | 95 RXE_ATOMIC_WRITE_MASK | RXE_FLUSH_MASK | 96 RXE_ATOMIC_MASK), 97 }; 98 99 #define OPCODE_NONE (-1) 100 #define RXE_NUM_OPCODE 256 101 102 struct rxe_opcode_info { 103 char *name; 104 enum rxe_hdr_mask mask; 105 int length; 106 int offset[NUM_HDR_TYPES]; 107 }; 108 109 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 110 111 #endif /* RXE_OPCODE_H */ 112