1*8700e3e7SMoni Shoua /* 2*8700e3e7SMoni Shoua * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 3*8700e3e7SMoni Shoua * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 4*8700e3e7SMoni Shoua * 5*8700e3e7SMoni Shoua * This software is available to you under a choice of one of two 6*8700e3e7SMoni Shoua * licenses. You may choose to be licensed under the terms of the GNU 7*8700e3e7SMoni Shoua * General Public License (GPL) Version 2, available from the file 8*8700e3e7SMoni Shoua * COPYING in the main directory of this source tree, or the 9*8700e3e7SMoni Shoua * OpenIB.org BSD license below: 10*8700e3e7SMoni Shoua * 11*8700e3e7SMoni Shoua * Redistribution and use in source and binary forms, with or 12*8700e3e7SMoni Shoua * without modification, are permitted provided that the following 13*8700e3e7SMoni Shoua * conditions are met: 14*8700e3e7SMoni Shoua * 15*8700e3e7SMoni Shoua * - Redistributions of source code must retain the above 16*8700e3e7SMoni Shoua * copyright notice, this list of conditions and the following 17*8700e3e7SMoni Shoua * disclaimer. 18*8700e3e7SMoni Shoua * 19*8700e3e7SMoni Shoua * - Redistributions in binary form must reproduce the above 20*8700e3e7SMoni Shoua * copyright notice, this list of conditions and the following 21*8700e3e7SMoni Shoua * disclaimer in the documentation and/or other materials 22*8700e3e7SMoni Shoua * provided with the distribution. 23*8700e3e7SMoni Shoua * 24*8700e3e7SMoni Shoua * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*8700e3e7SMoni Shoua * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*8700e3e7SMoni Shoua * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*8700e3e7SMoni Shoua * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*8700e3e7SMoni Shoua * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*8700e3e7SMoni Shoua * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*8700e3e7SMoni Shoua * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*8700e3e7SMoni Shoua * SOFTWARE. 32*8700e3e7SMoni Shoua */ 33*8700e3e7SMoni Shoua 34*8700e3e7SMoni Shoua #ifndef RXE_OPCODE_H 35*8700e3e7SMoni Shoua #define RXE_OPCODE_H 36*8700e3e7SMoni Shoua 37*8700e3e7SMoni Shoua /* 38*8700e3e7SMoni Shoua * contains header bit mask definitions and header lengths 39*8700e3e7SMoni Shoua * declaration of the rxe_opcode_info struct and 40*8700e3e7SMoni Shoua * rxe_wr_opcode_info struct 41*8700e3e7SMoni Shoua */ 42*8700e3e7SMoni Shoua 43*8700e3e7SMoni Shoua enum rxe_wr_mask { 44*8700e3e7SMoni Shoua WR_INLINE_MASK = BIT(0), 45*8700e3e7SMoni Shoua WR_ATOMIC_MASK = BIT(1), 46*8700e3e7SMoni Shoua WR_SEND_MASK = BIT(2), 47*8700e3e7SMoni Shoua WR_READ_MASK = BIT(3), 48*8700e3e7SMoni Shoua WR_WRITE_MASK = BIT(4), 49*8700e3e7SMoni Shoua WR_LOCAL_MASK = BIT(5), 50*8700e3e7SMoni Shoua WR_REG_MASK = BIT(6), 51*8700e3e7SMoni Shoua 52*8700e3e7SMoni Shoua WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 53*8700e3e7SMoni Shoua WR_READ_WRITE_OR_SEND_MASK = WR_READ_OR_WRITE_MASK | WR_SEND_MASK, 54*8700e3e7SMoni Shoua WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 55*8700e3e7SMoni Shoua WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 56*8700e3e7SMoni Shoua }; 57*8700e3e7SMoni Shoua 58*8700e3e7SMoni Shoua #define WR_MAX_QPT (8) 59*8700e3e7SMoni Shoua 60*8700e3e7SMoni Shoua struct rxe_wr_opcode_info { 61*8700e3e7SMoni Shoua char *name; 62*8700e3e7SMoni Shoua enum rxe_wr_mask mask[WR_MAX_QPT]; 63*8700e3e7SMoni Shoua }; 64*8700e3e7SMoni Shoua 65*8700e3e7SMoni Shoua extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 66*8700e3e7SMoni Shoua 67*8700e3e7SMoni Shoua enum rxe_hdr_type { 68*8700e3e7SMoni Shoua RXE_LRH, 69*8700e3e7SMoni Shoua RXE_GRH, 70*8700e3e7SMoni Shoua RXE_BTH, 71*8700e3e7SMoni Shoua RXE_RETH, 72*8700e3e7SMoni Shoua RXE_AETH, 73*8700e3e7SMoni Shoua RXE_ATMETH, 74*8700e3e7SMoni Shoua RXE_ATMACK, 75*8700e3e7SMoni Shoua RXE_IETH, 76*8700e3e7SMoni Shoua RXE_RDETH, 77*8700e3e7SMoni Shoua RXE_DETH, 78*8700e3e7SMoni Shoua RXE_IMMDT, 79*8700e3e7SMoni Shoua RXE_PAYLOAD, 80*8700e3e7SMoni Shoua NUM_HDR_TYPES 81*8700e3e7SMoni Shoua }; 82*8700e3e7SMoni Shoua 83*8700e3e7SMoni Shoua enum rxe_hdr_mask { 84*8700e3e7SMoni Shoua RXE_LRH_MASK = BIT(RXE_LRH), 85*8700e3e7SMoni Shoua RXE_GRH_MASK = BIT(RXE_GRH), 86*8700e3e7SMoni Shoua RXE_BTH_MASK = BIT(RXE_BTH), 87*8700e3e7SMoni Shoua RXE_IMMDT_MASK = BIT(RXE_IMMDT), 88*8700e3e7SMoni Shoua RXE_RETH_MASK = BIT(RXE_RETH), 89*8700e3e7SMoni Shoua RXE_AETH_MASK = BIT(RXE_AETH), 90*8700e3e7SMoni Shoua RXE_ATMETH_MASK = BIT(RXE_ATMETH), 91*8700e3e7SMoni Shoua RXE_ATMACK_MASK = BIT(RXE_ATMACK), 92*8700e3e7SMoni Shoua RXE_IETH_MASK = BIT(RXE_IETH), 93*8700e3e7SMoni Shoua RXE_RDETH_MASK = BIT(RXE_RDETH), 94*8700e3e7SMoni Shoua RXE_DETH_MASK = BIT(RXE_DETH), 95*8700e3e7SMoni Shoua RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 96*8700e3e7SMoni Shoua 97*8700e3e7SMoni Shoua RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 98*8700e3e7SMoni Shoua RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 99*8700e3e7SMoni Shoua RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 100*8700e3e7SMoni Shoua RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 101*8700e3e7SMoni Shoua RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 102*8700e3e7SMoni Shoua RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 103*8700e3e7SMoni Shoua 104*8700e3e7SMoni Shoua RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), 105*8700e3e7SMoni Shoua RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), 106*8700e3e7SMoni Shoua 107*8700e3e7SMoni Shoua RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), 108*8700e3e7SMoni Shoua RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), 109*8700e3e7SMoni Shoua RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), 110*8700e3e7SMoni Shoua 111*8700e3e7SMoni Shoua RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 112*8700e3e7SMoni Shoua 113*8700e3e7SMoni Shoua RXE_READ_OR_ATOMIC = (RXE_READ_MASK | RXE_ATOMIC_MASK), 114*8700e3e7SMoni Shoua RXE_WRITE_OR_SEND = (RXE_WRITE_MASK | RXE_SEND_MASK), 115*8700e3e7SMoni Shoua }; 116*8700e3e7SMoni Shoua 117*8700e3e7SMoni Shoua #define OPCODE_NONE (-1) 118*8700e3e7SMoni Shoua #define RXE_NUM_OPCODE 256 119*8700e3e7SMoni Shoua 120*8700e3e7SMoni Shoua struct rxe_opcode_info { 121*8700e3e7SMoni Shoua char *name; 122*8700e3e7SMoni Shoua enum rxe_hdr_mask mask; 123*8700e3e7SMoni Shoua int length; 124*8700e3e7SMoni Shoua int offset[NUM_HDR_TYPES]; 125*8700e3e7SMoni Shoua }; 126*8700e3e7SMoni Shoua 127*8700e3e7SMoni Shoua extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 128*8700e3e7SMoni Shoua 129*8700e3e7SMoni Shoua #endif /* RXE_OPCODE_H */ 130