1*63fa15dbSBob Pearson /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 28700e3e7SMoni Shoua /* 38700e3e7SMoni Shoua * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 48700e3e7SMoni Shoua * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 58700e3e7SMoni Shoua */ 68700e3e7SMoni Shoua 78700e3e7SMoni Shoua #ifndef RXE_OPCODE_H 88700e3e7SMoni Shoua #define RXE_OPCODE_H 98700e3e7SMoni Shoua 108700e3e7SMoni Shoua /* 118700e3e7SMoni Shoua * contains header bit mask definitions and header lengths 128700e3e7SMoni Shoua * declaration of the rxe_opcode_info struct and 138700e3e7SMoni Shoua * rxe_wr_opcode_info struct 148700e3e7SMoni Shoua */ 158700e3e7SMoni Shoua 168700e3e7SMoni Shoua enum rxe_wr_mask { 178700e3e7SMoni Shoua WR_INLINE_MASK = BIT(0), 188700e3e7SMoni Shoua WR_ATOMIC_MASK = BIT(1), 198700e3e7SMoni Shoua WR_SEND_MASK = BIT(2), 208700e3e7SMoni Shoua WR_READ_MASK = BIT(3), 218700e3e7SMoni Shoua WR_WRITE_MASK = BIT(4), 228700e3e7SMoni Shoua WR_LOCAL_MASK = BIT(5), 238700e3e7SMoni Shoua WR_REG_MASK = BIT(6), 248700e3e7SMoni Shoua 258700e3e7SMoni Shoua WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 268700e3e7SMoni Shoua WR_READ_WRITE_OR_SEND_MASK = WR_READ_OR_WRITE_MASK | WR_SEND_MASK, 278700e3e7SMoni Shoua WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 288700e3e7SMoni Shoua WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 298700e3e7SMoni Shoua }; 308700e3e7SMoni Shoua 318700e3e7SMoni Shoua #define WR_MAX_QPT (8) 328700e3e7SMoni Shoua 338700e3e7SMoni Shoua struct rxe_wr_opcode_info { 348700e3e7SMoni Shoua char *name; 358700e3e7SMoni Shoua enum rxe_wr_mask mask[WR_MAX_QPT]; 368700e3e7SMoni Shoua }; 378700e3e7SMoni Shoua 388700e3e7SMoni Shoua extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 398700e3e7SMoni Shoua 408700e3e7SMoni Shoua enum rxe_hdr_type { 418700e3e7SMoni Shoua RXE_LRH, 428700e3e7SMoni Shoua RXE_GRH, 438700e3e7SMoni Shoua RXE_BTH, 448700e3e7SMoni Shoua RXE_RETH, 458700e3e7SMoni Shoua RXE_AETH, 468700e3e7SMoni Shoua RXE_ATMETH, 478700e3e7SMoni Shoua RXE_ATMACK, 488700e3e7SMoni Shoua RXE_IETH, 498700e3e7SMoni Shoua RXE_RDETH, 508700e3e7SMoni Shoua RXE_DETH, 518700e3e7SMoni Shoua RXE_IMMDT, 528700e3e7SMoni Shoua RXE_PAYLOAD, 538700e3e7SMoni Shoua NUM_HDR_TYPES 548700e3e7SMoni Shoua }; 558700e3e7SMoni Shoua 568700e3e7SMoni Shoua enum rxe_hdr_mask { 578700e3e7SMoni Shoua RXE_LRH_MASK = BIT(RXE_LRH), 588700e3e7SMoni Shoua RXE_GRH_MASK = BIT(RXE_GRH), 598700e3e7SMoni Shoua RXE_BTH_MASK = BIT(RXE_BTH), 608700e3e7SMoni Shoua RXE_IMMDT_MASK = BIT(RXE_IMMDT), 618700e3e7SMoni Shoua RXE_RETH_MASK = BIT(RXE_RETH), 628700e3e7SMoni Shoua RXE_AETH_MASK = BIT(RXE_AETH), 638700e3e7SMoni Shoua RXE_ATMETH_MASK = BIT(RXE_ATMETH), 648700e3e7SMoni Shoua RXE_ATMACK_MASK = BIT(RXE_ATMACK), 658700e3e7SMoni Shoua RXE_IETH_MASK = BIT(RXE_IETH), 668700e3e7SMoni Shoua RXE_RDETH_MASK = BIT(RXE_RDETH), 678700e3e7SMoni Shoua RXE_DETH_MASK = BIT(RXE_DETH), 688700e3e7SMoni Shoua RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 698700e3e7SMoni Shoua 708700e3e7SMoni Shoua RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 718700e3e7SMoni Shoua RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 728700e3e7SMoni Shoua RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 738700e3e7SMoni Shoua RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 748700e3e7SMoni Shoua RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 758700e3e7SMoni Shoua RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 768700e3e7SMoni Shoua 778700e3e7SMoni Shoua RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), 788700e3e7SMoni Shoua RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), 798700e3e7SMoni Shoua 808700e3e7SMoni Shoua RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), 818700e3e7SMoni Shoua RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), 828700e3e7SMoni Shoua RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), 838700e3e7SMoni Shoua 848700e3e7SMoni Shoua RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 858700e3e7SMoni Shoua 868700e3e7SMoni Shoua RXE_READ_OR_ATOMIC = (RXE_READ_MASK | RXE_ATOMIC_MASK), 878700e3e7SMoni Shoua RXE_WRITE_OR_SEND = (RXE_WRITE_MASK | RXE_SEND_MASK), 888700e3e7SMoni Shoua }; 898700e3e7SMoni Shoua 908700e3e7SMoni Shoua #define OPCODE_NONE (-1) 918700e3e7SMoni Shoua #define RXE_NUM_OPCODE 256 928700e3e7SMoni Shoua 938700e3e7SMoni Shoua struct rxe_opcode_info { 948700e3e7SMoni Shoua char *name; 958700e3e7SMoni Shoua enum rxe_hdr_mask mask; 968700e3e7SMoni Shoua int length; 978700e3e7SMoni Shoua int offset[NUM_HDR_TYPES]; 988700e3e7SMoni Shoua }; 998700e3e7SMoni Shoua 1008700e3e7SMoni Shoua extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 1018700e3e7SMoni Shoua 1028700e3e7SMoni Shoua #endif /* RXE_OPCODE_H */ 103