163fa15dbSBob Pearson /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 28700e3e7SMoni Shoua /* 38700e3e7SMoni Shoua * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 48700e3e7SMoni Shoua * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 58700e3e7SMoni Shoua */ 68700e3e7SMoni Shoua 78700e3e7SMoni Shoua #ifndef RXE_OPCODE_H 88700e3e7SMoni Shoua #define RXE_OPCODE_H 98700e3e7SMoni Shoua 108700e3e7SMoni Shoua /* 118700e3e7SMoni Shoua * contains header bit mask definitions and header lengths 128700e3e7SMoni Shoua * declaration of the rxe_opcode_info struct and 138700e3e7SMoni Shoua * rxe_wr_opcode_info struct 148700e3e7SMoni Shoua */ 158700e3e7SMoni Shoua 168700e3e7SMoni Shoua enum rxe_wr_mask { 178700e3e7SMoni Shoua WR_INLINE_MASK = BIT(0), 188700e3e7SMoni Shoua WR_ATOMIC_MASK = BIT(1), 198700e3e7SMoni Shoua WR_SEND_MASK = BIT(2), 208700e3e7SMoni Shoua WR_READ_MASK = BIT(3), 218700e3e7SMoni Shoua WR_WRITE_MASK = BIT(4), 22886441fbSBob Pearson WR_LOCAL_OP_MASK = BIT(5), 2302e9a31cSLi Zhijian WR_FLUSH_MASK = BIT(6), 245c7af6c7SXiao Yang WR_ATOMIC_WRITE_MASK = BIT(7), 258700e3e7SMoni Shoua 268700e3e7SMoni Shoua WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 278700e3e7SMoni Shoua WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 288700e3e7SMoni Shoua WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 298700e3e7SMoni Shoua }; 308700e3e7SMoni Shoua 318700e3e7SMoni Shoua #define WR_MAX_QPT (8) 328700e3e7SMoni Shoua 338700e3e7SMoni Shoua struct rxe_wr_opcode_info { 348700e3e7SMoni Shoua char *name; 358700e3e7SMoni Shoua enum rxe_wr_mask mask[WR_MAX_QPT]; 368700e3e7SMoni Shoua }; 378700e3e7SMoni Shoua 388700e3e7SMoni Shoua extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 398700e3e7SMoni Shoua 408700e3e7SMoni Shoua enum rxe_hdr_type { 418700e3e7SMoni Shoua RXE_LRH, 428700e3e7SMoni Shoua RXE_GRH, 438700e3e7SMoni Shoua RXE_BTH, 448700e3e7SMoni Shoua RXE_RETH, 458700e3e7SMoni Shoua RXE_AETH, 468700e3e7SMoni Shoua RXE_ATMETH, 478700e3e7SMoni Shoua RXE_ATMACK, 488700e3e7SMoni Shoua RXE_IETH, 498700e3e7SMoni Shoua RXE_RDETH, 508700e3e7SMoni Shoua RXE_DETH, 518700e3e7SMoni Shoua RXE_IMMDT, 5202e9a31cSLi Zhijian RXE_FETH, 538700e3e7SMoni Shoua RXE_PAYLOAD, 548700e3e7SMoni Shoua NUM_HDR_TYPES 558700e3e7SMoni Shoua }; 568700e3e7SMoni Shoua 578700e3e7SMoni Shoua enum rxe_hdr_mask { 588700e3e7SMoni Shoua RXE_LRH_MASK = BIT(RXE_LRH), 598700e3e7SMoni Shoua RXE_GRH_MASK = BIT(RXE_GRH), 608700e3e7SMoni Shoua RXE_BTH_MASK = BIT(RXE_BTH), 618700e3e7SMoni Shoua RXE_IMMDT_MASK = BIT(RXE_IMMDT), 628700e3e7SMoni Shoua RXE_RETH_MASK = BIT(RXE_RETH), 638700e3e7SMoni Shoua RXE_AETH_MASK = BIT(RXE_AETH), 648700e3e7SMoni Shoua RXE_ATMETH_MASK = BIT(RXE_ATMETH), 658700e3e7SMoni Shoua RXE_ATMACK_MASK = BIT(RXE_ATMACK), 668700e3e7SMoni Shoua RXE_IETH_MASK = BIT(RXE_IETH), 678700e3e7SMoni Shoua RXE_RDETH_MASK = BIT(RXE_RDETH), 688700e3e7SMoni Shoua RXE_DETH_MASK = BIT(RXE_DETH), 6902e9a31cSLi Zhijian RXE_FETH_MASK = BIT(RXE_FETH), 708700e3e7SMoni Shoua RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 718700e3e7SMoni Shoua 728700e3e7SMoni Shoua RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 738700e3e7SMoni Shoua RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 748700e3e7SMoni Shoua RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 758700e3e7SMoni Shoua RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 768700e3e7SMoni Shoua RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 778700e3e7SMoni Shoua RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 7802e9a31cSLi Zhijian RXE_FLUSH_MASK = BIT(NUM_HDR_TYPES + 6), 798700e3e7SMoni Shoua 8002e9a31cSLi Zhijian RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 7), 8102e9a31cSLi Zhijian RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 8), 828700e3e7SMoni Shoua 8302e9a31cSLi Zhijian RXE_START_MASK = BIT(NUM_HDR_TYPES + 9), 8402e9a31cSLi Zhijian RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 10), 8502e9a31cSLi Zhijian RXE_END_MASK = BIT(NUM_HDR_TYPES + 11), 868700e3e7SMoni Shoua 878700e3e7SMoni Shoua RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 888700e3e7SMoni Shoua 895c7af6c7SXiao Yang RXE_ATOMIC_WRITE_MASK = BIT(NUM_HDR_TYPES + 14), 905c7af6c7SXiao Yang 9145216d63SXiao Yang RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK), 9245216d63SXiao Yang RXE_WRITE_OR_SEND_MASK = (RXE_WRITE_MASK | RXE_SEND_MASK), 93373efe0fSXiao Yang RXE_READ_OR_WRITE_MASK = (RXE_READ_MASK | RXE_WRITE_MASK), 94*2a129958SBob Pearson RXE_RDMA_OP_MASK = (RXE_READ_MASK | RXE_WRITE_MASK | 95*2a129958SBob Pearson RXE_ATOMIC_WRITE_MASK | RXE_FLUSH_MASK | 96*2a129958SBob Pearson RXE_ATOMIC_MASK), 978700e3e7SMoni Shoua }; 988700e3e7SMoni Shoua 998700e3e7SMoni Shoua #define OPCODE_NONE (-1) 1008700e3e7SMoni Shoua #define RXE_NUM_OPCODE 256 1018700e3e7SMoni Shoua 1028700e3e7SMoni Shoua struct rxe_opcode_info { 1038700e3e7SMoni Shoua char *name; 1048700e3e7SMoni Shoua enum rxe_hdr_mask mask; 1058700e3e7SMoni Shoua int length; 1068700e3e7SMoni Shoua int offset[NUM_HDR_TYPES]; 1078700e3e7SMoni Shoua }; 1088700e3e7SMoni Shoua 1098700e3e7SMoni Shoua extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 1108700e3e7SMoni Shoua 1118700e3e7SMoni Shoua #endif /* RXE_OPCODE_H */ 112