1*1648bcf1Szhenwei pi // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2*1648bcf1Szhenwei pi /* 3*1648bcf1Szhenwei pi * Copyright (c) 2026 zhenwei pi <zhenwei.pi@linux.dev> 4*1648bcf1Szhenwei pi */ 5*1648bcf1Szhenwei pi 6*1648bcf1Szhenwei pi #include <rdma/ib_pma.h> 7*1648bcf1Szhenwei pi #include "rxe.h" 8*1648bcf1Szhenwei pi #include "rxe_hw_counters.h" 9*1648bcf1Szhenwei pi 10*1648bcf1Szhenwei pi static int rxe_get_pma_info(struct ib_mad *out) 11*1648bcf1Szhenwei pi { 12*1648bcf1Szhenwei pi struct ib_class_port_info cpi = {}; 13*1648bcf1Szhenwei pi 14*1648bcf1Szhenwei pi cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 15*1648bcf1Szhenwei pi memcpy((out->data + 40), &cpi, sizeof(cpi)); 16*1648bcf1Szhenwei pi 17*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 18*1648bcf1Szhenwei pi } 19*1648bcf1Szhenwei pi 20*1648bcf1Szhenwei pi static int rxe_get_pma_counters(struct rxe_dev *rxe, struct ib_mad *out) 21*1648bcf1Szhenwei pi { 22*1648bcf1Szhenwei pi struct ib_pma_portcounters *pma_cnt = (struct ib_pma_portcounters *)(out->data + 40); 23*1648bcf1Szhenwei pi s64 val; 24*1648bcf1Szhenwei pi 25*1648bcf1Szhenwei pi /* IBA release 1.8, 16.1.3.5: During operation, instead of overflowing, they shall stop 26*1648bcf1Szhenwei pi * at all ones. 27*1648bcf1Szhenwei pi */ 28*1648bcf1Szhenwei pi val = atomic64_read(&rxe->stats_counters[RXE_CNT_LINK_DOWNED]); 29*1648bcf1Szhenwei pi pma_cnt->link_downed_counter = clamp(val, 0, U8_MAX); 30*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 31*1648bcf1Szhenwei pi } 32*1648bcf1Szhenwei pi 33*1648bcf1Szhenwei pi static int rxe_get_pma_counters_ext(struct rxe_dev *rxe, struct ib_mad *out) 34*1648bcf1Szhenwei pi { 35*1648bcf1Szhenwei pi struct ib_pma_portcounters_ext *pma_cnt_ext = 36*1648bcf1Szhenwei pi (struct ib_pma_portcounters_ext *)(out->data + 40); 37*1648bcf1Szhenwei pi s64 val; 38*1648bcf1Szhenwei pi 39*1648bcf1Szhenwei pi val = atomic64_read(&rxe->stats_counters[RXE_CNT_SENT_BYTES]); 40*1648bcf1Szhenwei pi pma_cnt_ext->port_xmit_data = cpu_to_be64(val >> 2); 41*1648bcf1Szhenwei pi 42*1648bcf1Szhenwei pi val = atomic64_read(&rxe->stats_counters[RXE_CNT_RCVD_BYTES]); 43*1648bcf1Szhenwei pi pma_cnt_ext->port_rcv_data = cpu_to_be64(val >> 2); 44*1648bcf1Szhenwei pi 45*1648bcf1Szhenwei pi val = atomic64_read(&rxe->stats_counters[RXE_CNT_SENT_PKTS]); 46*1648bcf1Szhenwei pi pma_cnt_ext->port_xmit_packets = cpu_to_be64(val); 47*1648bcf1Szhenwei pi 48*1648bcf1Szhenwei pi val = atomic64_read(&rxe->stats_counters[RXE_CNT_RCVD_PKTS]); 49*1648bcf1Szhenwei pi pma_cnt_ext->port_rcv_packets = cpu_to_be64(val); 50*1648bcf1Szhenwei pi 51*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 52*1648bcf1Szhenwei pi } 53*1648bcf1Szhenwei pi 54*1648bcf1Szhenwei pi static int rxe_get_perf_mgmt(struct rxe_dev *rxe, const struct ib_mad *in, struct ib_mad *out) 55*1648bcf1Szhenwei pi { 56*1648bcf1Szhenwei pi switch (in->mad_hdr.attr_id) { 57*1648bcf1Szhenwei pi case IB_PMA_CLASS_PORT_INFO: 58*1648bcf1Szhenwei pi return rxe_get_pma_info(out); 59*1648bcf1Szhenwei pi 60*1648bcf1Szhenwei pi case IB_PMA_PORT_COUNTERS: 61*1648bcf1Szhenwei pi return rxe_get_pma_counters(rxe, out); 62*1648bcf1Szhenwei pi 63*1648bcf1Szhenwei pi case IB_PMA_PORT_COUNTERS_EXT: 64*1648bcf1Szhenwei pi return rxe_get_pma_counters_ext(rxe, out); 65*1648bcf1Szhenwei pi 66*1648bcf1Szhenwei pi default: 67*1648bcf1Szhenwei pi out->mad_hdr.status = cpu_to_be16(IB_MGMT_MAD_STATUS_UNSUPPORTED_METHOD_ATTRIB); 68*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS; 69*1648bcf1Szhenwei pi } 70*1648bcf1Szhenwei pi } 71*1648bcf1Szhenwei pi 72*1648bcf1Szhenwei pi int rxe_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 73*1648bcf1Szhenwei pi const struct ib_wc *in_wc, const struct ib_grh *in_grh, 74*1648bcf1Szhenwei pi const struct ib_mad *in, struct ib_mad *out, 75*1648bcf1Szhenwei pi size_t *out_mad_size, u16 *out_mad_pkey_index) 76*1648bcf1Szhenwei pi { 77*1648bcf1Szhenwei pi struct rxe_dev *rxe = to_rdev(ibdev); 78*1648bcf1Szhenwei pi u8 mgmt_class = in->mad_hdr.mgmt_class; 79*1648bcf1Szhenwei pi u8 method = in->mad_hdr.method; 80*1648bcf1Szhenwei pi 81*1648bcf1Szhenwei pi if (port_num != 1) 82*1648bcf1Szhenwei pi return IB_MAD_RESULT_FAILURE; 83*1648bcf1Szhenwei pi 84*1648bcf1Szhenwei pi memset(out, 0, sizeof(*out)); 85*1648bcf1Szhenwei pi switch (mgmt_class) { 86*1648bcf1Szhenwei pi case IB_MGMT_CLASS_PERF_MGMT: 87*1648bcf1Szhenwei pi if (method == IB_MGMT_METHOD_GET) 88*1648bcf1Szhenwei pi return rxe_get_perf_mgmt(rxe, in, out); 89*1648bcf1Szhenwei pi break; 90*1648bcf1Szhenwei pi 91*1648bcf1Szhenwei pi default: 92*1648bcf1Szhenwei pi out->mad_hdr.status = cpu_to_be16(IB_MGMT_MAD_STATUS_UNSUPPORTED_METHOD); 93*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS; 94*1648bcf1Szhenwei pi } 95*1648bcf1Szhenwei pi 96*1648bcf1Szhenwei pi return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 97*1648bcf1Szhenwei pi } 98