xref: /linux/drivers/infiniband/hw/qib/qib_pcie.c (revision 4413e16d9d21673bb5048a2e542f1aaa00015c2e)
1 /*
2  * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/pci.h>
34 #include <linux/io.h>
35 #include <linux/delay.h>
36 #include <linux/vmalloc.h>
37 #include <linux/aer.h>
38 #include <linux/module.h>
39 
40 #include "qib.h"
41 
42 /*
43  * This file contains PCIe utility routines that are common to the
44  * various QLogic InfiniPath adapters
45  */
46 
47 /*
48  * Code to adjust PCIe capabilities.
49  * To minimize the change footprint, we call it
50  * from qib_pcie_params, which every chip-specific
51  * file calls, even though this violates some
52  * expectations of harmlessness.
53  */
54 static int qib_tune_pcie_caps(struct qib_devdata *);
55 static int qib_tune_pcie_coalesce(struct qib_devdata *);
56 
57 /*
58  * Do all the common PCIe setup and initialization.
59  * devdata is not yet allocated, and is not allocated until after this
60  * routine returns success.  Therefore qib_dev_err() can't be used for error
61  * printing.
62  */
63 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
64 {
65 	int ret;
66 
67 	ret = pci_enable_device(pdev);
68 	if (ret) {
69 		/*
70 		 * This can happen (in theory) iff:
71 		 * We did a chip reset, and then failed to reprogram the
72 		 * BAR, or the chip reset due to an internal error.  We then
73 		 * unloaded the driver and reloaded it.
74 		 *
75 		 * Both reset cases set the BAR back to initial state.  For
76 		 * the latter case, the AER sticky error bit at offset 0x718
77 		 * should be set, but the Linux kernel doesn't yet know
78 		 * about that, it appears.  If the original BAR was retained
79 		 * in the kernel data structures, this may be OK.
80 		 */
81 		qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
82 			      -ret);
83 		goto done;
84 	}
85 
86 	ret = pci_request_regions(pdev, QIB_DRV_NAME);
87 	if (ret) {
88 		qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
89 		goto bail;
90 	}
91 
92 	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
93 	if (ret) {
94 		/*
95 		 * If the 64 bit setup fails, try 32 bit.  Some systems
96 		 * do not setup 64 bit maps on systems with 2GB or less
97 		 * memory installed.
98 		 */
99 		ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
100 		if (ret) {
101 			qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
102 			goto bail;
103 		}
104 		ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
105 	} else
106 		ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
107 	if (ret) {
108 		qib_early_err(&pdev->dev,
109 			      "Unable to set DMA consistent mask: %d\n", ret);
110 		goto bail;
111 	}
112 
113 	pci_set_master(pdev);
114 	ret = pci_enable_pcie_error_reporting(pdev);
115 	if (ret) {
116 		qib_early_err(&pdev->dev,
117 			      "Unable to enable pcie error reporting: %d\n",
118 			      ret);
119 		ret = 0;
120 	}
121 	goto done;
122 
123 bail:
124 	pci_disable_device(pdev);
125 	pci_release_regions(pdev);
126 done:
127 	return ret;
128 }
129 
130 /*
131  * Do remaining PCIe setup, once dd is allocated, and save away
132  * fields required to re-initialize after a chip reset, or for
133  * various other purposes
134  */
135 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
136 		    const struct pci_device_id *ent)
137 {
138 	unsigned long len;
139 	resource_size_t addr;
140 
141 	dd->pcidev = pdev;
142 	pci_set_drvdata(pdev, dd);
143 
144 	addr = pci_resource_start(pdev, 0);
145 	len = pci_resource_len(pdev, 0);
146 
147 #if defined(__powerpc__)
148 	/* There isn't a generic way to specify writethrough mappings */
149 	dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU);
150 #else
151 	dd->kregbase = ioremap_nocache(addr, len);
152 #endif
153 
154 	if (!dd->kregbase)
155 		return -ENOMEM;
156 
157 	dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
158 	dd->physaddr = addr;        /* used for io_remap, etc. */
159 
160 	/*
161 	 * Save BARs to rewrite after device reset.  Save all 64 bits of
162 	 * BAR, just in case.
163 	 */
164 	dd->pcibar0 = addr;
165 	dd->pcibar1 = addr >> 32;
166 	dd->deviceid = ent->device; /* save for later use */
167 	dd->vendorid = ent->vendor;
168 
169 	return 0;
170 }
171 
172 /*
173  * Do PCIe cleanup, after chip-specific cleanup, etc.  Just prior
174  * to releasing the dd memory.
175  * void because none of the core pcie cleanup returns are void
176  */
177 void qib_pcie_ddcleanup(struct qib_devdata *dd)
178 {
179 	u64 __iomem *base = (void __iomem *) dd->kregbase;
180 
181 	dd->kregbase = NULL;
182 	iounmap(base);
183 	if (dd->piobase)
184 		iounmap(dd->piobase);
185 	if (dd->userbase)
186 		iounmap(dd->userbase);
187 	if (dd->piovl15base)
188 		iounmap(dd->piovl15base);
189 
190 	pci_disable_device(dd->pcidev);
191 	pci_release_regions(dd->pcidev);
192 
193 	pci_set_drvdata(dd->pcidev, NULL);
194 }
195 
196 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
197 			   struct qib_msix_entry *qib_msix_entry)
198 {
199 	int ret;
200 	u32 tabsize = 0;
201 	u16 msix_flags;
202 	struct msix_entry *msix_entry;
203 	int i;
204 
205 	/* We can't pass qib_msix_entry array to qib_msix_setup
206 	 * so use a dummy msix_entry array and copy the allocated
207 	 * irq back to the qib_msix_entry array. */
208 	msix_entry = kmalloc(*msixcnt * sizeof(*msix_entry), GFP_KERNEL);
209 	if (!msix_entry) {
210 		ret = -ENOMEM;
211 		goto do_intx;
212 	}
213 	for (i = 0; i < *msixcnt; i++)
214 		msix_entry[i] = qib_msix_entry[i].msix;
215 
216 	pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags);
217 	tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE);
218 	if (tabsize > *msixcnt)
219 		tabsize = *msixcnt;
220 	ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
221 	if (ret > 0) {
222 		tabsize = ret;
223 		ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
224 	}
225 do_intx:
226 	if (ret) {
227 		qib_dev_err(dd,
228 			"pci_enable_msix %d vectors failed: %d, falling back to INTx\n",
229 			tabsize, ret);
230 		tabsize = 0;
231 	}
232 	for (i = 0; i < tabsize; i++)
233 		qib_msix_entry[i].msix = msix_entry[i];
234 	kfree(msix_entry);
235 	*msixcnt = tabsize;
236 
237 	if (ret)
238 		qib_enable_intx(dd->pcidev);
239 
240 }
241 
242 /**
243  * We save the msi lo and hi values, so we can restore them after
244  * chip reset (the kernel PCI infrastructure doesn't yet handle that
245  * correctly.
246  */
247 static int qib_msi_setup(struct qib_devdata *dd, int pos)
248 {
249 	struct pci_dev *pdev = dd->pcidev;
250 	u16 control;
251 	int ret;
252 
253 	ret = pci_enable_msi(pdev);
254 	if (ret)
255 		qib_dev_err(dd,
256 			"pci_enable_msi failed: %d, interrupts may not work\n",
257 			ret);
258 	/* continue even if it fails, we may still be OK... */
259 
260 	pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
261 			      &dd->msi_lo);
262 	pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
263 			      &dd->msi_hi);
264 	pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
265 	/* now save the data (vector) info */
266 	pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT)
267 				    ? 12 : 8),
268 			     &dd->msi_data);
269 	return ret;
270 }
271 
272 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
273 		    struct qib_msix_entry *entry)
274 {
275 	u16 linkstat, speed;
276 	int pos = 0, ret = 1;
277 
278 	if (!pci_is_pcie(dd->pcidev)) {
279 		qib_dev_err(dd, "Can't find PCI Express capability!\n");
280 		/* set up something... */
281 		dd->lbus_width = 1;
282 		dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
283 		goto bail;
284 	}
285 
286 	pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX);
287 	if (nent && *nent && pos) {
288 		qib_msix_setup(dd, pos, nent, entry);
289 		ret = 0; /* did it, either MSIx or INTx */
290 	} else {
291 		pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
292 		if (pos)
293 			ret = qib_msi_setup(dd, pos);
294 		else
295 			qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
296 	}
297 	if (!pos)
298 		qib_enable_intx(dd->pcidev);
299 
300 	pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
301 	/*
302 	 * speed is bits 0-3, linkwidth is bits 4-8
303 	 * no defines for them in headers
304 	 */
305 	speed = linkstat & 0xf;
306 	linkstat >>= 4;
307 	linkstat &= 0x1f;
308 	dd->lbus_width = linkstat;
309 
310 	switch (speed) {
311 	case 1:
312 		dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
313 		break;
314 	case 2:
315 		dd->lbus_speed = 5000; /* Gen1, 5GHz */
316 		break;
317 	default: /* not defined, assume gen1 */
318 		dd->lbus_speed = 2500;
319 		break;
320 	}
321 
322 	/*
323 	 * Check against expected pcie width and complain if "wrong"
324 	 * on first initialization, not afterwards (i.e., reset).
325 	 */
326 	if (minw && linkstat < minw)
327 		qib_dev_err(dd,
328 			    "PCIe width %u (x%u HCA), performance reduced\n",
329 			    linkstat, minw);
330 
331 	qib_tune_pcie_caps(dd);
332 
333 	qib_tune_pcie_coalesce(dd);
334 
335 bail:
336 	/* fill in string, even on errors */
337 	snprintf(dd->lbus_info, sizeof(dd->lbus_info),
338 		 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
339 	return ret;
340 }
341 
342 /*
343  * Setup pcie interrupt stuff again after a reset.  I'd like to just call
344  * pci_enable_msi() again for msi, but when I do that,
345  * the MSI enable bit doesn't get set in the command word, and
346  * we switch to to a different interrupt vector, which is confusing,
347  * so I instead just do it all inline.  Perhaps somehow can tie this
348  * into the PCIe hotplug support at some point
349  */
350 int qib_reinit_intr(struct qib_devdata *dd)
351 {
352 	int pos;
353 	u16 control;
354 	int ret = 0;
355 
356 	/* If we aren't using MSI, don't restore it */
357 	if (!dd->msi_lo)
358 		goto bail;
359 
360 	pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
361 	if (!pos) {
362 		qib_dev_err(dd,
363 			"Can't find MSI capability, can't restore MSI settings\n");
364 		ret = 0;
365 		/* nothing special for MSIx, just MSI */
366 		goto bail;
367 	}
368 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
369 			       dd->msi_lo);
370 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
371 			       dd->msi_hi);
372 	pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
373 	if (!(control & PCI_MSI_FLAGS_ENABLE)) {
374 		control |= PCI_MSI_FLAGS_ENABLE;
375 		pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
376 				      control);
377 	}
378 	/* now rewrite the data (vector) info */
379 	pci_write_config_word(dd->pcidev, pos +
380 			      ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
381 			      dd->msi_data);
382 	ret = 1;
383 bail:
384 	if (!ret && (dd->flags & QIB_HAS_INTX)) {
385 		qib_enable_intx(dd->pcidev);
386 		ret = 1;
387 	}
388 
389 	/* and now set the pci master bit again */
390 	pci_set_master(dd->pcidev);
391 
392 	return ret;
393 }
394 
395 /*
396  * Disable msi interrupt if enabled, and clear msi_lo.
397  * This is used primarily for the fallback to INTx, but
398  * is also used in reinit after reset, and during cleanup.
399  */
400 void qib_nomsi(struct qib_devdata *dd)
401 {
402 	dd->msi_lo = 0;
403 	pci_disable_msi(dd->pcidev);
404 }
405 
406 /*
407  * Same as qib_nosmi, but for MSIx.
408  */
409 void qib_nomsix(struct qib_devdata *dd)
410 {
411 	pci_disable_msix(dd->pcidev);
412 }
413 
414 /*
415  * Similar to pci_intx(pdev, 1), except that we make sure
416  * msi(x) is off.
417  */
418 void qib_enable_intx(struct pci_dev *pdev)
419 {
420 	u16 cw, new;
421 	int pos;
422 
423 	/* first, turn on INTx */
424 	pci_read_config_word(pdev, PCI_COMMAND, &cw);
425 	new = cw & ~PCI_COMMAND_INTX_DISABLE;
426 	if (new != cw)
427 		pci_write_config_word(pdev, PCI_COMMAND, new);
428 
429 	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
430 	if (pos) {
431 		/* then turn off MSI */
432 		pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
433 		new = cw & ~PCI_MSI_FLAGS_ENABLE;
434 		if (new != cw)
435 			pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
436 	}
437 	pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
438 	if (pos) {
439 		/* then turn off MSIx */
440 		pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw);
441 		new = cw & ~PCI_MSIX_FLAGS_ENABLE;
442 		if (new != cw)
443 			pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new);
444 	}
445 }
446 
447 /*
448  * These two routines are helper routines for the device reset code
449  * to move all the pcie code out of the chip-specific driver code.
450  */
451 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
452 {
453 	pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
454 	pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
455 	pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
456 }
457 
458 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
459 {
460 	int r;
461 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
462 				   dd->pcibar0);
463 	if (r)
464 		qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
465 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
466 				   dd->pcibar1);
467 	if (r)
468 		qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
469 	/* now re-enable memory access, and restore cosmetic settings */
470 	pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
471 	pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
472 	pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
473 	r = pci_enable_device(dd->pcidev);
474 	if (r)
475 		qib_dev_err(dd,
476 			"pci_enable_device failed after reset: %d\n", r);
477 }
478 
479 /* code to adjust PCIe capabilities. */
480 
481 static int fld2val(int wd, int mask)
482 {
483 	int lsbmask;
484 
485 	if (!mask)
486 		return 0;
487 	wd &= mask;
488 	lsbmask = mask ^ (mask & (mask - 1));
489 	wd /= lsbmask;
490 	return wd;
491 }
492 
493 static int val2fld(int wd, int mask)
494 {
495 	int lsbmask;
496 
497 	if (!mask)
498 		return 0;
499 	lsbmask = mask ^ (mask & (mask - 1));
500 	wd *= lsbmask;
501 	return wd;
502 }
503 
504 static int qib_pcie_coalesce;
505 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
506 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
507 
508 /*
509  * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
510  * chipsets.   This is known to be unsafe for some revisions of some
511  * of these chipsets, with some BIOS settings, and enabling it on those
512  * systems may result in the system crashing, and/or data corruption.
513  */
514 static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
515 {
516 	int r;
517 	struct pci_dev *parent;
518 	u16 devid;
519 	u32 mask, bits, val;
520 
521 	if (!qib_pcie_coalesce)
522 		return 0;
523 
524 	/* Find out supported and configured values for parent (root) */
525 	parent = dd->pcidev->bus->self;
526 	if (parent->bus->parent) {
527 		qib_devinfo(dd->pcidev, "Parent not root\n");
528 		return 1;
529 	}
530 	if (!pci_is_pcie(parent))
531 		return 1;
532 	if (parent->vendor != 0x8086)
533 		return 1;
534 
535 	/*
536 	 *  - bit 12: Max_rdcmp_Imt_EN: need to set to 1
537 	 *  - bit 11: COALESCE_FORCE: need to set to 0
538 	 *  - bit 10: COALESCE_EN: need to set to 1
539 	 *  (but limitations on some on some chipsets)
540 	 *
541 	 *  On the Intel 5000, 5100, and 7300 chipsets, there is
542 	 *  also: - bit 25:24: COALESCE_MODE, need to set to 0
543 	 */
544 	devid = parent->device;
545 	if (devid >= 0x25e2 && devid <= 0x25fa) {
546 		/* 5000 P/V/X/Z */
547 		if (parent->revision <= 0xb2)
548 			bits = 1U << 10;
549 		else
550 			bits = 7U << 10;
551 		mask = (3U << 24) | (7U << 10);
552 	} else if (devid >= 0x65e2 && devid <= 0x65fa) {
553 		/* 5100 */
554 		bits = 1U << 10;
555 		mask = (3U << 24) | (7U << 10);
556 	} else if (devid >= 0x4021 && devid <= 0x402e) {
557 		/* 5400 */
558 		bits = 7U << 10;
559 		mask = 7U << 10;
560 	} else if (devid >= 0x3604 && devid <= 0x360a) {
561 		/* 7300 */
562 		bits = 7U << 10;
563 		mask = (3U << 24) | (7U << 10);
564 	} else {
565 		/* not one of the chipsets that we know about */
566 		return 1;
567 	}
568 	pci_read_config_dword(parent, 0x48, &val);
569 	val &= ~mask;
570 	val |= bits;
571 	r = pci_write_config_dword(parent, 0x48, val);
572 	return 0;
573 }
574 
575 /*
576  * BIOS may not set PCIe bus-utilization parameters for best performance.
577  * Check and optionally adjust them to maximize our throughput.
578  */
579 static int qib_pcie_caps;
580 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
581 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
582 
583 static int qib_tune_pcie_caps(struct qib_devdata *dd)
584 {
585 	int ret = 1; /* Assume the worst */
586 	struct pci_dev *parent;
587 	u16 pcaps, pctl, ecaps, ectl;
588 	int rc_sup, ep_sup;
589 	int rc_cur, ep_cur;
590 
591 	/* Find out supported and configured values for parent (root) */
592 	parent = dd->pcidev->bus->self;
593 	if (parent->bus->parent) {
594 		qib_devinfo(dd->pcidev, "Parent not root\n");
595 		goto bail;
596 	}
597 
598 	if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
599 		goto bail;
600 	pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
601 	pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
602 	/* Find out supported and configured values for endpoint (us) */
603 	pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
604 	pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
605 
606 	ret = 0;
607 	/* Find max payload supported by root, endpoint */
608 	rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
609 	ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD);
610 	if (rc_sup > ep_sup)
611 		rc_sup = ep_sup;
612 
613 	rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD);
614 	ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD);
615 
616 	/* If Supported greater than limit in module param, limit it */
617 	if (rc_sup > (qib_pcie_caps & 7))
618 		rc_sup = qib_pcie_caps & 7;
619 	/* If less than (allowed, supported), bump root payload */
620 	if (rc_sup > rc_cur) {
621 		rc_cur = rc_sup;
622 		pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
623 			val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
624 		pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
625 	}
626 	/* If less than (allowed, supported), bump endpoint payload */
627 	if (rc_sup > ep_cur) {
628 		ep_cur = rc_sup;
629 		ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
630 			val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
631 		pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
632 	}
633 
634 	/*
635 	 * Now the Read Request size.
636 	 * No field for max supported, but PCIe spec limits it to 4096,
637 	 * which is code '5' (log2(4096) - 7)
638 	 */
639 	rc_sup = 5;
640 	if (rc_sup > ((qib_pcie_caps >> 4) & 7))
641 		rc_sup = (qib_pcie_caps >> 4) & 7;
642 	rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ);
643 	ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ);
644 
645 	if (rc_sup > rc_cur) {
646 		rc_cur = rc_sup;
647 		pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
648 			val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
649 		pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
650 	}
651 	if (rc_sup > ep_cur) {
652 		ep_cur = rc_sup;
653 		ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
654 			val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
655 		pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
656 	}
657 bail:
658 	return ret;
659 }
660 /* End of PCIe capability tuning */
661 
662 /*
663  * From here through qib_pci_err_handler definition is invoked via
664  * PCI error infrastructure, registered via pci
665  */
666 static pci_ers_result_t
667 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
668 {
669 	struct qib_devdata *dd = pci_get_drvdata(pdev);
670 	pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
671 
672 	switch (state) {
673 	case pci_channel_io_normal:
674 		qib_devinfo(pdev, "State Normal, ignoring\n");
675 		break;
676 
677 	case pci_channel_io_frozen:
678 		qib_devinfo(pdev, "State Frozen, requesting reset\n");
679 		pci_disable_device(pdev);
680 		ret = PCI_ERS_RESULT_NEED_RESET;
681 		break;
682 
683 	case pci_channel_io_perm_failure:
684 		qib_devinfo(pdev, "State Permanent Failure, disabling\n");
685 		if (dd) {
686 			/* no more register accesses! */
687 			dd->flags &= ~QIB_PRESENT;
688 			qib_disable_after_error(dd);
689 		}
690 		 /* else early, or other problem */
691 		ret =  PCI_ERS_RESULT_DISCONNECT;
692 		break;
693 
694 	default: /* shouldn't happen */
695 		qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
696 			state);
697 		break;
698 	}
699 	return ret;
700 }
701 
702 static pci_ers_result_t
703 qib_pci_mmio_enabled(struct pci_dev *pdev)
704 {
705 	u64 words = 0U;
706 	struct qib_devdata *dd = pci_get_drvdata(pdev);
707 	pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
708 
709 	if (dd && dd->pport) {
710 		words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
711 		if (words == ~0ULL)
712 			ret = PCI_ERS_RESULT_NEED_RESET;
713 	}
714 	qib_devinfo(pdev,
715 		"QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
716 		words, ret);
717 	return  ret;
718 }
719 
720 static pci_ers_result_t
721 qib_pci_slot_reset(struct pci_dev *pdev)
722 {
723 	qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
724 	return PCI_ERS_RESULT_CAN_RECOVER;
725 }
726 
727 static pci_ers_result_t
728 qib_pci_link_reset(struct pci_dev *pdev)
729 {
730 	qib_devinfo(pdev, "QIB link_reset function called, ignored\n");
731 	return PCI_ERS_RESULT_CAN_RECOVER;
732 }
733 
734 static void
735 qib_pci_resume(struct pci_dev *pdev)
736 {
737 	struct qib_devdata *dd = pci_get_drvdata(pdev);
738 	qib_devinfo(pdev, "QIB resume function called\n");
739 	pci_cleanup_aer_uncorrect_error_status(pdev);
740 	/*
741 	 * Running jobs will fail, since it's asynchronous
742 	 * unlike sysfs-requested reset.   Better than
743 	 * doing nothing.
744 	 */
745 	qib_init(dd, 1); /* same as re-init after reset */
746 }
747 
748 const struct pci_error_handlers qib_pci_err_handler = {
749 	.error_detected = qib_pci_error_detected,
750 	.mmio_enabled = qib_pci_mmio_enabled,
751 	.link_reset = qib_pci_link_reset,
752 	.slot_reset = qib_pci_slot_reset,
753 	.resume = qib_pci_resume,
754 };
755