1 /* 2 * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved. 3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * This file contains all of the code that is specific to the 36 * InfiniPath 7322 chip 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/pci.h> 41 #include <linux/delay.h> 42 #include <linux/io.h> 43 #include <linux/jiffies.h> 44 #include <linux/module.h> 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_smi.h> 47 #ifdef CONFIG_INFINIBAND_QIB_DCA 48 #include <linux/dca.h> 49 #endif 50 51 #include "qib.h" 52 #include "qib_7322_regs.h" 53 #include "qib_qsfp.h" 54 55 #include "qib_mad.h" 56 #include "qib_verbs.h" 57 58 #undef pr_fmt 59 #define pr_fmt(fmt) QIB_DRV_NAME " " fmt 60 61 static void qib_setup_7322_setextled(struct qib_pportdata *, u32); 62 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t); 63 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op); 64 static irqreturn_t qib_7322intr(int irq, void *data); 65 static irqreturn_t qib_7322bufavail(int irq, void *data); 66 static irqreturn_t sdma_intr(int irq, void *data); 67 static irqreturn_t sdma_idle_intr(int irq, void *data); 68 static irqreturn_t sdma_progress_intr(int irq, void *data); 69 static irqreturn_t sdma_cleanup_intr(int irq, void *data); 70 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32, 71 struct qib_ctxtdata *rcd); 72 static u8 qib_7322_phys_portstate(u64); 73 static u32 qib_7322_iblink_state(u64); 74 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 75 u16 linitcmd); 76 static void force_h1(struct qib_pportdata *); 77 static void adj_tx_serdes(struct qib_pportdata *); 78 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8); 79 static void qib_7322_mini_pcs_reset(struct qib_pportdata *); 80 81 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); 82 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); 83 static void serdes_7322_los_enable(struct qib_pportdata *, int); 84 static int serdes_7322_init_old(struct qib_pportdata *); 85 static int serdes_7322_init_new(struct qib_pportdata *); 86 static void dump_sdma_7322_state(struct qib_pportdata *); 87 88 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) 89 90 /* LE2 serdes values for different cases */ 91 #define LE2_DEFAULT 5 92 #define LE2_5m 4 93 #define LE2_QME 0 94 95 /* Below is special-purpose, so only really works for the IB SerDes blocks. */ 96 #define IBSD(hw_pidx) (hw_pidx + 2) 97 98 /* these are variables for documentation and experimentation purposes */ 99 static const unsigned rcv_int_timeout = 375; 100 static const unsigned rcv_int_count = 16; 101 static const unsigned sdma_idle_cnt = 64; 102 103 /* Time to stop altering Rx Equalization parameters, after link up. */ 104 #define RXEQ_DISABLE_MSECS 2500 105 106 /* 107 * Number of VLs we are configured to use (to allow for more 108 * credits per vl, etc.) 109 */ 110 ushort qib_num_cfg_vls = 2; 111 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO); 112 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 113 114 static ushort qib_chase = 1; 115 module_param_named(chase, qib_chase, ushort, S_IRUGO); 116 MODULE_PARM_DESC(chase, "Enable state chase handling"); 117 118 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */ 119 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO); 120 MODULE_PARM_DESC(long_attenuation, 121 "attenuation cutoff (dB) for long copper cable setup"); 122 123 static ushort qib_singleport; 124 module_param_named(singleport, qib_singleport, ushort, S_IRUGO); 125 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); 126 127 static ushort qib_krcvq01_no_msi; 128 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO); 129 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2"); 130 131 /* 132 * Receive header queue sizes 133 */ 134 static unsigned qib_rcvhdrcnt; 135 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); 136 MODULE_PARM_DESC(rcvhdrcnt, "receive header count"); 137 138 static unsigned qib_rcvhdrsize; 139 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); 140 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words"); 141 142 static unsigned qib_rcvhdrentsize; 143 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); 144 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words"); 145 146 #define MAX_ATTEN_LEN 64 /* plenty for any real system */ 147 /* for read back, default index is ~5m copper cable */ 148 static char txselect_list[MAX_ATTEN_LEN] = "10"; 149 static struct kparam_string kp_txselect = { 150 .string = txselect_list, 151 .maxlen = MAX_ATTEN_LEN 152 }; 153 static int setup_txselect(const char *, const struct kernel_param *); 154 module_param_call(txselect, setup_txselect, param_get_string, 155 &kp_txselect, S_IWUSR | S_IRUGO); 156 MODULE_PARM_DESC(txselect, 157 "Tx serdes indices (for no QSFP or invalid QSFP data)"); 158 159 #define BOARD_QME7342 5 160 #define BOARD_QMH7342 6 161 #define BOARD_QMH7360 9 162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 163 BOARD_QMH7342) 164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 165 BOARD_QME7342) 166 167 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64)) 168 169 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64))) 170 171 #define MASK_ACROSS(lsb, msb) \ 172 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb)) 173 174 #define SYM_RMASK(regname, fldname) ((u64) \ 175 QIB_7322_##regname##_##fldname##_RMASK) 176 177 #define SYM_MASK(regname, fldname) ((u64) \ 178 QIB_7322_##regname##_##fldname##_RMASK << \ 179 QIB_7322_##regname##_##fldname##_LSB) 180 181 #define SYM_FIELD(value, regname, fldname) ((u64) \ 182 (((value) >> SYM_LSB(regname, fldname)) & \ 183 SYM_RMASK(regname, fldname))) 184 185 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */ 186 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \ 187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits)) 188 189 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask) 190 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask) 191 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask) 192 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) 193 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port) 194 /* Below because most, but not all, fields of IntMask have that full suffix */ 195 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port) 196 197 198 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) 199 200 /* 201 * the size bits give us 2^N, in KB units. 0 marks as invalid, 202 * and 7 is reserved. We currently use only 2KB and 4KB 203 */ 204 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB 205 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */ 206 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */ 207 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */ 208 209 #define SendIBSLIDAssignMask \ 210 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 211 #define SendIBSLMCMask \ 212 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 213 214 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn) 215 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn) 216 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn) 217 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn) 218 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN) 219 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN) 220 221 #define _QIB_GPIO_SDA_NUM 1 222 #define _QIB_GPIO_SCL_NUM 0 223 #define QIB_EEPROM_WEN_NUM 14 224 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */ 225 226 /* HW counter clock is at 4nsec */ 227 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000 228 229 /* full speed IB port 1 only */ 230 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR) 231 #define PORT_SPD_CAP_SHIFT 3 232 233 /* full speed featuremask, both ports */ 234 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT)) 235 236 /* 237 * This file contains almost all the chip-specific register information and 238 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip. 239 */ 240 241 /* Use defines to tie machine-generated names to lower-case names */ 242 #define kr_contextcnt KREG_IDX(ContextCnt) 243 #define kr_control KREG_IDX(Control) 244 #define kr_counterregbase KREG_IDX(CntrRegBase) 245 #define kr_errclear KREG_IDX(ErrClear) 246 #define kr_errmask KREG_IDX(ErrMask) 247 #define kr_errstatus KREG_IDX(ErrStatus) 248 #define kr_extctrl KREG_IDX(EXTCtrl) 249 #define kr_extstatus KREG_IDX(EXTStatus) 250 #define kr_gpio_clear KREG_IDX(GPIOClear) 251 #define kr_gpio_mask KREG_IDX(GPIOMask) 252 #define kr_gpio_out KREG_IDX(GPIOOut) 253 #define kr_gpio_status KREG_IDX(GPIOStatus) 254 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl) 255 #define kr_debugportval KREG_IDX(DebugPortValueReg) 256 #define kr_fmask KREG_IDX(feature_mask) 257 #define kr_act_fmask KREG_IDX(active_feature_mask) 258 #define kr_hwerrclear KREG_IDX(HwErrClear) 259 #define kr_hwerrmask KREG_IDX(HwErrMask) 260 #define kr_hwerrstatus KREG_IDX(HwErrStatus) 261 #define kr_intclear KREG_IDX(IntClear) 262 #define kr_intmask KREG_IDX(IntMask) 263 #define kr_intredirect KREG_IDX(IntRedirect0) 264 #define kr_intstatus KREG_IDX(IntStatus) 265 #define kr_pagealign KREG_IDX(PageAlign) 266 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0) 267 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */ 268 #define kr_rcvegrbase KREG_IDX(RcvEgrBase) 269 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt) 270 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt) 271 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize) 272 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize) 273 #define kr_rcvtidbase KREG_IDX(RcvTIDBase) 274 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt) 275 #define kr_revision KREG_IDX(Revision) 276 #define kr_scratch KREG_IDX(Scratch) 277 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */ 278 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */ 279 #define kr_sendctrl KREG_IDX(SendCtrl) 280 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */ 281 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */ 282 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr) 283 #define kr_sendpiobufbase KREG_IDX(SendBufBase) 284 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt) 285 #define kr_sendpiosize KREG_IDX(SendBufSize) 286 #define kr_sendregbase KREG_IDX(SendRegBase) 287 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0) 288 #define kr_userregbase KREG_IDX(UserRegBase) 289 #define kr_intgranted KREG_IDX(Int_Granted) 290 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int) 291 #define kr_intblocked KREG_IDX(IntBlocked) 292 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG) 293 294 /* 295 * per-port kernel registers. Access only with qib_read_kreg_port() 296 * or qib_write_kreg_port() 297 */ 298 #define krp_errclear KREG_IBPORT_IDX(ErrClear) 299 #define krp_errmask KREG_IBPORT_IDX(ErrMask) 300 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus) 301 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0) 302 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit) 303 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID) 304 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig) 305 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA) 306 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB) 307 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC) 308 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA) 309 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB) 310 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus) 311 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0) 312 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl) 313 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey) 314 #define krp_psinterval KREG_IBPORT_IDX(PSInterval) 315 #define krp_psstart KREG_IBPORT_IDX(PSStart) 316 #define krp_psstat KREG_IBPORT_IDX(PSStat) 317 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP) 318 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl) 319 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt) 320 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA) 321 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0) 322 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15) 323 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl) 324 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl) 325 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase) 326 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0) 327 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1) 328 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2) 329 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0) 330 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1) 331 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2) 332 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt) 333 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead) 334 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr) 335 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt) 336 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen) 337 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld) 338 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt) 339 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus) 340 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail) 341 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom) 342 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign) 343 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask) 344 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX) 345 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD) 346 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE) 347 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl) 348 349 /* 350 * Per-context kernel registers. Access only with qib_read_kreg_ctxt() 351 * or qib_write_kreg_ctxt() 352 */ 353 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0) 354 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0) 355 356 /* 357 * TID Flow table, per context. Reduces 358 * number of hdrq updates to one per flow (or on errors). 359 * context 0 and 1 share same memory, but have distinct 360 * addresses. Since for now, we never use expected sends 361 * on kernel contexts, we don't worry about that (we initialize 362 * those entries for ctxt 0/1 on driver load twice, for example). 363 */ 364 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */ 365 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0)) 366 367 /* these are the error bits in the tid flows, and are W1C */ 368 #define TIDFLOW_ERRBITS ( \ 369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \ 370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \ 371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \ 372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch))) 373 374 /* Most (not all) Counters are per-IBport. 375 * Requires LBIntCnt is at offset 0 in the group 376 */ 377 #define CREG_IDX(regname) \ 378 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 379 380 #define crp_badformat CREG_IDX(RxVersionErrCnt) 381 #define crp_err_rlen CREG_IDX(RxLenErrCnt) 382 #define crp_erricrc CREG_IDX(RxICRCErrCnt) 383 #define crp_errlink CREG_IDX(RxLinkMalformCnt) 384 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt) 385 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt) 386 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt) 387 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt) 388 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt) 389 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt) 390 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt) 391 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt) 392 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt) 393 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt) 394 #define crp_pktrcv CREG_IDX(RxDataPktCnt) 395 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt) 396 #define crp_pktsend CREG_IDX(TxDataPktCnt) 397 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt) 398 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount) 399 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount) 400 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount) 401 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount) 402 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount) 403 #define crp_rcvebp CREG_IDX(RxEBPCnt) 404 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt) 405 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt) 406 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt) 407 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt) 408 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt) 409 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt) 410 #define crp_rxvlerr CREG_IDX(RxVlErrCnt) 411 #define crp_sendstall CREG_IDX(TxFlowStallCnt) 412 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt) 413 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt) 414 #define crp_txlenerr CREG_IDX(TxLenErrCnt) 415 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt) 416 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt) 417 #define crp_txunderrun CREG_IDX(TxUnderrunCnt) 418 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt) 419 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt) 420 #define crp_wordrcv CREG_IDX(RxDwordCnt) 421 #define crp_wordsend CREG_IDX(TxDwordCnt) 422 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut) 423 424 /* these are the (few) counters that are not port-specific */ 425 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \ 426 QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 427 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt) 428 #define cr_lbint CREG_DEVIDX(LBIntCnt) 429 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt) 430 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt) 431 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt) 432 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt) 433 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt) 434 435 /* no chip register for # of IB ports supported, so define */ 436 #define NUM_IB_PORTS 2 437 438 /* 1 VL15 buffer per hardware IB port, no register for this, so define */ 439 #define NUM_VL15_BUFS NUM_IB_PORTS 440 441 /* 442 * context 0 and 1 are special, and there is no chip register that 443 * defines this value, so we have to define it here. 444 * These are all allocated to either 0 or 1 for single port 445 * hardware configuration, otherwise each gets half 446 */ 447 #define KCTXT0_EGRCNT 2048 448 449 /* values for vl and port fields in PBC, 7322-specific */ 450 #define PBC_PORT_SEL_LSB 26 451 #define PBC_PORT_SEL_RMASK 1 452 #define PBC_VL_NUM_LSB 27 453 #define PBC_VL_NUM_RMASK 7 454 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */ 455 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */ 456 457 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = { 458 [IB_RATE_2_5_GBPS] = 16, 459 [IB_RATE_5_GBPS] = 8, 460 [IB_RATE_10_GBPS] = 4, 461 [IB_RATE_20_GBPS] = 2, 462 [IB_RATE_30_GBPS] = 2, 463 [IB_RATE_40_GBPS] = 1 464 }; 465 466 static const char * const qib_sdma_state_names[] = { 467 [qib_sdma_state_s00_hw_down] = "s00_HwDown", 468 [qib_sdma_state_s10_hw_start_up_wait] = "s10_HwStartUpWait", 469 [qib_sdma_state_s20_idle] = "s20_Idle", 470 [qib_sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait", 471 [qib_sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait", 472 [qib_sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait", 473 [qib_sdma_state_s99_running] = "s99_Running", 474 }; 475 476 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive) 477 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive) 478 479 /* link training states, from IBC */ 480 #define IB_7322_LT_STATE_DISABLED 0x00 481 #define IB_7322_LT_STATE_LINKUP 0x01 482 #define IB_7322_LT_STATE_POLLACTIVE 0x02 483 #define IB_7322_LT_STATE_POLLQUIET 0x03 484 #define IB_7322_LT_STATE_SLEEPDELAY 0x04 485 #define IB_7322_LT_STATE_SLEEPQUIET 0x05 486 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08 487 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09 488 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a 489 #define IB_7322_LT_STATE_CFGIDLE 0x0b 490 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c 491 #define IB_7322_LT_STATE_TXREVLANES 0x0d 492 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e 493 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f 494 #define IB_7322_LT_STATE_CFGENH 0x10 495 #define IB_7322_LT_STATE_CFGTEST 0x11 496 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12 497 #define IB_7322_LT_STATE_CFGWAITENH 0x13 498 499 /* link state machine states from IBC */ 500 #define IB_7322_L_STATE_DOWN 0x0 501 #define IB_7322_L_STATE_INIT 0x1 502 #define IB_7322_L_STATE_ARM 0x2 503 #define IB_7322_L_STATE_ACTIVE 0x3 504 #define IB_7322_L_STATE_ACT_DEFER 0x4 505 506 static const u8 qib_7322_physportstate[0x20] = { 507 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED, 508 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP, 509 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL, 510 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL, 511 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP, 512 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP, 513 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN, 514 [IB_7322_LT_STATE_CFGRCVFCFG] = 515 IB_PHYSPORTSTATE_CFG_TRAIN, 516 [IB_7322_LT_STATE_CFGWAITRMT] = 517 IB_PHYSPORTSTATE_CFG_TRAIN, 518 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE, 519 [IB_7322_LT_STATE_RECOVERRETRAIN] = 520 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 521 [IB_7322_LT_STATE_RECOVERWAITRMT] = 522 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 523 [IB_7322_LT_STATE_RECOVERIDLE] = 524 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 525 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH, 526 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN, 527 [IB_7322_LT_STATE_CFGWAITRMTTEST] = 528 IB_PHYSPORTSTATE_CFG_TRAIN, 529 [IB_7322_LT_STATE_CFGWAITENH] = 530 IB_PHYSPORTSTATE_CFG_WAIT_ENH, 531 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN, 532 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN, 533 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN, 534 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN 535 }; 536 537 #ifdef CONFIG_INFINIBAND_QIB_DCA 538 struct qib_irq_notify { 539 int rcv; 540 void *arg; 541 struct irq_affinity_notify notify; 542 }; 543 #endif 544 545 struct qib_chip_specific { 546 u64 __iomem *cregbase; 547 u64 *cntrs; 548 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */ 549 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */ 550 u64 main_int_mask; /* clear bits which have dedicated handlers */ 551 u64 int_enable_mask; /* for per port interrupts in single port mode */ 552 u64 errormask; 553 u64 hwerrmask; 554 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */ 555 u64 gpio_mask; /* shadow the gpio mask register */ 556 u64 extctrl; /* shadow the gpio output enable, etc... */ 557 u32 ncntrs; 558 u32 nportcntrs; 559 u32 cntrnamelen; 560 u32 portcntrnamelen; 561 u32 numctxts; 562 u32 rcvegrcnt; 563 u32 updthresh; /* current AvailUpdThld */ 564 u32 updthresh_dflt; /* default AvailUpdThld */ 565 u32 r1; 566 u32 num_msix_entries; 567 u32 sdmabufcnt; 568 u32 lastbuf_for_pio; 569 u32 stay_in_freeze; 570 u32 recovery_ports_initted; 571 #ifdef CONFIG_INFINIBAND_QIB_DCA 572 u32 dca_ctrl; 573 int rhdr_cpu[18]; 574 int sdma_cpu[2]; 575 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */ 576 #endif 577 struct qib_msix_entry *msix_entries; 578 unsigned long *sendchkenable; 579 unsigned long *sendgrhchk; 580 unsigned long *sendibchk; 581 u32 rcvavail_timeout[18]; 582 char emsgbuf[128]; /* for device error interrupt msg buffer */ 583 }; 584 585 /* Table of entries in "human readable" form Tx Emphasis. */ 586 struct txdds_ent { 587 u8 amp; 588 u8 pre; 589 u8 main; 590 u8 post; 591 }; 592 593 struct vendor_txdds_ent { 594 u8 oui[QSFP_VOUI_LEN]; 595 u8 *partnum; 596 struct txdds_ent sdr; 597 struct txdds_ent ddr; 598 struct txdds_ent qdr; 599 }; 600 601 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); 602 603 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 604 #define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */ 605 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */ 606 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 607 608 #define H1_FORCE_VAL 8 609 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */ 610 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */ 611 612 /* The static and dynamic registers are paired, and the pairs indexed by spd */ 613 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \ 614 + ((spd) * 2)) 615 616 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */ 617 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */ 618 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */ 619 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */ 620 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */ 621 622 struct qib_chippport_specific { 623 u64 __iomem *kpregbase; 624 u64 __iomem *cpregbase; 625 u64 *portcntrs; 626 struct qib_pportdata *ppd; 627 wait_queue_head_t autoneg_wait; 628 struct delayed_work autoneg_work; 629 struct delayed_work ipg_work; 630 struct timer_list chase_timer; 631 /* 632 * these 5 fields are used to establish deltas for IB symbol 633 * errors and linkrecovery errors. They can be reported on 634 * some chips during link negotiation prior to INIT, and with 635 * DDR when faking DDR negotiations with non-IBTA switches. 636 * The chip counters are adjusted at driver unload if there is 637 * a non-zero delta. 638 */ 639 u64 ibdeltainprog; 640 u64 ibsymdelta; 641 u64 ibsymsnap; 642 u64 iblnkerrdelta; 643 u64 iblnkerrsnap; 644 u64 iblnkdownsnap; 645 u64 iblnkdowndelta; 646 u64 ibmalfdelta; 647 u64 ibmalfsnap; 648 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */ 649 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */ 650 unsigned long qdr_dfe_time; 651 unsigned long chase_end; 652 u32 autoneg_tries; 653 u32 recovery_init; 654 u32 qdr_dfe_on; 655 u32 qdr_reforce; 656 /* 657 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR. 658 * entry zero is unused, to simplify indexing 659 */ 660 u8 h1_val; 661 u8 no_eep; /* txselect table index to use if no qsfp info */ 662 u8 ipg_tries; 663 u8 ibmalfusesnap; 664 struct qib_qsfp_data qsfp_data; 665 char epmsgbuf[192]; /* for port error interrupt msg buffer */ 666 char sdmamsgbuf[192]; /* for per-port sdma error messages */ 667 }; 668 669 static struct { 670 const char *name; 671 irq_handler_t handler; 672 int lsb; 673 int port; /* 0 if not port-specific, else port # */ 674 int dca; 675 } irq_table[] = { 676 { "", qib_7322intr, -1, 0, 0 }, 677 { " (buf avail)", qib_7322bufavail, 678 SYM_LSB(IntStatus, SendBufAvail), 0, 0}, 679 { " (sdma 0)", sdma_intr, 680 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 }, 681 { " (sdma 1)", sdma_intr, 682 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 }, 683 { " (sdmaI 0)", sdma_idle_intr, 684 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1}, 685 { " (sdmaI 1)", sdma_idle_intr, 686 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1}, 687 { " (sdmaP 0)", sdma_progress_intr, 688 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 }, 689 { " (sdmaP 1)", sdma_progress_intr, 690 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 }, 691 { " (sdmaC 0)", sdma_cleanup_intr, 692 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 }, 693 { " (sdmaC 1)", sdma_cleanup_intr, 694 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0}, 695 }; 696 697 #ifdef CONFIG_INFINIBAND_QIB_DCA 698 699 static const struct dca_reg_map { 700 int shadow_inx; 701 int lsb; 702 u64 mask; 703 u16 regno; 704 } dca_rcvhdr_reg_map[] = { 705 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH), 706 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) }, 707 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH), 708 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) }, 709 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH), 710 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) }, 711 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH), 712 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) }, 713 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH), 714 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) }, 715 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH), 716 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) }, 717 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH), 718 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) }, 719 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH), 720 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) }, 721 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH), 722 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) }, 723 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH), 724 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) }, 725 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH), 726 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) }, 727 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH), 728 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) }, 729 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH), 730 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) }, 731 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH), 732 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) }, 733 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH), 734 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) }, 735 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH), 736 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) }, 737 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH), 738 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) }, 739 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH), 740 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) }, 741 }; 742 #endif 743 744 /* ibcctrl bits */ 745 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 746 /* cycle through TS1/TS2 till OK */ 747 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2 748 /* wait for TS1, then go on */ 749 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3 750 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16 751 752 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */ 753 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ 754 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ 755 756 #define BLOB_7322_IBCHG 0x101 757 758 static inline void qib_write_kreg(const struct qib_devdata *dd, 759 const u32 regno, u64 value); 760 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32); 761 static void write_7322_initregs(struct qib_devdata *); 762 static void write_7322_init_portregs(struct qib_pportdata *); 763 static void setup_7322_link_recovery(struct qib_pportdata *, u32); 764 static void check_7322_rxe_status(struct qib_pportdata *); 765 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); 766 #ifdef CONFIG_INFINIBAND_QIB_DCA 767 static void qib_setup_dca(struct qib_devdata *dd); 768 static void setup_dca_notifier(struct qib_devdata *dd, int msixnum); 769 static void reset_dca_notifier(struct qib_devdata *dd, int msixnum); 770 #endif 771 772 /** 773 * qib_read_ureg32 - read 32-bit virtualized per-context register 774 * @dd: device 775 * @regno: register number 776 * @ctxt: context number 777 * 778 * Return the contents of a register that is virtualized to be per context. 779 * Returns -1 on errors (not distinguishable from valid contents at 780 * runtime; we may add a separate error variable at some point). 781 */ 782 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, 783 enum qib_ureg regno, int ctxt) 784 { 785 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 786 return 0; 787 return readl(regno + (u64 __iomem *)( 788 (dd->ureg_align * ctxt) + (dd->userbase ? 789 (char __iomem *)dd->userbase : 790 (char __iomem *)dd->kregbase + dd->uregbase))); 791 } 792 793 /** 794 * qib_read_ureg - read virtualized per-context register 795 * @dd: device 796 * @regno: register number 797 * @ctxt: context number 798 * 799 * Return the contents of a register that is virtualized to be per context. 800 * Returns -1 on errors (not distinguishable from valid contents at 801 * runtime; we may add a separate error variable at some point). 802 */ 803 static inline u64 qib_read_ureg(const struct qib_devdata *dd, 804 enum qib_ureg regno, int ctxt) 805 { 806 807 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 808 return 0; 809 return readq(regno + (u64 __iomem *)( 810 (dd->ureg_align * ctxt) + (dd->userbase ? 811 (char __iomem *)dd->userbase : 812 (char __iomem *)dd->kregbase + dd->uregbase))); 813 } 814 815 /** 816 * qib_write_ureg - write virtualized per-context register 817 * @dd: device 818 * @regno: register number 819 * @value: value 820 * @ctxt: context 821 * 822 * Write the contents of a register that is virtualized to be per context. 823 */ 824 static inline void qib_write_ureg(const struct qib_devdata *dd, 825 enum qib_ureg regno, u64 value, int ctxt) 826 { 827 u64 __iomem *ubase; 828 829 if (dd->userbase) 830 ubase = (u64 __iomem *) 831 ((char __iomem *) dd->userbase + 832 dd->ureg_align * ctxt); 833 else 834 ubase = (u64 __iomem *) 835 (dd->uregbase + 836 (char __iomem *) dd->kregbase + 837 dd->ureg_align * ctxt); 838 839 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 840 writeq(value, &ubase[regno]); 841 } 842 843 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, 844 const u32 regno) 845 { 846 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 847 return -1; 848 return readl((u32 __iomem *) &dd->kregbase[regno]); 849 } 850 851 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, 852 const u32 regno) 853 { 854 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 855 return -1; 856 return readq(&dd->kregbase[regno]); 857 } 858 859 static inline void qib_write_kreg(const struct qib_devdata *dd, 860 const u32 regno, u64 value) 861 { 862 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 863 writeq(value, &dd->kregbase[regno]); 864 } 865 866 /* 867 * not many sanity checks for the port-specific kernel register routines, 868 * since they are only used when it's known to be safe. 869 */ 870 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd, 871 const u16 regno) 872 { 873 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) 874 return 0ULL; 875 return readq(&ppd->cpspec->kpregbase[regno]); 876 } 877 878 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd, 879 const u16 regno, u64 value) 880 { 881 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && 882 (ppd->dd->flags & QIB_PRESENT)) 883 writeq(value, &ppd->cpspec->kpregbase[regno]); 884 } 885 886 /** 887 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register 888 * @dd: the qlogic_ib device 889 * @regno: the register number to write 890 * @ctxt: the context containing the register 891 * @value: the value to write 892 */ 893 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, 894 const u16 regno, unsigned ctxt, 895 u64 value) 896 { 897 qib_write_kreg(dd, regno + ctxt, value); 898 } 899 900 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) 901 { 902 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 903 return 0; 904 return readq(&dd->cspec->cregbase[regno]); 905 906 907 } 908 909 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) 910 { 911 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 912 return 0; 913 return readl(&dd->cspec->cregbase[regno]); 914 915 916 } 917 918 static inline void write_7322_creg_port(const struct qib_pportdata *ppd, 919 u16 regno, u64 value) 920 { 921 if (ppd->cpspec && ppd->cpspec->cpregbase && 922 (ppd->dd->flags & QIB_PRESENT)) 923 writeq(value, &ppd->cpspec->cpregbase[regno]); 924 } 925 926 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd, 927 u16 regno) 928 { 929 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 930 !(ppd->dd->flags & QIB_PRESENT)) 931 return 0; 932 return readq(&ppd->cpspec->cpregbase[regno]); 933 } 934 935 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd, 936 u16 regno) 937 { 938 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 939 !(ppd->dd->flags & QIB_PRESENT)) 940 return 0; 941 return readl(&ppd->cpspec->cpregbase[regno]); 942 } 943 944 /* bits in Control register */ 945 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset) 946 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn) 947 948 /* bits in general interrupt regs */ 949 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask) 950 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17) 951 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB) 952 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask) 953 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17) 954 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB) 955 #define QIB_I_C_ERROR INT_MASK(Err) 956 957 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1)) 958 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail) 959 #define QIB_I_GPIO INT_MASK(AssertGPIO) 960 #define QIB_I_P_SDMAINT(pidx) \ 961 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 962 INT_MASK_P(SDmaProgress, pidx) | \ 963 INT_MASK_PM(SDmaCleanupDone, pidx)) 964 965 /* Interrupt bits that are "per port" */ 966 #define QIB_I_P_BITSEXTANT(pidx) \ 967 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \ 968 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 969 INT_MASK_P(SDmaProgress, pidx) | \ 970 INT_MASK_PM(SDmaCleanupDone, pidx)) 971 972 /* Interrupt bits that are common to a device */ 973 /* currently unused: QIB_I_SPIOSENT */ 974 #define QIB_I_C_BITSEXTANT \ 975 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \ 976 QIB_I_SPIOSENT | \ 977 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO) 978 979 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \ 980 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1)) 981 982 /* 983 * Error bits that are "per port". 984 */ 985 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged) 986 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr) 987 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr) 988 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr) 989 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr) 990 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr) 991 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr) 992 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr) 993 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr) 994 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr) 995 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr) 996 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr) 997 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr) 998 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr) 999 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr) 1000 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr) 1001 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr) 1002 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr) 1003 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr) 1004 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr) 1005 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr) 1006 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr) 1007 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr) 1008 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr) 1009 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr) 1010 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr) 1011 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr) 1012 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr) 1013 1014 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr) 1015 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr) 1016 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr) 1017 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr) 1018 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr) 1019 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr) 1020 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr) 1021 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr) 1022 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr) 1023 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr) 1024 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr) 1025 1026 /* Error bits that are common to a device */ 1027 #define QIB_E_RESET ERR_MASK(ResetNegated) 1028 #define QIB_E_HARDWARE ERR_MASK(HardwareErr) 1029 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr) 1030 1031 1032 /* 1033 * Per chip (rather than per-port) errors. Most either do 1034 * nothing but trigger a print (because they self-recover, or 1035 * always occur in tandem with other errors that handle the 1036 * issue), or because they indicate errors with no recovery, 1037 * but we want to know that they happened. 1038 */ 1039 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr) 1040 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd) 1041 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr) 1042 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr) 1043 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr) 1044 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr) 1045 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr) 1046 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr) 1047 1048 /* SDMA chip errors (not per port) 1049 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get 1050 * the SDMAHALT error immediately, so we just print the dup error via the 1051 * E_AUTO mechanism. This is true of most of the per-port fatal errors 1052 * as well, but since this is port-independent, by definition, it's 1053 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per 1054 * packet send errors, and so are handled in the same manner as other 1055 * per-packet errors. 1056 */ 1057 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err) 1058 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr) 1059 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr) 1060 1061 /* 1062 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS 1063 * it is used to print "common" packet errors. 1064 */ 1065 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\ 1066 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\ 1067 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\ 1068 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 1069 QIB_E_P_REBP) 1070 1071 /* Error Bits that Packet-related (Receive, per-port) */ 1072 #define QIB_E_P_RPKTERRS (\ 1073 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \ 1074 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \ 1075 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\ 1076 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \ 1077 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \ 1078 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP) 1079 1080 /* 1081 * Error bits that are Send-related (per port) 1082 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling). 1083 * All of these potentially need to have a buffer disarmed 1084 */ 1085 #define QIB_E_P_SPKTERRS (\ 1086 QIB_E_P_SUNEXP_PKTNUM |\ 1087 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1088 QIB_E_P_SMAXPKTLEN |\ 1089 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 1090 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \ 1091 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL) 1092 1093 #define QIB_E_SPKTERRS ( \ 1094 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \ 1095 ERR_MASK_N(SendUnsupportedVLErr) | \ 1096 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT) 1097 1098 #define QIB_E_P_SDMAERRS ( \ 1099 QIB_E_P_SDMAHALT | \ 1100 QIB_E_P_SDMADESCADDRMISALIGN | \ 1101 QIB_E_P_SDMAUNEXPDATA | \ 1102 QIB_E_P_SDMAMISSINGDW | \ 1103 QIB_E_P_SDMADWEN | \ 1104 QIB_E_P_SDMARPYTAG | \ 1105 QIB_E_P_SDMA1STDESC | \ 1106 QIB_E_P_SDMABASE | \ 1107 QIB_E_P_SDMATAILOUTOFBOUND | \ 1108 QIB_E_P_SDMAOUTOFBOUND | \ 1109 QIB_E_P_SDMAGENMISMATCH) 1110 1111 /* 1112 * This sets some bits more than once, but makes it more obvious which 1113 * bits are not handled under other categories, and the repeat definition 1114 * is not a problem. 1115 */ 1116 #define QIB_E_P_BITSEXTANT ( \ 1117 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \ 1118 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \ 1119 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \ 1120 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \ 1121 ) 1122 1123 /* 1124 * These are errors that can occur when the link 1125 * changes state while a packet is being sent or received. This doesn't 1126 * cover things like EBP or VCRC that can be the result of a sending 1127 * having the link change state, so we receive a "known bad" packet. 1128 * All of these are "per port", so renamed: 1129 */ 1130 #define QIB_E_P_LINK_PKTERRS (\ 1131 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1132 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\ 1133 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\ 1134 QIB_E_P_RUNEXPCHAR) 1135 1136 /* 1137 * This sets some bits more than once, but makes it more obvious which 1138 * bits are not handled under other categories (such as QIB_E_SPKTERRS), 1139 * and the repeat definition is not a problem. 1140 */ 1141 #define QIB_E_C_BITSEXTANT (\ 1142 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\ 1143 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\ 1144 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE) 1145 1146 /* Likewise Neuter E_SPKT_ERRS_IGNORE */ 1147 #define E_SPKT_ERRS_IGNORE 0 1148 1149 #define QIB_EXTS_MEMBIST_DISABLED \ 1150 SYM_MASK(EXTStatus, MemBISTDisabled) 1151 #define QIB_EXTS_MEMBIST_ENDTEST \ 1152 SYM_MASK(EXTStatus, MemBISTEndTest) 1153 1154 #define QIB_E_SPIOARMLAUNCH \ 1155 ERR_MASK(SendArmLaunchErr) 1156 1157 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd) 1158 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd) 1159 1160 /* 1161 * IBTA_1_2 is set when multiple speeds are enabled (normal), 1162 * and also if forced QDR (only QDR enabled). It's enabled for the 1163 * forced QDR case so that scrambling will be enabled by the TS3 1164 * exchange, when supported by both sides of the link. 1165 */ 1166 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE) 1167 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED) 1168 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR) 1169 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) 1170 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) 1171 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \ 1172 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)) 1173 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR) 1174 1175 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod) 1176 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod) 1177 1178 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS) 1179 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1180 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1181 1182 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1183 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1184 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \ 1185 SYM_MASK(IBCCtrlB_0, HRTBT_ENB)) 1186 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \ 1187 SYM_LSB(IBCCtrlB_0, HRTBT_ENB)) 1188 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB) 1189 1190 #define IBA7322_REDIRECT_VEC_PER_REG 12 1191 1192 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En) 1193 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En) 1194 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En) 1195 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En) 1196 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En) 1197 1198 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */ 1199 1200 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \ 1201 .msg = #fldname , .sz = sizeof(#fldname) } 1202 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \ 1203 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) } 1204 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = { 1205 HWE_AUTO_P(IBSerdesPClkNotDetect, 1), 1206 HWE_AUTO_P(IBSerdesPClkNotDetect, 0), 1207 HWE_AUTO(PCIESerdesPClkNotDetect), 1208 HWE_AUTO(PowerOnBISTFailed), 1209 HWE_AUTO(TempsenseTholdReached), 1210 HWE_AUTO(MemoryErr), 1211 HWE_AUTO(PCIeBusParityErr), 1212 HWE_AUTO(PcieCplTimeout), 1213 HWE_AUTO(PciePoisonedTLP), 1214 HWE_AUTO_P(SDmaMemReadErr, 1), 1215 HWE_AUTO_P(SDmaMemReadErr, 0), 1216 HWE_AUTO_P(IBCBusFromSPCParityErr, 1), 1217 HWE_AUTO_P(IBCBusToSPCParityErr, 1), 1218 HWE_AUTO_P(IBCBusFromSPCParityErr, 0), 1219 HWE_AUTO(statusValidNoEop), 1220 HWE_AUTO(LATriggered), 1221 { .mask = 0, .sz = 0 } 1222 }; 1223 1224 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \ 1225 .msg = #fldname, .sz = sizeof(#fldname) } 1226 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \ 1227 .msg = #fldname, .sz = sizeof(#fldname) } 1228 static const struct qib_hwerror_msgs qib_7322error_msgs[] = { 1229 E_AUTO(RcvEgrFullErr), 1230 E_AUTO(RcvHdrFullErr), 1231 E_AUTO(ResetNegated), 1232 E_AUTO(HardwareErr), 1233 E_AUTO(InvalidAddrErr), 1234 E_AUTO(SDmaVL15Err), 1235 E_AUTO(SBufVL15MisUseErr), 1236 E_AUTO(InvalidEEPCmd), 1237 E_AUTO(RcvContextShareErr), 1238 E_AUTO(SendVLMismatchErr), 1239 E_AUTO(SendArmLaunchErr), 1240 E_AUTO(SendSpecialTriggerErr), 1241 E_AUTO(SDmaWrongPortErr), 1242 E_AUTO(SDmaBufMaskDuplicateErr), 1243 { .mask = 0, .sz = 0 } 1244 }; 1245 1246 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = { 1247 E_P_AUTO(IBStatusChanged), 1248 E_P_AUTO(SHeadersErr), 1249 E_P_AUTO(VL15BufMisuseErr), 1250 /* 1251 * SDmaHaltErr is not really an error, make it clearer; 1252 */ 1253 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted", 1254 .sz = 11}, 1255 E_P_AUTO(SDmaDescAddrMisalignErr), 1256 E_P_AUTO(SDmaUnexpDataErr), 1257 E_P_AUTO(SDmaMissingDwErr), 1258 E_P_AUTO(SDmaDwEnErr), 1259 E_P_AUTO(SDmaRpyTagErr), 1260 E_P_AUTO(SDma1stDescErr), 1261 E_P_AUTO(SDmaBaseErr), 1262 E_P_AUTO(SDmaTailOutOfBoundErr), 1263 E_P_AUTO(SDmaOutOfBoundErr), 1264 E_P_AUTO(SDmaGenMismatchErr), 1265 E_P_AUTO(SendBufMisuseErr), 1266 E_P_AUTO(SendUnsupportedVLErr), 1267 E_P_AUTO(SendUnexpectedPktNumErr), 1268 E_P_AUTO(SendDroppedDataPktErr), 1269 E_P_AUTO(SendDroppedSmpPktErr), 1270 E_P_AUTO(SendPktLenErr), 1271 E_P_AUTO(SendUnderRunErr), 1272 E_P_AUTO(SendMaxPktLenErr), 1273 E_P_AUTO(SendMinPktLenErr), 1274 E_P_AUTO(RcvIBLostLinkErr), 1275 E_P_AUTO(RcvHdrErr), 1276 E_P_AUTO(RcvHdrLenErr), 1277 E_P_AUTO(RcvBadTidErr), 1278 E_P_AUTO(RcvBadVersionErr), 1279 E_P_AUTO(RcvIBFlowErr), 1280 E_P_AUTO(RcvEBPErr), 1281 E_P_AUTO(RcvUnsupportedVLErr), 1282 E_P_AUTO(RcvUnexpectedCharErr), 1283 E_P_AUTO(RcvShortPktLenErr), 1284 E_P_AUTO(RcvLongPktLenErr), 1285 E_P_AUTO(RcvMaxPktLenErr), 1286 E_P_AUTO(RcvMinPktLenErr), 1287 E_P_AUTO(RcvICRCErr), 1288 E_P_AUTO(RcvVCRCErr), 1289 E_P_AUTO(RcvFormatErr), 1290 { .mask = 0, .sz = 0 } 1291 }; 1292 1293 /* 1294 * Below generates "auto-message" for interrupts not specific to any port or 1295 * context 1296 */ 1297 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \ 1298 .msg = #fldname, .sz = sizeof(#fldname) } 1299 /* Below generates "auto-message" for interrupts specific to a port */ 1300 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\ 1301 SYM_LSB(IntMask, fldname##Mask##_0), \ 1302 SYM_LSB(IntMask, fldname##Mask##_1)), \ 1303 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1304 /* For some reason, the SerDesTrimDone bits are reversed */ 1305 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\ 1306 SYM_LSB(IntMask, fldname##Mask##_1), \ 1307 SYM_LSB(IntMask, fldname##Mask##_0)), \ 1308 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1309 /* 1310 * Below generates "auto-message" for interrupts specific to a context, 1311 * with ctxt-number appended 1312 */ 1313 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\ 1314 SYM_LSB(IntMask, fldname##0IntMask), \ 1315 SYM_LSB(IntMask, fldname##17IntMask)), \ 1316 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") } 1317 1318 #define TXSYMPTOM_AUTO_P(fldname) \ 1319 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \ 1320 .msg = #fldname, .sz = sizeof(#fldname) } 1321 static const struct qib_hwerror_msgs hdrchk_msgs[] = { 1322 TXSYMPTOM_AUTO_P(NonKeyPacket), 1323 TXSYMPTOM_AUTO_P(GRHFail), 1324 TXSYMPTOM_AUTO_P(PkeyFail), 1325 TXSYMPTOM_AUTO_P(QPFail), 1326 TXSYMPTOM_AUTO_P(SLIDFail), 1327 TXSYMPTOM_AUTO_P(RawIPV6), 1328 TXSYMPTOM_AUTO_P(PacketTooSmall), 1329 { .mask = 0, .sz = 0 } 1330 }; 1331 1332 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */ 1333 1334 /* 1335 * Called when we might have an error that is specific to a particular 1336 * PIO buffer, and may need to cancel that buffer, so it can be re-used, 1337 * because we don't need to force the update of pioavail 1338 */ 1339 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd) 1340 { 1341 struct qib_devdata *dd = ppd->dd; 1342 u32 i; 1343 int any; 1344 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 1345 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG; 1346 unsigned long sbuf[4]; 1347 1348 /* 1349 * It's possible that sendbuffererror could have bits set; might 1350 * have already done this as a result of hardware error handling. 1351 */ 1352 any = 0; 1353 for (i = 0; i < regcnt; ++i) { 1354 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); 1355 if (sbuf[i]) { 1356 any = 1; 1357 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); 1358 } 1359 } 1360 1361 if (any) 1362 qib_disarm_piobufs_set(dd, sbuf, piobcnt); 1363 } 1364 1365 /* No txe_recover yet, if ever */ 1366 1367 /* No decode__errors yet */ 1368 static void err_decode(char *msg, size_t len, u64 errs, 1369 const struct qib_hwerror_msgs *msp) 1370 { 1371 u64 these, lmask; 1372 int took, multi, n = 0; 1373 1374 while (errs && msp && msp->mask) { 1375 multi = (msp->mask & (msp->mask - 1)); 1376 while (errs & msp->mask) { 1377 these = (errs & msp->mask); 1378 lmask = (these & (these - 1)) ^ these; 1379 if (len) { 1380 if (n++) { 1381 /* separate the strings */ 1382 *msg++ = ','; 1383 len--; 1384 } 1385 /* msp->sz counts the nul */ 1386 took = min_t(size_t, msp->sz - (size_t)1, len); 1387 memcpy(msg, msp->msg, took); 1388 len -= took; 1389 msg += took; 1390 if (len) 1391 *msg = '\0'; 1392 } 1393 errs &= ~lmask; 1394 if (len && multi) { 1395 /* More than one bit this mask */ 1396 int idx = -1; 1397 1398 while (lmask & msp->mask) { 1399 ++idx; 1400 lmask >>= 1; 1401 } 1402 took = scnprintf(msg, len, "_%d", idx); 1403 len -= took; 1404 msg += took; 1405 } 1406 } 1407 ++msp; 1408 } 1409 /* If some bits are left, show in hex. */ 1410 if (len && errs) 1411 snprintf(msg, len, "%sMORE:%llX", n ? "," : "", 1412 (unsigned long long) errs); 1413 } 1414 1415 /* only called if r1 set */ 1416 static void flush_fifo(struct qib_pportdata *ppd) 1417 { 1418 struct qib_devdata *dd = ppd->dd; 1419 u32 __iomem *piobuf; 1420 u32 bufn; 1421 u32 *hdr; 1422 u64 pbc; 1423 const unsigned hdrwords = 7; 1424 static struct ib_header ibhdr = { 1425 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH), 1426 .lrh[1] = IB_LID_PERMISSIVE, 1427 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC), 1428 .lrh[3] = IB_LID_PERMISSIVE, 1429 .u.oth.bth[0] = cpu_to_be32( 1430 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY), 1431 .u.oth.bth[1] = cpu_to_be32(0), 1432 .u.oth.bth[2] = cpu_to_be32(0), 1433 .u.oth.u.ud.deth[0] = cpu_to_be32(0), 1434 .u.oth.u.ud.deth[1] = cpu_to_be32(0), 1435 }; 1436 1437 /* 1438 * Send a dummy VL15 packet to flush the launch FIFO. 1439 * This will not actually be sent since the TxeBypassIbc bit is set. 1440 */ 1441 pbc = PBC_7322_VL15_SEND | 1442 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) | 1443 (hdrwords + SIZE_OF_CRC); 1444 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn); 1445 if (!piobuf) 1446 return; 1447 writeq(pbc, piobuf); 1448 hdr = (u32 *) &ibhdr; 1449 if (dd->flags & QIB_PIO_FLUSH_WC) { 1450 qib_flush_wc(); 1451 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1); 1452 qib_flush_wc(); 1453 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1); 1454 qib_flush_wc(); 1455 } else 1456 qib_pio_copy(piobuf + 2, hdr, hdrwords); 1457 qib_sendbuf_done(dd, bufn); 1458 } 1459 1460 /* 1461 * This is called with interrupts disabled and sdma_lock held. 1462 */ 1463 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) 1464 { 1465 struct qib_devdata *dd = ppd->dd; 1466 u64 set_sendctrl = 0; 1467 u64 clr_sendctrl = 0; 1468 1469 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE) 1470 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1471 else 1472 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1473 1474 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE) 1475 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1476 else 1477 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1478 1479 if (op & QIB_SDMA_SENDCTRL_OP_HALT) 1480 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1481 else 1482 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1483 1484 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) 1485 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1486 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1487 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1488 else 1489 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1490 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1491 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1492 1493 spin_lock(&dd->sendctrl_lock); 1494 1495 /* If we are draining everything, block sends first */ 1496 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1497 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 1498 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1499 qib_write_kreg(dd, kr_scratch, 0); 1500 } 1501 1502 ppd->p_sendctrl |= set_sendctrl; 1503 ppd->p_sendctrl &= ~clr_sendctrl; 1504 1505 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP) 1506 qib_write_kreg_port(ppd, krp_sendctrl, 1507 ppd->p_sendctrl | 1508 SYM_MASK(SendCtrl_0, SDmaCleanup)); 1509 else 1510 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1511 qib_write_kreg(dd, kr_scratch, 0); 1512 1513 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1514 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 1515 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1516 qib_write_kreg(dd, kr_scratch, 0); 1517 } 1518 1519 spin_unlock(&dd->sendctrl_lock); 1520 1521 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) 1522 flush_fifo(ppd); 1523 } 1524 1525 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd) 1526 { 1527 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned); 1528 } 1529 1530 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd) 1531 { 1532 /* 1533 * Set SendDmaLenGen and clear and set 1534 * the MSB of the generation count to enable generation checking 1535 * and load the internal generation counter. 1536 */ 1537 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt); 1538 qib_write_kreg_port(ppd, krp_senddmalengen, 1539 ppd->sdma_descq_cnt | 1540 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB)); 1541 } 1542 1543 /* 1544 * Must be called with sdma_lock held, or before init finished. 1545 */ 1546 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail) 1547 { 1548 /* Commit writes to memory and advance the tail on the chip */ 1549 wmb(); 1550 ppd->sdma_descq_tail = tail; 1551 qib_write_kreg_port(ppd, krp_senddmatail, tail); 1552 } 1553 1554 /* 1555 * This is called with interrupts disabled and sdma_lock held. 1556 */ 1557 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd) 1558 { 1559 /* 1560 * Drain all FIFOs. 1561 * The hardware doesn't require this but we do it so that verbs 1562 * and user applications don't wait for link active to send stale 1563 * data. 1564 */ 1565 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH); 1566 1567 qib_sdma_7322_setlengen(ppd); 1568 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 1569 ppd->sdma_head_dma[0] = 0; 1570 qib_7322_sdma_sendctrl(ppd, 1571 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP); 1572 } 1573 1574 #define DISABLES_SDMA ( \ 1575 QIB_E_P_SDMAHALT | \ 1576 QIB_E_P_SDMADESCADDRMISALIGN | \ 1577 QIB_E_P_SDMAMISSINGDW | \ 1578 QIB_E_P_SDMADWEN | \ 1579 QIB_E_P_SDMARPYTAG | \ 1580 QIB_E_P_SDMA1STDESC | \ 1581 QIB_E_P_SDMABASE | \ 1582 QIB_E_P_SDMATAILOUTOFBOUND | \ 1583 QIB_E_P_SDMAOUTOFBOUND | \ 1584 QIB_E_P_SDMAGENMISMATCH) 1585 1586 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs) 1587 { 1588 unsigned long flags; 1589 struct qib_devdata *dd = ppd->dd; 1590 1591 errs &= QIB_E_P_SDMAERRS; 1592 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf), 1593 errs, qib_7322p_error_msgs); 1594 1595 if (errs & QIB_E_P_SDMAUNEXPDATA) 1596 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, 1597 ppd->port); 1598 1599 spin_lock_irqsave(&ppd->sdma_lock, flags); 1600 1601 if (errs != QIB_E_P_SDMAHALT) { 1602 /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */ 1603 qib_dev_porterr(dd, ppd->port, 1604 "SDMA %s 0x%016llx %s\n", 1605 qib_sdma_state_names[ppd->sdma_state.current_state], 1606 errs, ppd->cpspec->sdmamsgbuf); 1607 dump_sdma_7322_state(ppd); 1608 } 1609 1610 switch (ppd->sdma_state.current_state) { 1611 case qib_sdma_state_s00_hw_down: 1612 break; 1613 1614 case qib_sdma_state_s10_hw_start_up_wait: 1615 if (errs & QIB_E_P_SDMAHALT) 1616 __qib_sdma_process_event(ppd, 1617 qib_sdma_event_e20_hw_started); 1618 break; 1619 1620 case qib_sdma_state_s20_idle: 1621 break; 1622 1623 case qib_sdma_state_s30_sw_clean_up_wait: 1624 break; 1625 1626 case qib_sdma_state_s40_hw_clean_up_wait: 1627 if (errs & QIB_E_P_SDMAHALT) 1628 __qib_sdma_process_event(ppd, 1629 qib_sdma_event_e50_hw_cleaned); 1630 break; 1631 1632 case qib_sdma_state_s50_hw_halt_wait: 1633 if (errs & QIB_E_P_SDMAHALT) 1634 __qib_sdma_process_event(ppd, 1635 qib_sdma_event_e60_hw_halted); 1636 break; 1637 1638 case qib_sdma_state_s99_running: 1639 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted); 1640 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted); 1641 break; 1642 } 1643 1644 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 1645 } 1646 1647 /* 1648 * handle per-device errors (not per-port errors) 1649 */ 1650 static noinline void handle_7322_errors(struct qib_devdata *dd) 1651 { 1652 char *msg; 1653 u64 iserr = 0; 1654 u64 errs; 1655 u64 mask; 1656 1657 qib_stats.sps_errints++; 1658 errs = qib_read_kreg64(dd, kr_errstatus); 1659 if (!errs) { 1660 qib_devinfo(dd->pcidev, 1661 "device error interrupt, but no error bits set!\n"); 1662 goto done; 1663 } 1664 1665 /* don't report errors that are masked */ 1666 errs &= dd->cspec->errormask; 1667 msg = dd->cspec->emsgbuf; 1668 1669 /* do these first, they are most important */ 1670 if (errs & QIB_E_HARDWARE) { 1671 *msg = '\0'; 1672 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); 1673 } 1674 1675 if (errs & QIB_E_SPKTERRS) { 1676 qib_disarm_7322_senderrbufs(dd->pport); 1677 qib_stats.sps_txerrs++; 1678 } else if (errs & QIB_E_INVALIDADDR) 1679 qib_stats.sps_txerrs++; 1680 else if (errs & QIB_E_ARMLAUNCH) { 1681 qib_stats.sps_txerrs++; 1682 qib_disarm_7322_senderrbufs(dd->pport); 1683 } 1684 qib_write_kreg(dd, kr_errclear, errs); 1685 1686 /* 1687 * The ones we mask off are handled specially below 1688 * or above. Also mask SDMADISABLED by default as it 1689 * is too chatty. 1690 */ 1691 mask = QIB_E_HARDWARE; 1692 *msg = '\0'; 1693 1694 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, 1695 qib_7322error_msgs); 1696 1697 /* 1698 * Getting reset is a tragedy for all ports. Mark the device 1699 * _and_ the ports as "offline" in way meaningful to each. 1700 */ 1701 if (errs & QIB_E_RESET) { 1702 int pidx; 1703 1704 qib_dev_err(dd, 1705 "Got reset, requires re-init (unload and reload driver)\n"); 1706 dd->flags &= ~QIB_INITTED; /* needs re-init */ 1707 /* mark as having had error */ 1708 *dd->devstatusp |= QIB_STATUS_HWERROR; 1709 for (pidx = 0; pidx < dd->num_pports; ++pidx) 1710 if (dd->pport[pidx].link_speed_supported) 1711 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; 1712 } 1713 1714 if (*msg && iserr) 1715 qib_dev_err(dd, "%s error\n", msg); 1716 1717 /* 1718 * If there were hdrq or egrfull errors, wake up any processes 1719 * waiting in poll. We used to try to check which contexts had 1720 * the overflow, but given the cost of that and the chip reads 1721 * to support it, it's better to just wake everybody up if we 1722 * get an overflow; waiters can poll again if it's not them. 1723 */ 1724 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) { 1725 qib_handle_urcv(dd, ~0U); 1726 if (errs & ERR_MASK(RcvEgrFullErr)) 1727 qib_stats.sps_buffull++; 1728 else 1729 qib_stats.sps_hdrfull++; 1730 } 1731 1732 done: 1733 return; 1734 } 1735 1736 static void qib_error_tasklet(unsigned long data) 1737 { 1738 struct qib_devdata *dd = (struct qib_devdata *)data; 1739 1740 handle_7322_errors(dd); 1741 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1742 } 1743 1744 static void reenable_chase(struct timer_list *t) 1745 { 1746 struct qib_chippport_specific *cp = from_timer(cp, t, chase_timer); 1747 struct qib_pportdata *ppd = cp->ppd; 1748 1749 ppd->cpspec->chase_timer.expires = 0; 1750 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1751 QLOGIC_IB_IBCC_LINKINITCMD_POLL); 1752 } 1753 1754 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow, 1755 u8 ibclt) 1756 { 1757 ppd->cpspec->chase_end = 0; 1758 1759 if (!qib_chase) 1760 return; 1761 1762 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1763 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1764 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME; 1765 add_timer(&ppd->cpspec->chase_timer); 1766 } 1767 1768 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst) 1769 { 1770 u8 ibclt; 1771 unsigned long tnow; 1772 1773 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState); 1774 1775 /* 1776 * Detect and handle the state chase issue, where we can 1777 * get stuck if we are unlucky on timing on both sides of 1778 * the link. If we are, we disable, set a timer, and 1779 * then re-enable. 1780 */ 1781 switch (ibclt) { 1782 case IB_7322_LT_STATE_CFGRCVFCFG: 1783 case IB_7322_LT_STATE_CFGWAITRMT: 1784 case IB_7322_LT_STATE_TXREVLANES: 1785 case IB_7322_LT_STATE_CFGENH: 1786 tnow = jiffies; 1787 if (ppd->cpspec->chase_end && 1788 time_after(tnow, ppd->cpspec->chase_end)) 1789 disable_chase(ppd, tnow, ibclt); 1790 else if (!ppd->cpspec->chase_end) 1791 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME; 1792 break; 1793 default: 1794 ppd->cpspec->chase_end = 0; 1795 break; 1796 } 1797 1798 if (((ibclt >= IB_7322_LT_STATE_CFGTEST && 1799 ibclt <= IB_7322_LT_STATE_CFGWAITENH) || 1800 ibclt == IB_7322_LT_STATE_LINKUP) && 1801 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { 1802 force_h1(ppd); 1803 ppd->cpspec->qdr_reforce = 1; 1804 if (!ppd->dd->cspec->r1) 1805 serdes_7322_los_enable(ppd, 0); 1806 } else if (ppd->cpspec->qdr_reforce && 1807 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && 1808 (ibclt == IB_7322_LT_STATE_CFGENH || 1809 ibclt == IB_7322_LT_STATE_CFGIDLE || 1810 ibclt == IB_7322_LT_STATE_LINKUP)) 1811 force_h1(ppd); 1812 1813 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && 1814 ppd->link_speed_enabled == QIB_IB_QDR && 1815 (ibclt == IB_7322_LT_STATE_CFGTEST || 1816 ibclt == IB_7322_LT_STATE_CFGENH || 1817 (ibclt >= IB_7322_LT_STATE_POLLACTIVE && 1818 ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) 1819 adj_tx_serdes(ppd); 1820 1821 if (ibclt != IB_7322_LT_STATE_LINKUP) { 1822 u8 ltstate = qib_7322_phys_portstate(ibcst); 1823 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, 1824 LinkTrainingState); 1825 if (!ppd->dd->cspec->r1 && 1826 pibclt == IB_7322_LT_STATE_LINKUP && 1827 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1828 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1829 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1830 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1831 /* If the link went down (but no into recovery, 1832 * turn LOS back on */ 1833 serdes_7322_los_enable(ppd, 1); 1834 if (!ppd->cpspec->qdr_dfe_on && 1835 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { 1836 ppd->cpspec->qdr_dfe_on = 1; 1837 ppd->cpspec->qdr_dfe_time = 0; 1838 /* On link down, reenable QDR adaptation */ 1839 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 1840 ppd->dd->cspec->r1 ? 1841 QDR_STATIC_ADAPT_DOWN_R1 : 1842 QDR_STATIC_ADAPT_DOWN); 1843 pr_info( 1844 "IB%u:%u re-enabled QDR adaptation ibclt %x\n", 1845 ppd->dd->unit, ppd->port, ibclt); 1846 } 1847 } 1848 } 1849 1850 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); 1851 1852 /* 1853 * This is per-pport error handling. 1854 * will likely get it's own MSIx interrupt (one for each port, 1855 * although just a single handler). 1856 */ 1857 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd) 1858 { 1859 char *msg; 1860 u64 ignore_this_time = 0, iserr = 0, errs, fmask; 1861 struct qib_devdata *dd = ppd->dd; 1862 1863 /* do this as soon as possible */ 1864 fmask = qib_read_kreg64(dd, kr_act_fmask); 1865 if (!fmask) 1866 check_7322_rxe_status(ppd); 1867 1868 errs = qib_read_kreg_port(ppd, krp_errstatus); 1869 if (!errs) 1870 qib_devinfo(dd->pcidev, 1871 "Port%d error interrupt, but no error bits set!\n", 1872 ppd->port); 1873 if (!fmask) 1874 errs &= ~QIB_E_P_IBSTATUSCHANGED; 1875 if (!errs) 1876 goto done; 1877 1878 msg = ppd->cpspec->epmsgbuf; 1879 *msg = '\0'; 1880 1881 if (errs & ~QIB_E_P_BITSEXTANT) { 1882 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), 1883 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs); 1884 if (!*msg) 1885 snprintf(msg, sizeof(ppd->cpspec->epmsgbuf), 1886 "no others"); 1887 qib_dev_porterr(dd, ppd->port, 1888 "error interrupt with unknown errors 0x%016Lx set (and %s)\n", 1889 (errs & ~QIB_E_P_BITSEXTANT), msg); 1890 *msg = '\0'; 1891 } 1892 1893 if (errs & QIB_E_P_SHDR) { 1894 u64 symptom; 1895 1896 /* determine cause, then write to clear */ 1897 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom); 1898 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0); 1899 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom, 1900 hdrchk_msgs); 1901 *msg = '\0'; 1902 /* senderrbuf cleared in SPKTERRS below */ 1903 } 1904 1905 if (errs & QIB_E_P_SPKTERRS) { 1906 if ((errs & QIB_E_P_LINK_PKTERRS) && 1907 !(ppd->lflags & QIBL_LINKACTIVE)) { 1908 /* 1909 * This can happen when trying to bring the link 1910 * up, but the IB link changes state at the "wrong" 1911 * time. The IB logic then complains that the packet 1912 * isn't valid. We don't want to confuse people, so 1913 * we just don't print them, except at debug 1914 */ 1915 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), 1916 (errs & QIB_E_P_LINK_PKTERRS), 1917 qib_7322p_error_msgs); 1918 *msg = '\0'; 1919 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1920 } 1921 qib_disarm_7322_senderrbufs(ppd); 1922 } else if ((errs & QIB_E_P_LINK_PKTERRS) && 1923 !(ppd->lflags & QIBL_LINKACTIVE)) { 1924 /* 1925 * This can happen when SMA is trying to bring the link 1926 * up, but the IB link changes state at the "wrong" time. 1927 * The IB logic then complains that the packet isn't 1928 * valid. We don't want to confuse people, so we just 1929 * don't print them, except at debug 1930 */ 1931 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs, 1932 qib_7322p_error_msgs); 1933 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1934 *msg = '\0'; 1935 } 1936 1937 qib_write_kreg_port(ppd, krp_errclear, errs); 1938 1939 errs &= ~ignore_this_time; 1940 if (!errs) 1941 goto done; 1942 1943 if (errs & QIB_E_P_RPKTERRS) 1944 qib_stats.sps_rcverrs++; 1945 if (errs & QIB_E_P_SPKTERRS) 1946 qib_stats.sps_txerrs++; 1947 1948 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS); 1949 1950 if (errs & QIB_E_P_SDMAERRS) 1951 sdma_7322_p_errors(ppd, errs); 1952 1953 if (errs & QIB_E_P_IBSTATUSCHANGED) { 1954 u64 ibcs; 1955 u8 ltstate; 1956 1957 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a); 1958 ltstate = qib_7322_phys_portstate(ibcs); 1959 1960 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 1961 handle_serdes_issues(ppd, ibcs); 1962 if (!(ppd->cpspec->ibcctrl_a & 1963 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { 1964 /* 1965 * We got our interrupt, so init code should be 1966 * happy and not try alternatives. Now squelch 1967 * other "chatter" from link-negotiation (pre Init) 1968 */ 1969 ppd->cpspec->ibcctrl_a |= 1970 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 1971 qib_write_kreg_port(ppd, krp_ibcctrl_a, 1972 ppd->cpspec->ibcctrl_a); 1973 } 1974 1975 /* Update our picture of width and speed from chip */ 1976 ppd->link_width_active = 1977 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? 1978 IB_WIDTH_4X : IB_WIDTH_1X; 1979 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, 1980 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs & 1981 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? 1982 QIB_IB_DDR : QIB_IB_SDR; 1983 1984 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate != 1985 IB_PHYSPORTSTATE_DISABLED) 1986 qib_set_ib_7322_lstate(ppd, 0, 1987 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1988 else 1989 /* 1990 * Since going into a recovery state causes the link 1991 * state to go down and since recovery is transitory, 1992 * it is better if we "miss" ever seeing the link 1993 * training state go into recovery (i.e., ignore this 1994 * transition for link state special handling purposes) 1995 * without updating lastibcstat. 1996 */ 1997 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1998 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1999 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 2000 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 2001 qib_handle_e_ibstatuschanged(ppd, ibcs); 2002 } 2003 if (*msg && iserr) 2004 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); 2005 2006 if (ppd->state_wanted & ppd->lflags) 2007 wake_up_interruptible(&ppd->state_wait); 2008 done: 2009 return; 2010 } 2011 2012 /* enable/disable chip from delivering interrupts */ 2013 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) 2014 { 2015 if (enable) { 2016 if (dd->flags & QIB_BADINTR) 2017 return; 2018 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); 2019 /* cause any pending enabled interrupts to be re-delivered */ 2020 qib_write_kreg(dd, kr_intclear, 0ULL); 2021 if (dd->cspec->num_msix_entries) { 2022 /* and same for MSIx */ 2023 u64 val = qib_read_kreg64(dd, kr_intgranted); 2024 2025 if (val) 2026 qib_write_kreg(dd, kr_intgranted, val); 2027 } 2028 } else 2029 qib_write_kreg(dd, kr_intmask, 0ULL); 2030 } 2031 2032 /* 2033 * Try to cleanup as much as possible for anything that might have gone 2034 * wrong while in freeze mode, such as pio buffers being written by user 2035 * processes (causing armlaunch), send errors due to going into freeze mode, 2036 * etc., and try to avoid causing extra interrupts while doing so. 2037 * Forcibly update the in-memory pioavail register copies after cleanup 2038 * because the chip won't do it while in freeze mode (the register values 2039 * themselves are kept correct). 2040 * Make sure that we don't lose any important interrupts by using the chip 2041 * feature that says that writing 0 to a bit in *clear that is set in 2042 * *status will cause an interrupt to be generated again (if allowed by 2043 * the *mask value). 2044 * This is in chip-specific code because of all of the register accesses, 2045 * even though the details are similar on most chips. 2046 */ 2047 static void qib_7322_clear_freeze(struct qib_devdata *dd) 2048 { 2049 int pidx; 2050 2051 /* disable error interrupts, to avoid confusion */ 2052 qib_write_kreg(dd, kr_errmask, 0ULL); 2053 2054 for (pidx = 0; pidx < dd->num_pports; ++pidx) 2055 if (dd->pport[pidx].link_speed_supported) 2056 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 2057 0ULL); 2058 2059 /* also disable interrupts; errormask is sometimes overwritten */ 2060 qib_7322_set_intr_state(dd, 0); 2061 2062 /* clear the freeze, and be sure chip saw it */ 2063 qib_write_kreg(dd, kr_control, dd->control); 2064 qib_read_kreg32(dd, kr_scratch); 2065 2066 /* 2067 * Force new interrupt if any hwerr, error or interrupt bits are 2068 * still set, and clear "safe" send packet errors related to freeze 2069 * and cancelling sends. Re-enable error interrupts before possible 2070 * force of re-interrupt on pending interrupts. 2071 */ 2072 qib_write_kreg(dd, kr_hwerrclear, 0ULL); 2073 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); 2074 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 2075 /* We need to purge per-port errs and reset mask, too */ 2076 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 2077 if (!dd->pport[pidx].link_speed_supported) 2078 continue; 2079 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); 2080 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); 2081 } 2082 qib_7322_set_intr_state(dd, 1); 2083 } 2084 2085 /* no error handling to speak of */ 2086 /** 2087 * qib_7322_handle_hwerrors - display hardware errors. 2088 * @dd: the qlogic_ib device 2089 * @msg: the output buffer 2090 * @msgl: the size of the output buffer 2091 * 2092 * Use same msg buffer as regular errors to avoid excessive stack 2093 * use. Most hardware errors are catastrophic, but for right now, 2094 * we'll print them and continue. We reuse the same message buffer as 2095 * qib_handle_errors() to avoid excessive stack usage. 2096 */ 2097 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, 2098 size_t msgl) 2099 { 2100 u64 hwerrs; 2101 u32 ctrl; 2102 int isfatal = 0; 2103 2104 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 2105 if (!hwerrs) 2106 goto bail; 2107 if (hwerrs == ~0ULL) { 2108 qib_dev_err(dd, 2109 "Read of hardware error status failed (all bits set); ignoring\n"); 2110 goto bail; 2111 } 2112 qib_stats.sps_hwerrs++; 2113 2114 /* Always clear the error status register, except BIST fail */ 2115 qib_write_kreg(dd, kr_hwerrclear, hwerrs & 2116 ~HWE_MASK(PowerOnBISTFailed)); 2117 2118 hwerrs &= dd->cspec->hwerrmask; 2119 2120 /* no EEPROM logging, yet */ 2121 2122 if (hwerrs) 2123 qib_devinfo(dd->pcidev, 2124 "Hardware error: hwerr=0x%llx (cleared)\n", 2125 (unsigned long long) hwerrs); 2126 2127 ctrl = qib_read_kreg32(dd, kr_control); 2128 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { 2129 /* 2130 * No recovery yet... 2131 */ 2132 if ((hwerrs & ~HWE_MASK(LATriggered)) || 2133 dd->cspec->stay_in_freeze) { 2134 /* 2135 * If any set that we aren't ignoring only make the 2136 * complaint once, in case it's stuck or recurring, 2137 * and we get here multiple times 2138 * Force link down, so switch knows, and 2139 * LEDs are turned off. 2140 */ 2141 if (dd->flags & QIB_INITTED) 2142 isfatal = 1; 2143 } else 2144 qib_7322_clear_freeze(dd); 2145 } 2146 2147 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) { 2148 isfatal = 1; 2149 strlcpy(msg, 2150 "[Memory BIST test failed, InfiniPath hardware unusable]", 2151 msgl); 2152 /* ignore from now on, so disable until driver reloaded */ 2153 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); 2154 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2155 } 2156 2157 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs); 2158 2159 /* Ignore esoteric PLL failures et al. */ 2160 2161 qib_dev_err(dd, "%s hardware error\n", msg); 2162 2163 if (hwerrs & 2164 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) | 2165 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) { 2166 int pidx = 0; 2167 int err; 2168 unsigned long flags; 2169 struct qib_pportdata *ppd = dd->pport; 2170 2171 for (; pidx < dd->num_pports; ++pidx, ppd++) { 2172 err = 0; 2173 if (pidx == 0 && (hwerrs & 2174 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0))) 2175 err++; 2176 if (pidx == 1 && (hwerrs & 2177 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) 2178 err++; 2179 if (err) { 2180 spin_lock_irqsave(&ppd->sdma_lock, flags); 2181 dump_sdma_7322_state(ppd); 2182 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 2183 } 2184 } 2185 } 2186 2187 if (isfatal && !dd->diag_client) { 2188 qib_dev_err(dd, 2189 "Fatal Hardware Error, no longer usable, SN %.16s\n", 2190 dd->serial); 2191 /* 2192 * for /sys status file and user programs to print; if no 2193 * trailing brace is copied, we'll know it was truncated. 2194 */ 2195 if (dd->freezemsg) 2196 snprintf(dd->freezemsg, dd->freezelen, 2197 "{%s}", msg); 2198 qib_disable_after_error(dd); 2199 } 2200 bail:; 2201 } 2202 2203 /** 2204 * qib_7322_init_hwerrors - enable hardware errors 2205 * @dd: the qlogic_ib device 2206 * 2207 * now that we have finished initializing everything that might reasonably 2208 * cause a hardware error, and cleared those errors bits as they occur, 2209 * we can enable hardware errors in the mask (potentially enabling 2210 * freeze mode), and enable hardware errors as errors (along with 2211 * everything else) in errormask 2212 */ 2213 static void qib_7322_init_hwerrors(struct qib_devdata *dd) 2214 { 2215 int pidx; 2216 u64 extsval; 2217 2218 extsval = qib_read_kreg64(dd, kr_extstatus); 2219 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED | 2220 QIB_EXTS_MEMBIST_ENDTEST))) 2221 qib_dev_err(dd, "MemBIST did not complete!\n"); 2222 2223 /* never clear BIST failure, so reported on each driver load */ 2224 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); 2225 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2226 2227 /* clear all */ 2228 qib_write_kreg(dd, kr_errclear, ~0ULL); 2229 /* enable errors that are masked, at least this first time. */ 2230 qib_write_kreg(dd, kr_errmask, ~0ULL); 2231 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); 2232 for (pidx = 0; pidx < dd->num_pports; ++pidx) 2233 if (dd->pport[pidx].link_speed_supported) 2234 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 2235 ~0ULL); 2236 } 2237 2238 /* 2239 * Disable and enable the armlaunch error. Used for PIO bandwidth testing 2240 * on chips that are count-based, rather than trigger-based. There is no 2241 * reference counting, but that's also fine, given the intended use. 2242 * Only chip-specific because it's all register accesses 2243 */ 2244 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) 2245 { 2246 if (enable) { 2247 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); 2248 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; 2249 } else 2250 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; 2251 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 2252 } 2253 2254 /* 2255 * Formerly took parameter <which> in pre-shifted, 2256 * pre-merged form with LinkCmd and LinkInitCmd 2257 * together, and assuming the zero was NOP. 2258 */ 2259 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 2260 u16 linitcmd) 2261 { 2262 u64 mod_wd; 2263 struct qib_devdata *dd = ppd->dd; 2264 unsigned long flags; 2265 2266 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) { 2267 /* 2268 * If we are told to disable, note that so link-recovery 2269 * code does not attempt to bring us back up. 2270 * Also reset everything that we can, so we start 2271 * completely clean when re-enabled (before we 2272 * actually issue the disable to the IBC) 2273 */ 2274 qib_7322_mini_pcs_reset(ppd); 2275 spin_lock_irqsave(&ppd->lflags_lock, flags); 2276 ppd->lflags |= QIBL_IB_LINK_DISABLED; 2277 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2278 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) { 2279 /* 2280 * Any other linkinitcmd will lead to LINKDOWN and then 2281 * to INIT (if all is well), so clear flag to let 2282 * link-recovery code attempt to bring us back up. 2283 */ 2284 spin_lock_irqsave(&ppd->lflags_lock, flags); 2285 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; 2286 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2287 /* 2288 * Clear status change interrupt reduction so the 2289 * new state is seen. 2290 */ 2291 ppd->cpspec->ibcctrl_a &= 2292 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 2293 } 2294 2295 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) | 2296 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2297 2298 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a | 2299 mod_wd); 2300 /* write to chip to prevent back-to-back writes of ibc reg */ 2301 qib_write_kreg(dd, kr_scratch, 0); 2302 2303 } 2304 2305 /* 2306 * The total RCV buffer memory is 64KB, used for both ports, and is 2307 * in units of 64 bytes (same as IB flow control credit unit). 2308 * The consumedVL unit in the same registers are in 32 byte units! 2309 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks, 2310 * and we can therefore allocate just 9 IB credits for 2 VL15 packets 2311 * in krp_rxcreditvl15, rather than 10. 2312 */ 2313 #define RCV_BUF_UNITSZ 64 2314 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) 2315 2316 static void set_vls(struct qib_pportdata *ppd) 2317 { 2318 int i, numvls, totcred, cred_vl, vl0extra; 2319 struct qib_devdata *dd = ppd->dd; 2320 u64 val; 2321 2322 numvls = qib_num_vls(ppd->vls_operational); 2323 2324 /* 2325 * Set up per-VL credits. Below is kluge based on these assumptions: 2326 * 1) port is disabled at the time early_init is called. 2327 * 2) give VL15 17 credits, for two max-plausible packets. 2328 * 3) Give VL0-N the rest, with any rounding excess used for VL0 2329 */ 2330 /* 2 VL15 packets @ 288 bytes each (including IB headers) */ 2331 totcred = NUM_RCV_BUF_UNITS(dd); 2332 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ; 2333 totcred -= cred_vl; 2334 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl); 2335 cred_vl = totcred / numvls; 2336 vl0extra = totcred - cred_vl * numvls; 2337 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra); 2338 for (i = 1; i < numvls; i++) 2339 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl); 2340 for (; i < 8; i++) /* no buffer space for other VLs */ 2341 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 2342 2343 /* Notify IBC that credits need to be recalculated */ 2344 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 2345 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2346 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2347 qib_write_kreg(dd, kr_scratch, 0ULL); 2348 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2349 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2350 2351 for (i = 0; i < numvls; i++) 2352 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i); 2353 val = qib_read_kreg_port(ppd, krp_rxcreditvl15); 2354 2355 /* Change the number of operational VLs */ 2356 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a & 2357 ~SYM_MASK(IBCCtrlA_0, NumVLane)) | 2358 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); 2359 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2360 qib_write_kreg(dd, kr_scratch, 0ULL); 2361 } 2362 2363 /* 2364 * The code that deals with actual SerDes is in serdes_7322_init(). 2365 * Compared to the code for iba7220, it is minimal. 2366 */ 2367 static int serdes_7322_init(struct qib_pportdata *ppd); 2368 2369 /** 2370 * qib_7322_bringup_serdes - bring up the serdes 2371 * @ppd: physical port on the qlogic_ib device 2372 */ 2373 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd) 2374 { 2375 struct qib_devdata *dd = ppd->dd; 2376 u64 val, guid, ibc; 2377 unsigned long flags; 2378 int ret = 0; 2379 2380 /* 2381 * SerDes model not in Pd, but still need to 2382 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere 2383 * eventually. 2384 */ 2385 /* Put IBC in reset, sends disabled (should be in reset already) */ 2386 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2387 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2388 qib_write_kreg(dd, kr_scratch, 0ULL); 2389 2390 /* ensure previous Tx parameters are not still forced */ 2391 qib_write_kreg_port(ppd, krp_tx_deemph_override, 2392 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 2393 reset_tx_deemphasis_override)); 2394 2395 if (qib_compat_ddr_negotiate) { 2396 ppd->cpspec->ibdeltainprog = 1; 2397 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 2398 crp_ibsymbolerr); 2399 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 2400 crp_iblinkerrrecov); 2401 } 2402 2403 /* flowcontrolwatermark is in units of KBytes */ 2404 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); 2405 /* 2406 * Flow control is sent this often, even if no changes in 2407 * buffer space occur. Units are 128ns for this chip. 2408 * Set to 3usec. 2409 */ 2410 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); 2411 /* max error tolerance */ 2412 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 2413 /* IB credit flow control. */ 2414 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); 2415 /* 2416 * set initial max size pkt IBC will send, including ICRC; it's the 2417 * PIO buffer size in dwords, less 1; also see qib_set_mtu() 2418 */ 2419 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << 2420 SYM_LSB(IBCCtrlA_0, MaxPktLen); 2421 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */ 2422 2423 /* 2424 * Reset the PCS interface to the serdes (and also ibc, which is still 2425 * in reset from above). Writes new value of ibcctrl_a as last step. 2426 */ 2427 qib_7322_mini_pcs_reset(ppd); 2428 2429 if (!ppd->cpspec->ibcctrl_b) { 2430 unsigned lse = ppd->link_speed_enabled; 2431 2432 /* 2433 * Not on re-init after reset, establish shadow 2434 * and force initial config. 2435 */ 2436 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd, 2437 krp_ibcctrl_b); 2438 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR | 2439 IBA7322_IBC_SPEED_DDR | 2440 IBA7322_IBC_SPEED_SDR | 2441 IBA7322_IBC_WIDTH_AUTONEG | 2442 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); 2443 if (lse & (lse - 1)) /* Muliple speeds enabled */ 2444 ppd->cpspec->ibcctrl_b |= 2445 (lse << IBA7322_IBC_SPEED_LSB) | 2446 IBA7322_IBC_IBTA_1_2_MASK | 2447 IBA7322_IBC_MAX_SPEED_MASK; 2448 else 2449 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ? 2450 IBA7322_IBC_SPEED_QDR | 2451 IBA7322_IBC_IBTA_1_2_MASK : 2452 (lse == QIB_IB_DDR) ? 2453 IBA7322_IBC_SPEED_DDR : 2454 IBA7322_IBC_SPEED_SDR; 2455 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) == 2456 (IB_WIDTH_1X | IB_WIDTH_4X)) 2457 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG; 2458 else 2459 ppd->cpspec->ibcctrl_b |= 2460 ppd->link_width_enabled == IB_WIDTH_4X ? 2461 IBA7322_IBC_WIDTH_4X_ONLY : 2462 IBA7322_IBC_WIDTH_1X_ONLY; 2463 2464 /* always enable these on driver reload, not sticky */ 2465 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK | 2466 IBA7322_IBC_HRTBT_MASK); 2467 } 2468 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 2469 2470 /* setup so we have more time at CFGTEST to change H1 */ 2471 val = qib_read_kreg_port(ppd, krp_ibcctrl_c); 2472 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); 2473 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); 2474 qib_write_kreg_port(ppd, krp_ibcctrl_c, val); 2475 2476 serdes_7322_init(ppd); 2477 2478 guid = be64_to_cpu(ppd->guid); 2479 if (!guid) { 2480 if (dd->base_guid) 2481 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; 2482 ppd->guid = cpu_to_be64(guid); 2483 } 2484 2485 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid); 2486 /* write to chip to prevent back-to-back writes of ibc reg */ 2487 qib_write_kreg(dd, kr_scratch, 0); 2488 2489 /* Enable port */ 2490 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); 2491 set_vls(ppd); 2492 2493 /* initially come up DISABLED, without sending anything. */ 2494 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << 2495 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2496 qib_write_kreg_port(ppd, krp_ibcctrl_a, val); 2497 qib_write_kreg(dd, kr_scratch, 0ULL); 2498 /* clear the linkinit cmds */ 2499 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); 2500 2501 /* be paranoid against later code motion, etc. */ 2502 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 2503 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); 2504 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 2505 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 2506 2507 /* Also enable IBSTATUSCHG interrupt. */ 2508 val = qib_read_kreg_port(ppd, krp_errmask); 2509 qib_write_kreg_port(ppd, krp_errmask, 2510 val | ERR_MASK_N(IBStatusChanged)); 2511 2512 /* Always zero until we start messing with SerDes for real */ 2513 return ret; 2514 } 2515 2516 /** 2517 * qib_7322_quiet_serdes - set serdes to txidle 2518 * @dd: the qlogic_ib device 2519 * Called when driver is being unloaded 2520 */ 2521 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd) 2522 { 2523 u64 val; 2524 unsigned long flags; 2525 2526 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 2527 2528 spin_lock_irqsave(&ppd->lflags_lock, flags); 2529 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 2530 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2531 wake_up(&ppd->cpspec->autoneg_wait); 2532 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work); 2533 if (ppd->dd->cspec->r1) 2534 cancel_delayed_work_sync(&ppd->cpspec->ipg_work); 2535 2536 ppd->cpspec->chase_end = 0; 2537 if (ppd->cpspec->chase_timer.function) /* if initted */ 2538 del_timer_sync(&ppd->cpspec->chase_timer); 2539 2540 /* 2541 * Despite the name, actually disables IBC as well. Do it when 2542 * we are as sure as possible that no more packets can be 2543 * received, following the down and the PCS reset. 2544 * The actual disabling happens in qib_7322_mini_pci_reset(), 2545 * along with the PCS being reset. 2546 */ 2547 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2548 qib_7322_mini_pcs_reset(ppd); 2549 2550 /* 2551 * Update the adjusted counters so the adjustment persists 2552 * across driver reload. 2553 */ 2554 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || 2555 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) { 2556 struct qib_devdata *dd = ppd->dd; 2557 u64 diagc; 2558 2559 /* enable counter writes */ 2560 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); 2561 qib_write_kreg(dd, kr_hwdiagctrl, 2562 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); 2563 2564 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) { 2565 val = read_7322_creg32_port(ppd, crp_ibsymbolerr); 2566 if (ppd->cpspec->ibdeltainprog) 2567 val -= val - ppd->cpspec->ibsymsnap; 2568 val -= ppd->cpspec->ibsymdelta; 2569 write_7322_creg_port(ppd, crp_ibsymbolerr, val); 2570 } 2571 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) { 2572 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov); 2573 if (ppd->cpspec->ibdeltainprog) 2574 val -= val - ppd->cpspec->iblnkerrsnap; 2575 val -= ppd->cpspec->iblnkerrdelta; 2576 write_7322_creg_port(ppd, crp_iblinkerrrecov, val); 2577 } 2578 if (ppd->cpspec->iblnkdowndelta) { 2579 val = read_7322_creg32_port(ppd, crp_iblinkdown); 2580 val += ppd->cpspec->iblnkdowndelta; 2581 write_7322_creg_port(ppd, crp_iblinkdown, val); 2582 } 2583 /* 2584 * No need to save ibmalfdelta since IB perfcounters 2585 * are cleared on driver reload. 2586 */ 2587 2588 /* and disable counter writes */ 2589 qib_write_kreg(dd, kr_hwdiagctrl, diagc); 2590 } 2591 } 2592 2593 /** 2594 * qib_setup_7322_setextled - set the state of the two external LEDs 2595 * @ppd: physical port on the qlogic_ib device 2596 * @on: whether the link is up or not 2597 * 2598 * The exact combo of LEDs if on is true is determined by looking 2599 * at the ibcstatus. 2600 * 2601 * These LEDs indicate the physical and logical state of IB link. 2602 * For this chip (at least with recommended board pinouts), LED1 2603 * is Yellow (logical state) and LED2 is Green (physical state), 2604 * 2605 * Note: We try to match the Mellanox HCA LED behavior as best 2606 * we can. Green indicates physical link state is OK (something is 2607 * plugged in, and we can train). 2608 * Amber indicates the link is logically up (ACTIVE). 2609 * Mellanox further blinks the amber LED to indicate data packet 2610 * activity, but we have no hardware support for that, so it would 2611 * require waking up every 10-20 msecs and checking the counters 2612 * on the chip, and then turning the LED off if appropriate. That's 2613 * visible overhead, so not something we will do. 2614 */ 2615 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) 2616 { 2617 struct qib_devdata *dd = ppd->dd; 2618 u64 extctl, ledblink = 0, val; 2619 unsigned long flags; 2620 int yel, grn; 2621 2622 /* 2623 * The diags use the LED to indicate diag info, so we leave 2624 * the external LED alone when the diags are running. 2625 */ 2626 if (dd->diag_client) 2627 return; 2628 2629 /* Allow override of LED display for, e.g. Locating system in rack */ 2630 if (ppd->led_override) { 2631 grn = (ppd->led_override & QIB_LED_PHYS); 2632 yel = (ppd->led_override & QIB_LED_LOG); 2633 } else if (on) { 2634 val = qib_read_kreg_port(ppd, krp_ibcstatus_a); 2635 grn = qib_7322_phys_portstate(val) == 2636 IB_PHYSPORTSTATE_LINKUP; 2637 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE; 2638 } else { 2639 grn = 0; 2640 yel = 0; 2641 } 2642 2643 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2644 extctl = dd->cspec->extctrl & (ppd->port == 1 ? 2645 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK); 2646 if (grn) { 2647 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN; 2648 /* 2649 * Counts are in chip clock (4ns) periods. 2650 * This is 1/16 sec (66.6ms) on, 2651 * 3/16 sec (187.5 ms) off, with packets rcvd. 2652 */ 2653 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) | 2654 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT); 2655 } 2656 if (yel) 2657 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL; 2658 dd->cspec->extctrl = extctl; 2659 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 2660 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2661 2662 if (ledblink) /* blink the LED on packet receive */ 2663 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); 2664 } 2665 2666 #ifdef CONFIG_INFINIBAND_QIB_DCA 2667 2668 static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event) 2669 { 2670 switch (event) { 2671 case DCA_PROVIDER_ADD: 2672 if (dd->flags & QIB_DCA_ENABLED) 2673 break; 2674 if (!dca_add_requester(&dd->pcidev->dev)) { 2675 qib_devinfo(dd->pcidev, "DCA enabled\n"); 2676 dd->flags |= QIB_DCA_ENABLED; 2677 qib_setup_dca(dd); 2678 } 2679 break; 2680 case DCA_PROVIDER_REMOVE: 2681 if (dd->flags & QIB_DCA_ENABLED) { 2682 dca_remove_requester(&dd->pcidev->dev); 2683 dd->flags &= ~QIB_DCA_ENABLED; 2684 dd->cspec->dca_ctrl = 0; 2685 qib_write_kreg(dd, KREG_IDX(DCACtrlA), 2686 dd->cspec->dca_ctrl); 2687 } 2688 break; 2689 } 2690 return 0; 2691 } 2692 2693 static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu) 2694 { 2695 struct qib_devdata *dd = rcd->dd; 2696 struct qib_chip_specific *cspec = dd->cspec; 2697 2698 if (!(dd->flags & QIB_DCA_ENABLED)) 2699 return; 2700 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { 2701 const struct dca_reg_map *rmp; 2702 2703 cspec->rhdr_cpu[rcd->ctxt] = cpu; 2704 rmp = &dca_rcvhdr_reg_map[rcd->ctxt]; 2705 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; 2706 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= 2707 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb; 2708 qib_devinfo(dd->pcidev, 2709 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu, 2710 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); 2711 qib_write_kreg(dd, rmp->regno, 2712 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); 2713 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); 2714 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); 2715 } 2716 } 2717 2718 static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu) 2719 { 2720 struct qib_devdata *dd = ppd->dd; 2721 struct qib_chip_specific *cspec = dd->cspec; 2722 unsigned pidx = ppd->port - 1; 2723 2724 if (!(dd->flags & QIB_DCA_ENABLED)) 2725 return; 2726 if (cspec->sdma_cpu[pidx] != cpu) { 2727 cspec->sdma_cpu[pidx] = cpu; 2728 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? 2729 SYM_MASK(DCACtrlF, SendDma1DCAOPH) : 2730 SYM_MASK(DCACtrlF, SendDma0DCAOPH)); 2731 cspec->dca_rcvhdr_ctrl[4] |= 2732 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << 2733 (ppd->hw_pidx ? 2734 SYM_LSB(DCACtrlF, SendDma1DCAOPH) : 2735 SYM_LSB(DCACtrlF, SendDma0DCAOPH)); 2736 qib_devinfo(dd->pcidev, 2737 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu, 2738 (long long) cspec->dca_rcvhdr_ctrl[4]); 2739 qib_write_kreg(dd, KREG_IDX(DCACtrlF), 2740 cspec->dca_rcvhdr_ctrl[4]); 2741 cspec->dca_ctrl |= ppd->hw_pidx ? 2742 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) : 2743 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable); 2744 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); 2745 } 2746 } 2747 2748 static void qib_setup_dca(struct qib_devdata *dd) 2749 { 2750 struct qib_chip_specific *cspec = dd->cspec; 2751 int i; 2752 2753 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) 2754 cspec->rhdr_cpu[i] = -1; 2755 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) 2756 cspec->sdma_cpu[i] = -1; 2757 cspec->dca_rcvhdr_ctrl[0] = 2758 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) | 2759 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) | 2760 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) | 2761 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt)); 2762 cspec->dca_rcvhdr_ctrl[1] = 2763 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) | 2764 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) | 2765 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) | 2766 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt)); 2767 cspec->dca_rcvhdr_ctrl[2] = 2768 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) | 2769 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) | 2770 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) | 2771 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt)); 2772 cspec->dca_rcvhdr_ctrl[3] = 2773 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) | 2774 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) | 2775 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) | 2776 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt)); 2777 cspec->dca_rcvhdr_ctrl[4] = 2778 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) | 2779 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt)); 2780 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) 2781 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i, 2782 cspec->dca_rcvhdr_ctrl[i]); 2783 for (i = 0; i < cspec->num_msix_entries; i++) 2784 setup_dca_notifier(dd, i); 2785 } 2786 2787 static void qib_irq_notifier_notify(struct irq_affinity_notify *notify, 2788 const cpumask_t *mask) 2789 { 2790 struct qib_irq_notify *n = 2791 container_of(notify, struct qib_irq_notify, notify); 2792 int cpu = cpumask_first(mask); 2793 2794 if (n->rcv) { 2795 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; 2796 2797 qib_update_rhdrq_dca(rcd, cpu); 2798 } else { 2799 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; 2800 2801 qib_update_sdma_dca(ppd, cpu); 2802 } 2803 } 2804 2805 static void qib_irq_notifier_release(struct kref *ref) 2806 { 2807 struct qib_irq_notify *n = 2808 container_of(ref, struct qib_irq_notify, notify.kref); 2809 struct qib_devdata *dd; 2810 2811 if (n->rcv) { 2812 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; 2813 2814 dd = rcd->dd; 2815 } else { 2816 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; 2817 2818 dd = ppd->dd; 2819 } 2820 qib_devinfo(dd->pcidev, 2821 "release on HCA notify 0x%p n 0x%p\n", ref, n); 2822 kfree(n); 2823 } 2824 #endif 2825 2826 static void qib_7322_free_irq(struct qib_devdata *dd) 2827 { 2828 u64 intgranted; 2829 int i; 2830 2831 dd->cspec->main_int_mask = ~0ULL; 2832 2833 for (i = 0; i < dd->cspec->num_msix_entries; i++) { 2834 /* only free IRQs that were allocated */ 2835 if (dd->cspec->msix_entries[i].arg) { 2836 #ifdef CONFIG_INFINIBAND_QIB_DCA 2837 reset_dca_notifier(dd, i); 2838 #endif 2839 irq_set_affinity_hint(pci_irq_vector(dd->pcidev, i), 2840 NULL); 2841 free_cpumask_var(dd->cspec->msix_entries[i].mask); 2842 pci_free_irq(dd->pcidev, i, 2843 dd->cspec->msix_entries[i].arg); 2844 } 2845 } 2846 2847 /* If num_msix_entries was 0, disable the INTx IRQ */ 2848 if (!dd->cspec->num_msix_entries) 2849 pci_free_irq(dd->pcidev, 0, dd); 2850 else 2851 dd->cspec->num_msix_entries = 0; 2852 2853 pci_free_irq_vectors(dd->pcidev); 2854 2855 /* make sure no MSIx interrupts are left pending */ 2856 intgranted = qib_read_kreg64(dd, kr_intgranted); 2857 if (intgranted) 2858 qib_write_kreg(dd, kr_intgranted, intgranted); 2859 } 2860 2861 static void qib_setup_7322_cleanup(struct qib_devdata *dd) 2862 { 2863 int i; 2864 2865 #ifdef CONFIG_INFINIBAND_QIB_DCA 2866 if (dd->flags & QIB_DCA_ENABLED) { 2867 dca_remove_requester(&dd->pcidev->dev); 2868 dd->flags &= ~QIB_DCA_ENABLED; 2869 dd->cspec->dca_ctrl = 0; 2870 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); 2871 } 2872 #endif 2873 2874 qib_7322_free_irq(dd); 2875 kfree(dd->cspec->cntrs); 2876 kfree(dd->cspec->sendchkenable); 2877 kfree(dd->cspec->sendgrhchk); 2878 kfree(dd->cspec->sendibchk); 2879 kfree(dd->cspec->msix_entries); 2880 for (i = 0; i < dd->num_pports; i++) { 2881 unsigned long flags; 2882 u32 mask = QSFP_GPIO_MOD_PRS_N | 2883 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT); 2884 2885 kfree(dd->pport[i].cpspec->portcntrs); 2886 if (dd->flags & QIB_HAS_QSFP) { 2887 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2888 dd->cspec->gpio_mask &= ~mask; 2889 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 2890 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2891 } 2892 } 2893 } 2894 2895 /* handle SDMA interrupts */ 2896 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) 2897 { 2898 struct qib_pportdata *ppd0 = &dd->pport[0]; 2899 struct qib_pportdata *ppd1 = &dd->pport[1]; 2900 u64 intr0 = istat & (INT_MASK_P(SDma, 0) | 2901 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0)); 2902 u64 intr1 = istat & (INT_MASK_P(SDma, 1) | 2903 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1)); 2904 2905 if (intr0) 2906 qib_sdma_intr(ppd0); 2907 if (intr1) 2908 qib_sdma_intr(ppd1); 2909 2910 if (istat & INT_MASK_PM(SDmaCleanupDone, 0)) 2911 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started); 2912 if (istat & INT_MASK_PM(SDmaCleanupDone, 1)) 2913 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started); 2914 } 2915 2916 /* 2917 * Set or clear the Send buffer available interrupt enable bit. 2918 */ 2919 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) 2920 { 2921 unsigned long flags; 2922 2923 spin_lock_irqsave(&dd->sendctrl_lock, flags); 2924 if (needint) 2925 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); 2926 else 2927 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); 2928 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 2929 qib_write_kreg(dd, kr_scratch, 0ULL); 2930 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 2931 } 2932 2933 /* 2934 * Somehow got an interrupt with reserved bits set in interrupt status. 2935 * Print a message so we know it happened, then clear them. 2936 * keep mainline interrupt handler cache-friendly 2937 */ 2938 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) 2939 { 2940 u64 kills; 2941 char msg[128]; 2942 2943 kills = istat & ~QIB_I_BITSEXTANT; 2944 qib_dev_err(dd, 2945 "Clearing reserved interrupt(s) 0x%016llx: %s\n", 2946 (unsigned long long) kills, msg); 2947 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); 2948 } 2949 2950 /* keep mainline interrupt handler cache-friendly */ 2951 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) 2952 { 2953 u32 gpiostatus; 2954 int handled = 0; 2955 int pidx; 2956 2957 /* 2958 * Boards for this chip currently don't use GPIO interrupts, 2959 * so clear by writing GPIOstatus to GPIOclear, and complain 2960 * to developer. To avoid endless repeats, clear 2961 * the bits in the mask, since there is some kind of 2962 * programming error or chip problem. 2963 */ 2964 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); 2965 /* 2966 * In theory, writing GPIOstatus to GPIOclear could 2967 * have a bad side-effect on some diagnostic that wanted 2968 * to poll for a status-change, but the various shadows 2969 * make that problematic at best. Diags will just suppress 2970 * all GPIO interrupts during such tests. 2971 */ 2972 qib_write_kreg(dd, kr_gpio_clear, gpiostatus); 2973 /* 2974 * Check for QSFP MOD_PRS changes 2975 * only works for single port if IB1 != pidx1 2976 */ 2977 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); 2978 ++pidx) { 2979 struct qib_pportdata *ppd; 2980 struct qib_qsfp_data *qd; 2981 u32 mask; 2982 2983 if (!dd->pport[pidx].link_speed_supported) 2984 continue; 2985 mask = QSFP_GPIO_MOD_PRS_N; 2986 ppd = dd->pport + pidx; 2987 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 2988 if (gpiostatus & dd->cspec->gpio_mask & mask) { 2989 u64 pins; 2990 2991 qd = &ppd->cpspec->qsfp_data; 2992 gpiostatus &= ~mask; 2993 pins = qib_read_kreg64(dd, kr_extstatus); 2994 pins >>= SYM_LSB(EXTStatus, GPIOIn); 2995 if (!(pins & mask)) { 2996 ++handled; 2997 qd->t_insert = jiffies; 2998 queue_work(ib_wq, &qd->work); 2999 } 3000 } 3001 } 3002 3003 if (gpiostatus && !handled) { 3004 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); 3005 u32 gpio_irq = mask & gpiostatus; 3006 3007 /* 3008 * Clear any troublemakers, and update chip from shadow 3009 */ 3010 dd->cspec->gpio_mask &= ~gpio_irq; 3011 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 3012 } 3013 } 3014 3015 /* 3016 * Handle errors and unusual events first, separate function 3017 * to improve cache hits for fast path interrupt handling. 3018 */ 3019 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) 3020 { 3021 if (istat & ~QIB_I_BITSEXTANT) 3022 unknown_7322_ibits(dd, istat); 3023 if (istat & QIB_I_GPIO) 3024 unknown_7322_gpio_intr(dd); 3025 if (istat & QIB_I_C_ERROR) { 3026 qib_write_kreg(dd, kr_errmask, 0ULL); 3027 tasklet_schedule(&dd->error_tasklet); 3028 } 3029 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) 3030 handle_7322_p_errors(dd->rcd[0]->ppd); 3031 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) 3032 handle_7322_p_errors(dd->rcd[1]->ppd); 3033 } 3034 3035 /* 3036 * Dynamically adjust the rcv int timeout for a context based on incoming 3037 * packet rate. 3038 */ 3039 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts) 3040 { 3041 struct qib_devdata *dd = rcd->dd; 3042 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; 3043 3044 /* 3045 * Dynamically adjust idle timeout on chip 3046 * based on number of packets processed. 3047 */ 3048 if (npkts < rcv_int_count && timeout > 2) 3049 timeout >>= 1; 3050 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout) 3051 timeout = min(timeout << 1, rcv_int_timeout); 3052 else 3053 return; 3054 3055 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; 3056 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); 3057 } 3058 3059 /* 3060 * This is the main interrupt handler. 3061 * It will normally only be used for low frequency interrupts but may 3062 * have to handle all interrupts if INTx is enabled or fewer than normal 3063 * MSIx interrupts were allocated. 3064 * This routine should ignore the interrupt bits for any of the 3065 * dedicated MSIx handlers. 3066 */ 3067 static irqreturn_t qib_7322intr(int irq, void *data) 3068 { 3069 struct qib_devdata *dd = data; 3070 irqreturn_t ret; 3071 u64 istat; 3072 u64 ctxtrbits; 3073 u64 rmask; 3074 unsigned i; 3075 u32 npkts; 3076 3077 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { 3078 /* 3079 * This return value is not great, but we do not want the 3080 * interrupt core code to remove our interrupt handler 3081 * because we don't appear to be handling an interrupt 3082 * during a chip reset. 3083 */ 3084 ret = IRQ_HANDLED; 3085 goto bail; 3086 } 3087 3088 istat = qib_read_kreg64(dd, kr_intstatus); 3089 3090 if (unlikely(istat == ~0ULL)) { 3091 qib_bad_intrstatus(dd); 3092 qib_dev_err(dd, "Interrupt status all f's, skipping\n"); 3093 /* don't know if it was our interrupt or not */ 3094 ret = IRQ_NONE; 3095 goto bail; 3096 } 3097 3098 istat &= dd->cspec->main_int_mask; 3099 if (unlikely(!istat)) { 3100 /* already handled, or shared and not us */ 3101 ret = IRQ_NONE; 3102 goto bail; 3103 } 3104 3105 this_cpu_inc(*dd->int_counter); 3106 3107 /* handle "errors" of various kinds first, device ahead of port */ 3108 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO | 3109 QIB_I_C_ERROR | INT_MASK_P(Err, 0) | 3110 INT_MASK_P(Err, 1)))) 3111 unlikely_7322_intr(dd, istat); 3112 3113 /* 3114 * Clear the interrupt bits we found set, relatively early, so we 3115 * "know" know the chip will have seen this by the time we process 3116 * the queue, and will re-interrupt if necessary. The processor 3117 * itself won't take the interrupt again until we return. 3118 */ 3119 qib_write_kreg(dd, kr_intclear, istat); 3120 3121 /* 3122 * Handle kernel receive queues before checking for pio buffers 3123 * available since receives can overflow; piobuf waiters can afford 3124 * a few extra cycles, since they were waiting anyway. 3125 */ 3126 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK); 3127 if (ctxtrbits) { 3128 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) | 3129 (1ULL << QIB_I_RCVURG_LSB); 3130 for (i = 0; i < dd->first_user_ctxt; i++) { 3131 if (ctxtrbits & rmask) { 3132 ctxtrbits &= ~rmask; 3133 if (dd->rcd[i]) 3134 qib_kreceive(dd->rcd[i], NULL, &npkts); 3135 } 3136 rmask <<= 1; 3137 } 3138 if (ctxtrbits) { 3139 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) | 3140 (ctxtrbits >> QIB_I_RCVURG_LSB); 3141 qib_handle_urcv(dd, ctxtrbits); 3142 } 3143 } 3144 3145 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1))) 3146 sdma_7322_intr(dd, istat); 3147 3148 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) 3149 qib_ib_piobufavail(dd); 3150 3151 ret = IRQ_HANDLED; 3152 bail: 3153 return ret; 3154 } 3155 3156 /* 3157 * Dedicated receive packet available interrupt handler. 3158 */ 3159 static irqreturn_t qib_7322pintr(int irq, void *data) 3160 { 3161 struct qib_ctxtdata *rcd = data; 3162 struct qib_devdata *dd = rcd->dd; 3163 u32 npkts; 3164 3165 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3166 /* 3167 * This return value is not great, but we do not want the 3168 * interrupt core code to remove our interrupt handler 3169 * because we don't appear to be handling an interrupt 3170 * during a chip reset. 3171 */ 3172 return IRQ_HANDLED; 3173 3174 this_cpu_inc(*dd->int_counter); 3175 3176 /* Clear the interrupt bit we expect to be set. */ 3177 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | 3178 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); 3179 3180 qib_kreceive(rcd, NULL, &npkts); 3181 3182 return IRQ_HANDLED; 3183 } 3184 3185 /* 3186 * Dedicated Send buffer available interrupt handler. 3187 */ 3188 static irqreturn_t qib_7322bufavail(int irq, void *data) 3189 { 3190 struct qib_devdata *dd = data; 3191 3192 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3193 /* 3194 * This return value is not great, but we do not want the 3195 * interrupt core code to remove our interrupt handler 3196 * because we don't appear to be handling an interrupt 3197 * during a chip reset. 3198 */ 3199 return IRQ_HANDLED; 3200 3201 this_cpu_inc(*dd->int_counter); 3202 3203 /* Clear the interrupt bit we expect to be set. */ 3204 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); 3205 3206 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */ 3207 if (dd->flags & QIB_INITTED) 3208 qib_ib_piobufavail(dd); 3209 else 3210 qib_wantpiobuf_7322_intr(dd, 0); 3211 3212 return IRQ_HANDLED; 3213 } 3214 3215 /* 3216 * Dedicated Send DMA interrupt handler. 3217 */ 3218 static irqreturn_t sdma_intr(int irq, void *data) 3219 { 3220 struct qib_pportdata *ppd = data; 3221 struct qib_devdata *dd = ppd->dd; 3222 3223 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3224 /* 3225 * This return value is not great, but we do not want the 3226 * interrupt core code to remove our interrupt handler 3227 * because we don't appear to be handling an interrupt 3228 * during a chip reset. 3229 */ 3230 return IRQ_HANDLED; 3231 3232 this_cpu_inc(*dd->int_counter); 3233 3234 /* Clear the interrupt bit we expect to be set. */ 3235 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3236 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); 3237 qib_sdma_intr(ppd); 3238 3239 return IRQ_HANDLED; 3240 } 3241 3242 /* 3243 * Dedicated Send DMA idle interrupt handler. 3244 */ 3245 static irqreturn_t sdma_idle_intr(int irq, void *data) 3246 { 3247 struct qib_pportdata *ppd = data; 3248 struct qib_devdata *dd = ppd->dd; 3249 3250 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3251 /* 3252 * This return value is not great, but we do not want the 3253 * interrupt core code to remove our interrupt handler 3254 * because we don't appear to be handling an interrupt 3255 * during a chip reset. 3256 */ 3257 return IRQ_HANDLED; 3258 3259 this_cpu_inc(*dd->int_counter); 3260 3261 /* Clear the interrupt bit we expect to be set. */ 3262 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3263 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); 3264 qib_sdma_intr(ppd); 3265 3266 return IRQ_HANDLED; 3267 } 3268 3269 /* 3270 * Dedicated Send DMA progress interrupt handler. 3271 */ 3272 static irqreturn_t sdma_progress_intr(int irq, void *data) 3273 { 3274 struct qib_pportdata *ppd = data; 3275 struct qib_devdata *dd = ppd->dd; 3276 3277 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3278 /* 3279 * This return value is not great, but we do not want the 3280 * interrupt core code to remove our interrupt handler 3281 * because we don't appear to be handling an interrupt 3282 * during a chip reset. 3283 */ 3284 return IRQ_HANDLED; 3285 3286 this_cpu_inc(*dd->int_counter); 3287 3288 /* Clear the interrupt bit we expect to be set. */ 3289 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3290 INT_MASK_P(SDmaProgress, 1) : 3291 INT_MASK_P(SDmaProgress, 0)); 3292 qib_sdma_intr(ppd); 3293 3294 return IRQ_HANDLED; 3295 } 3296 3297 /* 3298 * Dedicated Send DMA cleanup interrupt handler. 3299 */ 3300 static irqreturn_t sdma_cleanup_intr(int irq, void *data) 3301 { 3302 struct qib_pportdata *ppd = data; 3303 struct qib_devdata *dd = ppd->dd; 3304 3305 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3306 /* 3307 * This return value is not great, but we do not want the 3308 * interrupt core code to remove our interrupt handler 3309 * because we don't appear to be handling an interrupt 3310 * during a chip reset. 3311 */ 3312 return IRQ_HANDLED; 3313 3314 this_cpu_inc(*dd->int_counter); 3315 3316 /* Clear the interrupt bit we expect to be set. */ 3317 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3318 INT_MASK_PM(SDmaCleanupDone, 1) : 3319 INT_MASK_PM(SDmaCleanupDone, 0)); 3320 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started); 3321 3322 return IRQ_HANDLED; 3323 } 3324 3325 #ifdef CONFIG_INFINIBAND_QIB_DCA 3326 3327 static void reset_dca_notifier(struct qib_devdata *dd, int msixnum) 3328 { 3329 if (!dd->cspec->msix_entries[msixnum].dca) 3330 return; 3331 3332 qib_devinfo(dd->pcidev, "Disabling notifier on HCA %d irq %d\n", 3333 dd->unit, pci_irq_vector(dd->pcidev, msixnum)); 3334 irq_set_affinity_notifier(pci_irq_vector(dd->pcidev, msixnum), NULL); 3335 dd->cspec->msix_entries[msixnum].notifier = NULL; 3336 } 3337 3338 static void setup_dca_notifier(struct qib_devdata *dd, int msixnum) 3339 { 3340 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum]; 3341 struct qib_irq_notify *n; 3342 3343 if (!m->dca) 3344 return; 3345 n = kzalloc(sizeof(*n), GFP_KERNEL); 3346 if (n) { 3347 int ret; 3348 3349 m->notifier = n; 3350 n->notify.irq = pci_irq_vector(dd->pcidev, msixnum); 3351 n->notify.notify = qib_irq_notifier_notify; 3352 n->notify.release = qib_irq_notifier_release; 3353 n->arg = m->arg; 3354 n->rcv = m->rcv; 3355 qib_devinfo(dd->pcidev, 3356 "set notifier irq %d rcv %d notify %p\n", 3357 n->notify.irq, n->rcv, &n->notify); 3358 ret = irq_set_affinity_notifier( 3359 n->notify.irq, 3360 &n->notify); 3361 if (ret) { 3362 m->notifier = NULL; 3363 kfree(n); 3364 } 3365 } 3366 } 3367 3368 #endif 3369 3370 /* 3371 * Set up our chip-specific interrupt handler. 3372 * The interrupt type has already been setup, so 3373 * we just need to do the registration and error checking. 3374 * If we are using MSIx interrupts, we may fall back to 3375 * INTx later, if the interrupt handler doesn't get called 3376 * within 1/2 second (see verify_interrupt()). 3377 */ 3378 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) 3379 { 3380 int ret, i, msixnum; 3381 u64 redirect[6]; 3382 u64 mask; 3383 const struct cpumask *local_mask; 3384 int firstcpu, secondcpu = 0, currrcvcpu = 0; 3385 3386 if (!dd->num_pports) 3387 return; 3388 3389 if (clearpend) { 3390 /* 3391 * if not switching interrupt types, be sure interrupts are 3392 * disabled, and then clear anything pending at this point, 3393 * because we are starting clean. 3394 */ 3395 qib_7322_set_intr_state(dd, 0); 3396 3397 /* clear the reset error, init error/hwerror mask */ 3398 qib_7322_init_hwerrors(dd); 3399 3400 /* clear any interrupt bits that might be set */ 3401 qib_write_kreg(dd, kr_intclear, ~0ULL); 3402 3403 /* make sure no pending MSIx intr, and clear diag reg */ 3404 qib_write_kreg(dd, kr_intgranted, ~0ULL); 3405 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); 3406 } 3407 3408 if (!dd->cspec->num_msix_entries) { 3409 /* Try to get INTx interrupt */ 3410 try_intx: 3411 ret = pci_request_irq(dd->pcidev, 0, qib_7322intr, NULL, dd, 3412 QIB_DRV_NAME); 3413 if (ret) { 3414 qib_dev_err( 3415 dd, 3416 "Couldn't setup INTx interrupt (irq=%d): %d\n", 3417 pci_irq_vector(dd->pcidev, 0), ret); 3418 return; 3419 } 3420 dd->cspec->main_int_mask = ~0ULL; 3421 return; 3422 } 3423 3424 /* Try to get MSIx interrupts */ 3425 memset(redirect, 0, sizeof(redirect)); 3426 mask = ~0ULL; 3427 msixnum = 0; 3428 local_mask = cpumask_of_pcibus(dd->pcidev->bus); 3429 firstcpu = cpumask_first(local_mask); 3430 if (firstcpu >= nr_cpu_ids || 3431 cpumask_weight(local_mask) == num_online_cpus()) { 3432 local_mask = topology_core_cpumask(0); 3433 firstcpu = cpumask_first(local_mask); 3434 } 3435 if (firstcpu < nr_cpu_ids) { 3436 secondcpu = cpumask_next(firstcpu, local_mask); 3437 if (secondcpu >= nr_cpu_ids) 3438 secondcpu = firstcpu; 3439 currrcvcpu = secondcpu; 3440 } 3441 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { 3442 irq_handler_t handler; 3443 void *arg; 3444 int lsb, reg, sh; 3445 #ifdef CONFIG_INFINIBAND_QIB_DCA 3446 int dca = 0; 3447 #endif 3448 if (i < ARRAY_SIZE(irq_table)) { 3449 if (irq_table[i].port) { 3450 /* skip if for a non-configured port */ 3451 if (irq_table[i].port > dd->num_pports) 3452 continue; 3453 arg = dd->pport + irq_table[i].port - 1; 3454 } else 3455 arg = dd; 3456 #ifdef CONFIG_INFINIBAND_QIB_DCA 3457 dca = irq_table[i].dca; 3458 #endif 3459 lsb = irq_table[i].lsb; 3460 handler = irq_table[i].handler; 3461 ret = pci_request_irq(dd->pcidev, msixnum, handler, 3462 NULL, arg, QIB_DRV_NAME "%d%s", 3463 dd->unit, 3464 irq_table[i].name); 3465 } else { 3466 unsigned ctxt; 3467 3468 ctxt = i - ARRAY_SIZE(irq_table); 3469 /* per krcvq context receive interrupt */ 3470 arg = dd->rcd[ctxt]; 3471 if (!arg) 3472 continue; 3473 if (qib_krcvq01_no_msi && ctxt < 2) 3474 continue; 3475 #ifdef CONFIG_INFINIBAND_QIB_DCA 3476 dca = 1; 3477 #endif 3478 lsb = QIB_I_RCVAVAIL_LSB + ctxt; 3479 handler = qib_7322pintr; 3480 ret = pci_request_irq(dd->pcidev, msixnum, handler, 3481 NULL, arg, 3482 QIB_DRV_NAME "%d (kctx)", 3483 dd->unit); 3484 } 3485 3486 if (ret) { 3487 /* 3488 * Shouldn't happen since the enable said we could 3489 * have as many as we are trying to setup here. 3490 */ 3491 qib_dev_err(dd, 3492 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n", 3493 msixnum, 3494 pci_irq_vector(dd->pcidev, msixnum), 3495 ret); 3496 qib_7322_free_irq(dd); 3497 pci_alloc_irq_vectors(dd->pcidev, 1, 1, 3498 PCI_IRQ_LEGACY); 3499 goto try_intx; 3500 } 3501 dd->cspec->msix_entries[msixnum].arg = arg; 3502 #ifdef CONFIG_INFINIBAND_QIB_DCA 3503 dd->cspec->msix_entries[msixnum].dca = dca; 3504 dd->cspec->msix_entries[msixnum].rcv = 3505 handler == qib_7322pintr; 3506 #endif 3507 if (lsb >= 0) { 3508 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG; 3509 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) * 3510 SYM_LSB(IntRedirect0, vec1); 3511 mask &= ~(1ULL << lsb); 3512 redirect[reg] |= ((u64) msixnum) << sh; 3513 } 3514 qib_read_kreg64(dd, 2 * msixnum + 1 + 3515 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3516 if (firstcpu < nr_cpu_ids && 3517 zalloc_cpumask_var( 3518 &dd->cspec->msix_entries[msixnum].mask, 3519 GFP_KERNEL)) { 3520 if (handler == qib_7322pintr) { 3521 cpumask_set_cpu(currrcvcpu, 3522 dd->cspec->msix_entries[msixnum].mask); 3523 currrcvcpu = cpumask_next(currrcvcpu, 3524 local_mask); 3525 if (currrcvcpu >= nr_cpu_ids) 3526 currrcvcpu = secondcpu; 3527 } else { 3528 cpumask_set_cpu(firstcpu, 3529 dd->cspec->msix_entries[msixnum].mask); 3530 } 3531 irq_set_affinity_hint( 3532 pci_irq_vector(dd->pcidev, msixnum), 3533 dd->cspec->msix_entries[msixnum].mask); 3534 } 3535 msixnum++; 3536 } 3537 /* Initialize the vector mapping */ 3538 for (i = 0; i < ARRAY_SIZE(redirect); i++) 3539 qib_write_kreg(dd, kr_intredirect + i, redirect[i]); 3540 dd->cspec->main_int_mask = mask; 3541 tasklet_init(&dd->error_tasklet, qib_error_tasklet, 3542 (unsigned long)dd); 3543 } 3544 3545 /** 3546 * qib_7322_boardname - fill in the board name and note features 3547 * @dd: the qlogic_ib device 3548 * 3549 * info will be based on the board revision register 3550 */ 3551 static unsigned qib_7322_boardname(struct qib_devdata *dd) 3552 { 3553 /* Will need enumeration of board-types here */ 3554 u32 boardid; 3555 unsigned int features = DUAL_PORT_CAP; 3556 3557 boardid = SYM_FIELD(dd->revision, Revision, BoardID); 3558 3559 switch (boardid) { 3560 case 0: 3561 dd->boardname = "InfiniPath_QLE7342_Emulation"; 3562 break; 3563 case 1: 3564 dd->boardname = "InfiniPath_QLE7340"; 3565 dd->flags |= QIB_HAS_QSFP; 3566 features = PORT_SPD_CAP; 3567 break; 3568 case 2: 3569 dd->boardname = "InfiniPath_QLE7342"; 3570 dd->flags |= QIB_HAS_QSFP; 3571 break; 3572 case 3: 3573 dd->boardname = "InfiniPath_QMI7342"; 3574 break; 3575 case 4: 3576 dd->boardname = "InfiniPath_Unsupported7342"; 3577 qib_dev_err(dd, "Unsupported version of QMH7342\n"); 3578 features = 0; 3579 break; 3580 case BOARD_QMH7342: 3581 dd->boardname = "InfiniPath_QMH7342"; 3582 features = 0x24; 3583 break; 3584 case BOARD_QME7342: 3585 dd->boardname = "InfiniPath_QME7342"; 3586 break; 3587 case 8: 3588 dd->boardname = "InfiniPath_QME7362"; 3589 dd->flags |= QIB_HAS_QSFP; 3590 break; 3591 case BOARD_QMH7360: 3592 dd->boardname = "Intel IB QDR 1P FLR-QSFP Adptr"; 3593 dd->flags |= QIB_HAS_QSFP; 3594 break; 3595 case 15: 3596 dd->boardname = "InfiniPath_QLE7342_TEST"; 3597 dd->flags |= QIB_HAS_QSFP; 3598 break; 3599 default: 3600 dd->boardname = "InfiniPath_QLE73xy_UNKNOWN"; 3601 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); 3602 break; 3603 } 3604 dd->board_atten = 1; /* index into txdds_Xdr */ 3605 3606 snprintf(dd->boardversion, sizeof(dd->boardversion), 3607 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n", 3608 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, 3609 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), 3610 dd->majrev, dd->minrev, 3611 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); 3612 3613 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) { 3614 qib_devinfo(dd->pcidev, 3615 "IB%u: Forced to single port mode by module parameter\n", 3616 dd->unit); 3617 features &= PORT_SPD_CAP; 3618 } 3619 3620 return features; 3621 } 3622 3623 /* 3624 * This routine sleeps, so it can only be called from user context, not 3625 * from interrupt context. 3626 */ 3627 static int qib_do_7322_reset(struct qib_devdata *dd) 3628 { 3629 u64 val; 3630 u64 *msix_vecsave = NULL; 3631 int i, msix_entries, ret = 1; 3632 u16 cmdval; 3633 u8 int_line, clinesz; 3634 unsigned long flags; 3635 3636 /* Use dev_err so it shows up in logs, etc. */ 3637 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); 3638 3639 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); 3640 3641 msix_entries = dd->cspec->num_msix_entries; 3642 3643 /* no interrupts till re-initted */ 3644 qib_7322_set_intr_state(dd, 0); 3645 3646 qib_7322_free_irq(dd); 3647 3648 if (msix_entries) { 3649 /* can be up to 512 bytes, too big for stack */ 3650 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries, 3651 sizeof(u64), 3652 GFP_KERNEL); 3653 } 3654 3655 /* 3656 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector 3657 * info that is set up by the BIOS, so we have to save and restore 3658 * it ourselves. There is some risk something could change it, 3659 * after we save it, but since we have disabled the MSIx, it 3660 * shouldn't be touched... 3661 */ 3662 for (i = 0; i < msix_entries; i++) { 3663 u64 vecaddr, vecdata; 3664 3665 vecaddr = qib_read_kreg64(dd, 2 * i + 3666 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3667 vecdata = qib_read_kreg64(dd, 1 + 2 * i + 3668 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3669 if (msix_vecsave) { 3670 msix_vecsave[2 * i] = vecaddr; 3671 /* save it without the masked bit set */ 3672 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL; 3673 } 3674 } 3675 3676 dd->pport->cpspec->ibdeltainprog = 0; 3677 dd->pport->cpspec->ibsymdelta = 0; 3678 dd->pport->cpspec->iblnkerrdelta = 0; 3679 dd->pport->cpspec->ibmalfdelta = 0; 3680 /* so we check interrupts work again */ 3681 dd->z_int_counter = qib_int_counter(dd); 3682 3683 /* 3684 * Keep chip from being accessed until we are ready. Use 3685 * writeq() directly, to allow the write even though QIB_PRESENT 3686 * isn't set. 3687 */ 3688 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); 3689 dd->flags |= QIB_DOING_RESET; 3690 val = dd->control | QLOGIC_IB_C_RESET; 3691 writeq(val, &dd->kregbase[kr_control]); 3692 3693 for (i = 1; i <= 5; i++) { 3694 /* 3695 * Allow MBIST, etc. to complete; longer on each retry. 3696 * We sometimes get machine checks from bus timeout if no 3697 * response, so for now, make it *really* long. 3698 */ 3699 msleep(1000 + (1 + i) * 3000); 3700 3701 qib_pcie_reenable(dd, cmdval, int_line, clinesz); 3702 3703 /* 3704 * Use readq directly, so we don't need to mark it as PRESENT 3705 * until we get a successful indication that all is well. 3706 */ 3707 val = readq(&dd->kregbase[kr_revision]); 3708 if (val == dd->revision) 3709 break; 3710 if (i == 5) { 3711 qib_dev_err(dd, 3712 "Failed to initialize after reset, unusable\n"); 3713 ret = 0; 3714 goto bail; 3715 } 3716 } 3717 3718 dd->flags |= QIB_PRESENT; /* it's back */ 3719 3720 if (msix_entries) { 3721 /* restore the MSIx vector address and data if saved above */ 3722 for (i = 0; i < msix_entries; i++) { 3723 if (!msix_vecsave || !msix_vecsave[2 * i]) 3724 continue; 3725 qib_write_kreg(dd, 2 * i + 3726 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3727 msix_vecsave[2 * i]); 3728 qib_write_kreg(dd, 1 + 2 * i + 3729 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3730 msix_vecsave[1 + 2 * i]); 3731 } 3732 } 3733 3734 /* initialize the remaining registers. */ 3735 for (i = 0; i < dd->num_pports; ++i) 3736 write_7322_init_portregs(&dd->pport[i]); 3737 write_7322_initregs(dd); 3738 3739 if (qib_pcie_params(dd, dd->lbus_width, &msix_entries)) 3740 qib_dev_err(dd, 3741 "Reset failed to setup PCIe or interrupts; continuing anyway\n"); 3742 3743 dd->cspec->num_msix_entries = msix_entries; 3744 qib_setup_7322_interrupt(dd, 1); 3745 3746 for (i = 0; i < dd->num_pports; ++i) { 3747 struct qib_pportdata *ppd = &dd->pport[i]; 3748 3749 spin_lock_irqsave(&ppd->lflags_lock, flags); 3750 ppd->lflags |= QIBL_IB_FORCE_NOTIFY; 3751 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 3752 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3753 } 3754 3755 bail: 3756 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ 3757 kfree(msix_vecsave); 3758 return ret; 3759 } 3760 3761 /** 3762 * qib_7322_put_tid - write a TID to the chip 3763 * @dd: the qlogic_ib device 3764 * @tidptr: pointer to the expected TID (in chip) to update 3765 * @tidtype: 0 for eager, 1 for expected 3766 * @pa: physical address of in memory buffer; tidinvalid if freeing 3767 */ 3768 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, 3769 u32 type, unsigned long pa) 3770 { 3771 if (!(dd->flags & QIB_PRESENT)) 3772 return; 3773 if (pa != dd->tidinvalid) { 3774 u64 chippa = pa >> IBA7322_TID_PA_SHIFT; 3775 3776 /* paranoia checks */ 3777 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) { 3778 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", 3779 pa); 3780 return; 3781 } 3782 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) { 3783 qib_dev_err(dd, 3784 "Physical page address 0x%lx larger than supported\n", 3785 pa); 3786 return; 3787 } 3788 3789 if (type == RCVHQ_RCV_TYPE_EAGER) 3790 chippa |= dd->tidtemplate; 3791 else /* for now, always full 4KB page */ 3792 chippa |= IBA7322_TID_SZ_4K; 3793 pa = chippa; 3794 } 3795 writeq(pa, tidptr); 3796 mmiowb(); 3797 } 3798 3799 /** 3800 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager 3801 * @dd: the qlogic_ib device 3802 * @ctxt: the ctxt 3803 * 3804 * clear all TID entries for a ctxt, expected and eager. 3805 * Used from qib_close(). 3806 */ 3807 static void qib_7322_clear_tids(struct qib_devdata *dd, 3808 struct qib_ctxtdata *rcd) 3809 { 3810 u64 __iomem *tidbase; 3811 unsigned long tidinv; 3812 u32 ctxt; 3813 int i; 3814 3815 if (!dd->kregbase || !rcd) 3816 return; 3817 3818 ctxt = rcd->ctxt; 3819 3820 tidinv = dd->tidinvalid; 3821 tidbase = (u64 __iomem *) 3822 ((char __iomem *) dd->kregbase + 3823 dd->rcvtidbase + 3824 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); 3825 3826 for (i = 0; i < dd->rcvtidcnt; i++) 3827 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, 3828 tidinv); 3829 3830 tidbase = (u64 __iomem *) 3831 ((char __iomem *) dd->kregbase + 3832 dd->rcvegrbase + 3833 rcd->rcvegr_tid_base * sizeof(*tidbase)); 3834 3835 for (i = 0; i < rcd->rcvegrcnt; i++) 3836 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, 3837 tidinv); 3838 } 3839 3840 /** 3841 * qib_7322_tidtemplate - setup constants for TID updates 3842 * @dd: the qlogic_ib device 3843 * 3844 * We setup stuff that we use a lot, to avoid calculating each time 3845 */ 3846 static void qib_7322_tidtemplate(struct qib_devdata *dd) 3847 { 3848 /* 3849 * For now, we always allocate 4KB buffers (at init) so we can 3850 * receive max size packets. We may want a module parameter to 3851 * specify 2KB or 4KB and/or make it per port instead of per device 3852 * for those who want to reduce memory footprint. Note that the 3853 * rcvhdrentsize size must be large enough to hold the largest 3854 * IB header (currently 96 bytes) that we expect to handle (plus of 3855 * course the 2 dwords of RHF). 3856 */ 3857 if (dd->rcvegrbufsize == 2048) 3858 dd->tidtemplate = IBA7322_TID_SZ_2K; 3859 else if (dd->rcvegrbufsize == 4096) 3860 dd->tidtemplate = IBA7322_TID_SZ_4K; 3861 dd->tidinvalid = 0; 3862 } 3863 3864 /** 3865 * qib_init_7322_get_base_info - set chip-specific flags for user code 3866 * @rcd: the qlogic_ib ctxt 3867 * @kbase: qib_base_info pointer 3868 * 3869 * We set the PCIE flag because the lower bandwidth on PCIe vs 3870 * HyperTransport can affect some user packet algorithims. 3871 */ 3872 3873 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd, 3874 struct qib_base_info *kinfo) 3875 { 3876 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP | 3877 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL | 3878 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA; 3879 if (rcd->dd->cspec->r1) 3880 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK; 3881 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) 3882 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER; 3883 3884 return 0; 3885 } 3886 3887 static struct qib_message_header * 3888 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) 3889 { 3890 u32 offset = qib_hdrget_offset(rhf_addr); 3891 3892 return (struct qib_message_header *) 3893 (rhf_addr - dd->rhf_offset + offset); 3894 } 3895 3896 /* 3897 * Configure number of contexts. 3898 */ 3899 static void qib_7322_config_ctxts(struct qib_devdata *dd) 3900 { 3901 unsigned long flags; 3902 u32 nchipctxts; 3903 3904 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); 3905 dd->cspec->numctxts = nchipctxts; 3906 if (qib_n_krcv_queues > 1 && dd->num_pports) { 3907 dd->first_user_ctxt = NUM_IB_PORTS + 3908 (qib_n_krcv_queues - 1) * dd->num_pports; 3909 if (dd->first_user_ctxt > nchipctxts) 3910 dd->first_user_ctxt = nchipctxts; 3911 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; 3912 } else { 3913 dd->first_user_ctxt = NUM_IB_PORTS; 3914 dd->n_krcv_queues = 1; 3915 } 3916 3917 if (!qib_cfgctxts) { 3918 int nctxts = dd->first_user_ctxt + num_online_cpus(); 3919 3920 if (nctxts <= 6) 3921 dd->ctxtcnt = 6; 3922 else if (nctxts <= 10) 3923 dd->ctxtcnt = 10; 3924 else if (nctxts <= nchipctxts) 3925 dd->ctxtcnt = nchipctxts; 3926 } else if (qib_cfgctxts < dd->num_pports) 3927 dd->ctxtcnt = dd->num_pports; 3928 else if (qib_cfgctxts <= nchipctxts) 3929 dd->ctxtcnt = qib_cfgctxts; 3930 if (!dd->ctxtcnt) /* none of the above, set to max */ 3931 dd->ctxtcnt = nchipctxts; 3932 3933 /* 3934 * Chip can be configured for 6, 10, or 18 ctxts, and choice 3935 * affects number of eager TIDs per ctxt (1K, 2K, 4K). 3936 * Lock to be paranoid about later motion, etc. 3937 */ 3938 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 3939 if (dd->ctxtcnt > 10) 3940 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); 3941 else if (dd->ctxtcnt > 6) 3942 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); 3943 /* else configure for default 6 receive ctxts */ 3944 3945 /* The XRC opcode is 5. */ 3946 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); 3947 3948 /* 3949 * RcvCtrl *must* be written here so that the 3950 * chip understands how to change rcvegrcnt below. 3951 */ 3952 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 3953 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 3954 3955 /* kr_rcvegrcnt changes based on the number of contexts enabled */ 3956 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3957 if (qib_rcvhdrcnt) 3958 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); 3959 else 3960 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, 3961 dd->num_pports > 1 ? 1024U : 2048U); 3962 } 3963 3964 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) 3965 { 3966 3967 int lsb, ret = 0; 3968 u64 maskr; /* right-justified mask */ 3969 3970 switch (which) { 3971 3972 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */ 3973 ret = ppd->link_width_enabled; 3974 goto done; 3975 3976 case QIB_IB_CFG_LWID: /* Get currently active Link-width */ 3977 ret = ppd->link_width_active; 3978 goto done; 3979 3980 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */ 3981 ret = ppd->link_speed_enabled; 3982 goto done; 3983 3984 case QIB_IB_CFG_SPD: /* Get current Link spd */ 3985 ret = ppd->link_speed_active; 3986 goto done; 3987 3988 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */ 3989 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3990 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3991 break; 3992 3993 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */ 3994 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3995 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3996 break; 3997 3998 case QIB_IB_CFG_LINKLATENCY: 3999 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 4000 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); 4001 goto done; 4002 4003 case QIB_IB_CFG_OP_VLS: 4004 ret = ppd->vls_operational; 4005 goto done; 4006 4007 case QIB_IB_CFG_VL_HIGH_CAP: 4008 ret = 16; 4009 goto done; 4010 4011 case QIB_IB_CFG_VL_LOW_CAP: 4012 ret = 16; 4013 goto done; 4014 4015 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 4016 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 4017 OverrunThreshold); 4018 goto done; 4019 4020 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 4021 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 4022 PhyerrThreshold); 4023 goto done; 4024 4025 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 4026 /* will only take effect when the link state changes */ 4027 ret = (ppd->cpspec->ibcctrl_a & 4028 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? 4029 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL; 4030 goto done; 4031 4032 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */ 4033 lsb = IBA7322_IBC_HRTBT_LSB; 4034 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 4035 break; 4036 4037 case QIB_IB_CFG_PMA_TICKS: 4038 /* 4039 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs 4040 * Since the clock is always 250MHz, the value is 3, 1 or 0. 4041 */ 4042 if (ppd->link_speed_active == QIB_IB_QDR) 4043 ret = 3; 4044 else if (ppd->link_speed_active == QIB_IB_DDR) 4045 ret = 1; 4046 else 4047 ret = 0; 4048 goto done; 4049 4050 default: 4051 ret = -EINVAL; 4052 goto done; 4053 } 4054 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr); 4055 done: 4056 return ret; 4057 } 4058 4059 /* 4060 * Below again cribbed liberally from older version. Do not lean 4061 * heavily on it. 4062 */ 4063 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB 4064 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \ 4065 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16)) 4066 4067 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) 4068 { 4069 struct qib_devdata *dd = ppd->dd; 4070 u64 maskr; /* right-justified mask */ 4071 int lsb, ret = 0; 4072 u16 lcmd, licmd; 4073 unsigned long flags; 4074 4075 switch (which) { 4076 case QIB_IB_CFG_LIDLMC: 4077 /* 4078 * Set LID and LMC. Combined to avoid possible hazard 4079 * caller puts LMC in 16MSbits, DLID in 16LSbits of val 4080 */ 4081 lsb = IBA7322_IBC_DLIDLMC_SHIFT; 4082 maskr = IBA7322_IBC_DLIDLMC_MASK; 4083 /* 4084 * For header-checking, the SLID in the packet will 4085 * be masked with SendIBSLMCMask, and compared 4086 * with SendIBSLIDAssignMask. Make sure we do not 4087 * set any bits not covered by the mask, or we get 4088 * false-positives. 4089 */ 4090 qib_write_kreg_port(ppd, krp_sendslid, 4091 val & (val >> 16) & SendIBSLIDAssignMask); 4092 qib_write_kreg_port(ppd, krp_sendslidmask, 4093 (val >> 16) & SendIBSLMCMask); 4094 break; 4095 4096 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */ 4097 ppd->link_width_enabled = val; 4098 /* convert IB value to chip register value */ 4099 if (val == IB_WIDTH_1X) 4100 val = 0; 4101 else if (val == IB_WIDTH_4X) 4102 val = 1; 4103 else 4104 val = 3; 4105 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS); 4106 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); 4107 break; 4108 4109 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */ 4110 /* 4111 * As with width, only write the actual register if the 4112 * link is currently down, otherwise takes effect on next 4113 * link change. Since setting is being explicitly requested 4114 * (via MAD or sysfs), clear autoneg failure status if speed 4115 * autoneg is enabled. 4116 */ 4117 ppd->link_speed_enabled = val; 4118 val <<= IBA7322_IBC_SPEED_LSB; 4119 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK | 4120 IBA7322_IBC_MAX_SPEED_MASK; 4121 if (val & (val - 1)) { 4122 /* Muliple speeds enabled */ 4123 val |= IBA7322_IBC_IBTA_1_2_MASK | 4124 IBA7322_IBC_MAX_SPEED_MASK; 4125 spin_lock_irqsave(&ppd->lflags_lock, flags); 4126 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 4127 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 4128 } else if (val & IBA7322_IBC_SPEED_QDR) 4129 val |= IBA7322_IBC_IBTA_1_2_MASK; 4130 /* IBTA 1.2 mode + min/max + speed bits are contiguous */ 4131 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); 4132 break; 4133 4134 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */ 4135 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 4136 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 4137 break; 4138 4139 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */ 4140 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 4141 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 4142 break; 4143 4144 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 4145 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 4146 OverrunThreshold); 4147 if (maskr != val) { 4148 ppd->cpspec->ibcctrl_a &= 4149 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); 4150 ppd->cpspec->ibcctrl_a |= (u64) val << 4151 SYM_LSB(IBCCtrlA_0, OverrunThreshold); 4152 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4153 ppd->cpspec->ibcctrl_a); 4154 qib_write_kreg(dd, kr_scratch, 0ULL); 4155 } 4156 goto bail; 4157 4158 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 4159 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 4160 PhyerrThreshold); 4161 if (maskr != val) { 4162 ppd->cpspec->ibcctrl_a &= 4163 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); 4164 ppd->cpspec->ibcctrl_a |= (u64) val << 4165 SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 4166 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4167 ppd->cpspec->ibcctrl_a); 4168 qib_write_kreg(dd, kr_scratch, 0ULL); 4169 } 4170 goto bail; 4171 4172 case QIB_IB_CFG_PKEYS: /* update pkeys */ 4173 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | 4174 ((u64) ppd->pkeys[2] << 32) | 4175 ((u64) ppd->pkeys[3] << 48); 4176 qib_write_kreg_port(ppd, krp_partitionkey, maskr); 4177 goto bail; 4178 4179 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 4180 /* will only take effect when the link state changes */ 4181 if (val == IB_LINKINITCMD_POLL) 4182 ppd->cpspec->ibcctrl_a &= 4183 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 4184 else /* SLEEP */ 4185 ppd->cpspec->ibcctrl_a |= 4186 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 4187 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 4188 qib_write_kreg(dd, kr_scratch, 0ULL); 4189 goto bail; 4190 4191 case QIB_IB_CFG_MTU: /* update the MTU in IBC */ 4192 /* 4193 * Update our housekeeping variables, and set IBC max 4194 * size, same as init code; max IBC is max we allow in 4195 * buffer, less the qword pbc, plus 1 for ICRC, in dwords 4196 * Set even if it's unchanged, print debug message only 4197 * on changes. 4198 */ 4199 val = (ppd->ibmaxlen >> 2) + 1; 4200 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); 4201 ppd->cpspec->ibcctrl_a |= (u64)val << 4202 SYM_LSB(IBCCtrlA_0, MaxPktLen); 4203 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4204 ppd->cpspec->ibcctrl_a); 4205 qib_write_kreg(dd, kr_scratch, 0ULL); 4206 goto bail; 4207 4208 case QIB_IB_CFG_LSTATE: /* set the IB link state */ 4209 switch (val & 0xffff0000) { 4210 case IB_LINKCMD_DOWN: 4211 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN; 4212 ppd->cpspec->ibmalfusesnap = 1; 4213 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 4214 crp_errlink); 4215 if (!ppd->cpspec->ibdeltainprog && 4216 qib_compat_ddr_negotiate) { 4217 ppd->cpspec->ibdeltainprog = 1; 4218 ppd->cpspec->ibsymsnap = 4219 read_7322_creg32_port(ppd, 4220 crp_ibsymbolerr); 4221 ppd->cpspec->iblnkerrsnap = 4222 read_7322_creg32_port(ppd, 4223 crp_iblinkerrrecov); 4224 } 4225 break; 4226 4227 case IB_LINKCMD_ARMED: 4228 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED; 4229 if (ppd->cpspec->ibmalfusesnap) { 4230 ppd->cpspec->ibmalfusesnap = 0; 4231 ppd->cpspec->ibmalfdelta += 4232 read_7322_creg32_port(ppd, 4233 crp_errlink) - 4234 ppd->cpspec->ibmalfsnap; 4235 } 4236 break; 4237 4238 case IB_LINKCMD_ACTIVE: 4239 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE; 4240 break; 4241 4242 default: 4243 ret = -EINVAL; 4244 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); 4245 goto bail; 4246 } 4247 switch (val & 0xffff) { 4248 case IB_LINKINITCMD_NOP: 4249 licmd = 0; 4250 break; 4251 4252 case IB_LINKINITCMD_POLL: 4253 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL; 4254 break; 4255 4256 case IB_LINKINITCMD_SLEEP: 4257 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP; 4258 break; 4259 4260 case IB_LINKINITCMD_DISABLE: 4261 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE; 4262 ppd->cpspec->chase_end = 0; 4263 /* 4264 * stop state chase counter and timer, if running. 4265 * wait forpending timer, but don't clear .data (ppd)! 4266 */ 4267 if (ppd->cpspec->chase_timer.expires) { 4268 del_timer_sync(&ppd->cpspec->chase_timer); 4269 ppd->cpspec->chase_timer.expires = 0; 4270 } 4271 break; 4272 4273 default: 4274 ret = -EINVAL; 4275 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", 4276 val & 0xffff); 4277 goto bail; 4278 } 4279 qib_set_ib_7322_lstate(ppd, lcmd, licmd); 4280 goto bail; 4281 4282 case QIB_IB_CFG_OP_VLS: 4283 if (ppd->vls_operational != val) { 4284 ppd->vls_operational = val; 4285 set_vls(ppd); 4286 } 4287 goto bail; 4288 4289 case QIB_IB_CFG_VL_HIGH_LIMIT: 4290 qib_write_kreg_port(ppd, krp_highprio_limit, val); 4291 goto bail; 4292 4293 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */ 4294 if (val > 3) { 4295 ret = -EINVAL; 4296 goto bail; 4297 } 4298 lsb = IBA7322_IBC_HRTBT_LSB; 4299 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 4300 break; 4301 4302 case QIB_IB_CFG_PORT: 4303 /* val is the port number of the switch we are connected to. */ 4304 if (ppd->dd->cspec->r1) { 4305 cancel_delayed_work(&ppd->cpspec->ipg_work); 4306 ppd->cpspec->ipg_tries = 0; 4307 } 4308 goto bail; 4309 4310 default: 4311 ret = -EINVAL; 4312 goto bail; 4313 } 4314 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb); 4315 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); 4316 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 4317 qib_write_kreg(dd, kr_scratch, 0); 4318 bail: 4319 return ret; 4320 } 4321 4322 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what) 4323 { 4324 int ret = 0; 4325 u64 val, ctrlb; 4326 4327 /* only IBC loopback, may add serdes and xgxs loopbacks later */ 4328 if (!strncmp(what, "ibc", 3)) { 4329 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, 4330 Loopback); 4331 val = 0; /* disable heart beat, so link will come up */ 4332 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", 4333 ppd->dd->unit, ppd->port); 4334 } else if (!strncmp(what, "off", 3)) { 4335 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, 4336 Loopback); 4337 /* enable heart beat again */ 4338 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB; 4339 qib_devinfo(ppd->dd->pcidev, 4340 "Disabling IB%u:%u IBC loopback (normal)\n", 4341 ppd->dd->unit, ppd->port); 4342 } else 4343 ret = -EINVAL; 4344 if (!ret) { 4345 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4346 ppd->cpspec->ibcctrl_a); 4347 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK 4348 << IBA7322_IBC_HRTBT_LSB); 4349 ppd->cpspec->ibcctrl_b = ctrlb | val; 4350 qib_write_kreg_port(ppd, krp_ibcctrl_b, 4351 ppd->cpspec->ibcctrl_b); 4352 qib_write_kreg(ppd->dd, kr_scratch, 0); 4353 } 4354 return ret; 4355 } 4356 4357 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4358 struct ib_vl_weight_elem *vl) 4359 { 4360 unsigned i; 4361 4362 for (i = 0; i < 16; i++, regno++, vl++) { 4363 u32 val = qib_read_kreg_port(ppd, regno); 4364 4365 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & 4366 SYM_RMASK(LowPriority0_0, VirtualLane); 4367 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & 4368 SYM_RMASK(LowPriority0_0, Weight); 4369 } 4370 } 4371 4372 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4373 struct ib_vl_weight_elem *vl) 4374 { 4375 unsigned i; 4376 4377 for (i = 0; i < 16; i++, regno++, vl++) { 4378 u64 val; 4379 4380 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << 4381 SYM_LSB(LowPriority0_0, VirtualLane)) | 4382 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) << 4383 SYM_LSB(LowPriority0_0, Weight)); 4384 qib_write_kreg_port(ppd, regno, val); 4385 } 4386 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { 4387 struct qib_devdata *dd = ppd->dd; 4388 unsigned long flags; 4389 4390 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4391 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); 4392 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4393 qib_write_kreg(dd, kr_scratch, 0); 4394 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4395 } 4396 } 4397 4398 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t) 4399 { 4400 switch (which) { 4401 case QIB_IB_TBL_VL_HIGH_ARB: 4402 get_vl_weights(ppd, krp_highprio_0, t); 4403 break; 4404 4405 case QIB_IB_TBL_VL_LOW_ARB: 4406 get_vl_weights(ppd, krp_lowprio_0, t); 4407 break; 4408 4409 default: 4410 return -EINVAL; 4411 } 4412 return 0; 4413 } 4414 4415 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t) 4416 { 4417 switch (which) { 4418 case QIB_IB_TBL_VL_HIGH_ARB: 4419 set_vl_weights(ppd, krp_highprio_0, t); 4420 break; 4421 4422 case QIB_IB_TBL_VL_LOW_ARB: 4423 set_vl_weights(ppd, krp_lowprio_0, t); 4424 break; 4425 4426 default: 4427 return -EINVAL; 4428 } 4429 return 0; 4430 } 4431 4432 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, 4433 u32 updegr, u32 egrhd, u32 npkts) 4434 { 4435 /* 4436 * Need to write timeout register before updating rcvhdrhead to ensure 4437 * that the timer is enabled on reception of a packet. 4438 */ 4439 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT) 4440 adjust_rcv_timeout(rcd, npkts); 4441 if (updegr) 4442 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); 4443 mmiowb(); 4444 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4445 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4446 mmiowb(); 4447 } 4448 4449 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd) 4450 { 4451 u32 head, tail; 4452 4453 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); 4454 if (rcd->rcvhdrtail_kvaddr) 4455 tail = qib_get_rcvhdrtail(rcd); 4456 else 4457 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); 4458 return head == tail; 4459 } 4460 4461 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4462 QIB_RCVCTRL_CTXT_DIS | \ 4463 QIB_RCVCTRL_TIDFLOW_ENB | \ 4464 QIB_RCVCTRL_TIDFLOW_DIS | \ 4465 QIB_RCVCTRL_TAILUPD_ENB | \ 4466 QIB_RCVCTRL_TAILUPD_DIS | \ 4467 QIB_RCVCTRL_INTRAVAIL_ENB | \ 4468 QIB_RCVCTRL_INTRAVAIL_DIS | \ 4469 QIB_RCVCTRL_BP_ENB | \ 4470 QIB_RCVCTRL_BP_DIS) 4471 4472 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4473 QIB_RCVCTRL_CTXT_DIS | \ 4474 QIB_RCVCTRL_PKEY_DIS | \ 4475 QIB_RCVCTRL_PKEY_ENB) 4476 4477 /* 4478 * Modify the RCVCTRL register in chip-specific way. This 4479 * is a function because bit positions and (future) register 4480 * location is chip-specifc, but the needed operations are 4481 * generic. <op> is a bit-mask because we often want to 4482 * do multiple modifications. 4483 */ 4484 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, 4485 int ctxt) 4486 { 4487 struct qib_devdata *dd = ppd->dd; 4488 struct qib_ctxtdata *rcd; 4489 u64 mask, val; 4490 unsigned long flags; 4491 4492 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 4493 4494 if (op & QIB_RCVCTRL_TIDFLOW_ENB) 4495 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); 4496 if (op & QIB_RCVCTRL_TIDFLOW_DIS) 4497 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); 4498 if (op & QIB_RCVCTRL_TAILUPD_ENB) 4499 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4500 if (op & QIB_RCVCTRL_TAILUPD_DIS) 4501 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); 4502 if (op & QIB_RCVCTRL_PKEY_ENB) 4503 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4504 if (op & QIB_RCVCTRL_PKEY_DIS) 4505 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4506 if (ctxt < 0) { 4507 mask = (1ULL << dd->ctxtcnt) - 1; 4508 rcd = NULL; 4509 } else { 4510 mask = (1ULL << ctxt); 4511 rcd = dd->rcd[ctxt]; 4512 } 4513 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) { 4514 ppd->p_rcvctrl |= 4515 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4516 if (!(dd->flags & QIB_NODMA_RTAIL)) { 4517 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */ 4518 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4519 } 4520 /* Write these registers before the context is enabled. */ 4521 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 4522 rcd->rcvhdrqtailaddr_phys); 4523 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 4524 rcd->rcvhdrq_phys); 4525 rcd->seq_cnt = 1; 4526 } 4527 if (op & QIB_RCVCTRL_CTXT_DIS) 4528 ppd->p_rcvctrl &= 4529 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4530 if (op & QIB_RCVCTRL_BP_ENB) 4531 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); 4532 if (op & QIB_RCVCTRL_BP_DIS) 4533 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); 4534 if (op & QIB_RCVCTRL_INTRAVAIL_ENB) 4535 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); 4536 if (op & QIB_RCVCTRL_INTRAVAIL_DIS) 4537 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); 4538 /* 4539 * Decide which registers to write depending on the ops enabled. 4540 * Special case is "flush" (no bits set at all) 4541 * which needs to write both. 4542 */ 4543 if (op == 0 || (op & RCVCTRL_COMMON_MODS)) 4544 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 4545 if (op == 0 || (op & RCVCTRL_PORT_MODS)) 4546 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 4547 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { 4548 /* 4549 * Init the context registers also; if we were 4550 * disabled, tail and head should both be zero 4551 * already from the enable, but since we don't 4552 * know, we have to do it explicitly. 4553 */ 4554 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); 4555 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); 4556 4557 /* be sure enabling write seen; hd/tl should be 0 */ 4558 (void) qib_read_kreg32(dd, kr_scratch); 4559 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); 4560 dd->rcd[ctxt]->head = val; 4561 /* If kctxt, interrupt on next receive. */ 4562 if (ctxt < dd->first_user_ctxt) 4563 val |= dd->rhdrhead_intr_off; 4564 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4565 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && 4566 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { 4567 /* arm rcv interrupt */ 4568 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; 4569 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4570 } 4571 if (op & QIB_RCVCTRL_CTXT_DIS) { 4572 unsigned f; 4573 4574 /* Now that the context is disabled, clear these registers. */ 4575 if (ctxt >= 0) { 4576 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); 4577 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); 4578 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4579 qib_write_ureg(dd, ur_rcvflowtable + f, 4580 TIDFLOW_ERRBITS, ctxt); 4581 } else { 4582 unsigned i; 4583 4584 for (i = 0; i < dd->cfgctxts; i++) { 4585 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, 4586 i, 0); 4587 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); 4588 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4589 qib_write_ureg(dd, ur_rcvflowtable + f, 4590 TIDFLOW_ERRBITS, i); 4591 } 4592 } 4593 } 4594 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 4595 } 4596 4597 /* 4598 * Modify the SENDCTRL register in chip-specific way. This 4599 * is a function where there are multiple such registers with 4600 * slightly different layouts. 4601 * The chip doesn't allow back-to-back sendctrl writes, so write 4602 * the scratch register after writing sendctrl. 4603 * 4604 * Which register is written depends on the operation. 4605 * Most operate on the common register, while 4606 * SEND_ENB and SEND_DIS operate on the per-port ones. 4607 * SEND_ENB is included in common because it can change SPCL_TRIG 4608 */ 4609 #define SENDCTRL_COMMON_MODS (\ 4610 QIB_SENDCTRL_CLEAR | \ 4611 QIB_SENDCTRL_AVAIL_DIS | \ 4612 QIB_SENDCTRL_AVAIL_ENB | \ 4613 QIB_SENDCTRL_AVAIL_BLIP | \ 4614 QIB_SENDCTRL_DISARM | \ 4615 QIB_SENDCTRL_DISARM_ALL | \ 4616 QIB_SENDCTRL_SEND_ENB) 4617 4618 #define SENDCTRL_PORT_MODS (\ 4619 QIB_SENDCTRL_CLEAR | \ 4620 QIB_SENDCTRL_SEND_ENB | \ 4621 QIB_SENDCTRL_SEND_DIS | \ 4622 QIB_SENDCTRL_FLUSH) 4623 4624 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op) 4625 { 4626 struct qib_devdata *dd = ppd->dd; 4627 u64 tmp_dd_sendctrl; 4628 unsigned long flags; 4629 4630 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4631 4632 /* First the dd ones that are "sticky", saved in shadow */ 4633 if (op & QIB_SENDCTRL_CLEAR) 4634 dd->sendctrl = 0; 4635 if (op & QIB_SENDCTRL_AVAIL_DIS) 4636 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4637 else if (op & QIB_SENDCTRL_AVAIL_ENB) { 4638 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); 4639 if (dd->flags & QIB_USE_SPCL_TRIG) 4640 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); 4641 } 4642 4643 /* Then the ppd ones that are "sticky", saved in shadow */ 4644 if (op & QIB_SENDCTRL_SEND_DIS) 4645 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 4646 else if (op & QIB_SENDCTRL_SEND_ENB) 4647 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 4648 4649 if (op & QIB_SENDCTRL_DISARM_ALL) { 4650 u32 i, last; 4651 4652 tmp_dd_sendctrl = dd->sendctrl; 4653 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 4654 /* 4655 * Disarm any buffers that are not yet launched, 4656 * disabling updates until done. 4657 */ 4658 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4659 for (i = 0; i < last; i++) { 4660 qib_write_kreg(dd, kr_sendctrl, 4661 tmp_dd_sendctrl | 4662 SYM_MASK(SendCtrl, Disarm) | i); 4663 qib_write_kreg(dd, kr_scratch, 0); 4664 } 4665 } 4666 4667 if (op & QIB_SENDCTRL_FLUSH) { 4668 u64 tmp_ppd_sendctrl = ppd->p_sendctrl; 4669 4670 /* 4671 * Now drain all the fifos. The Abort bit should never be 4672 * needed, so for now, at least, we don't use it. 4673 */ 4674 tmp_ppd_sendctrl |= 4675 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | 4676 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | 4677 SYM_MASK(SendCtrl_0, TxeBypassIbc); 4678 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl); 4679 qib_write_kreg(dd, kr_scratch, 0); 4680 } 4681 4682 tmp_dd_sendctrl = dd->sendctrl; 4683 4684 if (op & QIB_SENDCTRL_DISARM) 4685 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | 4686 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) << 4687 SYM_LSB(SendCtrl, DisarmSendBuf)); 4688 if ((op & QIB_SENDCTRL_AVAIL_BLIP) && 4689 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) 4690 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4691 4692 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) { 4693 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); 4694 qib_write_kreg(dd, kr_scratch, 0); 4695 } 4696 4697 if (op == 0 || (op & SENDCTRL_PORT_MODS)) { 4698 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4699 qib_write_kreg(dd, kr_scratch, 0); 4700 } 4701 4702 if (op & QIB_SENDCTRL_AVAIL_BLIP) { 4703 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 4704 qib_write_kreg(dd, kr_scratch, 0); 4705 } 4706 4707 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4708 4709 if (op & QIB_SENDCTRL_FLUSH) { 4710 u32 v; 4711 /* 4712 * ensure writes have hit chip, then do a few 4713 * more reads, to allow DMA of pioavail registers 4714 * to occur, so in-memory copy is in sync with 4715 * the chip. Not always safe to sleep. 4716 */ 4717 v = qib_read_kreg32(dd, kr_scratch); 4718 qib_write_kreg(dd, kr_scratch, v); 4719 v = qib_read_kreg32(dd, kr_scratch); 4720 qib_write_kreg(dd, kr_scratch, v); 4721 qib_read_kreg32(dd, kr_scratch); 4722 } 4723 } 4724 4725 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */ 4726 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */ 4727 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */ 4728 4729 /** 4730 * qib_portcntr_7322 - read a per-port chip counter 4731 * @ppd: the qlogic_ib pport 4732 * @creg: the counter to read (not a chip offset) 4733 */ 4734 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) 4735 { 4736 struct qib_devdata *dd = ppd->dd; 4737 u64 ret = 0ULL; 4738 u16 creg; 4739 /* 0xffff for unimplemented or synthesized counters */ 4740 static const u32 xlator[] = { 4741 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG, 4742 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG, 4743 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount, 4744 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount, 4745 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount, 4746 [QIBPORTCNTR_SENDSTALL] = crp_sendstall, 4747 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG, 4748 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount, 4749 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount, 4750 [QIBPORTCNTR_RCVEBP] = crp_rcvebp, 4751 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl, 4752 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG, 4753 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */ 4754 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr, 4755 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr, 4756 [QIBPORTCNTR_ERRICRC] = crp_erricrc, 4757 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc, 4758 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc, 4759 [QIBPORTCNTR_BADFORMAT] = crp_badformat, 4760 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen, 4761 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr, 4762 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen, 4763 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl, 4764 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl, 4765 [QIBPORTCNTR_ERRLINK] = crp_errlink, 4766 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown, 4767 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov, 4768 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr, 4769 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt, 4770 [QIBPORTCNTR_ERRPKEY] = crp_errpkey, 4771 /* 4772 * the next 3 aren't really counters, but were implemented 4773 * as counters in older chips, so still get accessed as 4774 * though they were counters from this code. 4775 */ 4776 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval, 4777 [QIBPORTCNTR_PSSTART] = krp_psstart, 4778 [QIBPORTCNTR_PSSTAT] = krp_psstat, 4779 /* pseudo-counter, summed for all ports */ 4780 [QIBPORTCNTR_KHDROVFL] = 0xffff, 4781 }; 4782 4783 if (reg >= ARRAY_SIZE(xlator)) { 4784 qib_devinfo(ppd->dd->pcidev, 4785 "Unimplemented portcounter %u\n", reg); 4786 goto done; 4787 } 4788 creg = xlator[reg] & _PORT_CNTR_IDXMASK; 4789 4790 /* handle non-counters and special cases first */ 4791 if (reg == QIBPORTCNTR_KHDROVFL) { 4792 int i; 4793 4794 /* sum over all kernel contexts (skip if mini_init) */ 4795 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { 4796 struct qib_ctxtdata *rcd = dd->rcd[i]; 4797 4798 if (!rcd || rcd->ppd != ppd) 4799 continue; 4800 ret += read_7322_creg32(dd, cr_base_egrovfl + i); 4801 } 4802 goto done; 4803 } else if (reg == QIBPORTCNTR_RXDROPPKT) { 4804 /* 4805 * Used as part of the synthesis of port_rcv_errors 4806 * in the verbs code for IBTA counters. Not needed for 7322, 4807 * because all the errors are already counted by other cntrs. 4808 */ 4809 goto done; 4810 } else if (reg == QIBPORTCNTR_PSINTERVAL || 4811 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) { 4812 /* were counters in older chips, now per-port kernel regs */ 4813 ret = qib_read_kreg_port(ppd, creg); 4814 goto done; 4815 } 4816 4817 /* 4818 * Only fast increment counters are 64 bits; use 32 bit reads to 4819 * avoid two independent reads when on Opteron. 4820 */ 4821 if (xlator[reg] & _PORT_64BIT_FLAG) 4822 ret = read_7322_creg_port(ppd, creg); 4823 else 4824 ret = read_7322_creg32_port(ppd, creg); 4825 if (creg == crp_ibsymbolerr) { 4826 if (ppd->cpspec->ibdeltainprog) 4827 ret -= ret - ppd->cpspec->ibsymsnap; 4828 ret -= ppd->cpspec->ibsymdelta; 4829 } else if (creg == crp_iblinkerrrecov) { 4830 if (ppd->cpspec->ibdeltainprog) 4831 ret -= ret - ppd->cpspec->iblnkerrsnap; 4832 ret -= ppd->cpspec->iblnkerrdelta; 4833 } else if (creg == crp_errlink) 4834 ret -= ppd->cpspec->ibmalfdelta; 4835 else if (creg == crp_iblinkdown) 4836 ret += ppd->cpspec->iblnkdowndelta; 4837 done: 4838 return ret; 4839 } 4840 4841 /* 4842 * Device counter names (not port-specific), one line per stat, 4843 * single string. Used by utilities like ipathstats to print the stats 4844 * in a way which works for different versions of drivers, without changing 4845 * the utility. Names need to be 12 chars or less (w/o newline), for proper 4846 * display by utility. 4847 * Non-error counters are first. 4848 * Start of "error" conters is indicated by a leading "E " on the first 4849 * "error" counter, and doesn't count in label length. 4850 * The EgrOvfl list needs to be last so we truncate them at the configured 4851 * context count for the device. 4852 * cntr7322indices contains the corresponding register indices. 4853 */ 4854 static const char cntr7322names[] = 4855 "Interrupts\n" 4856 "HostBusStall\n" 4857 "E RxTIDFull\n" 4858 "RxTIDInvalid\n" 4859 "RxTIDFloDrop\n" /* 7322 only */ 4860 "Ctxt0EgrOvfl\n" 4861 "Ctxt1EgrOvfl\n" 4862 "Ctxt2EgrOvfl\n" 4863 "Ctxt3EgrOvfl\n" 4864 "Ctxt4EgrOvfl\n" 4865 "Ctxt5EgrOvfl\n" 4866 "Ctxt6EgrOvfl\n" 4867 "Ctxt7EgrOvfl\n" 4868 "Ctxt8EgrOvfl\n" 4869 "Ctxt9EgrOvfl\n" 4870 "Ctx10EgrOvfl\n" 4871 "Ctx11EgrOvfl\n" 4872 "Ctx12EgrOvfl\n" 4873 "Ctx13EgrOvfl\n" 4874 "Ctx14EgrOvfl\n" 4875 "Ctx15EgrOvfl\n" 4876 "Ctx16EgrOvfl\n" 4877 "Ctx17EgrOvfl\n" 4878 ; 4879 4880 static const u32 cntr7322indices[] = { 4881 cr_lbint | _PORT_64BIT_FLAG, 4882 cr_lbstall | _PORT_64BIT_FLAG, 4883 cr_tidfull, 4884 cr_tidinvalid, 4885 cr_rxtidflowdrop, 4886 cr_base_egrovfl + 0, 4887 cr_base_egrovfl + 1, 4888 cr_base_egrovfl + 2, 4889 cr_base_egrovfl + 3, 4890 cr_base_egrovfl + 4, 4891 cr_base_egrovfl + 5, 4892 cr_base_egrovfl + 6, 4893 cr_base_egrovfl + 7, 4894 cr_base_egrovfl + 8, 4895 cr_base_egrovfl + 9, 4896 cr_base_egrovfl + 10, 4897 cr_base_egrovfl + 11, 4898 cr_base_egrovfl + 12, 4899 cr_base_egrovfl + 13, 4900 cr_base_egrovfl + 14, 4901 cr_base_egrovfl + 15, 4902 cr_base_egrovfl + 16, 4903 cr_base_egrovfl + 17, 4904 }; 4905 4906 /* 4907 * same as cntr7322names and cntr7322indices, but for port-specific counters. 4908 * portcntr7322indices is somewhat complicated by some registers needing 4909 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG 4910 */ 4911 static const char portcntr7322names[] = 4912 "TxPkt\n" 4913 "TxFlowPkt\n" 4914 "TxWords\n" 4915 "RxPkt\n" 4916 "RxFlowPkt\n" 4917 "RxWords\n" 4918 "TxFlowStall\n" 4919 "TxDmaDesc\n" /* 7220 and 7322-only */ 4920 "E RxDlidFltr\n" /* 7220 and 7322-only */ 4921 "IBStatusChng\n" 4922 "IBLinkDown\n" 4923 "IBLnkRecov\n" 4924 "IBRxLinkErr\n" 4925 "IBSymbolErr\n" 4926 "RxLLIErr\n" 4927 "RxBadFormat\n" 4928 "RxBadLen\n" 4929 "RxBufOvrfl\n" 4930 "RxEBP\n" 4931 "RxFlowCtlErr\n" 4932 "RxICRCerr\n" 4933 "RxLPCRCerr\n" 4934 "RxVCRCerr\n" 4935 "RxInvalLen\n" 4936 "RxInvalPKey\n" 4937 "RxPktDropped\n" 4938 "TxBadLength\n" 4939 "TxDropped\n" 4940 "TxInvalLen\n" 4941 "TxUnderrun\n" 4942 "TxUnsupVL\n" 4943 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */ 4944 "RxVL15Drop\n" 4945 "RxVlErr\n" 4946 "XcessBufOvfl\n" 4947 "RxQPBadCtxt\n" /* 7322-only from here down */ 4948 "TXBadHeader\n" 4949 ; 4950 4951 static const u32 portcntr7322indices[] = { 4952 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG, 4953 crp_pktsendflow, 4954 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG, 4955 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG, 4956 crp_pktrcvflowctrl, 4957 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG, 4958 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG, 4959 crp_txsdmadesc | _PORT_64BIT_FLAG, 4960 crp_rxdlidfltr, 4961 crp_ibstatuschange, 4962 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG, 4963 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG, 4964 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG, 4965 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG, 4966 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG, 4967 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG, 4968 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG, 4969 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG, 4970 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG, 4971 crp_rcvflowctrlviol, 4972 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG, 4973 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG, 4974 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG, 4975 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG, 4976 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG, 4977 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG, 4978 crp_txminmaxlenerr, 4979 crp_txdroppedpkt, 4980 crp_txlenerr, 4981 crp_txunderrun, 4982 crp_txunsupvl, 4983 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG, 4984 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG, 4985 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG, 4986 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG, 4987 crp_rxqpinvalidctxt, 4988 crp_txhdrerr, 4989 }; 4990 4991 /* do all the setup to make the counter reads efficient later */ 4992 static void init_7322_cntrnames(struct qib_devdata *dd) 4993 { 4994 int i, j = 0; 4995 char *s; 4996 4997 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; 4998 i++) { 4999 /* we always have at least one counter before the egrovfl */ 5000 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12)) 5001 j = 1; 5002 s = strchr(s + 1, '\n'); 5003 if (s && j) 5004 j++; 5005 } 5006 dd->cspec->ncntrs = i; 5007 if (!s) 5008 /* full list; size is without terminating null */ 5009 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; 5010 else 5011 dd->cspec->cntrnamelen = 1 + s - cntr7322names; 5012 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), 5013 GFP_KERNEL); 5014 5015 for (i = 0, s = (char *)portcntr7322names; s; i++) 5016 s = strchr(s + 1, '\n'); 5017 dd->cspec->nportcntrs = i - 1; 5018 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; 5019 for (i = 0; i < dd->num_pports; ++i) { 5020 dd->pport[i].cpspec->portcntrs = 5021 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64), 5022 GFP_KERNEL); 5023 } 5024 } 5025 5026 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 5027 u64 **cntrp) 5028 { 5029 u32 ret; 5030 5031 if (namep) { 5032 ret = dd->cspec->cntrnamelen; 5033 if (pos >= ret) 5034 ret = 0; /* final read after getting everything */ 5035 else 5036 *namep = (char *) cntr7322names; 5037 } else { 5038 u64 *cntr = dd->cspec->cntrs; 5039 int i; 5040 5041 ret = dd->cspec->ncntrs * sizeof(u64); 5042 if (!cntr || pos >= ret) { 5043 /* everything read, or couldn't get memory */ 5044 ret = 0; 5045 goto done; 5046 } 5047 *cntrp = cntr; 5048 for (i = 0; i < dd->cspec->ncntrs; i++) 5049 if (cntr7322indices[i] & _PORT_64BIT_FLAG) 5050 *cntr++ = read_7322_creg(dd, 5051 cntr7322indices[i] & 5052 _PORT_CNTR_IDXMASK); 5053 else 5054 *cntr++ = read_7322_creg32(dd, 5055 cntr7322indices[i]); 5056 } 5057 done: 5058 return ret; 5059 } 5060 5061 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, 5062 char **namep, u64 **cntrp) 5063 { 5064 u32 ret; 5065 5066 if (namep) { 5067 ret = dd->cspec->portcntrnamelen; 5068 if (pos >= ret) 5069 ret = 0; /* final read after getting everything */ 5070 else 5071 *namep = (char *)portcntr7322names; 5072 } else { 5073 struct qib_pportdata *ppd = &dd->pport[port]; 5074 u64 *cntr = ppd->cpspec->portcntrs; 5075 int i; 5076 5077 ret = dd->cspec->nportcntrs * sizeof(u64); 5078 if (!cntr || pos >= ret) { 5079 /* everything read, or couldn't get memory */ 5080 ret = 0; 5081 goto done; 5082 } 5083 *cntrp = cntr; 5084 for (i = 0; i < dd->cspec->nportcntrs; i++) { 5085 if (portcntr7322indices[i] & _PORT_VIRT_FLAG) 5086 *cntr++ = qib_portcntr_7322(ppd, 5087 portcntr7322indices[i] & 5088 _PORT_CNTR_IDXMASK); 5089 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG) 5090 *cntr++ = read_7322_creg_port(ppd, 5091 portcntr7322indices[i] & 5092 _PORT_CNTR_IDXMASK); 5093 else 5094 *cntr++ = read_7322_creg32_port(ppd, 5095 portcntr7322indices[i]); 5096 } 5097 } 5098 done: 5099 return ret; 5100 } 5101 5102 /** 5103 * qib_get_7322_faststats - get word counters from chip before they overflow 5104 * @opaque - contains a pointer to the qlogic_ib device qib_devdata 5105 * 5106 * VESTIGIAL IBA7322 has no "small fast counters", so the only 5107 * real purpose of this function is to maintain the notion of 5108 * "active time", which in turn is only logged into the eeprom, 5109 * which we don;t have, yet, for 7322-based boards. 5110 * 5111 * called from add_timer 5112 */ 5113 static void qib_get_7322_faststats(struct timer_list *t) 5114 { 5115 struct qib_devdata *dd = from_timer(dd, t, stats_timer); 5116 struct qib_pportdata *ppd; 5117 unsigned long flags; 5118 u64 traffic_wds; 5119 int pidx; 5120 5121 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5122 ppd = dd->pport + pidx; 5123 5124 /* 5125 * If port isn't enabled or not operational ports, or 5126 * diags is running (can cause memory diags to fail) 5127 * skip this port this time. 5128 */ 5129 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) 5130 || dd->diag_client) 5131 continue; 5132 5133 /* 5134 * Maintain an activity timer, based on traffic 5135 * exceeding a threshold, so we need to check the word-counts 5136 * even if they are 64-bit. 5137 */ 5138 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) + 5139 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND); 5140 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); 5141 traffic_wds -= ppd->dd->traffic_wds; 5142 ppd->dd->traffic_wds += traffic_wds; 5143 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); 5144 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active & 5145 QIB_IB_QDR) && 5146 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 5147 QIBL_LINKACTIVE)) && 5148 ppd->cpspec->qdr_dfe_time && 5149 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) { 5150 ppd->cpspec->qdr_dfe_on = 0; 5151 5152 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 5153 ppd->dd->cspec->r1 ? 5154 QDR_STATIC_ADAPT_INIT_R1 : 5155 QDR_STATIC_ADAPT_INIT); 5156 force_h1(ppd); 5157 } 5158 } 5159 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); 5160 } 5161 5162 /* 5163 * If we were using MSIx, try to fallback to INTx. 5164 */ 5165 static int qib_7322_intr_fallback(struct qib_devdata *dd) 5166 { 5167 if (!dd->cspec->num_msix_entries) 5168 return 0; /* already using INTx */ 5169 5170 qib_devinfo(dd->pcidev, 5171 "MSIx interrupt not detected, trying INTx interrupts\n"); 5172 qib_7322_free_irq(dd); 5173 if (pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_LEGACY) < 0) 5174 qib_dev_err(dd, "Failed to enable INTx\n"); 5175 qib_setup_7322_interrupt(dd, 0); 5176 return 1; 5177 } 5178 5179 /* 5180 * Reset the XGXS (between serdes and IBC). Slightly less intrusive 5181 * than resetting the IBC or external link state, and useful in some 5182 * cases to cause some retraining. To do this right, we reset IBC 5183 * as well, then return to previous state (which may be still in reset) 5184 * NOTE: some callers of this "know" this writes the current value 5185 * of cpspec->ibcctrl_a as part of it's operation, so if that changes, 5186 * check all callers. 5187 */ 5188 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd) 5189 { 5190 u64 val; 5191 struct qib_devdata *dd = ppd->dd; 5192 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | 5193 SYM_MASK(IBPCSConfig_0, xcv_treset) | 5194 SYM_MASK(IBPCSConfig_0, tx_rx_reset); 5195 5196 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); 5197 qib_write_kreg(dd, kr_hwerrmask, 5198 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); 5199 qib_write_kreg_port(ppd, krp_ibcctrl_a, 5200 ppd->cpspec->ibcctrl_a & 5201 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); 5202 5203 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits); 5204 qib_read_kreg32(dd, kr_scratch); 5205 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); 5206 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 5207 qib_write_kreg(dd, kr_scratch, 0ULL); 5208 qib_write_kreg(dd, kr_hwerrclear, 5209 SYM_MASK(HwErrClear, statusValidNoEopClear)); 5210 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 5211 } 5212 5213 /* 5214 * This code for non-IBTA-compliant IB speed negotiation is only known to 5215 * work for the SDR to DDR transition, and only between an HCA and a switch 5216 * with recent firmware. It is based on observed heuristics, rather than 5217 * actual knowledge of the non-compliant speed negotiation. 5218 * It has a number of hard-coded fields, since the hope is to rewrite this 5219 * when a spec is available on how the negoation is intended to work. 5220 */ 5221 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr, 5222 u32 dcnt, u32 *data) 5223 { 5224 int i; 5225 u64 pbc; 5226 u32 __iomem *piobuf; 5227 u32 pnum, control, len; 5228 struct qib_devdata *dd = ppd->dd; 5229 5230 i = 0; 5231 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */ 5232 control = qib_7322_setpbc_control(ppd, len, 0, 15); 5233 pbc = ((u64) control << 32) | len; 5234 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) { 5235 if (i++ > 15) 5236 return; 5237 udelay(2); 5238 } 5239 /* disable header check on this packet, since it can't be valid */ 5240 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); 5241 writeq(pbc, piobuf); 5242 qib_flush_wc(); 5243 qib_pio_copy(piobuf + 2, hdr, 7); 5244 qib_pio_copy(piobuf + 9, data, dcnt); 5245 if (dd->flags & QIB_USE_SPCL_TRIG) { 5246 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; 5247 5248 qib_flush_wc(); 5249 __raw_writel(0xaebecede, piobuf + spcl_off); 5250 } 5251 qib_flush_wc(); 5252 qib_sendbuf_done(dd, pnum); 5253 /* and re-enable hdr check */ 5254 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); 5255 } 5256 5257 /* 5258 * _start packet gets sent twice at start, _done gets sent twice at end 5259 */ 5260 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which) 5261 { 5262 struct qib_devdata *dd = ppd->dd; 5263 static u32 swapped; 5264 u32 dw, i, hcnt, dcnt, *data; 5265 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba }; 5266 static u32 madpayload_start[0x40] = { 5267 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 5268 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 5269 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */ 5270 }; 5271 static u32 madpayload_done[0x40] = { 5272 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 5273 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 5274 0x40000001, 0x1388, 0x15e, /* rest 0's */ 5275 }; 5276 5277 dcnt = ARRAY_SIZE(madpayload_start); 5278 hcnt = ARRAY_SIZE(hdr); 5279 if (!swapped) { 5280 /* for maintainability, do it at runtime */ 5281 for (i = 0; i < hcnt; i++) { 5282 dw = (__force u32) cpu_to_be32(hdr[i]); 5283 hdr[i] = dw; 5284 } 5285 for (i = 0; i < dcnt; i++) { 5286 dw = (__force u32) cpu_to_be32(madpayload_start[i]); 5287 madpayload_start[i] = dw; 5288 dw = (__force u32) cpu_to_be32(madpayload_done[i]); 5289 madpayload_done[i] = dw; 5290 } 5291 swapped = 1; 5292 } 5293 5294 data = which ? madpayload_done : madpayload_start; 5295 5296 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 5297 qib_read_kreg64(dd, kr_scratch); 5298 udelay(2); 5299 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 5300 qib_read_kreg64(dd, kr_scratch); 5301 udelay(2); 5302 } 5303 5304 /* 5305 * Do the absolute minimum to cause an IB speed change, and make it 5306 * ready, but don't actually trigger the change. The caller will 5307 * do that when ready (if link is in Polling training state, it will 5308 * happen immediately, otherwise when link next goes down) 5309 * 5310 * This routine should only be used as part of the DDR autonegotation 5311 * code for devices that are not compliant with IB 1.2 (or code that 5312 * fixes things up for same). 5313 * 5314 * When link has gone down, and autoneg enabled, or autoneg has 5315 * failed and we give up until next time we set both speeds, and 5316 * then we want IBTA enabled as well as "use max enabled speed. 5317 */ 5318 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed) 5319 { 5320 u64 newctrlb; 5321 5322 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK | 5323 IBA7322_IBC_IBTA_1_2_MASK | 5324 IBA7322_IBC_MAX_SPEED_MASK); 5325 5326 if (speed & (speed - 1)) /* multiple speeds */ 5327 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) | 5328 IBA7322_IBC_IBTA_1_2_MASK | 5329 IBA7322_IBC_MAX_SPEED_MASK; 5330 else 5331 newctrlb |= speed == QIB_IB_QDR ? 5332 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK : 5333 ((speed == QIB_IB_DDR ? 5334 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR)); 5335 5336 if (newctrlb == ppd->cpspec->ibcctrl_b) 5337 return; 5338 5339 ppd->cpspec->ibcctrl_b = newctrlb; 5340 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 5341 qib_write_kreg(ppd->dd, kr_scratch, 0); 5342 } 5343 5344 /* 5345 * This routine is only used when we are not talking to another 5346 * IB 1.2-compliant device that we think can do DDR. 5347 * (This includes all existing switch chips as of Oct 2007.) 5348 * 1.2-compliant devices go directly to DDR prior to reaching INIT 5349 */ 5350 static void try_7322_autoneg(struct qib_pportdata *ppd) 5351 { 5352 unsigned long flags; 5353 5354 spin_lock_irqsave(&ppd->lflags_lock, flags); 5355 ppd->lflags |= QIBL_IB_AUTONEG_INPROG; 5356 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5357 qib_autoneg_7322_send(ppd, 0); 5358 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5359 qib_7322_mini_pcs_reset(ppd); 5360 /* 2 msec is minimum length of a poll cycle */ 5361 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work, 5362 msecs_to_jiffies(2)); 5363 } 5364 5365 /* 5366 * Handle the empirically determined mechanism for auto-negotiation 5367 * of DDR speed with switches. 5368 */ 5369 static void autoneg_7322_work(struct work_struct *work) 5370 { 5371 struct qib_pportdata *ppd; 5372 u32 i; 5373 unsigned long flags; 5374 5375 ppd = container_of(work, struct qib_chippport_specific, 5376 autoneg_work.work)->ppd; 5377 5378 /* 5379 * Busy wait for this first part, it should be at most a 5380 * few hundred usec, since we scheduled ourselves for 2msec. 5381 */ 5382 for (i = 0; i < 25; i++) { 5383 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState) 5384 == IB_7322_LT_STATE_POLLQUIET) { 5385 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE); 5386 break; 5387 } 5388 udelay(100); 5389 } 5390 5391 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 5392 goto done; /* we got there early or told to stop */ 5393 5394 /* we expect this to timeout */ 5395 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5396 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5397 msecs_to_jiffies(90))) 5398 goto done; 5399 qib_7322_mini_pcs_reset(ppd); 5400 5401 /* we expect this to timeout */ 5402 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5403 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5404 msecs_to_jiffies(1700))) 5405 goto done; 5406 qib_7322_mini_pcs_reset(ppd); 5407 5408 set_7322_ibspeed_fast(ppd, QIB_IB_SDR); 5409 5410 /* 5411 * Wait up to 250 msec for link to train and get to INIT at DDR; 5412 * this should terminate early. 5413 */ 5414 wait_event_timeout(ppd->cpspec->autoneg_wait, 5415 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5416 msecs_to_jiffies(250)); 5417 done: 5418 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) { 5419 spin_lock_irqsave(&ppd->lflags_lock, flags); 5420 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 5421 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) { 5422 ppd->lflags |= QIBL_IB_AUTONEG_FAILED; 5423 ppd->cpspec->autoneg_tries = 0; 5424 } 5425 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5426 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5427 } 5428 } 5429 5430 /* 5431 * This routine is used to request IPG set in the QLogic switch. 5432 * Only called if r1. 5433 */ 5434 static void try_7322_ipg(struct qib_pportdata *ppd) 5435 { 5436 struct qib_ibport *ibp = &ppd->ibport_data; 5437 struct ib_mad_send_buf *send_buf; 5438 struct ib_mad_agent *agent; 5439 struct ib_smp *smp; 5440 unsigned delay; 5441 int ret; 5442 5443 agent = ibp->rvp.send_agent; 5444 if (!agent) 5445 goto retry; 5446 5447 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR, 5448 IB_MGMT_MAD_DATA, GFP_ATOMIC, 5449 IB_MGMT_BASE_VERSION); 5450 if (IS_ERR(send_buf)) 5451 goto retry; 5452 5453 if (!ibp->smi_ah) { 5454 struct ib_ah *ah; 5455 5456 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE)); 5457 if (IS_ERR(ah)) 5458 ret = PTR_ERR(ah); 5459 else { 5460 send_buf->ah = ah; 5461 ibp->smi_ah = ibah_to_rvtah(ah); 5462 ret = 0; 5463 } 5464 } else { 5465 send_buf->ah = &ibp->smi_ah->ibah; 5466 ret = 0; 5467 } 5468 5469 smp = send_buf->mad; 5470 smp->base_version = IB_MGMT_BASE_VERSION; 5471 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE; 5472 smp->class_version = 1; 5473 smp->method = IB_MGMT_METHOD_SEND; 5474 smp->hop_cnt = 1; 5475 smp->attr_id = QIB_VENDOR_IPG; 5476 smp->attr_mod = 0; 5477 5478 if (!ret) 5479 ret = ib_post_send_mad(send_buf, NULL); 5480 if (ret) 5481 ib_free_send_mad(send_buf); 5482 retry: 5483 delay = 2 << ppd->cpspec->ipg_tries; 5484 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work, 5485 msecs_to_jiffies(delay)); 5486 } 5487 5488 /* 5489 * Timeout handler for setting IPG. 5490 * Only called if r1. 5491 */ 5492 static void ipg_7322_work(struct work_struct *work) 5493 { 5494 struct qib_pportdata *ppd; 5495 5496 ppd = container_of(work, struct qib_chippport_specific, 5497 ipg_work.work)->ppd; 5498 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE)) 5499 && ++ppd->cpspec->ipg_tries <= 10) 5500 try_7322_ipg(ppd); 5501 } 5502 5503 static u32 qib_7322_iblink_state(u64 ibcs) 5504 { 5505 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState); 5506 5507 switch (state) { 5508 case IB_7322_L_STATE_INIT: 5509 state = IB_PORT_INIT; 5510 break; 5511 case IB_7322_L_STATE_ARM: 5512 state = IB_PORT_ARMED; 5513 break; 5514 case IB_7322_L_STATE_ACTIVE: 5515 /* fall through */ 5516 case IB_7322_L_STATE_ACT_DEFER: 5517 state = IB_PORT_ACTIVE; 5518 break; 5519 default: /* fall through */ 5520 case IB_7322_L_STATE_DOWN: 5521 state = IB_PORT_DOWN; 5522 break; 5523 } 5524 return state; 5525 } 5526 5527 /* returns the IBTA port state, rather than the IBC link training state */ 5528 static u8 qib_7322_phys_portstate(u64 ibcs) 5529 { 5530 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState); 5531 return qib_7322_physportstate[state]; 5532 } 5533 5534 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) 5535 { 5536 int ret = 0, symadj = 0; 5537 unsigned long flags; 5538 int mult; 5539 5540 spin_lock_irqsave(&ppd->lflags_lock, flags); 5541 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; 5542 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5543 5544 /* Update our picture of width and speed from chip */ 5545 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { 5546 ppd->link_speed_active = QIB_IB_QDR; 5547 mult = 4; 5548 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { 5549 ppd->link_speed_active = QIB_IB_DDR; 5550 mult = 2; 5551 } else { 5552 ppd->link_speed_active = QIB_IB_SDR; 5553 mult = 1; 5554 } 5555 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { 5556 ppd->link_width_active = IB_WIDTH_4X; 5557 mult *= 4; 5558 } else 5559 ppd->link_width_active = IB_WIDTH_1X; 5560 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)]; 5561 5562 if (!ibup) { 5563 u64 clr; 5564 5565 /* Link went down. */ 5566 /* do IPG MAD again after linkdown, even if last time failed */ 5567 ppd->cpspec->ipg_tries = 0; 5568 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 5569 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | 5570 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); 5571 if (clr) 5572 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr); 5573 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5574 QIBL_IB_AUTONEG_INPROG))) 5575 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5576 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5577 struct qib_qsfp_data *qd = 5578 &ppd->cpspec->qsfp_data; 5579 /* unlock the Tx settings, speed may change */ 5580 qib_write_kreg_port(ppd, krp_tx_deemph_override, 5581 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 5582 reset_tx_deemphasis_override)); 5583 qib_cancel_sends(ppd); 5584 /* on link down, ensure sane pcs state */ 5585 qib_7322_mini_pcs_reset(ppd); 5586 /* schedule the qsfp refresh which should turn the link 5587 off */ 5588 if (ppd->dd->flags & QIB_HAS_QSFP) { 5589 qd->t_insert = jiffies; 5590 queue_work(ib_wq, &qd->work); 5591 } 5592 spin_lock_irqsave(&ppd->sdma_lock, flags); 5593 if (__qib_sdma_running(ppd)) 5594 __qib_sdma_process_event(ppd, 5595 qib_sdma_event_e70_go_idle); 5596 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 5597 } 5598 clr = read_7322_creg32_port(ppd, crp_iblinkdown); 5599 if (clr == ppd->cpspec->iblnkdownsnap) 5600 ppd->cpspec->iblnkdowndelta++; 5601 } else { 5602 if (qib_compat_ddr_negotiate && 5603 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5604 QIBL_IB_AUTONEG_INPROG)) && 5605 ppd->link_speed_active == QIB_IB_SDR && 5606 (ppd->link_speed_enabled & QIB_IB_DDR) 5607 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) { 5608 /* we are SDR, and auto-negotiation enabled */ 5609 ++ppd->cpspec->autoneg_tries; 5610 if (!ppd->cpspec->ibdeltainprog) { 5611 ppd->cpspec->ibdeltainprog = 1; 5612 ppd->cpspec->ibsymdelta += 5613 read_7322_creg32_port(ppd, 5614 crp_ibsymbolerr) - 5615 ppd->cpspec->ibsymsnap; 5616 ppd->cpspec->iblnkerrdelta += 5617 read_7322_creg32_port(ppd, 5618 crp_iblinkerrrecov) - 5619 ppd->cpspec->iblnkerrsnap; 5620 } 5621 try_7322_autoneg(ppd); 5622 ret = 1; /* no other IB status change processing */ 5623 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5624 ppd->link_speed_active == QIB_IB_SDR) { 5625 qib_autoneg_7322_send(ppd, 1); 5626 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5627 qib_7322_mini_pcs_reset(ppd); 5628 udelay(2); 5629 ret = 1; /* no other IB status change processing */ 5630 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5631 (ppd->link_speed_active & QIB_IB_DDR)) { 5632 spin_lock_irqsave(&ppd->lflags_lock, flags); 5633 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG | 5634 QIBL_IB_AUTONEG_FAILED); 5635 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5636 ppd->cpspec->autoneg_tries = 0; 5637 /* re-enable SDR, for next link down */ 5638 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5639 wake_up(&ppd->cpspec->autoneg_wait); 5640 symadj = 1; 5641 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) { 5642 /* 5643 * Clear autoneg failure flag, and do setup 5644 * so we'll try next time link goes down and 5645 * back to INIT (possibly connected to a 5646 * different device). 5647 */ 5648 spin_lock_irqsave(&ppd->lflags_lock, flags); 5649 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 5650 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5651 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK; 5652 symadj = 1; 5653 } 5654 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5655 symadj = 1; 5656 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) 5657 try_7322_ipg(ppd); 5658 if (!ppd->cpspec->recovery_init) 5659 setup_7322_link_recovery(ppd, 0); 5660 ppd->cpspec->qdr_dfe_time = jiffies + 5661 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY); 5662 } 5663 ppd->cpspec->ibmalfusesnap = 0; 5664 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 5665 crp_errlink); 5666 } 5667 if (symadj) { 5668 ppd->cpspec->iblnkdownsnap = 5669 read_7322_creg32_port(ppd, crp_iblinkdown); 5670 if (ppd->cpspec->ibdeltainprog) { 5671 ppd->cpspec->ibdeltainprog = 0; 5672 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd, 5673 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap; 5674 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd, 5675 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap; 5676 } 5677 } else if (!ibup && qib_compat_ddr_negotiate && 5678 !ppd->cpspec->ibdeltainprog && 5679 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5680 ppd->cpspec->ibdeltainprog = 1; 5681 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 5682 crp_ibsymbolerr); 5683 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 5684 crp_iblinkerrrecov); 5685 } 5686 5687 if (!ret) 5688 qib_setup_7322_setextled(ppd, ibup); 5689 return ret; 5690 } 5691 5692 /* 5693 * Does read/modify/write to appropriate registers to 5694 * set output and direction bits selected by mask. 5695 * these are in their canonical postions (e.g. lsb of 5696 * dir will end up in D48 of extctrl on existing chips). 5697 * returns contents of GP Inputs. 5698 */ 5699 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) 5700 { 5701 u64 read_val, new_out; 5702 unsigned long flags; 5703 5704 if (mask) { 5705 /* some bits being written, lock access to GPIO */ 5706 dir &= mask; 5707 out &= mask; 5708 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 5709 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); 5710 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); 5711 new_out = (dd->cspec->gpio_out & ~mask) | out; 5712 5713 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 5714 qib_write_kreg(dd, kr_gpio_out, new_out); 5715 dd->cspec->gpio_out = new_out; 5716 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 5717 } 5718 /* 5719 * It is unlikely that a read at this time would get valid 5720 * data on a pin whose direction line was set in the same 5721 * call to this function. We include the read here because 5722 * that allows us to potentially combine a change on one pin with 5723 * a read on another, and because the old code did something like 5724 * this. 5725 */ 5726 read_val = qib_read_kreg64(dd, kr_extstatus); 5727 return SYM_FIELD(read_val, EXTStatus, GPIOIn); 5728 } 5729 5730 /* Enable writes to config EEPROM, if possible. Returns previous state */ 5731 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) 5732 { 5733 int prev_wen; 5734 u32 mask; 5735 5736 mask = 1 << QIB_EEPROM_WEN_NUM; 5737 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; 5738 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); 5739 5740 return prev_wen & 1; 5741 } 5742 5743 /* 5744 * Read fundamental info we need to use the chip. These are 5745 * the registers that describe chip capabilities, and are 5746 * saved in shadow registers. 5747 */ 5748 static void get_7322_chip_params(struct qib_devdata *dd) 5749 { 5750 u64 val; 5751 u32 piobufs; 5752 int mtu; 5753 5754 dd->palign = qib_read_kreg32(dd, kr_pagealign); 5755 5756 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); 5757 5758 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); 5759 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); 5760 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); 5761 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); 5762 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; 5763 5764 val = qib_read_kreg64(dd, kr_sendpiobufcnt); 5765 dd->piobcnt2k = val & ~0U; 5766 dd->piobcnt4k = val >> 32; 5767 val = qib_read_kreg64(dd, kr_sendpiosize); 5768 dd->piosize2k = val & ~0U; 5769 dd->piosize4k = val >> 32; 5770 5771 mtu = ib_mtu_enum_to_int(qib_ibmtu); 5772 if (mtu == -1) 5773 mtu = QIB_DEFAULT_MTU; 5774 dd->pport[0].ibmtu = (u32)mtu; 5775 dd->pport[1].ibmtu = (u32)mtu; 5776 5777 /* these may be adjusted in init_chip_wc_pat() */ 5778 dd->pio2kbase = (u32 __iomem *) 5779 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); 5780 dd->pio4kbase = (u32 __iomem *) 5781 ((char __iomem *) dd->kregbase + 5782 (dd->piobufbase >> 32)); 5783 /* 5784 * 4K buffers take 2 pages; we use roundup just to be 5785 * paranoid; we calculate it once here, rather than on 5786 * ever buf allocate 5787 */ 5788 dd->align4k = ALIGN(dd->piosize4k, dd->palign); 5789 5790 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; 5791 5792 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / 5793 (sizeof(u64) * BITS_PER_BYTE / 2); 5794 } 5795 5796 /* 5797 * The chip base addresses in cspec and cpspec have to be set 5798 * after possible init_chip_wc_pat(), rather than in 5799 * get_7322_chip_params(), so split out as separate function 5800 */ 5801 static void qib_7322_set_baseaddrs(struct qib_devdata *dd) 5802 { 5803 u32 cregbase; 5804 5805 cregbase = qib_read_kreg32(dd, kr_counterregbase); 5806 5807 dd->cspec->cregbase = (u64 __iomem *)(cregbase + 5808 (char __iomem *)dd->kregbase); 5809 5810 dd->egrtidbase = (u64 __iomem *) 5811 ((char __iomem *) dd->kregbase + dd->rcvegrbase); 5812 5813 /* port registers are defined as relative to base of chip */ 5814 dd->pport[0].cpspec->kpregbase = 5815 (u64 __iomem *)((char __iomem *)dd->kregbase); 5816 dd->pport[1].cpspec->kpregbase = 5817 (u64 __iomem *)(dd->palign + 5818 (char __iomem *)dd->kregbase); 5819 dd->pport[0].cpspec->cpregbase = 5820 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], 5821 kr_counterregbase) + (char __iomem *)dd->kregbase); 5822 dd->pport[1].cpspec->cpregbase = 5823 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], 5824 kr_counterregbase) + (char __iomem *)dd->kregbase); 5825 } 5826 5827 /* 5828 * This is a fairly special-purpose observer, so we only support 5829 * the port-specific parts of SendCtrl 5830 */ 5831 5832 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \ 5833 SYM_MASK(SendCtrl_0, SDmaEnable) | \ 5834 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \ 5835 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \ 5836 SYM_MASK(SendCtrl_0, SDmaHalt) | \ 5837 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \ 5838 SYM_MASK(SendCtrl_0, ForceCreditUpToDate)) 5839 5840 static int sendctrl_hook(struct qib_devdata *dd, 5841 const struct diag_observer *op, u32 offs, 5842 u64 *data, u64 mask, int only_32) 5843 { 5844 unsigned long flags; 5845 unsigned idx; 5846 unsigned pidx; 5847 struct qib_pportdata *ppd = NULL; 5848 u64 local_data, all_bits; 5849 5850 /* 5851 * The fixed correspondence between Physical ports and pports is 5852 * severed. We need to hunt for the ppd that corresponds 5853 * to the offset we got. And we have to do that without admitting 5854 * we know the stride, apparently. 5855 */ 5856 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5857 u64 __iomem *psptr; 5858 u32 psoffs; 5859 5860 ppd = dd->pport + pidx; 5861 if (!ppd->cpspec->kpregbase) 5862 continue; 5863 5864 psptr = ppd->cpspec->kpregbase + krp_sendctrl; 5865 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); 5866 if (psoffs == offs) 5867 break; 5868 } 5869 5870 /* If pport is not being managed by driver, just avoid shadows. */ 5871 if (pidx >= dd->num_pports) 5872 ppd = NULL; 5873 5874 /* In any case, "idx" is flat index in kreg space */ 5875 idx = offs / sizeof(u64); 5876 5877 all_bits = ~0ULL; 5878 if (only_32) 5879 all_bits >>= 32; 5880 5881 spin_lock_irqsave(&dd->sendctrl_lock, flags); 5882 if (!ppd || (mask & all_bits) != all_bits) { 5883 /* 5884 * At least some mask bits are zero, so we need 5885 * to read. The judgement call is whether from 5886 * reg or shadow. First-cut: read reg, and complain 5887 * if any bits which should be shadowed are different 5888 * from their shadowed value. 5889 */ 5890 if (only_32) 5891 local_data = (u64)qib_read_kreg32(dd, idx); 5892 else 5893 local_data = qib_read_kreg64(dd, idx); 5894 *data = (local_data & ~mask) | (*data & mask); 5895 } 5896 if (mask) { 5897 /* 5898 * At least some mask bits are one, so we need 5899 * to write, but only shadow some bits. 5900 */ 5901 u64 sval, tval; /* Shadowed, transient */ 5902 5903 /* 5904 * New shadow val is bits we don't want to touch, 5905 * ORed with bits we do, that are intended for shadow. 5906 */ 5907 if (ppd) { 5908 sval = ppd->p_sendctrl & ~mask; 5909 sval |= *data & SENDCTRL_SHADOWED & mask; 5910 ppd->p_sendctrl = sval; 5911 } else 5912 sval = *data & SENDCTRL_SHADOWED & mask; 5913 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); 5914 qib_write_kreg(dd, idx, tval); 5915 qib_write_kreg(dd, kr_scratch, 0Ull); 5916 } 5917 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 5918 return only_32 ? 4 : 8; 5919 } 5920 5921 static const struct diag_observer sendctrl_0_observer = { 5922 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64), 5923 KREG_IDX(SendCtrl_0) * sizeof(u64) 5924 }; 5925 5926 static const struct diag_observer sendctrl_1_observer = { 5927 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64), 5928 KREG_IDX(SendCtrl_1) * sizeof(u64) 5929 }; 5930 5931 static ushort sdma_fetch_prio = 8; 5932 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO); 5933 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority"); 5934 5935 /* Besides logging QSFP events, we set appropriate TxDDS values */ 5936 static void init_txdds_table(struct qib_pportdata *ppd, int override); 5937 5938 static void qsfp_7322_event(struct work_struct *work) 5939 { 5940 struct qib_qsfp_data *qd; 5941 struct qib_pportdata *ppd; 5942 unsigned long pwrup; 5943 unsigned long flags; 5944 int ret; 5945 u32 le2; 5946 5947 qd = container_of(work, struct qib_qsfp_data, work); 5948 ppd = qd->ppd; 5949 pwrup = qd->t_insert + 5950 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC); 5951 5952 /* Delay for 20 msecs to allow ModPrs resistor to setup */ 5953 mdelay(QSFP_MODPRS_LAG_MSEC); 5954 5955 if (!qib_qsfp_mod_present(ppd)) { 5956 ppd->cpspec->qsfp_data.modpresent = 0; 5957 /* Set the physical link to disabled */ 5958 qib_set_ib_7322_lstate(ppd, 0, 5959 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 5960 spin_lock_irqsave(&ppd->lflags_lock, flags); 5961 ppd->lflags &= ~QIBL_LINKV; 5962 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5963 } else { 5964 /* 5965 * Some QSFP's not only do not respond until the full power-up 5966 * time, but may behave badly if we try. So hold off responding 5967 * to insertion. 5968 */ 5969 while (1) { 5970 if (time_is_before_jiffies(pwrup)) 5971 break; 5972 msleep(20); 5973 } 5974 5975 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 5976 5977 /* 5978 * Need to change LE2 back to defaults if we couldn't 5979 * read the cable type (to handle cable swaps), so do this 5980 * even on failure to read cable information. We don't 5981 * get here for QME, so IS_QME check not needed here. 5982 */ 5983 if (!ret && !ppd->dd->cspec->r1) { 5984 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) 5985 le2 = LE2_QME; 5986 else if (qd->cache.atten[1] >= qib_long_atten && 5987 QSFP_IS_CU(qd->cache.tech)) 5988 le2 = LE2_5m; 5989 else 5990 le2 = LE2_DEFAULT; 5991 } else 5992 le2 = LE2_DEFAULT; 5993 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7)); 5994 /* 5995 * We always change parameteters, since we can choose 5996 * values for cables without eeproms, and the cable may have 5997 * changed from a cable with full or partial eeprom content 5998 * to one with partial or no content. 5999 */ 6000 init_txdds_table(ppd, 0); 6001 /* The physical link is being re-enabled only when the 6002 * previous state was DISABLED and the VALID bit is not 6003 * set. This should only happen when the cable has been 6004 * physically pulled. */ 6005 if (!ppd->cpspec->qsfp_data.modpresent && 6006 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) { 6007 ppd->cpspec->qsfp_data.modpresent = 1; 6008 qib_set_ib_7322_lstate(ppd, 0, 6009 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 6010 spin_lock_irqsave(&ppd->lflags_lock, flags); 6011 ppd->lflags |= QIBL_LINKV; 6012 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 6013 } 6014 } 6015 } 6016 6017 /* 6018 * There is little we can do but complain to the user if QSFP 6019 * initialization fails. 6020 */ 6021 static void qib_init_7322_qsfp(struct qib_pportdata *ppd) 6022 { 6023 unsigned long flags; 6024 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data; 6025 struct qib_devdata *dd = ppd->dd; 6026 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N; 6027 6028 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 6029 qd->ppd = ppd; 6030 qib_qsfp_init(qd, qsfp_7322_event); 6031 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 6032 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); 6033 dd->cspec->gpio_mask |= mod_prs_bit; 6034 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 6035 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 6036 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 6037 } 6038 6039 /* 6040 * called at device initialization time, and also if the txselect 6041 * module parameter is changed. This is used for cables that don't 6042 * have valid QSFP EEPROMs (not present, or attenuation is zero). 6043 * We initialize to the default, then if there is a specific 6044 * unit,port match, we use that (and set it immediately, for the 6045 * current speed, if the link is at INIT or better). 6046 * String format is "default# unit#,port#=# ... u,p=#", separators must 6047 * be a SPACE character. A newline terminates. The u,p=# tuples may 6048 * optionally have "u,p=#,#", where the final # is the H1 value 6049 * The last specific match is used (actually, all are used, but last 6050 * one is the one that winds up set); if none at all, fall back on default. 6051 */ 6052 static void set_no_qsfp_atten(struct qib_devdata *dd, int change) 6053 { 6054 char *nxt, *str; 6055 u32 pidx, unit, port, deflt, h1; 6056 unsigned long val; 6057 int any = 0, seth1; 6058 int txdds_size; 6059 6060 str = txselect_list; 6061 6062 /* default number is validated in setup_txselect() */ 6063 deflt = simple_strtoul(str, &nxt, 0); 6064 for (pidx = 0; pidx < dd->num_pports; ++pidx) 6065 dd->pport[pidx].cpspec->no_eep = deflt; 6066 6067 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ; 6068 if (IS_QME(dd) || IS_QMH(dd)) 6069 txdds_size += TXDDS_MFG_SZ; 6070 6071 while (*nxt && nxt[1]) { 6072 str = ++nxt; 6073 unit = simple_strtoul(str, &nxt, 0); 6074 if (nxt == str || !*nxt || *nxt != ',') { 6075 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 6076 ; 6077 continue; 6078 } 6079 str = ++nxt; 6080 port = simple_strtoul(str, &nxt, 0); 6081 if (nxt == str || *nxt != '=') { 6082 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 6083 ; 6084 continue; 6085 } 6086 str = ++nxt; 6087 val = simple_strtoul(str, &nxt, 0); 6088 if (nxt == str) { 6089 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 6090 ; 6091 continue; 6092 } 6093 if (val >= txdds_size) 6094 continue; 6095 seth1 = 0; 6096 h1 = 0; /* gcc thinks it might be used uninitted */ 6097 if (*nxt == ',' && nxt[1]) { 6098 str = ++nxt; 6099 h1 = (u32)simple_strtoul(str, &nxt, 0); 6100 if (nxt == str) 6101 while (*nxt && *nxt++ != ' ') /* skip */ 6102 ; 6103 else 6104 seth1 = 1; 6105 } 6106 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; 6107 ++pidx) { 6108 struct qib_pportdata *ppd = &dd->pport[pidx]; 6109 6110 if (ppd->port != port || !ppd->link_speed_supported) 6111 continue; 6112 ppd->cpspec->no_eep = val; 6113 if (seth1) 6114 ppd->cpspec->h1_val = h1; 6115 /* now change the IBC and serdes, overriding generic */ 6116 init_txdds_table(ppd, 1); 6117 /* Re-enable the physical state machine on mezz boards 6118 * now that the correct settings have been set. 6119 * QSFP boards are handles by the QSFP event handler */ 6120 if (IS_QMH(dd) || IS_QME(dd)) 6121 qib_set_ib_7322_lstate(ppd, 0, 6122 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 6123 any++; 6124 } 6125 if (*nxt == '\n') 6126 break; /* done */ 6127 } 6128 if (change && !any) { 6129 /* no specific setting, use the default. 6130 * Change the IBC and serdes, but since it's 6131 * general, don't override specific settings. 6132 */ 6133 for (pidx = 0; pidx < dd->num_pports; ++pidx) 6134 if (dd->pport[pidx].link_speed_supported) 6135 init_txdds_table(&dd->pport[pidx], 0); 6136 } 6137 } 6138 6139 /* handle the txselect parameter changing */ 6140 static int setup_txselect(const char *str, const struct kernel_param *kp) 6141 { 6142 struct qib_devdata *dd; 6143 unsigned long val; 6144 char *n; 6145 6146 if (strlen(str) >= ARRAY_SIZE(txselect_list)) { 6147 pr_info("txselect_values string too long\n"); 6148 return -ENOSPC; 6149 } 6150 val = simple_strtoul(str, &n, 0); 6151 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 6152 TXDDS_MFG_SZ)) { 6153 pr_info("txselect_values must start with a number < %d\n", 6154 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); 6155 return -EINVAL; 6156 } 6157 strncpy(txselect_list, str, ARRAY_SIZE(txselect_list) - 1); 6158 6159 list_for_each_entry(dd, &qib_dev_list, list) 6160 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) 6161 set_no_qsfp_atten(dd, 1); 6162 return 0; 6163 } 6164 6165 /* 6166 * Write the final few registers that depend on some of the 6167 * init setup. Done late in init, just before bringing up 6168 * the serdes. 6169 */ 6170 static int qib_late_7322_initreg(struct qib_devdata *dd) 6171 { 6172 int ret = 0, n; 6173 u64 val; 6174 6175 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); 6176 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); 6177 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); 6178 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); 6179 val = qib_read_kreg64(dd, kr_sendpioavailaddr); 6180 if (val != dd->pioavailregs_phys) { 6181 qib_dev_err(dd, 6182 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n", 6183 (unsigned long) dd->pioavailregs_phys, 6184 (unsigned long long) val); 6185 ret = -EINVAL; 6186 } 6187 6188 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 6189 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); 6190 /* driver sends get pkey, lid, etc. checking also, to catch bugs */ 6191 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); 6192 6193 qib_register_observer(dd, &sendctrl_0_observer); 6194 qib_register_observer(dd, &sendctrl_1_observer); 6195 6196 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; 6197 qib_write_kreg(dd, kr_control, dd->control); 6198 /* 6199 * Set SendDmaFetchPriority and init Tx params, including 6200 * QSFP handler on boards that have QSFP. 6201 * First set our default attenuation entry for cables that 6202 * don't have valid attenuation. 6203 */ 6204 set_no_qsfp_atten(dd, 0); 6205 for (n = 0; n < dd->num_pports; ++n) { 6206 struct qib_pportdata *ppd = dd->pport + n; 6207 6208 qib_write_kreg_port(ppd, krp_senddmaprioritythld, 6209 sdma_fetch_prio & 0xf); 6210 /* Initialize qsfp if present on board. */ 6211 if (dd->flags & QIB_HAS_QSFP) 6212 qib_init_7322_qsfp(ppd); 6213 } 6214 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; 6215 qib_write_kreg(dd, kr_control, dd->control); 6216 6217 return ret; 6218 } 6219 6220 /* per IB port errors. */ 6221 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \ 6222 MASK_ACROSS(8, 15)) 6223 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41)) 6224 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \ 6225 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \ 6226 MASK_ACROSS(0, 11)) 6227 6228 /* 6229 * Write the initialization per-port registers that need to be done at 6230 * driver load and after reset completes (i.e., that aren't done as part 6231 * of other init procedures called from qib_init.c). 6232 * Some of these should be redundant on reset, but play safe. 6233 */ 6234 static void write_7322_init_portregs(struct qib_pportdata *ppd) 6235 { 6236 u64 val; 6237 int i; 6238 6239 if (!ppd->link_speed_supported) { 6240 /* no buffer credits for this port */ 6241 for (i = 1; i < 8; i++) 6242 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 6243 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0); 6244 qib_write_kreg(ppd->dd, kr_scratch, 0); 6245 return; 6246 } 6247 6248 /* 6249 * Set the number of supported virtual lanes in IBC, 6250 * for flow control packet handling on unsupported VLs 6251 */ 6252 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 6253 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); 6254 val |= (u64)(ppd->vls_supported - 1) << 6255 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); 6256 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 6257 6258 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP); 6259 6260 /* enable tx header checking */ 6261 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY | 6262 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID | 6263 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ); 6264 6265 qib_write_kreg_port(ppd, krp_ncmodectrl, 6266 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); 6267 6268 /* 6269 * Unconditionally clear the bufmask bits. If SDMA is 6270 * enabled, we'll set them appropriately later. 6271 */ 6272 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0); 6273 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0); 6274 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0); 6275 if (ppd->dd->cspec->r1) 6276 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); 6277 } 6278 6279 /* 6280 * Write the initialization per-device registers that need to be done at 6281 * driver load and after reset completes (i.e., that aren't done as part 6282 * of other init procedures called from qib_init.c). Also write per-port 6283 * registers that are affected by overall device config, such as QP mapping 6284 * Some of these should be redundant on reset, but play safe. 6285 */ 6286 static void write_7322_initregs(struct qib_devdata *dd) 6287 { 6288 struct qib_pportdata *ppd; 6289 int i, pidx; 6290 u64 val; 6291 6292 /* Set Multicast QPs received by port 2 to map to context one. */ 6293 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); 6294 6295 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 6296 unsigned n, regno; 6297 unsigned long flags; 6298 6299 if (dd->n_krcv_queues < 2 || 6300 !dd->pport[pidx].link_speed_supported) 6301 continue; 6302 6303 ppd = &dd->pport[pidx]; 6304 6305 /* be paranoid against later code motion, etc. */ 6306 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 6307 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); 6308 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 6309 6310 /* Initialize QP to context mapping */ 6311 regno = krp_rcvqpmaptable; 6312 val = 0; 6313 if (dd->num_pports > 1) 6314 n = dd->first_user_ctxt / dd->num_pports; 6315 else 6316 n = dd->first_user_ctxt - 1; 6317 for (i = 0; i < 32; ) { 6318 unsigned ctxt; 6319 6320 if (dd->num_pports > 1) 6321 ctxt = (i % n) * dd->num_pports + pidx; 6322 else if (i % n) 6323 ctxt = (i % n) + 1; 6324 else 6325 ctxt = ppd->hw_pidx; 6326 val |= ctxt << (5 * (i % 6)); 6327 i++; 6328 if (i % 6 == 0) { 6329 qib_write_kreg_port(ppd, regno, val); 6330 val = 0; 6331 regno++; 6332 } 6333 } 6334 qib_write_kreg_port(ppd, regno, val); 6335 } 6336 6337 /* 6338 * Setup up interrupt mitigation for kernel contexts, but 6339 * not user contexts (user contexts use interrupts when 6340 * stalled waiting for any packet, so want those interrupts 6341 * right away). 6342 */ 6343 for (i = 0; i < dd->first_user_ctxt; i++) { 6344 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; 6345 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); 6346 } 6347 6348 /* 6349 * Initialize as (disabled) rcvflow tables. Application code 6350 * will setup each flow as it uses the flow. 6351 * Doesn't clear any of the error bits that might be set. 6352 */ 6353 val = TIDFLOW_ERRBITS; /* these are W1C */ 6354 for (i = 0; i < dd->cfgctxts; i++) { 6355 int flow; 6356 6357 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++) 6358 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); 6359 } 6360 6361 /* 6362 * dual cards init to dual port recovery, single port cards to 6363 * the one port. Dual port cards may later adjust to 1 port, 6364 * and then back to dual port if both ports are connected 6365 * */ 6366 if (dd->num_pports) 6367 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); 6368 } 6369 6370 static int qib_init_7322_variables(struct qib_devdata *dd) 6371 { 6372 struct qib_pportdata *ppd; 6373 unsigned features, pidx, sbufcnt; 6374 int ret, mtu; 6375 u32 sbufs, updthresh; 6376 resource_size_t vl15off; 6377 6378 /* pport structs are contiguous, allocated after devdata */ 6379 ppd = (struct qib_pportdata *)(dd + 1); 6380 dd->pport = ppd; 6381 ppd[0].dd = dd; 6382 ppd[1].dd = dd; 6383 6384 dd->cspec = (struct qib_chip_specific *)(ppd + 2); 6385 6386 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); 6387 ppd[1].cpspec = &ppd[0].cpspec[1]; 6388 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */ 6389 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */ 6390 6391 spin_lock_init(&dd->cspec->rcvmod_lock); 6392 spin_lock_init(&dd->cspec->gpio_lock); 6393 6394 /* we haven't yet set QIB_PRESENT, so use read directly */ 6395 dd->revision = readq(&dd->kregbase[kr_revision]); 6396 6397 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { 6398 qib_dev_err(dd, 6399 "Revision register read failure, giving up initialization\n"); 6400 ret = -ENODEV; 6401 goto bail; 6402 } 6403 dd->flags |= QIB_PRESENT; /* now register routines work */ 6404 6405 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); 6406 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); 6407 dd->cspec->r1 = dd->minrev == 1; 6408 6409 get_7322_chip_params(dd); 6410 features = qib_7322_boardname(dd); 6411 6412 /* now that piobcnt2k and 4k set, we can allocate these */ 6413 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + 6414 NUM_VL15_BUFS + BITS_PER_LONG - 1; 6415 sbufcnt /= BITS_PER_LONG; 6416 dd->cspec->sendchkenable = 6417 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendchkenable), 6418 GFP_KERNEL); 6419 dd->cspec->sendgrhchk = 6420 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendgrhchk), 6421 GFP_KERNEL); 6422 dd->cspec->sendibchk = 6423 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendibchk), 6424 GFP_KERNEL); 6425 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || 6426 !dd->cspec->sendibchk) { 6427 ret = -ENOMEM; 6428 goto bail; 6429 } 6430 6431 ppd = dd->pport; 6432 6433 /* 6434 * GPIO bits for TWSI data and clock, 6435 * used for serial EEPROM. 6436 */ 6437 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; 6438 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; 6439 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; 6440 6441 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | 6442 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP | 6443 QIB_HAS_THRESH_UPDATE | 6444 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0); 6445 dd->flags |= qib_special_trigger ? 6446 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA; 6447 6448 /* 6449 * Setup initial values. These may change when PAT is enabled, but 6450 * we need these to do initial chip register accesses. 6451 */ 6452 qib_7322_set_baseaddrs(dd); 6453 6454 mtu = ib_mtu_enum_to_int(qib_ibmtu); 6455 if (mtu == -1) 6456 mtu = QIB_DEFAULT_MTU; 6457 6458 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; 6459 /* all hwerrors become interrupts, unless special purposed */ 6460 dd->cspec->hwerrmask = ~0ULL; 6461 /* link_recovery setup causes these errors, so ignore them, 6462 * other than clearing them when they occur */ 6463 dd->cspec->hwerrmask &= 6464 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | 6465 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | 6466 HWE_MASK(LATriggered)); 6467 6468 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) { 6469 struct qib_chippport_specific *cp = ppd->cpspec; 6470 6471 ppd->link_speed_supported = features & PORT_SPD_CAP; 6472 features >>= PORT_SPD_CAP_SHIFT; 6473 if (!ppd->link_speed_supported) { 6474 /* single port mode (7340, or configured) */ 6475 dd->skip_kctxt_mask |= 1 << pidx; 6476 if (pidx == 0) { 6477 /* Make sure port is disabled. */ 6478 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6479 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6480 ppd[0] = ppd[1]; 6481 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6482 IBSerdesPClkNotDetectMask_0) 6483 | SYM_MASK(HwErrMask, 6484 SDmaMemReadErrMask_0)); 6485 dd->cspec->int_enable_mask &= ~( 6486 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | 6487 SYM_MASK(IntMask, SDmaIdleIntMask_0) | 6488 SYM_MASK(IntMask, SDmaProgressIntMask_0) | 6489 SYM_MASK(IntMask, SDmaIntMask_0) | 6490 SYM_MASK(IntMask, ErrIntMask_0) | 6491 SYM_MASK(IntMask, SendDoneIntMask_0)); 6492 } else { 6493 /* Make sure port is disabled. */ 6494 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6495 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6496 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6497 IBSerdesPClkNotDetectMask_1) 6498 | SYM_MASK(HwErrMask, 6499 SDmaMemReadErrMask_1)); 6500 dd->cspec->int_enable_mask &= ~( 6501 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | 6502 SYM_MASK(IntMask, SDmaIdleIntMask_1) | 6503 SYM_MASK(IntMask, SDmaProgressIntMask_1) | 6504 SYM_MASK(IntMask, SDmaIntMask_1) | 6505 SYM_MASK(IntMask, ErrIntMask_1) | 6506 SYM_MASK(IntMask, SendDoneIntMask_1)); 6507 } 6508 continue; 6509 } 6510 6511 dd->num_pports++; 6512 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports); 6513 if (ret) { 6514 dd->num_pports--; 6515 goto bail; 6516 } 6517 6518 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; 6519 ppd->link_width_enabled = IB_WIDTH_4X; 6520 ppd->link_speed_enabled = ppd->link_speed_supported; 6521 /* 6522 * Set the initial values to reasonable default, will be set 6523 * for real when link is up. 6524 */ 6525 ppd->link_width_active = IB_WIDTH_4X; 6526 ppd->link_speed_active = QIB_IB_SDR; 6527 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS]; 6528 switch (qib_num_cfg_vls) { 6529 case 1: 6530 ppd->vls_supported = IB_VL_VL0; 6531 break; 6532 case 2: 6533 ppd->vls_supported = IB_VL_VL0_1; 6534 break; 6535 default: 6536 qib_devinfo(dd->pcidev, 6537 "Invalid num_vls %u, using 4 VLs\n", 6538 qib_num_cfg_vls); 6539 qib_num_cfg_vls = 4; 6540 /* fall through */ 6541 case 4: 6542 ppd->vls_supported = IB_VL_VL0_3; 6543 break; 6544 case 8: 6545 if (mtu <= 2048) 6546 ppd->vls_supported = IB_VL_VL0_7; 6547 else { 6548 qib_devinfo(dd->pcidev, 6549 "Invalid num_vls %u for MTU %d , using 4 VLs\n", 6550 qib_num_cfg_vls, mtu); 6551 ppd->vls_supported = IB_VL_VL0_3; 6552 qib_num_cfg_vls = 4; 6553 } 6554 break; 6555 } 6556 ppd->vls_operational = ppd->vls_supported; 6557 6558 init_waitqueue_head(&cp->autoneg_wait); 6559 INIT_DELAYED_WORK(&cp->autoneg_work, 6560 autoneg_7322_work); 6561 if (ppd->dd->cspec->r1) 6562 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work); 6563 6564 /* 6565 * For Mez and similar cards, no qsfp info, so do 6566 * the "cable info" setup here. Can be overridden 6567 * in adapter-specific routines. 6568 */ 6569 if (!(dd->flags & QIB_HAS_QSFP)) { 6570 if (!IS_QMH(dd) && !IS_QME(dd)) 6571 qib_devinfo(dd->pcidev, 6572 "IB%u:%u: Unknown mezzanine card type\n", 6573 dd->unit, ppd->port); 6574 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; 6575 /* 6576 * Choose center value as default tx serdes setting 6577 * until changed through module parameter. 6578 */ 6579 ppd->cpspec->no_eep = IS_QMH(dd) ? 6580 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4; 6581 } else 6582 cp->h1_val = H1_FORCE_VAL; 6583 6584 /* Avoid writes to chip for mini_init */ 6585 if (!qib_mini_init) 6586 write_7322_init_portregs(ppd); 6587 6588 timer_setup(&cp->chase_timer, reenable_chase, 0); 6589 6590 ppd++; 6591 } 6592 6593 dd->rcvhdrentsize = qib_rcvhdrentsize ? 6594 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE; 6595 dd->rcvhdrsize = qib_rcvhdrsize ? 6596 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE; 6597 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); 6598 6599 /* we always allocate at least 2048 bytes for eager buffers */ 6600 dd->rcvegrbufsize = max(mtu, 2048); 6601 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); 6602 6603 qib_7322_tidtemplate(dd); 6604 6605 /* 6606 * We can request a receive interrupt for 1 or 6607 * more packets from current offset. 6608 */ 6609 dd->rhdrhead_intr_off = 6610 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT; 6611 6612 /* setup the stats timer; the add_timer is done at end of init */ 6613 timer_setup(&dd->stats_timer, qib_get_7322_faststats, 0); 6614 6615 dd->ureg_align = 0x10000; /* 64KB alignment */ 6616 6617 dd->piosize2kmax_dwords = dd->piosize2k >> 2; 6618 6619 qib_7322_config_ctxts(dd); 6620 qib_set_ctxtcnt(dd); 6621 6622 /* 6623 * We do not set WC on the VL15 buffers to avoid 6624 * a rare problem with unaligned writes from 6625 * interrupt-flushed store buffers, so we need 6626 * to map those separately here. We can't solve 6627 * this for the rarely used mtrr case. 6628 */ 6629 ret = init_chip_wc_pat(dd, 0); 6630 if (ret) 6631 goto bail; 6632 6633 /* vl15 buffers start just after the 4k buffers */ 6634 vl15off = dd->physaddr + (dd->piobufbase >> 32) + 6635 dd->piobcnt4k * dd->align4k; 6636 dd->piovl15base = ioremap_nocache(vl15off, 6637 NUM_VL15_BUFS * dd->align4k); 6638 if (!dd->piovl15base) { 6639 ret = -ENOMEM; 6640 goto bail; 6641 } 6642 6643 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ 6644 6645 ret = 0; 6646 if (qib_mini_init) 6647 goto bail; 6648 if (!dd->num_pports) { 6649 qib_dev_err(dd, "No ports enabled, giving up initialization\n"); 6650 goto bail; /* no error, so can still figure out why err */ 6651 } 6652 6653 write_7322_initregs(dd); 6654 ret = qib_create_ctxts(dd); 6655 init_7322_cntrnames(dd); 6656 6657 updthresh = 8U; /* update threshold */ 6658 6659 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA. 6660 * reserve the update threshold amount for other kernel use, such 6661 * as sending SMI, MAD, and ACKs, or 3, whichever is greater, 6662 * unless we aren't enabling SDMA, in which case we want to use 6663 * all the 4k bufs for the kernel. 6664 * if this was less than the update threshold, we could wait 6665 * a long time for an update. Coded this way because we 6666 * sometimes change the update threshold for various reasons, 6667 * and we want this to remain robust. 6668 */ 6669 if (dd->flags & QIB_HAS_SEND_DMA) { 6670 dd->cspec->sdmabufcnt = dd->piobcnt4k; 6671 sbufs = updthresh > 3 ? updthresh : 3; 6672 } else { 6673 dd->cspec->sdmabufcnt = 0; 6674 sbufs = dd->piobcnt4k; 6675 } 6676 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - 6677 dd->cspec->sdmabufcnt; 6678 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; 6679 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ 6680 dd->last_pio = dd->cspec->lastbuf_for_pio; 6681 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? 6682 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; 6683 6684 /* 6685 * If we have 16 user contexts, we will have 7 sbufs 6686 * per context, so reduce the update threshold to match. We 6687 * want to update before we actually run out, at low pbufs/ctxt 6688 * so give ourselves some margin. 6689 */ 6690 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) 6691 updthresh = dd->pbufsctxt - 2; 6692 dd->cspec->updthresh_dflt = updthresh; 6693 dd->cspec->updthresh = updthresh; 6694 6695 /* before full enable, no interrupts, no locking needed */ 6696 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) 6697 << SYM_LSB(SendCtrl, AvailUpdThld)) | 6698 SYM_MASK(SendCtrl, SendBufAvailPad64Byte); 6699 6700 dd->psxmitwait_supported = 1; 6701 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; 6702 bail: 6703 if (!dd->ctxtcnt) 6704 dd->ctxtcnt = 1; /* for other initialization code */ 6705 6706 return ret; 6707 } 6708 6709 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc, 6710 u32 *pbufnum) 6711 { 6712 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK; 6713 struct qib_devdata *dd = ppd->dd; 6714 6715 /* last is same for 2k and 4k, because we use 4k if all 2k busy */ 6716 if (pbc & PBC_7322_VL15_SEND) { 6717 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; 6718 last = first; 6719 } else { 6720 if ((plen + 1) > dd->piosize2kmax_dwords) 6721 first = dd->piobcnt2k; 6722 else 6723 first = 0; 6724 last = dd->cspec->lastbuf_for_pio; 6725 } 6726 return qib_getsendbuf_range(dd, pbufnum, first, last); 6727 } 6728 6729 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv, 6730 u32 start) 6731 { 6732 qib_write_kreg_port(ppd, krp_psinterval, intv); 6733 qib_write_kreg_port(ppd, krp_psstart, start); 6734 } 6735 6736 /* 6737 * Must be called with sdma_lock held, or before init finished. 6738 */ 6739 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) 6740 { 6741 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt); 6742 } 6743 6744 /* 6745 * sdma_lock should be acquired before calling this routine 6746 */ 6747 static void dump_sdma_7322_state(struct qib_pportdata *ppd) 6748 { 6749 u64 reg, reg1, reg2; 6750 6751 reg = qib_read_kreg_port(ppd, krp_senddmastatus); 6752 qib_dev_porterr(ppd->dd, ppd->port, 6753 "SDMA senddmastatus: 0x%016llx\n", reg); 6754 6755 reg = qib_read_kreg_port(ppd, krp_sendctrl); 6756 qib_dev_porterr(ppd->dd, ppd->port, 6757 "SDMA sendctrl: 0x%016llx\n", reg); 6758 6759 reg = qib_read_kreg_port(ppd, krp_senddmabase); 6760 qib_dev_porterr(ppd->dd, ppd->port, 6761 "SDMA senddmabase: 0x%016llx\n", reg); 6762 6763 reg = qib_read_kreg_port(ppd, krp_senddmabufmask0); 6764 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1); 6765 reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2); 6766 qib_dev_porterr(ppd->dd, ppd->port, 6767 "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n", 6768 reg, reg1, reg2); 6769 6770 /* get bufuse bits, clear them, and print them again if non-zero */ 6771 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); 6772 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg); 6773 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); 6774 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1); 6775 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); 6776 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2); 6777 /* 0 and 1 should always be zero, so print as short form */ 6778 qib_dev_porterr(ppd->dd, ppd->port, 6779 "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n", 6780 reg, reg1, reg2); 6781 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); 6782 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); 6783 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); 6784 /* 0 and 1 should always be zero, so print as short form */ 6785 qib_dev_porterr(ppd->dd, ppd->port, 6786 "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n", 6787 reg, reg1, reg2); 6788 6789 reg = qib_read_kreg_port(ppd, krp_senddmatail); 6790 qib_dev_porterr(ppd->dd, ppd->port, 6791 "SDMA senddmatail: 0x%016llx\n", reg); 6792 6793 reg = qib_read_kreg_port(ppd, krp_senddmahead); 6794 qib_dev_porterr(ppd->dd, ppd->port, 6795 "SDMA senddmahead: 0x%016llx\n", reg); 6796 6797 reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr); 6798 qib_dev_porterr(ppd->dd, ppd->port, 6799 "SDMA senddmaheadaddr: 0x%016llx\n", reg); 6800 6801 reg = qib_read_kreg_port(ppd, krp_senddmalengen); 6802 qib_dev_porterr(ppd->dd, ppd->port, 6803 "SDMA senddmalengen: 0x%016llx\n", reg); 6804 6805 reg = qib_read_kreg_port(ppd, krp_senddmadesccnt); 6806 qib_dev_porterr(ppd->dd, ppd->port, 6807 "SDMA senddmadesccnt: 0x%016llx\n", reg); 6808 6809 reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt); 6810 qib_dev_porterr(ppd->dd, ppd->port, 6811 "SDMA senddmaidlecnt: 0x%016llx\n", reg); 6812 6813 reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld); 6814 qib_dev_porterr(ppd->dd, ppd->port, 6815 "SDMA senddmapriorityhld: 0x%016llx\n", reg); 6816 6817 reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt); 6818 qib_dev_porterr(ppd->dd, ppd->port, 6819 "SDMA senddmareloadcnt: 0x%016llx\n", reg); 6820 6821 dump_sdma_state(ppd); 6822 } 6823 6824 static struct sdma_set_state_action sdma_7322_action_table[] = { 6825 [qib_sdma_state_s00_hw_down] = { 6826 .go_s99_running_tofalse = 1, 6827 .op_enable = 0, 6828 .op_intenable = 0, 6829 .op_halt = 0, 6830 .op_drain = 0, 6831 }, 6832 [qib_sdma_state_s10_hw_start_up_wait] = { 6833 .op_enable = 0, 6834 .op_intenable = 1, 6835 .op_halt = 1, 6836 .op_drain = 0, 6837 }, 6838 [qib_sdma_state_s20_idle] = { 6839 .op_enable = 1, 6840 .op_intenable = 1, 6841 .op_halt = 1, 6842 .op_drain = 0, 6843 }, 6844 [qib_sdma_state_s30_sw_clean_up_wait] = { 6845 .op_enable = 0, 6846 .op_intenable = 1, 6847 .op_halt = 1, 6848 .op_drain = 0, 6849 }, 6850 [qib_sdma_state_s40_hw_clean_up_wait] = { 6851 .op_enable = 1, 6852 .op_intenable = 1, 6853 .op_halt = 1, 6854 .op_drain = 0, 6855 }, 6856 [qib_sdma_state_s50_hw_halt_wait] = { 6857 .op_enable = 1, 6858 .op_intenable = 1, 6859 .op_halt = 1, 6860 .op_drain = 1, 6861 }, 6862 [qib_sdma_state_s99_running] = { 6863 .op_enable = 1, 6864 .op_intenable = 1, 6865 .op_halt = 0, 6866 .op_drain = 0, 6867 .go_s99_running_totrue = 1, 6868 }, 6869 }; 6870 6871 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd) 6872 { 6873 ppd->sdma_state.set_state_action = sdma_7322_action_table; 6874 } 6875 6876 static int init_sdma_7322_regs(struct qib_pportdata *ppd) 6877 { 6878 struct qib_devdata *dd = ppd->dd; 6879 unsigned lastbuf, erstbuf; 6880 u64 senddmabufmask[3] = { 0 }; 6881 int n, ret = 0; 6882 6883 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys); 6884 qib_sdma_7322_setlengen(ppd); 6885 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 6886 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt); 6887 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0); 6888 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys); 6889 6890 if (dd->num_pports) 6891 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ 6892 else 6893 n = dd->cspec->sdmabufcnt; /* failsafe for init */ 6894 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - 6895 ((dd->num_pports == 1 || ppd->port == 2) ? n : 6896 dd->cspec->sdmabufcnt); 6897 lastbuf = erstbuf + n; 6898 6899 ppd->sdma_state.first_sendbuf = erstbuf; 6900 ppd->sdma_state.last_sendbuf = lastbuf; 6901 for (; erstbuf < lastbuf; ++erstbuf) { 6902 unsigned word = erstbuf / BITS_PER_LONG; 6903 unsigned bit = erstbuf & (BITS_PER_LONG - 1); 6904 6905 senddmabufmask[word] |= 1ULL << bit; 6906 } 6907 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]); 6908 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]); 6909 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]); 6910 return ret; 6911 } 6912 6913 /* sdma_lock must be held */ 6914 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd) 6915 { 6916 struct qib_devdata *dd = ppd->dd; 6917 int sane; 6918 int use_dmahead; 6919 u16 swhead; 6920 u16 swtail; 6921 u16 cnt; 6922 u16 hwhead; 6923 6924 use_dmahead = __qib_sdma_running(ppd) && 6925 (dd->flags & QIB_HAS_SDMA_TIMEOUT); 6926 retry: 6927 hwhead = use_dmahead ? 6928 (u16) le64_to_cpu(*ppd->sdma_head_dma) : 6929 (u16) qib_read_kreg_port(ppd, krp_senddmahead); 6930 6931 swhead = ppd->sdma_descq_head; 6932 swtail = ppd->sdma_descq_tail; 6933 cnt = ppd->sdma_descq_cnt; 6934 6935 if (swhead < swtail) 6936 /* not wrapped */ 6937 sane = (hwhead >= swhead) & (hwhead <= swtail); 6938 else if (swhead > swtail) 6939 /* wrapped around */ 6940 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 6941 (hwhead <= swtail); 6942 else 6943 /* empty */ 6944 sane = (hwhead == swhead); 6945 6946 if (unlikely(!sane)) { 6947 if (use_dmahead) { 6948 /* try one more time, directly from the register */ 6949 use_dmahead = 0; 6950 goto retry; 6951 } 6952 /* proceed as if no progress */ 6953 hwhead = swhead; 6954 } 6955 6956 return hwhead; 6957 } 6958 6959 static int qib_sdma_7322_busy(struct qib_pportdata *ppd) 6960 { 6961 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus); 6962 6963 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || 6964 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || 6965 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || 6966 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); 6967 } 6968 6969 /* 6970 * Compute the amount of delay before sending the next packet if the 6971 * port's send rate differs from the static rate set for the QP. 6972 * The delay affects the next packet and the amount of the delay is 6973 * based on the length of the this packet. 6974 */ 6975 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen, 6976 u8 srate, u8 vl) 6977 { 6978 u8 snd_mult = ppd->delay_mult; 6979 u8 rcv_mult = ib_rate_to_delay[srate]; 6980 u32 ret; 6981 6982 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0; 6983 6984 /* Indicate VL15, else set the VL in the control word */ 6985 if (vl == 15) 6986 ret |= PBC_7322_VL15_SEND_CTRL; 6987 else 6988 ret |= vl << PBC_VL_NUM_LSB; 6989 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB; 6990 6991 return ret; 6992 } 6993 6994 /* 6995 * Enable the per-port VL15 send buffers for use. 6996 * They follow the rest of the buffers, without a config parameter. 6997 * This was in initregs, but that is done before the shadow 6998 * is set up, and this has to be done after the shadow is 6999 * set up. 7000 */ 7001 static void qib_7322_initvl15_bufs(struct qib_devdata *dd) 7002 { 7003 unsigned vl15bufs; 7004 7005 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; 7006 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, 7007 TXCHK_CHG_TYPE_KERN, NULL); 7008 } 7009 7010 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd) 7011 { 7012 if (rcd->ctxt < NUM_IB_PORTS) { 7013 if (rcd->dd->num_pports > 1) { 7014 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2; 7015 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; 7016 } else { 7017 rcd->rcvegrcnt = KCTXT0_EGRCNT; 7018 rcd->rcvegr_tid_base = 0; 7019 } 7020 } else { 7021 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; 7022 rcd->rcvegr_tid_base = KCTXT0_EGRCNT + 7023 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; 7024 } 7025 } 7026 7027 #define QTXSLEEPS 5000 7028 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, 7029 u32 len, u32 which, struct qib_ctxtdata *rcd) 7030 { 7031 int i; 7032 const int last = start + len - 1; 7033 const int lastr = last / BITS_PER_LONG; 7034 u32 sleeps = 0; 7035 int wait = rcd != NULL; 7036 unsigned long flags; 7037 7038 while (wait) { 7039 unsigned long shadow = 0; 7040 int cstart, previ = -1; 7041 7042 /* 7043 * when flipping from kernel to user, we can't change 7044 * the checking type if the buffer is allocated to the 7045 * driver. It's OK the other direction, because it's 7046 * from close, and we have just disarm'ed all the 7047 * buffers. All the kernel to kernel changes are also 7048 * OK. 7049 */ 7050 for (cstart = start; cstart <= last; cstart++) { 7051 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 7052 / BITS_PER_LONG; 7053 if (i != previ) { 7054 shadow = (unsigned long) 7055 le64_to_cpu(dd->pioavailregs_dma[i]); 7056 previ = i; 7057 } 7058 if (test_bit(((2 * cstart) + 7059 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 7060 % BITS_PER_LONG, &shadow)) 7061 break; 7062 } 7063 7064 if (cstart > last) 7065 break; 7066 7067 if (sleeps == QTXSLEEPS) 7068 break; 7069 /* make sure we see an updated copy next time around */ 7070 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 7071 sleeps++; 7072 msleep(20); 7073 } 7074 7075 switch (which) { 7076 case TXCHK_CHG_TYPE_DIS1: 7077 /* 7078 * disable checking on a range; used by diags; just 7079 * one buffer, but still written generically 7080 */ 7081 for (i = start; i <= last; i++) 7082 clear_bit(i, dd->cspec->sendchkenable); 7083 break; 7084 7085 case TXCHK_CHG_TYPE_ENAB1: 7086 /* 7087 * (re)enable checking on a range; used by diags; just 7088 * one buffer, but still written generically; read 7089 * scratch to be sure buffer actually triggered, not 7090 * just flushed from processor. 7091 */ 7092 qib_read_kreg32(dd, kr_scratch); 7093 for (i = start; i <= last; i++) 7094 set_bit(i, dd->cspec->sendchkenable); 7095 break; 7096 7097 case TXCHK_CHG_TYPE_KERN: 7098 /* usable by kernel */ 7099 for (i = start; i <= last; i++) { 7100 set_bit(i, dd->cspec->sendibchk); 7101 clear_bit(i, dd->cspec->sendgrhchk); 7102 } 7103 spin_lock_irqsave(&dd->uctxt_lock, flags); 7104 /* see if we need to raise avail update threshold */ 7105 for (i = dd->first_user_ctxt; 7106 dd->cspec->updthresh != dd->cspec->updthresh_dflt 7107 && i < dd->cfgctxts; i++) 7108 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && 7109 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) 7110 < dd->cspec->updthresh_dflt) 7111 break; 7112 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 7113 if (i == dd->cfgctxts) { 7114 spin_lock_irqsave(&dd->sendctrl_lock, flags); 7115 dd->cspec->updthresh = dd->cspec->updthresh_dflt; 7116 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 7117 dd->sendctrl |= (dd->cspec->updthresh & 7118 SYM_RMASK(SendCtrl, AvailUpdThld)) << 7119 SYM_LSB(SendCtrl, AvailUpdThld); 7120 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 7121 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 7122 } 7123 break; 7124 7125 case TXCHK_CHG_TYPE_USER: 7126 /* for user process */ 7127 for (i = start; i <= last; i++) { 7128 clear_bit(i, dd->cspec->sendibchk); 7129 set_bit(i, dd->cspec->sendgrhchk); 7130 } 7131 spin_lock_irqsave(&dd->sendctrl_lock, flags); 7132 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt 7133 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { 7134 dd->cspec->updthresh = (rcd->piocnt / 7135 rcd->subctxt_cnt) - 1; 7136 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 7137 dd->sendctrl |= (dd->cspec->updthresh & 7138 SYM_RMASK(SendCtrl, AvailUpdThld)) 7139 << SYM_LSB(SendCtrl, AvailUpdThld); 7140 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 7141 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 7142 } else 7143 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 7144 break; 7145 7146 default: 7147 break; 7148 } 7149 7150 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i) 7151 qib_write_kreg(dd, kr_sendcheckmask + i, 7152 dd->cspec->sendchkenable[i]); 7153 7154 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) { 7155 qib_write_kreg(dd, kr_sendgrhcheckmask + i, 7156 dd->cspec->sendgrhchk[i]); 7157 qib_write_kreg(dd, kr_sendibpktmask + i, 7158 dd->cspec->sendibchk[i]); 7159 } 7160 7161 /* 7162 * Be sure whatever we did was seen by the chip and acted upon, 7163 * before we return. Mostly important for which >= 2. 7164 */ 7165 qib_read_kreg32(dd, kr_scratch); 7166 } 7167 7168 7169 /* useful for trigger analyzers, etc. */ 7170 static void writescratch(struct qib_devdata *dd, u32 val) 7171 { 7172 qib_write_kreg(dd, kr_scratch, val); 7173 } 7174 7175 /* Dummy for now, use chip regs soon */ 7176 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) 7177 { 7178 return -ENXIO; 7179 } 7180 7181 /** 7182 * qib_init_iba7322_funcs - set up the chip-specific function pointers 7183 * @dev: the pci_dev for qlogic_ib device 7184 * @ent: pci_device_id struct for this dev 7185 * 7186 * Also allocates, inits, and returns the devdata struct for this 7187 * device instance 7188 * 7189 * This is global, and is called directly at init to set up the 7190 * chip-specific function pointers for later use. 7191 */ 7192 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, 7193 const struct pci_device_id *ent) 7194 { 7195 struct qib_devdata *dd; 7196 int ret, i; 7197 u32 tabsize, actual_cnt = 0; 7198 7199 dd = qib_alloc_devdata(pdev, 7200 NUM_IB_PORTS * sizeof(struct qib_pportdata) + 7201 sizeof(struct qib_chip_specific) + 7202 NUM_IB_PORTS * sizeof(struct qib_chippport_specific)); 7203 if (IS_ERR(dd)) 7204 goto bail; 7205 7206 dd->f_bringup_serdes = qib_7322_bringup_serdes; 7207 dd->f_cleanup = qib_setup_7322_cleanup; 7208 dd->f_clear_tids = qib_7322_clear_tids; 7209 dd->f_free_irq = qib_7322_free_irq; 7210 dd->f_get_base_info = qib_7322_get_base_info; 7211 dd->f_get_msgheader = qib_7322_get_msgheader; 7212 dd->f_getsendbuf = qib_7322_getsendbuf; 7213 dd->f_gpio_mod = gpio_7322_mod; 7214 dd->f_eeprom_wen = qib_7322_eeprom_wen; 7215 dd->f_hdrqempty = qib_7322_hdrqempty; 7216 dd->f_ib_updown = qib_7322_ib_updown; 7217 dd->f_init_ctxt = qib_7322_init_ctxt; 7218 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; 7219 dd->f_intr_fallback = qib_7322_intr_fallback; 7220 dd->f_late_initreg = qib_late_7322_initreg; 7221 dd->f_setpbc_control = qib_7322_setpbc_control; 7222 dd->f_portcntr = qib_portcntr_7322; 7223 dd->f_put_tid = qib_7322_put_tid; 7224 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; 7225 dd->f_rcvctrl = rcvctrl_7322_mod; 7226 dd->f_read_cntrs = qib_read_7322cntrs; 7227 dd->f_read_portcntrs = qib_read_7322portcntrs; 7228 dd->f_reset = qib_do_7322_reset; 7229 dd->f_init_sdma_regs = init_sdma_7322_regs; 7230 dd->f_sdma_busy = qib_sdma_7322_busy; 7231 dd->f_sdma_gethead = qib_sdma_7322_gethead; 7232 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; 7233 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; 7234 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; 7235 dd->f_sendctrl = sendctrl_7322_mod; 7236 dd->f_set_armlaunch = qib_set_7322_armlaunch; 7237 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; 7238 dd->f_iblink_state = qib_7322_iblink_state; 7239 dd->f_ibphys_portstate = qib_7322_phys_portstate; 7240 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; 7241 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; 7242 dd->f_set_ib_loopback = qib_7322_set_loopback; 7243 dd->f_get_ib_table = qib_7322_get_ib_table; 7244 dd->f_set_ib_table = qib_7322_set_ib_table; 7245 dd->f_set_intr_state = qib_7322_set_intr_state; 7246 dd->f_setextled = qib_setup_7322_setextled; 7247 dd->f_txchk_change = qib_7322_txchk_change; 7248 dd->f_update_usrhead = qib_update_7322_usrhead; 7249 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; 7250 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; 7251 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; 7252 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; 7253 dd->f_sdma_init_early = qib_7322_sdma_init_early; 7254 dd->f_writescratch = writescratch; 7255 dd->f_tempsense_rd = qib_7322_tempsense_rd; 7256 #ifdef CONFIG_INFINIBAND_QIB_DCA 7257 dd->f_notify_dca = qib_7322_notify_dca; 7258 #endif 7259 /* 7260 * Do remaining PCIe setup and save PCIe values in dd. 7261 * Any error printing is already done by the init code. 7262 * On return, we have the chip mapped, but chip registers 7263 * are not set up until start of qib_init_7322_variables. 7264 */ 7265 ret = qib_pcie_ddinit(dd, pdev, ent); 7266 if (ret < 0) 7267 goto bail_free; 7268 7269 /* initialize chip-specific variables */ 7270 ret = qib_init_7322_variables(dd); 7271 if (ret) 7272 goto bail_cleanup; 7273 7274 if (qib_mini_init || !dd->num_pports) 7275 goto bail; 7276 7277 /* 7278 * Determine number of vectors we want; depends on port count 7279 * and number of configured kernel receive queues actually used. 7280 * Should also depend on whether sdma is enabled or not, but 7281 * that's such a rare testing case it's not worth worrying about. 7282 */ 7283 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); 7284 for (i = 0; i < tabsize; i++) 7285 if ((i < ARRAY_SIZE(irq_table) && 7286 irq_table[i].port <= dd->num_pports) || 7287 (i >= ARRAY_SIZE(irq_table) && 7288 dd->rcd[i - ARRAY_SIZE(irq_table)])) 7289 actual_cnt++; 7290 /* reduce by ctxt's < 2 */ 7291 if (qib_krcvq01_no_msi) 7292 actual_cnt -= dd->num_pports; 7293 7294 tabsize = actual_cnt; 7295 dd->cspec->msix_entries = kcalloc(tabsize, 7296 sizeof(struct qib_msix_entry), 7297 GFP_KERNEL); 7298 if (!dd->cspec->msix_entries) 7299 tabsize = 0; 7300 7301 if (qib_pcie_params(dd, 8, &tabsize)) 7302 qib_dev_err(dd, 7303 "Failed to setup PCIe or interrupts; continuing anyway\n"); 7304 /* may be less than we wanted, if not enough available */ 7305 dd->cspec->num_msix_entries = tabsize; 7306 7307 /* setup interrupt handler */ 7308 qib_setup_7322_interrupt(dd, 1); 7309 7310 /* clear diagctrl register, in case diags were running and crashed */ 7311 qib_write_kreg(dd, kr_hwdiagctrl, 0); 7312 #ifdef CONFIG_INFINIBAND_QIB_DCA 7313 if (!dca_add_requester(&pdev->dev)) { 7314 qib_devinfo(dd->pcidev, "DCA enabled\n"); 7315 dd->flags |= QIB_DCA_ENABLED; 7316 qib_setup_dca(dd); 7317 } 7318 #endif 7319 goto bail; 7320 7321 bail_cleanup: 7322 qib_pcie_ddcleanup(dd); 7323 bail_free: 7324 qib_free_devdata(dd); 7325 dd = ERR_PTR(ret); 7326 bail: 7327 return dd; 7328 } 7329 7330 /* 7331 * Set the table entry at the specified index from the table specifed. 7332 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first 7333 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR. 7334 * 'idx' below addresses the correct entry, while its 4 LSBs select the 7335 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table. 7336 */ 7337 #define DDS_ENT_AMP_LSB 14 7338 #define DDS_ENT_MAIN_LSB 9 7339 #define DDS_ENT_POST_LSB 5 7340 #define DDS_ENT_PRE_XTRA_LSB 3 7341 #define DDS_ENT_PRE_LSB 0 7342 7343 /* 7344 * Set one entry in the TxDDS table for spec'd port 7345 * ridx picks one of the entries, while tp points 7346 * to the appropriate table entry. 7347 */ 7348 static void set_txdds(struct qib_pportdata *ppd, int ridx, 7349 const struct txdds_ent *tp) 7350 { 7351 struct qib_devdata *dd = ppd->dd; 7352 u32 pack_ent; 7353 int regidx; 7354 7355 /* Get correct offset in chip-space, and in source table */ 7356 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx; 7357 /* 7358 * We do not use qib_write_kreg_port() because it was intended 7359 * only for registers in the lower "port specific" pages. 7360 * So do index calculation by hand. 7361 */ 7362 if (ppd->hw_pidx) 7363 regidx += (dd->palign / sizeof(u64)); 7364 7365 pack_ent = tp->amp << DDS_ENT_AMP_LSB; 7366 pack_ent |= tp->main << DDS_ENT_MAIN_LSB; 7367 pack_ent |= tp->pre << DDS_ENT_PRE_LSB; 7368 pack_ent |= tp->post << DDS_ENT_POST_LSB; 7369 qib_write_kreg(dd, regidx, pack_ent); 7370 /* Prevent back-to-back writes by hitting scratch */ 7371 qib_write_kreg(ppd->dd, kr_scratch, 0); 7372 } 7373 7374 static const struct vendor_txdds_ent vendor_txdds[] = { 7375 { /* Amphenol 1m 30awg NoEq */ 7376 { 0x41, 0x50, 0x48 }, "584470002 ", 7377 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 }, 7378 }, 7379 { /* Amphenol 3m 28awg NoEq */ 7380 { 0x41, 0x50, 0x48 }, "584470004 ", 7381 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 }, 7382 }, 7383 { /* Finisar 3m OM2 Optical */ 7384 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL", 7385 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 }, 7386 }, 7387 { /* Finisar 30m OM2 Optical */ 7388 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL", 7389 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 }, 7390 }, 7391 { /* Finisar Default OM2 Optical */ 7392 { 0x00, 0x90, 0x65 }, NULL, 7393 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 }, 7394 }, 7395 { /* Gore 1m 30awg NoEq */ 7396 { 0x00, 0x21, 0x77 }, "QSN3300-1 ", 7397 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 }, 7398 }, 7399 { /* Gore 2m 30awg NoEq */ 7400 { 0x00, 0x21, 0x77 }, "QSN3300-2 ", 7401 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 }, 7402 }, 7403 { /* Gore 1m 28awg NoEq */ 7404 { 0x00, 0x21, 0x77 }, "QSN3800-1 ", 7405 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 }, 7406 }, 7407 { /* Gore 3m 28awg NoEq */ 7408 { 0x00, 0x21, 0x77 }, "QSN3800-3 ", 7409 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 }, 7410 }, 7411 { /* Gore 5m 24awg Eq */ 7412 { 0x00, 0x21, 0x77 }, "QSN7000-5 ", 7413 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 }, 7414 }, 7415 { /* Gore 7m 24awg Eq */ 7416 { 0x00, 0x21, 0x77 }, "QSN7000-7 ", 7417 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 }, 7418 }, 7419 { /* Gore 5m 26awg Eq */ 7420 { 0x00, 0x21, 0x77 }, "QSN7600-5 ", 7421 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 }, 7422 }, 7423 { /* Gore 7m 26awg Eq */ 7424 { 0x00, 0x21, 0x77 }, "QSN7600-7 ", 7425 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 }, 7426 }, 7427 { /* Intersil 12m 24awg Active */ 7428 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224", 7429 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 }, 7430 }, 7431 { /* Intersil 10m 28awg Active */ 7432 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028", 7433 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 }, 7434 }, 7435 { /* Intersil 7m 30awg Active */ 7436 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730", 7437 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 }, 7438 }, 7439 { /* Intersil 5m 32awg Active */ 7440 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532", 7441 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 }, 7442 }, 7443 { /* Intersil Default Active */ 7444 { 0x00, 0x30, 0xB4 }, NULL, 7445 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 }, 7446 }, 7447 { /* Luxtera 20m Active Optical */ 7448 { 0x00, 0x25, 0x63 }, NULL, 7449 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 }, 7450 }, 7451 { /* Molex 1M Cu loopback */ 7452 { 0x00, 0x09, 0x3A }, "74763-0025 ", 7453 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, 7454 }, 7455 { /* Molex 2m 28awg NoEq */ 7456 { 0x00, 0x09, 0x3A }, "74757-2201 ", 7457 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 }, 7458 }, 7459 }; 7460 7461 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = { 7462 /* amp, pre, main, post */ 7463 { 2, 2, 15, 6 }, /* Loopback */ 7464 { 0, 0, 0, 1 }, /* 2 dB */ 7465 { 0, 0, 0, 2 }, /* 3 dB */ 7466 { 0, 0, 0, 3 }, /* 4 dB */ 7467 { 0, 0, 0, 4 }, /* 5 dB */ 7468 { 0, 0, 0, 5 }, /* 6 dB */ 7469 { 0, 0, 0, 6 }, /* 7 dB */ 7470 { 0, 0, 0, 7 }, /* 8 dB */ 7471 { 0, 0, 0, 8 }, /* 9 dB */ 7472 { 0, 0, 0, 9 }, /* 10 dB */ 7473 { 0, 0, 0, 10 }, /* 11 dB */ 7474 { 0, 0, 0, 11 }, /* 12 dB */ 7475 { 0, 0, 0, 12 }, /* 13 dB */ 7476 { 0, 0, 0, 13 }, /* 14 dB */ 7477 { 0, 0, 0, 14 }, /* 15 dB */ 7478 { 0, 0, 0, 15 }, /* 16 dB */ 7479 }; 7480 7481 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = { 7482 /* amp, pre, main, post */ 7483 { 2, 2, 15, 6 }, /* Loopback */ 7484 { 0, 0, 0, 8 }, /* 2 dB */ 7485 { 0, 0, 0, 8 }, /* 3 dB */ 7486 { 0, 0, 0, 9 }, /* 4 dB */ 7487 { 0, 0, 0, 9 }, /* 5 dB */ 7488 { 0, 0, 0, 10 }, /* 6 dB */ 7489 { 0, 0, 0, 10 }, /* 7 dB */ 7490 { 0, 0, 0, 11 }, /* 8 dB */ 7491 { 0, 0, 0, 11 }, /* 9 dB */ 7492 { 0, 0, 0, 12 }, /* 10 dB */ 7493 { 0, 0, 0, 12 }, /* 11 dB */ 7494 { 0, 0, 0, 13 }, /* 12 dB */ 7495 { 0, 0, 0, 13 }, /* 13 dB */ 7496 { 0, 0, 0, 14 }, /* 14 dB */ 7497 { 0, 0, 0, 14 }, /* 15 dB */ 7498 { 0, 0, 0, 15 }, /* 16 dB */ 7499 }; 7500 7501 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = { 7502 /* amp, pre, main, post */ 7503 { 2, 2, 15, 6 }, /* Loopback */ 7504 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */ 7505 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */ 7506 { 0, 1, 0, 11 }, /* 4 dB */ 7507 { 0, 1, 0, 13 }, /* 5 dB */ 7508 { 0, 1, 0, 15 }, /* 6 dB */ 7509 { 0, 1, 3, 15 }, /* 7 dB */ 7510 { 0, 1, 7, 15 }, /* 8 dB */ 7511 { 0, 1, 7, 15 }, /* 9 dB */ 7512 { 0, 1, 8, 15 }, /* 10 dB */ 7513 { 0, 1, 9, 15 }, /* 11 dB */ 7514 { 0, 1, 10, 15 }, /* 12 dB */ 7515 { 0, 2, 6, 15 }, /* 13 dB */ 7516 { 0, 2, 7, 15 }, /* 14 dB */ 7517 { 0, 2, 8, 15 }, /* 15 dB */ 7518 { 0, 2, 9, 15 }, /* 16 dB */ 7519 }; 7520 7521 /* 7522 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ. 7523 * These are mostly used for mez cards going through connectors 7524 * and backplane traces, but can be used to add other "unusual" 7525 * table values as well. 7526 */ 7527 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = { 7528 /* amp, pre, main, post */ 7529 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7530 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7531 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7532 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7533 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */ 7534 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */ 7535 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ 7536 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ 7537 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ 7538 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ 7539 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ 7540 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ 7541 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ 7542 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ 7543 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ 7544 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ 7545 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ 7546 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ 7547 }; 7548 7549 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = { 7550 /* amp, pre, main, post */ 7551 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7552 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7553 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7554 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7555 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */ 7556 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */ 7557 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ 7558 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ 7559 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ 7560 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ 7561 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ 7562 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ 7563 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ 7564 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ 7565 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ 7566 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ 7567 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ 7568 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ 7569 }; 7570 7571 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = { 7572 /* amp, pre, main, post */ 7573 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */ 7574 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */ 7575 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */ 7576 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */ 7577 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */ 7578 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ 7579 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */ 7580 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */ 7581 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */ 7582 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */ 7583 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */ 7584 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */ 7585 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */ 7586 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */ 7587 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */ 7588 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */ 7589 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */ 7590 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */ 7591 }; 7592 7593 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = { 7594 /* amp, pre, main, post */ 7595 { 0, 0, 0, 0 }, /* QME7342 mfg settings */ 7596 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */ 7597 }; 7598 7599 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 7600 unsigned atten) 7601 { 7602 /* 7603 * The attenuation table starts at 2dB for entry 1, 7604 * with entry 0 being the loopback entry. 7605 */ 7606 if (atten <= 2) 7607 atten = 1; 7608 else if (atten > TXDDS_TABLE_SZ) 7609 atten = TXDDS_TABLE_SZ - 1; 7610 else 7611 atten--; 7612 return txdds + atten; 7613 } 7614 7615 /* 7616 * if override is set, the module parameter txselect has a value 7617 * for this specific port, so use it, rather than our normal mechanism. 7618 */ 7619 static void find_best_ent(struct qib_pportdata *ppd, 7620 const struct txdds_ent **sdr_dds, 7621 const struct txdds_ent **ddr_dds, 7622 const struct txdds_ent **qdr_dds, int override) 7623 { 7624 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache; 7625 int idx; 7626 7627 /* Search table of known cables */ 7628 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) { 7629 const struct vendor_txdds_ent *v = vendor_txdds + idx; 7630 7631 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) && 7632 (!v->partnum || 7633 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) { 7634 *sdr_dds = &v->sdr; 7635 *ddr_dds = &v->ddr; 7636 *qdr_dds = &v->qdr; 7637 return; 7638 } 7639 } 7640 7641 /* Active cables don't have attenuation so we only set SERDES 7642 * settings to account for the attenuation of the board traces. */ 7643 if (!override && QSFP_IS_ACTIVE(qd->tech)) { 7644 *sdr_dds = txdds_sdr + ppd->dd->board_atten; 7645 *ddr_dds = txdds_ddr + ppd->dd->board_atten; 7646 *qdr_dds = txdds_qdr + ppd->dd->board_atten; 7647 return; 7648 } 7649 7650 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] || 7651 qd->atten[1])) { 7652 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]); 7653 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]); 7654 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]); 7655 return; 7656 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) { 7657 /* 7658 * If we have no (or incomplete) data from the cable 7659 * EEPROM, or no QSFP, or override is set, use the 7660 * module parameter value to index into the attentuation 7661 * table. 7662 */ 7663 idx = ppd->cpspec->no_eep; 7664 *sdr_dds = &txdds_sdr[idx]; 7665 *ddr_dds = &txdds_ddr[idx]; 7666 *qdr_dds = &txdds_qdr[idx]; 7667 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { 7668 /* similar to above, but index into the "extra" table. */ 7669 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ; 7670 *sdr_dds = &txdds_extra_sdr[idx]; 7671 *ddr_dds = &txdds_extra_ddr[idx]; 7672 *qdr_dds = &txdds_extra_qdr[idx]; 7673 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && 7674 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 7675 TXDDS_MFG_SZ)) { 7676 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); 7677 pr_info("IB%u:%u use idx %u into txdds_mfg\n", 7678 ppd->dd->unit, ppd->port, idx); 7679 *sdr_dds = &txdds_extra_mfg[idx]; 7680 *ddr_dds = &txdds_extra_mfg[idx]; 7681 *qdr_dds = &txdds_extra_mfg[idx]; 7682 } else { 7683 /* this shouldn't happen, it's range checked */ 7684 *sdr_dds = txdds_sdr + qib_long_atten; 7685 *ddr_dds = txdds_ddr + qib_long_atten; 7686 *qdr_dds = txdds_qdr + qib_long_atten; 7687 } 7688 } 7689 7690 static void init_txdds_table(struct qib_pportdata *ppd, int override) 7691 { 7692 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 7693 struct txdds_ent *dds; 7694 int idx; 7695 int single_ent = 0; 7696 7697 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override); 7698 7699 /* for mez cards or override, use the selected value for all entries */ 7700 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) 7701 single_ent = 1; 7702 7703 /* Fill in the first entry with the best entry found. */ 7704 set_txdds(ppd, 0, sdr_dds); 7705 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds); 7706 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds); 7707 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 7708 QIBL_LINKACTIVE)) { 7709 dds = (struct txdds_ent *)(ppd->link_speed_active == 7710 QIB_IB_QDR ? qdr_dds : 7711 (ppd->link_speed_active == 7712 QIB_IB_DDR ? ddr_dds : sdr_dds)); 7713 write_tx_serdes_param(ppd, dds); 7714 } 7715 7716 /* Fill in the remaining entries with the default table values. */ 7717 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) { 7718 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx); 7719 set_txdds(ppd, idx + TXDDS_TABLE_SZ, 7720 single_ent ? ddr_dds : txdds_ddr + idx); 7721 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ, 7722 single_ent ? qdr_dds : txdds_qdr + idx); 7723 } 7724 } 7725 7726 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl) 7727 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg) 7728 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy) 7729 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address) 7730 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data) 7731 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read) 7732 #define AHB_TRANS_TRIES 10 7733 7734 /* 7735 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4, 7736 * 5=subsystem which is why most calls have "chan + chan >> 1" 7737 * for the channel argument. 7738 */ 7739 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, 7740 u32 data, u32 mask) 7741 { 7742 u32 rd_data, wr_data, sz_mask; 7743 u64 trans, acc, prev_acc; 7744 u32 ret = 0xBAD0BAD; 7745 int tries; 7746 7747 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); 7748 /* From this point on, make sure we return access */ 7749 acc = (quad << 1) | 1; 7750 qib_write_kreg(dd, KR_AHB_ACC, acc); 7751 7752 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7753 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7754 if (trans & AHB_TRANS_RDY) 7755 break; 7756 } 7757 if (tries >= AHB_TRANS_TRIES) { 7758 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); 7759 goto bail; 7760 } 7761 7762 /* If mask is not all 1s, we need to read, but different SerDes 7763 * entities have different sizes 7764 */ 7765 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1; 7766 wr_data = data & mask & sz_mask; 7767 if ((~mask & sz_mask) != 0) { 7768 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7769 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7770 7771 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7772 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7773 if (trans & AHB_TRANS_RDY) 7774 break; 7775 } 7776 if (tries >= AHB_TRANS_TRIES) { 7777 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", 7778 AHB_TRANS_TRIES); 7779 goto bail; 7780 } 7781 /* Re-read in case host split reads and read data first */ 7782 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7783 rd_data = (uint32_t)(trans >> AHB_DATA_LSB); 7784 wr_data |= (rd_data & ~mask & sz_mask); 7785 } 7786 7787 /* If mask is not zero, we need to write. */ 7788 if (mask & sz_mask) { 7789 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7790 trans |= ((uint64_t)wr_data << AHB_DATA_LSB); 7791 trans |= AHB_WR; 7792 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7793 7794 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7795 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7796 if (trans & AHB_TRANS_RDY) 7797 break; 7798 } 7799 if (tries >= AHB_TRANS_TRIES) { 7800 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", 7801 AHB_TRANS_TRIES); 7802 goto bail; 7803 } 7804 } 7805 ret = wr_data; 7806 bail: 7807 qib_write_kreg(dd, KR_AHB_ACC, prev_acc); 7808 return ret; 7809 } 7810 7811 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data, 7812 unsigned mask) 7813 { 7814 struct qib_devdata *dd = ppd->dd; 7815 int chan; 7816 7817 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7818 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, 7819 data, mask); 7820 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, 7821 0, 0); 7822 } 7823 } 7824 7825 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) 7826 { 7827 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl); 7828 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN); 7829 7830 if (enable && !state) { 7831 pr_info("IB%u:%u Turning LOS on\n", 7832 ppd->dd->unit, ppd->port); 7833 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7834 } else if (!enable && state) { 7835 pr_info("IB%u:%u Turning LOS off\n", 7836 ppd->dd->unit, ppd->port); 7837 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7838 } 7839 qib_write_kreg_port(ppd, krp_serdesctrl, data); 7840 } 7841 7842 static int serdes_7322_init(struct qib_pportdata *ppd) 7843 { 7844 int ret = 0; 7845 7846 if (ppd->dd->cspec->r1) 7847 ret = serdes_7322_init_old(ppd); 7848 else 7849 ret = serdes_7322_init_new(ppd); 7850 return ret; 7851 } 7852 7853 static int serdes_7322_init_old(struct qib_pportdata *ppd) 7854 { 7855 u32 le_val; 7856 7857 /* 7858 * Initialize the Tx DDS tables. Also done every QSFP event, 7859 * for adapters with QSFP 7860 */ 7861 init_txdds_table(ppd, 0); 7862 7863 /* ensure no tx overrides from earlier driver loads */ 7864 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7865 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7866 reset_tx_deemphasis_override)); 7867 7868 /* Patch some SerDes defaults to "Better for IB" */ 7869 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */ 7870 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7871 7872 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7873 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7874 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */ 7875 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6)); 7876 7877 /* May be overridden in qsfp_7322_event */ 7878 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7879 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7880 7881 /* enable LE1 adaptation for all but QME, which is disabled */ 7882 le_val = IS_QME(ppd->dd) ? 0 : 1; 7883 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5)); 7884 7885 /* Clear cmode-override, may be set from older driver */ 7886 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7887 7888 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */ 7889 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8)); 7890 7891 /* setup LoS params; these are subsystem, so chan == 5 */ 7892 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7893 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7894 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7895 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7896 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7897 7898 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7899 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7900 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7901 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7902 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7903 7904 /* LoS filter select enabled */ 7905 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7906 7907 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7908 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7909 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7910 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7911 7912 serdes_7322_los_enable(ppd, 1); 7913 7914 /* rxbistena; set 0 to avoid effects of it switch later */ 7915 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); 7916 7917 /* Configure 4 DFE taps, and only they adapt */ 7918 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0)); 7919 7920 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7921 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7922 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7923 7924 /* 7925 * Set receive adaptation mode. SDR and DDR adaptation are 7926 * always on, and QDR is initially enabled; later disabled. 7927 */ 7928 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7929 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7930 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7931 ppd->dd->cspec->r1 ? 7932 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7933 ppd->cpspec->qdr_dfe_on = 1; 7934 7935 /* FLoop LOS gate: PPM filter enabled */ 7936 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7937 7938 /* rx offset center enabled */ 7939 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4); 7940 7941 if (!ppd->dd->cspec->r1) { 7942 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12); 7943 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8); 7944 } 7945 7946 /* Set the frequency loop bandwidth to 15 */ 7947 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); 7948 7949 return 0; 7950 } 7951 7952 static int serdes_7322_init_new(struct qib_pportdata *ppd) 7953 { 7954 unsigned long tend; 7955 u32 le_val, rxcaldone; 7956 int chan, chan_done = (1 << SERDES_CHANS) - 1; 7957 7958 /* Clear cmode-override, may be set from older driver */ 7959 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7960 7961 /* ensure no tx overrides from earlier driver loads */ 7962 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7963 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7964 reset_tx_deemphasis_override)); 7965 7966 /* START OF LSI SUGGESTED SERDES BRINGUP */ 7967 /* Reset - Calibration Setup */ 7968 /* Stop DFE adaptaion */ 7969 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1)); 7970 /* Disable LE1 */ 7971 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5)); 7972 /* Disable autoadapt for LE1 */ 7973 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15)); 7974 /* Disable LE2 */ 7975 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6)); 7976 /* Disable VGA */ 7977 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7978 /* Disable AFE Offset Cancel */ 7979 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12)); 7980 /* Disable Timing Loop */ 7981 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3)); 7982 /* Disable Frequency Loop */ 7983 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4)); 7984 /* Disable Baseline Wander Correction */ 7985 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13)); 7986 /* Disable RX Calibration */ 7987 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7988 /* Disable RX Offset Calibration */ 7989 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4)); 7990 /* Select BB CDR */ 7991 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15)); 7992 /* CDR Step Size */ 7993 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8)); 7994 /* Enable phase Calibration */ 7995 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5)); 7996 /* DFE Bandwidth [2:14-12] */ 7997 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12)); 7998 /* DFE Config (4 taps only) */ 7999 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0)); 8000 /* Gain Loop Bandwidth */ 8001 if (!ppd->dd->cspec->r1) { 8002 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12)); 8003 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8)); 8004 } else { 8005 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11)); 8006 } 8007 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ 8008 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ 8009 /* Data Rate Select [5:7-6] (leave as default) */ 8010 /* RX Parallel Word Width [3:10-8] (leave as default) */ 8011 8012 /* RX REST */ 8013 /* Single- or Multi-channel reset */ 8014 /* RX Analog reset */ 8015 /* RX Digital reset */ 8016 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13)); 8017 msleep(20); 8018 /* RX Analog reset */ 8019 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14)); 8020 msleep(20); 8021 /* RX Digital reset */ 8022 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13)); 8023 msleep(20); 8024 8025 /* setup LoS params; these are subsystem, so chan == 5 */ 8026 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 8027 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 8028 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 8029 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 8030 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 8031 8032 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 8033 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 8034 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 8035 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 8036 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 8037 8038 /* LoS filter select enabled */ 8039 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 8040 8041 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 8042 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 8043 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 8044 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 8045 8046 /* Turn on LOS on initial SERDES init */ 8047 serdes_7322_los_enable(ppd, 1); 8048 /* FLoop LOS gate: PPM filter enabled */ 8049 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 8050 8051 /* RX LATCH CALIBRATION */ 8052 /* Enable Eyefinder Phase Calibration latch */ 8053 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0)); 8054 /* Enable RX Offset Calibration latch */ 8055 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4)); 8056 msleep(20); 8057 /* Start Calibration */ 8058 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10)); 8059 tend = jiffies + msecs_to_jiffies(500); 8060 while (chan_done && !time_is_before_jiffies(tend)) { 8061 msleep(20); 8062 for (chan = 0; chan < SERDES_CHANS; ++chan) { 8063 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 8064 (chan + (chan >> 1)), 8065 25, 0, 0); 8066 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 && 8067 (~chan_done & (1 << chan)) == 0) 8068 chan_done &= ~(1 << chan); 8069 } 8070 } 8071 if (chan_done) { 8072 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n", 8073 IBSD(ppd->hw_pidx), chan_done); 8074 } else { 8075 for (chan = 0; chan < SERDES_CHANS; ++chan) { 8076 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 8077 (chan + (chan >> 1)), 8078 25, 0, 0); 8079 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0) 8080 pr_info("Serdes %d chan %d calibration failed\n", 8081 IBSD(ppd->hw_pidx), chan); 8082 } 8083 } 8084 8085 /* Turn off Calibration */ 8086 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 8087 msleep(20); 8088 8089 /* BRING RX UP */ 8090 /* Set LE2 value (May be overridden in qsfp_7322_event) */ 8091 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 8092 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 8093 /* Set LE2 Loop bandwidth */ 8094 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5)); 8095 /* Enable LE2 */ 8096 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6)); 8097 msleep(20); 8098 /* Enable H0 only */ 8099 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1)); 8100 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 8101 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 8102 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 8103 /* Enable VGA */ 8104 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 8105 msleep(20); 8106 /* Set Frequency Loop Bandwidth */ 8107 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5)); 8108 /* Enable Frequency Loop */ 8109 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4)); 8110 /* Set Timing Loop Bandwidth */ 8111 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 8112 /* Enable Timing Loop */ 8113 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3)); 8114 msleep(50); 8115 /* Enable DFE 8116 * Set receive adaptation mode. SDR and DDR adaptation are 8117 * always on, and QDR is initially enabled; later disabled. 8118 */ 8119 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 8120 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 8121 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 8122 ppd->dd->cspec->r1 ? 8123 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 8124 ppd->cpspec->qdr_dfe_on = 1; 8125 /* Disable LE1 */ 8126 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5)); 8127 /* Disable auto adapt for LE1 */ 8128 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15)); 8129 msleep(20); 8130 /* Enable AFE Offset Cancel */ 8131 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12)); 8132 /* Enable Baseline Wander Correction */ 8133 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13)); 8134 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 8135 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 8136 /* VGA output common mode */ 8137 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2)); 8138 8139 /* 8140 * Initialize the Tx DDS tables. Also done every QSFP event, 8141 * for adapters with QSFP 8142 */ 8143 init_txdds_table(ppd, 0); 8144 8145 return 0; 8146 } 8147 8148 /* start adjust QMH serdes parameters */ 8149 8150 static void set_man_code(struct qib_pportdata *ppd, int chan, int code) 8151 { 8152 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8153 9, code << 9, 0x3f << 9); 8154 } 8155 8156 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan, 8157 int enable, u32 tapenable) 8158 { 8159 if (enable) 8160 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8161 1, 3 << 10, 0x1f << 10); 8162 else 8163 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8164 1, 0, 0x1f << 10); 8165 } 8166 8167 /* Set clock to 1, 0, 1, 0 */ 8168 static void clock_man(struct qib_pportdata *ppd, int chan) 8169 { 8170 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8171 4, 0x4000, 0x4000); 8172 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8173 4, 0, 0x4000); 8174 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8175 4, 0x4000, 0x4000); 8176 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 8177 4, 0, 0x4000); 8178 } 8179 8180 /* 8181 * write the current Tx serdes pre,post,main,amp settings into the serdes. 8182 * The caller must pass the settings appropriate for the current speed, 8183 * or not care if they are correct for the current speed. 8184 */ 8185 static void write_tx_serdes_param(struct qib_pportdata *ppd, 8186 struct txdds_ent *txdds) 8187 { 8188 u64 deemph; 8189 8190 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override); 8191 /* field names for amp, main, post, pre, respectively */ 8192 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | 8193 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | 8194 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | 8195 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); 8196 8197 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8198 tx_override_deemphasis_select); 8199 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8200 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8201 txampcntl_d2a); 8202 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8203 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8204 txc0_ena); 8205 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8206 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8207 txcp1_ena); 8208 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8209 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 8210 txcn1_ena); 8211 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph); 8212 } 8213 8214 /* 8215 * Set the parameters for mez cards on link bounce, so they are 8216 * always exactly what was requested. Similar logic to init_txdds 8217 * but does just the serdes. 8218 */ 8219 static void adj_tx_serdes(struct qib_pportdata *ppd) 8220 { 8221 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 8222 struct txdds_ent *dds; 8223 8224 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1); 8225 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ? 8226 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ? 8227 ddr_dds : sdr_dds)); 8228 write_tx_serdes_param(ppd, dds); 8229 } 8230 8231 /* set QDR forced value for H1, if needed */ 8232 static void force_h1(struct qib_pportdata *ppd) 8233 { 8234 int chan; 8235 8236 ppd->cpspec->qdr_reforce = 0; 8237 if (!ppd->dd->cspec->r1) 8238 return; 8239 8240 for (chan = 0; chan < SERDES_CHANS; chan++) { 8241 set_man_mode_h1(ppd, chan, 1, 0); 8242 set_man_code(ppd, chan, ppd->cpspec->h1_val); 8243 clock_man(ppd, chan); 8244 set_man_mode_h1(ppd, chan, 0, 0); 8245 } 8246 } 8247 8248 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN) 8249 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en) 8250 8251 #define R_OPCODE_LSB 3 8252 #define R_OP_NOP 0 8253 #define R_OP_SHIFT 2 8254 #define R_OP_UPDATE 3 8255 #define R_TDI_LSB 2 8256 #define R_TDO_LSB 1 8257 #define R_RDY 1 8258 8259 static int qib_r_grab(struct qib_devdata *dd) 8260 { 8261 u64 val = SJA_EN; 8262 8263 qib_write_kreg(dd, kr_r_access, val); 8264 qib_read_kreg32(dd, kr_scratch); 8265 return 0; 8266 } 8267 8268 /* qib_r_wait_for_rdy() not only waits for the ready bit, it 8269 * returns the current state of R_TDO 8270 */ 8271 static int qib_r_wait_for_rdy(struct qib_devdata *dd) 8272 { 8273 u64 val; 8274 int timeout; 8275 8276 for (timeout = 0; timeout < 100 ; ++timeout) { 8277 val = qib_read_kreg32(dd, kr_r_access); 8278 if (val & R_RDY) 8279 return (val >> R_TDO_LSB) & 1; 8280 } 8281 return -1; 8282 } 8283 8284 static int qib_r_shift(struct qib_devdata *dd, int bisten, 8285 int len, u8 *inp, u8 *outp) 8286 { 8287 u64 valbase, val; 8288 int ret, pos; 8289 8290 valbase = SJA_EN | (bisten << BISTEN_LSB) | 8291 (R_OP_SHIFT << R_OPCODE_LSB); 8292 ret = qib_r_wait_for_rdy(dd); 8293 if (ret < 0) 8294 goto bail; 8295 for (pos = 0; pos < len; ++pos) { 8296 val = valbase; 8297 if (outp) { 8298 outp[pos >> 3] &= ~(1 << (pos & 7)); 8299 outp[pos >> 3] |= (ret << (pos & 7)); 8300 } 8301 if (inp) { 8302 int tdi = inp[pos >> 3] >> (pos & 7); 8303 8304 val |= ((tdi & 1) << R_TDI_LSB); 8305 } 8306 qib_write_kreg(dd, kr_r_access, val); 8307 qib_read_kreg32(dd, kr_scratch); 8308 ret = qib_r_wait_for_rdy(dd); 8309 if (ret < 0) 8310 break; 8311 } 8312 /* Restore to NOP between operations. */ 8313 val = SJA_EN | (bisten << BISTEN_LSB); 8314 qib_write_kreg(dd, kr_r_access, val); 8315 qib_read_kreg32(dd, kr_scratch); 8316 ret = qib_r_wait_for_rdy(dd); 8317 8318 if (ret >= 0) 8319 ret = pos; 8320 bail: 8321 return ret; 8322 } 8323 8324 static int qib_r_update(struct qib_devdata *dd, int bisten) 8325 { 8326 u64 val; 8327 int ret; 8328 8329 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB); 8330 ret = qib_r_wait_for_rdy(dd); 8331 if (ret >= 0) { 8332 qib_write_kreg(dd, kr_r_access, val); 8333 qib_read_kreg32(dd, kr_scratch); 8334 } 8335 return ret; 8336 } 8337 8338 #define BISTEN_PORT_SEL 15 8339 #define LEN_PORT_SEL 625 8340 #define BISTEN_AT 17 8341 #define LEN_AT 156 8342 #define BISTEN_ETM 16 8343 #define LEN_ETM 632 8344 8345 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE) 8346 8347 /* these are common for all IB port use cases. */ 8348 static u8 reset_at[BIT2BYTE(LEN_AT)] = { 8349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 8351 }; 8352 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = { 8353 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8354 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8355 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e, 8356 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7, 8357 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70, 8358 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00, 8359 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8360 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 8361 }; 8362 static u8 at[BIT2BYTE(LEN_AT)] = { 8363 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 8364 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 8365 }; 8366 8367 /* used for IB1 or IB2, only one in use */ 8368 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = { 8369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8370 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8372 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00, 8373 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8374 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03, 8375 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00, 8376 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 8377 }; 8378 8379 /* used when both IB1 and IB2 are in use */ 8380 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = { 8381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 8383 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 8384 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05, 8385 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 8386 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07, 8387 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00, 8388 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 8389 }; 8390 8391 /* used when only IB1 is in use */ 8392 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = { 8393 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 8394 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 8395 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 8396 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 8397 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 8398 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 8399 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 8400 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 8401 }; 8402 8403 /* used when only IB2 is in use */ 8404 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = { 8405 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39, 8406 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32, 8407 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 8408 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 8409 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32, 8410 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 8411 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 8412 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 8413 }; 8414 8415 /* used when both IB1 and IB2 are in use */ 8416 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = { 8417 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 8418 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 8419 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 8420 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 8421 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 8422 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a, 8423 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 8424 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 8425 }; 8426 8427 /* 8428 * Do setup to properly handle IB link recovery; if port is zero, we 8429 * are initializing to cover both ports; otherwise we are initializing 8430 * to cover a single port card, or the port has reached INIT and we may 8431 * need to switch coverage types. 8432 */ 8433 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both) 8434 { 8435 u8 *portsel, *etm; 8436 struct qib_devdata *dd = ppd->dd; 8437 8438 if (!ppd->dd->cspec->r1) 8439 return; 8440 if (!both) { 8441 dd->cspec->recovery_ports_initted++; 8442 ppd->cpspec->recovery_init = 1; 8443 } 8444 if (!both && dd->cspec->recovery_ports_initted == 1) { 8445 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2; 8446 etm = atetm_1port; 8447 } else { 8448 portsel = portsel_2port; 8449 etm = atetm_2port; 8450 } 8451 8452 if (qib_r_grab(dd) < 0 || 8453 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || 8454 qib_r_update(dd, BISTEN_ETM) < 0 || 8455 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || 8456 qib_r_update(dd, BISTEN_AT) < 0 || 8457 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, 8458 portsel, NULL) < 0 || 8459 qib_r_update(dd, BISTEN_PORT_SEL) < 0 || 8460 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || 8461 qib_r_update(dd, BISTEN_AT) < 0 || 8462 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || 8463 qib_r_update(dd, BISTEN_ETM) < 0) 8464 qib_dev_err(dd, "Failed IB link recovery setup\n"); 8465 } 8466 8467 static void check_7322_rxe_status(struct qib_pportdata *ppd) 8468 { 8469 struct qib_devdata *dd = ppd->dd; 8470 u64 fmask; 8471 8472 if (dd->cspec->recovery_ports_initted != 1) 8473 return; /* rest doesn't apply to dualport */ 8474 qib_write_kreg(dd, kr_control, dd->control | 8475 SYM_MASK(Control, FreezeMode)); 8476 (void)qib_read_kreg64(dd, kr_scratch); 8477 udelay(3); /* ibcreset asserted 400ns, be sure that's over */ 8478 fmask = qib_read_kreg64(dd, kr_act_fmask); 8479 if (!fmask) { 8480 /* 8481 * require a powercycle before we'll work again, and make 8482 * sure we get no more interrupts, and don't turn off 8483 * freeze. 8484 */ 8485 ppd->dd->cspec->stay_in_freeze = 1; 8486 qib_7322_set_intr_state(ppd->dd, 0); 8487 qib_write_kreg(dd, kr_fmask, 0ULL); 8488 qib_dev_err(dd, "HCA unusable until powercycled\n"); 8489 return; /* eventually reset */ 8490 } 8491 8492 qib_write_kreg(ppd->dd, kr_hwerrclear, 8493 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); 8494 8495 /* don't do the full clear_freeze(), not needed for this */ 8496 qib_write_kreg(dd, kr_control, dd->control); 8497 qib_read_kreg32(dd, kr_scratch); 8498 /* take IBC out of reset */ 8499 if (ppd->link_speed_supported) { 8500 ppd->cpspec->ibcctrl_a &= 8501 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 8502 qib_write_kreg_port(ppd, krp_ibcctrl_a, 8503 ppd->cpspec->ibcctrl_a); 8504 qib_read_kreg32(dd, kr_scratch); 8505 if (ppd->lflags & QIBL_IB_LINK_DISABLED) 8506 qib_set_ib_7322_lstate(ppd, 0, 8507 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 8508 } 8509 } 8510