1 /* 2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 /* 34 * This file contains all of the code that is specific to the 35 * InfiniPath 7322 chip 36 */ 37 38 #include <linux/interrupt.h> 39 #include <linux/pci.h> 40 #include <linux/delay.h> 41 #include <linux/io.h> 42 #include <linux/jiffies.h> 43 #include <linux/module.h> 44 #include <rdma/ib_verbs.h> 45 #include <rdma/ib_smi.h> 46 47 #include "qib.h" 48 #include "qib_7322_regs.h" 49 #include "qib_qsfp.h" 50 51 #include "qib_mad.h" 52 53 static void qib_setup_7322_setextled(struct qib_pportdata *, u32); 54 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t); 55 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op); 56 static irqreturn_t qib_7322intr(int irq, void *data); 57 static irqreturn_t qib_7322bufavail(int irq, void *data); 58 static irqreturn_t sdma_intr(int irq, void *data); 59 static irqreturn_t sdma_idle_intr(int irq, void *data); 60 static irqreturn_t sdma_progress_intr(int irq, void *data); 61 static irqreturn_t sdma_cleanup_intr(int irq, void *data); 62 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32, 63 struct qib_ctxtdata *rcd); 64 static u8 qib_7322_phys_portstate(u64); 65 static u32 qib_7322_iblink_state(u64); 66 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 67 u16 linitcmd); 68 static void force_h1(struct qib_pportdata *); 69 static void adj_tx_serdes(struct qib_pportdata *); 70 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8); 71 static void qib_7322_mini_pcs_reset(struct qib_pportdata *); 72 73 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); 74 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); 75 static void serdes_7322_los_enable(struct qib_pportdata *, int); 76 static int serdes_7322_init_old(struct qib_pportdata *); 77 static int serdes_7322_init_new(struct qib_pportdata *); 78 79 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) 80 81 /* LE2 serdes values for different cases */ 82 #define LE2_DEFAULT 5 83 #define LE2_5m 4 84 #define LE2_QME 0 85 86 /* Below is special-purpose, so only really works for the IB SerDes blocks. */ 87 #define IBSD(hw_pidx) (hw_pidx + 2) 88 89 /* these are variables for documentation and experimentation purposes */ 90 static const unsigned rcv_int_timeout = 375; 91 static const unsigned rcv_int_count = 16; 92 static const unsigned sdma_idle_cnt = 64; 93 94 /* Time to stop altering Rx Equalization parameters, after link up. */ 95 #define RXEQ_DISABLE_MSECS 2500 96 97 /* 98 * Number of VLs we are configured to use (to allow for more 99 * credits per vl, etc.) 100 */ 101 ushort qib_num_cfg_vls = 2; 102 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO); 103 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 104 105 static ushort qib_chase = 1; 106 module_param_named(chase, qib_chase, ushort, S_IRUGO); 107 MODULE_PARM_DESC(chase, "Enable state chase handling"); 108 109 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */ 110 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO); 111 MODULE_PARM_DESC(long_attenuation, \ 112 "attenuation cutoff (dB) for long copper cable setup"); 113 114 static ushort qib_singleport; 115 module_param_named(singleport, qib_singleport, ushort, S_IRUGO); 116 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); 117 118 static ushort qib_krcvq01_no_msi; 119 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO); 120 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2"); 121 122 /* 123 * Receive header queue sizes 124 */ 125 static unsigned qib_rcvhdrcnt; 126 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); 127 MODULE_PARM_DESC(rcvhdrcnt, "receive header count"); 128 129 static unsigned qib_rcvhdrsize; 130 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); 131 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words"); 132 133 static unsigned qib_rcvhdrentsize; 134 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); 135 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words"); 136 137 #define MAX_ATTEN_LEN 64 /* plenty for any real system */ 138 /* for read back, default index is ~5m copper cable */ 139 static char txselect_list[MAX_ATTEN_LEN] = "10"; 140 static struct kparam_string kp_txselect = { 141 .string = txselect_list, 142 .maxlen = MAX_ATTEN_LEN 143 }; 144 static int setup_txselect(const char *, struct kernel_param *); 145 module_param_call(txselect, setup_txselect, param_get_string, 146 &kp_txselect, S_IWUSR | S_IRUGO); 147 MODULE_PARM_DESC(txselect, \ 148 "Tx serdes indices (for no QSFP or invalid QSFP data)"); 149 150 #define BOARD_QME7342 5 151 #define BOARD_QMH7342 6 152 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 153 BOARD_QMH7342) 154 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 155 BOARD_QME7342) 156 157 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64)) 158 159 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64))) 160 161 #define MASK_ACROSS(lsb, msb) \ 162 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb)) 163 164 #define SYM_RMASK(regname, fldname) ((u64) \ 165 QIB_7322_##regname##_##fldname##_RMASK) 166 167 #define SYM_MASK(regname, fldname) ((u64) \ 168 QIB_7322_##regname##_##fldname##_RMASK << \ 169 QIB_7322_##regname##_##fldname##_LSB) 170 171 #define SYM_FIELD(value, regname, fldname) ((u64) \ 172 (((value) >> SYM_LSB(regname, fldname)) & \ 173 SYM_RMASK(regname, fldname))) 174 175 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */ 176 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \ 177 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits)) 178 179 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask) 180 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask) 181 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask) 182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) 183 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port) 184 /* Below because most, but not all, fields of IntMask have that full suffix */ 185 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port) 186 187 188 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) 189 190 /* 191 * the size bits give us 2^N, in KB units. 0 marks as invalid, 192 * and 7 is reserved. We currently use only 2KB and 4KB 193 */ 194 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB 195 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */ 196 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */ 197 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */ 198 199 #define SendIBSLIDAssignMask \ 200 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 201 #define SendIBSLMCMask \ 202 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 203 204 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn) 205 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn) 206 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn) 207 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn) 208 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN) 209 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN) 210 211 #define _QIB_GPIO_SDA_NUM 1 212 #define _QIB_GPIO_SCL_NUM 0 213 #define QIB_EEPROM_WEN_NUM 14 214 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */ 215 216 /* HW counter clock is at 4nsec */ 217 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000 218 219 /* full speed IB port 1 only */ 220 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR) 221 #define PORT_SPD_CAP_SHIFT 3 222 223 /* full speed featuremask, both ports */ 224 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT)) 225 226 /* 227 * This file contains almost all the chip-specific register information and 228 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip. 229 */ 230 231 /* Use defines to tie machine-generated names to lower-case names */ 232 #define kr_contextcnt KREG_IDX(ContextCnt) 233 #define kr_control KREG_IDX(Control) 234 #define kr_counterregbase KREG_IDX(CntrRegBase) 235 #define kr_errclear KREG_IDX(ErrClear) 236 #define kr_errmask KREG_IDX(ErrMask) 237 #define kr_errstatus KREG_IDX(ErrStatus) 238 #define kr_extctrl KREG_IDX(EXTCtrl) 239 #define kr_extstatus KREG_IDX(EXTStatus) 240 #define kr_gpio_clear KREG_IDX(GPIOClear) 241 #define kr_gpio_mask KREG_IDX(GPIOMask) 242 #define kr_gpio_out KREG_IDX(GPIOOut) 243 #define kr_gpio_status KREG_IDX(GPIOStatus) 244 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl) 245 #define kr_debugportval KREG_IDX(DebugPortValueReg) 246 #define kr_fmask KREG_IDX(feature_mask) 247 #define kr_act_fmask KREG_IDX(active_feature_mask) 248 #define kr_hwerrclear KREG_IDX(HwErrClear) 249 #define kr_hwerrmask KREG_IDX(HwErrMask) 250 #define kr_hwerrstatus KREG_IDX(HwErrStatus) 251 #define kr_intclear KREG_IDX(IntClear) 252 #define kr_intmask KREG_IDX(IntMask) 253 #define kr_intredirect KREG_IDX(IntRedirect0) 254 #define kr_intstatus KREG_IDX(IntStatus) 255 #define kr_pagealign KREG_IDX(PageAlign) 256 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0) 257 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */ 258 #define kr_rcvegrbase KREG_IDX(RcvEgrBase) 259 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt) 260 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt) 261 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize) 262 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize) 263 #define kr_rcvtidbase KREG_IDX(RcvTIDBase) 264 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt) 265 #define kr_revision KREG_IDX(Revision) 266 #define kr_scratch KREG_IDX(Scratch) 267 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */ 268 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */ 269 #define kr_sendctrl KREG_IDX(SendCtrl) 270 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */ 271 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */ 272 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr) 273 #define kr_sendpiobufbase KREG_IDX(SendBufBase) 274 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt) 275 #define kr_sendpiosize KREG_IDX(SendBufSize) 276 #define kr_sendregbase KREG_IDX(SendRegBase) 277 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0) 278 #define kr_userregbase KREG_IDX(UserRegBase) 279 #define kr_intgranted KREG_IDX(Int_Granted) 280 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int) 281 #define kr_intblocked KREG_IDX(IntBlocked) 282 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG) 283 284 /* 285 * per-port kernel registers. Access only with qib_read_kreg_port() 286 * or qib_write_kreg_port() 287 */ 288 #define krp_errclear KREG_IBPORT_IDX(ErrClear) 289 #define krp_errmask KREG_IBPORT_IDX(ErrMask) 290 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus) 291 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0) 292 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit) 293 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID) 294 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig) 295 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA) 296 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB) 297 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC) 298 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA) 299 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB) 300 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus) 301 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0) 302 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl) 303 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey) 304 #define krp_psinterval KREG_IBPORT_IDX(PSInterval) 305 #define krp_psstart KREG_IBPORT_IDX(PSStart) 306 #define krp_psstat KREG_IBPORT_IDX(PSStat) 307 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP) 308 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl) 309 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt) 310 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA) 311 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0) 312 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15) 313 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl) 314 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl) 315 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase) 316 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0) 317 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1) 318 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2) 319 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0) 320 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1) 321 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2) 322 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt) 323 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead) 324 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr) 325 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt) 326 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen) 327 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld) 328 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt) 329 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus) 330 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail) 331 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom) 332 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign) 333 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask) 334 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX) 335 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD) 336 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE) 337 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl) 338 339 /* 340 * Per-context kernel registers. Access only with qib_read_kreg_ctxt() 341 * or qib_write_kreg_ctxt() 342 */ 343 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0) 344 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0) 345 346 /* 347 * TID Flow table, per context. Reduces 348 * number of hdrq updates to one per flow (or on errors). 349 * context 0 and 1 share same memory, but have distinct 350 * addresses. Since for now, we never use expected sends 351 * on kernel contexts, we don't worry about that (we initialize 352 * those entries for ctxt 0/1 on driver load twice, for example). 353 */ 354 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */ 355 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0)) 356 357 /* these are the error bits in the tid flows, and are W1C */ 358 #define TIDFLOW_ERRBITS ( \ 359 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \ 360 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \ 361 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \ 362 SYM_LSB(RcvTIDFlowTable0, SeqMismatch))) 363 364 /* Most (not all) Counters are per-IBport. 365 * Requires LBIntCnt is at offset 0 in the group 366 */ 367 #define CREG_IDX(regname) \ 368 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 369 370 #define crp_badformat CREG_IDX(RxVersionErrCnt) 371 #define crp_err_rlen CREG_IDX(RxLenErrCnt) 372 #define crp_erricrc CREG_IDX(RxICRCErrCnt) 373 #define crp_errlink CREG_IDX(RxLinkMalformCnt) 374 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt) 375 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt) 376 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt) 377 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt) 378 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt) 379 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt) 380 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt) 381 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt) 382 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt) 383 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt) 384 #define crp_pktrcv CREG_IDX(RxDataPktCnt) 385 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt) 386 #define crp_pktsend CREG_IDX(TxDataPktCnt) 387 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt) 388 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount) 389 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount) 390 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount) 391 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount) 392 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount) 393 #define crp_rcvebp CREG_IDX(RxEBPCnt) 394 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt) 395 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt) 396 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt) 397 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt) 398 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt) 399 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt) 400 #define crp_rxvlerr CREG_IDX(RxVlErrCnt) 401 #define crp_sendstall CREG_IDX(TxFlowStallCnt) 402 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt) 403 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt) 404 #define crp_txlenerr CREG_IDX(TxLenErrCnt) 405 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt) 406 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt) 407 #define crp_txunderrun CREG_IDX(TxUnderrunCnt) 408 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt) 409 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt) 410 #define crp_wordrcv CREG_IDX(RxDwordCnt) 411 #define crp_wordsend CREG_IDX(TxDwordCnt) 412 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut) 413 414 /* these are the (few) counters that are not port-specific */ 415 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \ 416 QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 417 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt) 418 #define cr_lbint CREG_DEVIDX(LBIntCnt) 419 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt) 420 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt) 421 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt) 422 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt) 423 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt) 424 425 /* no chip register for # of IB ports supported, so define */ 426 #define NUM_IB_PORTS 2 427 428 /* 1 VL15 buffer per hardware IB port, no register for this, so define */ 429 #define NUM_VL15_BUFS NUM_IB_PORTS 430 431 /* 432 * context 0 and 1 are special, and there is no chip register that 433 * defines this value, so we have to define it here. 434 * These are all allocated to either 0 or 1 for single port 435 * hardware configuration, otherwise each gets half 436 */ 437 #define KCTXT0_EGRCNT 2048 438 439 /* values for vl and port fields in PBC, 7322-specific */ 440 #define PBC_PORT_SEL_LSB 26 441 #define PBC_PORT_SEL_RMASK 1 442 #define PBC_VL_NUM_LSB 27 443 #define PBC_VL_NUM_RMASK 7 444 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */ 445 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */ 446 447 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = { 448 [IB_RATE_2_5_GBPS] = 16, 449 [IB_RATE_5_GBPS] = 8, 450 [IB_RATE_10_GBPS] = 4, 451 [IB_RATE_20_GBPS] = 2, 452 [IB_RATE_30_GBPS] = 2, 453 [IB_RATE_40_GBPS] = 1 454 }; 455 456 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive) 457 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive) 458 459 /* link training states, from IBC */ 460 #define IB_7322_LT_STATE_DISABLED 0x00 461 #define IB_7322_LT_STATE_LINKUP 0x01 462 #define IB_7322_LT_STATE_POLLACTIVE 0x02 463 #define IB_7322_LT_STATE_POLLQUIET 0x03 464 #define IB_7322_LT_STATE_SLEEPDELAY 0x04 465 #define IB_7322_LT_STATE_SLEEPQUIET 0x05 466 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08 467 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09 468 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a 469 #define IB_7322_LT_STATE_CFGIDLE 0x0b 470 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c 471 #define IB_7322_LT_STATE_TXREVLANES 0x0d 472 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e 473 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f 474 #define IB_7322_LT_STATE_CFGENH 0x10 475 #define IB_7322_LT_STATE_CFGTEST 0x11 476 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12 477 #define IB_7322_LT_STATE_CFGWAITENH 0x13 478 479 /* link state machine states from IBC */ 480 #define IB_7322_L_STATE_DOWN 0x0 481 #define IB_7322_L_STATE_INIT 0x1 482 #define IB_7322_L_STATE_ARM 0x2 483 #define IB_7322_L_STATE_ACTIVE 0x3 484 #define IB_7322_L_STATE_ACT_DEFER 0x4 485 486 static const u8 qib_7322_physportstate[0x20] = { 487 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED, 488 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP, 489 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL, 490 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL, 491 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP, 492 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP, 493 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN, 494 [IB_7322_LT_STATE_CFGRCVFCFG] = 495 IB_PHYSPORTSTATE_CFG_TRAIN, 496 [IB_7322_LT_STATE_CFGWAITRMT] = 497 IB_PHYSPORTSTATE_CFG_TRAIN, 498 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE, 499 [IB_7322_LT_STATE_RECOVERRETRAIN] = 500 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 501 [IB_7322_LT_STATE_RECOVERWAITRMT] = 502 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 503 [IB_7322_LT_STATE_RECOVERIDLE] = 504 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 505 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH, 506 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN, 507 [IB_7322_LT_STATE_CFGWAITRMTTEST] = 508 IB_PHYSPORTSTATE_CFG_TRAIN, 509 [IB_7322_LT_STATE_CFGWAITENH] = 510 IB_PHYSPORTSTATE_CFG_WAIT_ENH, 511 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN, 512 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN, 513 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN, 514 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN 515 }; 516 517 struct qib_chip_specific { 518 u64 __iomem *cregbase; 519 u64 *cntrs; 520 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */ 521 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */ 522 u64 main_int_mask; /* clear bits which have dedicated handlers */ 523 u64 int_enable_mask; /* for per port interrupts in single port mode */ 524 u64 errormask; 525 u64 hwerrmask; 526 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */ 527 u64 gpio_mask; /* shadow the gpio mask register */ 528 u64 extctrl; /* shadow the gpio output enable, etc... */ 529 u32 ncntrs; 530 u32 nportcntrs; 531 u32 cntrnamelen; 532 u32 portcntrnamelen; 533 u32 numctxts; 534 u32 rcvegrcnt; 535 u32 updthresh; /* current AvailUpdThld */ 536 u32 updthresh_dflt; /* default AvailUpdThld */ 537 u32 r1; 538 int irq; 539 u32 num_msix_entries; 540 u32 sdmabufcnt; 541 u32 lastbuf_for_pio; 542 u32 stay_in_freeze; 543 u32 recovery_ports_initted; 544 struct msix_entry *msix_entries; 545 void **msix_arg; 546 unsigned long *sendchkenable; 547 unsigned long *sendgrhchk; 548 unsigned long *sendibchk; 549 u32 rcvavail_timeout[18]; 550 char emsgbuf[128]; /* for device error interrupt msg buffer */ 551 }; 552 553 /* Table of entries in "human readable" form Tx Emphasis. */ 554 struct txdds_ent { 555 u8 amp; 556 u8 pre; 557 u8 main; 558 u8 post; 559 }; 560 561 struct vendor_txdds_ent { 562 u8 oui[QSFP_VOUI_LEN]; 563 u8 *partnum; 564 struct txdds_ent sdr; 565 struct txdds_ent ddr; 566 struct txdds_ent qdr; 567 }; 568 569 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); 570 571 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 572 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */ 573 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */ 574 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 575 576 #define H1_FORCE_VAL 8 577 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */ 578 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */ 579 580 /* The static and dynamic registers are paired, and the pairs indexed by spd */ 581 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \ 582 + ((spd) * 2)) 583 584 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */ 585 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */ 586 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */ 587 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */ 588 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */ 589 590 struct qib_chippport_specific { 591 u64 __iomem *kpregbase; 592 u64 __iomem *cpregbase; 593 u64 *portcntrs; 594 struct qib_pportdata *ppd; 595 wait_queue_head_t autoneg_wait; 596 struct delayed_work autoneg_work; 597 struct delayed_work ipg_work; 598 struct timer_list chase_timer; 599 /* 600 * these 5 fields are used to establish deltas for IB symbol 601 * errors and linkrecovery errors. They can be reported on 602 * some chips during link negotiation prior to INIT, and with 603 * DDR when faking DDR negotiations with non-IBTA switches. 604 * The chip counters are adjusted at driver unload if there is 605 * a non-zero delta. 606 */ 607 u64 ibdeltainprog; 608 u64 ibsymdelta; 609 u64 ibsymsnap; 610 u64 iblnkerrdelta; 611 u64 iblnkerrsnap; 612 u64 iblnkdownsnap; 613 u64 iblnkdowndelta; 614 u64 ibmalfdelta; 615 u64 ibmalfsnap; 616 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */ 617 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */ 618 unsigned long qdr_dfe_time; 619 unsigned long chase_end; 620 u32 autoneg_tries; 621 u32 recovery_init; 622 u32 qdr_dfe_on; 623 u32 qdr_reforce; 624 /* 625 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR. 626 * entry zero is unused, to simplify indexing 627 */ 628 u8 h1_val; 629 u8 no_eep; /* txselect table index to use if no qsfp info */ 630 u8 ipg_tries; 631 u8 ibmalfusesnap; 632 struct qib_qsfp_data qsfp_data; 633 char epmsgbuf[192]; /* for port error interrupt msg buffer */ 634 }; 635 636 static struct { 637 const char *name; 638 irq_handler_t handler; 639 int lsb; 640 int port; /* 0 if not port-specific, else port # */ 641 } irq_table[] = { 642 { QIB_DRV_NAME, qib_7322intr, -1, 0 }, 643 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail, 644 SYM_LSB(IntStatus, SendBufAvail), 0 }, 645 { QIB_DRV_NAME " (sdma 0)", sdma_intr, 646 SYM_LSB(IntStatus, SDmaInt_0), 1 }, 647 { QIB_DRV_NAME " (sdma 1)", sdma_intr, 648 SYM_LSB(IntStatus, SDmaInt_1), 2 }, 649 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr, 650 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 }, 651 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr, 652 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 }, 653 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr, 654 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 }, 655 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr, 656 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 }, 657 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr, 658 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 }, 659 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr, 660 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 }, 661 }; 662 663 /* ibcctrl bits */ 664 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 665 /* cycle through TS1/TS2 till OK */ 666 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2 667 /* wait for TS1, then go on */ 668 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3 669 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16 670 671 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */ 672 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ 673 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ 674 675 #define BLOB_7322_IBCHG 0x101 676 677 static inline void qib_write_kreg(const struct qib_devdata *dd, 678 const u32 regno, u64 value); 679 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32); 680 static void write_7322_initregs(struct qib_devdata *); 681 static void write_7322_init_portregs(struct qib_pportdata *); 682 static void setup_7322_link_recovery(struct qib_pportdata *, u32); 683 static void check_7322_rxe_status(struct qib_pportdata *); 684 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); 685 686 /** 687 * qib_read_ureg32 - read 32-bit virtualized per-context register 688 * @dd: device 689 * @regno: register number 690 * @ctxt: context number 691 * 692 * Return the contents of a register that is virtualized to be per context. 693 * Returns -1 on errors (not distinguishable from valid contents at 694 * runtime; we may add a separate error variable at some point). 695 */ 696 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, 697 enum qib_ureg regno, int ctxt) 698 { 699 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 700 return 0; 701 return readl(regno + (u64 __iomem *)( 702 (dd->ureg_align * ctxt) + (dd->userbase ? 703 (char __iomem *)dd->userbase : 704 (char __iomem *)dd->kregbase + dd->uregbase))); 705 } 706 707 /** 708 * qib_read_ureg - read virtualized per-context register 709 * @dd: device 710 * @regno: register number 711 * @ctxt: context number 712 * 713 * Return the contents of a register that is virtualized to be per context. 714 * Returns -1 on errors (not distinguishable from valid contents at 715 * runtime; we may add a separate error variable at some point). 716 */ 717 static inline u64 qib_read_ureg(const struct qib_devdata *dd, 718 enum qib_ureg regno, int ctxt) 719 { 720 721 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 722 return 0; 723 return readq(regno + (u64 __iomem *)( 724 (dd->ureg_align * ctxt) + (dd->userbase ? 725 (char __iomem *)dd->userbase : 726 (char __iomem *)dd->kregbase + dd->uregbase))); 727 } 728 729 /** 730 * qib_write_ureg - write virtualized per-context register 731 * @dd: device 732 * @regno: register number 733 * @value: value 734 * @ctxt: context 735 * 736 * Write the contents of a register that is virtualized to be per context. 737 */ 738 static inline void qib_write_ureg(const struct qib_devdata *dd, 739 enum qib_ureg regno, u64 value, int ctxt) 740 { 741 u64 __iomem *ubase; 742 if (dd->userbase) 743 ubase = (u64 __iomem *) 744 ((char __iomem *) dd->userbase + 745 dd->ureg_align * ctxt); 746 else 747 ubase = (u64 __iomem *) 748 (dd->uregbase + 749 (char __iomem *) dd->kregbase + 750 dd->ureg_align * ctxt); 751 752 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 753 writeq(value, &ubase[regno]); 754 } 755 756 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, 757 const u32 regno) 758 { 759 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 760 return -1; 761 return readl((u32 __iomem *) &dd->kregbase[regno]); 762 } 763 764 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, 765 const u32 regno) 766 { 767 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 768 return -1; 769 return readq(&dd->kregbase[regno]); 770 } 771 772 static inline void qib_write_kreg(const struct qib_devdata *dd, 773 const u32 regno, u64 value) 774 { 775 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 776 writeq(value, &dd->kregbase[regno]); 777 } 778 779 /* 780 * not many sanity checks for the port-specific kernel register routines, 781 * since they are only used when it's known to be safe. 782 */ 783 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd, 784 const u16 regno) 785 { 786 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) 787 return 0ULL; 788 return readq(&ppd->cpspec->kpregbase[regno]); 789 } 790 791 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd, 792 const u16 regno, u64 value) 793 { 794 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && 795 (ppd->dd->flags & QIB_PRESENT)) 796 writeq(value, &ppd->cpspec->kpregbase[regno]); 797 } 798 799 /** 800 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register 801 * @dd: the qlogic_ib device 802 * @regno: the register number to write 803 * @ctxt: the context containing the register 804 * @value: the value to write 805 */ 806 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, 807 const u16 regno, unsigned ctxt, 808 u64 value) 809 { 810 qib_write_kreg(dd, regno + ctxt, value); 811 } 812 813 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) 814 { 815 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 816 return 0; 817 return readq(&dd->cspec->cregbase[regno]); 818 819 820 } 821 822 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) 823 { 824 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 825 return 0; 826 return readl(&dd->cspec->cregbase[regno]); 827 828 829 } 830 831 static inline void write_7322_creg_port(const struct qib_pportdata *ppd, 832 u16 regno, u64 value) 833 { 834 if (ppd->cpspec && ppd->cpspec->cpregbase && 835 (ppd->dd->flags & QIB_PRESENT)) 836 writeq(value, &ppd->cpspec->cpregbase[regno]); 837 } 838 839 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd, 840 u16 regno) 841 { 842 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 843 !(ppd->dd->flags & QIB_PRESENT)) 844 return 0; 845 return readq(&ppd->cpspec->cpregbase[regno]); 846 } 847 848 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd, 849 u16 regno) 850 { 851 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 852 !(ppd->dd->flags & QIB_PRESENT)) 853 return 0; 854 return readl(&ppd->cpspec->cpregbase[regno]); 855 } 856 857 /* bits in Control register */ 858 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset) 859 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn) 860 861 /* bits in general interrupt regs */ 862 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask) 863 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17) 864 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB) 865 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask) 866 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17) 867 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB) 868 #define QIB_I_C_ERROR INT_MASK(Err) 869 870 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1)) 871 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail) 872 #define QIB_I_GPIO INT_MASK(AssertGPIO) 873 #define QIB_I_P_SDMAINT(pidx) \ 874 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 875 INT_MASK_P(SDmaProgress, pidx) | \ 876 INT_MASK_PM(SDmaCleanupDone, pidx)) 877 878 /* Interrupt bits that are "per port" */ 879 #define QIB_I_P_BITSEXTANT(pidx) \ 880 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \ 881 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 882 INT_MASK_P(SDmaProgress, pidx) | \ 883 INT_MASK_PM(SDmaCleanupDone, pidx)) 884 885 /* Interrupt bits that are common to a device */ 886 /* currently unused: QIB_I_SPIOSENT */ 887 #define QIB_I_C_BITSEXTANT \ 888 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \ 889 QIB_I_SPIOSENT | \ 890 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO) 891 892 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \ 893 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1)) 894 895 /* 896 * Error bits that are "per port". 897 */ 898 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged) 899 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr) 900 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr) 901 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr) 902 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr) 903 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr) 904 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr) 905 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr) 906 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr) 907 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr) 908 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr) 909 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr) 910 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr) 911 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr) 912 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr) 913 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr) 914 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr) 915 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr) 916 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr) 917 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr) 918 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr) 919 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr) 920 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr) 921 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr) 922 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr) 923 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr) 924 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr) 925 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr) 926 927 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr) 928 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr) 929 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr) 930 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr) 931 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr) 932 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr) 933 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr) 934 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr) 935 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr) 936 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr) 937 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr) 938 939 /* Error bits that are common to a device */ 940 #define QIB_E_RESET ERR_MASK(ResetNegated) 941 #define QIB_E_HARDWARE ERR_MASK(HardwareErr) 942 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr) 943 944 945 /* 946 * Per chip (rather than per-port) errors. Most either do 947 * nothing but trigger a print (because they self-recover, or 948 * always occur in tandem with other errors that handle the 949 * issue), or because they indicate errors with no recovery, 950 * but we want to know that they happened. 951 */ 952 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr) 953 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd) 954 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr) 955 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr) 956 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr) 957 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr) 958 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr) 959 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr) 960 961 /* SDMA chip errors (not per port) 962 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get 963 * the SDMAHALT error immediately, so we just print the dup error via the 964 * E_AUTO mechanism. This is true of most of the per-port fatal errors 965 * as well, but since this is port-independent, by definition, it's 966 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per 967 * packet send errors, and so are handled in the same manner as other 968 * per-packet errors. 969 */ 970 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err) 971 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr) 972 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr) 973 974 /* 975 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS 976 * it is used to print "common" packet errors. 977 */ 978 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\ 979 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\ 980 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\ 981 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 982 QIB_E_P_REBP) 983 984 /* Error Bits that Packet-related (Receive, per-port) */ 985 #define QIB_E_P_RPKTERRS (\ 986 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \ 987 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \ 988 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\ 989 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \ 990 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \ 991 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP) 992 993 /* 994 * Error bits that are Send-related (per port) 995 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling). 996 * All of these potentially need to have a buffer disarmed 997 */ 998 #define QIB_E_P_SPKTERRS (\ 999 QIB_E_P_SUNEXP_PKTNUM |\ 1000 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1001 QIB_E_P_SMAXPKTLEN |\ 1002 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 1003 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \ 1004 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL) 1005 1006 #define QIB_E_SPKTERRS ( \ 1007 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \ 1008 ERR_MASK_N(SendUnsupportedVLErr) | \ 1009 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT) 1010 1011 #define QIB_E_P_SDMAERRS ( \ 1012 QIB_E_P_SDMAHALT | \ 1013 QIB_E_P_SDMADESCADDRMISALIGN | \ 1014 QIB_E_P_SDMAUNEXPDATA | \ 1015 QIB_E_P_SDMAMISSINGDW | \ 1016 QIB_E_P_SDMADWEN | \ 1017 QIB_E_P_SDMARPYTAG | \ 1018 QIB_E_P_SDMA1STDESC | \ 1019 QIB_E_P_SDMABASE | \ 1020 QIB_E_P_SDMATAILOUTOFBOUND | \ 1021 QIB_E_P_SDMAOUTOFBOUND | \ 1022 QIB_E_P_SDMAGENMISMATCH) 1023 1024 /* 1025 * This sets some bits more than once, but makes it more obvious which 1026 * bits are not handled under other categories, and the repeat definition 1027 * is not a problem. 1028 */ 1029 #define QIB_E_P_BITSEXTANT ( \ 1030 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \ 1031 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \ 1032 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \ 1033 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \ 1034 ) 1035 1036 /* 1037 * These are errors that can occur when the link 1038 * changes state while a packet is being sent or received. This doesn't 1039 * cover things like EBP or VCRC that can be the result of a sending 1040 * having the link change state, so we receive a "known bad" packet. 1041 * All of these are "per port", so renamed: 1042 */ 1043 #define QIB_E_P_LINK_PKTERRS (\ 1044 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1045 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\ 1046 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\ 1047 QIB_E_P_RUNEXPCHAR) 1048 1049 /* 1050 * This sets some bits more than once, but makes it more obvious which 1051 * bits are not handled under other categories (such as QIB_E_SPKTERRS), 1052 * and the repeat definition is not a problem. 1053 */ 1054 #define QIB_E_C_BITSEXTANT (\ 1055 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\ 1056 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\ 1057 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE) 1058 1059 /* Likewise Neuter E_SPKT_ERRS_IGNORE */ 1060 #define E_SPKT_ERRS_IGNORE 0 1061 1062 #define QIB_EXTS_MEMBIST_DISABLED \ 1063 SYM_MASK(EXTStatus, MemBISTDisabled) 1064 #define QIB_EXTS_MEMBIST_ENDTEST \ 1065 SYM_MASK(EXTStatus, MemBISTEndTest) 1066 1067 #define QIB_E_SPIOARMLAUNCH \ 1068 ERR_MASK(SendArmLaunchErr) 1069 1070 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd) 1071 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd) 1072 1073 /* 1074 * IBTA_1_2 is set when multiple speeds are enabled (normal), 1075 * and also if forced QDR (only QDR enabled). It's enabled for the 1076 * forced QDR case so that scrambling will be enabled by the TS3 1077 * exchange, when supported by both sides of the link. 1078 */ 1079 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE) 1080 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED) 1081 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR) 1082 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) 1083 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) 1084 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \ 1085 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)) 1086 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR) 1087 1088 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod) 1089 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod) 1090 1091 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS) 1092 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1093 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1094 1095 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1096 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1097 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \ 1098 SYM_MASK(IBCCtrlB_0, HRTBT_ENB)) 1099 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \ 1100 SYM_LSB(IBCCtrlB_0, HRTBT_ENB)) 1101 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB) 1102 1103 #define IBA7322_REDIRECT_VEC_PER_REG 12 1104 1105 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En) 1106 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En) 1107 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En) 1108 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En) 1109 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En) 1110 1111 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */ 1112 1113 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \ 1114 .msg = #fldname , .sz = sizeof(#fldname) } 1115 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \ 1116 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) } 1117 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = { 1118 HWE_AUTO_P(IBSerdesPClkNotDetect, 1), 1119 HWE_AUTO_P(IBSerdesPClkNotDetect, 0), 1120 HWE_AUTO(PCIESerdesPClkNotDetect), 1121 HWE_AUTO(PowerOnBISTFailed), 1122 HWE_AUTO(TempsenseTholdReached), 1123 HWE_AUTO(MemoryErr), 1124 HWE_AUTO(PCIeBusParityErr), 1125 HWE_AUTO(PcieCplTimeout), 1126 HWE_AUTO(PciePoisonedTLP), 1127 HWE_AUTO_P(SDmaMemReadErr, 1), 1128 HWE_AUTO_P(SDmaMemReadErr, 0), 1129 HWE_AUTO_P(IBCBusFromSPCParityErr, 1), 1130 HWE_AUTO_P(IBCBusToSPCParityErr, 1), 1131 HWE_AUTO_P(IBCBusFromSPCParityErr, 0), 1132 HWE_AUTO(statusValidNoEop), 1133 HWE_AUTO(LATriggered), 1134 { .mask = 0, .sz = 0 } 1135 }; 1136 1137 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \ 1138 .msg = #fldname, .sz = sizeof(#fldname) } 1139 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \ 1140 .msg = #fldname, .sz = sizeof(#fldname) } 1141 static const struct qib_hwerror_msgs qib_7322error_msgs[] = { 1142 E_AUTO(RcvEgrFullErr), 1143 E_AUTO(RcvHdrFullErr), 1144 E_AUTO(ResetNegated), 1145 E_AUTO(HardwareErr), 1146 E_AUTO(InvalidAddrErr), 1147 E_AUTO(SDmaVL15Err), 1148 E_AUTO(SBufVL15MisUseErr), 1149 E_AUTO(InvalidEEPCmd), 1150 E_AUTO(RcvContextShareErr), 1151 E_AUTO(SendVLMismatchErr), 1152 E_AUTO(SendArmLaunchErr), 1153 E_AUTO(SendSpecialTriggerErr), 1154 E_AUTO(SDmaWrongPortErr), 1155 E_AUTO(SDmaBufMaskDuplicateErr), 1156 { .mask = 0, .sz = 0 } 1157 }; 1158 1159 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = { 1160 E_P_AUTO(IBStatusChanged), 1161 E_P_AUTO(SHeadersErr), 1162 E_P_AUTO(VL15BufMisuseErr), 1163 /* 1164 * SDmaHaltErr is not really an error, make it clearer; 1165 */ 1166 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted", 1167 .sz = 11}, 1168 E_P_AUTO(SDmaDescAddrMisalignErr), 1169 E_P_AUTO(SDmaUnexpDataErr), 1170 E_P_AUTO(SDmaMissingDwErr), 1171 E_P_AUTO(SDmaDwEnErr), 1172 E_P_AUTO(SDmaRpyTagErr), 1173 E_P_AUTO(SDma1stDescErr), 1174 E_P_AUTO(SDmaBaseErr), 1175 E_P_AUTO(SDmaTailOutOfBoundErr), 1176 E_P_AUTO(SDmaOutOfBoundErr), 1177 E_P_AUTO(SDmaGenMismatchErr), 1178 E_P_AUTO(SendBufMisuseErr), 1179 E_P_AUTO(SendUnsupportedVLErr), 1180 E_P_AUTO(SendUnexpectedPktNumErr), 1181 E_P_AUTO(SendDroppedDataPktErr), 1182 E_P_AUTO(SendDroppedSmpPktErr), 1183 E_P_AUTO(SendPktLenErr), 1184 E_P_AUTO(SendUnderRunErr), 1185 E_P_AUTO(SendMaxPktLenErr), 1186 E_P_AUTO(SendMinPktLenErr), 1187 E_P_AUTO(RcvIBLostLinkErr), 1188 E_P_AUTO(RcvHdrErr), 1189 E_P_AUTO(RcvHdrLenErr), 1190 E_P_AUTO(RcvBadTidErr), 1191 E_P_AUTO(RcvBadVersionErr), 1192 E_P_AUTO(RcvIBFlowErr), 1193 E_P_AUTO(RcvEBPErr), 1194 E_P_AUTO(RcvUnsupportedVLErr), 1195 E_P_AUTO(RcvUnexpectedCharErr), 1196 E_P_AUTO(RcvShortPktLenErr), 1197 E_P_AUTO(RcvLongPktLenErr), 1198 E_P_AUTO(RcvMaxPktLenErr), 1199 E_P_AUTO(RcvMinPktLenErr), 1200 E_P_AUTO(RcvICRCErr), 1201 E_P_AUTO(RcvVCRCErr), 1202 E_P_AUTO(RcvFormatErr), 1203 { .mask = 0, .sz = 0 } 1204 }; 1205 1206 /* 1207 * Below generates "auto-message" for interrupts not specific to any port or 1208 * context 1209 */ 1210 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \ 1211 .msg = #fldname, .sz = sizeof(#fldname) } 1212 /* Below generates "auto-message" for interrupts specific to a port */ 1213 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\ 1214 SYM_LSB(IntMask, fldname##Mask##_0), \ 1215 SYM_LSB(IntMask, fldname##Mask##_1)), \ 1216 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1217 /* For some reason, the SerDesTrimDone bits are reversed */ 1218 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\ 1219 SYM_LSB(IntMask, fldname##Mask##_1), \ 1220 SYM_LSB(IntMask, fldname##Mask##_0)), \ 1221 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1222 /* 1223 * Below generates "auto-message" for interrupts specific to a context, 1224 * with ctxt-number appended 1225 */ 1226 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\ 1227 SYM_LSB(IntMask, fldname##0IntMask), \ 1228 SYM_LSB(IntMask, fldname##17IntMask)), \ 1229 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") } 1230 1231 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = { 1232 INTR_AUTO_P(SDmaInt), 1233 INTR_AUTO_P(SDmaProgressInt), 1234 INTR_AUTO_P(SDmaIdleInt), 1235 INTR_AUTO_P(SDmaCleanupDone), 1236 INTR_AUTO_C(RcvUrg), 1237 INTR_AUTO_P(ErrInt), 1238 INTR_AUTO(ErrInt), /* non-port-specific errs */ 1239 INTR_AUTO(AssertGPIOInt), 1240 INTR_AUTO_P(SendDoneInt), 1241 INTR_AUTO(SendBufAvailInt), 1242 INTR_AUTO_C(RcvAvail), 1243 { .mask = 0, .sz = 0 } 1244 }; 1245 1246 #define TXSYMPTOM_AUTO_P(fldname) \ 1247 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \ 1248 .msg = #fldname, .sz = sizeof(#fldname) } 1249 static const struct qib_hwerror_msgs hdrchk_msgs[] = { 1250 TXSYMPTOM_AUTO_P(NonKeyPacket), 1251 TXSYMPTOM_AUTO_P(GRHFail), 1252 TXSYMPTOM_AUTO_P(PkeyFail), 1253 TXSYMPTOM_AUTO_P(QPFail), 1254 TXSYMPTOM_AUTO_P(SLIDFail), 1255 TXSYMPTOM_AUTO_P(RawIPV6), 1256 TXSYMPTOM_AUTO_P(PacketTooSmall), 1257 { .mask = 0, .sz = 0 } 1258 }; 1259 1260 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */ 1261 1262 /* 1263 * Called when we might have an error that is specific to a particular 1264 * PIO buffer, and may need to cancel that buffer, so it can be re-used, 1265 * because we don't need to force the update of pioavail 1266 */ 1267 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd) 1268 { 1269 struct qib_devdata *dd = ppd->dd; 1270 u32 i; 1271 int any; 1272 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 1273 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG; 1274 unsigned long sbuf[4]; 1275 1276 /* 1277 * It's possible that sendbuffererror could have bits set; might 1278 * have already done this as a result of hardware error handling. 1279 */ 1280 any = 0; 1281 for (i = 0; i < regcnt; ++i) { 1282 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); 1283 if (sbuf[i]) { 1284 any = 1; 1285 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); 1286 } 1287 } 1288 1289 if (any) 1290 qib_disarm_piobufs_set(dd, sbuf, piobcnt); 1291 } 1292 1293 /* No txe_recover yet, if ever */ 1294 1295 /* No decode__errors yet */ 1296 static void err_decode(char *msg, size_t len, u64 errs, 1297 const struct qib_hwerror_msgs *msp) 1298 { 1299 u64 these, lmask; 1300 int took, multi, n = 0; 1301 1302 while (errs && msp && msp->mask) { 1303 multi = (msp->mask & (msp->mask - 1)); 1304 while (errs & msp->mask) { 1305 these = (errs & msp->mask); 1306 lmask = (these & (these - 1)) ^ these; 1307 if (len) { 1308 if (n++) { 1309 /* separate the strings */ 1310 *msg++ = ','; 1311 len--; 1312 } 1313 BUG_ON(!msp->sz); 1314 /* msp->sz counts the nul */ 1315 took = min_t(size_t, msp->sz - (size_t)1, len); 1316 memcpy(msg, msp->msg, took); 1317 len -= took; 1318 msg += took; 1319 if (len) 1320 *msg = '\0'; 1321 } 1322 errs &= ~lmask; 1323 if (len && multi) { 1324 /* More than one bit this mask */ 1325 int idx = -1; 1326 1327 while (lmask & msp->mask) { 1328 ++idx; 1329 lmask >>= 1; 1330 } 1331 took = scnprintf(msg, len, "_%d", idx); 1332 len -= took; 1333 msg += took; 1334 } 1335 } 1336 ++msp; 1337 } 1338 /* If some bits are left, show in hex. */ 1339 if (len && errs) 1340 snprintf(msg, len, "%sMORE:%llX", n ? "," : "", 1341 (unsigned long long) errs); 1342 } 1343 1344 /* only called if r1 set */ 1345 static void flush_fifo(struct qib_pportdata *ppd) 1346 { 1347 struct qib_devdata *dd = ppd->dd; 1348 u32 __iomem *piobuf; 1349 u32 bufn; 1350 u32 *hdr; 1351 u64 pbc; 1352 const unsigned hdrwords = 7; 1353 static struct qib_ib_header ibhdr = { 1354 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH), 1355 .lrh[1] = IB_LID_PERMISSIVE, 1356 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC), 1357 .lrh[3] = IB_LID_PERMISSIVE, 1358 .u.oth.bth[0] = cpu_to_be32( 1359 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY), 1360 .u.oth.bth[1] = cpu_to_be32(0), 1361 .u.oth.bth[2] = cpu_to_be32(0), 1362 .u.oth.u.ud.deth[0] = cpu_to_be32(0), 1363 .u.oth.u.ud.deth[1] = cpu_to_be32(0), 1364 }; 1365 1366 /* 1367 * Send a dummy VL15 packet to flush the launch FIFO. 1368 * This will not actually be sent since the TxeBypassIbc bit is set. 1369 */ 1370 pbc = PBC_7322_VL15_SEND | 1371 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) | 1372 (hdrwords + SIZE_OF_CRC); 1373 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn); 1374 if (!piobuf) 1375 return; 1376 writeq(pbc, piobuf); 1377 hdr = (u32 *) &ibhdr; 1378 if (dd->flags & QIB_PIO_FLUSH_WC) { 1379 qib_flush_wc(); 1380 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1); 1381 qib_flush_wc(); 1382 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1); 1383 qib_flush_wc(); 1384 } else 1385 qib_pio_copy(piobuf + 2, hdr, hdrwords); 1386 qib_sendbuf_done(dd, bufn); 1387 } 1388 1389 /* 1390 * This is called with interrupts disabled and sdma_lock held. 1391 */ 1392 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) 1393 { 1394 struct qib_devdata *dd = ppd->dd; 1395 u64 set_sendctrl = 0; 1396 u64 clr_sendctrl = 0; 1397 1398 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE) 1399 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1400 else 1401 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1402 1403 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE) 1404 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1405 else 1406 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1407 1408 if (op & QIB_SDMA_SENDCTRL_OP_HALT) 1409 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1410 else 1411 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1412 1413 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) 1414 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1415 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1416 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1417 else 1418 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1419 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1420 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1421 1422 spin_lock(&dd->sendctrl_lock); 1423 1424 /* If we are draining everything, block sends first */ 1425 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1426 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 1427 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1428 qib_write_kreg(dd, kr_scratch, 0); 1429 } 1430 1431 ppd->p_sendctrl |= set_sendctrl; 1432 ppd->p_sendctrl &= ~clr_sendctrl; 1433 1434 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP) 1435 qib_write_kreg_port(ppd, krp_sendctrl, 1436 ppd->p_sendctrl | 1437 SYM_MASK(SendCtrl_0, SDmaCleanup)); 1438 else 1439 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1440 qib_write_kreg(dd, kr_scratch, 0); 1441 1442 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1443 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 1444 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1445 qib_write_kreg(dd, kr_scratch, 0); 1446 } 1447 1448 spin_unlock(&dd->sendctrl_lock); 1449 1450 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) 1451 flush_fifo(ppd); 1452 } 1453 1454 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd) 1455 { 1456 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned); 1457 } 1458 1459 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd) 1460 { 1461 /* 1462 * Set SendDmaLenGen and clear and set 1463 * the MSB of the generation count to enable generation checking 1464 * and load the internal generation counter. 1465 */ 1466 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt); 1467 qib_write_kreg_port(ppd, krp_senddmalengen, 1468 ppd->sdma_descq_cnt | 1469 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB)); 1470 } 1471 1472 /* 1473 * Must be called with sdma_lock held, or before init finished. 1474 */ 1475 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail) 1476 { 1477 /* Commit writes to memory and advance the tail on the chip */ 1478 wmb(); 1479 ppd->sdma_descq_tail = tail; 1480 qib_write_kreg_port(ppd, krp_senddmatail, tail); 1481 } 1482 1483 /* 1484 * This is called with interrupts disabled and sdma_lock held. 1485 */ 1486 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd) 1487 { 1488 /* 1489 * Drain all FIFOs. 1490 * The hardware doesn't require this but we do it so that verbs 1491 * and user applications don't wait for link active to send stale 1492 * data. 1493 */ 1494 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH); 1495 1496 qib_sdma_7322_setlengen(ppd); 1497 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 1498 ppd->sdma_head_dma[0] = 0; 1499 qib_7322_sdma_sendctrl(ppd, 1500 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP); 1501 } 1502 1503 #define DISABLES_SDMA ( \ 1504 QIB_E_P_SDMAHALT | \ 1505 QIB_E_P_SDMADESCADDRMISALIGN | \ 1506 QIB_E_P_SDMAMISSINGDW | \ 1507 QIB_E_P_SDMADWEN | \ 1508 QIB_E_P_SDMARPYTAG | \ 1509 QIB_E_P_SDMA1STDESC | \ 1510 QIB_E_P_SDMABASE | \ 1511 QIB_E_P_SDMATAILOUTOFBOUND | \ 1512 QIB_E_P_SDMAOUTOFBOUND | \ 1513 QIB_E_P_SDMAGENMISMATCH) 1514 1515 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs) 1516 { 1517 unsigned long flags; 1518 struct qib_devdata *dd = ppd->dd; 1519 1520 errs &= QIB_E_P_SDMAERRS; 1521 1522 if (errs & QIB_E_P_SDMAUNEXPDATA) 1523 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, 1524 ppd->port); 1525 1526 spin_lock_irqsave(&ppd->sdma_lock, flags); 1527 1528 switch (ppd->sdma_state.current_state) { 1529 case qib_sdma_state_s00_hw_down: 1530 break; 1531 1532 case qib_sdma_state_s10_hw_start_up_wait: 1533 if (errs & QIB_E_P_SDMAHALT) 1534 __qib_sdma_process_event(ppd, 1535 qib_sdma_event_e20_hw_started); 1536 break; 1537 1538 case qib_sdma_state_s20_idle: 1539 break; 1540 1541 case qib_sdma_state_s30_sw_clean_up_wait: 1542 break; 1543 1544 case qib_sdma_state_s40_hw_clean_up_wait: 1545 if (errs & QIB_E_P_SDMAHALT) 1546 __qib_sdma_process_event(ppd, 1547 qib_sdma_event_e50_hw_cleaned); 1548 break; 1549 1550 case qib_sdma_state_s50_hw_halt_wait: 1551 if (errs & QIB_E_P_SDMAHALT) 1552 __qib_sdma_process_event(ppd, 1553 qib_sdma_event_e60_hw_halted); 1554 break; 1555 1556 case qib_sdma_state_s99_running: 1557 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted); 1558 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted); 1559 break; 1560 } 1561 1562 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 1563 } 1564 1565 /* 1566 * handle per-device errors (not per-port errors) 1567 */ 1568 static noinline void handle_7322_errors(struct qib_devdata *dd) 1569 { 1570 char *msg; 1571 u64 iserr = 0; 1572 u64 errs; 1573 u64 mask; 1574 int log_idx; 1575 1576 qib_stats.sps_errints++; 1577 errs = qib_read_kreg64(dd, kr_errstatus); 1578 if (!errs) { 1579 qib_devinfo(dd->pcidev, "device error interrupt, " 1580 "but no error bits set!\n"); 1581 goto done; 1582 } 1583 1584 /* don't report errors that are masked */ 1585 errs &= dd->cspec->errormask; 1586 msg = dd->cspec->emsgbuf; 1587 1588 /* do these first, they are most important */ 1589 if (errs & QIB_E_HARDWARE) { 1590 *msg = '\0'; 1591 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf); 1592 } else 1593 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx) 1594 if (errs & dd->eep_st_masks[log_idx].errs_to_log) 1595 qib_inc_eeprom_err(dd, log_idx, 1); 1596 1597 if (errs & QIB_E_SPKTERRS) { 1598 qib_disarm_7322_senderrbufs(dd->pport); 1599 qib_stats.sps_txerrs++; 1600 } else if (errs & QIB_E_INVALIDADDR) 1601 qib_stats.sps_txerrs++; 1602 else if (errs & QIB_E_ARMLAUNCH) { 1603 qib_stats.sps_txerrs++; 1604 qib_disarm_7322_senderrbufs(dd->pport); 1605 } 1606 qib_write_kreg(dd, kr_errclear, errs); 1607 1608 /* 1609 * The ones we mask off are handled specially below 1610 * or above. Also mask SDMADISABLED by default as it 1611 * is too chatty. 1612 */ 1613 mask = QIB_E_HARDWARE; 1614 *msg = '\0'; 1615 1616 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask, 1617 qib_7322error_msgs); 1618 1619 /* 1620 * Getting reset is a tragedy for all ports. Mark the device 1621 * _and_ the ports as "offline" in way meaningful to each. 1622 */ 1623 if (errs & QIB_E_RESET) { 1624 int pidx; 1625 1626 qib_dev_err(dd, "Got reset, requires re-init " 1627 "(unload and reload driver)\n"); 1628 dd->flags &= ~QIB_INITTED; /* needs re-init */ 1629 /* mark as having had error */ 1630 *dd->devstatusp |= QIB_STATUS_HWERROR; 1631 for (pidx = 0; pidx < dd->num_pports; ++pidx) 1632 if (dd->pport[pidx].link_speed_supported) 1633 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; 1634 } 1635 1636 if (*msg && iserr) 1637 qib_dev_err(dd, "%s error\n", msg); 1638 1639 /* 1640 * If there were hdrq or egrfull errors, wake up any processes 1641 * waiting in poll. We used to try to check which contexts had 1642 * the overflow, but given the cost of that and the chip reads 1643 * to support it, it's better to just wake everybody up if we 1644 * get an overflow; waiters can poll again if it's not them. 1645 */ 1646 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) { 1647 qib_handle_urcv(dd, ~0U); 1648 if (errs & ERR_MASK(RcvEgrFullErr)) 1649 qib_stats.sps_buffull++; 1650 else 1651 qib_stats.sps_hdrfull++; 1652 } 1653 1654 done: 1655 return; 1656 } 1657 1658 static void qib_error_tasklet(unsigned long data) 1659 { 1660 struct qib_devdata *dd = (struct qib_devdata *)data; 1661 1662 handle_7322_errors(dd); 1663 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1664 } 1665 1666 static void reenable_chase(unsigned long opaque) 1667 { 1668 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 1669 1670 ppd->cpspec->chase_timer.expires = 0; 1671 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1672 QLOGIC_IB_IBCC_LINKINITCMD_POLL); 1673 } 1674 1675 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow, 1676 u8 ibclt) 1677 { 1678 ppd->cpspec->chase_end = 0; 1679 1680 if (!qib_chase) 1681 return; 1682 1683 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1684 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1685 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME; 1686 add_timer(&ppd->cpspec->chase_timer); 1687 } 1688 1689 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst) 1690 { 1691 u8 ibclt; 1692 unsigned long tnow; 1693 1694 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState); 1695 1696 /* 1697 * Detect and handle the state chase issue, where we can 1698 * get stuck if we are unlucky on timing on both sides of 1699 * the link. If we are, we disable, set a timer, and 1700 * then re-enable. 1701 */ 1702 switch (ibclt) { 1703 case IB_7322_LT_STATE_CFGRCVFCFG: 1704 case IB_7322_LT_STATE_CFGWAITRMT: 1705 case IB_7322_LT_STATE_TXREVLANES: 1706 case IB_7322_LT_STATE_CFGENH: 1707 tnow = jiffies; 1708 if (ppd->cpspec->chase_end && 1709 time_after(tnow, ppd->cpspec->chase_end)) 1710 disable_chase(ppd, tnow, ibclt); 1711 else if (!ppd->cpspec->chase_end) 1712 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME; 1713 break; 1714 default: 1715 ppd->cpspec->chase_end = 0; 1716 break; 1717 } 1718 1719 if (((ibclt >= IB_7322_LT_STATE_CFGTEST && 1720 ibclt <= IB_7322_LT_STATE_CFGWAITENH) || 1721 ibclt == IB_7322_LT_STATE_LINKUP) && 1722 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { 1723 force_h1(ppd); 1724 ppd->cpspec->qdr_reforce = 1; 1725 if (!ppd->dd->cspec->r1) 1726 serdes_7322_los_enable(ppd, 0); 1727 } else if (ppd->cpspec->qdr_reforce && 1728 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && 1729 (ibclt == IB_7322_LT_STATE_CFGENH || 1730 ibclt == IB_7322_LT_STATE_CFGIDLE || 1731 ibclt == IB_7322_LT_STATE_LINKUP)) 1732 force_h1(ppd); 1733 1734 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && 1735 ppd->link_speed_enabled == QIB_IB_QDR && 1736 (ibclt == IB_7322_LT_STATE_CFGTEST || 1737 ibclt == IB_7322_LT_STATE_CFGENH || 1738 (ibclt >= IB_7322_LT_STATE_POLLACTIVE && 1739 ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) 1740 adj_tx_serdes(ppd); 1741 1742 if (ibclt != IB_7322_LT_STATE_LINKUP) { 1743 u8 ltstate = qib_7322_phys_portstate(ibcst); 1744 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, 1745 LinkTrainingState); 1746 if (!ppd->dd->cspec->r1 && 1747 pibclt == IB_7322_LT_STATE_LINKUP && 1748 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1749 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1750 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1751 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1752 /* If the link went down (but no into recovery, 1753 * turn LOS back on */ 1754 serdes_7322_los_enable(ppd, 1); 1755 if (!ppd->cpspec->qdr_dfe_on && 1756 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { 1757 ppd->cpspec->qdr_dfe_on = 1; 1758 ppd->cpspec->qdr_dfe_time = 0; 1759 /* On link down, reenable QDR adaptation */ 1760 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 1761 ppd->dd->cspec->r1 ? 1762 QDR_STATIC_ADAPT_DOWN_R1 : 1763 QDR_STATIC_ADAPT_DOWN); 1764 printk(KERN_INFO QIB_DRV_NAME 1765 " IB%u:%u re-enabled QDR adaptation " 1766 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt); 1767 } 1768 } 1769 } 1770 1771 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); 1772 1773 /* 1774 * This is per-pport error handling. 1775 * will likely get it's own MSIx interrupt (one for each port, 1776 * although just a single handler). 1777 */ 1778 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd) 1779 { 1780 char *msg; 1781 u64 ignore_this_time = 0, iserr = 0, errs, fmask; 1782 struct qib_devdata *dd = ppd->dd; 1783 1784 /* do this as soon as possible */ 1785 fmask = qib_read_kreg64(dd, kr_act_fmask); 1786 if (!fmask) 1787 check_7322_rxe_status(ppd); 1788 1789 errs = qib_read_kreg_port(ppd, krp_errstatus); 1790 if (!errs) 1791 qib_devinfo(dd->pcidev, 1792 "Port%d error interrupt, but no error bits set!\n", 1793 ppd->port); 1794 if (!fmask) 1795 errs &= ~QIB_E_P_IBSTATUSCHANGED; 1796 if (!errs) 1797 goto done; 1798 1799 msg = ppd->cpspec->epmsgbuf; 1800 *msg = '\0'; 1801 1802 if (errs & ~QIB_E_P_BITSEXTANT) { 1803 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, 1804 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs); 1805 if (!*msg) 1806 snprintf(msg, sizeof ppd->cpspec->epmsgbuf, 1807 "no others"); 1808 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown" 1809 " errors 0x%016Lx set (and %s)\n", 1810 (errs & ~QIB_E_P_BITSEXTANT), msg); 1811 *msg = '\0'; 1812 } 1813 1814 if (errs & QIB_E_P_SHDR) { 1815 u64 symptom; 1816 1817 /* determine cause, then write to clear */ 1818 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom); 1819 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0); 1820 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom, 1821 hdrchk_msgs); 1822 *msg = '\0'; 1823 /* senderrbuf cleared in SPKTERRS below */ 1824 } 1825 1826 if (errs & QIB_E_P_SPKTERRS) { 1827 if ((errs & QIB_E_P_LINK_PKTERRS) && 1828 !(ppd->lflags & QIBL_LINKACTIVE)) { 1829 /* 1830 * This can happen when trying to bring the link 1831 * up, but the IB link changes state at the "wrong" 1832 * time. The IB logic then complains that the packet 1833 * isn't valid. We don't want to confuse people, so 1834 * we just don't print them, except at debug 1835 */ 1836 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, 1837 (errs & QIB_E_P_LINK_PKTERRS), 1838 qib_7322p_error_msgs); 1839 *msg = '\0'; 1840 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1841 } 1842 qib_disarm_7322_senderrbufs(ppd); 1843 } else if ((errs & QIB_E_P_LINK_PKTERRS) && 1844 !(ppd->lflags & QIBL_LINKACTIVE)) { 1845 /* 1846 * This can happen when SMA is trying to bring the link 1847 * up, but the IB link changes state at the "wrong" time. 1848 * The IB logic then complains that the packet isn't 1849 * valid. We don't want to confuse people, so we just 1850 * don't print them, except at debug 1851 */ 1852 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs, 1853 qib_7322p_error_msgs); 1854 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1855 *msg = '\0'; 1856 } 1857 1858 qib_write_kreg_port(ppd, krp_errclear, errs); 1859 1860 errs &= ~ignore_this_time; 1861 if (!errs) 1862 goto done; 1863 1864 if (errs & QIB_E_P_RPKTERRS) 1865 qib_stats.sps_rcverrs++; 1866 if (errs & QIB_E_P_SPKTERRS) 1867 qib_stats.sps_txerrs++; 1868 1869 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS); 1870 1871 if (errs & QIB_E_P_SDMAERRS) 1872 sdma_7322_p_errors(ppd, errs); 1873 1874 if (errs & QIB_E_P_IBSTATUSCHANGED) { 1875 u64 ibcs; 1876 u8 ltstate; 1877 1878 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a); 1879 ltstate = qib_7322_phys_portstate(ibcs); 1880 1881 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 1882 handle_serdes_issues(ppd, ibcs); 1883 if (!(ppd->cpspec->ibcctrl_a & 1884 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { 1885 /* 1886 * We got our interrupt, so init code should be 1887 * happy and not try alternatives. Now squelch 1888 * other "chatter" from link-negotiation (pre Init) 1889 */ 1890 ppd->cpspec->ibcctrl_a |= 1891 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 1892 qib_write_kreg_port(ppd, krp_ibcctrl_a, 1893 ppd->cpspec->ibcctrl_a); 1894 } 1895 1896 /* Update our picture of width and speed from chip */ 1897 ppd->link_width_active = 1898 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? 1899 IB_WIDTH_4X : IB_WIDTH_1X; 1900 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, 1901 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs & 1902 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? 1903 QIB_IB_DDR : QIB_IB_SDR; 1904 1905 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate != 1906 IB_PHYSPORTSTATE_DISABLED) 1907 qib_set_ib_7322_lstate(ppd, 0, 1908 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1909 else 1910 /* 1911 * Since going into a recovery state causes the link 1912 * state to go down and since recovery is transitory, 1913 * it is better if we "miss" ever seeing the link 1914 * training state go into recovery (i.e., ignore this 1915 * transition for link state special handling purposes) 1916 * without updating lastibcstat. 1917 */ 1918 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1919 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1920 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1921 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1922 qib_handle_e_ibstatuschanged(ppd, ibcs); 1923 } 1924 if (*msg && iserr) 1925 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); 1926 1927 if (ppd->state_wanted & ppd->lflags) 1928 wake_up_interruptible(&ppd->state_wait); 1929 done: 1930 return; 1931 } 1932 1933 /* enable/disable chip from delivering interrupts */ 1934 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) 1935 { 1936 if (enable) { 1937 if (dd->flags & QIB_BADINTR) 1938 return; 1939 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); 1940 /* cause any pending enabled interrupts to be re-delivered */ 1941 qib_write_kreg(dd, kr_intclear, 0ULL); 1942 if (dd->cspec->num_msix_entries) { 1943 /* and same for MSIx */ 1944 u64 val = qib_read_kreg64(dd, kr_intgranted); 1945 if (val) 1946 qib_write_kreg(dd, kr_intgranted, val); 1947 } 1948 } else 1949 qib_write_kreg(dd, kr_intmask, 0ULL); 1950 } 1951 1952 /* 1953 * Try to cleanup as much as possible for anything that might have gone 1954 * wrong while in freeze mode, such as pio buffers being written by user 1955 * processes (causing armlaunch), send errors due to going into freeze mode, 1956 * etc., and try to avoid causing extra interrupts while doing so. 1957 * Forcibly update the in-memory pioavail register copies after cleanup 1958 * because the chip won't do it while in freeze mode (the register values 1959 * themselves are kept correct). 1960 * Make sure that we don't lose any important interrupts by using the chip 1961 * feature that says that writing 0 to a bit in *clear that is set in 1962 * *status will cause an interrupt to be generated again (if allowed by 1963 * the *mask value). 1964 * This is in chip-specific code because of all of the register accesses, 1965 * even though the details are similar on most chips. 1966 */ 1967 static void qib_7322_clear_freeze(struct qib_devdata *dd) 1968 { 1969 int pidx; 1970 1971 /* disable error interrupts, to avoid confusion */ 1972 qib_write_kreg(dd, kr_errmask, 0ULL); 1973 1974 for (pidx = 0; pidx < dd->num_pports; ++pidx) 1975 if (dd->pport[pidx].link_speed_supported) 1976 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 1977 0ULL); 1978 1979 /* also disable interrupts; errormask is sometimes overwriten */ 1980 qib_7322_set_intr_state(dd, 0); 1981 1982 /* clear the freeze, and be sure chip saw it */ 1983 qib_write_kreg(dd, kr_control, dd->control); 1984 qib_read_kreg32(dd, kr_scratch); 1985 1986 /* 1987 * Force new interrupt if any hwerr, error or interrupt bits are 1988 * still set, and clear "safe" send packet errors related to freeze 1989 * and cancelling sends. Re-enable error interrupts before possible 1990 * force of re-interrupt on pending interrupts. 1991 */ 1992 qib_write_kreg(dd, kr_hwerrclear, 0ULL); 1993 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); 1994 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1995 /* We need to purge per-port errs and reset mask, too */ 1996 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1997 if (!dd->pport[pidx].link_speed_supported) 1998 continue; 1999 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); 2000 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); 2001 } 2002 qib_7322_set_intr_state(dd, 1); 2003 } 2004 2005 /* no error handling to speak of */ 2006 /** 2007 * qib_7322_handle_hwerrors - display hardware errors. 2008 * @dd: the qlogic_ib device 2009 * @msg: the output buffer 2010 * @msgl: the size of the output buffer 2011 * 2012 * Use same msg buffer as regular errors to avoid excessive stack 2013 * use. Most hardware errors are catastrophic, but for right now, 2014 * we'll print them and continue. We reuse the same message buffer as 2015 * qib_handle_errors() to avoid excessive stack usage. 2016 */ 2017 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, 2018 size_t msgl) 2019 { 2020 u64 hwerrs; 2021 u32 ctrl; 2022 int isfatal = 0; 2023 2024 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 2025 if (!hwerrs) 2026 goto bail; 2027 if (hwerrs == ~0ULL) { 2028 qib_dev_err(dd, "Read of hardware error status failed " 2029 "(all bits set); ignoring\n"); 2030 goto bail; 2031 } 2032 qib_stats.sps_hwerrs++; 2033 2034 /* Always clear the error status register, except BIST fail */ 2035 qib_write_kreg(dd, kr_hwerrclear, hwerrs & 2036 ~HWE_MASK(PowerOnBISTFailed)); 2037 2038 hwerrs &= dd->cspec->hwerrmask; 2039 2040 /* no EEPROM logging, yet */ 2041 2042 if (hwerrs) 2043 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx " 2044 "(cleared)\n", (unsigned long long) hwerrs); 2045 2046 ctrl = qib_read_kreg32(dd, kr_control); 2047 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { 2048 /* 2049 * No recovery yet... 2050 */ 2051 if ((hwerrs & ~HWE_MASK(LATriggered)) || 2052 dd->cspec->stay_in_freeze) { 2053 /* 2054 * If any set that we aren't ignoring only make the 2055 * complaint once, in case it's stuck or recurring, 2056 * and we get here multiple times 2057 * Force link down, so switch knows, and 2058 * LEDs are turned off. 2059 */ 2060 if (dd->flags & QIB_INITTED) 2061 isfatal = 1; 2062 } else 2063 qib_7322_clear_freeze(dd); 2064 } 2065 2066 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) { 2067 isfatal = 1; 2068 strlcpy(msg, "[Memory BIST test failed, " 2069 "InfiniPath hardware unusable]", msgl); 2070 /* ignore from now on, so disable until driver reloaded */ 2071 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); 2072 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2073 } 2074 2075 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs); 2076 2077 /* Ignore esoteric PLL failures et al. */ 2078 2079 qib_dev_err(dd, "%s hardware error\n", msg); 2080 2081 if (isfatal && !dd->diag_client) { 2082 qib_dev_err(dd, "Fatal Hardware Error, no longer" 2083 " usable, SN %.16s\n", dd->serial); 2084 /* 2085 * for /sys status file and user programs to print; if no 2086 * trailing brace is copied, we'll know it was truncated. 2087 */ 2088 if (dd->freezemsg) 2089 snprintf(dd->freezemsg, dd->freezelen, 2090 "{%s}", msg); 2091 qib_disable_after_error(dd); 2092 } 2093 bail:; 2094 } 2095 2096 /** 2097 * qib_7322_init_hwerrors - enable hardware errors 2098 * @dd: the qlogic_ib device 2099 * 2100 * now that we have finished initializing everything that might reasonably 2101 * cause a hardware error, and cleared those errors bits as they occur, 2102 * we can enable hardware errors in the mask (potentially enabling 2103 * freeze mode), and enable hardware errors as errors (along with 2104 * everything else) in errormask 2105 */ 2106 static void qib_7322_init_hwerrors(struct qib_devdata *dd) 2107 { 2108 int pidx; 2109 u64 extsval; 2110 2111 extsval = qib_read_kreg64(dd, kr_extstatus); 2112 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED | 2113 QIB_EXTS_MEMBIST_ENDTEST))) 2114 qib_dev_err(dd, "MemBIST did not complete!\n"); 2115 2116 /* never clear BIST failure, so reported on each driver load */ 2117 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); 2118 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2119 2120 /* clear all */ 2121 qib_write_kreg(dd, kr_errclear, ~0ULL); 2122 /* enable errors that are masked, at least this first time. */ 2123 qib_write_kreg(dd, kr_errmask, ~0ULL); 2124 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); 2125 for (pidx = 0; pidx < dd->num_pports; ++pidx) 2126 if (dd->pport[pidx].link_speed_supported) 2127 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 2128 ~0ULL); 2129 } 2130 2131 /* 2132 * Disable and enable the armlaunch error. Used for PIO bandwidth testing 2133 * on chips that are count-based, rather than trigger-based. There is no 2134 * reference counting, but that's also fine, given the intended use. 2135 * Only chip-specific because it's all register accesses 2136 */ 2137 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) 2138 { 2139 if (enable) { 2140 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); 2141 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; 2142 } else 2143 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; 2144 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 2145 } 2146 2147 /* 2148 * Formerly took parameter <which> in pre-shifted, 2149 * pre-merged form with LinkCmd and LinkInitCmd 2150 * together, and assuming the zero was NOP. 2151 */ 2152 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 2153 u16 linitcmd) 2154 { 2155 u64 mod_wd; 2156 struct qib_devdata *dd = ppd->dd; 2157 unsigned long flags; 2158 2159 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) { 2160 /* 2161 * If we are told to disable, note that so link-recovery 2162 * code does not attempt to bring us back up. 2163 * Also reset everything that we can, so we start 2164 * completely clean when re-enabled (before we 2165 * actually issue the disable to the IBC) 2166 */ 2167 qib_7322_mini_pcs_reset(ppd); 2168 spin_lock_irqsave(&ppd->lflags_lock, flags); 2169 ppd->lflags |= QIBL_IB_LINK_DISABLED; 2170 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2171 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) { 2172 /* 2173 * Any other linkinitcmd will lead to LINKDOWN and then 2174 * to INIT (if all is well), so clear flag to let 2175 * link-recovery code attempt to bring us back up. 2176 */ 2177 spin_lock_irqsave(&ppd->lflags_lock, flags); 2178 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; 2179 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2180 /* 2181 * Clear status change interrupt reduction so the 2182 * new state is seen. 2183 */ 2184 ppd->cpspec->ibcctrl_a &= 2185 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 2186 } 2187 2188 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) | 2189 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2190 2191 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a | 2192 mod_wd); 2193 /* write to chip to prevent back-to-back writes of ibc reg */ 2194 qib_write_kreg(dd, kr_scratch, 0); 2195 2196 } 2197 2198 /* 2199 * The total RCV buffer memory is 64KB, used for both ports, and is 2200 * in units of 64 bytes (same as IB flow control credit unit). 2201 * The consumedVL unit in the same registers are in 32 byte units! 2202 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks, 2203 * and we can therefore allocate just 9 IB credits for 2 VL15 packets 2204 * in krp_rxcreditvl15, rather than 10. 2205 */ 2206 #define RCV_BUF_UNITSZ 64 2207 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) 2208 2209 static void set_vls(struct qib_pportdata *ppd) 2210 { 2211 int i, numvls, totcred, cred_vl, vl0extra; 2212 struct qib_devdata *dd = ppd->dd; 2213 u64 val; 2214 2215 numvls = qib_num_vls(ppd->vls_operational); 2216 2217 /* 2218 * Set up per-VL credits. Below is kluge based on these assumptions: 2219 * 1) port is disabled at the time early_init is called. 2220 * 2) give VL15 17 credits, for two max-plausible packets. 2221 * 3) Give VL0-N the rest, with any rounding excess used for VL0 2222 */ 2223 /* 2 VL15 packets @ 288 bytes each (including IB headers) */ 2224 totcred = NUM_RCV_BUF_UNITS(dd); 2225 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ; 2226 totcred -= cred_vl; 2227 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl); 2228 cred_vl = totcred / numvls; 2229 vl0extra = totcred - cred_vl * numvls; 2230 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra); 2231 for (i = 1; i < numvls; i++) 2232 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl); 2233 for (; i < 8; i++) /* no buffer space for other VLs */ 2234 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 2235 2236 /* Notify IBC that credits need to be recalculated */ 2237 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 2238 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2239 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2240 qib_write_kreg(dd, kr_scratch, 0ULL); 2241 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2242 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2243 2244 for (i = 0; i < numvls; i++) 2245 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i); 2246 val = qib_read_kreg_port(ppd, krp_rxcreditvl15); 2247 2248 /* Change the number of operational VLs */ 2249 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a & 2250 ~SYM_MASK(IBCCtrlA_0, NumVLane)) | 2251 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); 2252 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2253 qib_write_kreg(dd, kr_scratch, 0ULL); 2254 } 2255 2256 /* 2257 * The code that deals with actual SerDes is in serdes_7322_init(). 2258 * Compared to the code for iba7220, it is minimal. 2259 */ 2260 static int serdes_7322_init(struct qib_pportdata *ppd); 2261 2262 /** 2263 * qib_7322_bringup_serdes - bring up the serdes 2264 * @ppd: physical port on the qlogic_ib device 2265 */ 2266 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd) 2267 { 2268 struct qib_devdata *dd = ppd->dd; 2269 u64 val, guid, ibc; 2270 unsigned long flags; 2271 int ret = 0; 2272 2273 /* 2274 * SerDes model not in Pd, but still need to 2275 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere 2276 * eventually. 2277 */ 2278 /* Put IBC in reset, sends disabled (should be in reset already) */ 2279 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2280 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2281 qib_write_kreg(dd, kr_scratch, 0ULL); 2282 2283 if (qib_compat_ddr_negotiate) { 2284 ppd->cpspec->ibdeltainprog = 1; 2285 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 2286 crp_ibsymbolerr); 2287 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 2288 crp_iblinkerrrecov); 2289 } 2290 2291 /* flowcontrolwatermark is in units of KBytes */ 2292 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); 2293 /* 2294 * Flow control is sent this often, even if no changes in 2295 * buffer space occur. Units are 128ns for this chip. 2296 * Set to 3usec. 2297 */ 2298 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); 2299 /* max error tolerance */ 2300 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 2301 /* IB credit flow control. */ 2302 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); 2303 /* 2304 * set initial max size pkt IBC will send, including ICRC; it's the 2305 * PIO buffer size in dwords, less 1; also see qib_set_mtu() 2306 */ 2307 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << 2308 SYM_LSB(IBCCtrlA_0, MaxPktLen); 2309 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */ 2310 2311 /* 2312 * Reset the PCS interface to the serdes (and also ibc, which is still 2313 * in reset from above). Writes new value of ibcctrl_a as last step. 2314 */ 2315 qib_7322_mini_pcs_reset(ppd); 2316 2317 if (!ppd->cpspec->ibcctrl_b) { 2318 unsigned lse = ppd->link_speed_enabled; 2319 2320 /* 2321 * Not on re-init after reset, establish shadow 2322 * and force initial config. 2323 */ 2324 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd, 2325 krp_ibcctrl_b); 2326 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR | 2327 IBA7322_IBC_SPEED_DDR | 2328 IBA7322_IBC_SPEED_SDR | 2329 IBA7322_IBC_WIDTH_AUTONEG | 2330 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); 2331 if (lse & (lse - 1)) /* Muliple speeds enabled */ 2332 ppd->cpspec->ibcctrl_b |= 2333 (lse << IBA7322_IBC_SPEED_LSB) | 2334 IBA7322_IBC_IBTA_1_2_MASK | 2335 IBA7322_IBC_MAX_SPEED_MASK; 2336 else 2337 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ? 2338 IBA7322_IBC_SPEED_QDR | 2339 IBA7322_IBC_IBTA_1_2_MASK : 2340 (lse == QIB_IB_DDR) ? 2341 IBA7322_IBC_SPEED_DDR : 2342 IBA7322_IBC_SPEED_SDR; 2343 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) == 2344 (IB_WIDTH_1X | IB_WIDTH_4X)) 2345 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG; 2346 else 2347 ppd->cpspec->ibcctrl_b |= 2348 ppd->link_width_enabled == IB_WIDTH_4X ? 2349 IBA7322_IBC_WIDTH_4X_ONLY : 2350 IBA7322_IBC_WIDTH_1X_ONLY; 2351 2352 /* always enable these on driver reload, not sticky */ 2353 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK | 2354 IBA7322_IBC_HRTBT_MASK); 2355 } 2356 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 2357 2358 /* setup so we have more time at CFGTEST to change H1 */ 2359 val = qib_read_kreg_port(ppd, krp_ibcctrl_c); 2360 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); 2361 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); 2362 qib_write_kreg_port(ppd, krp_ibcctrl_c, val); 2363 2364 serdes_7322_init(ppd); 2365 2366 guid = be64_to_cpu(ppd->guid); 2367 if (!guid) { 2368 if (dd->base_guid) 2369 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; 2370 ppd->guid = cpu_to_be64(guid); 2371 } 2372 2373 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid); 2374 /* write to chip to prevent back-to-back writes of ibc reg */ 2375 qib_write_kreg(dd, kr_scratch, 0); 2376 2377 /* Enable port */ 2378 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); 2379 set_vls(ppd); 2380 2381 /* initially come up DISABLED, without sending anything. */ 2382 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << 2383 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2384 qib_write_kreg_port(ppd, krp_ibcctrl_a, val); 2385 qib_write_kreg(dd, kr_scratch, 0ULL); 2386 /* clear the linkinit cmds */ 2387 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); 2388 2389 /* be paranoid against later code motion, etc. */ 2390 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 2391 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); 2392 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 2393 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 2394 2395 /* Also enable IBSTATUSCHG interrupt. */ 2396 val = qib_read_kreg_port(ppd, krp_errmask); 2397 qib_write_kreg_port(ppd, krp_errmask, 2398 val | ERR_MASK_N(IBStatusChanged)); 2399 2400 /* Always zero until we start messing with SerDes for real */ 2401 return ret; 2402 } 2403 2404 /** 2405 * qib_7322_quiet_serdes - set serdes to txidle 2406 * @dd: the qlogic_ib device 2407 * Called when driver is being unloaded 2408 */ 2409 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd) 2410 { 2411 u64 val; 2412 unsigned long flags; 2413 2414 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 2415 2416 spin_lock_irqsave(&ppd->lflags_lock, flags); 2417 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 2418 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2419 wake_up(&ppd->cpspec->autoneg_wait); 2420 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work); 2421 if (ppd->dd->cspec->r1) 2422 cancel_delayed_work_sync(&ppd->cpspec->ipg_work); 2423 2424 ppd->cpspec->chase_end = 0; 2425 if (ppd->cpspec->chase_timer.data) /* if initted */ 2426 del_timer_sync(&ppd->cpspec->chase_timer); 2427 2428 /* 2429 * Despite the name, actually disables IBC as well. Do it when 2430 * we are as sure as possible that no more packets can be 2431 * received, following the down and the PCS reset. 2432 * The actual disabling happens in qib_7322_mini_pci_reset(), 2433 * along with the PCS being reset. 2434 */ 2435 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2436 qib_7322_mini_pcs_reset(ppd); 2437 2438 /* 2439 * Update the adjusted counters so the adjustment persists 2440 * across driver reload. 2441 */ 2442 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || 2443 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) { 2444 struct qib_devdata *dd = ppd->dd; 2445 u64 diagc; 2446 2447 /* enable counter writes */ 2448 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); 2449 qib_write_kreg(dd, kr_hwdiagctrl, 2450 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); 2451 2452 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) { 2453 val = read_7322_creg32_port(ppd, crp_ibsymbolerr); 2454 if (ppd->cpspec->ibdeltainprog) 2455 val -= val - ppd->cpspec->ibsymsnap; 2456 val -= ppd->cpspec->ibsymdelta; 2457 write_7322_creg_port(ppd, crp_ibsymbolerr, val); 2458 } 2459 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) { 2460 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov); 2461 if (ppd->cpspec->ibdeltainprog) 2462 val -= val - ppd->cpspec->iblnkerrsnap; 2463 val -= ppd->cpspec->iblnkerrdelta; 2464 write_7322_creg_port(ppd, crp_iblinkerrrecov, val); 2465 } 2466 if (ppd->cpspec->iblnkdowndelta) { 2467 val = read_7322_creg32_port(ppd, crp_iblinkdown); 2468 val += ppd->cpspec->iblnkdowndelta; 2469 write_7322_creg_port(ppd, crp_iblinkdown, val); 2470 } 2471 /* 2472 * No need to save ibmalfdelta since IB perfcounters 2473 * are cleared on driver reload. 2474 */ 2475 2476 /* and disable counter writes */ 2477 qib_write_kreg(dd, kr_hwdiagctrl, diagc); 2478 } 2479 } 2480 2481 /** 2482 * qib_setup_7322_setextled - set the state of the two external LEDs 2483 * @ppd: physical port on the qlogic_ib device 2484 * @on: whether the link is up or not 2485 * 2486 * The exact combo of LEDs if on is true is determined by looking 2487 * at the ibcstatus. 2488 * 2489 * These LEDs indicate the physical and logical state of IB link. 2490 * For this chip (at least with recommended board pinouts), LED1 2491 * is Yellow (logical state) and LED2 is Green (physical state), 2492 * 2493 * Note: We try to match the Mellanox HCA LED behavior as best 2494 * we can. Green indicates physical link state is OK (something is 2495 * plugged in, and we can train). 2496 * Amber indicates the link is logically up (ACTIVE). 2497 * Mellanox further blinks the amber LED to indicate data packet 2498 * activity, but we have no hardware support for that, so it would 2499 * require waking up every 10-20 msecs and checking the counters 2500 * on the chip, and then turning the LED off if appropriate. That's 2501 * visible overhead, so not something we will do. 2502 */ 2503 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) 2504 { 2505 struct qib_devdata *dd = ppd->dd; 2506 u64 extctl, ledblink = 0, val; 2507 unsigned long flags; 2508 int yel, grn; 2509 2510 /* 2511 * The diags use the LED to indicate diag info, so we leave 2512 * the external LED alone when the diags are running. 2513 */ 2514 if (dd->diag_client) 2515 return; 2516 2517 /* Allow override of LED display for, e.g. Locating system in rack */ 2518 if (ppd->led_override) { 2519 grn = (ppd->led_override & QIB_LED_PHYS); 2520 yel = (ppd->led_override & QIB_LED_LOG); 2521 } else if (on) { 2522 val = qib_read_kreg_port(ppd, krp_ibcstatus_a); 2523 grn = qib_7322_phys_portstate(val) == 2524 IB_PHYSPORTSTATE_LINKUP; 2525 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE; 2526 } else { 2527 grn = 0; 2528 yel = 0; 2529 } 2530 2531 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2532 extctl = dd->cspec->extctrl & (ppd->port == 1 ? 2533 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK); 2534 if (grn) { 2535 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN; 2536 /* 2537 * Counts are in chip clock (4ns) periods. 2538 * This is 1/16 sec (66.6ms) on, 2539 * 3/16 sec (187.5 ms) off, with packets rcvd. 2540 */ 2541 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) | 2542 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT); 2543 } 2544 if (yel) 2545 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL; 2546 dd->cspec->extctrl = extctl; 2547 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 2548 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2549 2550 if (ledblink) /* blink the LED on packet receive */ 2551 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); 2552 } 2553 2554 /* 2555 * Disable MSIx interrupt if enabled, call generic MSIx code 2556 * to cleanup, and clear pending MSIx interrupts. 2557 * Used for fallback to INTx, after reset, and when MSIx setup fails. 2558 */ 2559 static void qib_7322_nomsix(struct qib_devdata *dd) 2560 { 2561 u64 intgranted; 2562 int n; 2563 2564 dd->cspec->main_int_mask = ~0ULL; 2565 n = dd->cspec->num_msix_entries; 2566 if (n) { 2567 int i; 2568 2569 dd->cspec->num_msix_entries = 0; 2570 for (i = 0; i < n; i++) 2571 free_irq(dd->cspec->msix_entries[i].vector, 2572 dd->cspec->msix_arg[i]); 2573 qib_nomsix(dd); 2574 } 2575 /* make sure no MSIx interrupts are left pending */ 2576 intgranted = qib_read_kreg64(dd, kr_intgranted); 2577 if (intgranted) 2578 qib_write_kreg(dd, kr_intgranted, intgranted); 2579 } 2580 2581 static void qib_7322_free_irq(struct qib_devdata *dd) 2582 { 2583 if (dd->cspec->irq) { 2584 free_irq(dd->cspec->irq, dd); 2585 dd->cspec->irq = 0; 2586 } 2587 qib_7322_nomsix(dd); 2588 } 2589 2590 static void qib_setup_7322_cleanup(struct qib_devdata *dd) 2591 { 2592 int i; 2593 2594 qib_7322_free_irq(dd); 2595 kfree(dd->cspec->cntrs); 2596 kfree(dd->cspec->sendchkenable); 2597 kfree(dd->cspec->sendgrhchk); 2598 kfree(dd->cspec->sendibchk); 2599 kfree(dd->cspec->msix_entries); 2600 kfree(dd->cspec->msix_arg); 2601 for (i = 0; i < dd->num_pports; i++) { 2602 unsigned long flags; 2603 u32 mask = QSFP_GPIO_MOD_PRS_N | 2604 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT); 2605 2606 kfree(dd->pport[i].cpspec->portcntrs); 2607 if (dd->flags & QIB_HAS_QSFP) { 2608 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2609 dd->cspec->gpio_mask &= ~mask; 2610 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 2611 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2612 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data); 2613 } 2614 if (dd->pport[i].ibport_data.smi_ah) 2615 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah); 2616 } 2617 } 2618 2619 /* handle SDMA interrupts */ 2620 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) 2621 { 2622 struct qib_pportdata *ppd0 = &dd->pport[0]; 2623 struct qib_pportdata *ppd1 = &dd->pport[1]; 2624 u64 intr0 = istat & (INT_MASK_P(SDma, 0) | 2625 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0)); 2626 u64 intr1 = istat & (INT_MASK_P(SDma, 1) | 2627 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1)); 2628 2629 if (intr0) 2630 qib_sdma_intr(ppd0); 2631 if (intr1) 2632 qib_sdma_intr(ppd1); 2633 2634 if (istat & INT_MASK_PM(SDmaCleanupDone, 0)) 2635 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started); 2636 if (istat & INT_MASK_PM(SDmaCleanupDone, 1)) 2637 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started); 2638 } 2639 2640 /* 2641 * Set or clear the Send buffer available interrupt enable bit. 2642 */ 2643 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) 2644 { 2645 unsigned long flags; 2646 2647 spin_lock_irqsave(&dd->sendctrl_lock, flags); 2648 if (needint) 2649 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); 2650 else 2651 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); 2652 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 2653 qib_write_kreg(dd, kr_scratch, 0ULL); 2654 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 2655 } 2656 2657 /* 2658 * Somehow got an interrupt with reserved bits set in interrupt status. 2659 * Print a message so we know it happened, then clear them. 2660 * keep mainline interrupt handler cache-friendly 2661 */ 2662 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) 2663 { 2664 u64 kills; 2665 char msg[128]; 2666 2667 kills = istat & ~QIB_I_BITSEXTANT; 2668 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:" 2669 " %s\n", (unsigned long long) kills, msg); 2670 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); 2671 } 2672 2673 /* keep mainline interrupt handler cache-friendly */ 2674 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) 2675 { 2676 u32 gpiostatus; 2677 int handled = 0; 2678 int pidx; 2679 2680 /* 2681 * Boards for this chip currently don't use GPIO interrupts, 2682 * so clear by writing GPIOstatus to GPIOclear, and complain 2683 * to developer. To avoid endless repeats, clear 2684 * the bits in the mask, since there is some kind of 2685 * programming error or chip problem. 2686 */ 2687 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); 2688 /* 2689 * In theory, writing GPIOstatus to GPIOclear could 2690 * have a bad side-effect on some diagnostic that wanted 2691 * to poll for a status-change, but the various shadows 2692 * make that problematic at best. Diags will just suppress 2693 * all GPIO interrupts during such tests. 2694 */ 2695 qib_write_kreg(dd, kr_gpio_clear, gpiostatus); 2696 /* 2697 * Check for QSFP MOD_PRS changes 2698 * only works for single port if IB1 != pidx1 2699 */ 2700 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); 2701 ++pidx) { 2702 struct qib_pportdata *ppd; 2703 struct qib_qsfp_data *qd; 2704 u32 mask; 2705 if (!dd->pport[pidx].link_speed_supported) 2706 continue; 2707 mask = QSFP_GPIO_MOD_PRS_N; 2708 ppd = dd->pport + pidx; 2709 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 2710 if (gpiostatus & dd->cspec->gpio_mask & mask) { 2711 u64 pins; 2712 qd = &ppd->cpspec->qsfp_data; 2713 gpiostatus &= ~mask; 2714 pins = qib_read_kreg64(dd, kr_extstatus); 2715 pins >>= SYM_LSB(EXTStatus, GPIOIn); 2716 if (!(pins & mask)) { 2717 ++handled; 2718 qd->t_insert = jiffies; 2719 queue_work(ib_wq, &qd->work); 2720 } 2721 } 2722 } 2723 2724 if (gpiostatus && !handled) { 2725 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); 2726 u32 gpio_irq = mask & gpiostatus; 2727 2728 /* 2729 * Clear any troublemakers, and update chip from shadow 2730 */ 2731 dd->cspec->gpio_mask &= ~gpio_irq; 2732 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 2733 } 2734 } 2735 2736 /* 2737 * Handle errors and unusual events first, separate function 2738 * to improve cache hits for fast path interrupt handling. 2739 */ 2740 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) 2741 { 2742 if (istat & ~QIB_I_BITSEXTANT) 2743 unknown_7322_ibits(dd, istat); 2744 if (istat & QIB_I_GPIO) 2745 unknown_7322_gpio_intr(dd); 2746 if (istat & QIB_I_C_ERROR) { 2747 qib_write_kreg(dd, kr_errmask, 0ULL); 2748 tasklet_schedule(&dd->error_tasklet); 2749 } 2750 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) 2751 handle_7322_p_errors(dd->rcd[0]->ppd); 2752 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) 2753 handle_7322_p_errors(dd->rcd[1]->ppd); 2754 } 2755 2756 /* 2757 * Dynamically adjust the rcv int timeout for a context based on incoming 2758 * packet rate. 2759 */ 2760 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts) 2761 { 2762 struct qib_devdata *dd = rcd->dd; 2763 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; 2764 2765 /* 2766 * Dynamically adjust idle timeout on chip 2767 * based on number of packets processed. 2768 */ 2769 if (npkts < rcv_int_count && timeout > 2) 2770 timeout >>= 1; 2771 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout) 2772 timeout = min(timeout << 1, rcv_int_timeout); 2773 else 2774 return; 2775 2776 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; 2777 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); 2778 } 2779 2780 /* 2781 * This is the main interrupt handler. 2782 * It will normally only be used for low frequency interrupts but may 2783 * have to handle all interrupts if INTx is enabled or fewer than normal 2784 * MSIx interrupts were allocated. 2785 * This routine should ignore the interrupt bits for any of the 2786 * dedicated MSIx handlers. 2787 */ 2788 static irqreturn_t qib_7322intr(int irq, void *data) 2789 { 2790 struct qib_devdata *dd = data; 2791 irqreturn_t ret; 2792 u64 istat; 2793 u64 ctxtrbits; 2794 u64 rmask; 2795 unsigned i; 2796 u32 npkts; 2797 2798 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { 2799 /* 2800 * This return value is not great, but we do not want the 2801 * interrupt core code to remove our interrupt handler 2802 * because we don't appear to be handling an interrupt 2803 * during a chip reset. 2804 */ 2805 ret = IRQ_HANDLED; 2806 goto bail; 2807 } 2808 2809 istat = qib_read_kreg64(dd, kr_intstatus); 2810 2811 if (unlikely(istat == ~0ULL)) { 2812 qib_bad_intrstatus(dd); 2813 qib_dev_err(dd, "Interrupt status all f's, skipping\n"); 2814 /* don't know if it was our interrupt or not */ 2815 ret = IRQ_NONE; 2816 goto bail; 2817 } 2818 2819 istat &= dd->cspec->main_int_mask; 2820 if (unlikely(!istat)) { 2821 /* already handled, or shared and not us */ 2822 ret = IRQ_NONE; 2823 goto bail; 2824 } 2825 2826 qib_stats.sps_ints++; 2827 if (dd->int_counter != (u32) -1) 2828 dd->int_counter++; 2829 2830 /* handle "errors" of various kinds first, device ahead of port */ 2831 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO | 2832 QIB_I_C_ERROR | INT_MASK_P(Err, 0) | 2833 INT_MASK_P(Err, 1)))) 2834 unlikely_7322_intr(dd, istat); 2835 2836 /* 2837 * Clear the interrupt bits we found set, relatively early, so we 2838 * "know" know the chip will have seen this by the time we process 2839 * the queue, and will re-interrupt if necessary. The processor 2840 * itself won't take the interrupt again until we return. 2841 */ 2842 qib_write_kreg(dd, kr_intclear, istat); 2843 2844 /* 2845 * Handle kernel receive queues before checking for pio buffers 2846 * available since receives can overflow; piobuf waiters can afford 2847 * a few extra cycles, since they were waiting anyway. 2848 */ 2849 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK); 2850 if (ctxtrbits) { 2851 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) | 2852 (1ULL << QIB_I_RCVURG_LSB); 2853 for (i = 0; i < dd->first_user_ctxt; i++) { 2854 if (ctxtrbits & rmask) { 2855 ctxtrbits &= ~rmask; 2856 if (dd->rcd[i]) 2857 qib_kreceive(dd->rcd[i], NULL, &npkts); 2858 } 2859 rmask <<= 1; 2860 } 2861 if (ctxtrbits) { 2862 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) | 2863 (ctxtrbits >> QIB_I_RCVURG_LSB); 2864 qib_handle_urcv(dd, ctxtrbits); 2865 } 2866 } 2867 2868 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1))) 2869 sdma_7322_intr(dd, istat); 2870 2871 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) 2872 qib_ib_piobufavail(dd); 2873 2874 ret = IRQ_HANDLED; 2875 bail: 2876 return ret; 2877 } 2878 2879 /* 2880 * Dedicated receive packet available interrupt handler. 2881 */ 2882 static irqreturn_t qib_7322pintr(int irq, void *data) 2883 { 2884 struct qib_ctxtdata *rcd = data; 2885 struct qib_devdata *dd = rcd->dd; 2886 u32 npkts; 2887 2888 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2889 /* 2890 * This return value is not great, but we do not want the 2891 * interrupt core code to remove our interrupt handler 2892 * because we don't appear to be handling an interrupt 2893 * during a chip reset. 2894 */ 2895 return IRQ_HANDLED; 2896 2897 qib_stats.sps_ints++; 2898 if (dd->int_counter != (u32) -1) 2899 dd->int_counter++; 2900 2901 /* Clear the interrupt bit we expect to be set. */ 2902 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | 2903 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); 2904 2905 qib_kreceive(rcd, NULL, &npkts); 2906 2907 return IRQ_HANDLED; 2908 } 2909 2910 /* 2911 * Dedicated Send buffer available interrupt handler. 2912 */ 2913 static irqreturn_t qib_7322bufavail(int irq, void *data) 2914 { 2915 struct qib_devdata *dd = data; 2916 2917 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2918 /* 2919 * This return value is not great, but we do not want the 2920 * interrupt core code to remove our interrupt handler 2921 * because we don't appear to be handling an interrupt 2922 * during a chip reset. 2923 */ 2924 return IRQ_HANDLED; 2925 2926 qib_stats.sps_ints++; 2927 if (dd->int_counter != (u32) -1) 2928 dd->int_counter++; 2929 2930 /* Clear the interrupt bit we expect to be set. */ 2931 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); 2932 2933 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */ 2934 if (dd->flags & QIB_INITTED) 2935 qib_ib_piobufavail(dd); 2936 else 2937 qib_wantpiobuf_7322_intr(dd, 0); 2938 2939 return IRQ_HANDLED; 2940 } 2941 2942 /* 2943 * Dedicated Send DMA interrupt handler. 2944 */ 2945 static irqreturn_t sdma_intr(int irq, void *data) 2946 { 2947 struct qib_pportdata *ppd = data; 2948 struct qib_devdata *dd = ppd->dd; 2949 2950 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2951 /* 2952 * This return value is not great, but we do not want the 2953 * interrupt core code to remove our interrupt handler 2954 * because we don't appear to be handling an interrupt 2955 * during a chip reset. 2956 */ 2957 return IRQ_HANDLED; 2958 2959 qib_stats.sps_ints++; 2960 if (dd->int_counter != (u32) -1) 2961 dd->int_counter++; 2962 2963 /* Clear the interrupt bit we expect to be set. */ 2964 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 2965 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); 2966 qib_sdma_intr(ppd); 2967 2968 return IRQ_HANDLED; 2969 } 2970 2971 /* 2972 * Dedicated Send DMA idle interrupt handler. 2973 */ 2974 static irqreturn_t sdma_idle_intr(int irq, void *data) 2975 { 2976 struct qib_pportdata *ppd = data; 2977 struct qib_devdata *dd = ppd->dd; 2978 2979 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2980 /* 2981 * This return value is not great, but we do not want the 2982 * interrupt core code to remove our interrupt handler 2983 * because we don't appear to be handling an interrupt 2984 * during a chip reset. 2985 */ 2986 return IRQ_HANDLED; 2987 2988 qib_stats.sps_ints++; 2989 if (dd->int_counter != (u32) -1) 2990 dd->int_counter++; 2991 2992 /* Clear the interrupt bit we expect to be set. */ 2993 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 2994 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); 2995 qib_sdma_intr(ppd); 2996 2997 return IRQ_HANDLED; 2998 } 2999 3000 /* 3001 * Dedicated Send DMA progress interrupt handler. 3002 */ 3003 static irqreturn_t sdma_progress_intr(int irq, void *data) 3004 { 3005 struct qib_pportdata *ppd = data; 3006 struct qib_devdata *dd = ppd->dd; 3007 3008 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3009 /* 3010 * This return value is not great, but we do not want the 3011 * interrupt core code to remove our interrupt handler 3012 * because we don't appear to be handling an interrupt 3013 * during a chip reset. 3014 */ 3015 return IRQ_HANDLED; 3016 3017 qib_stats.sps_ints++; 3018 if (dd->int_counter != (u32) -1) 3019 dd->int_counter++; 3020 3021 /* Clear the interrupt bit we expect to be set. */ 3022 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3023 INT_MASK_P(SDmaProgress, 1) : 3024 INT_MASK_P(SDmaProgress, 0)); 3025 qib_sdma_intr(ppd); 3026 3027 return IRQ_HANDLED; 3028 } 3029 3030 /* 3031 * Dedicated Send DMA cleanup interrupt handler. 3032 */ 3033 static irqreturn_t sdma_cleanup_intr(int irq, void *data) 3034 { 3035 struct qib_pportdata *ppd = data; 3036 struct qib_devdata *dd = ppd->dd; 3037 3038 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3039 /* 3040 * This return value is not great, but we do not want the 3041 * interrupt core code to remove our interrupt handler 3042 * because we don't appear to be handling an interrupt 3043 * during a chip reset. 3044 */ 3045 return IRQ_HANDLED; 3046 3047 qib_stats.sps_ints++; 3048 if (dd->int_counter != (u32) -1) 3049 dd->int_counter++; 3050 3051 /* Clear the interrupt bit we expect to be set. */ 3052 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3053 INT_MASK_PM(SDmaCleanupDone, 1) : 3054 INT_MASK_PM(SDmaCleanupDone, 0)); 3055 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started); 3056 3057 return IRQ_HANDLED; 3058 } 3059 3060 /* 3061 * Set up our chip-specific interrupt handler. 3062 * The interrupt type has already been setup, so 3063 * we just need to do the registration and error checking. 3064 * If we are using MSIx interrupts, we may fall back to 3065 * INTx later, if the interrupt handler doesn't get called 3066 * within 1/2 second (see verify_interrupt()). 3067 */ 3068 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) 3069 { 3070 int ret, i, msixnum; 3071 u64 redirect[6]; 3072 u64 mask; 3073 3074 if (!dd->num_pports) 3075 return; 3076 3077 if (clearpend) { 3078 /* 3079 * if not switching interrupt types, be sure interrupts are 3080 * disabled, and then clear anything pending at this point, 3081 * because we are starting clean. 3082 */ 3083 qib_7322_set_intr_state(dd, 0); 3084 3085 /* clear the reset error, init error/hwerror mask */ 3086 qib_7322_init_hwerrors(dd); 3087 3088 /* clear any interrupt bits that might be set */ 3089 qib_write_kreg(dd, kr_intclear, ~0ULL); 3090 3091 /* make sure no pending MSIx intr, and clear diag reg */ 3092 qib_write_kreg(dd, kr_intgranted, ~0ULL); 3093 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); 3094 } 3095 3096 if (!dd->cspec->num_msix_entries) { 3097 /* Try to get INTx interrupt */ 3098 try_intx: 3099 if (!dd->pcidev->irq) { 3100 qib_dev_err(dd, "irq is 0, BIOS error? " 3101 "Interrupts won't work\n"); 3102 goto bail; 3103 } 3104 ret = request_irq(dd->pcidev->irq, qib_7322intr, 3105 IRQF_SHARED, QIB_DRV_NAME, dd); 3106 if (ret) { 3107 qib_dev_err(dd, "Couldn't setup INTx " 3108 "interrupt (irq=%d): %d\n", 3109 dd->pcidev->irq, ret); 3110 goto bail; 3111 } 3112 dd->cspec->irq = dd->pcidev->irq; 3113 dd->cspec->main_int_mask = ~0ULL; 3114 goto bail; 3115 } 3116 3117 /* Try to get MSIx interrupts */ 3118 memset(redirect, 0, sizeof redirect); 3119 mask = ~0ULL; 3120 msixnum = 0; 3121 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { 3122 irq_handler_t handler; 3123 const char *name; 3124 void *arg; 3125 u64 val; 3126 int lsb, reg, sh; 3127 3128 if (i < ARRAY_SIZE(irq_table)) { 3129 if (irq_table[i].port) { 3130 /* skip if for a non-configured port */ 3131 if (irq_table[i].port > dd->num_pports) 3132 continue; 3133 arg = dd->pport + irq_table[i].port - 1; 3134 } else 3135 arg = dd; 3136 lsb = irq_table[i].lsb; 3137 handler = irq_table[i].handler; 3138 name = irq_table[i].name; 3139 } else { 3140 unsigned ctxt; 3141 3142 ctxt = i - ARRAY_SIZE(irq_table); 3143 /* per krcvq context receive interrupt */ 3144 arg = dd->rcd[ctxt]; 3145 if (!arg) 3146 continue; 3147 if (qib_krcvq01_no_msi && ctxt < 2) 3148 continue; 3149 lsb = QIB_I_RCVAVAIL_LSB + ctxt; 3150 handler = qib_7322pintr; 3151 name = QIB_DRV_NAME " (kctx)"; 3152 } 3153 ret = request_irq(dd->cspec->msix_entries[msixnum].vector, 3154 handler, 0, name, arg); 3155 if (ret) { 3156 /* 3157 * Shouldn't happen since the enable said we could 3158 * have as many as we are trying to setup here. 3159 */ 3160 qib_dev_err(dd, "Couldn't setup MSIx " 3161 "interrupt (vec=%d, irq=%d): %d\n", msixnum, 3162 dd->cspec->msix_entries[msixnum].vector, 3163 ret); 3164 qib_7322_nomsix(dd); 3165 goto try_intx; 3166 } 3167 dd->cspec->msix_arg[msixnum] = arg; 3168 if (lsb >= 0) { 3169 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG; 3170 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) * 3171 SYM_LSB(IntRedirect0, vec1); 3172 mask &= ~(1ULL << lsb); 3173 redirect[reg] |= ((u64) msixnum) << sh; 3174 } 3175 val = qib_read_kreg64(dd, 2 * msixnum + 1 + 3176 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3177 msixnum++; 3178 } 3179 /* Initialize the vector mapping */ 3180 for (i = 0; i < ARRAY_SIZE(redirect); i++) 3181 qib_write_kreg(dd, kr_intredirect + i, redirect[i]); 3182 dd->cspec->main_int_mask = mask; 3183 tasklet_init(&dd->error_tasklet, qib_error_tasklet, 3184 (unsigned long)dd); 3185 bail:; 3186 } 3187 3188 /** 3189 * qib_7322_boardname - fill in the board name and note features 3190 * @dd: the qlogic_ib device 3191 * 3192 * info will be based on the board revision register 3193 */ 3194 static unsigned qib_7322_boardname(struct qib_devdata *dd) 3195 { 3196 /* Will need enumeration of board-types here */ 3197 char *n; 3198 u32 boardid, namelen; 3199 unsigned features = DUAL_PORT_CAP; 3200 3201 boardid = SYM_FIELD(dd->revision, Revision, BoardID); 3202 3203 switch (boardid) { 3204 case 0: 3205 n = "InfiniPath_QLE7342_Emulation"; 3206 break; 3207 case 1: 3208 n = "InfiniPath_QLE7340"; 3209 dd->flags |= QIB_HAS_QSFP; 3210 features = PORT_SPD_CAP; 3211 break; 3212 case 2: 3213 n = "InfiniPath_QLE7342"; 3214 dd->flags |= QIB_HAS_QSFP; 3215 break; 3216 case 3: 3217 n = "InfiniPath_QMI7342"; 3218 break; 3219 case 4: 3220 n = "InfiniPath_Unsupported7342"; 3221 qib_dev_err(dd, "Unsupported version of QMH7342\n"); 3222 features = 0; 3223 break; 3224 case BOARD_QMH7342: 3225 n = "InfiniPath_QMH7342"; 3226 features = 0x24; 3227 break; 3228 case BOARD_QME7342: 3229 n = "InfiniPath_QME7342"; 3230 break; 3231 case 8: 3232 n = "InfiniPath_QME7362"; 3233 dd->flags |= QIB_HAS_QSFP; 3234 break; 3235 case 15: 3236 n = "InfiniPath_QLE7342_TEST"; 3237 dd->flags |= QIB_HAS_QSFP; 3238 break; 3239 default: 3240 n = "InfiniPath_QLE73xy_UNKNOWN"; 3241 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); 3242 break; 3243 } 3244 dd->board_atten = 1; /* index into txdds_Xdr */ 3245 3246 namelen = strlen(n) + 1; 3247 dd->boardname = kmalloc(namelen, GFP_KERNEL); 3248 if (!dd->boardname) 3249 qib_dev_err(dd, "Failed allocation for board name: %s\n", n); 3250 else 3251 snprintf(dd->boardname, namelen, "%s", n); 3252 3253 snprintf(dd->boardversion, sizeof(dd->boardversion), 3254 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n", 3255 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, 3256 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch), 3257 dd->majrev, dd->minrev, 3258 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW)); 3259 3260 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) { 3261 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode" 3262 " by module parameter\n", dd->unit); 3263 features &= PORT_SPD_CAP; 3264 } 3265 3266 return features; 3267 } 3268 3269 /* 3270 * This routine sleeps, so it can only be called from user context, not 3271 * from interrupt context. 3272 */ 3273 static int qib_do_7322_reset(struct qib_devdata *dd) 3274 { 3275 u64 val; 3276 u64 *msix_vecsave; 3277 int i, msix_entries, ret = 1; 3278 u16 cmdval; 3279 u8 int_line, clinesz; 3280 unsigned long flags; 3281 3282 /* Use dev_err so it shows up in logs, etc. */ 3283 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); 3284 3285 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); 3286 3287 msix_entries = dd->cspec->num_msix_entries; 3288 3289 /* no interrupts till re-initted */ 3290 qib_7322_set_intr_state(dd, 0); 3291 3292 if (msix_entries) { 3293 qib_7322_nomsix(dd); 3294 /* can be up to 512 bytes, too big for stack */ 3295 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * 3296 sizeof(u64), GFP_KERNEL); 3297 if (!msix_vecsave) 3298 qib_dev_err(dd, "No mem to save MSIx data\n"); 3299 } else 3300 msix_vecsave = NULL; 3301 3302 /* 3303 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector 3304 * info that is set up by the BIOS, so we have to save and restore 3305 * it ourselves. There is some risk something could change it, 3306 * after we save it, but since we have disabled the MSIx, it 3307 * shouldn't be touched... 3308 */ 3309 for (i = 0; i < msix_entries; i++) { 3310 u64 vecaddr, vecdata; 3311 vecaddr = qib_read_kreg64(dd, 2 * i + 3312 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3313 vecdata = qib_read_kreg64(dd, 1 + 2 * i + 3314 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3315 if (msix_vecsave) { 3316 msix_vecsave[2 * i] = vecaddr; 3317 /* save it without the masked bit set */ 3318 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL; 3319 } 3320 } 3321 3322 dd->pport->cpspec->ibdeltainprog = 0; 3323 dd->pport->cpspec->ibsymdelta = 0; 3324 dd->pport->cpspec->iblnkerrdelta = 0; 3325 dd->pport->cpspec->ibmalfdelta = 0; 3326 dd->int_counter = 0; /* so we check interrupts work again */ 3327 3328 /* 3329 * Keep chip from being accessed until we are ready. Use 3330 * writeq() directly, to allow the write even though QIB_PRESENT 3331 * isn't set. 3332 */ 3333 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); 3334 dd->flags |= QIB_DOING_RESET; 3335 val = dd->control | QLOGIC_IB_C_RESET; 3336 writeq(val, &dd->kregbase[kr_control]); 3337 3338 for (i = 1; i <= 5; i++) { 3339 /* 3340 * Allow MBIST, etc. to complete; longer on each retry. 3341 * We sometimes get machine checks from bus timeout if no 3342 * response, so for now, make it *really* long. 3343 */ 3344 msleep(1000 + (1 + i) * 3000); 3345 3346 qib_pcie_reenable(dd, cmdval, int_line, clinesz); 3347 3348 /* 3349 * Use readq directly, so we don't need to mark it as PRESENT 3350 * until we get a successful indication that all is well. 3351 */ 3352 val = readq(&dd->kregbase[kr_revision]); 3353 if (val == dd->revision) 3354 break; 3355 if (i == 5) { 3356 qib_dev_err(dd, "Failed to initialize after reset, " 3357 "unusable\n"); 3358 ret = 0; 3359 goto bail; 3360 } 3361 } 3362 3363 dd->flags |= QIB_PRESENT; /* it's back */ 3364 3365 if (msix_entries) { 3366 /* restore the MSIx vector address and data if saved above */ 3367 for (i = 0; i < msix_entries; i++) { 3368 dd->cspec->msix_entries[i].entry = i; 3369 if (!msix_vecsave || !msix_vecsave[2 * i]) 3370 continue; 3371 qib_write_kreg(dd, 2 * i + 3372 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3373 msix_vecsave[2 * i]); 3374 qib_write_kreg(dd, 1 + 2 * i + 3375 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3376 msix_vecsave[1 + 2 * i]); 3377 } 3378 } 3379 3380 /* initialize the remaining registers. */ 3381 for (i = 0; i < dd->num_pports; ++i) 3382 write_7322_init_portregs(&dd->pport[i]); 3383 write_7322_initregs(dd); 3384 3385 if (qib_pcie_params(dd, dd->lbus_width, 3386 &dd->cspec->num_msix_entries, 3387 dd->cspec->msix_entries)) 3388 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; " 3389 "continuing anyway\n"); 3390 3391 qib_setup_7322_interrupt(dd, 1); 3392 3393 for (i = 0; i < dd->num_pports; ++i) { 3394 struct qib_pportdata *ppd = &dd->pport[i]; 3395 3396 spin_lock_irqsave(&ppd->lflags_lock, flags); 3397 ppd->lflags |= QIBL_IB_FORCE_NOTIFY; 3398 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 3399 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3400 } 3401 3402 bail: 3403 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ 3404 kfree(msix_vecsave); 3405 return ret; 3406 } 3407 3408 /** 3409 * qib_7322_put_tid - write a TID to the chip 3410 * @dd: the qlogic_ib device 3411 * @tidptr: pointer to the expected TID (in chip) to update 3412 * @tidtype: 0 for eager, 1 for expected 3413 * @pa: physical address of in memory buffer; tidinvalid if freeing 3414 */ 3415 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, 3416 u32 type, unsigned long pa) 3417 { 3418 if (!(dd->flags & QIB_PRESENT)) 3419 return; 3420 if (pa != dd->tidinvalid) { 3421 u64 chippa = pa >> IBA7322_TID_PA_SHIFT; 3422 3423 /* paranoia checks */ 3424 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) { 3425 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", 3426 pa); 3427 return; 3428 } 3429 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) { 3430 qib_dev_err(dd, "Physical page address 0x%lx " 3431 "larger than supported\n", pa); 3432 return; 3433 } 3434 3435 if (type == RCVHQ_RCV_TYPE_EAGER) 3436 chippa |= dd->tidtemplate; 3437 else /* for now, always full 4KB page */ 3438 chippa |= IBA7322_TID_SZ_4K; 3439 pa = chippa; 3440 } 3441 writeq(pa, tidptr); 3442 mmiowb(); 3443 } 3444 3445 /** 3446 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager 3447 * @dd: the qlogic_ib device 3448 * @ctxt: the ctxt 3449 * 3450 * clear all TID entries for a ctxt, expected and eager. 3451 * Used from qib_close(). 3452 */ 3453 static void qib_7322_clear_tids(struct qib_devdata *dd, 3454 struct qib_ctxtdata *rcd) 3455 { 3456 u64 __iomem *tidbase; 3457 unsigned long tidinv; 3458 u32 ctxt; 3459 int i; 3460 3461 if (!dd->kregbase || !rcd) 3462 return; 3463 3464 ctxt = rcd->ctxt; 3465 3466 tidinv = dd->tidinvalid; 3467 tidbase = (u64 __iomem *) 3468 ((char __iomem *) dd->kregbase + 3469 dd->rcvtidbase + 3470 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); 3471 3472 for (i = 0; i < dd->rcvtidcnt; i++) 3473 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, 3474 tidinv); 3475 3476 tidbase = (u64 __iomem *) 3477 ((char __iomem *) dd->kregbase + 3478 dd->rcvegrbase + 3479 rcd->rcvegr_tid_base * sizeof(*tidbase)); 3480 3481 for (i = 0; i < rcd->rcvegrcnt; i++) 3482 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, 3483 tidinv); 3484 } 3485 3486 /** 3487 * qib_7322_tidtemplate - setup constants for TID updates 3488 * @dd: the qlogic_ib device 3489 * 3490 * We setup stuff that we use a lot, to avoid calculating each time 3491 */ 3492 static void qib_7322_tidtemplate(struct qib_devdata *dd) 3493 { 3494 /* 3495 * For now, we always allocate 4KB buffers (at init) so we can 3496 * receive max size packets. We may want a module parameter to 3497 * specify 2KB or 4KB and/or make it per port instead of per device 3498 * for those who want to reduce memory footprint. Note that the 3499 * rcvhdrentsize size must be large enough to hold the largest 3500 * IB header (currently 96 bytes) that we expect to handle (plus of 3501 * course the 2 dwords of RHF). 3502 */ 3503 if (dd->rcvegrbufsize == 2048) 3504 dd->tidtemplate = IBA7322_TID_SZ_2K; 3505 else if (dd->rcvegrbufsize == 4096) 3506 dd->tidtemplate = IBA7322_TID_SZ_4K; 3507 dd->tidinvalid = 0; 3508 } 3509 3510 /** 3511 * qib_init_7322_get_base_info - set chip-specific flags for user code 3512 * @rcd: the qlogic_ib ctxt 3513 * @kbase: qib_base_info pointer 3514 * 3515 * We set the PCIE flag because the lower bandwidth on PCIe vs 3516 * HyperTransport can affect some user packet algorithims. 3517 */ 3518 3519 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd, 3520 struct qib_base_info *kinfo) 3521 { 3522 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP | 3523 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL | 3524 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA; 3525 if (rcd->dd->cspec->r1) 3526 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK; 3527 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) 3528 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER; 3529 3530 return 0; 3531 } 3532 3533 static struct qib_message_header * 3534 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) 3535 { 3536 u32 offset = qib_hdrget_offset(rhf_addr); 3537 3538 return (struct qib_message_header *) 3539 (rhf_addr - dd->rhf_offset + offset); 3540 } 3541 3542 /* 3543 * Configure number of contexts. 3544 */ 3545 static void qib_7322_config_ctxts(struct qib_devdata *dd) 3546 { 3547 unsigned long flags; 3548 u32 nchipctxts; 3549 3550 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); 3551 dd->cspec->numctxts = nchipctxts; 3552 if (qib_n_krcv_queues > 1 && dd->num_pports) { 3553 dd->first_user_ctxt = NUM_IB_PORTS + 3554 (qib_n_krcv_queues - 1) * dd->num_pports; 3555 if (dd->first_user_ctxt > nchipctxts) 3556 dd->first_user_ctxt = nchipctxts; 3557 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; 3558 } else { 3559 dd->first_user_ctxt = NUM_IB_PORTS; 3560 dd->n_krcv_queues = 1; 3561 } 3562 3563 if (!qib_cfgctxts) { 3564 int nctxts = dd->first_user_ctxt + num_online_cpus(); 3565 3566 if (nctxts <= 6) 3567 dd->ctxtcnt = 6; 3568 else if (nctxts <= 10) 3569 dd->ctxtcnt = 10; 3570 else if (nctxts <= nchipctxts) 3571 dd->ctxtcnt = nchipctxts; 3572 } else if (qib_cfgctxts < dd->num_pports) 3573 dd->ctxtcnt = dd->num_pports; 3574 else if (qib_cfgctxts <= nchipctxts) 3575 dd->ctxtcnt = qib_cfgctxts; 3576 if (!dd->ctxtcnt) /* none of the above, set to max */ 3577 dd->ctxtcnt = nchipctxts; 3578 3579 /* 3580 * Chip can be configured for 6, 10, or 18 ctxts, and choice 3581 * affects number of eager TIDs per ctxt (1K, 2K, 4K). 3582 * Lock to be paranoid about later motion, etc. 3583 */ 3584 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 3585 if (dd->ctxtcnt > 10) 3586 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); 3587 else if (dd->ctxtcnt > 6) 3588 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); 3589 /* else configure for default 6 receive ctxts */ 3590 3591 /* The XRC opcode is 5. */ 3592 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); 3593 3594 /* 3595 * RcvCtrl *must* be written here so that the 3596 * chip understands how to change rcvegrcnt below. 3597 */ 3598 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 3599 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 3600 3601 /* kr_rcvegrcnt changes based on the number of contexts enabled */ 3602 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3603 if (qib_rcvhdrcnt) 3604 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); 3605 else 3606 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, 3607 dd->num_pports > 1 ? 1024U : 2048U); 3608 } 3609 3610 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) 3611 { 3612 3613 int lsb, ret = 0; 3614 u64 maskr; /* right-justified mask */ 3615 3616 switch (which) { 3617 3618 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */ 3619 ret = ppd->link_width_enabled; 3620 goto done; 3621 3622 case QIB_IB_CFG_LWID: /* Get currently active Link-width */ 3623 ret = ppd->link_width_active; 3624 goto done; 3625 3626 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */ 3627 ret = ppd->link_speed_enabled; 3628 goto done; 3629 3630 case QIB_IB_CFG_SPD: /* Get current Link spd */ 3631 ret = ppd->link_speed_active; 3632 goto done; 3633 3634 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */ 3635 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3636 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3637 break; 3638 3639 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */ 3640 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3641 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3642 break; 3643 3644 case QIB_IB_CFG_LINKLATENCY: 3645 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 3646 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); 3647 goto done; 3648 3649 case QIB_IB_CFG_OP_VLS: 3650 ret = ppd->vls_operational; 3651 goto done; 3652 3653 case QIB_IB_CFG_VL_HIGH_CAP: 3654 ret = 16; 3655 goto done; 3656 3657 case QIB_IB_CFG_VL_LOW_CAP: 3658 ret = 16; 3659 goto done; 3660 3661 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 3662 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3663 OverrunThreshold); 3664 goto done; 3665 3666 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 3667 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3668 PhyerrThreshold); 3669 goto done; 3670 3671 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 3672 /* will only take effect when the link state changes */ 3673 ret = (ppd->cpspec->ibcctrl_a & 3674 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? 3675 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL; 3676 goto done; 3677 3678 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */ 3679 lsb = IBA7322_IBC_HRTBT_LSB; 3680 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 3681 break; 3682 3683 case QIB_IB_CFG_PMA_TICKS: 3684 /* 3685 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs 3686 * Since the clock is always 250MHz, the value is 3, 1 or 0. 3687 */ 3688 if (ppd->link_speed_active == QIB_IB_QDR) 3689 ret = 3; 3690 else if (ppd->link_speed_active == QIB_IB_DDR) 3691 ret = 1; 3692 else 3693 ret = 0; 3694 goto done; 3695 3696 default: 3697 ret = -EINVAL; 3698 goto done; 3699 } 3700 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr); 3701 done: 3702 return ret; 3703 } 3704 3705 /* 3706 * Below again cribbed liberally from older version. Do not lean 3707 * heavily on it. 3708 */ 3709 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB 3710 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \ 3711 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16)) 3712 3713 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) 3714 { 3715 struct qib_devdata *dd = ppd->dd; 3716 u64 maskr; /* right-justified mask */ 3717 int lsb, ret = 0; 3718 u16 lcmd, licmd; 3719 unsigned long flags; 3720 3721 switch (which) { 3722 case QIB_IB_CFG_LIDLMC: 3723 /* 3724 * Set LID and LMC. Combined to avoid possible hazard 3725 * caller puts LMC in 16MSbits, DLID in 16LSbits of val 3726 */ 3727 lsb = IBA7322_IBC_DLIDLMC_SHIFT; 3728 maskr = IBA7322_IBC_DLIDLMC_MASK; 3729 /* 3730 * For header-checking, the SLID in the packet will 3731 * be masked with SendIBSLMCMask, and compared 3732 * with SendIBSLIDAssignMask. Make sure we do not 3733 * set any bits not covered by the mask, or we get 3734 * false-positives. 3735 */ 3736 qib_write_kreg_port(ppd, krp_sendslid, 3737 val & (val >> 16) & SendIBSLIDAssignMask); 3738 qib_write_kreg_port(ppd, krp_sendslidmask, 3739 (val >> 16) & SendIBSLMCMask); 3740 break; 3741 3742 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */ 3743 ppd->link_width_enabled = val; 3744 /* convert IB value to chip register value */ 3745 if (val == IB_WIDTH_1X) 3746 val = 0; 3747 else if (val == IB_WIDTH_4X) 3748 val = 1; 3749 else 3750 val = 3; 3751 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS); 3752 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); 3753 break; 3754 3755 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */ 3756 /* 3757 * As with width, only write the actual register if the 3758 * link is currently down, otherwise takes effect on next 3759 * link change. Since setting is being explicitly requested 3760 * (via MAD or sysfs), clear autoneg failure status if speed 3761 * autoneg is enabled. 3762 */ 3763 ppd->link_speed_enabled = val; 3764 val <<= IBA7322_IBC_SPEED_LSB; 3765 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK | 3766 IBA7322_IBC_MAX_SPEED_MASK; 3767 if (val & (val - 1)) { 3768 /* Muliple speeds enabled */ 3769 val |= IBA7322_IBC_IBTA_1_2_MASK | 3770 IBA7322_IBC_MAX_SPEED_MASK; 3771 spin_lock_irqsave(&ppd->lflags_lock, flags); 3772 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 3773 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3774 } else if (val & IBA7322_IBC_SPEED_QDR) 3775 val |= IBA7322_IBC_IBTA_1_2_MASK; 3776 /* IBTA 1.2 mode + min/max + speed bits are contiguous */ 3777 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); 3778 break; 3779 3780 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */ 3781 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3782 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3783 break; 3784 3785 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */ 3786 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3787 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3788 break; 3789 3790 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 3791 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3792 OverrunThreshold); 3793 if (maskr != val) { 3794 ppd->cpspec->ibcctrl_a &= 3795 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); 3796 ppd->cpspec->ibcctrl_a |= (u64) val << 3797 SYM_LSB(IBCCtrlA_0, OverrunThreshold); 3798 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3799 ppd->cpspec->ibcctrl_a); 3800 qib_write_kreg(dd, kr_scratch, 0ULL); 3801 } 3802 goto bail; 3803 3804 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 3805 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3806 PhyerrThreshold); 3807 if (maskr != val) { 3808 ppd->cpspec->ibcctrl_a &= 3809 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); 3810 ppd->cpspec->ibcctrl_a |= (u64) val << 3811 SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 3812 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3813 ppd->cpspec->ibcctrl_a); 3814 qib_write_kreg(dd, kr_scratch, 0ULL); 3815 } 3816 goto bail; 3817 3818 case QIB_IB_CFG_PKEYS: /* update pkeys */ 3819 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | 3820 ((u64) ppd->pkeys[2] << 32) | 3821 ((u64) ppd->pkeys[3] << 48); 3822 qib_write_kreg_port(ppd, krp_partitionkey, maskr); 3823 goto bail; 3824 3825 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 3826 /* will only take effect when the link state changes */ 3827 if (val == IB_LINKINITCMD_POLL) 3828 ppd->cpspec->ibcctrl_a &= 3829 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 3830 else /* SLEEP */ 3831 ppd->cpspec->ibcctrl_a |= 3832 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 3833 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 3834 qib_write_kreg(dd, kr_scratch, 0ULL); 3835 goto bail; 3836 3837 case QIB_IB_CFG_MTU: /* update the MTU in IBC */ 3838 /* 3839 * Update our housekeeping variables, and set IBC max 3840 * size, same as init code; max IBC is max we allow in 3841 * buffer, less the qword pbc, plus 1 for ICRC, in dwords 3842 * Set even if it's unchanged, print debug message only 3843 * on changes. 3844 */ 3845 val = (ppd->ibmaxlen >> 2) + 1; 3846 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); 3847 ppd->cpspec->ibcctrl_a |= (u64)val << 3848 SYM_LSB(IBCCtrlA_0, MaxPktLen); 3849 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3850 ppd->cpspec->ibcctrl_a); 3851 qib_write_kreg(dd, kr_scratch, 0ULL); 3852 goto bail; 3853 3854 case QIB_IB_CFG_LSTATE: /* set the IB link state */ 3855 switch (val & 0xffff0000) { 3856 case IB_LINKCMD_DOWN: 3857 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN; 3858 ppd->cpspec->ibmalfusesnap = 1; 3859 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 3860 crp_errlink); 3861 if (!ppd->cpspec->ibdeltainprog && 3862 qib_compat_ddr_negotiate) { 3863 ppd->cpspec->ibdeltainprog = 1; 3864 ppd->cpspec->ibsymsnap = 3865 read_7322_creg32_port(ppd, 3866 crp_ibsymbolerr); 3867 ppd->cpspec->iblnkerrsnap = 3868 read_7322_creg32_port(ppd, 3869 crp_iblinkerrrecov); 3870 } 3871 break; 3872 3873 case IB_LINKCMD_ARMED: 3874 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED; 3875 if (ppd->cpspec->ibmalfusesnap) { 3876 ppd->cpspec->ibmalfusesnap = 0; 3877 ppd->cpspec->ibmalfdelta += 3878 read_7322_creg32_port(ppd, 3879 crp_errlink) - 3880 ppd->cpspec->ibmalfsnap; 3881 } 3882 break; 3883 3884 case IB_LINKCMD_ACTIVE: 3885 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE; 3886 break; 3887 3888 default: 3889 ret = -EINVAL; 3890 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); 3891 goto bail; 3892 } 3893 switch (val & 0xffff) { 3894 case IB_LINKINITCMD_NOP: 3895 licmd = 0; 3896 break; 3897 3898 case IB_LINKINITCMD_POLL: 3899 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL; 3900 break; 3901 3902 case IB_LINKINITCMD_SLEEP: 3903 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP; 3904 break; 3905 3906 case IB_LINKINITCMD_DISABLE: 3907 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE; 3908 ppd->cpspec->chase_end = 0; 3909 /* 3910 * stop state chase counter and timer, if running. 3911 * wait forpending timer, but don't clear .data (ppd)! 3912 */ 3913 if (ppd->cpspec->chase_timer.expires) { 3914 del_timer_sync(&ppd->cpspec->chase_timer); 3915 ppd->cpspec->chase_timer.expires = 0; 3916 } 3917 break; 3918 3919 default: 3920 ret = -EINVAL; 3921 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", 3922 val & 0xffff); 3923 goto bail; 3924 } 3925 qib_set_ib_7322_lstate(ppd, lcmd, licmd); 3926 goto bail; 3927 3928 case QIB_IB_CFG_OP_VLS: 3929 if (ppd->vls_operational != val) { 3930 ppd->vls_operational = val; 3931 set_vls(ppd); 3932 } 3933 goto bail; 3934 3935 case QIB_IB_CFG_VL_HIGH_LIMIT: 3936 qib_write_kreg_port(ppd, krp_highprio_limit, val); 3937 goto bail; 3938 3939 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */ 3940 if (val > 3) { 3941 ret = -EINVAL; 3942 goto bail; 3943 } 3944 lsb = IBA7322_IBC_HRTBT_LSB; 3945 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 3946 break; 3947 3948 case QIB_IB_CFG_PORT: 3949 /* val is the port number of the switch we are connected to. */ 3950 if (ppd->dd->cspec->r1) { 3951 cancel_delayed_work(&ppd->cpspec->ipg_work); 3952 ppd->cpspec->ipg_tries = 0; 3953 } 3954 goto bail; 3955 3956 default: 3957 ret = -EINVAL; 3958 goto bail; 3959 } 3960 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb); 3961 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); 3962 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 3963 qib_write_kreg(dd, kr_scratch, 0); 3964 bail: 3965 return ret; 3966 } 3967 3968 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what) 3969 { 3970 int ret = 0; 3971 u64 val, ctrlb; 3972 3973 /* only IBC loopback, may add serdes and xgxs loopbacks later */ 3974 if (!strncmp(what, "ibc", 3)) { 3975 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, 3976 Loopback); 3977 val = 0; /* disable heart beat, so link will come up */ 3978 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", 3979 ppd->dd->unit, ppd->port); 3980 } else if (!strncmp(what, "off", 3)) { 3981 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, 3982 Loopback); 3983 /* enable heart beat again */ 3984 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB; 3985 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback " 3986 "(normal)\n", ppd->dd->unit, ppd->port); 3987 } else 3988 ret = -EINVAL; 3989 if (!ret) { 3990 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3991 ppd->cpspec->ibcctrl_a); 3992 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK 3993 << IBA7322_IBC_HRTBT_LSB); 3994 ppd->cpspec->ibcctrl_b = ctrlb | val; 3995 qib_write_kreg_port(ppd, krp_ibcctrl_b, 3996 ppd->cpspec->ibcctrl_b); 3997 qib_write_kreg(ppd->dd, kr_scratch, 0); 3998 } 3999 return ret; 4000 } 4001 4002 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4003 struct ib_vl_weight_elem *vl) 4004 { 4005 unsigned i; 4006 4007 for (i = 0; i < 16; i++, regno++, vl++) { 4008 u32 val = qib_read_kreg_port(ppd, regno); 4009 4010 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & 4011 SYM_RMASK(LowPriority0_0, VirtualLane); 4012 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & 4013 SYM_RMASK(LowPriority0_0, Weight); 4014 } 4015 } 4016 4017 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4018 struct ib_vl_weight_elem *vl) 4019 { 4020 unsigned i; 4021 4022 for (i = 0; i < 16; i++, regno++, vl++) { 4023 u64 val; 4024 4025 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << 4026 SYM_LSB(LowPriority0_0, VirtualLane)) | 4027 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) << 4028 SYM_LSB(LowPriority0_0, Weight)); 4029 qib_write_kreg_port(ppd, regno, val); 4030 } 4031 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { 4032 struct qib_devdata *dd = ppd->dd; 4033 unsigned long flags; 4034 4035 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4036 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); 4037 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4038 qib_write_kreg(dd, kr_scratch, 0); 4039 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4040 } 4041 } 4042 4043 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t) 4044 { 4045 switch (which) { 4046 case QIB_IB_TBL_VL_HIGH_ARB: 4047 get_vl_weights(ppd, krp_highprio_0, t); 4048 break; 4049 4050 case QIB_IB_TBL_VL_LOW_ARB: 4051 get_vl_weights(ppd, krp_lowprio_0, t); 4052 break; 4053 4054 default: 4055 return -EINVAL; 4056 } 4057 return 0; 4058 } 4059 4060 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t) 4061 { 4062 switch (which) { 4063 case QIB_IB_TBL_VL_HIGH_ARB: 4064 set_vl_weights(ppd, krp_highprio_0, t); 4065 break; 4066 4067 case QIB_IB_TBL_VL_LOW_ARB: 4068 set_vl_weights(ppd, krp_lowprio_0, t); 4069 break; 4070 4071 default: 4072 return -EINVAL; 4073 } 4074 return 0; 4075 } 4076 4077 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, 4078 u32 updegr, u32 egrhd, u32 npkts) 4079 { 4080 /* 4081 * Need to write timeout register before updating rcvhdrhead to ensure 4082 * that the timer is enabled on reception of a packet. 4083 */ 4084 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT) 4085 adjust_rcv_timeout(rcd, npkts); 4086 if (updegr) 4087 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); 4088 mmiowb(); 4089 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4090 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4091 mmiowb(); 4092 } 4093 4094 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd) 4095 { 4096 u32 head, tail; 4097 4098 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); 4099 if (rcd->rcvhdrtail_kvaddr) 4100 tail = qib_get_rcvhdrtail(rcd); 4101 else 4102 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); 4103 return head == tail; 4104 } 4105 4106 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4107 QIB_RCVCTRL_CTXT_DIS | \ 4108 QIB_RCVCTRL_TIDFLOW_ENB | \ 4109 QIB_RCVCTRL_TIDFLOW_DIS | \ 4110 QIB_RCVCTRL_TAILUPD_ENB | \ 4111 QIB_RCVCTRL_TAILUPD_DIS | \ 4112 QIB_RCVCTRL_INTRAVAIL_ENB | \ 4113 QIB_RCVCTRL_INTRAVAIL_DIS | \ 4114 QIB_RCVCTRL_BP_ENB | \ 4115 QIB_RCVCTRL_BP_DIS) 4116 4117 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4118 QIB_RCVCTRL_CTXT_DIS | \ 4119 QIB_RCVCTRL_PKEY_DIS | \ 4120 QIB_RCVCTRL_PKEY_ENB) 4121 4122 /* 4123 * Modify the RCVCTRL register in chip-specific way. This 4124 * is a function because bit positions and (future) register 4125 * location is chip-specifc, but the needed operations are 4126 * generic. <op> is a bit-mask because we often want to 4127 * do multiple modifications. 4128 */ 4129 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, 4130 int ctxt) 4131 { 4132 struct qib_devdata *dd = ppd->dd; 4133 struct qib_ctxtdata *rcd; 4134 u64 mask, val; 4135 unsigned long flags; 4136 4137 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 4138 4139 if (op & QIB_RCVCTRL_TIDFLOW_ENB) 4140 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); 4141 if (op & QIB_RCVCTRL_TIDFLOW_DIS) 4142 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); 4143 if (op & QIB_RCVCTRL_TAILUPD_ENB) 4144 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4145 if (op & QIB_RCVCTRL_TAILUPD_DIS) 4146 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); 4147 if (op & QIB_RCVCTRL_PKEY_ENB) 4148 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4149 if (op & QIB_RCVCTRL_PKEY_DIS) 4150 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4151 if (ctxt < 0) { 4152 mask = (1ULL << dd->ctxtcnt) - 1; 4153 rcd = NULL; 4154 } else { 4155 mask = (1ULL << ctxt); 4156 rcd = dd->rcd[ctxt]; 4157 } 4158 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) { 4159 ppd->p_rcvctrl |= 4160 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4161 if (!(dd->flags & QIB_NODMA_RTAIL)) { 4162 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */ 4163 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4164 } 4165 /* Write these registers before the context is enabled. */ 4166 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 4167 rcd->rcvhdrqtailaddr_phys); 4168 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 4169 rcd->rcvhdrq_phys); 4170 rcd->seq_cnt = 1; 4171 } 4172 if (op & QIB_RCVCTRL_CTXT_DIS) 4173 ppd->p_rcvctrl &= 4174 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4175 if (op & QIB_RCVCTRL_BP_ENB) 4176 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); 4177 if (op & QIB_RCVCTRL_BP_DIS) 4178 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); 4179 if (op & QIB_RCVCTRL_INTRAVAIL_ENB) 4180 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); 4181 if (op & QIB_RCVCTRL_INTRAVAIL_DIS) 4182 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); 4183 /* 4184 * Decide which registers to write depending on the ops enabled. 4185 * Special case is "flush" (no bits set at all) 4186 * which needs to write both. 4187 */ 4188 if (op == 0 || (op & RCVCTRL_COMMON_MODS)) 4189 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 4190 if (op == 0 || (op & RCVCTRL_PORT_MODS)) 4191 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 4192 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { 4193 /* 4194 * Init the context registers also; if we were 4195 * disabled, tail and head should both be zero 4196 * already from the enable, but since we don't 4197 * know, we have to do it explicitly. 4198 */ 4199 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); 4200 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); 4201 4202 /* be sure enabling write seen; hd/tl should be 0 */ 4203 (void) qib_read_kreg32(dd, kr_scratch); 4204 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); 4205 dd->rcd[ctxt]->head = val; 4206 /* If kctxt, interrupt on next receive. */ 4207 if (ctxt < dd->first_user_ctxt) 4208 val |= dd->rhdrhead_intr_off; 4209 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4210 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && 4211 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { 4212 /* arm rcv interrupt */ 4213 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; 4214 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4215 } 4216 if (op & QIB_RCVCTRL_CTXT_DIS) { 4217 unsigned f; 4218 4219 /* Now that the context is disabled, clear these registers. */ 4220 if (ctxt >= 0) { 4221 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); 4222 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); 4223 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4224 qib_write_ureg(dd, ur_rcvflowtable + f, 4225 TIDFLOW_ERRBITS, ctxt); 4226 } else { 4227 unsigned i; 4228 4229 for (i = 0; i < dd->cfgctxts; i++) { 4230 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, 4231 i, 0); 4232 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); 4233 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4234 qib_write_ureg(dd, ur_rcvflowtable + f, 4235 TIDFLOW_ERRBITS, i); 4236 } 4237 } 4238 } 4239 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 4240 } 4241 4242 /* 4243 * Modify the SENDCTRL register in chip-specific way. This 4244 * is a function where there are multiple such registers with 4245 * slightly different layouts. 4246 * The chip doesn't allow back-to-back sendctrl writes, so write 4247 * the scratch register after writing sendctrl. 4248 * 4249 * Which register is written depends on the operation. 4250 * Most operate on the common register, while 4251 * SEND_ENB and SEND_DIS operate on the per-port ones. 4252 * SEND_ENB is included in common because it can change SPCL_TRIG 4253 */ 4254 #define SENDCTRL_COMMON_MODS (\ 4255 QIB_SENDCTRL_CLEAR | \ 4256 QIB_SENDCTRL_AVAIL_DIS | \ 4257 QIB_SENDCTRL_AVAIL_ENB | \ 4258 QIB_SENDCTRL_AVAIL_BLIP | \ 4259 QIB_SENDCTRL_DISARM | \ 4260 QIB_SENDCTRL_DISARM_ALL | \ 4261 QIB_SENDCTRL_SEND_ENB) 4262 4263 #define SENDCTRL_PORT_MODS (\ 4264 QIB_SENDCTRL_CLEAR | \ 4265 QIB_SENDCTRL_SEND_ENB | \ 4266 QIB_SENDCTRL_SEND_DIS | \ 4267 QIB_SENDCTRL_FLUSH) 4268 4269 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op) 4270 { 4271 struct qib_devdata *dd = ppd->dd; 4272 u64 tmp_dd_sendctrl; 4273 unsigned long flags; 4274 4275 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4276 4277 /* First the dd ones that are "sticky", saved in shadow */ 4278 if (op & QIB_SENDCTRL_CLEAR) 4279 dd->sendctrl = 0; 4280 if (op & QIB_SENDCTRL_AVAIL_DIS) 4281 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4282 else if (op & QIB_SENDCTRL_AVAIL_ENB) { 4283 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); 4284 if (dd->flags & QIB_USE_SPCL_TRIG) 4285 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); 4286 } 4287 4288 /* Then the ppd ones that are "sticky", saved in shadow */ 4289 if (op & QIB_SENDCTRL_SEND_DIS) 4290 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 4291 else if (op & QIB_SENDCTRL_SEND_ENB) 4292 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 4293 4294 if (op & QIB_SENDCTRL_DISARM_ALL) { 4295 u32 i, last; 4296 4297 tmp_dd_sendctrl = dd->sendctrl; 4298 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 4299 /* 4300 * Disarm any buffers that are not yet launched, 4301 * disabling updates until done. 4302 */ 4303 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4304 for (i = 0; i < last; i++) { 4305 qib_write_kreg(dd, kr_sendctrl, 4306 tmp_dd_sendctrl | 4307 SYM_MASK(SendCtrl, Disarm) | i); 4308 qib_write_kreg(dd, kr_scratch, 0); 4309 } 4310 } 4311 4312 if (op & QIB_SENDCTRL_FLUSH) { 4313 u64 tmp_ppd_sendctrl = ppd->p_sendctrl; 4314 4315 /* 4316 * Now drain all the fifos. The Abort bit should never be 4317 * needed, so for now, at least, we don't use it. 4318 */ 4319 tmp_ppd_sendctrl |= 4320 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | 4321 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | 4322 SYM_MASK(SendCtrl_0, TxeBypassIbc); 4323 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl); 4324 qib_write_kreg(dd, kr_scratch, 0); 4325 } 4326 4327 tmp_dd_sendctrl = dd->sendctrl; 4328 4329 if (op & QIB_SENDCTRL_DISARM) 4330 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | 4331 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) << 4332 SYM_LSB(SendCtrl, DisarmSendBuf)); 4333 if ((op & QIB_SENDCTRL_AVAIL_BLIP) && 4334 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) 4335 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4336 4337 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) { 4338 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); 4339 qib_write_kreg(dd, kr_scratch, 0); 4340 } 4341 4342 if (op == 0 || (op & SENDCTRL_PORT_MODS)) { 4343 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4344 qib_write_kreg(dd, kr_scratch, 0); 4345 } 4346 4347 if (op & QIB_SENDCTRL_AVAIL_BLIP) { 4348 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 4349 qib_write_kreg(dd, kr_scratch, 0); 4350 } 4351 4352 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4353 4354 if (op & QIB_SENDCTRL_FLUSH) { 4355 u32 v; 4356 /* 4357 * ensure writes have hit chip, then do a few 4358 * more reads, to allow DMA of pioavail registers 4359 * to occur, so in-memory copy is in sync with 4360 * the chip. Not always safe to sleep. 4361 */ 4362 v = qib_read_kreg32(dd, kr_scratch); 4363 qib_write_kreg(dd, kr_scratch, v); 4364 v = qib_read_kreg32(dd, kr_scratch); 4365 qib_write_kreg(dd, kr_scratch, v); 4366 qib_read_kreg32(dd, kr_scratch); 4367 } 4368 } 4369 4370 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */ 4371 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */ 4372 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */ 4373 4374 /** 4375 * qib_portcntr_7322 - read a per-port chip counter 4376 * @ppd: the qlogic_ib pport 4377 * @creg: the counter to read (not a chip offset) 4378 */ 4379 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) 4380 { 4381 struct qib_devdata *dd = ppd->dd; 4382 u64 ret = 0ULL; 4383 u16 creg; 4384 /* 0xffff for unimplemented or synthesized counters */ 4385 static const u32 xlator[] = { 4386 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG, 4387 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG, 4388 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount, 4389 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount, 4390 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount, 4391 [QIBPORTCNTR_SENDSTALL] = crp_sendstall, 4392 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG, 4393 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount, 4394 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount, 4395 [QIBPORTCNTR_RCVEBP] = crp_rcvebp, 4396 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl, 4397 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG, 4398 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */ 4399 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr, 4400 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr, 4401 [QIBPORTCNTR_ERRICRC] = crp_erricrc, 4402 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc, 4403 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc, 4404 [QIBPORTCNTR_BADFORMAT] = crp_badformat, 4405 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen, 4406 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr, 4407 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen, 4408 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl, 4409 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl, 4410 [QIBPORTCNTR_ERRLINK] = crp_errlink, 4411 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown, 4412 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov, 4413 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr, 4414 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt, 4415 [QIBPORTCNTR_ERRPKEY] = crp_errpkey, 4416 /* 4417 * the next 3 aren't really counters, but were implemented 4418 * as counters in older chips, so still get accessed as 4419 * though they were counters from this code. 4420 */ 4421 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval, 4422 [QIBPORTCNTR_PSSTART] = krp_psstart, 4423 [QIBPORTCNTR_PSSTAT] = krp_psstat, 4424 /* pseudo-counter, summed for all ports */ 4425 [QIBPORTCNTR_KHDROVFL] = 0xffff, 4426 }; 4427 4428 if (reg >= ARRAY_SIZE(xlator)) { 4429 qib_devinfo(ppd->dd->pcidev, 4430 "Unimplemented portcounter %u\n", reg); 4431 goto done; 4432 } 4433 creg = xlator[reg] & _PORT_CNTR_IDXMASK; 4434 4435 /* handle non-counters and special cases first */ 4436 if (reg == QIBPORTCNTR_KHDROVFL) { 4437 int i; 4438 4439 /* sum over all kernel contexts (skip if mini_init) */ 4440 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { 4441 struct qib_ctxtdata *rcd = dd->rcd[i]; 4442 4443 if (!rcd || rcd->ppd != ppd) 4444 continue; 4445 ret += read_7322_creg32(dd, cr_base_egrovfl + i); 4446 } 4447 goto done; 4448 } else if (reg == QIBPORTCNTR_RXDROPPKT) { 4449 /* 4450 * Used as part of the synthesis of port_rcv_errors 4451 * in the verbs code for IBTA counters. Not needed for 7322, 4452 * because all the errors are already counted by other cntrs. 4453 */ 4454 goto done; 4455 } else if (reg == QIBPORTCNTR_PSINTERVAL || 4456 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) { 4457 /* were counters in older chips, now per-port kernel regs */ 4458 ret = qib_read_kreg_port(ppd, creg); 4459 goto done; 4460 } 4461 4462 /* 4463 * Only fast increment counters are 64 bits; use 32 bit reads to 4464 * avoid two independent reads when on Opteron. 4465 */ 4466 if (xlator[reg] & _PORT_64BIT_FLAG) 4467 ret = read_7322_creg_port(ppd, creg); 4468 else 4469 ret = read_7322_creg32_port(ppd, creg); 4470 if (creg == crp_ibsymbolerr) { 4471 if (ppd->cpspec->ibdeltainprog) 4472 ret -= ret - ppd->cpspec->ibsymsnap; 4473 ret -= ppd->cpspec->ibsymdelta; 4474 } else if (creg == crp_iblinkerrrecov) { 4475 if (ppd->cpspec->ibdeltainprog) 4476 ret -= ret - ppd->cpspec->iblnkerrsnap; 4477 ret -= ppd->cpspec->iblnkerrdelta; 4478 } else if (creg == crp_errlink) 4479 ret -= ppd->cpspec->ibmalfdelta; 4480 else if (creg == crp_iblinkdown) 4481 ret += ppd->cpspec->iblnkdowndelta; 4482 done: 4483 return ret; 4484 } 4485 4486 /* 4487 * Device counter names (not port-specific), one line per stat, 4488 * single string. Used by utilities like ipathstats to print the stats 4489 * in a way which works for different versions of drivers, without changing 4490 * the utility. Names need to be 12 chars or less (w/o newline), for proper 4491 * display by utility. 4492 * Non-error counters are first. 4493 * Start of "error" conters is indicated by a leading "E " on the first 4494 * "error" counter, and doesn't count in label length. 4495 * The EgrOvfl list needs to be last so we truncate them at the configured 4496 * context count for the device. 4497 * cntr7322indices contains the corresponding register indices. 4498 */ 4499 static const char cntr7322names[] = 4500 "Interrupts\n" 4501 "HostBusStall\n" 4502 "E RxTIDFull\n" 4503 "RxTIDInvalid\n" 4504 "RxTIDFloDrop\n" /* 7322 only */ 4505 "Ctxt0EgrOvfl\n" 4506 "Ctxt1EgrOvfl\n" 4507 "Ctxt2EgrOvfl\n" 4508 "Ctxt3EgrOvfl\n" 4509 "Ctxt4EgrOvfl\n" 4510 "Ctxt5EgrOvfl\n" 4511 "Ctxt6EgrOvfl\n" 4512 "Ctxt7EgrOvfl\n" 4513 "Ctxt8EgrOvfl\n" 4514 "Ctxt9EgrOvfl\n" 4515 "Ctx10EgrOvfl\n" 4516 "Ctx11EgrOvfl\n" 4517 "Ctx12EgrOvfl\n" 4518 "Ctx13EgrOvfl\n" 4519 "Ctx14EgrOvfl\n" 4520 "Ctx15EgrOvfl\n" 4521 "Ctx16EgrOvfl\n" 4522 "Ctx17EgrOvfl\n" 4523 ; 4524 4525 static const u32 cntr7322indices[] = { 4526 cr_lbint | _PORT_64BIT_FLAG, 4527 cr_lbstall | _PORT_64BIT_FLAG, 4528 cr_tidfull, 4529 cr_tidinvalid, 4530 cr_rxtidflowdrop, 4531 cr_base_egrovfl + 0, 4532 cr_base_egrovfl + 1, 4533 cr_base_egrovfl + 2, 4534 cr_base_egrovfl + 3, 4535 cr_base_egrovfl + 4, 4536 cr_base_egrovfl + 5, 4537 cr_base_egrovfl + 6, 4538 cr_base_egrovfl + 7, 4539 cr_base_egrovfl + 8, 4540 cr_base_egrovfl + 9, 4541 cr_base_egrovfl + 10, 4542 cr_base_egrovfl + 11, 4543 cr_base_egrovfl + 12, 4544 cr_base_egrovfl + 13, 4545 cr_base_egrovfl + 14, 4546 cr_base_egrovfl + 15, 4547 cr_base_egrovfl + 16, 4548 cr_base_egrovfl + 17, 4549 }; 4550 4551 /* 4552 * same as cntr7322names and cntr7322indices, but for port-specific counters. 4553 * portcntr7322indices is somewhat complicated by some registers needing 4554 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG 4555 */ 4556 static const char portcntr7322names[] = 4557 "TxPkt\n" 4558 "TxFlowPkt\n" 4559 "TxWords\n" 4560 "RxPkt\n" 4561 "RxFlowPkt\n" 4562 "RxWords\n" 4563 "TxFlowStall\n" 4564 "TxDmaDesc\n" /* 7220 and 7322-only */ 4565 "E RxDlidFltr\n" /* 7220 and 7322-only */ 4566 "IBStatusChng\n" 4567 "IBLinkDown\n" 4568 "IBLnkRecov\n" 4569 "IBRxLinkErr\n" 4570 "IBSymbolErr\n" 4571 "RxLLIErr\n" 4572 "RxBadFormat\n" 4573 "RxBadLen\n" 4574 "RxBufOvrfl\n" 4575 "RxEBP\n" 4576 "RxFlowCtlErr\n" 4577 "RxICRCerr\n" 4578 "RxLPCRCerr\n" 4579 "RxVCRCerr\n" 4580 "RxInvalLen\n" 4581 "RxInvalPKey\n" 4582 "RxPktDropped\n" 4583 "TxBadLength\n" 4584 "TxDropped\n" 4585 "TxInvalLen\n" 4586 "TxUnderrun\n" 4587 "TxUnsupVL\n" 4588 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */ 4589 "RxVL15Drop\n" 4590 "RxVlErr\n" 4591 "XcessBufOvfl\n" 4592 "RxQPBadCtxt\n" /* 7322-only from here down */ 4593 "TXBadHeader\n" 4594 ; 4595 4596 static const u32 portcntr7322indices[] = { 4597 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG, 4598 crp_pktsendflow, 4599 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG, 4600 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG, 4601 crp_pktrcvflowctrl, 4602 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG, 4603 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG, 4604 crp_txsdmadesc | _PORT_64BIT_FLAG, 4605 crp_rxdlidfltr, 4606 crp_ibstatuschange, 4607 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG, 4608 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG, 4609 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG, 4610 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG, 4611 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG, 4612 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG, 4613 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG, 4614 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG, 4615 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG, 4616 crp_rcvflowctrlviol, 4617 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG, 4618 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG, 4619 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG, 4620 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG, 4621 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG, 4622 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG, 4623 crp_txminmaxlenerr, 4624 crp_txdroppedpkt, 4625 crp_txlenerr, 4626 crp_txunderrun, 4627 crp_txunsupvl, 4628 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG, 4629 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG, 4630 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG, 4631 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG, 4632 crp_rxqpinvalidctxt, 4633 crp_txhdrerr, 4634 }; 4635 4636 /* do all the setup to make the counter reads efficient later */ 4637 static void init_7322_cntrnames(struct qib_devdata *dd) 4638 { 4639 int i, j = 0; 4640 char *s; 4641 4642 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; 4643 i++) { 4644 /* we always have at least one counter before the egrovfl */ 4645 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12)) 4646 j = 1; 4647 s = strchr(s + 1, '\n'); 4648 if (s && j) 4649 j++; 4650 } 4651 dd->cspec->ncntrs = i; 4652 if (!s) 4653 /* full list; size is without terminating null */ 4654 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; 4655 else 4656 dd->cspec->cntrnamelen = 1 + s - cntr7322names; 4657 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 4658 * sizeof(u64), GFP_KERNEL); 4659 if (!dd->cspec->cntrs) 4660 qib_dev_err(dd, "Failed allocation for counters\n"); 4661 4662 for (i = 0, s = (char *)portcntr7322names; s; i++) 4663 s = strchr(s + 1, '\n'); 4664 dd->cspec->nportcntrs = i - 1; 4665 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; 4666 for (i = 0; i < dd->num_pports; ++i) { 4667 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs 4668 * sizeof(u64), GFP_KERNEL); 4669 if (!dd->pport[i].cpspec->portcntrs) 4670 qib_dev_err(dd, "Failed allocation for" 4671 " portcounters\n"); 4672 } 4673 } 4674 4675 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 4676 u64 **cntrp) 4677 { 4678 u32 ret; 4679 4680 if (namep) { 4681 ret = dd->cspec->cntrnamelen; 4682 if (pos >= ret) 4683 ret = 0; /* final read after getting everything */ 4684 else 4685 *namep = (char *) cntr7322names; 4686 } else { 4687 u64 *cntr = dd->cspec->cntrs; 4688 int i; 4689 4690 ret = dd->cspec->ncntrs * sizeof(u64); 4691 if (!cntr || pos >= ret) { 4692 /* everything read, or couldn't get memory */ 4693 ret = 0; 4694 goto done; 4695 } 4696 *cntrp = cntr; 4697 for (i = 0; i < dd->cspec->ncntrs; i++) 4698 if (cntr7322indices[i] & _PORT_64BIT_FLAG) 4699 *cntr++ = read_7322_creg(dd, 4700 cntr7322indices[i] & 4701 _PORT_CNTR_IDXMASK); 4702 else 4703 *cntr++ = read_7322_creg32(dd, 4704 cntr7322indices[i]); 4705 } 4706 done: 4707 return ret; 4708 } 4709 4710 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, 4711 char **namep, u64 **cntrp) 4712 { 4713 u32 ret; 4714 4715 if (namep) { 4716 ret = dd->cspec->portcntrnamelen; 4717 if (pos >= ret) 4718 ret = 0; /* final read after getting everything */ 4719 else 4720 *namep = (char *)portcntr7322names; 4721 } else { 4722 struct qib_pportdata *ppd = &dd->pport[port]; 4723 u64 *cntr = ppd->cpspec->portcntrs; 4724 int i; 4725 4726 ret = dd->cspec->nportcntrs * sizeof(u64); 4727 if (!cntr || pos >= ret) { 4728 /* everything read, or couldn't get memory */ 4729 ret = 0; 4730 goto done; 4731 } 4732 *cntrp = cntr; 4733 for (i = 0; i < dd->cspec->nportcntrs; i++) { 4734 if (portcntr7322indices[i] & _PORT_VIRT_FLAG) 4735 *cntr++ = qib_portcntr_7322(ppd, 4736 portcntr7322indices[i] & 4737 _PORT_CNTR_IDXMASK); 4738 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG) 4739 *cntr++ = read_7322_creg_port(ppd, 4740 portcntr7322indices[i] & 4741 _PORT_CNTR_IDXMASK); 4742 else 4743 *cntr++ = read_7322_creg32_port(ppd, 4744 portcntr7322indices[i]); 4745 } 4746 } 4747 done: 4748 return ret; 4749 } 4750 4751 /** 4752 * qib_get_7322_faststats - get word counters from chip before they overflow 4753 * @opaque - contains a pointer to the qlogic_ib device qib_devdata 4754 * 4755 * VESTIGIAL IBA7322 has no "small fast counters", so the only 4756 * real purpose of this function is to maintain the notion of 4757 * "active time", which in turn is only logged into the eeprom, 4758 * which we don;t have, yet, for 7322-based boards. 4759 * 4760 * called from add_timer 4761 */ 4762 static void qib_get_7322_faststats(unsigned long opaque) 4763 { 4764 struct qib_devdata *dd = (struct qib_devdata *) opaque; 4765 struct qib_pportdata *ppd; 4766 unsigned long flags; 4767 u64 traffic_wds; 4768 int pidx; 4769 4770 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 4771 ppd = dd->pport + pidx; 4772 4773 /* 4774 * If port isn't enabled or not operational ports, or 4775 * diags is running (can cause memory diags to fail) 4776 * skip this port this time. 4777 */ 4778 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) 4779 || dd->diag_client) 4780 continue; 4781 4782 /* 4783 * Maintain an activity timer, based on traffic 4784 * exceeding a threshold, so we need to check the word-counts 4785 * even if they are 64-bit. 4786 */ 4787 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) + 4788 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND); 4789 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); 4790 traffic_wds -= ppd->dd->traffic_wds; 4791 ppd->dd->traffic_wds += traffic_wds; 4792 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD) 4793 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time); 4794 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); 4795 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active & 4796 QIB_IB_QDR) && 4797 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 4798 QIBL_LINKACTIVE)) && 4799 ppd->cpspec->qdr_dfe_time && 4800 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) { 4801 ppd->cpspec->qdr_dfe_on = 0; 4802 4803 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 4804 ppd->dd->cspec->r1 ? 4805 QDR_STATIC_ADAPT_INIT_R1 : 4806 QDR_STATIC_ADAPT_INIT); 4807 force_h1(ppd); 4808 } 4809 } 4810 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); 4811 } 4812 4813 /* 4814 * If we were using MSIx, try to fallback to INTx. 4815 */ 4816 static int qib_7322_intr_fallback(struct qib_devdata *dd) 4817 { 4818 if (!dd->cspec->num_msix_entries) 4819 return 0; /* already using INTx */ 4820 4821 qib_devinfo(dd->pcidev, "MSIx interrupt not detected," 4822 " trying INTx interrupts\n"); 4823 qib_7322_nomsix(dd); 4824 qib_enable_intx(dd->pcidev); 4825 qib_setup_7322_interrupt(dd, 0); 4826 return 1; 4827 } 4828 4829 /* 4830 * Reset the XGXS (between serdes and IBC). Slightly less intrusive 4831 * than resetting the IBC or external link state, and useful in some 4832 * cases to cause some retraining. To do this right, we reset IBC 4833 * as well, then return to previous state (which may be still in reset) 4834 * NOTE: some callers of this "know" this writes the current value 4835 * of cpspec->ibcctrl_a as part of it's operation, so if that changes, 4836 * check all callers. 4837 */ 4838 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd) 4839 { 4840 u64 val; 4841 struct qib_devdata *dd = ppd->dd; 4842 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | 4843 SYM_MASK(IBPCSConfig_0, xcv_treset) | 4844 SYM_MASK(IBPCSConfig_0, tx_rx_reset); 4845 4846 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); 4847 qib_write_kreg(dd, kr_hwerrmask, 4848 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); 4849 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4850 ppd->cpspec->ibcctrl_a & 4851 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); 4852 4853 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits); 4854 qib_read_kreg32(dd, kr_scratch); 4855 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); 4856 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 4857 qib_write_kreg(dd, kr_scratch, 0ULL); 4858 qib_write_kreg(dd, kr_hwerrclear, 4859 SYM_MASK(HwErrClear, statusValidNoEopClear)); 4860 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 4861 } 4862 4863 /* 4864 * This code for non-IBTA-compliant IB speed negotiation is only known to 4865 * work for the SDR to DDR transition, and only between an HCA and a switch 4866 * with recent firmware. It is based on observed heuristics, rather than 4867 * actual knowledge of the non-compliant speed negotiation. 4868 * It has a number of hard-coded fields, since the hope is to rewrite this 4869 * when a spec is available on how the negoation is intended to work. 4870 */ 4871 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr, 4872 u32 dcnt, u32 *data) 4873 { 4874 int i; 4875 u64 pbc; 4876 u32 __iomem *piobuf; 4877 u32 pnum, control, len; 4878 struct qib_devdata *dd = ppd->dd; 4879 4880 i = 0; 4881 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */ 4882 control = qib_7322_setpbc_control(ppd, len, 0, 15); 4883 pbc = ((u64) control << 32) | len; 4884 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) { 4885 if (i++ > 15) 4886 return; 4887 udelay(2); 4888 } 4889 /* disable header check on this packet, since it can't be valid */ 4890 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); 4891 writeq(pbc, piobuf); 4892 qib_flush_wc(); 4893 qib_pio_copy(piobuf + 2, hdr, 7); 4894 qib_pio_copy(piobuf + 9, data, dcnt); 4895 if (dd->flags & QIB_USE_SPCL_TRIG) { 4896 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; 4897 4898 qib_flush_wc(); 4899 __raw_writel(0xaebecede, piobuf + spcl_off); 4900 } 4901 qib_flush_wc(); 4902 qib_sendbuf_done(dd, pnum); 4903 /* and re-enable hdr check */ 4904 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); 4905 } 4906 4907 /* 4908 * _start packet gets sent twice at start, _done gets sent twice at end 4909 */ 4910 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which) 4911 { 4912 struct qib_devdata *dd = ppd->dd; 4913 static u32 swapped; 4914 u32 dw, i, hcnt, dcnt, *data; 4915 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba }; 4916 static u32 madpayload_start[0x40] = { 4917 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 4918 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 4919 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */ 4920 }; 4921 static u32 madpayload_done[0x40] = { 4922 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 4923 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 4924 0x40000001, 0x1388, 0x15e, /* rest 0's */ 4925 }; 4926 4927 dcnt = ARRAY_SIZE(madpayload_start); 4928 hcnt = ARRAY_SIZE(hdr); 4929 if (!swapped) { 4930 /* for maintainability, do it at runtime */ 4931 for (i = 0; i < hcnt; i++) { 4932 dw = (__force u32) cpu_to_be32(hdr[i]); 4933 hdr[i] = dw; 4934 } 4935 for (i = 0; i < dcnt; i++) { 4936 dw = (__force u32) cpu_to_be32(madpayload_start[i]); 4937 madpayload_start[i] = dw; 4938 dw = (__force u32) cpu_to_be32(madpayload_done[i]); 4939 madpayload_done[i] = dw; 4940 } 4941 swapped = 1; 4942 } 4943 4944 data = which ? madpayload_done : madpayload_start; 4945 4946 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 4947 qib_read_kreg64(dd, kr_scratch); 4948 udelay(2); 4949 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 4950 qib_read_kreg64(dd, kr_scratch); 4951 udelay(2); 4952 } 4953 4954 /* 4955 * Do the absolute minimum to cause an IB speed change, and make it 4956 * ready, but don't actually trigger the change. The caller will 4957 * do that when ready (if link is in Polling training state, it will 4958 * happen immediately, otherwise when link next goes down) 4959 * 4960 * This routine should only be used as part of the DDR autonegotation 4961 * code for devices that are not compliant with IB 1.2 (or code that 4962 * fixes things up for same). 4963 * 4964 * When link has gone down, and autoneg enabled, or autoneg has 4965 * failed and we give up until next time we set both speeds, and 4966 * then we want IBTA enabled as well as "use max enabled speed. 4967 */ 4968 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed) 4969 { 4970 u64 newctrlb; 4971 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK | 4972 IBA7322_IBC_IBTA_1_2_MASK | 4973 IBA7322_IBC_MAX_SPEED_MASK); 4974 4975 if (speed & (speed - 1)) /* multiple speeds */ 4976 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) | 4977 IBA7322_IBC_IBTA_1_2_MASK | 4978 IBA7322_IBC_MAX_SPEED_MASK; 4979 else 4980 newctrlb |= speed == QIB_IB_QDR ? 4981 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK : 4982 ((speed == QIB_IB_DDR ? 4983 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR)); 4984 4985 if (newctrlb == ppd->cpspec->ibcctrl_b) 4986 return; 4987 4988 ppd->cpspec->ibcctrl_b = newctrlb; 4989 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 4990 qib_write_kreg(ppd->dd, kr_scratch, 0); 4991 } 4992 4993 /* 4994 * This routine is only used when we are not talking to another 4995 * IB 1.2-compliant device that we think can do DDR. 4996 * (This includes all existing switch chips as of Oct 2007.) 4997 * 1.2-compliant devices go directly to DDR prior to reaching INIT 4998 */ 4999 static void try_7322_autoneg(struct qib_pportdata *ppd) 5000 { 5001 unsigned long flags; 5002 5003 spin_lock_irqsave(&ppd->lflags_lock, flags); 5004 ppd->lflags |= QIBL_IB_AUTONEG_INPROG; 5005 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5006 qib_autoneg_7322_send(ppd, 0); 5007 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5008 qib_7322_mini_pcs_reset(ppd); 5009 /* 2 msec is minimum length of a poll cycle */ 5010 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work, 5011 msecs_to_jiffies(2)); 5012 } 5013 5014 /* 5015 * Handle the empirically determined mechanism for auto-negotiation 5016 * of DDR speed with switches. 5017 */ 5018 static void autoneg_7322_work(struct work_struct *work) 5019 { 5020 struct qib_pportdata *ppd; 5021 struct qib_devdata *dd; 5022 u64 startms; 5023 u32 i; 5024 unsigned long flags; 5025 5026 ppd = container_of(work, struct qib_chippport_specific, 5027 autoneg_work.work)->ppd; 5028 dd = ppd->dd; 5029 5030 startms = jiffies_to_msecs(jiffies); 5031 5032 /* 5033 * Busy wait for this first part, it should be at most a 5034 * few hundred usec, since we scheduled ourselves for 2msec. 5035 */ 5036 for (i = 0; i < 25; i++) { 5037 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState) 5038 == IB_7322_LT_STATE_POLLQUIET) { 5039 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE); 5040 break; 5041 } 5042 udelay(100); 5043 } 5044 5045 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 5046 goto done; /* we got there early or told to stop */ 5047 5048 /* we expect this to timeout */ 5049 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5050 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5051 msecs_to_jiffies(90))) 5052 goto done; 5053 qib_7322_mini_pcs_reset(ppd); 5054 5055 /* we expect this to timeout */ 5056 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5057 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5058 msecs_to_jiffies(1700))) 5059 goto done; 5060 qib_7322_mini_pcs_reset(ppd); 5061 5062 set_7322_ibspeed_fast(ppd, QIB_IB_SDR); 5063 5064 /* 5065 * Wait up to 250 msec for link to train and get to INIT at DDR; 5066 * this should terminate early. 5067 */ 5068 wait_event_timeout(ppd->cpspec->autoneg_wait, 5069 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5070 msecs_to_jiffies(250)); 5071 done: 5072 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) { 5073 spin_lock_irqsave(&ppd->lflags_lock, flags); 5074 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 5075 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) { 5076 ppd->lflags |= QIBL_IB_AUTONEG_FAILED; 5077 ppd->cpspec->autoneg_tries = 0; 5078 } 5079 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5080 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5081 } 5082 } 5083 5084 /* 5085 * This routine is used to request IPG set in the QLogic switch. 5086 * Only called if r1. 5087 */ 5088 static void try_7322_ipg(struct qib_pportdata *ppd) 5089 { 5090 struct qib_ibport *ibp = &ppd->ibport_data; 5091 struct ib_mad_send_buf *send_buf; 5092 struct ib_mad_agent *agent; 5093 struct ib_smp *smp; 5094 unsigned delay; 5095 int ret; 5096 5097 agent = ibp->send_agent; 5098 if (!agent) 5099 goto retry; 5100 5101 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR, 5102 IB_MGMT_MAD_DATA, GFP_ATOMIC); 5103 if (IS_ERR(send_buf)) 5104 goto retry; 5105 5106 if (!ibp->smi_ah) { 5107 struct ib_ah_attr attr; 5108 struct ib_ah *ah; 5109 5110 memset(&attr, 0, sizeof attr); 5111 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE); 5112 attr.port_num = ppd->port; 5113 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr); 5114 if (IS_ERR(ah)) 5115 ret = -EINVAL; 5116 else { 5117 send_buf->ah = ah; 5118 ibp->smi_ah = to_iah(ah); 5119 ret = 0; 5120 } 5121 } else { 5122 send_buf->ah = &ibp->smi_ah->ibah; 5123 ret = 0; 5124 } 5125 5126 smp = send_buf->mad; 5127 smp->base_version = IB_MGMT_BASE_VERSION; 5128 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE; 5129 smp->class_version = 1; 5130 smp->method = IB_MGMT_METHOD_SEND; 5131 smp->hop_cnt = 1; 5132 smp->attr_id = QIB_VENDOR_IPG; 5133 smp->attr_mod = 0; 5134 5135 if (!ret) 5136 ret = ib_post_send_mad(send_buf, NULL); 5137 if (ret) 5138 ib_free_send_mad(send_buf); 5139 retry: 5140 delay = 2 << ppd->cpspec->ipg_tries; 5141 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work, 5142 msecs_to_jiffies(delay)); 5143 } 5144 5145 /* 5146 * Timeout handler for setting IPG. 5147 * Only called if r1. 5148 */ 5149 static void ipg_7322_work(struct work_struct *work) 5150 { 5151 struct qib_pportdata *ppd; 5152 5153 ppd = container_of(work, struct qib_chippport_specific, 5154 ipg_work.work)->ppd; 5155 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE)) 5156 && ++ppd->cpspec->ipg_tries <= 10) 5157 try_7322_ipg(ppd); 5158 } 5159 5160 static u32 qib_7322_iblink_state(u64 ibcs) 5161 { 5162 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState); 5163 5164 switch (state) { 5165 case IB_7322_L_STATE_INIT: 5166 state = IB_PORT_INIT; 5167 break; 5168 case IB_7322_L_STATE_ARM: 5169 state = IB_PORT_ARMED; 5170 break; 5171 case IB_7322_L_STATE_ACTIVE: 5172 /* fall through */ 5173 case IB_7322_L_STATE_ACT_DEFER: 5174 state = IB_PORT_ACTIVE; 5175 break; 5176 default: /* fall through */ 5177 case IB_7322_L_STATE_DOWN: 5178 state = IB_PORT_DOWN; 5179 break; 5180 } 5181 return state; 5182 } 5183 5184 /* returns the IBTA port state, rather than the IBC link training state */ 5185 static u8 qib_7322_phys_portstate(u64 ibcs) 5186 { 5187 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState); 5188 return qib_7322_physportstate[state]; 5189 } 5190 5191 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) 5192 { 5193 int ret = 0, symadj = 0; 5194 unsigned long flags; 5195 int mult; 5196 5197 spin_lock_irqsave(&ppd->lflags_lock, flags); 5198 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; 5199 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5200 5201 /* Update our picture of width and speed from chip */ 5202 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { 5203 ppd->link_speed_active = QIB_IB_QDR; 5204 mult = 4; 5205 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { 5206 ppd->link_speed_active = QIB_IB_DDR; 5207 mult = 2; 5208 } else { 5209 ppd->link_speed_active = QIB_IB_SDR; 5210 mult = 1; 5211 } 5212 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { 5213 ppd->link_width_active = IB_WIDTH_4X; 5214 mult *= 4; 5215 } else 5216 ppd->link_width_active = IB_WIDTH_1X; 5217 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)]; 5218 5219 if (!ibup) { 5220 u64 clr; 5221 5222 /* Link went down. */ 5223 /* do IPG MAD again after linkdown, even if last time failed */ 5224 ppd->cpspec->ipg_tries = 0; 5225 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 5226 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | 5227 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); 5228 if (clr) 5229 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr); 5230 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5231 QIBL_IB_AUTONEG_INPROG))) 5232 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5233 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5234 struct qib_qsfp_data *qd = 5235 &ppd->cpspec->qsfp_data; 5236 /* unlock the Tx settings, speed may change */ 5237 qib_write_kreg_port(ppd, krp_tx_deemph_override, 5238 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 5239 reset_tx_deemphasis_override)); 5240 qib_cancel_sends(ppd); 5241 /* on link down, ensure sane pcs state */ 5242 qib_7322_mini_pcs_reset(ppd); 5243 /* schedule the qsfp refresh which should turn the link 5244 off */ 5245 if (ppd->dd->flags & QIB_HAS_QSFP) { 5246 qd->t_insert = jiffies; 5247 queue_work(ib_wq, &qd->work); 5248 } 5249 spin_lock_irqsave(&ppd->sdma_lock, flags); 5250 if (__qib_sdma_running(ppd)) 5251 __qib_sdma_process_event(ppd, 5252 qib_sdma_event_e70_go_idle); 5253 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 5254 } 5255 clr = read_7322_creg32_port(ppd, crp_iblinkdown); 5256 if (clr == ppd->cpspec->iblnkdownsnap) 5257 ppd->cpspec->iblnkdowndelta++; 5258 } else { 5259 if (qib_compat_ddr_negotiate && 5260 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5261 QIBL_IB_AUTONEG_INPROG)) && 5262 ppd->link_speed_active == QIB_IB_SDR && 5263 (ppd->link_speed_enabled & QIB_IB_DDR) 5264 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) { 5265 /* we are SDR, and auto-negotiation enabled */ 5266 ++ppd->cpspec->autoneg_tries; 5267 if (!ppd->cpspec->ibdeltainprog) { 5268 ppd->cpspec->ibdeltainprog = 1; 5269 ppd->cpspec->ibsymdelta += 5270 read_7322_creg32_port(ppd, 5271 crp_ibsymbolerr) - 5272 ppd->cpspec->ibsymsnap; 5273 ppd->cpspec->iblnkerrdelta += 5274 read_7322_creg32_port(ppd, 5275 crp_iblinkerrrecov) - 5276 ppd->cpspec->iblnkerrsnap; 5277 } 5278 try_7322_autoneg(ppd); 5279 ret = 1; /* no other IB status change processing */ 5280 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5281 ppd->link_speed_active == QIB_IB_SDR) { 5282 qib_autoneg_7322_send(ppd, 1); 5283 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5284 qib_7322_mini_pcs_reset(ppd); 5285 udelay(2); 5286 ret = 1; /* no other IB status change processing */ 5287 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5288 (ppd->link_speed_active & QIB_IB_DDR)) { 5289 spin_lock_irqsave(&ppd->lflags_lock, flags); 5290 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG | 5291 QIBL_IB_AUTONEG_FAILED); 5292 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5293 ppd->cpspec->autoneg_tries = 0; 5294 /* re-enable SDR, for next link down */ 5295 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5296 wake_up(&ppd->cpspec->autoneg_wait); 5297 symadj = 1; 5298 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) { 5299 /* 5300 * Clear autoneg failure flag, and do setup 5301 * so we'll try next time link goes down and 5302 * back to INIT (possibly connected to a 5303 * different device). 5304 */ 5305 spin_lock_irqsave(&ppd->lflags_lock, flags); 5306 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 5307 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5308 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK; 5309 symadj = 1; 5310 } 5311 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5312 symadj = 1; 5313 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) 5314 try_7322_ipg(ppd); 5315 if (!ppd->cpspec->recovery_init) 5316 setup_7322_link_recovery(ppd, 0); 5317 ppd->cpspec->qdr_dfe_time = jiffies + 5318 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY); 5319 } 5320 ppd->cpspec->ibmalfusesnap = 0; 5321 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 5322 crp_errlink); 5323 } 5324 if (symadj) { 5325 ppd->cpspec->iblnkdownsnap = 5326 read_7322_creg32_port(ppd, crp_iblinkdown); 5327 if (ppd->cpspec->ibdeltainprog) { 5328 ppd->cpspec->ibdeltainprog = 0; 5329 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd, 5330 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap; 5331 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd, 5332 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap; 5333 } 5334 } else if (!ibup && qib_compat_ddr_negotiate && 5335 !ppd->cpspec->ibdeltainprog && 5336 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5337 ppd->cpspec->ibdeltainprog = 1; 5338 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 5339 crp_ibsymbolerr); 5340 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 5341 crp_iblinkerrrecov); 5342 } 5343 5344 if (!ret) 5345 qib_setup_7322_setextled(ppd, ibup); 5346 return ret; 5347 } 5348 5349 /* 5350 * Does read/modify/write to appropriate registers to 5351 * set output and direction bits selected by mask. 5352 * these are in their canonical postions (e.g. lsb of 5353 * dir will end up in D48 of extctrl on existing chips). 5354 * returns contents of GP Inputs. 5355 */ 5356 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) 5357 { 5358 u64 read_val, new_out; 5359 unsigned long flags; 5360 5361 if (mask) { 5362 /* some bits being written, lock access to GPIO */ 5363 dir &= mask; 5364 out &= mask; 5365 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 5366 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); 5367 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); 5368 new_out = (dd->cspec->gpio_out & ~mask) | out; 5369 5370 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 5371 qib_write_kreg(dd, kr_gpio_out, new_out); 5372 dd->cspec->gpio_out = new_out; 5373 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 5374 } 5375 /* 5376 * It is unlikely that a read at this time would get valid 5377 * data on a pin whose direction line was set in the same 5378 * call to this function. We include the read here because 5379 * that allows us to potentially combine a change on one pin with 5380 * a read on another, and because the old code did something like 5381 * this. 5382 */ 5383 read_val = qib_read_kreg64(dd, kr_extstatus); 5384 return SYM_FIELD(read_val, EXTStatus, GPIOIn); 5385 } 5386 5387 /* Enable writes to config EEPROM, if possible. Returns previous state */ 5388 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) 5389 { 5390 int prev_wen; 5391 u32 mask; 5392 5393 mask = 1 << QIB_EEPROM_WEN_NUM; 5394 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; 5395 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); 5396 5397 return prev_wen & 1; 5398 } 5399 5400 /* 5401 * Read fundamental info we need to use the chip. These are 5402 * the registers that describe chip capabilities, and are 5403 * saved in shadow registers. 5404 */ 5405 static void get_7322_chip_params(struct qib_devdata *dd) 5406 { 5407 u64 val; 5408 u32 piobufs; 5409 int mtu; 5410 5411 dd->palign = qib_read_kreg32(dd, kr_pagealign); 5412 5413 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); 5414 5415 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); 5416 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); 5417 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); 5418 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); 5419 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; 5420 5421 val = qib_read_kreg64(dd, kr_sendpiobufcnt); 5422 dd->piobcnt2k = val & ~0U; 5423 dd->piobcnt4k = val >> 32; 5424 val = qib_read_kreg64(dd, kr_sendpiosize); 5425 dd->piosize2k = val & ~0U; 5426 dd->piosize4k = val >> 32; 5427 5428 mtu = ib_mtu_enum_to_int(qib_ibmtu); 5429 if (mtu == -1) 5430 mtu = QIB_DEFAULT_MTU; 5431 dd->pport[0].ibmtu = (u32)mtu; 5432 dd->pport[1].ibmtu = (u32)mtu; 5433 5434 /* these may be adjusted in init_chip_wc_pat() */ 5435 dd->pio2kbase = (u32 __iomem *) 5436 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); 5437 dd->pio4kbase = (u32 __iomem *) 5438 ((char __iomem *) dd->kregbase + 5439 (dd->piobufbase >> 32)); 5440 /* 5441 * 4K buffers take 2 pages; we use roundup just to be 5442 * paranoid; we calculate it once here, rather than on 5443 * ever buf allocate 5444 */ 5445 dd->align4k = ALIGN(dd->piosize4k, dd->palign); 5446 5447 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; 5448 5449 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / 5450 (sizeof(u64) * BITS_PER_BYTE / 2); 5451 } 5452 5453 /* 5454 * The chip base addresses in cspec and cpspec have to be set 5455 * after possible init_chip_wc_pat(), rather than in 5456 * get_7322_chip_params(), so split out as separate function 5457 */ 5458 static void qib_7322_set_baseaddrs(struct qib_devdata *dd) 5459 { 5460 u32 cregbase; 5461 cregbase = qib_read_kreg32(dd, kr_counterregbase); 5462 5463 dd->cspec->cregbase = (u64 __iomem *)(cregbase + 5464 (char __iomem *)dd->kregbase); 5465 5466 dd->egrtidbase = (u64 __iomem *) 5467 ((char __iomem *) dd->kregbase + dd->rcvegrbase); 5468 5469 /* port registers are defined as relative to base of chip */ 5470 dd->pport[0].cpspec->kpregbase = 5471 (u64 __iomem *)((char __iomem *)dd->kregbase); 5472 dd->pport[1].cpspec->kpregbase = 5473 (u64 __iomem *)(dd->palign + 5474 (char __iomem *)dd->kregbase); 5475 dd->pport[0].cpspec->cpregbase = 5476 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], 5477 kr_counterregbase) + (char __iomem *)dd->kregbase); 5478 dd->pport[1].cpspec->cpregbase = 5479 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], 5480 kr_counterregbase) + (char __iomem *)dd->kregbase); 5481 } 5482 5483 /* 5484 * This is a fairly special-purpose observer, so we only support 5485 * the port-specific parts of SendCtrl 5486 */ 5487 5488 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \ 5489 SYM_MASK(SendCtrl_0, SDmaEnable) | \ 5490 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \ 5491 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \ 5492 SYM_MASK(SendCtrl_0, SDmaHalt) | \ 5493 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \ 5494 SYM_MASK(SendCtrl_0, ForceCreditUpToDate)) 5495 5496 static int sendctrl_hook(struct qib_devdata *dd, 5497 const struct diag_observer *op, u32 offs, 5498 u64 *data, u64 mask, int only_32) 5499 { 5500 unsigned long flags; 5501 unsigned idx; 5502 unsigned pidx; 5503 struct qib_pportdata *ppd = NULL; 5504 u64 local_data, all_bits; 5505 5506 /* 5507 * The fixed correspondence between Physical ports and pports is 5508 * severed. We need to hunt for the ppd that corresponds 5509 * to the offset we got. And we have to do that without admitting 5510 * we know the stride, apparently. 5511 */ 5512 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5513 u64 __iomem *psptr; 5514 u32 psoffs; 5515 5516 ppd = dd->pport + pidx; 5517 if (!ppd->cpspec->kpregbase) 5518 continue; 5519 5520 psptr = ppd->cpspec->kpregbase + krp_sendctrl; 5521 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); 5522 if (psoffs == offs) 5523 break; 5524 } 5525 5526 /* If pport is not being managed by driver, just avoid shadows. */ 5527 if (pidx >= dd->num_pports) 5528 ppd = NULL; 5529 5530 /* In any case, "idx" is flat index in kreg space */ 5531 idx = offs / sizeof(u64); 5532 5533 all_bits = ~0ULL; 5534 if (only_32) 5535 all_bits >>= 32; 5536 5537 spin_lock_irqsave(&dd->sendctrl_lock, flags); 5538 if (!ppd || (mask & all_bits) != all_bits) { 5539 /* 5540 * At least some mask bits are zero, so we need 5541 * to read. The judgement call is whether from 5542 * reg or shadow. First-cut: read reg, and complain 5543 * if any bits which should be shadowed are different 5544 * from their shadowed value. 5545 */ 5546 if (only_32) 5547 local_data = (u64)qib_read_kreg32(dd, idx); 5548 else 5549 local_data = qib_read_kreg64(dd, idx); 5550 *data = (local_data & ~mask) | (*data & mask); 5551 } 5552 if (mask) { 5553 /* 5554 * At least some mask bits are one, so we need 5555 * to write, but only shadow some bits. 5556 */ 5557 u64 sval, tval; /* Shadowed, transient */ 5558 5559 /* 5560 * New shadow val is bits we don't want to touch, 5561 * ORed with bits we do, that are intended for shadow. 5562 */ 5563 if (ppd) { 5564 sval = ppd->p_sendctrl & ~mask; 5565 sval |= *data & SENDCTRL_SHADOWED & mask; 5566 ppd->p_sendctrl = sval; 5567 } else 5568 sval = *data & SENDCTRL_SHADOWED & mask; 5569 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); 5570 qib_write_kreg(dd, idx, tval); 5571 qib_write_kreg(dd, kr_scratch, 0Ull); 5572 } 5573 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 5574 return only_32 ? 4 : 8; 5575 } 5576 5577 static const struct diag_observer sendctrl_0_observer = { 5578 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64), 5579 KREG_IDX(SendCtrl_0) * sizeof(u64) 5580 }; 5581 5582 static const struct diag_observer sendctrl_1_observer = { 5583 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64), 5584 KREG_IDX(SendCtrl_1) * sizeof(u64) 5585 }; 5586 5587 static ushort sdma_fetch_prio = 8; 5588 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO); 5589 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority"); 5590 5591 /* Besides logging QSFP events, we set appropriate TxDDS values */ 5592 static void init_txdds_table(struct qib_pportdata *ppd, int override); 5593 5594 static void qsfp_7322_event(struct work_struct *work) 5595 { 5596 struct qib_qsfp_data *qd; 5597 struct qib_pportdata *ppd; 5598 unsigned long pwrup; 5599 unsigned long flags; 5600 int ret; 5601 u32 le2; 5602 5603 qd = container_of(work, struct qib_qsfp_data, work); 5604 ppd = qd->ppd; 5605 pwrup = qd->t_insert + 5606 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC); 5607 5608 /* Delay for 20 msecs to allow ModPrs resistor to setup */ 5609 mdelay(QSFP_MODPRS_LAG_MSEC); 5610 5611 if (!qib_qsfp_mod_present(ppd)) { 5612 ppd->cpspec->qsfp_data.modpresent = 0; 5613 /* Set the physical link to disabled */ 5614 qib_set_ib_7322_lstate(ppd, 0, 5615 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 5616 spin_lock_irqsave(&ppd->lflags_lock, flags); 5617 ppd->lflags &= ~QIBL_LINKV; 5618 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5619 } else { 5620 /* 5621 * Some QSFP's not only do not respond until the full power-up 5622 * time, but may behave badly if we try. So hold off responding 5623 * to insertion. 5624 */ 5625 while (1) { 5626 if (time_is_before_jiffies(pwrup)) 5627 break; 5628 msleep(20); 5629 } 5630 5631 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 5632 5633 /* 5634 * Need to change LE2 back to defaults if we couldn't 5635 * read the cable type (to handle cable swaps), so do this 5636 * even on failure to read cable information. We don't 5637 * get here for QME, so IS_QME check not needed here. 5638 */ 5639 if (!ret && !ppd->dd->cspec->r1) { 5640 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) 5641 le2 = LE2_QME; 5642 else if (qd->cache.atten[1] >= qib_long_atten && 5643 QSFP_IS_CU(qd->cache.tech)) 5644 le2 = LE2_5m; 5645 else 5646 le2 = LE2_DEFAULT; 5647 } else 5648 le2 = LE2_DEFAULT; 5649 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7)); 5650 /* 5651 * We always change parameteters, since we can choose 5652 * values for cables without eeproms, and the cable may have 5653 * changed from a cable with full or partial eeprom content 5654 * to one with partial or no content. 5655 */ 5656 init_txdds_table(ppd, 0); 5657 /* The physical link is being re-enabled only when the 5658 * previous state was DISABLED and the VALID bit is not 5659 * set. This should only happen when the cable has been 5660 * physically pulled. */ 5661 if (!ppd->cpspec->qsfp_data.modpresent && 5662 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) { 5663 ppd->cpspec->qsfp_data.modpresent = 1; 5664 qib_set_ib_7322_lstate(ppd, 0, 5665 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 5666 spin_lock_irqsave(&ppd->lflags_lock, flags); 5667 ppd->lflags |= QIBL_LINKV; 5668 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5669 } 5670 } 5671 } 5672 5673 /* 5674 * There is little we can do but complain to the user if QSFP 5675 * initialization fails. 5676 */ 5677 static void qib_init_7322_qsfp(struct qib_pportdata *ppd) 5678 { 5679 unsigned long flags; 5680 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data; 5681 struct qib_devdata *dd = ppd->dd; 5682 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N; 5683 5684 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 5685 qd->ppd = ppd; 5686 qib_qsfp_init(qd, qsfp_7322_event); 5687 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 5688 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); 5689 dd->cspec->gpio_mask |= mod_prs_bit; 5690 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 5691 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 5692 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 5693 } 5694 5695 /* 5696 * called at device initialization time, and also if the txselect 5697 * module parameter is changed. This is used for cables that don't 5698 * have valid QSFP EEPROMs (not present, or attenuation is zero). 5699 * We initialize to the default, then if there is a specific 5700 * unit,port match, we use that (and set it immediately, for the 5701 * current speed, if the link is at INIT or better). 5702 * String format is "default# unit#,port#=# ... u,p=#", separators must 5703 * be a SPACE character. A newline terminates. The u,p=# tuples may 5704 * optionally have "u,p=#,#", where the final # is the H1 value 5705 * The last specific match is used (actually, all are used, but last 5706 * one is the one that winds up set); if none at all, fall back on default. 5707 */ 5708 static void set_no_qsfp_atten(struct qib_devdata *dd, int change) 5709 { 5710 char *nxt, *str; 5711 u32 pidx, unit, port, deflt, h1; 5712 unsigned long val; 5713 int any = 0, seth1; 5714 int txdds_size; 5715 5716 str = txselect_list; 5717 5718 /* default number is validated in setup_txselect() */ 5719 deflt = simple_strtoul(str, &nxt, 0); 5720 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5721 dd->pport[pidx].cpspec->no_eep = deflt; 5722 5723 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ; 5724 if (IS_QME(dd) || IS_QMH(dd)) 5725 txdds_size += TXDDS_MFG_SZ; 5726 5727 while (*nxt && nxt[1]) { 5728 str = ++nxt; 5729 unit = simple_strtoul(str, &nxt, 0); 5730 if (nxt == str || !*nxt || *nxt != ',') { 5731 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5732 ; 5733 continue; 5734 } 5735 str = ++nxt; 5736 port = simple_strtoul(str, &nxt, 0); 5737 if (nxt == str || *nxt != '=') { 5738 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5739 ; 5740 continue; 5741 } 5742 str = ++nxt; 5743 val = simple_strtoul(str, &nxt, 0); 5744 if (nxt == str) { 5745 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5746 ; 5747 continue; 5748 } 5749 if (val >= txdds_size) 5750 continue; 5751 seth1 = 0; 5752 h1 = 0; /* gcc thinks it might be used uninitted */ 5753 if (*nxt == ',' && nxt[1]) { 5754 str = ++nxt; 5755 h1 = (u32)simple_strtoul(str, &nxt, 0); 5756 if (nxt == str) 5757 while (*nxt && *nxt++ != ' ') /* skip */ 5758 ; 5759 else 5760 seth1 = 1; 5761 } 5762 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; 5763 ++pidx) { 5764 struct qib_pportdata *ppd = &dd->pport[pidx]; 5765 5766 if (ppd->port != port || !ppd->link_speed_supported) 5767 continue; 5768 ppd->cpspec->no_eep = val; 5769 if (seth1) 5770 ppd->cpspec->h1_val = h1; 5771 /* now change the IBC and serdes, overriding generic */ 5772 init_txdds_table(ppd, 1); 5773 /* Re-enable the physical state machine on mezz boards 5774 * now that the correct settings have been set. 5775 * QSFP boards are handles by the QSFP event handler */ 5776 if (IS_QMH(dd) || IS_QME(dd)) 5777 qib_set_ib_7322_lstate(ppd, 0, 5778 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 5779 any++; 5780 } 5781 if (*nxt == '\n') 5782 break; /* done */ 5783 } 5784 if (change && !any) { 5785 /* no specific setting, use the default. 5786 * Change the IBC and serdes, but since it's 5787 * general, don't override specific settings. 5788 */ 5789 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5790 if (dd->pport[pidx].link_speed_supported) 5791 init_txdds_table(&dd->pport[pidx], 0); 5792 } 5793 } 5794 5795 /* handle the txselect parameter changing */ 5796 static int setup_txselect(const char *str, struct kernel_param *kp) 5797 { 5798 struct qib_devdata *dd; 5799 unsigned long val; 5800 char *n; 5801 if (strlen(str) >= MAX_ATTEN_LEN) { 5802 printk(KERN_INFO QIB_DRV_NAME " txselect_values string " 5803 "too long\n"); 5804 return -ENOSPC; 5805 } 5806 val = simple_strtoul(str, &n, 0); 5807 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 5808 TXDDS_MFG_SZ)) { 5809 printk(KERN_INFO QIB_DRV_NAME 5810 "txselect_values must start with a number < %d\n", 5811 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); 5812 return -EINVAL; 5813 } 5814 strcpy(txselect_list, str); 5815 5816 list_for_each_entry(dd, &qib_dev_list, list) 5817 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) 5818 set_no_qsfp_atten(dd, 1); 5819 return 0; 5820 } 5821 5822 /* 5823 * Write the final few registers that depend on some of the 5824 * init setup. Done late in init, just before bringing up 5825 * the serdes. 5826 */ 5827 static int qib_late_7322_initreg(struct qib_devdata *dd) 5828 { 5829 int ret = 0, n; 5830 u64 val; 5831 5832 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); 5833 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); 5834 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); 5835 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); 5836 val = qib_read_kreg64(dd, kr_sendpioavailaddr); 5837 if (val != dd->pioavailregs_phys) { 5838 qib_dev_err(dd, "Catastrophic software error, " 5839 "SendPIOAvailAddr written as %lx, " 5840 "read back as %llx\n", 5841 (unsigned long) dd->pioavailregs_phys, 5842 (unsigned long long) val); 5843 ret = -EINVAL; 5844 } 5845 5846 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 5847 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); 5848 /* driver sends get pkey, lid, etc. checking also, to catch bugs */ 5849 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); 5850 5851 qib_register_observer(dd, &sendctrl_0_observer); 5852 qib_register_observer(dd, &sendctrl_1_observer); 5853 5854 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; 5855 qib_write_kreg(dd, kr_control, dd->control); 5856 /* 5857 * Set SendDmaFetchPriority and init Tx params, including 5858 * QSFP handler on boards that have QSFP. 5859 * First set our default attenuation entry for cables that 5860 * don't have valid attenuation. 5861 */ 5862 set_no_qsfp_atten(dd, 0); 5863 for (n = 0; n < dd->num_pports; ++n) { 5864 struct qib_pportdata *ppd = dd->pport + n; 5865 5866 qib_write_kreg_port(ppd, krp_senddmaprioritythld, 5867 sdma_fetch_prio & 0xf); 5868 /* Initialize qsfp if present on board. */ 5869 if (dd->flags & QIB_HAS_QSFP) 5870 qib_init_7322_qsfp(ppd); 5871 } 5872 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; 5873 qib_write_kreg(dd, kr_control, dd->control); 5874 5875 return ret; 5876 } 5877 5878 /* per IB port errors. */ 5879 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \ 5880 MASK_ACROSS(8, 15)) 5881 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41)) 5882 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \ 5883 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \ 5884 MASK_ACROSS(0, 11)) 5885 5886 /* 5887 * Write the initialization per-port registers that need to be done at 5888 * driver load and after reset completes (i.e., that aren't done as part 5889 * of other init procedures called from qib_init.c). 5890 * Some of these should be redundant on reset, but play safe. 5891 */ 5892 static void write_7322_init_portregs(struct qib_pportdata *ppd) 5893 { 5894 u64 val; 5895 int i; 5896 5897 if (!ppd->link_speed_supported) { 5898 /* no buffer credits for this port */ 5899 for (i = 1; i < 8; i++) 5900 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 5901 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0); 5902 qib_write_kreg(ppd->dd, kr_scratch, 0); 5903 return; 5904 } 5905 5906 /* 5907 * Set the number of supported virtual lanes in IBC, 5908 * for flow control packet handling on unsupported VLs 5909 */ 5910 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 5911 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); 5912 val |= (u64)(ppd->vls_supported - 1) << 5913 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); 5914 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 5915 5916 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP); 5917 5918 /* enable tx header checking */ 5919 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY | 5920 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID | 5921 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ); 5922 5923 qib_write_kreg_port(ppd, krp_ncmodectrl, 5924 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); 5925 5926 /* 5927 * Unconditionally clear the bufmask bits. If SDMA is 5928 * enabled, we'll set them appropriately later. 5929 */ 5930 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0); 5931 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0); 5932 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0); 5933 if (ppd->dd->cspec->r1) 5934 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); 5935 } 5936 5937 /* 5938 * Write the initialization per-device registers that need to be done at 5939 * driver load and after reset completes (i.e., that aren't done as part 5940 * of other init procedures called from qib_init.c). Also write per-port 5941 * registers that are affected by overall device config, such as QP mapping 5942 * Some of these should be redundant on reset, but play safe. 5943 */ 5944 static void write_7322_initregs(struct qib_devdata *dd) 5945 { 5946 struct qib_pportdata *ppd; 5947 int i, pidx; 5948 u64 val; 5949 5950 /* Set Multicast QPs received by port 2 to map to context one. */ 5951 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); 5952 5953 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5954 unsigned n, regno; 5955 unsigned long flags; 5956 5957 if (dd->n_krcv_queues < 2 || 5958 !dd->pport[pidx].link_speed_supported) 5959 continue; 5960 5961 ppd = &dd->pport[pidx]; 5962 5963 /* be paranoid against later code motion, etc. */ 5964 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 5965 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); 5966 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 5967 5968 /* Initialize QP to context mapping */ 5969 regno = krp_rcvqpmaptable; 5970 val = 0; 5971 if (dd->num_pports > 1) 5972 n = dd->first_user_ctxt / dd->num_pports; 5973 else 5974 n = dd->first_user_ctxt - 1; 5975 for (i = 0; i < 32; ) { 5976 unsigned ctxt; 5977 5978 if (dd->num_pports > 1) 5979 ctxt = (i % n) * dd->num_pports + pidx; 5980 else if (i % n) 5981 ctxt = (i % n) + 1; 5982 else 5983 ctxt = ppd->hw_pidx; 5984 val |= ctxt << (5 * (i % 6)); 5985 i++; 5986 if (i % 6 == 0) { 5987 qib_write_kreg_port(ppd, regno, val); 5988 val = 0; 5989 regno++; 5990 } 5991 } 5992 qib_write_kreg_port(ppd, regno, val); 5993 } 5994 5995 /* 5996 * Setup up interrupt mitigation for kernel contexts, but 5997 * not user contexts (user contexts use interrupts when 5998 * stalled waiting for any packet, so want those interrupts 5999 * right away). 6000 */ 6001 for (i = 0; i < dd->first_user_ctxt; i++) { 6002 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; 6003 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); 6004 } 6005 6006 /* 6007 * Initialize as (disabled) rcvflow tables. Application code 6008 * will setup each flow as it uses the flow. 6009 * Doesn't clear any of the error bits that might be set. 6010 */ 6011 val = TIDFLOW_ERRBITS; /* these are W1C */ 6012 for (i = 0; i < dd->cfgctxts; i++) { 6013 int flow; 6014 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++) 6015 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); 6016 } 6017 6018 /* 6019 * dual cards init to dual port recovery, single port cards to 6020 * the one port. Dual port cards may later adjust to 1 port, 6021 * and then back to dual port if both ports are connected 6022 * */ 6023 if (dd->num_pports) 6024 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); 6025 } 6026 6027 static int qib_init_7322_variables(struct qib_devdata *dd) 6028 { 6029 struct qib_pportdata *ppd; 6030 unsigned features, pidx, sbufcnt; 6031 int ret, mtu; 6032 u32 sbufs, updthresh; 6033 6034 /* pport structs are contiguous, allocated after devdata */ 6035 ppd = (struct qib_pportdata *)(dd + 1); 6036 dd->pport = ppd; 6037 ppd[0].dd = dd; 6038 ppd[1].dd = dd; 6039 6040 dd->cspec = (struct qib_chip_specific *)(ppd + 2); 6041 6042 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); 6043 ppd[1].cpspec = &ppd[0].cpspec[1]; 6044 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */ 6045 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */ 6046 6047 spin_lock_init(&dd->cspec->rcvmod_lock); 6048 spin_lock_init(&dd->cspec->gpio_lock); 6049 6050 /* we haven't yet set QIB_PRESENT, so use read directly */ 6051 dd->revision = readq(&dd->kregbase[kr_revision]); 6052 6053 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { 6054 qib_dev_err(dd, "Revision register read failure, " 6055 "giving up initialization\n"); 6056 ret = -ENODEV; 6057 goto bail; 6058 } 6059 dd->flags |= QIB_PRESENT; /* now register routines work */ 6060 6061 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); 6062 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); 6063 dd->cspec->r1 = dd->minrev == 1; 6064 6065 get_7322_chip_params(dd); 6066 features = qib_7322_boardname(dd); 6067 6068 /* now that piobcnt2k and 4k set, we can allocate these */ 6069 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + 6070 NUM_VL15_BUFS + BITS_PER_LONG - 1; 6071 sbufcnt /= BITS_PER_LONG; 6072 dd->cspec->sendchkenable = kmalloc(sbufcnt * 6073 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL); 6074 dd->cspec->sendgrhchk = kmalloc(sbufcnt * 6075 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL); 6076 dd->cspec->sendibchk = kmalloc(sbufcnt * 6077 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); 6078 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || 6079 !dd->cspec->sendibchk) { 6080 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n"); 6081 ret = -ENOMEM; 6082 goto bail; 6083 } 6084 6085 ppd = dd->pport; 6086 6087 /* 6088 * GPIO bits for TWSI data and clock, 6089 * used for serial EEPROM. 6090 */ 6091 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; 6092 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; 6093 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; 6094 6095 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | 6096 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP | 6097 QIB_HAS_THRESH_UPDATE | 6098 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0); 6099 dd->flags |= qib_special_trigger ? 6100 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA; 6101 6102 /* 6103 * Setup initial values. These may change when PAT is enabled, but 6104 * we need these to do initial chip register accesses. 6105 */ 6106 qib_7322_set_baseaddrs(dd); 6107 6108 mtu = ib_mtu_enum_to_int(qib_ibmtu); 6109 if (mtu == -1) 6110 mtu = QIB_DEFAULT_MTU; 6111 6112 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; 6113 /* all hwerrors become interrupts, unless special purposed */ 6114 dd->cspec->hwerrmask = ~0ULL; 6115 /* link_recovery setup causes these errors, so ignore them, 6116 * other than clearing them when they occur */ 6117 dd->cspec->hwerrmask &= 6118 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | 6119 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | 6120 HWE_MASK(LATriggered)); 6121 6122 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) { 6123 struct qib_chippport_specific *cp = ppd->cpspec; 6124 ppd->link_speed_supported = features & PORT_SPD_CAP; 6125 features >>= PORT_SPD_CAP_SHIFT; 6126 if (!ppd->link_speed_supported) { 6127 /* single port mode (7340, or configured) */ 6128 dd->skip_kctxt_mask |= 1 << pidx; 6129 if (pidx == 0) { 6130 /* Make sure port is disabled. */ 6131 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6132 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6133 ppd[0] = ppd[1]; 6134 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6135 IBSerdesPClkNotDetectMask_0) 6136 | SYM_MASK(HwErrMask, 6137 SDmaMemReadErrMask_0)); 6138 dd->cspec->int_enable_mask &= ~( 6139 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | 6140 SYM_MASK(IntMask, SDmaIdleIntMask_0) | 6141 SYM_MASK(IntMask, SDmaProgressIntMask_0) | 6142 SYM_MASK(IntMask, SDmaIntMask_0) | 6143 SYM_MASK(IntMask, ErrIntMask_0) | 6144 SYM_MASK(IntMask, SendDoneIntMask_0)); 6145 } else { 6146 /* Make sure port is disabled. */ 6147 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6148 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6149 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6150 IBSerdesPClkNotDetectMask_1) 6151 | SYM_MASK(HwErrMask, 6152 SDmaMemReadErrMask_1)); 6153 dd->cspec->int_enable_mask &= ~( 6154 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | 6155 SYM_MASK(IntMask, SDmaIdleIntMask_1) | 6156 SYM_MASK(IntMask, SDmaProgressIntMask_1) | 6157 SYM_MASK(IntMask, SDmaIntMask_1) | 6158 SYM_MASK(IntMask, ErrIntMask_1) | 6159 SYM_MASK(IntMask, SendDoneIntMask_1)); 6160 } 6161 continue; 6162 } 6163 6164 dd->num_pports++; 6165 qib_init_pportdata(ppd, dd, pidx, dd->num_pports); 6166 6167 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; 6168 ppd->link_width_enabled = IB_WIDTH_4X; 6169 ppd->link_speed_enabled = ppd->link_speed_supported; 6170 /* 6171 * Set the initial values to reasonable default, will be set 6172 * for real when link is up. 6173 */ 6174 ppd->link_width_active = IB_WIDTH_4X; 6175 ppd->link_speed_active = QIB_IB_SDR; 6176 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS]; 6177 switch (qib_num_cfg_vls) { 6178 case 1: 6179 ppd->vls_supported = IB_VL_VL0; 6180 break; 6181 case 2: 6182 ppd->vls_supported = IB_VL_VL0_1; 6183 break; 6184 default: 6185 qib_devinfo(dd->pcidev, 6186 "Invalid num_vls %u, using 4 VLs\n", 6187 qib_num_cfg_vls); 6188 qib_num_cfg_vls = 4; 6189 /* fall through */ 6190 case 4: 6191 ppd->vls_supported = IB_VL_VL0_3; 6192 break; 6193 case 8: 6194 if (mtu <= 2048) 6195 ppd->vls_supported = IB_VL_VL0_7; 6196 else { 6197 qib_devinfo(dd->pcidev, 6198 "Invalid num_vls %u for MTU %d " 6199 ", using 4 VLs\n", 6200 qib_num_cfg_vls, mtu); 6201 ppd->vls_supported = IB_VL_VL0_3; 6202 qib_num_cfg_vls = 4; 6203 } 6204 break; 6205 } 6206 ppd->vls_operational = ppd->vls_supported; 6207 6208 init_waitqueue_head(&cp->autoneg_wait); 6209 INIT_DELAYED_WORK(&cp->autoneg_work, 6210 autoneg_7322_work); 6211 if (ppd->dd->cspec->r1) 6212 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work); 6213 6214 /* 6215 * For Mez and similar cards, no qsfp info, so do 6216 * the "cable info" setup here. Can be overridden 6217 * in adapter-specific routines. 6218 */ 6219 if (!(dd->flags & QIB_HAS_QSFP)) { 6220 if (!IS_QMH(dd) && !IS_QME(dd)) 6221 qib_devinfo(dd->pcidev, "IB%u:%u: " 6222 "Unknown mezzanine card type\n", 6223 dd->unit, ppd->port); 6224 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; 6225 /* 6226 * Choose center value as default tx serdes setting 6227 * until changed through module parameter. 6228 */ 6229 ppd->cpspec->no_eep = IS_QMH(dd) ? 6230 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4; 6231 } else 6232 cp->h1_val = H1_FORCE_VAL; 6233 6234 /* Avoid writes to chip for mini_init */ 6235 if (!qib_mini_init) 6236 write_7322_init_portregs(ppd); 6237 6238 init_timer(&cp->chase_timer); 6239 cp->chase_timer.function = reenable_chase; 6240 cp->chase_timer.data = (unsigned long)ppd; 6241 6242 ppd++; 6243 } 6244 6245 dd->rcvhdrentsize = qib_rcvhdrentsize ? 6246 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE; 6247 dd->rcvhdrsize = qib_rcvhdrsize ? 6248 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE; 6249 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); 6250 6251 /* we always allocate at least 2048 bytes for eager buffers */ 6252 dd->rcvegrbufsize = max(mtu, 2048); 6253 BUG_ON(!is_power_of_2(dd->rcvegrbufsize)); 6254 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); 6255 6256 qib_7322_tidtemplate(dd); 6257 6258 /* 6259 * We can request a receive interrupt for 1 or 6260 * more packets from current offset. 6261 */ 6262 dd->rhdrhead_intr_off = 6263 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT; 6264 6265 /* setup the stats timer; the add_timer is done at end of init */ 6266 init_timer(&dd->stats_timer); 6267 dd->stats_timer.function = qib_get_7322_faststats; 6268 dd->stats_timer.data = (unsigned long) dd; 6269 6270 dd->ureg_align = 0x10000; /* 64KB alignment */ 6271 6272 dd->piosize2kmax_dwords = dd->piosize2k >> 2; 6273 6274 qib_7322_config_ctxts(dd); 6275 qib_set_ctxtcnt(dd); 6276 6277 if (qib_wc_pat) { 6278 resource_size_t vl15off; 6279 /* 6280 * We do not set WC on the VL15 buffers to avoid 6281 * a rare problem with unaligned writes from 6282 * interrupt-flushed store buffers, so we need 6283 * to map those separately here. We can't solve 6284 * this for the rarely used mtrr case. 6285 */ 6286 ret = init_chip_wc_pat(dd, 0); 6287 if (ret) 6288 goto bail; 6289 6290 /* vl15 buffers start just after the 4k buffers */ 6291 vl15off = dd->physaddr + (dd->piobufbase >> 32) + 6292 dd->piobcnt4k * dd->align4k; 6293 dd->piovl15base = ioremap_nocache(vl15off, 6294 NUM_VL15_BUFS * dd->align4k); 6295 if (!dd->piovl15base) 6296 goto bail; 6297 } 6298 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ 6299 6300 ret = 0; 6301 if (qib_mini_init) 6302 goto bail; 6303 if (!dd->num_pports) { 6304 qib_dev_err(dd, "No ports enabled, giving up initialization\n"); 6305 goto bail; /* no error, so can still figure out why err */ 6306 } 6307 6308 write_7322_initregs(dd); 6309 ret = qib_create_ctxts(dd); 6310 init_7322_cntrnames(dd); 6311 6312 updthresh = 8U; /* update threshold */ 6313 6314 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA. 6315 * reserve the update threshold amount for other kernel use, such 6316 * as sending SMI, MAD, and ACKs, or 3, whichever is greater, 6317 * unless we aren't enabling SDMA, in which case we want to use 6318 * all the 4k bufs for the kernel. 6319 * if this was less than the update threshold, we could wait 6320 * a long time for an update. Coded this way because we 6321 * sometimes change the update threshold for various reasons, 6322 * and we want this to remain robust. 6323 */ 6324 if (dd->flags & QIB_HAS_SEND_DMA) { 6325 dd->cspec->sdmabufcnt = dd->piobcnt4k; 6326 sbufs = updthresh > 3 ? updthresh : 3; 6327 } else { 6328 dd->cspec->sdmabufcnt = 0; 6329 sbufs = dd->piobcnt4k; 6330 } 6331 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - 6332 dd->cspec->sdmabufcnt; 6333 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; 6334 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ 6335 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? 6336 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; 6337 6338 /* 6339 * If we have 16 user contexts, we will have 7 sbufs 6340 * per context, so reduce the update threshold to match. We 6341 * want to update before we actually run out, at low pbufs/ctxt 6342 * so give ourselves some margin. 6343 */ 6344 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) 6345 updthresh = dd->pbufsctxt - 2; 6346 dd->cspec->updthresh_dflt = updthresh; 6347 dd->cspec->updthresh = updthresh; 6348 6349 /* before full enable, no interrupts, no locking needed */ 6350 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) 6351 << SYM_LSB(SendCtrl, AvailUpdThld)) | 6352 SYM_MASK(SendCtrl, SendBufAvailPad64Byte); 6353 6354 dd->psxmitwait_supported = 1; 6355 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; 6356 bail: 6357 if (!dd->ctxtcnt) 6358 dd->ctxtcnt = 1; /* for other initialization code */ 6359 6360 return ret; 6361 } 6362 6363 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc, 6364 u32 *pbufnum) 6365 { 6366 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK; 6367 struct qib_devdata *dd = ppd->dd; 6368 6369 /* last is same for 2k and 4k, because we use 4k if all 2k busy */ 6370 if (pbc & PBC_7322_VL15_SEND) { 6371 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; 6372 last = first; 6373 } else { 6374 if ((plen + 1) > dd->piosize2kmax_dwords) 6375 first = dd->piobcnt2k; 6376 else 6377 first = 0; 6378 last = dd->cspec->lastbuf_for_pio; 6379 } 6380 return qib_getsendbuf_range(dd, pbufnum, first, last); 6381 } 6382 6383 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv, 6384 u32 start) 6385 { 6386 qib_write_kreg_port(ppd, krp_psinterval, intv); 6387 qib_write_kreg_port(ppd, krp_psstart, start); 6388 } 6389 6390 /* 6391 * Must be called with sdma_lock held, or before init finished. 6392 */ 6393 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) 6394 { 6395 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt); 6396 } 6397 6398 static struct sdma_set_state_action sdma_7322_action_table[] = { 6399 [qib_sdma_state_s00_hw_down] = { 6400 .go_s99_running_tofalse = 1, 6401 .op_enable = 0, 6402 .op_intenable = 0, 6403 .op_halt = 0, 6404 .op_drain = 0, 6405 }, 6406 [qib_sdma_state_s10_hw_start_up_wait] = { 6407 .op_enable = 0, 6408 .op_intenable = 1, 6409 .op_halt = 1, 6410 .op_drain = 0, 6411 }, 6412 [qib_sdma_state_s20_idle] = { 6413 .op_enable = 1, 6414 .op_intenable = 1, 6415 .op_halt = 1, 6416 .op_drain = 0, 6417 }, 6418 [qib_sdma_state_s30_sw_clean_up_wait] = { 6419 .op_enable = 0, 6420 .op_intenable = 1, 6421 .op_halt = 1, 6422 .op_drain = 0, 6423 }, 6424 [qib_sdma_state_s40_hw_clean_up_wait] = { 6425 .op_enable = 1, 6426 .op_intenable = 1, 6427 .op_halt = 1, 6428 .op_drain = 0, 6429 }, 6430 [qib_sdma_state_s50_hw_halt_wait] = { 6431 .op_enable = 1, 6432 .op_intenable = 1, 6433 .op_halt = 1, 6434 .op_drain = 1, 6435 }, 6436 [qib_sdma_state_s99_running] = { 6437 .op_enable = 1, 6438 .op_intenable = 1, 6439 .op_halt = 0, 6440 .op_drain = 0, 6441 .go_s99_running_totrue = 1, 6442 }, 6443 }; 6444 6445 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd) 6446 { 6447 ppd->sdma_state.set_state_action = sdma_7322_action_table; 6448 } 6449 6450 static int init_sdma_7322_regs(struct qib_pportdata *ppd) 6451 { 6452 struct qib_devdata *dd = ppd->dd; 6453 unsigned lastbuf, erstbuf; 6454 u64 senddmabufmask[3] = { 0 }; 6455 int n, ret = 0; 6456 6457 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys); 6458 qib_sdma_7322_setlengen(ppd); 6459 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 6460 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt); 6461 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0); 6462 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys); 6463 6464 if (dd->num_pports) 6465 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ 6466 else 6467 n = dd->cspec->sdmabufcnt; /* failsafe for init */ 6468 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - 6469 ((dd->num_pports == 1 || ppd->port == 2) ? n : 6470 dd->cspec->sdmabufcnt); 6471 lastbuf = erstbuf + n; 6472 6473 ppd->sdma_state.first_sendbuf = erstbuf; 6474 ppd->sdma_state.last_sendbuf = lastbuf; 6475 for (; erstbuf < lastbuf; ++erstbuf) { 6476 unsigned word = erstbuf / BITS_PER_LONG; 6477 unsigned bit = erstbuf & (BITS_PER_LONG - 1); 6478 6479 BUG_ON(word >= 3); 6480 senddmabufmask[word] |= 1ULL << bit; 6481 } 6482 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]); 6483 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]); 6484 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]); 6485 return ret; 6486 } 6487 6488 /* sdma_lock must be held */ 6489 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd) 6490 { 6491 struct qib_devdata *dd = ppd->dd; 6492 int sane; 6493 int use_dmahead; 6494 u16 swhead; 6495 u16 swtail; 6496 u16 cnt; 6497 u16 hwhead; 6498 6499 use_dmahead = __qib_sdma_running(ppd) && 6500 (dd->flags & QIB_HAS_SDMA_TIMEOUT); 6501 retry: 6502 hwhead = use_dmahead ? 6503 (u16) le64_to_cpu(*ppd->sdma_head_dma) : 6504 (u16) qib_read_kreg_port(ppd, krp_senddmahead); 6505 6506 swhead = ppd->sdma_descq_head; 6507 swtail = ppd->sdma_descq_tail; 6508 cnt = ppd->sdma_descq_cnt; 6509 6510 if (swhead < swtail) 6511 /* not wrapped */ 6512 sane = (hwhead >= swhead) & (hwhead <= swtail); 6513 else if (swhead > swtail) 6514 /* wrapped around */ 6515 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 6516 (hwhead <= swtail); 6517 else 6518 /* empty */ 6519 sane = (hwhead == swhead); 6520 6521 if (unlikely(!sane)) { 6522 if (use_dmahead) { 6523 /* try one more time, directly from the register */ 6524 use_dmahead = 0; 6525 goto retry; 6526 } 6527 /* proceed as if no progress */ 6528 hwhead = swhead; 6529 } 6530 6531 return hwhead; 6532 } 6533 6534 static int qib_sdma_7322_busy(struct qib_pportdata *ppd) 6535 { 6536 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus); 6537 6538 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || 6539 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || 6540 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || 6541 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); 6542 } 6543 6544 /* 6545 * Compute the amount of delay before sending the next packet if the 6546 * port's send rate differs from the static rate set for the QP. 6547 * The delay affects the next packet and the amount of the delay is 6548 * based on the length of the this packet. 6549 */ 6550 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen, 6551 u8 srate, u8 vl) 6552 { 6553 u8 snd_mult = ppd->delay_mult; 6554 u8 rcv_mult = ib_rate_to_delay[srate]; 6555 u32 ret; 6556 6557 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0; 6558 6559 /* Indicate VL15, else set the VL in the control word */ 6560 if (vl == 15) 6561 ret |= PBC_7322_VL15_SEND_CTRL; 6562 else 6563 ret |= vl << PBC_VL_NUM_LSB; 6564 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB; 6565 6566 return ret; 6567 } 6568 6569 /* 6570 * Enable the per-port VL15 send buffers for use. 6571 * They follow the rest of the buffers, without a config parameter. 6572 * This was in initregs, but that is done before the shadow 6573 * is set up, and this has to be done after the shadow is 6574 * set up. 6575 */ 6576 static void qib_7322_initvl15_bufs(struct qib_devdata *dd) 6577 { 6578 unsigned vl15bufs; 6579 6580 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; 6581 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, 6582 TXCHK_CHG_TYPE_KERN, NULL); 6583 } 6584 6585 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd) 6586 { 6587 if (rcd->ctxt < NUM_IB_PORTS) { 6588 if (rcd->dd->num_pports > 1) { 6589 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2; 6590 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; 6591 } else { 6592 rcd->rcvegrcnt = KCTXT0_EGRCNT; 6593 rcd->rcvegr_tid_base = 0; 6594 } 6595 } else { 6596 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; 6597 rcd->rcvegr_tid_base = KCTXT0_EGRCNT + 6598 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; 6599 } 6600 } 6601 6602 #define QTXSLEEPS 5000 6603 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, 6604 u32 len, u32 which, struct qib_ctxtdata *rcd) 6605 { 6606 int i; 6607 const int last = start + len - 1; 6608 const int lastr = last / BITS_PER_LONG; 6609 u32 sleeps = 0; 6610 int wait = rcd != NULL; 6611 unsigned long flags; 6612 6613 while (wait) { 6614 unsigned long shadow; 6615 int cstart, previ = -1; 6616 6617 /* 6618 * when flipping from kernel to user, we can't change 6619 * the checking type if the buffer is allocated to the 6620 * driver. It's OK the other direction, because it's 6621 * from close, and we have just disarm'ed all the 6622 * buffers. All the kernel to kernel changes are also 6623 * OK. 6624 */ 6625 for (cstart = start; cstart <= last; cstart++) { 6626 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 6627 / BITS_PER_LONG; 6628 if (i != previ) { 6629 shadow = (unsigned long) 6630 le64_to_cpu(dd->pioavailregs_dma[i]); 6631 previ = i; 6632 } 6633 if (test_bit(((2 * cstart) + 6634 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 6635 % BITS_PER_LONG, &shadow)) 6636 break; 6637 } 6638 6639 if (cstart > last) 6640 break; 6641 6642 if (sleeps == QTXSLEEPS) 6643 break; 6644 /* make sure we see an updated copy next time around */ 6645 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6646 sleeps++; 6647 msleep(20); 6648 } 6649 6650 switch (which) { 6651 case TXCHK_CHG_TYPE_DIS1: 6652 /* 6653 * disable checking on a range; used by diags; just 6654 * one buffer, but still written generically 6655 */ 6656 for (i = start; i <= last; i++) 6657 clear_bit(i, dd->cspec->sendchkenable); 6658 break; 6659 6660 case TXCHK_CHG_TYPE_ENAB1: 6661 /* 6662 * (re)enable checking on a range; used by diags; just 6663 * one buffer, but still written generically; read 6664 * scratch to be sure buffer actually triggered, not 6665 * just flushed from processor. 6666 */ 6667 qib_read_kreg32(dd, kr_scratch); 6668 for (i = start; i <= last; i++) 6669 set_bit(i, dd->cspec->sendchkenable); 6670 break; 6671 6672 case TXCHK_CHG_TYPE_KERN: 6673 /* usable by kernel */ 6674 for (i = start; i <= last; i++) { 6675 set_bit(i, dd->cspec->sendibchk); 6676 clear_bit(i, dd->cspec->sendgrhchk); 6677 } 6678 spin_lock_irqsave(&dd->uctxt_lock, flags); 6679 /* see if we need to raise avail update threshold */ 6680 for (i = dd->first_user_ctxt; 6681 dd->cspec->updthresh != dd->cspec->updthresh_dflt 6682 && i < dd->cfgctxts; i++) 6683 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && 6684 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) 6685 < dd->cspec->updthresh_dflt) 6686 break; 6687 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 6688 if (i == dd->cfgctxts) { 6689 spin_lock_irqsave(&dd->sendctrl_lock, flags); 6690 dd->cspec->updthresh = dd->cspec->updthresh_dflt; 6691 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 6692 dd->sendctrl |= (dd->cspec->updthresh & 6693 SYM_RMASK(SendCtrl, AvailUpdThld)) << 6694 SYM_LSB(SendCtrl, AvailUpdThld); 6695 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6696 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6697 } 6698 break; 6699 6700 case TXCHK_CHG_TYPE_USER: 6701 /* for user process */ 6702 for (i = start; i <= last; i++) { 6703 clear_bit(i, dd->cspec->sendibchk); 6704 set_bit(i, dd->cspec->sendgrhchk); 6705 } 6706 spin_lock_irqsave(&dd->sendctrl_lock, flags); 6707 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt 6708 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { 6709 dd->cspec->updthresh = (rcd->piocnt / 6710 rcd->subctxt_cnt) - 1; 6711 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 6712 dd->sendctrl |= (dd->cspec->updthresh & 6713 SYM_RMASK(SendCtrl, AvailUpdThld)) 6714 << SYM_LSB(SendCtrl, AvailUpdThld); 6715 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6716 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6717 } else 6718 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6719 break; 6720 6721 default: 6722 break; 6723 } 6724 6725 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i) 6726 qib_write_kreg(dd, kr_sendcheckmask + i, 6727 dd->cspec->sendchkenable[i]); 6728 6729 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) { 6730 qib_write_kreg(dd, kr_sendgrhcheckmask + i, 6731 dd->cspec->sendgrhchk[i]); 6732 qib_write_kreg(dd, kr_sendibpktmask + i, 6733 dd->cspec->sendibchk[i]); 6734 } 6735 6736 /* 6737 * Be sure whatever we did was seen by the chip and acted upon, 6738 * before we return. Mostly important for which >= 2. 6739 */ 6740 qib_read_kreg32(dd, kr_scratch); 6741 } 6742 6743 6744 /* useful for trigger analyzers, etc. */ 6745 static void writescratch(struct qib_devdata *dd, u32 val) 6746 { 6747 qib_write_kreg(dd, kr_scratch, val); 6748 } 6749 6750 /* Dummy for now, use chip regs soon */ 6751 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) 6752 { 6753 return -ENXIO; 6754 } 6755 6756 /** 6757 * qib_init_iba7322_funcs - set up the chip-specific function pointers 6758 * @dev: the pci_dev for qlogic_ib device 6759 * @ent: pci_device_id struct for this dev 6760 * 6761 * Also allocates, inits, and returns the devdata struct for this 6762 * device instance 6763 * 6764 * This is global, and is called directly at init to set up the 6765 * chip-specific function pointers for later use. 6766 */ 6767 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, 6768 const struct pci_device_id *ent) 6769 { 6770 struct qib_devdata *dd; 6771 int ret, i; 6772 u32 tabsize, actual_cnt = 0; 6773 6774 dd = qib_alloc_devdata(pdev, 6775 NUM_IB_PORTS * sizeof(struct qib_pportdata) + 6776 sizeof(struct qib_chip_specific) + 6777 NUM_IB_PORTS * sizeof(struct qib_chippport_specific)); 6778 if (IS_ERR(dd)) 6779 goto bail; 6780 6781 dd->f_bringup_serdes = qib_7322_bringup_serdes; 6782 dd->f_cleanup = qib_setup_7322_cleanup; 6783 dd->f_clear_tids = qib_7322_clear_tids; 6784 dd->f_free_irq = qib_7322_free_irq; 6785 dd->f_get_base_info = qib_7322_get_base_info; 6786 dd->f_get_msgheader = qib_7322_get_msgheader; 6787 dd->f_getsendbuf = qib_7322_getsendbuf; 6788 dd->f_gpio_mod = gpio_7322_mod; 6789 dd->f_eeprom_wen = qib_7322_eeprom_wen; 6790 dd->f_hdrqempty = qib_7322_hdrqempty; 6791 dd->f_ib_updown = qib_7322_ib_updown; 6792 dd->f_init_ctxt = qib_7322_init_ctxt; 6793 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; 6794 dd->f_intr_fallback = qib_7322_intr_fallback; 6795 dd->f_late_initreg = qib_late_7322_initreg; 6796 dd->f_setpbc_control = qib_7322_setpbc_control; 6797 dd->f_portcntr = qib_portcntr_7322; 6798 dd->f_put_tid = qib_7322_put_tid; 6799 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; 6800 dd->f_rcvctrl = rcvctrl_7322_mod; 6801 dd->f_read_cntrs = qib_read_7322cntrs; 6802 dd->f_read_portcntrs = qib_read_7322portcntrs; 6803 dd->f_reset = qib_do_7322_reset; 6804 dd->f_init_sdma_regs = init_sdma_7322_regs; 6805 dd->f_sdma_busy = qib_sdma_7322_busy; 6806 dd->f_sdma_gethead = qib_sdma_7322_gethead; 6807 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; 6808 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; 6809 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; 6810 dd->f_sendctrl = sendctrl_7322_mod; 6811 dd->f_set_armlaunch = qib_set_7322_armlaunch; 6812 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; 6813 dd->f_iblink_state = qib_7322_iblink_state; 6814 dd->f_ibphys_portstate = qib_7322_phys_portstate; 6815 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; 6816 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; 6817 dd->f_set_ib_loopback = qib_7322_set_loopback; 6818 dd->f_get_ib_table = qib_7322_get_ib_table; 6819 dd->f_set_ib_table = qib_7322_set_ib_table; 6820 dd->f_set_intr_state = qib_7322_set_intr_state; 6821 dd->f_setextled = qib_setup_7322_setextled; 6822 dd->f_txchk_change = qib_7322_txchk_change; 6823 dd->f_update_usrhead = qib_update_7322_usrhead; 6824 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; 6825 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; 6826 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; 6827 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; 6828 dd->f_sdma_init_early = qib_7322_sdma_init_early; 6829 dd->f_writescratch = writescratch; 6830 dd->f_tempsense_rd = qib_7322_tempsense_rd; 6831 /* 6832 * Do remaining PCIe setup and save PCIe values in dd. 6833 * Any error printing is already done by the init code. 6834 * On return, we have the chip mapped, but chip registers 6835 * are not set up until start of qib_init_7322_variables. 6836 */ 6837 ret = qib_pcie_ddinit(dd, pdev, ent); 6838 if (ret < 0) 6839 goto bail_free; 6840 6841 /* initialize chip-specific variables */ 6842 ret = qib_init_7322_variables(dd); 6843 if (ret) 6844 goto bail_cleanup; 6845 6846 if (qib_mini_init || !dd->num_pports) 6847 goto bail; 6848 6849 /* 6850 * Determine number of vectors we want; depends on port count 6851 * and number of configured kernel receive queues actually used. 6852 * Should also depend on whether sdma is enabled or not, but 6853 * that's such a rare testing case it's not worth worrying about. 6854 */ 6855 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); 6856 for (i = 0; i < tabsize; i++) 6857 if ((i < ARRAY_SIZE(irq_table) && 6858 irq_table[i].port <= dd->num_pports) || 6859 (i >= ARRAY_SIZE(irq_table) && 6860 dd->rcd[i - ARRAY_SIZE(irq_table)])) 6861 actual_cnt++; 6862 /* reduce by ctxt's < 2 */ 6863 if (qib_krcvq01_no_msi) 6864 actual_cnt -= dd->num_pports; 6865 6866 tabsize = actual_cnt; 6867 dd->cspec->msix_entries = kmalloc(tabsize * 6868 sizeof(struct msix_entry), GFP_KERNEL); 6869 dd->cspec->msix_arg = kmalloc(tabsize * 6870 sizeof(void *), GFP_KERNEL); 6871 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) { 6872 qib_dev_err(dd, "No memory for MSIx table\n"); 6873 tabsize = 0; 6874 } 6875 for (i = 0; i < tabsize; i++) 6876 dd->cspec->msix_entries[i].entry = i; 6877 6878 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries)) 6879 qib_dev_err(dd, "Failed to setup PCIe or interrupts; " 6880 "continuing anyway\n"); 6881 /* may be less than we wanted, if not enough available */ 6882 dd->cspec->num_msix_entries = tabsize; 6883 6884 /* setup interrupt handler */ 6885 qib_setup_7322_interrupt(dd, 1); 6886 6887 /* clear diagctrl register, in case diags were running and crashed */ 6888 qib_write_kreg(dd, kr_hwdiagctrl, 0); 6889 6890 goto bail; 6891 6892 bail_cleanup: 6893 qib_pcie_ddcleanup(dd); 6894 bail_free: 6895 qib_free_devdata(dd); 6896 dd = ERR_PTR(ret); 6897 bail: 6898 return dd; 6899 } 6900 6901 /* 6902 * Set the table entry at the specified index from the table specifed. 6903 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first 6904 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR. 6905 * 'idx' below addresses the correct entry, while its 4 LSBs select the 6906 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table. 6907 */ 6908 #define DDS_ENT_AMP_LSB 14 6909 #define DDS_ENT_MAIN_LSB 9 6910 #define DDS_ENT_POST_LSB 5 6911 #define DDS_ENT_PRE_XTRA_LSB 3 6912 #define DDS_ENT_PRE_LSB 0 6913 6914 /* 6915 * Set one entry in the TxDDS table for spec'd port 6916 * ridx picks one of the entries, while tp points 6917 * to the appropriate table entry. 6918 */ 6919 static void set_txdds(struct qib_pportdata *ppd, int ridx, 6920 const struct txdds_ent *tp) 6921 { 6922 struct qib_devdata *dd = ppd->dd; 6923 u32 pack_ent; 6924 int regidx; 6925 6926 /* Get correct offset in chip-space, and in source table */ 6927 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx; 6928 /* 6929 * We do not use qib_write_kreg_port() because it was intended 6930 * only for registers in the lower "port specific" pages. 6931 * So do index calculation by hand. 6932 */ 6933 if (ppd->hw_pidx) 6934 regidx += (dd->palign / sizeof(u64)); 6935 6936 pack_ent = tp->amp << DDS_ENT_AMP_LSB; 6937 pack_ent |= tp->main << DDS_ENT_MAIN_LSB; 6938 pack_ent |= tp->pre << DDS_ENT_PRE_LSB; 6939 pack_ent |= tp->post << DDS_ENT_POST_LSB; 6940 qib_write_kreg(dd, regidx, pack_ent); 6941 /* Prevent back-to-back writes by hitting scratch */ 6942 qib_write_kreg(ppd->dd, kr_scratch, 0); 6943 } 6944 6945 static const struct vendor_txdds_ent vendor_txdds[] = { 6946 { /* Amphenol 1m 30awg NoEq */ 6947 { 0x41, 0x50, 0x48 }, "584470002 ", 6948 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 }, 6949 }, 6950 { /* Amphenol 3m 28awg NoEq */ 6951 { 0x41, 0x50, 0x48 }, "584470004 ", 6952 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 }, 6953 }, 6954 { /* Finisar 3m OM2 Optical */ 6955 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL", 6956 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 }, 6957 }, 6958 { /* Finisar 30m OM2 Optical */ 6959 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL", 6960 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 }, 6961 }, 6962 { /* Finisar Default OM2 Optical */ 6963 { 0x00, 0x90, 0x65 }, NULL, 6964 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 }, 6965 }, 6966 { /* Gore 1m 30awg NoEq */ 6967 { 0x00, 0x21, 0x77 }, "QSN3300-1 ", 6968 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 }, 6969 }, 6970 { /* Gore 2m 30awg NoEq */ 6971 { 0x00, 0x21, 0x77 }, "QSN3300-2 ", 6972 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 }, 6973 }, 6974 { /* Gore 1m 28awg NoEq */ 6975 { 0x00, 0x21, 0x77 }, "QSN3800-1 ", 6976 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 }, 6977 }, 6978 { /* Gore 3m 28awg NoEq */ 6979 { 0x00, 0x21, 0x77 }, "QSN3800-3 ", 6980 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 }, 6981 }, 6982 { /* Gore 5m 24awg Eq */ 6983 { 0x00, 0x21, 0x77 }, "QSN7000-5 ", 6984 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 }, 6985 }, 6986 { /* Gore 7m 24awg Eq */ 6987 { 0x00, 0x21, 0x77 }, "QSN7000-7 ", 6988 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 }, 6989 }, 6990 { /* Gore 5m 26awg Eq */ 6991 { 0x00, 0x21, 0x77 }, "QSN7600-5 ", 6992 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 }, 6993 }, 6994 { /* Gore 7m 26awg Eq */ 6995 { 0x00, 0x21, 0x77 }, "QSN7600-7 ", 6996 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 }, 6997 }, 6998 { /* Intersil 12m 24awg Active */ 6999 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224", 7000 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 }, 7001 }, 7002 { /* Intersil 10m 28awg Active */ 7003 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028", 7004 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 }, 7005 }, 7006 { /* Intersil 7m 30awg Active */ 7007 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730", 7008 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 }, 7009 }, 7010 { /* Intersil 5m 32awg Active */ 7011 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532", 7012 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 }, 7013 }, 7014 { /* Intersil Default Active */ 7015 { 0x00, 0x30, 0xB4 }, NULL, 7016 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 }, 7017 }, 7018 { /* Luxtera 20m Active Optical */ 7019 { 0x00, 0x25, 0x63 }, NULL, 7020 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 }, 7021 }, 7022 { /* Molex 1M Cu loopback */ 7023 { 0x00, 0x09, 0x3A }, "74763-0025 ", 7024 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, 7025 }, 7026 { /* Molex 2m 28awg NoEq */ 7027 { 0x00, 0x09, 0x3A }, "74757-2201 ", 7028 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 }, 7029 }, 7030 }; 7031 7032 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = { 7033 /* amp, pre, main, post */ 7034 { 2, 2, 15, 6 }, /* Loopback */ 7035 { 0, 0, 0, 1 }, /* 2 dB */ 7036 { 0, 0, 0, 2 }, /* 3 dB */ 7037 { 0, 0, 0, 3 }, /* 4 dB */ 7038 { 0, 0, 0, 4 }, /* 5 dB */ 7039 { 0, 0, 0, 5 }, /* 6 dB */ 7040 { 0, 0, 0, 6 }, /* 7 dB */ 7041 { 0, 0, 0, 7 }, /* 8 dB */ 7042 { 0, 0, 0, 8 }, /* 9 dB */ 7043 { 0, 0, 0, 9 }, /* 10 dB */ 7044 { 0, 0, 0, 10 }, /* 11 dB */ 7045 { 0, 0, 0, 11 }, /* 12 dB */ 7046 { 0, 0, 0, 12 }, /* 13 dB */ 7047 { 0, 0, 0, 13 }, /* 14 dB */ 7048 { 0, 0, 0, 14 }, /* 15 dB */ 7049 { 0, 0, 0, 15 }, /* 16 dB */ 7050 }; 7051 7052 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = { 7053 /* amp, pre, main, post */ 7054 { 2, 2, 15, 6 }, /* Loopback */ 7055 { 0, 0, 0, 8 }, /* 2 dB */ 7056 { 0, 0, 0, 8 }, /* 3 dB */ 7057 { 0, 0, 0, 9 }, /* 4 dB */ 7058 { 0, 0, 0, 9 }, /* 5 dB */ 7059 { 0, 0, 0, 10 }, /* 6 dB */ 7060 { 0, 0, 0, 10 }, /* 7 dB */ 7061 { 0, 0, 0, 11 }, /* 8 dB */ 7062 { 0, 0, 0, 11 }, /* 9 dB */ 7063 { 0, 0, 0, 12 }, /* 10 dB */ 7064 { 0, 0, 0, 12 }, /* 11 dB */ 7065 { 0, 0, 0, 13 }, /* 12 dB */ 7066 { 0, 0, 0, 13 }, /* 13 dB */ 7067 { 0, 0, 0, 14 }, /* 14 dB */ 7068 { 0, 0, 0, 14 }, /* 15 dB */ 7069 { 0, 0, 0, 15 }, /* 16 dB */ 7070 }; 7071 7072 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = { 7073 /* amp, pre, main, post */ 7074 { 2, 2, 15, 6 }, /* Loopback */ 7075 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */ 7076 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */ 7077 { 0, 1, 0, 11 }, /* 4 dB */ 7078 { 0, 1, 0, 13 }, /* 5 dB */ 7079 { 0, 1, 0, 15 }, /* 6 dB */ 7080 { 0, 1, 3, 15 }, /* 7 dB */ 7081 { 0, 1, 7, 15 }, /* 8 dB */ 7082 { 0, 1, 7, 15 }, /* 9 dB */ 7083 { 0, 1, 8, 15 }, /* 10 dB */ 7084 { 0, 1, 9, 15 }, /* 11 dB */ 7085 { 0, 1, 10, 15 }, /* 12 dB */ 7086 { 0, 2, 6, 15 }, /* 13 dB */ 7087 { 0, 2, 7, 15 }, /* 14 dB */ 7088 { 0, 2, 8, 15 }, /* 15 dB */ 7089 { 0, 2, 9, 15 }, /* 16 dB */ 7090 }; 7091 7092 /* 7093 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ. 7094 * These are mostly used for mez cards going through connectors 7095 * and backplane traces, but can be used to add other "unusual" 7096 * table values as well. 7097 */ 7098 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = { 7099 /* amp, pre, main, post */ 7100 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7101 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7102 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7103 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7104 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7105 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7106 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7107 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7108 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7109 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7110 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7111 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */ 7112 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */ 7113 }; 7114 7115 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = { 7116 /* amp, pre, main, post */ 7117 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7118 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7119 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7120 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7121 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7122 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7123 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7124 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7125 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7126 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7127 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7128 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */ 7129 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */ 7130 }; 7131 7132 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = { 7133 /* amp, pre, main, post */ 7134 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */ 7135 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */ 7136 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */ 7137 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */ 7138 { 0, 1, 12, 10 }, /* QME7342 backplane setting */ 7139 { 0, 1, 12, 11 }, /* QME7342 backplane setting */ 7140 { 0, 1, 12, 12 }, /* QME7342 backplane setting */ 7141 { 0, 1, 12, 14 }, /* QME7342 backplane setting */ 7142 { 0, 1, 12, 6 }, /* QME7342 backplane setting */ 7143 { 0, 1, 12, 7 }, /* QME7342 backplane setting */ 7144 { 0, 1, 12, 8 }, /* QME7342 backplane setting */ 7145 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */ 7146 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ 7147 }; 7148 7149 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = { 7150 /* amp, pre, main, post */ 7151 { 0, 0, 0, 0 }, /* QME7342 mfg settings */ 7152 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */ 7153 }; 7154 7155 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 7156 unsigned atten) 7157 { 7158 /* 7159 * The attenuation table starts at 2dB for entry 1, 7160 * with entry 0 being the loopback entry. 7161 */ 7162 if (atten <= 2) 7163 atten = 1; 7164 else if (atten > TXDDS_TABLE_SZ) 7165 atten = TXDDS_TABLE_SZ - 1; 7166 else 7167 atten--; 7168 return txdds + atten; 7169 } 7170 7171 /* 7172 * if override is set, the module parameter txselect has a value 7173 * for this specific port, so use it, rather than our normal mechanism. 7174 */ 7175 static void find_best_ent(struct qib_pportdata *ppd, 7176 const struct txdds_ent **sdr_dds, 7177 const struct txdds_ent **ddr_dds, 7178 const struct txdds_ent **qdr_dds, int override) 7179 { 7180 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache; 7181 int idx; 7182 7183 /* Search table of known cables */ 7184 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) { 7185 const struct vendor_txdds_ent *v = vendor_txdds + idx; 7186 7187 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) && 7188 (!v->partnum || 7189 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) { 7190 *sdr_dds = &v->sdr; 7191 *ddr_dds = &v->ddr; 7192 *qdr_dds = &v->qdr; 7193 return; 7194 } 7195 } 7196 7197 /* Active cables don't have attenuation so we only set SERDES 7198 * settings to account for the attenuation of the board traces. */ 7199 if (!override && QSFP_IS_ACTIVE(qd->tech)) { 7200 *sdr_dds = txdds_sdr + ppd->dd->board_atten; 7201 *ddr_dds = txdds_ddr + ppd->dd->board_atten; 7202 *qdr_dds = txdds_qdr + ppd->dd->board_atten; 7203 return; 7204 } 7205 7206 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] || 7207 qd->atten[1])) { 7208 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]); 7209 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]); 7210 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]); 7211 return; 7212 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) { 7213 /* 7214 * If we have no (or incomplete) data from the cable 7215 * EEPROM, or no QSFP, or override is set, use the 7216 * module parameter value to index into the attentuation 7217 * table. 7218 */ 7219 idx = ppd->cpspec->no_eep; 7220 *sdr_dds = &txdds_sdr[idx]; 7221 *ddr_dds = &txdds_ddr[idx]; 7222 *qdr_dds = &txdds_qdr[idx]; 7223 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { 7224 /* similar to above, but index into the "extra" table. */ 7225 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ; 7226 *sdr_dds = &txdds_extra_sdr[idx]; 7227 *ddr_dds = &txdds_extra_ddr[idx]; 7228 *qdr_dds = &txdds_extra_qdr[idx]; 7229 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && 7230 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 7231 TXDDS_MFG_SZ)) { 7232 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); 7233 printk(KERN_INFO QIB_DRV_NAME 7234 " IB%u:%u use idx %u into txdds_mfg\n", 7235 ppd->dd->unit, ppd->port, idx); 7236 *sdr_dds = &txdds_extra_mfg[idx]; 7237 *ddr_dds = &txdds_extra_mfg[idx]; 7238 *qdr_dds = &txdds_extra_mfg[idx]; 7239 } else { 7240 /* this shouldn't happen, it's range checked */ 7241 *sdr_dds = txdds_sdr + qib_long_atten; 7242 *ddr_dds = txdds_ddr + qib_long_atten; 7243 *qdr_dds = txdds_qdr + qib_long_atten; 7244 } 7245 } 7246 7247 static void init_txdds_table(struct qib_pportdata *ppd, int override) 7248 { 7249 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 7250 struct txdds_ent *dds; 7251 int idx; 7252 int single_ent = 0; 7253 7254 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override); 7255 7256 /* for mez cards or override, use the selected value for all entries */ 7257 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) 7258 single_ent = 1; 7259 7260 /* Fill in the first entry with the best entry found. */ 7261 set_txdds(ppd, 0, sdr_dds); 7262 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds); 7263 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds); 7264 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 7265 QIBL_LINKACTIVE)) { 7266 dds = (struct txdds_ent *)(ppd->link_speed_active == 7267 QIB_IB_QDR ? qdr_dds : 7268 (ppd->link_speed_active == 7269 QIB_IB_DDR ? ddr_dds : sdr_dds)); 7270 write_tx_serdes_param(ppd, dds); 7271 } 7272 7273 /* Fill in the remaining entries with the default table values. */ 7274 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) { 7275 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx); 7276 set_txdds(ppd, idx + TXDDS_TABLE_SZ, 7277 single_ent ? ddr_dds : txdds_ddr + idx); 7278 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ, 7279 single_ent ? qdr_dds : txdds_qdr + idx); 7280 } 7281 } 7282 7283 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl) 7284 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg) 7285 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy) 7286 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address) 7287 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data) 7288 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read) 7289 #define AHB_TRANS_TRIES 10 7290 7291 /* 7292 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4, 7293 * 5=subsystem which is why most calls have "chan + chan >> 1" 7294 * for the channel argument. 7295 */ 7296 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, 7297 u32 data, u32 mask) 7298 { 7299 u32 rd_data, wr_data, sz_mask; 7300 u64 trans, acc, prev_acc; 7301 u32 ret = 0xBAD0BAD; 7302 int tries; 7303 7304 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); 7305 /* From this point on, make sure we return access */ 7306 acc = (quad << 1) | 1; 7307 qib_write_kreg(dd, KR_AHB_ACC, acc); 7308 7309 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7310 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7311 if (trans & AHB_TRANS_RDY) 7312 break; 7313 } 7314 if (tries >= AHB_TRANS_TRIES) { 7315 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); 7316 goto bail; 7317 } 7318 7319 /* If mask is not all 1s, we need to read, but different SerDes 7320 * entities have different sizes 7321 */ 7322 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1; 7323 wr_data = data & mask & sz_mask; 7324 if ((~mask & sz_mask) != 0) { 7325 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7326 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7327 7328 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7329 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7330 if (trans & AHB_TRANS_RDY) 7331 break; 7332 } 7333 if (tries >= AHB_TRANS_TRIES) { 7334 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", 7335 AHB_TRANS_TRIES); 7336 goto bail; 7337 } 7338 /* Re-read in case host split reads and read data first */ 7339 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7340 rd_data = (uint32_t)(trans >> AHB_DATA_LSB); 7341 wr_data |= (rd_data & ~mask & sz_mask); 7342 } 7343 7344 /* If mask is not zero, we need to write. */ 7345 if (mask & sz_mask) { 7346 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7347 trans |= ((uint64_t)wr_data << AHB_DATA_LSB); 7348 trans |= AHB_WR; 7349 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7350 7351 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7352 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7353 if (trans & AHB_TRANS_RDY) 7354 break; 7355 } 7356 if (tries >= AHB_TRANS_TRIES) { 7357 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", 7358 AHB_TRANS_TRIES); 7359 goto bail; 7360 } 7361 } 7362 ret = wr_data; 7363 bail: 7364 qib_write_kreg(dd, KR_AHB_ACC, prev_acc); 7365 return ret; 7366 } 7367 7368 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data, 7369 unsigned mask) 7370 { 7371 struct qib_devdata *dd = ppd->dd; 7372 int chan; 7373 u32 rbc; 7374 7375 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7376 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, 7377 data, mask); 7378 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7379 addr, 0, 0); 7380 } 7381 } 7382 7383 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) 7384 { 7385 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl); 7386 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN); 7387 7388 if (enable && !state) { 7389 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n", 7390 ppd->dd->unit, ppd->port); 7391 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7392 } else if (!enable && state) { 7393 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n", 7394 ppd->dd->unit, ppd->port); 7395 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7396 } 7397 qib_write_kreg_port(ppd, krp_serdesctrl, data); 7398 } 7399 7400 static int serdes_7322_init(struct qib_pportdata *ppd) 7401 { 7402 int ret = 0; 7403 if (ppd->dd->cspec->r1) 7404 ret = serdes_7322_init_old(ppd); 7405 else 7406 ret = serdes_7322_init_new(ppd); 7407 return ret; 7408 } 7409 7410 static int serdes_7322_init_old(struct qib_pportdata *ppd) 7411 { 7412 u32 le_val; 7413 7414 /* 7415 * Initialize the Tx DDS tables. Also done every QSFP event, 7416 * for adapters with QSFP 7417 */ 7418 init_txdds_table(ppd, 0); 7419 7420 /* ensure no tx overrides from earlier driver loads */ 7421 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7422 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7423 reset_tx_deemphasis_override)); 7424 7425 /* Patch some SerDes defaults to "Better for IB" */ 7426 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */ 7427 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7428 7429 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7430 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7431 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */ 7432 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6)); 7433 7434 /* May be overridden in qsfp_7322_event */ 7435 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7436 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7437 7438 /* enable LE1 adaptation for all but QME, which is disabled */ 7439 le_val = IS_QME(ppd->dd) ? 0 : 1; 7440 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5)); 7441 7442 /* Clear cmode-override, may be set from older driver */ 7443 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7444 7445 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */ 7446 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8)); 7447 7448 /* setup LoS params; these are subsystem, so chan == 5 */ 7449 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7450 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7451 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7452 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7453 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7454 7455 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7456 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7457 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7458 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7459 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7460 7461 /* LoS filter select enabled */ 7462 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7463 7464 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7465 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7466 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7467 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7468 7469 serdes_7322_los_enable(ppd, 1); 7470 7471 /* rxbistena; set 0 to avoid effects of it switch later */ 7472 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); 7473 7474 /* Configure 4 DFE taps, and only they adapt */ 7475 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0)); 7476 7477 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7478 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7479 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7480 7481 /* 7482 * Set receive adaptation mode. SDR and DDR adaptation are 7483 * always on, and QDR is initially enabled; later disabled. 7484 */ 7485 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7486 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7487 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7488 ppd->dd->cspec->r1 ? 7489 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7490 ppd->cpspec->qdr_dfe_on = 1; 7491 7492 /* FLoop LOS gate: PPM filter enabled */ 7493 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7494 7495 /* rx offset center enabled */ 7496 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4); 7497 7498 if (!ppd->dd->cspec->r1) { 7499 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12); 7500 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8); 7501 } 7502 7503 /* Set the frequency loop bandwidth to 15 */ 7504 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); 7505 7506 return 0; 7507 } 7508 7509 static int serdes_7322_init_new(struct qib_pportdata *ppd) 7510 { 7511 unsigned long tend; 7512 u32 le_val, rxcaldone; 7513 int chan, chan_done = (1 << SERDES_CHANS) - 1; 7514 7515 /* Clear cmode-override, may be set from older driver */ 7516 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7517 7518 /* ensure no tx overrides from earlier driver loads */ 7519 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7520 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7521 reset_tx_deemphasis_override)); 7522 7523 /* START OF LSI SUGGESTED SERDES BRINGUP */ 7524 /* Reset - Calibration Setup */ 7525 /* Stop DFE adaptaion */ 7526 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1)); 7527 /* Disable LE1 */ 7528 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5)); 7529 /* Disable autoadapt for LE1 */ 7530 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15)); 7531 /* Disable LE2 */ 7532 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6)); 7533 /* Disable VGA */ 7534 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7535 /* Disable AFE Offset Cancel */ 7536 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12)); 7537 /* Disable Timing Loop */ 7538 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3)); 7539 /* Disable Frequency Loop */ 7540 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4)); 7541 /* Disable Baseline Wander Correction */ 7542 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13)); 7543 /* Disable RX Calibration */ 7544 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7545 /* Disable RX Offset Calibration */ 7546 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4)); 7547 /* Select BB CDR */ 7548 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15)); 7549 /* CDR Step Size */ 7550 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8)); 7551 /* Enable phase Calibration */ 7552 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5)); 7553 /* DFE Bandwidth [2:14-12] */ 7554 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12)); 7555 /* DFE Config (4 taps only) */ 7556 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0)); 7557 /* Gain Loop Bandwidth */ 7558 if (!ppd->dd->cspec->r1) { 7559 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12)); 7560 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8)); 7561 } else { 7562 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11)); 7563 } 7564 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ 7565 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ 7566 /* Data Rate Select [5:7-6] (leave as default) */ 7567 /* RX Parallel Word Width [3:10-8] (leave as default) */ 7568 7569 /* RX REST */ 7570 /* Single- or Multi-channel reset */ 7571 /* RX Analog reset */ 7572 /* RX Digital reset */ 7573 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13)); 7574 msleep(20); 7575 /* RX Analog reset */ 7576 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14)); 7577 msleep(20); 7578 /* RX Digital reset */ 7579 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13)); 7580 msleep(20); 7581 7582 /* setup LoS params; these are subsystem, so chan == 5 */ 7583 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7584 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7585 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7586 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7587 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7588 7589 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7590 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7591 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7592 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7593 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7594 7595 /* LoS filter select enabled */ 7596 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7597 7598 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7599 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7600 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7601 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7602 7603 /* Turn on LOS on initial SERDES init */ 7604 serdes_7322_los_enable(ppd, 1); 7605 /* FLoop LOS gate: PPM filter enabled */ 7606 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7607 7608 /* RX LATCH CALIBRATION */ 7609 /* Enable Eyefinder Phase Calibration latch */ 7610 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0)); 7611 /* Enable RX Offset Calibration latch */ 7612 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4)); 7613 msleep(20); 7614 /* Start Calibration */ 7615 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10)); 7616 tend = jiffies + msecs_to_jiffies(500); 7617 while (chan_done && !time_is_before_jiffies(tend)) { 7618 msleep(20); 7619 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7620 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7621 (chan + (chan >> 1)), 7622 25, 0, 0); 7623 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 && 7624 (~chan_done & (1 << chan)) == 0) 7625 chan_done &= ~(1 << chan); 7626 } 7627 } 7628 if (chan_done) { 7629 printk(KERN_INFO QIB_DRV_NAME 7630 " Serdes %d calibration not done after .5 sec: 0x%x\n", 7631 IBSD(ppd->hw_pidx), chan_done); 7632 } else { 7633 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7634 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7635 (chan + (chan >> 1)), 7636 25, 0, 0); 7637 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0) 7638 printk(KERN_INFO QIB_DRV_NAME 7639 " Serdes %d chan %d calibration " 7640 "failed\n", IBSD(ppd->hw_pidx), chan); 7641 } 7642 } 7643 7644 /* Turn off Calibration */ 7645 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7646 msleep(20); 7647 7648 /* BRING RX UP */ 7649 /* Set LE2 value (May be overridden in qsfp_7322_event) */ 7650 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7651 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7652 /* Set LE2 Loop bandwidth */ 7653 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5)); 7654 /* Enable LE2 */ 7655 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6)); 7656 msleep(20); 7657 /* Enable H0 only */ 7658 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1)); 7659 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7660 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7661 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7662 /* Enable VGA */ 7663 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7664 msleep(20); 7665 /* Set Frequency Loop Bandwidth */ 7666 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5)); 7667 /* Enable Frequency Loop */ 7668 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4)); 7669 /* Set Timing Loop Bandwidth */ 7670 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7671 /* Enable Timing Loop */ 7672 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3)); 7673 msleep(50); 7674 /* Enable DFE 7675 * Set receive adaptation mode. SDR and DDR adaptation are 7676 * always on, and QDR is initially enabled; later disabled. 7677 */ 7678 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7679 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7680 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7681 ppd->dd->cspec->r1 ? 7682 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7683 ppd->cpspec->qdr_dfe_on = 1; 7684 /* Disable LE1 */ 7685 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5)); 7686 /* Disable auto adapt for LE1 */ 7687 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15)); 7688 msleep(20); 7689 /* Enable AFE Offset Cancel */ 7690 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12)); 7691 /* Enable Baseline Wander Correction */ 7692 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13)); 7693 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7694 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7695 /* VGA output common mode */ 7696 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2)); 7697 7698 /* 7699 * Initialize the Tx DDS tables. Also done every QSFP event, 7700 * for adapters with QSFP 7701 */ 7702 init_txdds_table(ppd, 0); 7703 7704 return 0; 7705 } 7706 7707 /* start adjust QMH serdes parameters */ 7708 7709 static void set_man_code(struct qib_pportdata *ppd, int chan, int code) 7710 { 7711 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7712 9, code << 9, 0x3f << 9); 7713 } 7714 7715 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan, 7716 int enable, u32 tapenable) 7717 { 7718 if (enable) 7719 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7720 1, 3 << 10, 0x1f << 10); 7721 else 7722 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7723 1, 0, 0x1f << 10); 7724 } 7725 7726 /* Set clock to 1, 0, 1, 0 */ 7727 static void clock_man(struct qib_pportdata *ppd, int chan) 7728 { 7729 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7730 4, 0x4000, 0x4000); 7731 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7732 4, 0, 0x4000); 7733 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7734 4, 0x4000, 0x4000); 7735 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7736 4, 0, 0x4000); 7737 } 7738 7739 /* 7740 * write the current Tx serdes pre,post,main,amp settings into the serdes. 7741 * The caller must pass the settings appropriate for the current speed, 7742 * or not care if they are correct for the current speed. 7743 */ 7744 static void write_tx_serdes_param(struct qib_pportdata *ppd, 7745 struct txdds_ent *txdds) 7746 { 7747 u64 deemph; 7748 7749 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override); 7750 /* field names for amp, main, post, pre, respectively */ 7751 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | 7752 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | 7753 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | 7754 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); 7755 7756 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7757 tx_override_deemphasis_select); 7758 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7759 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7760 txampcntl_d2a); 7761 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7762 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7763 txc0_ena); 7764 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7765 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7766 txcp1_ena); 7767 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7768 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7769 txcn1_ena); 7770 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph); 7771 } 7772 7773 /* 7774 * Set the parameters for mez cards on link bounce, so they are 7775 * always exactly what was requested. Similar logic to init_txdds 7776 * but does just the serdes. 7777 */ 7778 static void adj_tx_serdes(struct qib_pportdata *ppd) 7779 { 7780 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 7781 struct txdds_ent *dds; 7782 7783 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1); 7784 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ? 7785 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ? 7786 ddr_dds : sdr_dds)); 7787 write_tx_serdes_param(ppd, dds); 7788 } 7789 7790 /* set QDR forced value for H1, if needed */ 7791 static void force_h1(struct qib_pportdata *ppd) 7792 { 7793 int chan; 7794 7795 ppd->cpspec->qdr_reforce = 0; 7796 if (!ppd->dd->cspec->r1) 7797 return; 7798 7799 for (chan = 0; chan < SERDES_CHANS; chan++) { 7800 set_man_mode_h1(ppd, chan, 1, 0); 7801 set_man_code(ppd, chan, ppd->cpspec->h1_val); 7802 clock_man(ppd, chan); 7803 set_man_mode_h1(ppd, chan, 0, 0); 7804 } 7805 } 7806 7807 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN) 7808 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en) 7809 7810 #define R_OPCODE_LSB 3 7811 #define R_OP_NOP 0 7812 #define R_OP_SHIFT 2 7813 #define R_OP_UPDATE 3 7814 #define R_TDI_LSB 2 7815 #define R_TDO_LSB 1 7816 #define R_RDY 1 7817 7818 static int qib_r_grab(struct qib_devdata *dd) 7819 { 7820 u64 val; 7821 val = SJA_EN; 7822 qib_write_kreg(dd, kr_r_access, val); 7823 qib_read_kreg32(dd, kr_scratch); 7824 return 0; 7825 } 7826 7827 /* qib_r_wait_for_rdy() not only waits for the ready bit, it 7828 * returns the current state of R_TDO 7829 */ 7830 static int qib_r_wait_for_rdy(struct qib_devdata *dd) 7831 { 7832 u64 val; 7833 int timeout; 7834 for (timeout = 0; timeout < 100 ; ++timeout) { 7835 val = qib_read_kreg32(dd, kr_r_access); 7836 if (val & R_RDY) 7837 return (val >> R_TDO_LSB) & 1; 7838 } 7839 return -1; 7840 } 7841 7842 static int qib_r_shift(struct qib_devdata *dd, int bisten, 7843 int len, u8 *inp, u8 *outp) 7844 { 7845 u64 valbase, val; 7846 int ret, pos; 7847 7848 valbase = SJA_EN | (bisten << BISTEN_LSB) | 7849 (R_OP_SHIFT << R_OPCODE_LSB); 7850 ret = qib_r_wait_for_rdy(dd); 7851 if (ret < 0) 7852 goto bail; 7853 for (pos = 0; pos < len; ++pos) { 7854 val = valbase; 7855 if (outp) { 7856 outp[pos >> 3] &= ~(1 << (pos & 7)); 7857 outp[pos >> 3] |= (ret << (pos & 7)); 7858 } 7859 if (inp) { 7860 int tdi = inp[pos >> 3] >> (pos & 7); 7861 val |= ((tdi & 1) << R_TDI_LSB); 7862 } 7863 qib_write_kreg(dd, kr_r_access, val); 7864 qib_read_kreg32(dd, kr_scratch); 7865 ret = qib_r_wait_for_rdy(dd); 7866 if (ret < 0) 7867 break; 7868 } 7869 /* Restore to NOP between operations. */ 7870 val = SJA_EN | (bisten << BISTEN_LSB); 7871 qib_write_kreg(dd, kr_r_access, val); 7872 qib_read_kreg32(dd, kr_scratch); 7873 ret = qib_r_wait_for_rdy(dd); 7874 7875 if (ret >= 0) 7876 ret = pos; 7877 bail: 7878 return ret; 7879 } 7880 7881 static int qib_r_update(struct qib_devdata *dd, int bisten) 7882 { 7883 u64 val; 7884 int ret; 7885 7886 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB); 7887 ret = qib_r_wait_for_rdy(dd); 7888 if (ret >= 0) { 7889 qib_write_kreg(dd, kr_r_access, val); 7890 qib_read_kreg32(dd, kr_scratch); 7891 } 7892 return ret; 7893 } 7894 7895 #define BISTEN_PORT_SEL 15 7896 #define LEN_PORT_SEL 625 7897 #define BISTEN_AT 17 7898 #define LEN_AT 156 7899 #define BISTEN_ETM 16 7900 #define LEN_ETM 632 7901 7902 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE) 7903 7904 /* these are common for all IB port use cases. */ 7905 static u8 reset_at[BIT2BYTE(LEN_AT)] = { 7906 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7907 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 7908 }; 7909 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = { 7910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7912 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e, 7913 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7, 7914 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70, 7915 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00, 7916 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7917 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 7918 }; 7919 static u8 at[BIT2BYTE(LEN_AT)] = { 7920 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 7921 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 7922 }; 7923 7924 /* used for IB1 or IB2, only one in use */ 7925 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = { 7926 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7927 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7928 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7929 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00, 7930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7931 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03, 7932 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00, 7933 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 7934 }; 7935 7936 /* used when both IB1 and IB2 are in use */ 7937 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = { 7938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 7940 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7941 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05, 7942 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 7943 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07, 7944 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00, 7945 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 7946 }; 7947 7948 /* used when only IB1 is in use */ 7949 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = { 7950 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 7951 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 7952 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7953 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7954 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 7955 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7956 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7957 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 7958 }; 7959 7960 /* used when only IB2 is in use */ 7961 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = { 7962 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39, 7963 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32, 7964 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 7965 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 7966 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32, 7967 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 7968 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 7969 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 7970 }; 7971 7972 /* used when both IB1 and IB2 are in use */ 7973 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = { 7974 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 7975 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 7976 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7977 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7978 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 7979 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a, 7980 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7981 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 7982 }; 7983 7984 /* 7985 * Do setup to properly handle IB link recovery; if port is zero, we 7986 * are initializing to cover both ports; otherwise we are initializing 7987 * to cover a single port card, or the port has reached INIT and we may 7988 * need to switch coverage types. 7989 */ 7990 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both) 7991 { 7992 u8 *portsel, *etm; 7993 struct qib_devdata *dd = ppd->dd; 7994 7995 if (!ppd->dd->cspec->r1) 7996 return; 7997 if (!both) { 7998 dd->cspec->recovery_ports_initted++; 7999 ppd->cpspec->recovery_init = 1; 8000 } 8001 if (!both && dd->cspec->recovery_ports_initted == 1) { 8002 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2; 8003 etm = atetm_1port; 8004 } else { 8005 portsel = portsel_2port; 8006 etm = atetm_2port; 8007 } 8008 8009 if (qib_r_grab(dd) < 0 || 8010 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || 8011 qib_r_update(dd, BISTEN_ETM) < 0 || 8012 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || 8013 qib_r_update(dd, BISTEN_AT) < 0 || 8014 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, 8015 portsel, NULL) < 0 || 8016 qib_r_update(dd, BISTEN_PORT_SEL) < 0 || 8017 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || 8018 qib_r_update(dd, BISTEN_AT) < 0 || 8019 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || 8020 qib_r_update(dd, BISTEN_ETM) < 0) 8021 qib_dev_err(dd, "Failed IB link recovery setup\n"); 8022 } 8023 8024 static void check_7322_rxe_status(struct qib_pportdata *ppd) 8025 { 8026 struct qib_devdata *dd = ppd->dd; 8027 u64 fmask; 8028 8029 if (dd->cspec->recovery_ports_initted != 1) 8030 return; /* rest doesn't apply to dualport */ 8031 qib_write_kreg(dd, kr_control, dd->control | 8032 SYM_MASK(Control, FreezeMode)); 8033 (void)qib_read_kreg64(dd, kr_scratch); 8034 udelay(3); /* ibcreset asserted 400ns, be sure that's over */ 8035 fmask = qib_read_kreg64(dd, kr_act_fmask); 8036 if (!fmask) { 8037 /* 8038 * require a powercycle before we'll work again, and make 8039 * sure we get no more interrupts, and don't turn off 8040 * freeze. 8041 */ 8042 ppd->dd->cspec->stay_in_freeze = 1; 8043 qib_7322_set_intr_state(ppd->dd, 0); 8044 qib_write_kreg(dd, kr_fmask, 0ULL); 8045 qib_dev_err(dd, "HCA unusable until powercycled\n"); 8046 return; /* eventually reset */ 8047 } 8048 8049 qib_write_kreg(ppd->dd, kr_hwerrclear, 8050 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); 8051 8052 /* don't do the full clear_freeze(), not needed for this */ 8053 qib_write_kreg(dd, kr_control, dd->control); 8054 qib_read_kreg32(dd, kr_scratch); 8055 /* take IBC out of reset */ 8056 if (ppd->link_speed_supported) { 8057 ppd->cpspec->ibcctrl_a &= 8058 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 8059 qib_write_kreg_port(ppd, krp_ibcctrl_a, 8060 ppd->cpspec->ibcctrl_a); 8061 qib_read_kreg32(dd, kr_scratch); 8062 if (ppd->lflags & QIBL_IB_LINK_DISABLED) 8063 qib_set_ib_7322_lstate(ppd, 0, 8064 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 8065 } 8066 } 8067