1 /* 2 * Copyright (c) 2013 Intel Corporation. All rights reserved. 3 * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved. 4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/spinlock.h> 36 #include <linux/pci.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/netdevice.h> 40 #include <linux/vmalloc.h> 41 #include <linux/module.h> 42 #include <linux/prefetch.h> 43 44 #include "qib.h" 45 46 /* 47 * The size has to be longer than this string, so we can append 48 * board/chip information to it in the init code. 49 */ 50 const char ib_qib_version[] = QIB_DRIVER_VERSION "\n"; 51 52 DEFINE_SPINLOCK(qib_devs_lock); 53 LIST_HEAD(qib_dev_list); 54 DEFINE_MUTEX(qib_mutex); /* general driver use */ 55 56 unsigned qib_ibmtu; 57 module_param_named(ibmtu, qib_ibmtu, uint, S_IRUGO); 58 MODULE_PARM_DESC(ibmtu, "Set max IB MTU (0=2KB, 1=256, 2=512, ... 5=4096"); 59 60 unsigned qib_compat_ddr_negotiate = 1; 61 module_param_named(compat_ddr_negotiate, qib_compat_ddr_negotiate, uint, 62 S_IWUSR | S_IRUGO); 63 MODULE_PARM_DESC(compat_ddr_negotiate, 64 "Attempt pre-IBTA 1.2 DDR speed negotiation"); 65 66 MODULE_LICENSE("Dual BSD/GPL"); 67 MODULE_AUTHOR("Intel <ibsupport@intel.com>"); 68 MODULE_DESCRIPTION("Intel IB driver"); 69 MODULE_VERSION(QIB_DRIVER_VERSION); 70 71 /* 72 * QIB_PIO_MAXIBHDR is the max IB header size allowed for in our 73 * PIO send buffers. This is well beyond anything currently 74 * defined in the InfiniBand spec. 75 */ 76 #define QIB_PIO_MAXIBHDR 128 77 78 /* 79 * QIB_MAX_PKT_RCV is the max # if packets processed per receive interrupt. 80 */ 81 #define QIB_MAX_PKT_RECV 64 82 83 struct qlogic_ib_stats qib_stats; 84 85 const char *qib_get_unit_name(int unit) 86 { 87 static char iname[16]; 88 89 snprintf(iname, sizeof(iname), "infinipath%u", unit); 90 return iname; 91 } 92 93 const char *qib_get_card_name(struct rvt_dev_info *rdi) 94 { 95 struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi); 96 struct qib_devdata *dd = container_of(ibdev, 97 struct qib_devdata, verbs_dev); 98 return qib_get_unit_name(dd->unit); 99 } 100 101 struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi) 102 { 103 struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi); 104 struct qib_devdata *dd = container_of(ibdev, 105 struct qib_devdata, verbs_dev); 106 return dd->pcidev; 107 } 108 109 /* 110 * Return count of units with at least one port ACTIVE. 111 */ 112 int qib_count_active_units(void) 113 { 114 struct qib_devdata *dd; 115 struct qib_pportdata *ppd; 116 unsigned long flags; 117 int pidx, nunits_active = 0; 118 119 spin_lock_irqsave(&qib_devs_lock, flags); 120 list_for_each_entry(dd, &qib_dev_list, list) { 121 if (!(dd->flags & QIB_PRESENT) || !dd->kregbase) 122 continue; 123 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 124 ppd = dd->pport + pidx; 125 if (ppd->lid && (ppd->lflags & (QIBL_LINKINIT | 126 QIBL_LINKARMED | QIBL_LINKACTIVE))) { 127 nunits_active++; 128 break; 129 } 130 } 131 } 132 spin_unlock_irqrestore(&qib_devs_lock, flags); 133 return nunits_active; 134 } 135 136 /* 137 * Return count of all units, optionally return in arguments 138 * the number of usable (present) units, and the number of 139 * ports that are up. 140 */ 141 int qib_count_units(int *npresentp, int *nupp) 142 { 143 int nunits = 0, npresent = 0, nup = 0; 144 struct qib_devdata *dd; 145 unsigned long flags; 146 int pidx; 147 struct qib_pportdata *ppd; 148 149 spin_lock_irqsave(&qib_devs_lock, flags); 150 151 list_for_each_entry(dd, &qib_dev_list, list) { 152 nunits++; 153 if ((dd->flags & QIB_PRESENT) && dd->kregbase) 154 npresent++; 155 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 156 ppd = dd->pport + pidx; 157 if (ppd->lid && (ppd->lflags & (QIBL_LINKINIT | 158 QIBL_LINKARMED | QIBL_LINKACTIVE))) 159 nup++; 160 } 161 } 162 163 spin_unlock_irqrestore(&qib_devs_lock, flags); 164 165 if (npresentp) 166 *npresentp = npresent; 167 if (nupp) 168 *nupp = nup; 169 170 return nunits; 171 } 172 173 /** 174 * qib_wait_linkstate - wait for an IB link state change to occur 175 * @dd: the qlogic_ib device 176 * @state: the state to wait for 177 * @msecs: the number of milliseconds to wait 178 * 179 * wait up to msecs milliseconds for IB link state change to occur for 180 * now, take the easy polling route. Currently used only by 181 * qib_set_linkstate. Returns 0 if state reached, otherwise 182 * -ETIMEDOUT state can have multiple states set, for any of several 183 * transitions. 184 */ 185 int qib_wait_linkstate(struct qib_pportdata *ppd, u32 state, int msecs) 186 { 187 int ret; 188 unsigned long flags; 189 190 spin_lock_irqsave(&ppd->lflags_lock, flags); 191 if (ppd->state_wanted) { 192 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 193 ret = -EBUSY; 194 goto bail; 195 } 196 ppd->state_wanted = state; 197 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 198 wait_event_interruptible_timeout(ppd->state_wait, 199 (ppd->lflags & state), 200 msecs_to_jiffies(msecs)); 201 spin_lock_irqsave(&ppd->lflags_lock, flags); 202 ppd->state_wanted = 0; 203 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 204 205 if (!(ppd->lflags & state)) 206 ret = -ETIMEDOUT; 207 else 208 ret = 0; 209 bail: 210 return ret; 211 } 212 213 int qib_set_linkstate(struct qib_pportdata *ppd, u8 newstate) 214 { 215 u32 lstate; 216 int ret; 217 struct qib_devdata *dd = ppd->dd; 218 unsigned long flags; 219 220 switch (newstate) { 221 case QIB_IB_LINKDOWN_ONLY: 222 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 223 IB_LINKCMD_DOWN | IB_LINKINITCMD_NOP); 224 /* don't wait */ 225 ret = 0; 226 goto bail; 227 228 case QIB_IB_LINKDOWN: 229 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 230 IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL); 231 /* don't wait */ 232 ret = 0; 233 goto bail; 234 235 case QIB_IB_LINKDOWN_SLEEP: 236 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 237 IB_LINKCMD_DOWN | IB_LINKINITCMD_SLEEP); 238 /* don't wait */ 239 ret = 0; 240 goto bail; 241 242 case QIB_IB_LINKDOWN_DISABLE: 243 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 244 IB_LINKCMD_DOWN | IB_LINKINITCMD_DISABLE); 245 /* don't wait */ 246 ret = 0; 247 goto bail; 248 249 case QIB_IB_LINKARM: 250 if (ppd->lflags & QIBL_LINKARMED) { 251 ret = 0; 252 goto bail; 253 } 254 if (!(ppd->lflags & (QIBL_LINKINIT | QIBL_LINKACTIVE))) { 255 ret = -EINVAL; 256 goto bail; 257 } 258 /* 259 * Since the port can be ACTIVE when we ask for ARMED, 260 * clear QIBL_LINKV so we can wait for a transition. 261 * If the link isn't ARMED, then something else happened 262 * and there is no point waiting for ARMED. 263 */ 264 spin_lock_irqsave(&ppd->lflags_lock, flags); 265 ppd->lflags &= ~QIBL_LINKV; 266 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 267 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 268 IB_LINKCMD_ARMED | IB_LINKINITCMD_NOP); 269 lstate = QIBL_LINKV; 270 break; 271 272 case QIB_IB_LINKACTIVE: 273 if (ppd->lflags & QIBL_LINKACTIVE) { 274 ret = 0; 275 goto bail; 276 } 277 if (!(ppd->lflags & QIBL_LINKARMED)) { 278 ret = -EINVAL; 279 goto bail; 280 } 281 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 282 IB_LINKCMD_ACTIVE | IB_LINKINITCMD_NOP); 283 lstate = QIBL_LINKACTIVE; 284 break; 285 286 default: 287 ret = -EINVAL; 288 goto bail; 289 } 290 ret = qib_wait_linkstate(ppd, lstate, 10); 291 292 bail: 293 return ret; 294 } 295 296 /* 297 * Get address of eager buffer from it's index (allocated in chunks, not 298 * contiguous). 299 */ 300 static inline void *qib_get_egrbuf(const struct qib_ctxtdata *rcd, u32 etail) 301 { 302 const u32 chunk = etail >> rcd->rcvegrbufs_perchunk_shift; 303 const u32 idx = etail & ((u32)rcd->rcvegrbufs_perchunk - 1); 304 305 return rcd->rcvegrbuf[chunk] + (idx << rcd->dd->rcvegrbufsize_shift); 306 } 307 308 /* 309 * Returns 1 if error was a CRC, else 0. 310 * Needed for some chip's synthesized error counters. 311 */ 312 static u32 qib_rcv_hdrerr(struct qib_ctxtdata *rcd, struct qib_pportdata *ppd, 313 u32 ctxt, u32 eflags, u32 l, u32 etail, 314 __le32 *rhf_addr, struct qib_message_header *rhdr) 315 { 316 u32 ret = 0; 317 318 if (eflags & (QLOGIC_IB_RHF_H_ICRCERR | QLOGIC_IB_RHF_H_VCRCERR)) 319 ret = 1; 320 else if (eflags == QLOGIC_IB_RHF_H_TIDERR) { 321 /* For TIDERR and RC QPs premptively schedule a NAK */ 322 struct ib_header *hdr = (struct ib_header *)rhdr; 323 struct ib_other_headers *ohdr = NULL; 324 struct qib_ibport *ibp = &ppd->ibport_data; 325 struct qib_devdata *dd = ppd->dd; 326 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi; 327 struct rvt_qp *qp = NULL; 328 u32 tlen = qib_hdrget_length_in_bytes(rhf_addr); 329 u16 lid = be16_to_cpu(hdr->lrh[1]); 330 int lnh = be16_to_cpu(hdr->lrh[0]) & 3; 331 u32 qp_num; 332 u32 opcode; 333 u32 psn; 334 int diff; 335 336 /* Sanity check packet */ 337 if (tlen < 24) 338 goto drop; 339 340 if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) { 341 lid &= ~((1 << ppd->lmc) - 1); 342 if (unlikely(lid != ppd->lid)) 343 goto drop; 344 } 345 346 /* Check for GRH */ 347 if (lnh == QIB_LRH_BTH) 348 ohdr = &hdr->u.oth; 349 else if (lnh == QIB_LRH_GRH) { 350 u32 vtf; 351 352 ohdr = &hdr->u.l.oth; 353 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR) 354 goto drop; 355 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow); 356 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION) 357 goto drop; 358 } else 359 goto drop; 360 361 /* Get opcode and PSN from packet */ 362 opcode = be32_to_cpu(ohdr->bth[0]); 363 opcode >>= 24; 364 psn = be32_to_cpu(ohdr->bth[2]); 365 366 /* Get the destination QP number. */ 367 qp_num = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK; 368 if (qp_num != QIB_MULTICAST_QPN) { 369 int ruc_res; 370 371 rcu_read_lock(); 372 qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num); 373 if (!qp) { 374 rcu_read_unlock(); 375 goto drop; 376 } 377 378 /* 379 * Handle only RC QPs - for other QP types drop error 380 * packet. 381 */ 382 spin_lock(&qp->r_lock); 383 384 /* Check for valid receive state. */ 385 if (!(ib_rvt_state_ops[qp->state] & 386 RVT_PROCESS_RECV_OK)) { 387 ibp->rvp.n_pkt_drops++; 388 goto unlock; 389 } 390 391 switch (qp->ibqp.qp_type) { 392 case IB_QPT_RC: 393 ruc_res = 394 qib_ruc_check_hdr( 395 ibp, hdr, 396 lnh == QIB_LRH_GRH, 397 qp, 398 be32_to_cpu(ohdr->bth[0])); 399 if (ruc_res) 400 goto unlock; 401 402 /* Only deal with RDMA Writes for now */ 403 if (opcode < 404 IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) { 405 diff = qib_cmp24(psn, qp->r_psn); 406 if (!qp->r_nak_state && diff >= 0) { 407 ibp->rvp.n_rc_seqnak++; 408 qp->r_nak_state = 409 IB_NAK_PSN_ERROR; 410 /* Use the expected PSN. */ 411 qp->r_ack_psn = qp->r_psn; 412 /* 413 * Wait to send the sequence 414 * NAK until all packets 415 * in the receive queue have 416 * been processed. 417 * Otherwise, we end up 418 * propagating congestion. 419 */ 420 if (list_empty(&qp->rspwait)) { 421 qp->r_flags |= 422 RVT_R_RSP_NAK; 423 rvt_get_qp(qp); 424 list_add_tail( 425 &qp->rspwait, 426 &rcd->qp_wait_list); 427 } 428 } /* Out of sequence NAK */ 429 } /* QP Request NAKs */ 430 break; 431 case IB_QPT_SMI: 432 case IB_QPT_GSI: 433 case IB_QPT_UD: 434 case IB_QPT_UC: 435 default: 436 /* For now don't handle any other QP types */ 437 break; 438 } 439 440 unlock: 441 spin_unlock(&qp->r_lock); 442 rcu_read_unlock(); 443 } /* Unicast QP */ 444 } /* Valid packet with TIDErr */ 445 446 drop: 447 return ret; 448 } 449 450 /* 451 * qib_kreceive - receive a packet 452 * @rcd: the qlogic_ib context 453 * @llic: gets count of good packets needed to clear lli, 454 * (used with chips that need need to track crcs for lli) 455 * 456 * called from interrupt handler for errors or receive interrupt 457 * Returns number of CRC error packets, needed by some chips for 458 * local link integrity tracking. crcs are adjusted down by following 459 * good packets, if any, and count of good packets is also tracked. 460 */ 461 u32 qib_kreceive(struct qib_ctxtdata *rcd, u32 *llic, u32 *npkts) 462 { 463 struct qib_devdata *dd = rcd->dd; 464 struct qib_pportdata *ppd = rcd->ppd; 465 __le32 *rhf_addr; 466 void *ebuf; 467 const u32 rsize = dd->rcvhdrentsize; /* words */ 468 const u32 maxcnt = dd->rcvhdrcnt * rsize; /* words */ 469 u32 etail = -1, l, hdrqtail; 470 struct qib_message_header *hdr; 471 u32 eflags, etype, tlen, i = 0, updegr = 0, crcs = 0; 472 int last; 473 u64 lval; 474 struct rvt_qp *qp, *nqp; 475 476 l = rcd->head; 477 rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; 478 if (dd->flags & QIB_NODMA_RTAIL) { 479 u32 seq = qib_hdrget_seq(rhf_addr); 480 481 if (seq != rcd->seq_cnt) 482 goto bail; 483 hdrqtail = 0; 484 } else { 485 hdrqtail = qib_get_rcvhdrtail(rcd); 486 if (l == hdrqtail) 487 goto bail; 488 smp_rmb(); /* prevent speculative reads of dma'ed hdrq */ 489 } 490 491 for (last = 0, i = 1; !last; i += !last) { 492 hdr = dd->f_get_msgheader(dd, rhf_addr); 493 eflags = qib_hdrget_err_flags(rhf_addr); 494 etype = qib_hdrget_rcv_type(rhf_addr); 495 /* total length */ 496 tlen = qib_hdrget_length_in_bytes(rhf_addr); 497 ebuf = NULL; 498 if ((dd->flags & QIB_NODMA_RTAIL) ? 499 qib_hdrget_use_egr_buf(rhf_addr) : 500 (etype != RCVHQ_RCV_TYPE_EXPECTED)) { 501 etail = qib_hdrget_index(rhf_addr); 502 updegr = 1; 503 if (tlen > sizeof(*hdr) || 504 etype >= RCVHQ_RCV_TYPE_NON_KD) { 505 ebuf = qib_get_egrbuf(rcd, etail); 506 prefetch_range(ebuf, tlen - sizeof(*hdr)); 507 } 508 } 509 if (!eflags) { 510 u16 lrh_len = be16_to_cpu(hdr->lrh[2]) << 2; 511 512 if (lrh_len != tlen) { 513 qib_stats.sps_lenerrs++; 514 goto move_along; 515 } 516 } 517 if (etype == RCVHQ_RCV_TYPE_NON_KD && !eflags && 518 ebuf == NULL && 519 tlen > (dd->rcvhdrentsize - 2 + 1 - 520 qib_hdrget_offset(rhf_addr)) << 2) { 521 goto move_along; 522 } 523 524 /* 525 * Both tiderr and qibhdrerr are set for all plain IB 526 * packets; only qibhdrerr should be set. 527 */ 528 if (unlikely(eflags)) 529 crcs += qib_rcv_hdrerr(rcd, ppd, rcd->ctxt, eflags, l, 530 etail, rhf_addr, hdr); 531 else if (etype == RCVHQ_RCV_TYPE_NON_KD) { 532 qib_ib_rcv(rcd, hdr, ebuf, tlen); 533 if (crcs) 534 crcs--; 535 else if (llic && *llic) 536 --*llic; 537 } 538 move_along: 539 l += rsize; 540 if (l >= maxcnt) 541 l = 0; 542 if (i == QIB_MAX_PKT_RECV) 543 last = 1; 544 545 rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; 546 if (dd->flags & QIB_NODMA_RTAIL) { 547 u32 seq = qib_hdrget_seq(rhf_addr); 548 549 if (++rcd->seq_cnt > 13) 550 rcd->seq_cnt = 1; 551 if (seq != rcd->seq_cnt) 552 last = 1; 553 } else if (l == hdrqtail) 554 last = 1; 555 /* 556 * Update head regs etc., every 16 packets, if not last pkt, 557 * to help prevent rcvhdrq overflows, when many packets 558 * are processed and queue is nearly full. 559 * Don't request an interrupt for intermediate updates. 560 */ 561 lval = l; 562 if (!last && !(i & 0xf)) { 563 dd->f_update_usrhead(rcd, lval, updegr, etail, i); 564 updegr = 0; 565 } 566 } 567 568 rcd->head = l; 569 570 /* 571 * Iterate over all QPs waiting to respond. 572 * The list won't change since the IRQ is only run on one CPU. 573 */ 574 list_for_each_entry_safe(qp, nqp, &rcd->qp_wait_list, rspwait) { 575 list_del_init(&qp->rspwait); 576 if (qp->r_flags & RVT_R_RSP_NAK) { 577 qp->r_flags &= ~RVT_R_RSP_NAK; 578 qib_send_rc_ack(qp); 579 } 580 if (qp->r_flags & RVT_R_RSP_SEND) { 581 unsigned long flags; 582 583 qp->r_flags &= ~RVT_R_RSP_SEND; 584 spin_lock_irqsave(&qp->s_lock, flags); 585 if (ib_rvt_state_ops[qp->state] & 586 RVT_PROCESS_OR_FLUSH_SEND) 587 qib_schedule_send(qp); 588 spin_unlock_irqrestore(&qp->s_lock, flags); 589 } 590 rvt_put_qp(qp); 591 } 592 593 bail: 594 /* Report number of packets consumed */ 595 if (npkts) 596 *npkts = i; 597 598 /* 599 * Always write head at end, and setup rcv interrupt, even 600 * if no packets were processed. 601 */ 602 lval = (u64)rcd->head | dd->rhdrhead_intr_off; 603 dd->f_update_usrhead(rcd, lval, updegr, etail, i); 604 return crcs; 605 } 606 607 /** 608 * qib_set_mtu - set the MTU 609 * @ppd: the perport data 610 * @arg: the new MTU 611 * 612 * We can handle "any" incoming size, the issue here is whether we 613 * need to restrict our outgoing size. For now, we don't do any 614 * sanity checking on this, and we don't deal with what happens to 615 * programs that are already running when the size changes. 616 * NOTE: changing the MTU will usually cause the IBC to go back to 617 * link INIT state... 618 */ 619 int qib_set_mtu(struct qib_pportdata *ppd, u16 arg) 620 { 621 u32 piosize; 622 int ret, chk; 623 624 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 && 625 arg != 4096) { 626 ret = -EINVAL; 627 goto bail; 628 } 629 chk = ib_mtu_enum_to_int(qib_ibmtu); 630 if (chk > 0 && arg > chk) { 631 ret = -EINVAL; 632 goto bail; 633 } 634 635 piosize = ppd->ibmaxlen; 636 ppd->ibmtu = arg; 637 638 if (arg >= (piosize - QIB_PIO_MAXIBHDR)) { 639 /* Only if it's not the initial value (or reset to it) */ 640 if (piosize != ppd->init_ibmaxlen) { 641 if (arg > piosize && arg <= ppd->init_ibmaxlen) 642 piosize = ppd->init_ibmaxlen - 2 * sizeof(u32); 643 ppd->ibmaxlen = piosize; 644 } 645 } else if ((arg + QIB_PIO_MAXIBHDR) != ppd->ibmaxlen) { 646 piosize = arg + QIB_PIO_MAXIBHDR - 2 * sizeof(u32); 647 ppd->ibmaxlen = piosize; 648 } 649 650 ppd->dd->f_set_ib_cfg(ppd, QIB_IB_CFG_MTU, 0); 651 652 ret = 0; 653 654 bail: 655 return ret; 656 } 657 658 int qib_set_lid(struct qib_pportdata *ppd, u32 lid, u8 lmc) 659 { 660 struct qib_devdata *dd = ppd->dd; 661 662 ppd->lid = lid; 663 ppd->lmc = lmc; 664 665 dd->f_set_ib_cfg(ppd, QIB_IB_CFG_LIDLMC, 666 lid | (~((1U << lmc) - 1)) << 16); 667 668 qib_devinfo(dd->pcidev, "IB%u:%u got a lid: 0x%x\n", 669 dd->unit, ppd->port, lid); 670 671 return 0; 672 } 673 674 /* 675 * Following deal with the "obviously simple" task of overriding the state 676 * of the LEDS, which normally indicate link physical and logical status. 677 * The complications arise in dealing with different hardware mappings 678 * and the board-dependent routine being called from interrupts. 679 * and then there's the requirement to _flash_ them. 680 */ 681 #define LED_OVER_FREQ_SHIFT 8 682 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT) 683 /* Below is "non-zero" to force override, but both actual LEDs are off */ 684 #define LED_OVER_BOTH_OFF (8) 685 686 static void qib_run_led_override(unsigned long opaque) 687 { 688 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 689 struct qib_devdata *dd = ppd->dd; 690 int timeoff; 691 int ph_idx; 692 693 if (!(dd->flags & QIB_INITTED)) 694 return; 695 696 ph_idx = ppd->led_override_phase++ & 1; 697 ppd->led_override = ppd->led_override_vals[ph_idx]; 698 timeoff = ppd->led_override_timeoff; 699 700 dd->f_setextled(ppd, 1); 701 /* 702 * don't re-fire the timer if user asked for it to be off; we let 703 * it fire one more time after they turn it off to simplify 704 */ 705 if (ppd->led_override_vals[0] || ppd->led_override_vals[1]) 706 mod_timer(&ppd->led_override_timer, jiffies + timeoff); 707 } 708 709 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val) 710 { 711 struct qib_devdata *dd = ppd->dd; 712 int timeoff, freq; 713 714 if (!(dd->flags & QIB_INITTED)) 715 return; 716 717 /* First check if we are blinking. If not, use 1HZ polling */ 718 timeoff = HZ; 719 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT; 720 721 if (freq) { 722 /* For blink, set each phase from one nybble of val */ 723 ppd->led_override_vals[0] = val & 0xF; 724 ppd->led_override_vals[1] = (val >> 4) & 0xF; 725 timeoff = (HZ << 4)/freq; 726 } else { 727 /* Non-blink set both phases the same. */ 728 ppd->led_override_vals[0] = val & 0xF; 729 ppd->led_override_vals[1] = val & 0xF; 730 } 731 ppd->led_override_timeoff = timeoff; 732 733 /* 734 * If the timer has not already been started, do so. Use a "quick" 735 * timeout so the function will be called soon, to look at our request. 736 */ 737 if (atomic_inc_return(&ppd->led_override_timer_active) == 1) { 738 /* Need to start timer */ 739 init_timer(&ppd->led_override_timer); 740 ppd->led_override_timer.function = qib_run_led_override; 741 ppd->led_override_timer.data = (unsigned long) ppd; 742 ppd->led_override_timer.expires = jiffies + 1; 743 add_timer(&ppd->led_override_timer); 744 } else { 745 if (ppd->led_override_vals[0] || ppd->led_override_vals[1]) 746 mod_timer(&ppd->led_override_timer, jiffies + 1); 747 atomic_dec(&ppd->led_override_timer_active); 748 } 749 } 750 751 /** 752 * qib_reset_device - reset the chip if possible 753 * @unit: the device to reset 754 * 755 * Whether or not reset is successful, we attempt to re-initialize the chip 756 * (that is, much like a driver unload/reload). We clear the INITTED flag 757 * so that the various entry points will fail until we reinitialize. For 758 * now, we only allow this if no user contexts are open that use chip resources 759 */ 760 int qib_reset_device(int unit) 761 { 762 int ret, i; 763 struct qib_devdata *dd = qib_lookup(unit); 764 struct qib_pportdata *ppd; 765 unsigned long flags; 766 int pidx; 767 768 if (!dd) { 769 ret = -ENODEV; 770 goto bail; 771 } 772 773 qib_devinfo(dd->pcidev, "Reset on unit %u requested\n", unit); 774 775 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) { 776 qib_devinfo(dd->pcidev, 777 "Invalid unit number %u or not initialized or not present\n", 778 unit); 779 ret = -ENXIO; 780 goto bail; 781 } 782 783 spin_lock_irqsave(&dd->uctxt_lock, flags); 784 if (dd->rcd) 785 for (i = dd->first_user_ctxt; i < dd->cfgctxts; i++) { 786 if (!dd->rcd[i] || !dd->rcd[i]->cnt) 787 continue; 788 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 789 ret = -EBUSY; 790 goto bail; 791 } 792 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 793 794 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 795 ppd = dd->pport + pidx; 796 if (atomic_read(&ppd->led_override_timer_active)) { 797 /* Need to stop LED timer, _then_ shut off LEDs */ 798 del_timer_sync(&ppd->led_override_timer); 799 atomic_set(&ppd->led_override_timer_active, 0); 800 } 801 802 /* Shut off LEDs after we are sure timer is not running */ 803 ppd->led_override = LED_OVER_BOTH_OFF; 804 dd->f_setextled(ppd, 0); 805 if (dd->flags & QIB_HAS_SEND_DMA) 806 qib_teardown_sdma(ppd); 807 } 808 809 ret = dd->f_reset(dd); 810 if (ret == 1) 811 ret = qib_init(dd, 1); 812 else 813 ret = -EAGAIN; 814 if (ret) 815 qib_dev_err(dd, 816 "Reinitialize unit %u after reset failed with %d\n", 817 unit, ret); 818 else 819 qib_devinfo(dd->pcidev, 820 "Reinitialized unit %u after resetting\n", 821 unit); 822 823 bail: 824 return ret; 825 } 826