1 #ifndef _QIB_KERNEL_H 2 #define _QIB_KERNEL_H 3 /* 4 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation. 5 * All rights reserved. 6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 /* 38 * This header file is the base header file for qlogic_ib kernel code 39 * qib_user.h serves a similar purpose for user code. 40 */ 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/mutex.h> 46 #include <linux/list.h> 47 #include <linux/scatterlist.h> 48 #include <linux/slab.h> 49 #include <linux/io.h> 50 #include <linux/fs.h> 51 #include <linux/completion.h> 52 #include <linux/kref.h> 53 #include <linux/sched.h> 54 55 #include "qib_common.h" 56 #include "qib_verbs.h" 57 58 /* only s/w major version of QLogic_IB we can handle */ 59 #define QIB_CHIP_VERS_MAJ 2U 60 61 /* don't care about this except printing */ 62 #define QIB_CHIP_VERS_MIN 0U 63 64 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 65 #define QIB_OUI 0x001175 66 #define QIB_OUI_LSB 40 67 68 /* 69 * per driver stats, either not device nor port-specific, or 70 * summed over all of the devices and ports. 71 * They are described by name via ipathfs filesystem, so layout 72 * and number of elements can change without breaking compatibility. 73 * If members are added or deleted qib_statnames[] in qib_fs.c must 74 * change to match. 75 */ 76 struct qlogic_ib_stats { 77 __u64 sps_ints; /* number of interrupts handled */ 78 __u64 sps_errints; /* number of error interrupts */ 79 __u64 sps_txerrs; /* tx-related packet errors */ 80 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 81 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 82 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 83 __u64 sps_ctxts; /* number of contexts currently open */ 84 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 85 __u64 sps_buffull; 86 __u64 sps_hdrfull; 87 }; 88 89 extern struct qlogic_ib_stats qib_stats; 90 extern struct pci_error_handlers qib_pci_err_handler; 91 extern struct pci_driver qib_driver; 92 93 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ 94 /* 95 * First-cut critierion for "device is active" is 96 * two thousand dwords combined Tx, Rx traffic per 97 * 5-second interval. SMA packets are 64 dwords, 98 * and occur "a few per second", presumably each way. 99 */ 100 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 101 102 /* 103 * Struct used to indicate which errors are logged in each of the 104 * error-counters that are logged to EEPROM. A counter is incremented 105 * _once_ (saturating at 255) for each event with any bits set in 106 * the error or hwerror register masks below. 107 */ 108 #define QIB_EEP_LOG_CNT (4) 109 struct qib_eep_log_mask { 110 u64 errs_to_log; 111 u64 hwerrs_to_log; 112 }; 113 114 /* 115 * Below contains all data related to a single context (formerly called port). 116 */ 117 struct qib_ctxtdata { 118 void **rcvegrbuf; 119 dma_addr_t *rcvegrbuf_phys; 120 /* rcvhdrq base, needs mmap before useful */ 121 void *rcvhdrq; 122 /* kernel virtual address where hdrqtail is updated */ 123 void *rcvhdrtail_kvaddr; 124 /* 125 * temp buffer for expected send setup, allocated at open, instead 126 * of each setup call 127 */ 128 void *tid_pg_list; 129 /* 130 * Shared page for kernel to signal user processes that send buffers 131 * need disarming. The process should call QIB_CMD_DISARM_BUFS 132 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 133 */ 134 unsigned long *user_event_mask; 135 /* when waiting for rcv or pioavail */ 136 wait_queue_head_t wait; 137 /* 138 * rcvegr bufs base, physical, must fit 139 * in 44 bits so 32 bit programs mmap64 44 bit works) 140 */ 141 dma_addr_t rcvegr_phys; 142 /* mmap of hdrq, must fit in 44 bits */ 143 dma_addr_t rcvhdrq_phys; 144 dma_addr_t rcvhdrqtailaddr_phys; 145 146 /* 147 * number of opens (including slave sub-contexts) on this instance 148 * (ignoring forks, dup, etc. for now) 149 */ 150 int cnt; 151 /* 152 * how much space to leave at start of eager TID entries for 153 * protocol use, on each TID 154 */ 155 /* instead of calculating it */ 156 unsigned ctxt; 157 /* non-zero if ctxt is being shared. */ 158 u16 subctxt_cnt; 159 /* non-zero if ctxt is being shared. */ 160 u16 subctxt_id; 161 /* number of eager TID entries. */ 162 u16 rcvegrcnt; 163 /* index of first eager TID entry. */ 164 u16 rcvegr_tid_base; 165 /* number of pio bufs for this ctxt (all procs, if shared) */ 166 u32 piocnt; 167 /* first pio buffer for this ctxt */ 168 u32 pio_base; 169 /* chip offset of PIO buffers for this ctxt */ 170 u32 piobufs; 171 /* how many alloc_pages() chunks in rcvegrbuf_pages */ 172 u32 rcvegrbuf_chunks; 173 /* how many egrbufs per chunk */ 174 u16 rcvegrbufs_perchunk; 175 /* ilog2 of above */ 176 u16 rcvegrbufs_perchunk_shift; 177 /* order for rcvegrbuf_pages */ 178 size_t rcvegrbuf_size; 179 /* rcvhdrq size (for freeing) */ 180 size_t rcvhdrq_size; 181 /* per-context flags for fileops/intr communication */ 182 unsigned long flag; 183 /* next expected TID to check when looking for free */ 184 u32 tidcursor; 185 /* WAIT_RCV that timed out, no interrupt */ 186 u32 rcvwait_to; 187 /* WAIT_PIO that timed out, no interrupt */ 188 u32 piowait_to; 189 /* WAIT_RCV already happened, no wait */ 190 u32 rcvnowait; 191 /* WAIT_PIO already happened, no wait */ 192 u32 pionowait; 193 /* total number of polled urgent packets */ 194 u32 urgent; 195 /* saved total number of polled urgent packets for poll edge trigger */ 196 u32 urgent_poll; 197 /* pid of process using this ctxt */ 198 pid_t pid; 199 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT]; 200 /* same size as task_struct .comm[], command that opened context */ 201 char comm[16]; 202 /* pkeys set by this use of this ctxt */ 203 u16 pkeys[4]; 204 /* so file ops can get at unit */ 205 struct qib_devdata *dd; 206 /* so funcs that need physical port can get it easily */ 207 struct qib_pportdata *ppd; 208 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 209 void *subctxt_uregbase; 210 /* An array of pages for the eager receive buffers * N */ 211 void *subctxt_rcvegrbuf; 212 /* An array of pages for the eager header queue entries * N */ 213 void *subctxt_rcvhdr_base; 214 /* The version of the library which opened this ctxt */ 215 u32 userversion; 216 /* Bitmask of active slaves */ 217 u32 active_slaves; 218 /* Type of packets or conditions we want to poll for */ 219 u16 poll_type; 220 /* receive packet sequence counter */ 221 u8 seq_cnt; 222 u8 redirect_seq_cnt; 223 /* ctxt rcvhdrq head offset */ 224 u32 head; 225 u32 pkt_count; 226 /* lookaside fields */ 227 struct qib_qp *lookaside_qp; 228 u32 lookaside_qpn; 229 /* QPs waiting for context processing */ 230 struct list_head qp_wait_list; 231 }; 232 233 struct qib_sge_state; 234 235 struct qib_sdma_txreq { 236 int flags; 237 int sg_count; 238 dma_addr_t addr; 239 void (*callback)(struct qib_sdma_txreq *, int); 240 u16 start_idx; /* sdma private */ 241 u16 next_descq_idx; /* sdma private */ 242 struct list_head list; /* sdma private */ 243 }; 244 245 struct qib_sdma_desc { 246 __le64 qw[2]; 247 }; 248 249 struct qib_verbs_txreq { 250 struct qib_sdma_txreq txreq; 251 struct qib_qp *qp; 252 struct qib_swqe *wqe; 253 u32 dwords; 254 u16 hdr_dwords; 255 u16 hdr_inx; 256 struct qib_pio_header *align_buf; 257 struct qib_mregion *mr; 258 struct qib_sge_state *ss; 259 }; 260 261 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1 262 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2 263 #define QIB_SDMA_TXREQ_F_INTREQ 0x4 264 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8 265 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10 266 267 #define QIB_SDMA_TXREQ_S_OK 0 268 #define QIB_SDMA_TXREQ_S_SENDERROR 1 269 #define QIB_SDMA_TXREQ_S_ABORTED 2 270 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3 271 272 /* 273 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 274 * Mostly for MADs that set or query link parameters, also ipath 275 * config interfaces 276 */ 277 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 278 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 279 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */ 280 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 281 #define QIB_IB_CFG_SPD 5 /* current Link spd */ 282 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 283 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 284 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 285 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 286 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */ 287 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 288 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 289 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 290 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 291 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 292 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */ 293 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */ 294 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */ 295 #define QIB_IB_CFG_VL_HIGH_LIMIT 19 296 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 297 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */ 298 299 /* 300 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16 301 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for 302 * QIB_IB_CFG_LINKDEFAULT cmd 303 */ 304 #define IB_LINKCMD_DOWN (0 << 16) 305 #define IB_LINKCMD_ARMED (1 << 16) 306 #define IB_LINKCMD_ACTIVE (2 << 16) 307 #define IB_LINKINITCMD_NOP 0 308 #define IB_LINKINITCMD_POLL 1 309 #define IB_LINKINITCMD_SLEEP 2 310 #define IB_LINKINITCMD_DISABLE 3 311 312 /* 313 * valid states passed to qib_set_linkstate() user call 314 */ 315 #define QIB_IB_LINKDOWN 0 316 #define QIB_IB_LINKARM 1 317 #define QIB_IB_LINKACTIVE 2 318 #define QIB_IB_LINKDOWN_ONLY 3 319 #define QIB_IB_LINKDOWN_SLEEP 4 320 #define QIB_IB_LINKDOWN_DISABLE 5 321 322 /* 323 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed 324 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg 325 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They 326 * are also the the possible values for qib_link_speed_enabled and active 327 * The values were chosen to match values used within the IB spec. 328 */ 329 #define QIB_IB_SDR 1 330 #define QIB_IB_DDR 2 331 #define QIB_IB_QDR 4 332 333 #define QIB_DEFAULT_MTU 4096 334 335 /* max number of IB ports supported per HCA */ 336 #define QIB_MAX_IB_PORTS 2 337 338 /* 339 * Possible IB config parameters for f_get/set_ib_table() 340 */ 341 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */ 342 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */ 343 344 /* 345 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 346 * these are bits so they can be combined, e.g. 347 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB 348 */ 349 #define QIB_RCVCTRL_TAILUPD_ENB 0x01 350 #define QIB_RCVCTRL_TAILUPD_DIS 0x02 351 #define QIB_RCVCTRL_CTXT_ENB 0x04 352 #define QIB_RCVCTRL_CTXT_DIS 0x08 353 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10 354 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20 355 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 356 #define QIB_RCVCTRL_PKEY_DIS 0x80 357 #define QIB_RCVCTRL_BP_ENB 0x0100 358 #define QIB_RCVCTRL_BP_DIS 0x0200 359 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400 360 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800 361 362 /* 363 * Possible "operations" for f_sendctrl(ppd, op, var) 364 * these are bits so they can be combined, e.g. 365 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB 366 * Some operations (e.g. DISARM, ABORT) are known to 367 * be "one-shot", so do not modify shadow. 368 */ 369 #define QIB_SENDCTRL_DISARM (0x1000) 370 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM) 371 /* available (0x2000) */ 372 #define QIB_SENDCTRL_AVAIL_DIS (0x4000) 373 #define QIB_SENDCTRL_AVAIL_ENB (0x8000) 374 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000) 375 #define QIB_SENDCTRL_SEND_DIS (0x20000) 376 #define QIB_SENDCTRL_SEND_ENB (0x40000) 377 #define QIB_SENDCTRL_FLUSH (0x80000) 378 #define QIB_SENDCTRL_CLEAR (0x100000) 379 #define QIB_SENDCTRL_DISARM_ALL (0x200000) 380 381 /* 382 * These are the generic indices for requesting per-port 383 * counter values via the f_portcntr function. They 384 * are always returned as 64 bit values, although most 385 * are 32 bit counters. 386 */ 387 /* send-related counters */ 388 #define QIBPORTCNTR_PKTSEND 0U 389 #define QIBPORTCNTR_WORDSEND 1U 390 #define QIBPORTCNTR_PSXMITDATA 2U 391 #define QIBPORTCNTR_PSXMITPKTS 3U 392 #define QIBPORTCNTR_PSXMITWAIT 4U 393 #define QIBPORTCNTR_SENDSTALL 5U 394 /* receive-related counters */ 395 #define QIBPORTCNTR_PKTRCV 6U 396 #define QIBPORTCNTR_PSRCVDATA 7U 397 #define QIBPORTCNTR_PSRCVPKTS 8U 398 #define QIBPORTCNTR_RCVEBP 9U 399 #define QIBPORTCNTR_RCVOVFL 10U 400 #define QIBPORTCNTR_WORDRCV 11U 401 /* IB link related error counters */ 402 #define QIBPORTCNTR_RXLOCALPHYERR 12U 403 #define QIBPORTCNTR_RXVLERR 13U 404 #define QIBPORTCNTR_ERRICRC 14U 405 #define QIBPORTCNTR_ERRVCRC 15U 406 #define QIBPORTCNTR_ERRLPCRC 16U 407 #define QIBPORTCNTR_BADFORMAT 17U 408 #define QIBPORTCNTR_ERR_RLEN 18U 409 #define QIBPORTCNTR_IBSYMBOLERR 19U 410 #define QIBPORTCNTR_INVALIDRLEN 20U 411 #define QIBPORTCNTR_UNSUPVL 21U 412 #define QIBPORTCNTR_EXCESSBUFOVFL 22U 413 #define QIBPORTCNTR_ERRLINK 23U 414 #define QIBPORTCNTR_IBLINKDOWN 24U 415 #define QIBPORTCNTR_IBLINKERRRECOV 25U 416 #define QIBPORTCNTR_LLI 26U 417 /* other error counters */ 418 #define QIBPORTCNTR_RXDROPPKT 27U 419 #define QIBPORTCNTR_VL15PKTDROP 28U 420 #define QIBPORTCNTR_ERRPKEY 29U 421 #define QIBPORTCNTR_KHDROVFL 30U 422 /* sampling counters (these are actually control registers) */ 423 #define QIBPORTCNTR_PSINTERVAL 31U 424 #define QIBPORTCNTR_PSSTART 32U 425 #define QIBPORTCNTR_PSSTAT 33U 426 427 /* how often we check for packet activity for "power on hours (in seconds) */ 428 #define ACTIVITY_TIMER 5 429 430 /* Below is an opaque struct. Each chip (device) can maintain 431 * private data needed for its operation, but not germane to the 432 * rest of the driver. For convenience, we define another that 433 * is chip-specific, per-port 434 */ 435 struct qib_chip_specific; 436 struct qib_chipport_specific; 437 438 enum qib_sdma_states { 439 qib_sdma_state_s00_hw_down, 440 qib_sdma_state_s10_hw_start_up_wait, 441 qib_sdma_state_s20_idle, 442 qib_sdma_state_s30_sw_clean_up_wait, 443 qib_sdma_state_s40_hw_clean_up_wait, 444 qib_sdma_state_s50_hw_halt_wait, 445 qib_sdma_state_s99_running, 446 }; 447 448 enum qib_sdma_events { 449 qib_sdma_event_e00_go_hw_down, 450 qib_sdma_event_e10_go_hw_start, 451 qib_sdma_event_e20_hw_started, 452 qib_sdma_event_e30_go_running, 453 qib_sdma_event_e40_sw_cleaned, 454 qib_sdma_event_e50_hw_cleaned, 455 qib_sdma_event_e60_hw_halted, 456 qib_sdma_event_e70_go_idle, 457 qib_sdma_event_e7220_err_halted, 458 qib_sdma_event_e7322_err_halted, 459 qib_sdma_event_e90_timer_tick, 460 }; 461 462 extern char *qib_sdma_state_names[]; 463 extern char *qib_sdma_event_names[]; 464 465 struct sdma_set_state_action { 466 unsigned op_enable:1; 467 unsigned op_intenable:1; 468 unsigned op_halt:1; 469 unsigned op_drain:1; 470 unsigned go_s99_running_tofalse:1; 471 unsigned go_s99_running_totrue:1; 472 }; 473 474 struct qib_sdma_state { 475 struct kref kref; 476 struct completion comp; 477 enum qib_sdma_states current_state; 478 struct sdma_set_state_action *set_state_action; 479 unsigned current_op; 480 unsigned go_s99_running; 481 unsigned first_sendbuf; 482 unsigned last_sendbuf; /* really last +1 */ 483 /* debugging/devel */ 484 enum qib_sdma_states previous_state; 485 unsigned previous_op; 486 enum qib_sdma_events last_event; 487 }; 488 489 struct xmit_wait { 490 struct timer_list timer; 491 u64 counter; 492 u8 flags; 493 struct cache { 494 u64 psxmitdata; 495 u64 psrcvdata; 496 u64 psxmitpkts; 497 u64 psrcvpkts; 498 u64 psxmitwait; 499 } counter_cache; 500 }; 501 502 /* 503 * The structure below encapsulates data relevant to a physical IB Port. 504 * Current chips support only one such port, but the separation 505 * clarifies things a bit. Note that to conform to IB conventions, 506 * port-numbers are one-based. The first or only port is port1. 507 */ 508 struct qib_pportdata { 509 struct qib_ibport ibport_data; 510 511 struct qib_devdata *dd; 512 struct qib_chippport_specific *cpspec; /* chip-specific per-port */ 513 struct kobject pport_kobj; 514 struct kobject sl2vl_kobj; 515 struct kobject diagc_kobj; 516 517 /* GUID for this interface, in network order */ 518 __be64 guid; 519 520 /* QIB_POLL, etc. link-state specific flags, per port */ 521 u32 lflags; 522 /* qib_lflags driver is waiting for */ 523 u32 state_wanted; 524 spinlock_t lflags_lock; 525 /* number of (port-specific) interrupts for this port -- saturates... */ 526 u32 int_counter; 527 528 /* ref count for each pkey */ 529 atomic_t pkeyrefs[4]; 530 531 /* 532 * this address is mapped readonly into user processes so they can 533 * get status cheaply, whenever they want. One qword of status per port 534 */ 535 u64 *statusp; 536 537 /* SendDMA related entries */ 538 spinlock_t sdma_lock; 539 struct qib_sdma_state sdma_state; 540 unsigned long sdma_buf_jiffies; 541 struct qib_sdma_desc *sdma_descq; 542 u64 sdma_descq_added; 543 u64 sdma_descq_removed; 544 u16 sdma_descq_cnt; 545 u16 sdma_descq_tail; 546 u16 sdma_descq_head; 547 u16 sdma_next_intr; 548 u16 sdma_reset_wait; 549 u8 sdma_generation; 550 struct tasklet_struct sdma_sw_clean_up_task; 551 struct list_head sdma_activelist; 552 553 dma_addr_t sdma_descq_phys; 554 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */ 555 dma_addr_t sdma_head_phys; 556 557 wait_queue_head_t state_wait; /* for state_wanted */ 558 559 /* HoL blocking for SMP replies */ 560 unsigned hol_state; 561 struct timer_list hol_timer; 562 563 /* 564 * Shadow copies of registers; size indicates read access size. 565 * Most of them are readonly, but some are write-only register, 566 * where we manipulate the bits in the shadow copy, and then write 567 * the shadow copy to qlogic_ib. 568 * 569 * We deliberately make most of these 32 bits, since they have 570 * restricted range. For any that we read, we won't to generate 32 571 * bit accesses, since Opteron will generate 2 separate 32 bit HT 572 * transactions for a 64 bit read, and we want to avoid unnecessary 573 * bus transactions. 574 */ 575 576 /* This is the 64 bit group */ 577 /* last ibcstatus. opaque outside chip-specific code */ 578 u64 lastibcstat; 579 580 /* these are the "32 bit" regs */ 581 582 /* 583 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 584 * all expect bit fields to be "unsigned long" 585 */ 586 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */ 587 unsigned long p_sendctrl; /* shadow per-port sendctrl */ 588 589 u32 ibmtu; /* The MTU programmed for this unit */ 590 /* 591 * Current max size IB packet (in bytes) including IB headers, that 592 * we can send. Changes when ibmtu changes. 593 */ 594 u32 ibmaxlen; 595 /* 596 * ibmaxlen at init time, limited by chip and by receive buffer 597 * size. Not changed after init. 598 */ 599 u32 init_ibmaxlen; 600 /* LID programmed for this instance */ 601 u16 lid; 602 /* list of pkeys programmed; 0 if not set */ 603 u16 pkeys[4]; 604 /* LID mask control */ 605 u8 lmc; 606 u8 link_width_supported; 607 u8 link_speed_supported; 608 u8 link_width_enabled; 609 u8 link_speed_enabled; 610 u8 link_width_active; 611 u8 link_speed_active; 612 u8 vls_supported; 613 u8 vls_operational; 614 /* Rx Polarity inversion (compensate for ~tx on partner) */ 615 u8 rx_pol_inv; 616 617 u8 hw_pidx; /* physical port index */ 618 u8 port; /* IB port number and index into dd->pports - 1 */ 619 620 u8 delay_mult; 621 622 /* used to override LED behavior */ 623 u8 led_override; /* Substituted for normal value, if non-zero */ 624 u16 led_override_timeoff; /* delta to next timer event */ 625 u8 led_override_vals[2]; /* Alternates per blink-frame */ 626 u8 led_override_phase; /* Just counts, LSB picks from vals[] */ 627 atomic_t led_override_timer_active; 628 /* Used to flash LEDs in override mode */ 629 struct timer_list led_override_timer; 630 struct xmit_wait cong_stats; 631 struct timer_list symerr_clear_timer; 632 }; 633 634 /* Observers. Not to be taken lightly, possibly not to ship. */ 635 /* 636 * If a diag read or write is to (bottom <= offset <= top), 637 * the "hoook" is called, allowing, e.g. shadows to be 638 * updated in sync with the driver. struct diag_observer 639 * is the "visible" part. 640 */ 641 struct diag_observer; 642 643 typedef int (*diag_hook) (struct qib_devdata *dd, 644 const struct diag_observer *op, 645 u32 offs, u64 *data, u64 mask, int only_32); 646 647 struct diag_observer { 648 diag_hook hook; 649 u32 bottom; 650 u32 top; 651 }; 652 653 extern int qib_register_observer(struct qib_devdata *dd, 654 const struct diag_observer *op); 655 656 /* Only declared here, not defined. Private to diags */ 657 struct diag_observer_list_elt; 658 659 /* device data struct now contains only "general per-device" info. 660 * fields related to a physical IB port are in a qib_pportdata struct, 661 * described above) while fields only used by a particular chip-type are in 662 * a qib_chipdata struct, whose contents are opaque to this file. 663 */ 664 struct qib_devdata { 665 struct qib_ibdev verbs_dev; /* must be first */ 666 struct list_head list; 667 /* pointers to related structs for this device */ 668 /* pci access data structure */ 669 struct pci_dev *pcidev; 670 struct cdev *user_cdev; 671 struct cdev *diag_cdev; 672 struct device *user_device; 673 struct device *diag_device; 674 675 /* mem-mapped pointer to base of chip regs */ 676 u64 __iomem *kregbase; 677 /* end of mem-mapped chip space excluding sendbuf and user regs */ 678 u64 __iomem *kregend; 679 /* physical address of chip for io_remap, etc. */ 680 resource_size_t physaddr; 681 /* qib_cfgctxts pointers */ 682 struct qib_ctxtdata **rcd; /* Receive Context Data */ 683 684 /* qib_pportdata, points to array of (physical) port-specific 685 * data structs, indexed by pidx (0..n-1) 686 */ 687 struct qib_pportdata *pport; 688 struct qib_chip_specific *cspec; /* chip-specific */ 689 690 /* kvirt address of 1st 2k pio buffer */ 691 void __iomem *pio2kbase; 692 /* kvirt address of 1st 4k pio buffer */ 693 void __iomem *pio4kbase; 694 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */ 695 void __iomem *piobase; 696 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */ 697 u64 __iomem *userbase; 698 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */ 699 /* 700 * points to area where PIOavail registers will be DMA'ed. 701 * Has to be on a page of it's own, because the page will be 702 * mapped into user program space. This copy is *ONLY* ever 703 * written by DMA, not by the driver! Need a copy per device 704 * when we get to multiple devices 705 */ 706 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */ 707 /* physical address where updates occur */ 708 dma_addr_t pioavailregs_phys; 709 710 /* device-specific implementations of functions needed by 711 * common code. Contrary to previous consensus, we can't 712 * really just point to a device-specific table, because we 713 * may need to "bend", e.g. *_f_put_tid 714 */ 715 /* fallback to alternate interrupt type if possible */ 716 int (*f_intr_fallback)(struct qib_devdata *); 717 /* hard reset chip */ 718 int (*f_reset)(struct qib_devdata *); 719 void (*f_quiet_serdes)(struct qib_pportdata *); 720 int (*f_bringup_serdes)(struct qib_pportdata *); 721 int (*f_early_init)(struct qib_devdata *); 722 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *); 723 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*, 724 u32, unsigned long); 725 void (*f_cleanup)(struct qib_devdata *); 726 void (*f_setextled)(struct qib_pportdata *, u32); 727 /* fill out chip-specific fields */ 728 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *); 729 /* free irq */ 730 void (*f_free_irq)(struct qib_devdata *); 731 struct qib_message_header *(*f_get_msgheader) 732 (struct qib_devdata *, __le32 *); 733 void (*f_config_ctxts)(struct qib_devdata *); 734 int (*f_get_ib_cfg)(struct qib_pportdata *, int); 735 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32); 736 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *); 737 int (*f_get_ib_table)(struct qib_pportdata *, int, void *); 738 int (*f_set_ib_table)(struct qib_pportdata *, int, void *); 739 u32 (*f_iblink_state)(u64); 740 u8 (*f_ibphys_portstate)(u64); 741 void (*f_xgxs_reset)(struct qib_pportdata *); 742 /* per chip actions needed for IB Link up/down changes */ 743 int (*f_ib_updown)(struct qib_pportdata *, int, u64); 744 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *); 745 /* Read/modify/write of GPIO pins (potentially chip-specific */ 746 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir, 747 u32 mask); 748 /* Enable writes to config EEPROM (if supported) */ 749 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen); 750 /* 751 * modify rcvctrl shadow[s] and write to appropriate chip-regs. 752 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations. 753 * (ctxt == -1) means "all contexts", only meaningful for 754 * clearing. Could remove if chip_spec shutdown properly done. 755 */ 756 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op, 757 int ctxt); 758 /* Read/modify/write sendctrl appropriately for op and port. */ 759 void (*f_sendctrl)(struct qib_pportdata *, u32 op); 760 void (*f_set_intr_state)(struct qib_devdata *, u32); 761 void (*f_set_armlaunch)(struct qib_devdata *, u32); 762 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32); 763 int (*f_late_initreg)(struct qib_devdata *); 764 int (*f_init_sdma_regs)(struct qib_pportdata *); 765 u16 (*f_sdma_gethead)(struct qib_pportdata *); 766 int (*f_sdma_busy)(struct qib_pportdata *); 767 void (*f_sdma_update_tail)(struct qib_pportdata *, u16); 768 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned); 769 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned); 770 void (*f_sdma_hw_clean_up)(struct qib_pportdata *); 771 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 772 void (*f_sdma_init_early)(struct qib_pportdata *); 773 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 774 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 775 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 776 u64 (*f_portcntr)(struct qib_pportdata *, u32); 777 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **, 778 u64 **); 779 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32, 780 char **, u64 **); 781 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8); 782 void (*f_initvl15_bufs)(struct qib_devdata *); 783 void (*f_init_ctxt)(struct qib_ctxtdata *); 784 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32, 785 struct qib_ctxtdata *); 786 void (*f_writescratch)(struct qib_devdata *, u32); 787 int (*f_tempsense_rd)(struct qib_devdata *, int regnum); 788 789 char *boardname; /* human readable board info */ 790 791 /* template for writing TIDs */ 792 u64 tidtemplate; 793 /* value to write to free TIDs */ 794 u64 tidinvalid; 795 796 /* number of registers used for pioavail */ 797 u32 pioavregs; 798 /* device (not port) flags, basically device capabilities */ 799 u32 flags; 800 /* last buffer for user use */ 801 u32 lastctxt_piobuf; 802 803 /* saturating counter of (non-port-specific) device interrupts */ 804 u32 int_counter; 805 806 /* pio bufs allocated per ctxt */ 807 u32 pbufsctxt; 808 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */ 809 u32 ctxts_extrabuf; 810 /* 811 * number of ctxts configured as max; zero is set to number chip 812 * supports, less gives more pio bufs/ctxt, etc. 813 */ 814 u32 cfgctxts; 815 /* 816 * number of ctxts available for PSM open 817 */ 818 u32 freectxts; 819 820 /* 821 * hint that we should update pioavailshadow before 822 * looking for a PIO buffer 823 */ 824 u32 upd_pio_shadow; 825 826 /* internal debugging stats */ 827 u32 maxpkts_call; 828 u32 avgpkts_call; 829 u64 nopiobufs; 830 831 /* PCI Vendor ID (here for NodeInfo) */ 832 u16 vendorid; 833 /* PCI Device ID (here for NodeInfo) */ 834 u16 deviceid; 835 /* for write combining settings */ 836 unsigned long wc_cookie; 837 unsigned long wc_base; 838 unsigned long wc_len; 839 840 /* shadow copy of struct page *'s for exp tid pages */ 841 struct page **pageshadow; 842 /* shadow copy of dma handles for exp tid pages */ 843 dma_addr_t *physshadow; 844 u64 __iomem *egrtidbase; 845 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */ 846 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 847 spinlock_t uctxt_lock; /* rcd and user context changes */ 848 /* 849 * per unit status, see also portdata statusp 850 * mapped readonly into user processes so they can get unit and 851 * IB link status cheaply 852 */ 853 u64 *devstatusp; 854 char *freezemsg; /* freeze msg if hw error put chip in freeze */ 855 u32 freezelen; /* max length of freezemsg */ 856 /* timer used to prevent stats overflow, error throttling, etc. */ 857 struct timer_list stats_timer; 858 859 /* timer to verify interrupts work, and fallback if possible */ 860 struct timer_list intrchk_timer; 861 unsigned long ureg_align; /* user register alignment */ 862 863 /* 864 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and 865 * pio_writing. 866 */ 867 spinlock_t pioavail_lock; 868 869 /* 870 * Shadow copies of registers; size indicates read access size. 871 * Most of them are readonly, but some are write-only register, 872 * where we manipulate the bits in the shadow copy, and then write 873 * the shadow copy to qlogic_ib. 874 * 875 * We deliberately make most of these 32 bits, since they have 876 * restricted range. For any that we read, we won't to generate 32 877 * bit accesses, since Opteron will generate 2 separate 32 bit HT 878 * transactions for a 64 bit read, and we want to avoid unnecessary 879 * bus transactions. 880 */ 881 882 /* This is the 64 bit group */ 883 884 unsigned long pioavailshadow[6]; 885 /* bitmap of send buffers available for the kernel to use with PIO. */ 886 unsigned long pioavailkernel[6]; 887 /* bitmap of send buffers which need to be disarmed. */ 888 unsigned long pio_need_disarm[3]; 889 /* bitmap of send buffers which are being written to. */ 890 unsigned long pio_writing[3]; 891 /* kr_revision shadow */ 892 u64 revision; 893 /* Base GUID for device (from eeprom, network order) */ 894 __be64 base_guid; 895 896 /* 897 * kr_sendpiobufbase value (chip offset of pio buffers), and the 898 * base of the 2KB buffer s(user processes only use 2K) 899 */ 900 u64 piobufbase; 901 u32 pio2k_bufbase; 902 903 /* these are the "32 bit" regs */ 904 905 /* number of GUIDs in the flash for this interface */ 906 u32 nguid; 907 /* 908 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 909 * all expect bit fields to be "unsigned long" 910 */ 911 unsigned long rcvctrl; /* shadow per device rcvctrl */ 912 unsigned long sendctrl; /* shadow per device sendctrl */ 913 914 /* value we put in kr_rcvhdrcnt */ 915 u32 rcvhdrcnt; 916 /* value we put in kr_rcvhdrsize */ 917 u32 rcvhdrsize; 918 /* value we put in kr_rcvhdrentsize */ 919 u32 rcvhdrentsize; 920 /* kr_ctxtcnt value */ 921 u32 ctxtcnt; 922 /* kr_pagealign value */ 923 u32 palign; 924 /* number of "2KB" PIO buffers */ 925 u32 piobcnt2k; 926 /* size in bytes of "2KB" PIO buffers */ 927 u32 piosize2k; 928 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */ 929 u32 piosize2kmax_dwords; 930 /* number of "4KB" PIO buffers */ 931 u32 piobcnt4k; 932 /* size in bytes of "4KB" PIO buffers */ 933 u32 piosize4k; 934 /* kr_rcvegrbase value */ 935 u32 rcvegrbase; 936 /* kr_rcvtidbase value */ 937 u32 rcvtidbase; 938 /* kr_rcvtidcnt value */ 939 u32 rcvtidcnt; 940 /* kr_userregbase */ 941 u32 uregbase; 942 /* shadow the control register contents */ 943 u32 control; 944 945 /* chip address space used by 4k pio buffers */ 946 u32 align4k; 947 /* size of each rcvegrbuffer */ 948 u16 rcvegrbufsize; 949 /* log2 of above */ 950 u16 rcvegrbufsize_shift; 951 /* localbus width (1, 2,4,8,16,32) from config space */ 952 u32 lbus_width; 953 /* localbus speed in MHz */ 954 u32 lbus_speed; 955 int unit; /* unit # of this chip */ 956 957 /* start of CHIP_SPEC move to chipspec, but need code changes */ 958 /* low and high portions of MSI capability/vector */ 959 u32 msi_lo; 960 /* saved after PCIe init for restore after reset */ 961 u32 msi_hi; 962 /* MSI data (vector) saved for restore */ 963 u16 msi_data; 964 /* so we can rewrite it after a chip reset */ 965 u32 pcibar0; 966 /* so we can rewrite it after a chip reset */ 967 u32 pcibar1; 968 u64 rhdrhead_intr_off; 969 970 /* 971 * ASCII serial number, from flash, large enough for original 972 * all digit strings, and longer QLogic serial number format 973 */ 974 u8 serial[16]; 975 /* human readable board version */ 976 u8 boardversion[96]; 977 u8 lbus_info[32]; /* human readable localbus info */ 978 /* chip major rev, from qib_revision */ 979 u8 majrev; 980 /* chip minor rev, from qib_revision */ 981 u8 minrev; 982 983 /* Misc small ints */ 984 /* Number of physical ports available */ 985 u8 num_pports; 986 /* Lowest context number which can be used by user processes */ 987 u8 first_user_ctxt; 988 u8 n_krcv_queues; 989 u8 qpn_mask; 990 u8 skip_kctxt_mask; 991 992 u16 rhf_offset; /* offset of RHF within receive header entry */ 993 994 /* 995 * GPIO pins for twsi-connected devices, and device code for eeprom 996 */ 997 u8 gpio_sda_num; 998 u8 gpio_scl_num; 999 u8 twsi_eeprom_dev; 1000 u8 board_atten; 1001 1002 /* Support (including locks) for EEPROM logging of errors and time */ 1003 /* control access to actual counters, timer */ 1004 spinlock_t eep_st_lock; 1005 /* control high-level access to EEPROM */ 1006 struct mutex eep_lock; 1007 uint64_t traffic_wds; 1008 /* active time is kept in seconds, but logged in hours */ 1009 atomic_t active_time; 1010 /* Below are nominal shadow of EEPROM, new since last EEPROM update */ 1011 uint8_t eep_st_errs[QIB_EEP_LOG_CNT]; 1012 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT]; 1013 uint16_t eep_hrs; 1014 /* 1015 * masks for which bits of errs, hwerrs that cause 1016 * each of the counters to increment. 1017 */ 1018 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT]; 1019 struct qib_diag_client *diag_client; 1020 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1021 struct diag_observer_list_elt *diag_observer_list; 1022 1023 u8 psxmitwait_supported; 1024 /* cycle length of PS* counters in HW (in picoseconds) */ 1025 u16 psxmitwait_check_rate; 1026 /* high volume overflow errors defered to tasklet */ 1027 struct tasklet_struct error_tasklet; 1028 }; 1029 1030 /* hol_state values */ 1031 #define QIB_HOL_UP 0 1032 #define QIB_HOL_INIT 1 1033 1034 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0) 1035 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1) 1036 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2) 1037 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3) 1038 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4) 1039 1040 /* operation types for f_txchk_change() */ 1041 #define TXCHK_CHG_TYPE_DIS1 3 1042 #define TXCHK_CHG_TYPE_ENAB1 2 1043 #define TXCHK_CHG_TYPE_KERN 1 1044 #define TXCHK_CHG_TYPE_USER 0 1045 1046 #define QIB_CHASE_TIME msecs_to_jiffies(145) 1047 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160) 1048 1049 /* Private data for file operations */ 1050 struct qib_filedata { 1051 struct qib_ctxtdata *rcd; 1052 unsigned subctxt; 1053 unsigned tidcursor; 1054 struct qib_user_sdma_queue *pq; 1055 int rec_cpu_num; /* for cpu affinity; -1 if none */ 1056 }; 1057 1058 extern struct list_head qib_dev_list; 1059 extern spinlock_t qib_devs_lock; 1060 extern struct qib_devdata *qib_lookup(int unit); 1061 extern u32 qib_cpulist_count; 1062 extern unsigned long *qib_cpulist; 1063 1064 extern unsigned qib_wc_pat; 1065 int qib_init(struct qib_devdata *, int); 1066 int init_chip_wc_pat(struct qib_devdata *dd, u32); 1067 int qib_enable_wc(struct qib_devdata *dd); 1068 void qib_disable_wc(struct qib_devdata *dd); 1069 int qib_count_units(int *npresentp, int *nupp); 1070 int qib_count_active_units(void); 1071 1072 int qib_cdev_init(int minor, const char *name, 1073 const struct file_operations *fops, 1074 struct cdev **cdevp, struct device **devp); 1075 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp); 1076 int qib_dev_init(void); 1077 void qib_dev_cleanup(void); 1078 1079 int qib_diag_add(struct qib_devdata *); 1080 void qib_diag_remove(struct qib_devdata *); 1081 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64); 1082 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */ 1083 1084 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err); 1085 void qib_bad_intrstatus(struct qib_devdata *); 1086 void qib_handle_urcv(struct qib_devdata *, u64); 1087 1088 /* clean up any per-chip chip-specific stuff */ 1089 void qib_chip_cleanup(struct qib_devdata *); 1090 /* clean up any chip type-specific stuff */ 1091 void qib_chip_done(void); 1092 1093 /* check to see if we have to force ordering for write combining */ 1094 int qib_unordered_wc(void); 1095 void qib_pio_copy(void __iomem *to, const void *from, size_t count); 1096 1097 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned); 1098 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *); 1099 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned); 1100 void qib_cancel_sends(struct qib_pportdata *); 1101 1102 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *); 1103 int qib_setup_eagerbufs(struct qib_ctxtdata *); 1104 void qib_set_ctxtcnt(struct qib_devdata *); 1105 int qib_create_ctxts(struct qib_devdata *dd); 1106 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32); 1107 void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8); 1108 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *); 1109 1110 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *); 1111 int qib_reset_device(int); 1112 int qib_wait_linkstate(struct qib_pportdata *, u32, int); 1113 int qib_set_linkstate(struct qib_pportdata *, u8); 1114 int qib_set_mtu(struct qib_pportdata *, u16); 1115 int qib_set_lid(struct qib_pportdata *, u32, u8); 1116 void qib_hol_down(struct qib_pportdata *); 1117 void qib_hol_init(struct qib_pportdata *); 1118 void qib_hol_up(struct qib_pportdata *); 1119 void qib_hol_event(unsigned long); 1120 void qib_disable_after_error(struct qib_devdata *); 1121 int qib_set_uevent_bits(struct qib_pportdata *, const int); 1122 1123 /* for use in system calls, where we want to know device type, etc. */ 1124 #define ctxt_fp(fp) \ 1125 (((struct qib_filedata *)(fp)->private_data)->rcd) 1126 #define subctxt_fp(fp) \ 1127 (((struct qib_filedata *)(fp)->private_data)->subctxt) 1128 #define tidcursor_fp(fp) \ 1129 (((struct qib_filedata *)(fp)->private_data)->tidcursor) 1130 #define user_sdma_queue_fp(fp) \ 1131 (((struct qib_filedata *)(fp)->private_data)->pq) 1132 1133 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd) 1134 { 1135 return ppd->dd; 1136 } 1137 1138 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev) 1139 { 1140 return container_of(dev, struct qib_devdata, verbs_dev); 1141 } 1142 1143 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev) 1144 { 1145 return dd_from_dev(to_idev(ibdev)); 1146 } 1147 1148 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp) 1149 { 1150 return container_of(ibp, struct qib_pportdata, ibport_data); 1151 } 1152 1153 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port) 1154 { 1155 struct qib_devdata *dd = dd_from_ibdev(ibdev); 1156 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1157 1158 WARN_ON(pidx >= dd->num_pports); 1159 return &dd->pport[pidx].ibport_data; 1160 } 1161 1162 /* 1163 * values for dd->flags (_device_ related flags) and 1164 */ 1165 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */ 1166 #define QIB_INITTED 0x2 /* chip and driver up and initted */ 1167 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */ 1168 #define QIB_PRESENT 0x8 /* chip accesses can be done */ 1169 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */ 1170 #define QIB_HAS_THRESH_UPDATE 0x40 1171 #define QIB_HAS_SDMA_TIMEOUT 0x80 1172 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */ 1173 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */ 1174 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */ 1175 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */ 1176 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */ 1177 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */ 1178 #define QIB_BADINTR 0x8000 /* severe interrupt problems */ 1179 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */ 1180 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */ 1181 1182 /* 1183 * values for ppd->lflags (_ib_port_ related flags) 1184 */ 1185 #define QIBL_LINKV 0x1 /* IB link state valid */ 1186 #define QIBL_LINKDOWN 0x8 /* IB link is down */ 1187 #define QIBL_LINKINIT 0x10 /* IB link level is up */ 1188 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */ 1189 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */ 1190 /* leave a gap for more IB-link state */ 1191 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */ 1192 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */ 1193 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced, 1194 * Do not try to bring up */ 1195 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */ 1196 1197 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1198 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1) 1199 1200 1201 /* ctxt_flag bit offsets */ 1202 /* waiting for a packet to arrive */ 1203 #define QIB_CTXT_WAITING_RCV 2 1204 /* master has not finished initializing */ 1205 #define QIB_CTXT_MASTER_UNINIT 4 1206 /* waiting for an urgent packet to arrive */ 1207 #define QIB_CTXT_WAITING_URG 5 1208 1209 /* free up any allocated data at closes */ 1210 void qib_free_data(struct qib_ctxtdata *dd); 1211 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned, 1212 u32, struct qib_ctxtdata *); 1213 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *, 1214 const struct pci_device_id *); 1215 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *, 1216 const struct pci_device_id *); 1217 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *, 1218 const struct pci_device_id *); 1219 void qib_free_devdata(struct qib_devdata *); 1220 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra); 1221 1222 #define QIB_TWSI_NO_DEV 0xFF 1223 /* Below qib_twsi_ functions must be called with eep_lock held */ 1224 int qib_twsi_reset(struct qib_devdata *dd); 1225 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer, 1226 int len); 1227 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1228 const void *buffer, int len); 1229 void qib_get_eeprom_info(struct qib_devdata *); 1230 int qib_update_eeprom_log(struct qib_devdata *dd); 1231 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr); 1232 void qib_dump_lookup_output_queue(struct qib_devdata *); 1233 void qib_force_pio_avail_update(struct qib_devdata *); 1234 void qib_clear_symerror_on_linkup(unsigned long opaque); 1235 1236 /* 1237 * Set LED override, only the two LSBs have "public" meaning, but 1238 * any non-zero value substitutes them for the Link and LinkTrain 1239 * LED states. 1240 */ 1241 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ 1242 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */ 1243 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); 1244 1245 /* send dma routines */ 1246 int qib_setup_sdma(struct qib_pportdata *); 1247 void qib_teardown_sdma(struct qib_pportdata *); 1248 void __qib_sdma_intr(struct qib_pportdata *); 1249 void qib_sdma_intr(struct qib_pportdata *); 1250 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *, 1251 u32, struct qib_verbs_txreq *); 1252 /* ppd->sdma_lock should be locked before calling this. */ 1253 int qib_sdma_make_progress(struct qib_pportdata *dd); 1254 1255 /* must be called under qib_sdma_lock */ 1256 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd) 1257 { 1258 return ppd->sdma_descq_cnt - 1259 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1; 1260 } 1261 1262 static inline int __qib_sdma_running(struct qib_pportdata *ppd) 1263 { 1264 return ppd->sdma_state.current_state == qib_sdma_state_s99_running; 1265 } 1266 int qib_sdma_running(struct qib_pportdata *); 1267 1268 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1269 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1270 1271 /* 1272 * number of words used for protocol header if not set by qib_userinit(); 1273 */ 1274 #define QIB_DFLT_RCVHDRSIZE 9 1275 1276 /* 1277 * We need to be able to handle an IB header of at least 24 dwords. 1278 * We need the rcvhdrq large enough to handle largest IB header, but 1279 * still have room for a 2KB MTU standard IB packet. 1280 * Additionally, some processor/memory controller combinations 1281 * benefit quite strongly from having the DMA'ed data be cacheline 1282 * aligned and a cacheline multiple, so we set the size to 32 dwords 1283 * (2 64-byte primary cachelines for pretty much all processors of 1284 * interest). The alignment hurts nothing, other than using somewhat 1285 * more memory. 1286 */ 1287 #define QIB_RCVHDR_ENTSIZE 32 1288 1289 int qib_get_user_pages(unsigned long, size_t, struct page **); 1290 void qib_release_user_pages(struct page **, size_t); 1291 int qib_eeprom_read(struct qib_devdata *, u8, void *, int); 1292 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int); 1293 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32); 1294 void qib_sendbuf_done(struct qib_devdata *, unsigned); 1295 1296 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd) 1297 { 1298 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; 1299 } 1300 1301 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd) 1302 { 1303 /* 1304 * volatile because it's a DMA target from the chip, routine is 1305 * inlined, and don't want register caching or reordering. 1306 */ 1307 return (u32) le64_to_cpu( 1308 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */ 1309 } 1310 1311 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd) 1312 { 1313 const struct qib_devdata *dd = rcd->dd; 1314 u32 hdrqtail; 1315 1316 if (dd->flags & QIB_NODMA_RTAIL) { 1317 __le32 *rhf_addr; 1318 u32 seq; 1319 1320 rhf_addr = (__le32 *) rcd->rcvhdrq + 1321 rcd->head + dd->rhf_offset; 1322 seq = qib_hdrget_seq(rhf_addr); 1323 hdrqtail = rcd->head; 1324 if (seq == rcd->seq_cnt) 1325 hdrqtail++; 1326 } else 1327 hdrqtail = qib_get_rcvhdrtail(rcd); 1328 1329 return hdrqtail; 1330 } 1331 1332 /* 1333 * sysfs interface. 1334 */ 1335 1336 extern const char ib_qib_version[]; 1337 1338 int qib_device_create(struct qib_devdata *); 1339 void qib_device_remove(struct qib_devdata *); 1340 1341 int qib_create_port_files(struct ib_device *ibdev, u8 port_num, 1342 struct kobject *kobj); 1343 int qib_verbs_register_sysfs(struct qib_devdata *); 1344 void qib_verbs_unregister_sysfs(struct qib_devdata *); 1345 /* Hook for sysfs read of QSFP */ 1346 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len); 1347 1348 int __init qib_init_qibfs(void); 1349 int __exit qib_exit_qibfs(void); 1350 1351 int qibfs_add(struct qib_devdata *); 1352 int qibfs_remove(struct qib_devdata *); 1353 1354 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *); 1355 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *, 1356 const struct pci_device_id *); 1357 void qib_pcie_ddcleanup(struct qib_devdata *); 1358 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct msix_entry *); 1359 int qib_reinit_intr(struct qib_devdata *); 1360 void qib_enable_intx(struct pci_dev *); 1361 void qib_nomsi(struct qib_devdata *); 1362 void qib_nomsix(struct qib_devdata *); 1363 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1364 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 1365 1366 /* 1367 * dma_addr wrappers - all 0's invalid for hw 1368 */ 1369 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long, 1370 size_t, int); 1371 const char *qib_get_unit_name(int unit); 1372 1373 /* 1374 * Flush write combining store buffers (if present) and perform a write 1375 * barrier. 1376 */ 1377 #if defined(CONFIG_X86_64) 1378 #define qib_flush_wc() asm volatile("sfence" : : : "memory") 1379 #else 1380 #define qib_flush_wc() wmb() /* no reorder around wc flush */ 1381 #endif 1382 1383 /* global module parameter variables */ 1384 extern unsigned qib_ibmtu; 1385 extern ushort qib_cfgctxts; 1386 extern ushort qib_num_cfg_vls; 1387 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */ 1388 extern unsigned qib_n_krcv_queues; 1389 extern unsigned qib_sdma_fetch_arb; 1390 extern unsigned qib_compat_ddr_negotiate; 1391 extern int qib_special_trigger; 1392 1393 extern struct mutex qib_mutex; 1394 1395 /* Number of seconds before our card status check... */ 1396 #define STATUS_TIMEOUT 60 1397 1398 #define QIB_DRV_NAME "ib_qib" 1399 #define QIB_USER_MINOR_BASE 0 1400 #define QIB_TRACE_MINOR 127 1401 #define QIB_DIAGPKT_MINOR 128 1402 #define QIB_DIAG_MINOR_BASE 129 1403 #define QIB_NMINORS 255 1404 1405 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 1406 #define PCI_VENDOR_ID_QLOGIC 0x1077 1407 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10 1408 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220 1409 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322 1410 1411 /* 1412 * qib_early_err is used (only!) to print early errors before devdata is 1413 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1414 * cleanup when devdata may have been freed, etc. qib_dev_porterr is 1415 * the same as qib_dev_err, but is used when the message really needs 1416 * the IB port# to be definitive as to what's happening.. 1417 * All of these go to the trace log, and the trace log entry is done 1418 * first to avoid possible serial port delays from printk. 1419 */ 1420 #define qib_early_err(dev, fmt, ...) \ 1421 do { \ 1422 dev_err(dev, fmt, ##__VA_ARGS__); \ 1423 } while (0) 1424 1425 #define qib_dev_err(dd, fmt, ...) \ 1426 do { \ 1427 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1428 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \ 1429 } while (0) 1430 1431 #define qib_dev_porterr(dd, port, fmt, ...) \ 1432 do { \ 1433 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ 1434 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \ 1435 ##__VA_ARGS__); \ 1436 } while (0) 1437 1438 #define qib_devinfo(pcidev, fmt, ...) \ 1439 do { \ 1440 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \ 1441 } while (0) 1442 1443 /* 1444 * this is used for formatting hw error messages... 1445 */ 1446 struct qib_hwerror_msgs { 1447 u64 mask; 1448 const char *msg; 1449 size_t sz; 1450 }; 1451 1452 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } 1453 1454 /* in qib_intr.c... */ 1455 void qib_format_hwerrors(u64 hwerrs, 1456 const struct qib_hwerror_msgs *hwerrmsgs, 1457 size_t nhwerrmsgs, char *msg, size_t lmsg); 1458 #endif /* _QIB_KERNEL_H */ 1459