1 #ifndef _QIB_KERNEL_H 2 #define _QIB_KERNEL_H 3 /* 4 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved. 5 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 /* 38 * This header file is the base header file for qlogic_ib kernel code 39 * qib_user.h serves a similar purpose for user code. 40 */ 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/mutex.h> 46 #include <linux/list.h> 47 #include <linux/scatterlist.h> 48 #include <linux/slab.h> 49 #include <linux/io.h> 50 #include <linux/fs.h> 51 #include <linux/completion.h> 52 #include <linux/kref.h> 53 #include <linux/sched.h> 54 #include <linux/kthread.h> 55 #include <rdma/rdma_vt.h> 56 57 #include "qib_common.h" 58 #include "qib_verbs.h" 59 60 /* only s/w major version of QLogic_IB we can handle */ 61 #define QIB_CHIP_VERS_MAJ 2U 62 63 /* don't care about this except printing */ 64 #define QIB_CHIP_VERS_MIN 0U 65 66 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 67 #define QIB_OUI 0x001175 68 #define QIB_OUI_LSB 40 69 70 /* 71 * per driver stats, either not device nor port-specific, or 72 * summed over all of the devices and ports. 73 * They are described by name via ipathfs filesystem, so layout 74 * and number of elements can change without breaking compatibility. 75 * If members are added or deleted qib_statnames[] in qib_fs.c must 76 * change to match. 77 */ 78 struct qlogic_ib_stats { 79 __u64 sps_ints; /* number of interrupts handled */ 80 __u64 sps_errints; /* number of error interrupts */ 81 __u64 sps_txerrs; /* tx-related packet errors */ 82 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 83 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 84 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 85 __u64 sps_ctxts; /* number of contexts currently open */ 86 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 87 __u64 sps_buffull; 88 __u64 sps_hdrfull; 89 }; 90 91 extern struct qlogic_ib_stats qib_stats; 92 extern const struct pci_error_handlers qib_pci_err_handler; 93 94 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ 95 /* 96 * First-cut critierion for "device is active" is 97 * two thousand dwords combined Tx, Rx traffic per 98 * 5-second interval. SMA packets are 64 dwords, 99 * and occur "a few per second", presumably each way. 100 */ 101 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 102 103 /* 104 * Struct used to indicate which errors are logged in each of the 105 * error-counters that are logged to EEPROM. A counter is incremented 106 * _once_ (saturating at 255) for each event with any bits set in 107 * the error or hwerror register masks below. 108 */ 109 #define QIB_EEP_LOG_CNT (4) 110 struct qib_eep_log_mask { 111 u64 errs_to_log; 112 u64 hwerrs_to_log; 113 }; 114 115 /* 116 * Below contains all data related to a single context (formerly called port). 117 */ 118 119 #ifdef CONFIG_DEBUG_FS 120 struct qib_opcode_stats_perctx; 121 #endif 122 123 struct qib_ctxtdata { 124 void **rcvegrbuf; 125 dma_addr_t *rcvegrbuf_phys; 126 /* rcvhdrq base, needs mmap before useful */ 127 void *rcvhdrq; 128 /* kernel virtual address where hdrqtail is updated */ 129 void *rcvhdrtail_kvaddr; 130 /* 131 * temp buffer for expected send setup, allocated at open, instead 132 * of each setup call 133 */ 134 void *tid_pg_list; 135 /* 136 * Shared page for kernel to signal user processes that send buffers 137 * need disarming. The process should call QIB_CMD_DISARM_BUFS 138 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 139 */ 140 unsigned long *user_event_mask; 141 /* when waiting for rcv or pioavail */ 142 wait_queue_head_t wait; 143 /* 144 * rcvegr bufs base, physical, must fit 145 * in 44 bits so 32 bit programs mmap64 44 bit works) 146 */ 147 dma_addr_t rcvegr_phys; 148 /* mmap of hdrq, must fit in 44 bits */ 149 dma_addr_t rcvhdrq_phys; 150 dma_addr_t rcvhdrqtailaddr_phys; 151 152 /* 153 * number of opens (including slave sub-contexts) on this instance 154 * (ignoring forks, dup, etc. for now) 155 */ 156 int cnt; 157 /* 158 * how much space to leave at start of eager TID entries for 159 * protocol use, on each TID 160 */ 161 /* instead of calculating it */ 162 unsigned ctxt; 163 /* local node of context */ 164 int node_id; 165 /* non-zero if ctxt is being shared. */ 166 u16 subctxt_cnt; 167 /* non-zero if ctxt is being shared. */ 168 u16 subctxt_id; 169 /* number of eager TID entries. */ 170 u16 rcvegrcnt; 171 /* index of first eager TID entry. */ 172 u16 rcvegr_tid_base; 173 /* number of pio bufs for this ctxt (all procs, if shared) */ 174 u32 piocnt; 175 /* first pio buffer for this ctxt */ 176 u32 pio_base; 177 /* chip offset of PIO buffers for this ctxt */ 178 u32 piobufs; 179 /* how many alloc_pages() chunks in rcvegrbuf_pages */ 180 u32 rcvegrbuf_chunks; 181 /* how many egrbufs per chunk */ 182 u16 rcvegrbufs_perchunk; 183 /* ilog2 of above */ 184 u16 rcvegrbufs_perchunk_shift; 185 /* order for rcvegrbuf_pages */ 186 size_t rcvegrbuf_size; 187 /* rcvhdrq size (for freeing) */ 188 size_t rcvhdrq_size; 189 /* per-context flags for fileops/intr communication */ 190 unsigned long flag; 191 /* next expected TID to check when looking for free */ 192 u32 tidcursor; 193 /* WAIT_RCV that timed out, no interrupt */ 194 u32 rcvwait_to; 195 /* WAIT_PIO that timed out, no interrupt */ 196 u32 piowait_to; 197 /* WAIT_RCV already happened, no wait */ 198 u32 rcvnowait; 199 /* WAIT_PIO already happened, no wait */ 200 u32 pionowait; 201 /* total number of polled urgent packets */ 202 u32 urgent; 203 /* saved total number of polled urgent packets for poll edge trigger */ 204 u32 urgent_poll; 205 /* pid of process using this ctxt */ 206 pid_t pid; 207 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT]; 208 /* same size as task_struct .comm[], command that opened context */ 209 char comm[16]; 210 /* pkeys set by this use of this ctxt */ 211 u16 pkeys[4]; 212 /* so file ops can get at unit */ 213 struct qib_devdata *dd; 214 /* so funcs that need physical port can get it easily */ 215 struct qib_pportdata *ppd; 216 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 217 void *subctxt_uregbase; 218 /* An array of pages for the eager receive buffers * N */ 219 void *subctxt_rcvegrbuf; 220 /* An array of pages for the eager header queue entries * N */ 221 void *subctxt_rcvhdr_base; 222 /* The version of the library which opened this ctxt */ 223 u32 userversion; 224 /* Bitmask of active slaves */ 225 u32 active_slaves; 226 /* Type of packets or conditions we want to poll for */ 227 u16 poll_type; 228 /* receive packet sequence counter */ 229 u8 seq_cnt; 230 u8 redirect_seq_cnt; 231 /* ctxt rcvhdrq head offset */ 232 u32 head; 233 /* QPs waiting for context processing */ 234 struct list_head qp_wait_list; 235 #ifdef CONFIG_DEBUG_FS 236 /* verbs stats per CTX */ 237 struct qib_opcode_stats_perctx *opstats; 238 #endif 239 }; 240 241 struct rvt_sge_state; 242 243 struct qib_sdma_txreq { 244 int flags; 245 int sg_count; 246 dma_addr_t addr; 247 void (*callback)(struct qib_sdma_txreq *, int); 248 u16 start_idx; /* sdma private */ 249 u16 next_descq_idx; /* sdma private */ 250 struct list_head list; /* sdma private */ 251 }; 252 253 struct qib_sdma_desc { 254 __le64 qw[2]; 255 }; 256 257 struct qib_verbs_txreq { 258 struct qib_sdma_txreq txreq; 259 struct rvt_qp *qp; 260 struct rvt_swqe *wqe; 261 u32 dwords; 262 u16 hdr_dwords; 263 u16 hdr_inx; 264 struct qib_pio_header *align_buf; 265 struct rvt_mregion *mr; 266 struct rvt_sge_state *ss; 267 }; 268 269 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1 270 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2 271 #define QIB_SDMA_TXREQ_F_INTREQ 0x4 272 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8 273 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10 274 275 #define QIB_SDMA_TXREQ_S_OK 0 276 #define QIB_SDMA_TXREQ_S_SENDERROR 1 277 #define QIB_SDMA_TXREQ_S_ABORTED 2 278 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3 279 280 /* 281 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 282 * Mostly for MADs that set or query link parameters, also ipath 283 * config interfaces 284 */ 285 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 286 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 287 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */ 288 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 289 #define QIB_IB_CFG_SPD 5 /* current Link spd */ 290 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 291 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 292 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 293 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 294 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */ 295 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 296 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 297 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 298 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 299 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 300 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */ 301 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */ 302 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */ 303 #define QIB_IB_CFG_VL_HIGH_LIMIT 19 304 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 305 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */ 306 307 /* 308 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16 309 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for 310 * QIB_IB_CFG_LINKDEFAULT cmd 311 */ 312 #define IB_LINKCMD_DOWN (0 << 16) 313 #define IB_LINKCMD_ARMED (1 << 16) 314 #define IB_LINKCMD_ACTIVE (2 << 16) 315 #define IB_LINKINITCMD_NOP 0 316 #define IB_LINKINITCMD_POLL 1 317 #define IB_LINKINITCMD_SLEEP 2 318 #define IB_LINKINITCMD_DISABLE 3 319 320 /* 321 * valid states passed to qib_set_linkstate() user call 322 */ 323 #define QIB_IB_LINKDOWN 0 324 #define QIB_IB_LINKARM 1 325 #define QIB_IB_LINKACTIVE 2 326 #define QIB_IB_LINKDOWN_ONLY 3 327 #define QIB_IB_LINKDOWN_SLEEP 4 328 #define QIB_IB_LINKDOWN_DISABLE 5 329 330 /* 331 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed 332 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg 333 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They 334 * are also the the possible values for qib_link_speed_enabled and active 335 * The values were chosen to match values used within the IB spec. 336 */ 337 #define QIB_IB_SDR 1 338 #define QIB_IB_DDR 2 339 #define QIB_IB_QDR 4 340 341 #define QIB_DEFAULT_MTU 4096 342 343 /* max number of IB ports supported per HCA */ 344 #define QIB_MAX_IB_PORTS 2 345 346 /* 347 * Possible IB config parameters for f_get/set_ib_table() 348 */ 349 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */ 350 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */ 351 352 /* 353 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 354 * these are bits so they can be combined, e.g. 355 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB 356 */ 357 #define QIB_RCVCTRL_TAILUPD_ENB 0x01 358 #define QIB_RCVCTRL_TAILUPD_DIS 0x02 359 #define QIB_RCVCTRL_CTXT_ENB 0x04 360 #define QIB_RCVCTRL_CTXT_DIS 0x08 361 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10 362 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20 363 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 364 #define QIB_RCVCTRL_PKEY_DIS 0x80 365 #define QIB_RCVCTRL_BP_ENB 0x0100 366 #define QIB_RCVCTRL_BP_DIS 0x0200 367 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400 368 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800 369 370 /* 371 * Possible "operations" for f_sendctrl(ppd, op, var) 372 * these are bits so they can be combined, e.g. 373 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB 374 * Some operations (e.g. DISARM, ABORT) are known to 375 * be "one-shot", so do not modify shadow. 376 */ 377 #define QIB_SENDCTRL_DISARM (0x1000) 378 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM) 379 /* available (0x2000) */ 380 #define QIB_SENDCTRL_AVAIL_DIS (0x4000) 381 #define QIB_SENDCTRL_AVAIL_ENB (0x8000) 382 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000) 383 #define QIB_SENDCTRL_SEND_DIS (0x20000) 384 #define QIB_SENDCTRL_SEND_ENB (0x40000) 385 #define QIB_SENDCTRL_FLUSH (0x80000) 386 #define QIB_SENDCTRL_CLEAR (0x100000) 387 #define QIB_SENDCTRL_DISARM_ALL (0x200000) 388 389 /* 390 * These are the generic indices for requesting per-port 391 * counter values via the f_portcntr function. They 392 * are always returned as 64 bit values, although most 393 * are 32 bit counters. 394 */ 395 /* send-related counters */ 396 #define QIBPORTCNTR_PKTSEND 0U 397 #define QIBPORTCNTR_WORDSEND 1U 398 #define QIBPORTCNTR_PSXMITDATA 2U 399 #define QIBPORTCNTR_PSXMITPKTS 3U 400 #define QIBPORTCNTR_PSXMITWAIT 4U 401 #define QIBPORTCNTR_SENDSTALL 5U 402 /* receive-related counters */ 403 #define QIBPORTCNTR_PKTRCV 6U 404 #define QIBPORTCNTR_PSRCVDATA 7U 405 #define QIBPORTCNTR_PSRCVPKTS 8U 406 #define QIBPORTCNTR_RCVEBP 9U 407 #define QIBPORTCNTR_RCVOVFL 10U 408 #define QIBPORTCNTR_WORDRCV 11U 409 /* IB link related error counters */ 410 #define QIBPORTCNTR_RXLOCALPHYERR 12U 411 #define QIBPORTCNTR_RXVLERR 13U 412 #define QIBPORTCNTR_ERRICRC 14U 413 #define QIBPORTCNTR_ERRVCRC 15U 414 #define QIBPORTCNTR_ERRLPCRC 16U 415 #define QIBPORTCNTR_BADFORMAT 17U 416 #define QIBPORTCNTR_ERR_RLEN 18U 417 #define QIBPORTCNTR_IBSYMBOLERR 19U 418 #define QIBPORTCNTR_INVALIDRLEN 20U 419 #define QIBPORTCNTR_UNSUPVL 21U 420 #define QIBPORTCNTR_EXCESSBUFOVFL 22U 421 #define QIBPORTCNTR_ERRLINK 23U 422 #define QIBPORTCNTR_IBLINKDOWN 24U 423 #define QIBPORTCNTR_IBLINKERRRECOV 25U 424 #define QIBPORTCNTR_LLI 26U 425 /* other error counters */ 426 #define QIBPORTCNTR_RXDROPPKT 27U 427 #define QIBPORTCNTR_VL15PKTDROP 28U 428 #define QIBPORTCNTR_ERRPKEY 29U 429 #define QIBPORTCNTR_KHDROVFL 30U 430 /* sampling counters (these are actually control registers) */ 431 #define QIBPORTCNTR_PSINTERVAL 31U 432 #define QIBPORTCNTR_PSSTART 32U 433 #define QIBPORTCNTR_PSSTAT 33U 434 435 /* how often we check for packet activity for "power on hours (in seconds) */ 436 #define ACTIVITY_TIMER 5 437 438 #define MAX_NAME_SIZE 64 439 440 #ifdef CONFIG_INFINIBAND_QIB_DCA 441 struct qib_irq_notify; 442 #endif 443 444 struct qib_msix_entry { 445 struct msix_entry msix; 446 void *arg; 447 #ifdef CONFIG_INFINIBAND_QIB_DCA 448 int dca; 449 int rcv; 450 struct qib_irq_notify *notifier; 451 #endif 452 char name[MAX_NAME_SIZE]; 453 cpumask_var_t mask; 454 }; 455 456 /* Below is an opaque struct. Each chip (device) can maintain 457 * private data needed for its operation, but not germane to the 458 * rest of the driver. For convenience, we define another that 459 * is chip-specific, per-port 460 */ 461 struct qib_chip_specific; 462 struct qib_chipport_specific; 463 464 enum qib_sdma_states { 465 qib_sdma_state_s00_hw_down, 466 qib_sdma_state_s10_hw_start_up_wait, 467 qib_sdma_state_s20_idle, 468 qib_sdma_state_s30_sw_clean_up_wait, 469 qib_sdma_state_s40_hw_clean_up_wait, 470 qib_sdma_state_s50_hw_halt_wait, 471 qib_sdma_state_s99_running, 472 }; 473 474 enum qib_sdma_events { 475 qib_sdma_event_e00_go_hw_down, 476 qib_sdma_event_e10_go_hw_start, 477 qib_sdma_event_e20_hw_started, 478 qib_sdma_event_e30_go_running, 479 qib_sdma_event_e40_sw_cleaned, 480 qib_sdma_event_e50_hw_cleaned, 481 qib_sdma_event_e60_hw_halted, 482 qib_sdma_event_e70_go_idle, 483 qib_sdma_event_e7220_err_halted, 484 qib_sdma_event_e7322_err_halted, 485 qib_sdma_event_e90_timer_tick, 486 }; 487 488 extern char *qib_sdma_state_names[]; 489 extern char *qib_sdma_event_names[]; 490 491 struct sdma_set_state_action { 492 unsigned op_enable:1; 493 unsigned op_intenable:1; 494 unsigned op_halt:1; 495 unsigned op_drain:1; 496 unsigned go_s99_running_tofalse:1; 497 unsigned go_s99_running_totrue:1; 498 }; 499 500 struct qib_sdma_state { 501 struct kref kref; 502 struct completion comp; 503 enum qib_sdma_states current_state; 504 struct sdma_set_state_action *set_state_action; 505 unsigned current_op; 506 unsigned go_s99_running; 507 unsigned first_sendbuf; 508 unsigned last_sendbuf; /* really last +1 */ 509 /* debugging/devel */ 510 enum qib_sdma_states previous_state; 511 unsigned previous_op; 512 enum qib_sdma_events last_event; 513 }; 514 515 struct xmit_wait { 516 struct timer_list timer; 517 u64 counter; 518 u8 flags; 519 struct cache { 520 u64 psxmitdata; 521 u64 psrcvdata; 522 u64 psxmitpkts; 523 u64 psrcvpkts; 524 u64 psxmitwait; 525 } counter_cache; 526 }; 527 528 /* 529 * The structure below encapsulates data relevant to a physical IB Port. 530 * Current chips support only one such port, but the separation 531 * clarifies things a bit. Note that to conform to IB conventions, 532 * port-numbers are one-based. The first or only port is port1. 533 */ 534 struct qib_pportdata { 535 struct qib_ibport ibport_data; 536 537 struct qib_devdata *dd; 538 struct qib_chippport_specific *cpspec; /* chip-specific per-port */ 539 struct kobject pport_kobj; 540 struct kobject pport_cc_kobj; 541 struct kobject sl2vl_kobj; 542 struct kobject diagc_kobj; 543 544 /* GUID for this interface, in network order */ 545 __be64 guid; 546 547 /* QIB_POLL, etc. link-state specific flags, per port */ 548 u32 lflags; 549 /* qib_lflags driver is waiting for */ 550 u32 state_wanted; 551 spinlock_t lflags_lock; 552 553 /* ref count for each pkey */ 554 atomic_t pkeyrefs[4]; 555 556 /* 557 * this address is mapped readonly into user processes so they can 558 * get status cheaply, whenever they want. One qword of status per port 559 */ 560 u64 *statusp; 561 562 /* SendDMA related entries */ 563 564 /* read mostly */ 565 struct qib_sdma_desc *sdma_descq; 566 struct workqueue_struct *qib_wq; 567 struct qib_sdma_state sdma_state; 568 dma_addr_t sdma_descq_phys; 569 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */ 570 dma_addr_t sdma_head_phys; 571 u16 sdma_descq_cnt; 572 573 /* read/write using lock */ 574 spinlock_t sdma_lock ____cacheline_aligned_in_smp; 575 struct list_head sdma_activelist; 576 struct list_head sdma_userpending; 577 u64 sdma_descq_added; 578 u64 sdma_descq_removed; 579 u16 sdma_descq_tail; 580 u16 sdma_descq_head; 581 u8 sdma_generation; 582 u8 sdma_intrequest; 583 584 struct tasklet_struct sdma_sw_clean_up_task 585 ____cacheline_aligned_in_smp; 586 587 wait_queue_head_t state_wait; /* for state_wanted */ 588 589 /* HoL blocking for SMP replies */ 590 unsigned hol_state; 591 struct timer_list hol_timer; 592 593 /* 594 * Shadow copies of registers; size indicates read access size. 595 * Most of them are readonly, but some are write-only register, 596 * where we manipulate the bits in the shadow copy, and then write 597 * the shadow copy to qlogic_ib. 598 * 599 * We deliberately make most of these 32 bits, since they have 600 * restricted range. For any that we read, we won't to generate 32 601 * bit accesses, since Opteron will generate 2 separate 32 bit HT 602 * transactions for a 64 bit read, and we want to avoid unnecessary 603 * bus transactions. 604 */ 605 606 /* This is the 64 bit group */ 607 /* last ibcstatus. opaque outside chip-specific code */ 608 u64 lastibcstat; 609 610 /* these are the "32 bit" regs */ 611 612 /* 613 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 614 * all expect bit fields to be "unsigned long" 615 */ 616 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */ 617 unsigned long p_sendctrl; /* shadow per-port sendctrl */ 618 619 u32 ibmtu; /* The MTU programmed for this unit */ 620 /* 621 * Current max size IB packet (in bytes) including IB headers, that 622 * we can send. Changes when ibmtu changes. 623 */ 624 u32 ibmaxlen; 625 /* 626 * ibmaxlen at init time, limited by chip and by receive buffer 627 * size. Not changed after init. 628 */ 629 u32 init_ibmaxlen; 630 /* LID programmed for this instance */ 631 u16 lid; 632 /* list of pkeys programmed; 0 if not set */ 633 u16 pkeys[4]; 634 /* LID mask control */ 635 u8 lmc; 636 u8 link_width_supported; 637 u8 link_speed_supported; 638 u8 link_width_enabled; 639 u8 link_speed_enabled; 640 u8 link_width_active; 641 u8 link_speed_active; 642 u8 vls_supported; 643 u8 vls_operational; 644 /* Rx Polarity inversion (compensate for ~tx on partner) */ 645 u8 rx_pol_inv; 646 647 u8 hw_pidx; /* physical port index */ 648 u8 port; /* IB port number and index into dd->pports - 1 */ 649 650 u8 delay_mult; 651 652 /* used to override LED behavior */ 653 u8 led_override; /* Substituted for normal value, if non-zero */ 654 u16 led_override_timeoff; /* delta to next timer event */ 655 u8 led_override_vals[2]; /* Alternates per blink-frame */ 656 u8 led_override_phase; /* Just counts, LSB picks from vals[] */ 657 atomic_t led_override_timer_active; 658 /* Used to flash LEDs in override mode */ 659 struct timer_list led_override_timer; 660 struct xmit_wait cong_stats; 661 struct timer_list symerr_clear_timer; 662 663 /* Synchronize access between driver writes and sysfs reads */ 664 spinlock_t cc_shadow_lock 665 ____cacheline_aligned_in_smp; 666 667 /* Shadow copy of the congestion control table */ 668 struct cc_table_shadow *ccti_entries_shadow; 669 670 /* Shadow copy of the congestion control entries */ 671 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow; 672 673 /* List of congestion control table entries */ 674 struct ib_cc_table_entry_shadow *ccti_entries; 675 676 /* 16 congestion entries with each entry corresponding to a SL */ 677 struct ib_cc_congestion_entry_shadow *congestion_entries; 678 679 /* Maximum number of congestion control entries that the agent expects 680 * the manager to send. 681 */ 682 u16 cc_supported_table_entries; 683 684 /* Total number of congestion control table entries */ 685 u16 total_cct_entry; 686 687 /* Bit map identifying service level */ 688 u16 cc_sl_control_map; 689 690 /* maximum congestion control table index */ 691 u16 ccti_limit; 692 693 /* CA's max number of 64 entry units in the congestion control table */ 694 u8 cc_max_table_entries; 695 }; 696 697 /* Observers. Not to be taken lightly, possibly not to ship. */ 698 /* 699 * If a diag read or write is to (bottom <= offset <= top), 700 * the "hoook" is called, allowing, e.g. shadows to be 701 * updated in sync with the driver. struct diag_observer 702 * is the "visible" part. 703 */ 704 struct diag_observer; 705 706 typedef int (*diag_hook) (struct qib_devdata *dd, 707 const struct diag_observer *op, 708 u32 offs, u64 *data, u64 mask, int only_32); 709 710 struct diag_observer { 711 diag_hook hook; 712 u32 bottom; 713 u32 top; 714 }; 715 716 extern int qib_register_observer(struct qib_devdata *dd, 717 const struct diag_observer *op); 718 719 /* Only declared here, not defined. Private to diags */ 720 struct diag_observer_list_elt; 721 722 /* device data struct now contains only "general per-device" info. 723 * fields related to a physical IB port are in a qib_pportdata struct, 724 * described above) while fields only used by a particular chip-type are in 725 * a qib_chipdata struct, whose contents are opaque to this file. 726 */ 727 struct qib_devdata { 728 struct qib_ibdev verbs_dev; /* must be first */ 729 struct list_head list; 730 /* pointers to related structs for this device */ 731 /* pci access data structure */ 732 struct pci_dev *pcidev; 733 struct cdev *user_cdev; 734 struct cdev *diag_cdev; 735 struct device *user_device; 736 struct device *diag_device; 737 738 /* mem-mapped pointer to base of chip regs */ 739 u64 __iomem *kregbase; 740 /* end of mem-mapped chip space excluding sendbuf and user regs */ 741 u64 __iomem *kregend; 742 /* physical address of chip for io_remap, etc. */ 743 resource_size_t physaddr; 744 /* qib_cfgctxts pointers */ 745 struct qib_ctxtdata **rcd; /* Receive Context Data */ 746 747 /* qib_pportdata, points to array of (physical) port-specific 748 * data structs, indexed by pidx (0..n-1) 749 */ 750 struct qib_pportdata *pport; 751 struct qib_chip_specific *cspec; /* chip-specific */ 752 753 /* kvirt address of 1st 2k pio buffer */ 754 void __iomem *pio2kbase; 755 /* kvirt address of 1st 4k pio buffer */ 756 void __iomem *pio4kbase; 757 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */ 758 void __iomem *piobase; 759 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */ 760 u64 __iomem *userbase; 761 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */ 762 /* 763 * points to area where PIOavail registers will be DMA'ed. 764 * Has to be on a page of it's own, because the page will be 765 * mapped into user program space. This copy is *ONLY* ever 766 * written by DMA, not by the driver! Need a copy per device 767 * when we get to multiple devices 768 */ 769 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */ 770 /* physical address where updates occur */ 771 dma_addr_t pioavailregs_phys; 772 773 /* device-specific implementations of functions needed by 774 * common code. Contrary to previous consensus, we can't 775 * really just point to a device-specific table, because we 776 * may need to "bend", e.g. *_f_put_tid 777 */ 778 /* fallback to alternate interrupt type if possible */ 779 int (*f_intr_fallback)(struct qib_devdata *); 780 /* hard reset chip */ 781 int (*f_reset)(struct qib_devdata *); 782 void (*f_quiet_serdes)(struct qib_pportdata *); 783 int (*f_bringup_serdes)(struct qib_pportdata *); 784 int (*f_early_init)(struct qib_devdata *); 785 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *); 786 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*, 787 u32, unsigned long); 788 void (*f_cleanup)(struct qib_devdata *); 789 void (*f_setextled)(struct qib_pportdata *, u32); 790 /* fill out chip-specific fields */ 791 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *); 792 /* free irq */ 793 void (*f_free_irq)(struct qib_devdata *); 794 struct qib_message_header *(*f_get_msgheader) 795 (struct qib_devdata *, __le32 *); 796 void (*f_config_ctxts)(struct qib_devdata *); 797 int (*f_get_ib_cfg)(struct qib_pportdata *, int); 798 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32); 799 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *); 800 int (*f_get_ib_table)(struct qib_pportdata *, int, void *); 801 int (*f_set_ib_table)(struct qib_pportdata *, int, void *); 802 u32 (*f_iblink_state)(u64); 803 u8 (*f_ibphys_portstate)(u64); 804 void (*f_xgxs_reset)(struct qib_pportdata *); 805 /* per chip actions needed for IB Link up/down changes */ 806 int (*f_ib_updown)(struct qib_pportdata *, int, u64); 807 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *); 808 /* Read/modify/write of GPIO pins (potentially chip-specific */ 809 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir, 810 u32 mask); 811 /* Enable writes to config EEPROM (if supported) */ 812 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen); 813 /* 814 * modify rcvctrl shadow[s] and write to appropriate chip-regs. 815 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations. 816 * (ctxt == -1) means "all contexts", only meaningful for 817 * clearing. Could remove if chip_spec shutdown properly done. 818 */ 819 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op, 820 int ctxt); 821 /* Read/modify/write sendctrl appropriately for op and port. */ 822 void (*f_sendctrl)(struct qib_pportdata *, u32 op); 823 void (*f_set_intr_state)(struct qib_devdata *, u32); 824 void (*f_set_armlaunch)(struct qib_devdata *, u32); 825 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32); 826 int (*f_late_initreg)(struct qib_devdata *); 827 int (*f_init_sdma_regs)(struct qib_pportdata *); 828 u16 (*f_sdma_gethead)(struct qib_pportdata *); 829 int (*f_sdma_busy)(struct qib_pportdata *); 830 void (*f_sdma_update_tail)(struct qib_pportdata *, u16); 831 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned); 832 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned); 833 void (*f_sdma_hw_clean_up)(struct qib_pportdata *); 834 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 835 void (*f_sdma_init_early)(struct qib_pportdata *); 836 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 837 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 838 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 839 u64 (*f_portcntr)(struct qib_pportdata *, u32); 840 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **, 841 u64 **); 842 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32, 843 char **, u64 **); 844 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8); 845 void (*f_initvl15_bufs)(struct qib_devdata *); 846 void (*f_init_ctxt)(struct qib_ctxtdata *); 847 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32, 848 struct qib_ctxtdata *); 849 void (*f_writescratch)(struct qib_devdata *, u32); 850 int (*f_tempsense_rd)(struct qib_devdata *, int regnum); 851 #ifdef CONFIG_INFINIBAND_QIB_DCA 852 int (*f_notify_dca)(struct qib_devdata *, unsigned long event); 853 #endif 854 855 char *boardname; /* human readable board info */ 856 857 /* template for writing TIDs */ 858 u64 tidtemplate; 859 /* value to write to free TIDs */ 860 u64 tidinvalid; 861 862 /* number of registers used for pioavail */ 863 u32 pioavregs; 864 /* device (not port) flags, basically device capabilities */ 865 u32 flags; 866 /* last buffer for user use */ 867 u32 lastctxt_piobuf; 868 869 /* reset value */ 870 u64 z_int_counter; 871 /* percpu intcounter */ 872 u64 __percpu *int_counter; 873 874 /* pio bufs allocated per ctxt */ 875 u32 pbufsctxt; 876 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */ 877 u32 ctxts_extrabuf; 878 /* 879 * number of ctxts configured as max; zero is set to number chip 880 * supports, less gives more pio bufs/ctxt, etc. 881 */ 882 u32 cfgctxts; 883 /* 884 * number of ctxts available for PSM open 885 */ 886 u32 freectxts; 887 888 /* 889 * hint that we should update pioavailshadow before 890 * looking for a PIO buffer 891 */ 892 u32 upd_pio_shadow; 893 894 /* internal debugging stats */ 895 u32 maxpkts_call; 896 u32 avgpkts_call; 897 u64 nopiobufs; 898 899 /* PCI Vendor ID (here for NodeInfo) */ 900 u16 vendorid; 901 /* PCI Device ID (here for NodeInfo) */ 902 u16 deviceid; 903 /* for write combining settings */ 904 int wc_cookie; 905 unsigned long wc_base; 906 unsigned long wc_len; 907 908 /* shadow copy of struct page *'s for exp tid pages */ 909 struct page **pageshadow; 910 /* shadow copy of dma handles for exp tid pages */ 911 dma_addr_t *physshadow; 912 u64 __iomem *egrtidbase; 913 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */ 914 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 915 spinlock_t uctxt_lock; /* rcd and user context changes */ 916 /* 917 * per unit status, see also portdata statusp 918 * mapped readonly into user processes so they can get unit and 919 * IB link status cheaply 920 */ 921 u64 *devstatusp; 922 char *freezemsg; /* freeze msg if hw error put chip in freeze */ 923 u32 freezelen; /* max length of freezemsg */ 924 /* timer used to prevent stats overflow, error throttling, etc. */ 925 struct timer_list stats_timer; 926 927 /* timer to verify interrupts work, and fallback if possible */ 928 struct timer_list intrchk_timer; 929 unsigned long ureg_align; /* user register alignment */ 930 931 /* 932 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and 933 * pio_writing. 934 */ 935 spinlock_t pioavail_lock; 936 /* 937 * index of last buffer to optimize search for next 938 */ 939 u32 last_pio; 940 /* 941 * min kernel pio buffer to optimize search 942 */ 943 u32 min_kernel_pio; 944 /* 945 * Shadow copies of registers; size indicates read access size. 946 * Most of them are readonly, but some are write-only register, 947 * where we manipulate the bits in the shadow copy, and then write 948 * the shadow copy to qlogic_ib. 949 * 950 * We deliberately make most of these 32 bits, since they have 951 * restricted range. For any that we read, we won't to generate 32 952 * bit accesses, since Opteron will generate 2 separate 32 bit HT 953 * transactions for a 64 bit read, and we want to avoid unnecessary 954 * bus transactions. 955 */ 956 957 /* This is the 64 bit group */ 958 959 unsigned long pioavailshadow[6]; 960 /* bitmap of send buffers available for the kernel to use with PIO. */ 961 unsigned long pioavailkernel[6]; 962 /* bitmap of send buffers which need to be disarmed. */ 963 unsigned long pio_need_disarm[3]; 964 /* bitmap of send buffers which are being written to. */ 965 unsigned long pio_writing[3]; 966 /* kr_revision shadow */ 967 u64 revision; 968 /* Base GUID for device (from eeprom, network order) */ 969 __be64 base_guid; 970 971 /* 972 * kr_sendpiobufbase value (chip offset of pio buffers), and the 973 * base of the 2KB buffer s(user processes only use 2K) 974 */ 975 u64 piobufbase; 976 u32 pio2k_bufbase; 977 978 /* these are the "32 bit" regs */ 979 980 /* number of GUIDs in the flash for this interface */ 981 u32 nguid; 982 /* 983 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 984 * all expect bit fields to be "unsigned long" 985 */ 986 unsigned long rcvctrl; /* shadow per device rcvctrl */ 987 unsigned long sendctrl; /* shadow per device sendctrl */ 988 989 /* value we put in kr_rcvhdrcnt */ 990 u32 rcvhdrcnt; 991 /* value we put in kr_rcvhdrsize */ 992 u32 rcvhdrsize; 993 /* value we put in kr_rcvhdrentsize */ 994 u32 rcvhdrentsize; 995 /* kr_ctxtcnt value */ 996 u32 ctxtcnt; 997 /* kr_pagealign value */ 998 u32 palign; 999 /* number of "2KB" PIO buffers */ 1000 u32 piobcnt2k; 1001 /* size in bytes of "2KB" PIO buffers */ 1002 u32 piosize2k; 1003 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */ 1004 u32 piosize2kmax_dwords; 1005 /* number of "4KB" PIO buffers */ 1006 u32 piobcnt4k; 1007 /* size in bytes of "4KB" PIO buffers */ 1008 u32 piosize4k; 1009 /* kr_rcvegrbase value */ 1010 u32 rcvegrbase; 1011 /* kr_rcvtidbase value */ 1012 u32 rcvtidbase; 1013 /* kr_rcvtidcnt value */ 1014 u32 rcvtidcnt; 1015 /* kr_userregbase */ 1016 u32 uregbase; 1017 /* shadow the control register contents */ 1018 u32 control; 1019 1020 /* chip address space used by 4k pio buffers */ 1021 u32 align4k; 1022 /* size of each rcvegrbuffer */ 1023 u16 rcvegrbufsize; 1024 /* log2 of above */ 1025 u16 rcvegrbufsize_shift; 1026 /* localbus width (1, 2,4,8,16,32) from config space */ 1027 u32 lbus_width; 1028 /* localbus speed in MHz */ 1029 u32 lbus_speed; 1030 int unit; /* unit # of this chip */ 1031 1032 /* start of CHIP_SPEC move to chipspec, but need code changes */ 1033 /* low and high portions of MSI capability/vector */ 1034 u32 msi_lo; 1035 /* saved after PCIe init for restore after reset */ 1036 u32 msi_hi; 1037 /* MSI data (vector) saved for restore */ 1038 u16 msi_data; 1039 /* so we can rewrite it after a chip reset */ 1040 u32 pcibar0; 1041 /* so we can rewrite it after a chip reset */ 1042 u32 pcibar1; 1043 u64 rhdrhead_intr_off; 1044 1045 /* 1046 * ASCII serial number, from flash, large enough for original 1047 * all digit strings, and longer QLogic serial number format 1048 */ 1049 u8 serial[16]; 1050 /* human readable board version */ 1051 u8 boardversion[96]; 1052 u8 lbus_info[32]; /* human readable localbus info */ 1053 /* chip major rev, from qib_revision */ 1054 u8 majrev; 1055 /* chip minor rev, from qib_revision */ 1056 u8 minrev; 1057 1058 /* Misc small ints */ 1059 /* Number of physical ports available */ 1060 u8 num_pports; 1061 /* Lowest context number which can be used by user processes */ 1062 u8 first_user_ctxt; 1063 u8 n_krcv_queues; 1064 u8 qpn_mask; 1065 u8 skip_kctxt_mask; 1066 1067 u16 rhf_offset; /* offset of RHF within receive header entry */ 1068 1069 /* 1070 * GPIO pins for twsi-connected devices, and device code for eeprom 1071 */ 1072 u8 gpio_sda_num; 1073 u8 gpio_scl_num; 1074 u8 twsi_eeprom_dev; 1075 u8 board_atten; 1076 1077 /* Support (including locks) for EEPROM logging of errors and time */ 1078 /* control access to actual counters, timer */ 1079 spinlock_t eep_st_lock; 1080 /* control high-level access to EEPROM */ 1081 struct mutex eep_lock; 1082 uint64_t traffic_wds; 1083 /* 1084 * masks for which bits of errs, hwerrs that cause 1085 * each of the counters to increment. 1086 */ 1087 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT]; 1088 struct qib_diag_client *diag_client; 1089 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1090 struct diag_observer_list_elt *diag_observer_list; 1091 1092 u8 psxmitwait_supported; 1093 /* cycle length of PS* counters in HW (in picoseconds) */ 1094 u16 psxmitwait_check_rate; 1095 /* high volume overflow errors defered to tasklet */ 1096 struct tasklet_struct error_tasklet; 1097 1098 int assigned_node_id; /* NUMA node closest to HCA */ 1099 }; 1100 1101 /* hol_state values */ 1102 #define QIB_HOL_UP 0 1103 #define QIB_HOL_INIT 1 1104 1105 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0) 1106 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1) 1107 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2) 1108 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3) 1109 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4) 1110 1111 /* operation types for f_txchk_change() */ 1112 #define TXCHK_CHG_TYPE_DIS1 3 1113 #define TXCHK_CHG_TYPE_ENAB1 2 1114 #define TXCHK_CHG_TYPE_KERN 1 1115 #define TXCHK_CHG_TYPE_USER 0 1116 1117 #define QIB_CHASE_TIME msecs_to_jiffies(145) 1118 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160) 1119 1120 /* Private data for file operations */ 1121 struct qib_filedata { 1122 struct qib_ctxtdata *rcd; 1123 unsigned subctxt; 1124 unsigned tidcursor; 1125 struct qib_user_sdma_queue *pq; 1126 int rec_cpu_num; /* for cpu affinity; -1 if none */ 1127 }; 1128 1129 extern struct list_head qib_dev_list; 1130 extern spinlock_t qib_devs_lock; 1131 extern struct qib_devdata *qib_lookup(int unit); 1132 extern u32 qib_cpulist_count; 1133 extern unsigned long *qib_cpulist; 1134 extern u16 qpt_mask; 1135 extern unsigned qib_cc_table_size; 1136 1137 int qib_init(struct qib_devdata *, int); 1138 int init_chip_wc_pat(struct qib_devdata *dd, u32); 1139 int qib_enable_wc(struct qib_devdata *dd); 1140 void qib_disable_wc(struct qib_devdata *dd); 1141 int qib_count_units(int *npresentp, int *nupp); 1142 int qib_count_active_units(void); 1143 1144 int qib_cdev_init(int minor, const char *name, 1145 const struct file_operations *fops, 1146 struct cdev **cdevp, struct device **devp); 1147 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp); 1148 int qib_dev_init(void); 1149 void qib_dev_cleanup(void); 1150 1151 int qib_diag_add(struct qib_devdata *); 1152 void qib_diag_remove(struct qib_devdata *); 1153 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64); 1154 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */ 1155 1156 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err); 1157 void qib_bad_intrstatus(struct qib_devdata *); 1158 void qib_handle_urcv(struct qib_devdata *, u64); 1159 1160 /* clean up any per-chip chip-specific stuff */ 1161 void qib_chip_cleanup(struct qib_devdata *); 1162 /* clean up any chip type-specific stuff */ 1163 void qib_chip_done(void); 1164 1165 /* check to see if we have to force ordering for write combining */ 1166 int qib_unordered_wc(void); 1167 void qib_pio_copy(void __iomem *to, const void *from, size_t count); 1168 1169 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned); 1170 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *); 1171 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned); 1172 void qib_cancel_sends(struct qib_pportdata *); 1173 1174 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *); 1175 int qib_setup_eagerbufs(struct qib_ctxtdata *); 1176 void qib_set_ctxtcnt(struct qib_devdata *); 1177 int qib_create_ctxts(struct qib_devdata *dd); 1178 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int); 1179 int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8); 1180 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *); 1181 1182 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *); 1183 int qib_reset_device(int); 1184 int qib_wait_linkstate(struct qib_pportdata *, u32, int); 1185 int qib_set_linkstate(struct qib_pportdata *, u8); 1186 int qib_set_mtu(struct qib_pportdata *, u16); 1187 int qib_set_lid(struct qib_pportdata *, u32, u8); 1188 void qib_hol_down(struct qib_pportdata *); 1189 void qib_hol_init(struct qib_pportdata *); 1190 void qib_hol_up(struct qib_pportdata *); 1191 void qib_hol_event(unsigned long); 1192 void qib_disable_after_error(struct qib_devdata *); 1193 int qib_set_uevent_bits(struct qib_pportdata *, const int); 1194 1195 /* for use in system calls, where we want to know device type, etc. */ 1196 #define ctxt_fp(fp) \ 1197 (((struct qib_filedata *)(fp)->private_data)->rcd) 1198 #define subctxt_fp(fp) \ 1199 (((struct qib_filedata *)(fp)->private_data)->subctxt) 1200 #define tidcursor_fp(fp) \ 1201 (((struct qib_filedata *)(fp)->private_data)->tidcursor) 1202 #define user_sdma_queue_fp(fp) \ 1203 (((struct qib_filedata *)(fp)->private_data)->pq) 1204 1205 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd) 1206 { 1207 return ppd->dd; 1208 } 1209 1210 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev) 1211 { 1212 return container_of(dev, struct qib_devdata, verbs_dev); 1213 } 1214 1215 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev) 1216 { 1217 return dd_from_dev(to_idev(ibdev)); 1218 } 1219 1220 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp) 1221 { 1222 return container_of(ibp, struct qib_pportdata, ibport_data); 1223 } 1224 1225 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port) 1226 { 1227 struct qib_devdata *dd = dd_from_ibdev(ibdev); 1228 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1229 1230 WARN_ON(pidx >= dd->num_pports); 1231 return &dd->pport[pidx].ibport_data; 1232 } 1233 1234 /* 1235 * values for dd->flags (_device_ related flags) and 1236 */ 1237 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */ 1238 #define QIB_INITTED 0x2 /* chip and driver up and initted */ 1239 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */ 1240 #define QIB_PRESENT 0x8 /* chip accesses can be done */ 1241 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */ 1242 #define QIB_HAS_THRESH_UPDATE 0x40 1243 #define QIB_HAS_SDMA_TIMEOUT 0x80 1244 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */ 1245 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */ 1246 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */ 1247 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */ 1248 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */ 1249 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */ 1250 #define QIB_BADINTR 0x8000 /* severe interrupt problems */ 1251 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */ 1252 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */ 1253 1254 /* 1255 * values for ppd->lflags (_ib_port_ related flags) 1256 */ 1257 #define QIBL_LINKV 0x1 /* IB link state valid */ 1258 #define QIBL_LINKDOWN 0x8 /* IB link is down */ 1259 #define QIBL_LINKINIT 0x10 /* IB link level is up */ 1260 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */ 1261 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */ 1262 /* leave a gap for more IB-link state */ 1263 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */ 1264 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */ 1265 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced, 1266 * Do not try to bring up */ 1267 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */ 1268 1269 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1270 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1) 1271 1272 1273 /* ctxt_flag bit offsets */ 1274 /* waiting for a packet to arrive */ 1275 #define QIB_CTXT_WAITING_RCV 2 1276 /* master has not finished initializing */ 1277 #define QIB_CTXT_MASTER_UNINIT 4 1278 /* waiting for an urgent packet to arrive */ 1279 #define QIB_CTXT_WAITING_URG 5 1280 1281 /* free up any allocated data at closes */ 1282 void qib_free_data(struct qib_ctxtdata *dd); 1283 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned, 1284 u32, struct qib_ctxtdata *); 1285 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *, 1286 const struct pci_device_id *); 1287 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *, 1288 const struct pci_device_id *); 1289 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *, 1290 const struct pci_device_id *); 1291 void qib_free_devdata(struct qib_devdata *); 1292 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra); 1293 1294 #define QIB_TWSI_NO_DEV 0xFF 1295 /* Below qib_twsi_ functions must be called with eep_lock held */ 1296 int qib_twsi_reset(struct qib_devdata *dd); 1297 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer, 1298 int len); 1299 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1300 const void *buffer, int len); 1301 void qib_get_eeprom_info(struct qib_devdata *); 1302 #define qib_inc_eeprom_err(dd, eidx, incr) 1303 void qib_dump_lookup_output_queue(struct qib_devdata *); 1304 void qib_force_pio_avail_update(struct qib_devdata *); 1305 void qib_clear_symerror_on_linkup(unsigned long opaque); 1306 1307 /* 1308 * Set LED override, only the two LSBs have "public" meaning, but 1309 * any non-zero value substitutes them for the Link and LinkTrain 1310 * LED states. 1311 */ 1312 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ 1313 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */ 1314 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); 1315 1316 /* send dma routines */ 1317 int qib_setup_sdma(struct qib_pportdata *); 1318 void qib_teardown_sdma(struct qib_pportdata *); 1319 void __qib_sdma_intr(struct qib_pportdata *); 1320 void qib_sdma_intr(struct qib_pportdata *); 1321 void qib_user_sdma_send_desc(struct qib_pportdata *dd, 1322 struct list_head *pktlist); 1323 int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *, 1324 u32, struct qib_verbs_txreq *); 1325 /* ppd->sdma_lock should be locked before calling this. */ 1326 int qib_sdma_make_progress(struct qib_pportdata *dd); 1327 1328 static inline int qib_sdma_empty(const struct qib_pportdata *ppd) 1329 { 1330 return ppd->sdma_descq_added == ppd->sdma_descq_removed; 1331 } 1332 1333 /* must be called under qib_sdma_lock */ 1334 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd) 1335 { 1336 return ppd->sdma_descq_cnt - 1337 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1; 1338 } 1339 1340 static inline int __qib_sdma_running(struct qib_pportdata *ppd) 1341 { 1342 return ppd->sdma_state.current_state == qib_sdma_state_s99_running; 1343 } 1344 int qib_sdma_running(struct qib_pportdata *); 1345 void dump_sdma_state(struct qib_pportdata *ppd); 1346 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1347 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1348 1349 /* 1350 * number of words used for protocol header if not set by qib_userinit(); 1351 */ 1352 #define QIB_DFLT_RCVHDRSIZE 9 1353 1354 /* 1355 * We need to be able to handle an IB header of at least 24 dwords. 1356 * We need the rcvhdrq large enough to handle largest IB header, but 1357 * still have room for a 2KB MTU standard IB packet. 1358 * Additionally, some processor/memory controller combinations 1359 * benefit quite strongly from having the DMA'ed data be cacheline 1360 * aligned and a cacheline multiple, so we set the size to 32 dwords 1361 * (2 64-byte primary cachelines for pretty much all processors of 1362 * interest). The alignment hurts nothing, other than using somewhat 1363 * more memory. 1364 */ 1365 #define QIB_RCVHDR_ENTSIZE 32 1366 1367 int qib_get_user_pages(unsigned long, size_t, struct page **); 1368 void qib_release_user_pages(struct page **, size_t); 1369 int qib_eeprom_read(struct qib_devdata *, u8, void *, int); 1370 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int); 1371 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32); 1372 void qib_sendbuf_done(struct qib_devdata *, unsigned); 1373 1374 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd) 1375 { 1376 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; 1377 } 1378 1379 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd) 1380 { 1381 /* 1382 * volatile because it's a DMA target from the chip, routine is 1383 * inlined, and don't want register caching or reordering. 1384 */ 1385 return (u32) le64_to_cpu( 1386 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */ 1387 } 1388 1389 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd) 1390 { 1391 const struct qib_devdata *dd = rcd->dd; 1392 u32 hdrqtail; 1393 1394 if (dd->flags & QIB_NODMA_RTAIL) { 1395 __le32 *rhf_addr; 1396 u32 seq; 1397 1398 rhf_addr = (__le32 *) rcd->rcvhdrq + 1399 rcd->head + dd->rhf_offset; 1400 seq = qib_hdrget_seq(rhf_addr); 1401 hdrqtail = rcd->head; 1402 if (seq == rcd->seq_cnt) 1403 hdrqtail++; 1404 } else 1405 hdrqtail = qib_get_rcvhdrtail(rcd); 1406 1407 return hdrqtail; 1408 } 1409 1410 /* 1411 * sysfs interface. 1412 */ 1413 1414 extern const char ib_qib_version[]; 1415 1416 int qib_device_create(struct qib_devdata *); 1417 void qib_device_remove(struct qib_devdata *); 1418 1419 int qib_create_port_files(struct ib_device *ibdev, u8 port_num, 1420 struct kobject *kobj); 1421 int qib_verbs_register_sysfs(struct qib_devdata *); 1422 void qib_verbs_unregister_sysfs(struct qib_devdata *); 1423 /* Hook for sysfs read of QSFP */ 1424 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len); 1425 1426 int __init qib_init_qibfs(void); 1427 int __exit qib_exit_qibfs(void); 1428 1429 int qibfs_add(struct qib_devdata *); 1430 int qibfs_remove(struct qib_devdata *); 1431 1432 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *); 1433 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *, 1434 const struct pci_device_id *); 1435 void qib_pcie_ddcleanup(struct qib_devdata *); 1436 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *); 1437 int qib_reinit_intr(struct qib_devdata *); 1438 void qib_enable_intx(struct pci_dev *); 1439 void qib_nomsi(struct qib_devdata *); 1440 void qib_nomsix(struct qib_devdata *); 1441 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1442 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 1443 /* interrupts for device */ 1444 u64 qib_int_counter(struct qib_devdata *); 1445 /* interrupt for all devices */ 1446 u64 qib_sps_ints(void); 1447 1448 /* 1449 * dma_addr wrappers - all 0's invalid for hw 1450 */ 1451 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long, 1452 size_t, int); 1453 const char *qib_get_unit_name(int unit); 1454 const char *qib_get_card_name(struct rvt_dev_info *rdi); 1455 struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi); 1456 1457 /* 1458 * Flush write combining store buffers (if present) and perform a write 1459 * barrier. 1460 */ 1461 static inline void qib_flush_wc(void) 1462 { 1463 #if defined(CONFIG_X86_64) 1464 asm volatile("sfence" : : : "memory"); 1465 #else 1466 wmb(); /* no reorder around wc flush */ 1467 #endif 1468 } 1469 1470 /* global module parameter variables */ 1471 extern unsigned qib_ibmtu; 1472 extern ushort qib_cfgctxts; 1473 extern ushort qib_num_cfg_vls; 1474 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */ 1475 extern unsigned qib_n_krcv_queues; 1476 extern unsigned qib_sdma_fetch_arb; 1477 extern unsigned qib_compat_ddr_negotiate; 1478 extern int qib_special_trigger; 1479 extern unsigned qib_numa_aware; 1480 1481 extern struct mutex qib_mutex; 1482 1483 /* Number of seconds before our card status check... */ 1484 #define STATUS_TIMEOUT 60 1485 1486 #define QIB_DRV_NAME "ib_qib" 1487 #define QIB_USER_MINOR_BASE 0 1488 #define QIB_TRACE_MINOR 127 1489 #define QIB_DIAGPKT_MINOR 128 1490 #define QIB_DIAG_MINOR_BASE 129 1491 #define QIB_NMINORS 255 1492 1493 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 1494 #define PCI_VENDOR_ID_QLOGIC 0x1077 1495 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10 1496 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220 1497 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322 1498 1499 /* 1500 * qib_early_err is used (only!) to print early errors before devdata is 1501 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1502 * cleanup when devdata may have been freed, etc. qib_dev_porterr is 1503 * the same as qib_dev_err, but is used when the message really needs 1504 * the IB port# to be definitive as to what's happening.. 1505 * All of these go to the trace log, and the trace log entry is done 1506 * first to avoid possible serial port delays from printk. 1507 */ 1508 #define qib_early_err(dev, fmt, ...) \ 1509 dev_err(dev, fmt, ##__VA_ARGS__) 1510 1511 #define qib_dev_err(dd, fmt, ...) \ 1512 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1513 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1514 1515 #define qib_dev_warn(dd, fmt, ...) \ 1516 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1517 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1518 1519 #define qib_dev_porterr(dd, port, fmt, ...) \ 1520 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ 1521 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \ 1522 ##__VA_ARGS__) 1523 1524 #define qib_devinfo(pcidev, fmt, ...) \ 1525 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__) 1526 1527 /* 1528 * this is used for formatting hw error messages... 1529 */ 1530 struct qib_hwerror_msgs { 1531 u64 mask; 1532 const char *msg; 1533 size_t sz; 1534 }; 1535 1536 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } 1537 1538 /* in qib_intr.c... */ 1539 void qib_format_hwerrors(u64 hwerrs, 1540 const struct qib_hwerror_msgs *hwerrmsgs, 1541 size_t nhwerrmsgs, char *msg, size_t lmsg); 1542 1543 void qib_stop_send_queue(struct rvt_qp *qp); 1544 void qib_quiesce_qp(struct rvt_qp *qp); 1545 void qib_flush_qp_waiters(struct rvt_qp *qp); 1546 int qib_mtu_to_path_mtu(u32 mtu); 1547 u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu); 1548 void qib_notify_error_qp(struct rvt_qp *qp); 1549 int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp, 1550 struct ib_qp_attr *attr); 1551 1552 #endif /* _QIB_KERNEL_H */ 1553