1f931551bSRalph Campbell #ifndef _QIB_KERNEL_H 2f931551bSRalph Campbell #define _QIB_KERNEL_H 3f931551bSRalph Campbell /* 4581d01aaSMichael J. Ruhl * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved. 5551ace12SMike Marciniszyn * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 6f931551bSRalph Campbell * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 7f931551bSRalph Campbell * 8f931551bSRalph Campbell * This software is available to you under a choice of one of two 9f931551bSRalph Campbell * licenses. You may choose to be licensed under the terms of the GNU 10f931551bSRalph Campbell * General Public License (GPL) Version 2, available from the file 11f931551bSRalph Campbell * COPYING in the main directory of this source tree, or the 12f931551bSRalph Campbell * OpenIB.org BSD license below: 13f931551bSRalph Campbell * 14f931551bSRalph Campbell * Redistribution and use in source and binary forms, with or 15f931551bSRalph Campbell * without modification, are permitted provided that the following 16f931551bSRalph Campbell * conditions are met: 17f931551bSRalph Campbell * 18f931551bSRalph Campbell * - Redistributions of source code must retain the above 19f931551bSRalph Campbell * copyright notice, this list of conditions and the following 20f931551bSRalph Campbell * disclaimer. 21f931551bSRalph Campbell * 22f931551bSRalph Campbell * - Redistributions in binary form must reproduce the above 23f931551bSRalph Campbell * copyright notice, this list of conditions and the following 24f931551bSRalph Campbell * disclaimer in the documentation and/or other materials 25f931551bSRalph Campbell * provided with the distribution. 26f931551bSRalph Campbell * 27f931551bSRalph Campbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28f931551bSRalph Campbell * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29f931551bSRalph Campbell * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30f931551bSRalph Campbell * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31f931551bSRalph Campbell * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32f931551bSRalph Campbell * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33f931551bSRalph Campbell * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34f931551bSRalph Campbell * SOFTWARE. 35f931551bSRalph Campbell */ 36f931551bSRalph Campbell 37f931551bSRalph Campbell /* 38f931551bSRalph Campbell * This header file is the base header file for qlogic_ib kernel code 39f931551bSRalph Campbell * qib_user.h serves a similar purpose for user code. 40f931551bSRalph Campbell */ 41f931551bSRalph Campbell 42f931551bSRalph Campbell #include <linux/interrupt.h> 43f931551bSRalph Campbell #include <linux/pci.h> 44f931551bSRalph Campbell #include <linux/dma-mapping.h> 45f931551bSRalph Campbell #include <linux/mutex.h> 46f931551bSRalph Campbell #include <linux/list.h> 47f931551bSRalph Campbell #include <linux/scatterlist.h> 48ba818afdSDavid Miller #include <linux/slab.h> 49f931551bSRalph Campbell #include <linux/io.h> 50f931551bSRalph Campbell #include <linux/fs.h> 51f931551bSRalph Campbell #include <linux/completion.h> 52f931551bSRalph Campbell #include <linux/kref.h> 53f931551bSRalph Campbell #include <linux/sched.h> 5485caafe3SMike Marciniszyn #include <linux/kthread.h> 55059d48fbSMatthew Wilcox #include <linux/xarray.h> 56261a4351SMike Marciniszyn #include <rdma/ib_hdrs.h> 572dc05ab5SDennis Dalessandro #include <rdma/rdma_vt.h> 58f931551bSRalph Campbell 59f931551bSRalph Campbell #include "qib_common.h" 60f931551bSRalph Campbell #include "qib_verbs.h" 61f931551bSRalph Campbell 62f931551bSRalph Campbell /* only s/w major version of QLogic_IB we can handle */ 63f931551bSRalph Campbell #define QIB_CHIP_VERS_MAJ 2U 64f931551bSRalph Campbell 65f931551bSRalph Campbell /* don't care about this except printing */ 66f931551bSRalph Campbell #define QIB_CHIP_VERS_MIN 0U 67f931551bSRalph Campbell 68f931551bSRalph Campbell /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 69f931551bSRalph Campbell #define QIB_OUI 0x001175 70f931551bSRalph Campbell #define QIB_OUI_LSB 40 71f931551bSRalph Campbell 72f931551bSRalph Campbell /* 73f931551bSRalph Campbell * per driver stats, either not device nor port-specific, or 74f931551bSRalph Campbell * summed over all of the devices and ports. 75f931551bSRalph Campbell * They are described by name via ipathfs filesystem, so layout 76f931551bSRalph Campbell * and number of elements can change without breaking compatibility. 77f931551bSRalph Campbell * If members are added or deleted qib_statnames[] in qib_fs.c must 78f931551bSRalph Campbell * change to match. 79f931551bSRalph Campbell */ 80f931551bSRalph Campbell struct qlogic_ib_stats { 81f931551bSRalph Campbell __u64 sps_ints; /* number of interrupts handled */ 82f931551bSRalph Campbell __u64 sps_errints; /* number of error interrupts */ 83f931551bSRalph Campbell __u64 sps_txerrs; /* tx-related packet errors */ 84f931551bSRalph Campbell __u64 sps_rcverrs; /* non-crc rcv packet errors */ 85f931551bSRalph Campbell __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 86f931551bSRalph Campbell __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 87f931551bSRalph Campbell __u64 sps_ctxts; /* number of contexts currently open */ 88f931551bSRalph Campbell __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 89f931551bSRalph Campbell __u64 sps_buffull; 90f931551bSRalph Campbell __u64 sps_hdrfull; 91f931551bSRalph Campbell }; 92f931551bSRalph Campbell 93f931551bSRalph Campbell extern struct qlogic_ib_stats qib_stats; 941d352035SStephen Hemminger extern const struct pci_error_handlers qib_pci_err_handler; 95f931551bSRalph Campbell 96f931551bSRalph Campbell #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ 97f931551bSRalph Campbell /* 98f931551bSRalph Campbell * First-cut critierion for "device is active" is 99f931551bSRalph Campbell * two thousand dwords combined Tx, Rx traffic per 100f931551bSRalph Campbell * 5-second interval. SMA packets are 64 dwords, 101f931551bSRalph Campbell * and occur "a few per second", presumably each way. 102f931551bSRalph Campbell */ 103f931551bSRalph Campbell #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 104f931551bSRalph Campbell 105f931551bSRalph Campbell /* 106f931551bSRalph Campbell * Below contains all data related to a single context (formerly called port). 107f931551bSRalph Campbell */ 108ddb88765SMike Marciniszyn 109ddb88765SMike Marciniszyn #ifdef CONFIG_DEBUG_FS 110ddb88765SMike Marciniszyn struct qib_opcode_stats_perctx; 111ddb88765SMike Marciniszyn #endif 112ddb88765SMike Marciniszyn 113f931551bSRalph Campbell struct qib_ctxtdata { 114f931551bSRalph Campbell void **rcvegrbuf; 115f931551bSRalph Campbell dma_addr_t *rcvegrbuf_phys; 116f931551bSRalph Campbell /* rcvhdrq base, needs mmap before useful */ 117f931551bSRalph Campbell void *rcvhdrq; 118f931551bSRalph Campbell /* kernel virtual address where hdrqtail is updated */ 119f931551bSRalph Campbell void *rcvhdrtail_kvaddr; 120f931551bSRalph Campbell /* 121f931551bSRalph Campbell * temp buffer for expected send setup, allocated at open, instead 122f931551bSRalph Campbell * of each setup call 123f931551bSRalph Campbell */ 124f931551bSRalph Campbell void *tid_pg_list; 125f931551bSRalph Campbell /* 126f931551bSRalph Campbell * Shared page for kernel to signal user processes that send buffers 127f931551bSRalph Campbell * need disarming. The process should call QIB_CMD_DISARM_BUFS 128f931551bSRalph Campbell * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 129f931551bSRalph Campbell */ 130f931551bSRalph Campbell unsigned long *user_event_mask; 131f931551bSRalph Campbell /* when waiting for rcv or pioavail */ 132f931551bSRalph Campbell wait_queue_head_t wait; 133f931551bSRalph Campbell /* 134f931551bSRalph Campbell * rcvegr bufs base, physical, must fit 135f931551bSRalph Campbell * in 44 bits so 32 bit programs mmap64 44 bit works) 136f931551bSRalph Campbell */ 137f931551bSRalph Campbell dma_addr_t rcvegr_phys; 138f931551bSRalph Campbell /* mmap of hdrq, must fit in 44 bits */ 139f931551bSRalph Campbell dma_addr_t rcvhdrq_phys; 140f931551bSRalph Campbell dma_addr_t rcvhdrqtailaddr_phys; 141f931551bSRalph Campbell 142f931551bSRalph Campbell /* 143f931551bSRalph Campbell * number of opens (including slave sub-contexts) on this instance 144f931551bSRalph Campbell * (ignoring forks, dup, etc. for now) 145f931551bSRalph Campbell */ 146f931551bSRalph Campbell int cnt; 147f931551bSRalph Campbell /* 148f931551bSRalph Campbell * how much space to leave at start of eager TID entries for 149f931551bSRalph Campbell * protocol use, on each TID 150f931551bSRalph Campbell */ 151f931551bSRalph Campbell /* instead of calculating it */ 152f931551bSRalph Campbell unsigned ctxt; 153e0f30bacSRamkrishna Vepa /* local node of context */ 154e0f30bacSRamkrishna Vepa int node_id; 155f931551bSRalph Campbell /* non-zero if ctxt is being shared. */ 156f931551bSRalph Campbell u16 subctxt_cnt; 157f931551bSRalph Campbell /* non-zero if ctxt is being shared. */ 158f931551bSRalph Campbell u16 subctxt_id; 159f931551bSRalph Campbell /* number of eager TID entries. */ 160f931551bSRalph Campbell u16 rcvegrcnt; 161f931551bSRalph Campbell /* index of first eager TID entry. */ 162f931551bSRalph Campbell u16 rcvegr_tid_base; 163f931551bSRalph Campbell /* number of pio bufs for this ctxt (all procs, if shared) */ 164f931551bSRalph Campbell u32 piocnt; 165f931551bSRalph Campbell /* first pio buffer for this ctxt */ 166f931551bSRalph Campbell u32 pio_base; 167f931551bSRalph Campbell /* chip offset of PIO buffers for this ctxt */ 168f931551bSRalph Campbell u32 piobufs; 169f931551bSRalph Campbell /* how many alloc_pages() chunks in rcvegrbuf_pages */ 170f931551bSRalph Campbell u32 rcvegrbuf_chunks; 171f931551bSRalph Campbell /* how many egrbufs per chunk */ 1729e1c0e43SMike Marciniszyn u16 rcvegrbufs_perchunk; 1739e1c0e43SMike Marciniszyn /* ilog2 of above */ 1749e1c0e43SMike Marciniszyn u16 rcvegrbufs_perchunk_shift; 175f931551bSRalph Campbell /* order for rcvegrbuf_pages */ 176f931551bSRalph Campbell size_t rcvegrbuf_size; 177f931551bSRalph Campbell /* rcvhdrq size (for freeing) */ 178f931551bSRalph Campbell size_t rcvhdrq_size; 179f931551bSRalph Campbell /* per-context flags for fileops/intr communication */ 180f931551bSRalph Campbell unsigned long flag; 181f931551bSRalph Campbell /* next expected TID to check when looking for free */ 182f931551bSRalph Campbell u32 tidcursor; 183f931551bSRalph Campbell /* WAIT_RCV that timed out, no interrupt */ 184f931551bSRalph Campbell u32 rcvwait_to; 185f931551bSRalph Campbell /* WAIT_PIO that timed out, no interrupt */ 186f931551bSRalph Campbell u32 piowait_to; 187f931551bSRalph Campbell /* WAIT_RCV already happened, no wait */ 188f931551bSRalph Campbell u32 rcvnowait; 189f931551bSRalph Campbell /* WAIT_PIO already happened, no wait */ 190f931551bSRalph Campbell u32 pionowait; 191f931551bSRalph Campbell /* total number of polled urgent packets */ 192f931551bSRalph Campbell u32 urgent; 193f931551bSRalph Campbell /* saved total number of polled urgent packets for poll edge trigger */ 194f931551bSRalph Campbell u32 urgent_poll; 195f931551bSRalph Campbell /* pid of process using this ctxt */ 196f931551bSRalph Campbell pid_t pid; 197f931551bSRalph Campbell pid_t subpid[QLOGIC_IB_MAX_SUBCTXT]; 198f931551bSRalph Campbell /* same size as task_struct .comm[], command that opened context */ 1997b6397d7SYafang Shao char comm[TASK_COMM_LEN]; 200f931551bSRalph Campbell /* pkeys set by this use of this ctxt */ 201f931551bSRalph Campbell u16 pkeys[4]; 202f931551bSRalph Campbell /* so file ops can get at unit */ 203f931551bSRalph Campbell struct qib_devdata *dd; 204f931551bSRalph Campbell /* so funcs that need physical port can get it easily */ 205f931551bSRalph Campbell struct qib_pportdata *ppd; 206f931551bSRalph Campbell /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 207f931551bSRalph Campbell void *subctxt_uregbase; 208f931551bSRalph Campbell /* An array of pages for the eager receive buffers * N */ 209f931551bSRalph Campbell void *subctxt_rcvegrbuf; 210f931551bSRalph Campbell /* An array of pages for the eager header queue entries * N */ 211f931551bSRalph Campbell void *subctxt_rcvhdr_base; 212f931551bSRalph Campbell /* The version of the library which opened this ctxt */ 213f931551bSRalph Campbell u32 userversion; 214f931551bSRalph Campbell /* Bitmask of active slaves */ 215f931551bSRalph Campbell u32 active_slaves; 216f931551bSRalph Campbell /* Type of packets or conditions we want to poll for */ 217f931551bSRalph Campbell u16 poll_type; 218f931551bSRalph Campbell /* receive packet sequence counter */ 219f931551bSRalph Campbell u8 seq_cnt; 220f931551bSRalph Campbell u8 redirect_seq_cnt; 221f931551bSRalph Campbell /* ctxt rcvhdrq head offset */ 222f931551bSRalph Campbell u32 head; 223f931551bSRalph Campbell /* QPs waiting for context processing */ 224f931551bSRalph Campbell struct list_head qp_wait_list; 225ddb88765SMike Marciniszyn #ifdef CONFIG_DEBUG_FS 226ddb88765SMike Marciniszyn /* verbs stats per CTX */ 227ddb88765SMike Marciniszyn struct qib_opcode_stats_perctx *opstats; 228ddb88765SMike Marciniszyn #endif 229f931551bSRalph Campbell }; 230f931551bSRalph Campbell 2317c2e11feSDennis Dalessandro struct rvt_sge_state; 232f931551bSRalph Campbell 233f931551bSRalph Campbell struct qib_sdma_txreq { 234f931551bSRalph Campbell int flags; 235f931551bSRalph Campbell int sg_count; 236f931551bSRalph Campbell dma_addr_t addr; 237f931551bSRalph Campbell void (*callback)(struct qib_sdma_txreq *, int); 238f931551bSRalph Campbell u16 start_idx; /* sdma private */ 239f931551bSRalph Campbell u16 next_descq_idx; /* sdma private */ 240f931551bSRalph Campbell struct list_head list; /* sdma private */ 241f931551bSRalph Campbell }; 242f931551bSRalph Campbell 243f931551bSRalph Campbell struct qib_sdma_desc { 244f931551bSRalph Campbell __le64 qw[2]; 245f931551bSRalph Campbell }; 246f931551bSRalph Campbell 247f931551bSRalph Campbell struct qib_verbs_txreq { 248f931551bSRalph Campbell struct qib_sdma_txreq txreq; 2497c2e11feSDennis Dalessandro struct rvt_qp *qp; 2507c2e11feSDennis Dalessandro struct rvt_swqe *wqe; 251f931551bSRalph Campbell u32 dwords; 252f931551bSRalph Campbell u16 hdr_dwords; 253f931551bSRalph Campbell u16 hdr_inx; 254f931551bSRalph Campbell struct qib_pio_header *align_buf; 2557c2e11feSDennis Dalessandro struct rvt_mregion *mr; 2567c2e11feSDennis Dalessandro struct rvt_sge_state *ss; 257f931551bSRalph Campbell }; 258f931551bSRalph Campbell 259f931551bSRalph Campbell #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1 260f931551bSRalph Campbell #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2 261f931551bSRalph Campbell #define QIB_SDMA_TXREQ_F_INTREQ 0x4 262f931551bSRalph Campbell #define QIB_SDMA_TXREQ_F_FREEBUF 0x8 263f931551bSRalph Campbell #define QIB_SDMA_TXREQ_F_FREEDESC 0x10 264f931551bSRalph Campbell 265f931551bSRalph Campbell #define QIB_SDMA_TXREQ_S_OK 0 266f931551bSRalph Campbell #define QIB_SDMA_TXREQ_S_SENDERROR 1 267f931551bSRalph Campbell #define QIB_SDMA_TXREQ_S_ABORTED 2 268f931551bSRalph Campbell #define QIB_SDMA_TXREQ_S_SHUTDOWN 3 269f931551bSRalph Campbell 270f931551bSRalph Campbell /* 271f931551bSRalph Campbell * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 272f931551bSRalph Campbell * Mostly for MADs that set or query link parameters, also ipath 273f931551bSRalph Campbell * config interfaces 274f931551bSRalph Campbell */ 275f931551bSRalph Campbell #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 276f931551bSRalph Campbell #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 277f931551bSRalph Campbell #define QIB_IB_CFG_LWID 3 /* currently active Link-width */ 278f931551bSRalph Campbell #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 279f931551bSRalph Campbell #define QIB_IB_CFG_SPD 5 /* current Link spd */ 280f931551bSRalph Campbell #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 281f931551bSRalph Campbell #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 282f931551bSRalph Campbell #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 283f931551bSRalph Campbell #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 284f931551bSRalph Campbell #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */ 285f931551bSRalph Campbell #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 286f931551bSRalph Campbell #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 287f931551bSRalph Campbell #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 288f931551bSRalph Campbell #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 289f931551bSRalph Campbell #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 290f931551bSRalph Campbell #define QIB_IB_CFG_PKEYS 16 /* update partition keys */ 291f931551bSRalph Campbell #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */ 292f931551bSRalph Campbell #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */ 293f931551bSRalph Campbell #define QIB_IB_CFG_VL_HIGH_LIMIT 19 294f931551bSRalph Campbell #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 295f931551bSRalph Campbell #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */ 296f931551bSRalph Campbell 297f931551bSRalph Campbell /* 298f931551bSRalph Campbell * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16 299f931551bSRalph Campbell * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for 300f931551bSRalph Campbell * QIB_IB_CFG_LINKDEFAULT cmd 301f931551bSRalph Campbell */ 302f931551bSRalph Campbell #define IB_LINKCMD_DOWN (0 << 16) 303f931551bSRalph Campbell #define IB_LINKCMD_ARMED (1 << 16) 304f931551bSRalph Campbell #define IB_LINKCMD_ACTIVE (2 << 16) 305f931551bSRalph Campbell #define IB_LINKINITCMD_NOP 0 306f931551bSRalph Campbell #define IB_LINKINITCMD_POLL 1 307f931551bSRalph Campbell #define IB_LINKINITCMD_SLEEP 2 308f931551bSRalph Campbell #define IB_LINKINITCMD_DISABLE 3 309f931551bSRalph Campbell 310f931551bSRalph Campbell /* 311f931551bSRalph Campbell * valid states passed to qib_set_linkstate() user call 312f931551bSRalph Campbell */ 313f931551bSRalph Campbell #define QIB_IB_LINKDOWN 0 314f931551bSRalph Campbell #define QIB_IB_LINKARM 1 315f931551bSRalph Campbell #define QIB_IB_LINKACTIVE 2 316f931551bSRalph Campbell #define QIB_IB_LINKDOWN_ONLY 3 317f931551bSRalph Campbell #define QIB_IB_LINKDOWN_SLEEP 4 318f931551bSRalph Campbell #define QIB_IB_LINKDOWN_DISABLE 5 319f931551bSRalph Campbell 320f931551bSRalph Campbell /* 321f931551bSRalph Campbell * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed 322f931551bSRalph Campbell * negotiation) are used for the 3rd argument to path_f_set_ib_cfg 323f931551bSRalph Campbell * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They 324*ca325edbSSlark Xiao * are also the possible values for qib_link_speed_enabled and active 325f931551bSRalph Campbell * The values were chosen to match values used within the IB spec. 326f931551bSRalph Campbell */ 327f931551bSRalph Campbell #define QIB_IB_SDR 1 328f931551bSRalph Campbell #define QIB_IB_DDR 2 329f931551bSRalph Campbell #define QIB_IB_QDR 4 330f931551bSRalph Campbell 331f931551bSRalph Campbell #define QIB_DEFAULT_MTU 4096 332f931551bSRalph Campbell 333cc323b2aSRalph Campbell /* max number of IB ports supported per HCA */ 334cc323b2aSRalph Campbell #define QIB_MAX_IB_PORTS 2 335cc323b2aSRalph Campbell 336f931551bSRalph Campbell /* 337f931551bSRalph Campbell * Possible IB config parameters for f_get/set_ib_table() 338f931551bSRalph Campbell */ 339f931551bSRalph Campbell #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */ 340f931551bSRalph Campbell #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */ 341f931551bSRalph Campbell 342f931551bSRalph Campbell /* 343f931551bSRalph Campbell * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 344f931551bSRalph Campbell * these are bits so they can be combined, e.g. 345f931551bSRalph Campbell * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB 346f931551bSRalph Campbell */ 347f931551bSRalph Campbell #define QIB_RCVCTRL_TAILUPD_ENB 0x01 348f931551bSRalph Campbell #define QIB_RCVCTRL_TAILUPD_DIS 0x02 349f931551bSRalph Campbell #define QIB_RCVCTRL_CTXT_ENB 0x04 350f931551bSRalph Campbell #define QIB_RCVCTRL_CTXT_DIS 0x08 351f931551bSRalph Campbell #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10 352f931551bSRalph Campbell #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20 353f931551bSRalph Campbell #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 354f931551bSRalph Campbell #define QIB_RCVCTRL_PKEY_DIS 0x80 355f931551bSRalph Campbell #define QIB_RCVCTRL_BP_ENB 0x0100 356f931551bSRalph Campbell #define QIB_RCVCTRL_BP_DIS 0x0200 357f931551bSRalph Campbell #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400 358f931551bSRalph Campbell #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800 359f931551bSRalph Campbell 360f931551bSRalph Campbell /* 361f931551bSRalph Campbell * Possible "operations" for f_sendctrl(ppd, op, var) 362f931551bSRalph Campbell * these are bits so they can be combined, e.g. 363f931551bSRalph Campbell * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB 364f931551bSRalph Campbell * Some operations (e.g. DISARM, ABORT) are known to 365f931551bSRalph Campbell * be "one-shot", so do not modify shadow. 366f931551bSRalph Campbell */ 367f931551bSRalph Campbell #define QIB_SENDCTRL_DISARM (0x1000) 368f931551bSRalph Campbell #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM) 369f931551bSRalph Campbell /* available (0x2000) */ 370f931551bSRalph Campbell #define QIB_SENDCTRL_AVAIL_DIS (0x4000) 371f931551bSRalph Campbell #define QIB_SENDCTRL_AVAIL_ENB (0x8000) 372f931551bSRalph Campbell #define QIB_SENDCTRL_AVAIL_BLIP (0x10000) 373f931551bSRalph Campbell #define QIB_SENDCTRL_SEND_DIS (0x20000) 374f931551bSRalph Campbell #define QIB_SENDCTRL_SEND_ENB (0x40000) 375f931551bSRalph Campbell #define QIB_SENDCTRL_FLUSH (0x80000) 376f931551bSRalph Campbell #define QIB_SENDCTRL_CLEAR (0x100000) 377f931551bSRalph Campbell #define QIB_SENDCTRL_DISARM_ALL (0x200000) 378f931551bSRalph Campbell 379f931551bSRalph Campbell /* 380f931551bSRalph Campbell * These are the generic indices for requesting per-port 381f931551bSRalph Campbell * counter values via the f_portcntr function. They 382f931551bSRalph Campbell * are always returned as 64 bit values, although most 383f931551bSRalph Campbell * are 32 bit counters. 384f931551bSRalph Campbell */ 385f931551bSRalph Campbell /* send-related counters */ 386f931551bSRalph Campbell #define QIBPORTCNTR_PKTSEND 0U 387f931551bSRalph Campbell #define QIBPORTCNTR_WORDSEND 1U 388f931551bSRalph Campbell #define QIBPORTCNTR_PSXMITDATA 2U 389f931551bSRalph Campbell #define QIBPORTCNTR_PSXMITPKTS 3U 390f931551bSRalph Campbell #define QIBPORTCNTR_PSXMITWAIT 4U 391f931551bSRalph Campbell #define QIBPORTCNTR_SENDSTALL 5U 392f931551bSRalph Campbell /* receive-related counters */ 393f931551bSRalph Campbell #define QIBPORTCNTR_PKTRCV 6U 394f931551bSRalph Campbell #define QIBPORTCNTR_PSRCVDATA 7U 395f931551bSRalph Campbell #define QIBPORTCNTR_PSRCVPKTS 8U 396f931551bSRalph Campbell #define QIBPORTCNTR_RCVEBP 9U 397f931551bSRalph Campbell #define QIBPORTCNTR_RCVOVFL 10U 398f931551bSRalph Campbell #define QIBPORTCNTR_WORDRCV 11U 399f931551bSRalph Campbell /* IB link related error counters */ 400f931551bSRalph Campbell #define QIBPORTCNTR_RXLOCALPHYERR 12U 401f931551bSRalph Campbell #define QIBPORTCNTR_RXVLERR 13U 402f931551bSRalph Campbell #define QIBPORTCNTR_ERRICRC 14U 403f931551bSRalph Campbell #define QIBPORTCNTR_ERRVCRC 15U 404f931551bSRalph Campbell #define QIBPORTCNTR_ERRLPCRC 16U 405f931551bSRalph Campbell #define QIBPORTCNTR_BADFORMAT 17U 406f931551bSRalph Campbell #define QIBPORTCNTR_ERR_RLEN 18U 407f931551bSRalph Campbell #define QIBPORTCNTR_IBSYMBOLERR 19U 408f931551bSRalph Campbell #define QIBPORTCNTR_INVALIDRLEN 20U 409f931551bSRalph Campbell #define QIBPORTCNTR_UNSUPVL 21U 410f931551bSRalph Campbell #define QIBPORTCNTR_EXCESSBUFOVFL 22U 411f931551bSRalph Campbell #define QIBPORTCNTR_ERRLINK 23U 412f931551bSRalph Campbell #define QIBPORTCNTR_IBLINKDOWN 24U 413f931551bSRalph Campbell #define QIBPORTCNTR_IBLINKERRRECOV 25U 414f931551bSRalph Campbell #define QIBPORTCNTR_LLI 26U 415f931551bSRalph Campbell /* other error counters */ 416f931551bSRalph Campbell #define QIBPORTCNTR_RXDROPPKT 27U 417f931551bSRalph Campbell #define QIBPORTCNTR_VL15PKTDROP 28U 418f931551bSRalph Campbell #define QIBPORTCNTR_ERRPKEY 29U 419f931551bSRalph Campbell #define QIBPORTCNTR_KHDROVFL 30U 420f931551bSRalph Campbell /* sampling counters (these are actually control registers) */ 421f931551bSRalph Campbell #define QIBPORTCNTR_PSINTERVAL 31U 422f931551bSRalph Campbell #define QIBPORTCNTR_PSSTART 32U 423f931551bSRalph Campbell #define QIBPORTCNTR_PSSTAT 33U 424f931551bSRalph Campbell 425f931551bSRalph Campbell /* how often we check for packet activity for "power on hours (in seconds) */ 426f931551bSRalph Campbell #define ACTIVITY_TIMER 5 427f931551bSRalph Campbell 428a778f3fdSMike Marciniszyn #define MAX_NAME_SIZE 64 4298469ba39SMike Marciniszyn 4308469ba39SMike Marciniszyn #ifdef CONFIG_INFINIBAND_QIB_DCA 4318469ba39SMike Marciniszyn struct qib_irq_notify; 4328469ba39SMike Marciniszyn #endif 4338469ba39SMike Marciniszyn 434a778f3fdSMike Marciniszyn struct qib_msix_entry { 435a778f3fdSMike Marciniszyn void *arg; 4368469ba39SMike Marciniszyn #ifdef CONFIG_INFINIBAND_QIB_DCA 4378469ba39SMike Marciniszyn int dca; 4388469ba39SMike Marciniszyn int rcv; 4398469ba39SMike Marciniszyn struct qib_irq_notify *notifier; 4408469ba39SMike Marciniszyn #endif 441a778f3fdSMike Marciniszyn cpumask_var_t mask; 442a778f3fdSMike Marciniszyn }; 443a778f3fdSMike Marciniszyn 444f931551bSRalph Campbell /* Below is an opaque struct. Each chip (device) can maintain 445f931551bSRalph Campbell * private data needed for its operation, but not germane to the 446f931551bSRalph Campbell * rest of the driver. For convenience, we define another that 447f931551bSRalph Campbell * is chip-specific, per-port 448f931551bSRalph Campbell */ 449f931551bSRalph Campbell struct qib_chip_specific; 450f931551bSRalph Campbell struct qib_chipport_specific; 451f931551bSRalph Campbell 452f931551bSRalph Campbell enum qib_sdma_states { 453f931551bSRalph Campbell qib_sdma_state_s00_hw_down, 454f931551bSRalph Campbell qib_sdma_state_s10_hw_start_up_wait, 455f931551bSRalph Campbell qib_sdma_state_s20_idle, 456f931551bSRalph Campbell qib_sdma_state_s30_sw_clean_up_wait, 457f931551bSRalph Campbell qib_sdma_state_s40_hw_clean_up_wait, 458f931551bSRalph Campbell qib_sdma_state_s50_hw_halt_wait, 459f931551bSRalph Campbell qib_sdma_state_s99_running, 460f931551bSRalph Campbell }; 461f931551bSRalph Campbell 462f931551bSRalph Campbell enum qib_sdma_events { 463f931551bSRalph Campbell qib_sdma_event_e00_go_hw_down, 464f931551bSRalph Campbell qib_sdma_event_e10_go_hw_start, 465f931551bSRalph Campbell qib_sdma_event_e20_hw_started, 466f931551bSRalph Campbell qib_sdma_event_e30_go_running, 467f931551bSRalph Campbell qib_sdma_event_e40_sw_cleaned, 468f931551bSRalph Campbell qib_sdma_event_e50_hw_cleaned, 469f931551bSRalph Campbell qib_sdma_event_e60_hw_halted, 470f931551bSRalph Campbell qib_sdma_event_e70_go_idle, 471f931551bSRalph Campbell qib_sdma_event_e7220_err_halted, 472f931551bSRalph Campbell qib_sdma_event_e7322_err_halted, 473f931551bSRalph Campbell qib_sdma_event_e90_timer_tick, 474f931551bSRalph Campbell }; 475f931551bSRalph Campbell 476f931551bSRalph Campbell struct sdma_set_state_action { 477f931551bSRalph Campbell unsigned op_enable:1; 478f931551bSRalph Campbell unsigned op_intenable:1; 479f931551bSRalph Campbell unsigned op_halt:1; 480f931551bSRalph Campbell unsigned op_drain:1; 481f931551bSRalph Campbell unsigned go_s99_running_tofalse:1; 482f931551bSRalph Campbell unsigned go_s99_running_totrue:1; 483f931551bSRalph Campbell }; 484f931551bSRalph Campbell 485f931551bSRalph Campbell struct qib_sdma_state { 486f931551bSRalph Campbell struct kref kref; 487f931551bSRalph Campbell struct completion comp; 488f931551bSRalph Campbell enum qib_sdma_states current_state; 489f931551bSRalph Campbell struct sdma_set_state_action *set_state_action; 490f931551bSRalph Campbell unsigned current_op; 491f931551bSRalph Campbell unsigned go_s99_running; 492f931551bSRalph Campbell unsigned first_sendbuf; 493f931551bSRalph Campbell unsigned last_sendbuf; /* really last +1 */ 494f931551bSRalph Campbell /* debugging/devel */ 495f931551bSRalph Campbell enum qib_sdma_states previous_state; 496f931551bSRalph Campbell unsigned previous_op; 497f931551bSRalph Campbell enum qib_sdma_events last_event; 498f931551bSRalph Campbell }; 499f931551bSRalph Campbell 500f931551bSRalph Campbell struct xmit_wait { 501f931551bSRalph Campbell struct timer_list timer; 502f931551bSRalph Campbell u64 counter; 503f931551bSRalph Campbell u8 flags; 504f931551bSRalph Campbell struct cache { 505f931551bSRalph Campbell u64 psxmitdata; 506f931551bSRalph Campbell u64 psrcvdata; 507f931551bSRalph Campbell u64 psxmitpkts; 508f931551bSRalph Campbell u64 psrcvpkts; 509f931551bSRalph Campbell u64 psxmitwait; 510f931551bSRalph Campbell } counter_cache; 511f931551bSRalph Campbell }; 512f931551bSRalph Campbell 513f931551bSRalph Campbell /* 514f931551bSRalph Campbell * The structure below encapsulates data relevant to a physical IB Port. 515f931551bSRalph Campbell * Current chips support only one such port, but the separation 516f931551bSRalph Campbell * clarifies things a bit. Note that to conform to IB conventions, 517f931551bSRalph Campbell * port-numbers are one-based. The first or only port is port1. 518f931551bSRalph Campbell */ 519f931551bSRalph Campbell struct qib_pportdata { 520f931551bSRalph Campbell struct qib_ibport ibport_data; 521f931551bSRalph Campbell 522f931551bSRalph Campbell struct qib_devdata *dd; 523f931551bSRalph Campbell struct qib_chippport_specific *cpspec; /* chip-specific per-port */ 524f931551bSRalph Campbell 525f931551bSRalph Campbell /* GUID for this interface, in network order */ 526f931551bSRalph Campbell __be64 guid; 527f931551bSRalph Campbell 528f931551bSRalph Campbell /* QIB_POLL, etc. link-state specific flags, per port */ 529f931551bSRalph Campbell u32 lflags; 530f931551bSRalph Campbell /* qib_lflags driver is waiting for */ 531f931551bSRalph Campbell u32 state_wanted; 532f931551bSRalph Campbell spinlock_t lflags_lock; 533f931551bSRalph Campbell 534f931551bSRalph Campbell /* ref count for each pkey */ 535f931551bSRalph Campbell atomic_t pkeyrefs[4]; 536f931551bSRalph Campbell 537f931551bSRalph Campbell /* 538f931551bSRalph Campbell * this address is mapped readonly into user processes so they can 539f931551bSRalph Campbell * get status cheaply, whenever they want. One qword of status per port 540f931551bSRalph Campbell */ 541f931551bSRalph Campbell u64 *statusp; 542f931551bSRalph Campbell 543f931551bSRalph Campbell /* SendDMA related entries */ 544f931551bSRalph Campbell 5451c94283dSMike Marciniszyn /* read mostly */ 5461c94283dSMike Marciniszyn struct qib_sdma_desc *sdma_descq; 547551ace12SMike Marciniszyn struct workqueue_struct *qib_wq; 5481c94283dSMike Marciniszyn struct qib_sdma_state sdma_state; 549f931551bSRalph Campbell dma_addr_t sdma_descq_phys; 550f931551bSRalph Campbell volatile __le64 *sdma_head_dma; /* DMA'ed by chip */ 551f931551bSRalph Campbell dma_addr_t sdma_head_phys; 5521c94283dSMike Marciniszyn u16 sdma_descq_cnt; 5531c94283dSMike Marciniszyn 5541c94283dSMike Marciniszyn /* read/write using lock */ 5551c94283dSMike Marciniszyn spinlock_t sdma_lock ____cacheline_aligned_in_smp; 5561c94283dSMike Marciniszyn struct list_head sdma_activelist; 5574668e4b5SCQ Tang struct list_head sdma_userpending; 5581c94283dSMike Marciniszyn u64 sdma_descq_added; 5591c94283dSMike Marciniszyn u64 sdma_descq_removed; 5601c94283dSMike Marciniszyn u16 sdma_descq_tail; 5611c94283dSMike Marciniszyn u16 sdma_descq_head; 5621c94283dSMike Marciniszyn u8 sdma_generation; 5634668e4b5SCQ Tang u8 sdma_intrequest; 5641c94283dSMike Marciniszyn 5651c94283dSMike Marciniszyn struct tasklet_struct sdma_sw_clean_up_task 5661c94283dSMike Marciniszyn ____cacheline_aligned_in_smp; 567f931551bSRalph Campbell 568f931551bSRalph Campbell wait_queue_head_t state_wait; /* for state_wanted */ 569f931551bSRalph Campbell 570f931551bSRalph Campbell /* HoL blocking for SMP replies */ 571f931551bSRalph Campbell unsigned hol_state; 572f931551bSRalph Campbell struct timer_list hol_timer; 573f931551bSRalph Campbell 574f931551bSRalph Campbell /* 575f931551bSRalph Campbell * Shadow copies of registers; size indicates read access size. 576f931551bSRalph Campbell * Most of them are readonly, but some are write-only register, 577f931551bSRalph Campbell * where we manipulate the bits in the shadow copy, and then write 578f931551bSRalph Campbell * the shadow copy to qlogic_ib. 579f931551bSRalph Campbell * 580f931551bSRalph Campbell * We deliberately make most of these 32 bits, since they have 581f931551bSRalph Campbell * restricted range. For any that we read, we won't to generate 32 582f931551bSRalph Campbell * bit accesses, since Opteron will generate 2 separate 32 bit HT 583f931551bSRalph Campbell * transactions for a 64 bit read, and we want to avoid unnecessary 584f931551bSRalph Campbell * bus transactions. 585f931551bSRalph Campbell */ 586f931551bSRalph Campbell 587f931551bSRalph Campbell /* This is the 64 bit group */ 588f931551bSRalph Campbell /* last ibcstatus. opaque outside chip-specific code */ 589f931551bSRalph Campbell u64 lastibcstat; 590f931551bSRalph Campbell 591f931551bSRalph Campbell /* these are the "32 bit" regs */ 592f931551bSRalph Campbell 593f931551bSRalph Campbell /* 594f931551bSRalph Campbell * the following two are 32-bit bitmasks, but {test,clear,set}_bit 595f931551bSRalph Campbell * all expect bit fields to be "unsigned long" 596f931551bSRalph Campbell */ 597f931551bSRalph Campbell unsigned long p_rcvctrl; /* shadow per-port rcvctrl */ 598f931551bSRalph Campbell unsigned long p_sendctrl; /* shadow per-port sendctrl */ 599f931551bSRalph Campbell 600f931551bSRalph Campbell u32 ibmtu; /* The MTU programmed for this unit */ 601f931551bSRalph Campbell /* 602f931551bSRalph Campbell * Current max size IB packet (in bytes) including IB headers, that 603f931551bSRalph Campbell * we can send. Changes when ibmtu changes. 604f931551bSRalph Campbell */ 605f931551bSRalph Campbell u32 ibmaxlen; 606f931551bSRalph Campbell /* 607f931551bSRalph Campbell * ibmaxlen at init time, limited by chip and by receive buffer 608f931551bSRalph Campbell * size. Not changed after init. 609f931551bSRalph Campbell */ 610f931551bSRalph Campbell u32 init_ibmaxlen; 611f931551bSRalph Campbell /* LID programmed for this instance */ 612f931551bSRalph Campbell u16 lid; 613f931551bSRalph Campbell /* list of pkeys programmed; 0 if not set */ 614f931551bSRalph Campbell u16 pkeys[4]; 615f931551bSRalph Campbell /* LID mask control */ 616f931551bSRalph Campbell u8 lmc; 617f931551bSRalph Campbell u8 link_width_supported; 618376ceb31SAharon Landau u16 link_speed_supported; 619f931551bSRalph Campbell u8 link_width_enabled; 620376ceb31SAharon Landau u16 link_speed_enabled; 621f931551bSRalph Campbell u8 link_width_active; 622376ceb31SAharon Landau u16 link_speed_active; 623f931551bSRalph Campbell u8 vls_supported; 624f931551bSRalph Campbell u8 vls_operational; 625f931551bSRalph Campbell /* Rx Polarity inversion (compensate for ~tx on partner) */ 626f931551bSRalph Campbell u8 rx_pol_inv; 627f931551bSRalph Campbell 628f931551bSRalph Campbell u8 hw_pidx; /* physical port index */ 6291fb7f897SMark Bloch u32 port; /* IB port number and index into dd->pports - 1 */ 630f931551bSRalph Campbell 631f931551bSRalph Campbell u8 delay_mult; 632f931551bSRalph Campbell 633f931551bSRalph Campbell /* used to override LED behavior */ 634f931551bSRalph Campbell u8 led_override; /* Substituted for normal value, if non-zero */ 635f931551bSRalph Campbell u16 led_override_timeoff; /* delta to next timer event */ 636f931551bSRalph Campbell u8 led_override_vals[2]; /* Alternates per blink-frame */ 637f931551bSRalph Campbell u8 led_override_phase; /* Just counts, LSB picks from vals[] */ 638f931551bSRalph Campbell atomic_t led_override_timer_active; 639f931551bSRalph Campbell /* Used to flash LEDs in override mode */ 640f931551bSRalph Campbell struct timer_list led_override_timer; 641f931551bSRalph Campbell struct xmit_wait cong_stats; 642f931551bSRalph Campbell struct timer_list symerr_clear_timer; 64336a8f01cSMike Marciniszyn 64436a8f01cSMike Marciniszyn /* Synchronize access between driver writes and sysfs reads */ 64536a8f01cSMike Marciniszyn spinlock_t cc_shadow_lock 64636a8f01cSMike Marciniszyn ____cacheline_aligned_in_smp; 64736a8f01cSMike Marciniszyn 64836a8f01cSMike Marciniszyn /* Shadow copy of the congestion control table */ 64936a8f01cSMike Marciniszyn struct cc_table_shadow *ccti_entries_shadow; 65036a8f01cSMike Marciniszyn 65136a8f01cSMike Marciniszyn /* Shadow copy of the congestion control entries */ 65236a8f01cSMike Marciniszyn struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow; 65336a8f01cSMike Marciniszyn 65436a8f01cSMike Marciniszyn /* List of congestion control table entries */ 65536a8f01cSMike Marciniszyn struct ib_cc_table_entry_shadow *ccti_entries; 65636a8f01cSMike Marciniszyn 65736a8f01cSMike Marciniszyn /* 16 congestion entries with each entry corresponding to a SL */ 65836a8f01cSMike Marciniszyn struct ib_cc_congestion_entry_shadow *congestion_entries; 65936a8f01cSMike Marciniszyn 6605d7fe4efSMike Marciniszyn /* Maximum number of congestion control entries that the agent expects 6615d7fe4efSMike Marciniszyn * the manager to send. 6625d7fe4efSMike Marciniszyn */ 6635d7fe4efSMike Marciniszyn u16 cc_supported_table_entries; 6645d7fe4efSMike Marciniszyn 66536a8f01cSMike Marciniszyn /* Total number of congestion control table entries */ 66636a8f01cSMike Marciniszyn u16 total_cct_entry; 66736a8f01cSMike Marciniszyn 66836a8f01cSMike Marciniszyn /* Bit map identifying service level */ 66936a8f01cSMike Marciniszyn u16 cc_sl_control_map; 67036a8f01cSMike Marciniszyn 67136a8f01cSMike Marciniszyn /* maximum congestion control table index */ 67236a8f01cSMike Marciniszyn u16 ccti_limit; 67336a8f01cSMike Marciniszyn 67436a8f01cSMike Marciniszyn /* CA's max number of 64 entry units in the congestion control table */ 67536a8f01cSMike Marciniszyn u8 cc_max_table_entries; 676f931551bSRalph Campbell }; 677f931551bSRalph Campbell 678f931551bSRalph Campbell /* Observers. Not to be taken lightly, possibly not to ship. */ 679f931551bSRalph Campbell /* 680f931551bSRalph Campbell * If a diag read or write is to (bottom <= offset <= top), 68125ec8b35SJulia Lawall * the "hook" is called, allowing, e.g. shadows to be 682f931551bSRalph Campbell * updated in sync with the driver. struct diag_observer 683f931551bSRalph Campbell * is the "visible" part. 684f931551bSRalph Campbell */ 685f931551bSRalph Campbell struct diag_observer; 686f931551bSRalph Campbell 687f931551bSRalph Campbell typedef int (*diag_hook) (struct qib_devdata *dd, 688f931551bSRalph Campbell const struct diag_observer *op, 689f931551bSRalph Campbell u32 offs, u64 *data, u64 mask, int only_32); 690f931551bSRalph Campbell 691f931551bSRalph Campbell struct diag_observer { 692f931551bSRalph Campbell diag_hook hook; 693f931551bSRalph Campbell u32 bottom; 694f931551bSRalph Campbell u32 top; 695f931551bSRalph Campbell }; 696f931551bSRalph Campbell 697f931551bSRalph Campbell extern int qib_register_observer(struct qib_devdata *dd, 698f931551bSRalph Campbell const struct diag_observer *op); 699f931551bSRalph Campbell 700f931551bSRalph Campbell /* Only declared here, not defined. Private to diags */ 701f931551bSRalph Campbell struct diag_observer_list_elt; 702f931551bSRalph Campbell 703f931551bSRalph Campbell /* device data struct now contains only "general per-device" info. 704f931551bSRalph Campbell * fields related to a physical IB port are in a qib_pportdata struct, 70525985edcSLucas De Marchi * described above) while fields only used by a particular chip-type are in 706f931551bSRalph Campbell * a qib_chipdata struct, whose contents are opaque to this file. 707f931551bSRalph Campbell */ 708f931551bSRalph Campbell struct qib_devdata { 709f931551bSRalph Campbell struct qib_ibdev verbs_dev; /* must be first */ 710f931551bSRalph Campbell struct list_head list; 711f931551bSRalph Campbell /* pointers to related structs for this device */ 712f931551bSRalph Campbell /* pci access data structure */ 713f931551bSRalph Campbell struct pci_dev *pcidev; 714f931551bSRalph Campbell struct cdev *user_cdev; 715f931551bSRalph Campbell struct cdev *diag_cdev; 716f931551bSRalph Campbell struct device *user_device; 717f931551bSRalph Campbell struct device *diag_device; 718f931551bSRalph Campbell 719f931551bSRalph Campbell /* mem-mapped pointer to base of chip regs */ 720f931551bSRalph Campbell u64 __iomem *kregbase; 721f931551bSRalph Campbell /* end of mem-mapped chip space excluding sendbuf and user regs */ 722f931551bSRalph Campbell u64 __iomem *kregend; 723f931551bSRalph Campbell /* physical address of chip for io_remap, etc. */ 724f931551bSRalph Campbell resource_size_t physaddr; 725f931551bSRalph Campbell /* qib_cfgctxts pointers */ 726f931551bSRalph Campbell struct qib_ctxtdata **rcd; /* Receive Context Data */ 727f931551bSRalph Campbell 728f931551bSRalph Campbell /* qib_pportdata, points to array of (physical) port-specific 729f931551bSRalph Campbell * data structs, indexed by pidx (0..n-1) 730f931551bSRalph Campbell */ 731f931551bSRalph Campbell struct qib_pportdata *pport; 732f931551bSRalph Campbell struct qib_chip_specific *cspec; /* chip-specific */ 733f931551bSRalph Campbell 734f931551bSRalph Campbell /* kvirt address of 1st 2k pio buffer */ 735f931551bSRalph Campbell void __iomem *pio2kbase; 736f931551bSRalph Campbell /* kvirt address of 1st 4k pio buffer */ 737f931551bSRalph Campbell void __iomem *pio4kbase; 738f931551bSRalph Campbell /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */ 739f931551bSRalph Campbell void __iomem *piobase; 740f931551bSRalph Campbell /* mem-mapped pointer to base of user chip regs (if using WC PAT) */ 741f931551bSRalph Campbell u64 __iomem *userbase; 742fce24a9dSDave Olson void __iomem *piovl15base; /* base of VL15 buffers, if not WC */ 743f931551bSRalph Campbell /* 744f931551bSRalph Campbell * points to area where PIOavail registers will be DMA'ed. 745f931551bSRalph Campbell * Has to be on a page of it's own, because the page will be 746f931551bSRalph Campbell * mapped into user program space. This copy is *ONLY* ever 747f931551bSRalph Campbell * written by DMA, not by the driver! Need a copy per device 748f931551bSRalph Campbell * when we get to multiple devices 749f931551bSRalph Campbell */ 750f931551bSRalph Campbell volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */ 751f931551bSRalph Campbell /* physical address where updates occur */ 752f931551bSRalph Campbell dma_addr_t pioavailregs_phys; 753f931551bSRalph Campbell 754f931551bSRalph Campbell /* device-specific implementations of functions needed by 755f931551bSRalph Campbell * common code. Contrary to previous consensus, we can't 756f931551bSRalph Campbell * really just point to a device-specific table, because we 757f931551bSRalph Campbell * may need to "bend", e.g. *_f_put_tid 758f931551bSRalph Campbell */ 759f931551bSRalph Campbell /* fallback to alternate interrupt type if possible */ 760f931551bSRalph Campbell int (*f_intr_fallback)(struct qib_devdata *); 761f931551bSRalph Campbell /* hard reset chip */ 762f931551bSRalph Campbell int (*f_reset)(struct qib_devdata *); 763f931551bSRalph Campbell void (*f_quiet_serdes)(struct qib_pportdata *); 764f931551bSRalph Campbell int (*f_bringup_serdes)(struct qib_pportdata *); 765f931551bSRalph Campbell int (*f_early_init)(struct qib_devdata *); 766f931551bSRalph Campbell void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *); 767f931551bSRalph Campbell void (*f_put_tid)(struct qib_devdata *, u64 __iomem*, 768f931551bSRalph Campbell u32, unsigned long); 769f931551bSRalph Campbell void (*f_cleanup)(struct qib_devdata *); 770f931551bSRalph Campbell void (*f_setextled)(struct qib_pportdata *, u32); 771f931551bSRalph Campbell /* fill out chip-specific fields */ 772f931551bSRalph Campbell int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *); 773f931551bSRalph Campbell /* free irq */ 774f931551bSRalph Campbell void (*f_free_irq)(struct qib_devdata *); 775f931551bSRalph Campbell struct qib_message_header *(*f_get_msgheader) 776f931551bSRalph Campbell (struct qib_devdata *, __le32 *); 777f931551bSRalph Campbell void (*f_config_ctxts)(struct qib_devdata *); 778f931551bSRalph Campbell int (*f_get_ib_cfg)(struct qib_pportdata *, int); 779f931551bSRalph Campbell int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32); 780f931551bSRalph Campbell int (*f_set_ib_loopback)(struct qib_pportdata *, const char *); 781f931551bSRalph Campbell int (*f_get_ib_table)(struct qib_pportdata *, int, void *); 782f931551bSRalph Campbell int (*f_set_ib_table)(struct qib_pportdata *, int, void *); 783f931551bSRalph Campbell u32 (*f_iblink_state)(u64); 784f931551bSRalph Campbell u8 (*f_ibphys_portstate)(u64); 785f931551bSRalph Campbell void (*f_xgxs_reset)(struct qib_pportdata *); 786f931551bSRalph Campbell /* per chip actions needed for IB Link up/down changes */ 787f931551bSRalph Campbell int (*f_ib_updown)(struct qib_pportdata *, int, u64); 788f931551bSRalph Campbell u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *); 789f931551bSRalph Campbell /* Read/modify/write of GPIO pins (potentially chip-specific */ 790f931551bSRalph Campbell int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir, 791f931551bSRalph Campbell u32 mask); 792f931551bSRalph Campbell /* Enable writes to config EEPROM (if supported) */ 793f931551bSRalph Campbell int (*f_eeprom_wen)(struct qib_devdata *dd, int wen); 794f931551bSRalph Campbell /* 795f931551bSRalph Campbell * modify rcvctrl shadow[s] and write to appropriate chip-regs. 796f931551bSRalph Campbell * see above QIB_RCVCTRL_xxx_ENB/DIS for operations. 797f931551bSRalph Campbell * (ctxt == -1) means "all contexts", only meaningful for 798f931551bSRalph Campbell * clearing. Could remove if chip_spec shutdown properly done. 799f931551bSRalph Campbell */ 800f931551bSRalph Campbell void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op, 801f931551bSRalph Campbell int ctxt); 802f931551bSRalph Campbell /* Read/modify/write sendctrl appropriately for op and port. */ 803f931551bSRalph Campbell void (*f_sendctrl)(struct qib_pportdata *, u32 op); 804f931551bSRalph Campbell void (*f_set_intr_state)(struct qib_devdata *, u32); 805f931551bSRalph Campbell void (*f_set_armlaunch)(struct qib_devdata *, u32); 806f931551bSRalph Campbell void (*f_wantpiobuf_intr)(struct qib_devdata *, u32); 807f931551bSRalph Campbell int (*f_late_initreg)(struct qib_devdata *); 808f931551bSRalph Campbell int (*f_init_sdma_regs)(struct qib_pportdata *); 809f931551bSRalph Campbell u16 (*f_sdma_gethead)(struct qib_pportdata *); 810f931551bSRalph Campbell int (*f_sdma_busy)(struct qib_pportdata *); 811f931551bSRalph Campbell void (*f_sdma_update_tail)(struct qib_pportdata *, u16); 812f931551bSRalph Campbell void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned); 813f931551bSRalph Campbell void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned); 814f931551bSRalph Campbell void (*f_sdma_hw_clean_up)(struct qib_pportdata *); 815f931551bSRalph Campbell void (*f_sdma_hw_start_up)(struct qib_pportdata *); 816f931551bSRalph Campbell void (*f_sdma_init_early)(struct qib_pportdata *); 817f931551bSRalph Campbell void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 81819ede2e4SMike Marciniszyn void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 819f931551bSRalph Campbell u32 (*f_hdrqempty)(struct qib_ctxtdata *); 820f931551bSRalph Campbell u64 (*f_portcntr)(struct qib_pportdata *, u32); 821f931551bSRalph Campbell u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **, 822f931551bSRalph Campbell u64 **); 823f931551bSRalph Campbell u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32, 824f931551bSRalph Campbell char **, u64 **); 825f931551bSRalph Campbell u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8); 826f931551bSRalph Campbell void (*f_initvl15_bufs)(struct qib_devdata *); 827f931551bSRalph Campbell void (*f_init_ctxt)(struct qib_ctxtdata *); 828f931551bSRalph Campbell void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32, 829f931551bSRalph Campbell struct qib_ctxtdata *); 830f931551bSRalph Campbell void (*f_writescratch)(struct qib_devdata *, u32); 831f931551bSRalph Campbell int (*f_tempsense_rd)(struct qib_devdata *, int regnum); 8328469ba39SMike Marciniszyn #ifdef CONFIG_INFINIBAND_QIB_DCA 8338469ba39SMike Marciniszyn int (*f_notify_dca)(struct qib_devdata *, unsigned long event); 8348469ba39SMike Marciniszyn #endif 835f931551bSRalph Campbell 836f931551bSRalph Campbell char *boardname; /* human readable board info */ 837f931551bSRalph Campbell 838f931551bSRalph Campbell /* template for writing TIDs */ 839f931551bSRalph Campbell u64 tidtemplate; 840f931551bSRalph Campbell /* value to write to free TIDs */ 841f931551bSRalph Campbell u64 tidinvalid; 842f931551bSRalph Campbell 843f931551bSRalph Campbell /* number of registers used for pioavail */ 844f931551bSRalph Campbell u32 pioavregs; 845f931551bSRalph Campbell /* device (not port) flags, basically device capabilities */ 846f931551bSRalph Campbell u32 flags; 847f931551bSRalph Campbell /* last buffer for user use */ 848f931551bSRalph Campbell u32 lastctxt_piobuf; 849f931551bSRalph Campbell 8501ed88dd7SMike Marciniszyn /* reset value */ 8511ed88dd7SMike Marciniszyn u64 z_int_counter; 8521ed88dd7SMike Marciniszyn /* percpu intcounter */ 8531ed88dd7SMike Marciniszyn u64 __percpu *int_counter; 854f931551bSRalph Campbell 855f931551bSRalph Campbell /* pio bufs allocated per ctxt */ 856f931551bSRalph Campbell u32 pbufsctxt; 857f931551bSRalph Campbell /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */ 858f931551bSRalph Campbell u32 ctxts_extrabuf; 859f931551bSRalph Campbell /* 860f931551bSRalph Campbell * number of ctxts configured as max; zero is set to number chip 861f931551bSRalph Campbell * supports, less gives more pio bufs/ctxt, etc. 862f931551bSRalph Campbell */ 863f931551bSRalph Campbell u32 cfgctxts; 86453ab1c64SMike Marciniszyn /* 86553ab1c64SMike Marciniszyn * number of ctxts available for PSM open 86653ab1c64SMike Marciniszyn */ 86753ab1c64SMike Marciniszyn u32 freectxts; 868f931551bSRalph Campbell 869f931551bSRalph Campbell /* 870f931551bSRalph Campbell * hint that we should update pioavailshadow before 871f931551bSRalph Campbell * looking for a PIO buffer 872f931551bSRalph Campbell */ 873f931551bSRalph Campbell u32 upd_pio_shadow; 874f931551bSRalph Campbell 875f931551bSRalph Campbell /* internal debugging stats */ 876f931551bSRalph Campbell u32 maxpkts_call; 877f931551bSRalph Campbell u32 avgpkts_call; 878f931551bSRalph Campbell u64 nopiobufs; 879f931551bSRalph Campbell 880f931551bSRalph Campbell /* PCI Vendor ID (here for NodeInfo) */ 881f931551bSRalph Campbell u16 vendorid; 882f931551bSRalph Campbell /* PCI Device ID (here for NodeInfo) */ 883f931551bSRalph Campbell u16 deviceid; 884f931551bSRalph Campbell /* for write combining settings */ 885ec40f925SMike Marciniszyn int wc_cookie; 886f931551bSRalph Campbell unsigned long wc_base; 887f931551bSRalph Campbell unsigned long wc_len; 888f931551bSRalph Campbell 889f931551bSRalph Campbell /* shadow copy of struct page *'s for exp tid pages */ 890f931551bSRalph Campbell struct page **pageshadow; 891f931551bSRalph Campbell /* shadow copy of dma handles for exp tid pages */ 892f931551bSRalph Campbell dma_addr_t *physshadow; 893f931551bSRalph Campbell u64 __iomem *egrtidbase; 894f931551bSRalph Campbell spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */ 895f931551bSRalph Campbell /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 896f931551bSRalph Campbell spinlock_t uctxt_lock; /* rcd and user context changes */ 897f931551bSRalph Campbell /* 898f931551bSRalph Campbell * per unit status, see also portdata statusp 899f931551bSRalph Campbell * mapped readonly into user processes so they can get unit and 900f931551bSRalph Campbell * IB link status cheaply 901f931551bSRalph Campbell */ 902f931551bSRalph Campbell u64 *devstatusp; 903f931551bSRalph Campbell char *freezemsg; /* freeze msg if hw error put chip in freeze */ 904f931551bSRalph Campbell u32 freezelen; /* max length of freezemsg */ 905f931551bSRalph Campbell /* timer used to prevent stats overflow, error throttling, etc. */ 906f931551bSRalph Campbell struct timer_list stats_timer; 907f931551bSRalph Campbell 908f931551bSRalph Campbell /* timer to verify interrupts work, and fallback if possible */ 909f931551bSRalph Campbell struct timer_list intrchk_timer; 910f931551bSRalph Campbell unsigned long ureg_align; /* user register alignment */ 911f931551bSRalph Campbell 912f931551bSRalph Campbell /* 913f931551bSRalph Campbell * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and 914f931551bSRalph Campbell * pio_writing. 915f931551bSRalph Campbell */ 916f931551bSRalph Campbell spinlock_t pioavail_lock; 917bb77a077SMike Marciniszyn /* 918bb77a077SMike Marciniszyn * index of last buffer to optimize search for next 919bb77a077SMike Marciniszyn */ 920bb77a077SMike Marciniszyn u32 last_pio; 921bb77a077SMike Marciniszyn /* 922bb77a077SMike Marciniszyn * min kernel pio buffer to optimize search 923bb77a077SMike Marciniszyn */ 924bb77a077SMike Marciniszyn u32 min_kernel_pio; 925f931551bSRalph Campbell /* 926f931551bSRalph Campbell * Shadow copies of registers; size indicates read access size. 927f931551bSRalph Campbell * Most of them are readonly, but some are write-only register, 928f931551bSRalph Campbell * where we manipulate the bits in the shadow copy, and then write 929f931551bSRalph Campbell * the shadow copy to qlogic_ib. 930f931551bSRalph Campbell * 931f931551bSRalph Campbell * We deliberately make most of these 32 bits, since they have 932f931551bSRalph Campbell * restricted range. For any that we read, we won't to generate 32 933f931551bSRalph Campbell * bit accesses, since Opteron will generate 2 separate 32 bit HT 934f931551bSRalph Campbell * transactions for a 64 bit read, and we want to avoid unnecessary 935f931551bSRalph Campbell * bus transactions. 936f931551bSRalph Campbell */ 937f931551bSRalph Campbell 938f931551bSRalph Campbell /* This is the 64 bit group */ 939f931551bSRalph Campbell 940f931551bSRalph Campbell unsigned long pioavailshadow[6]; 941f931551bSRalph Campbell /* bitmap of send buffers available for the kernel to use with PIO. */ 942f931551bSRalph Campbell unsigned long pioavailkernel[6]; 943f931551bSRalph Campbell /* bitmap of send buffers which need to be disarmed. */ 944f931551bSRalph Campbell unsigned long pio_need_disarm[3]; 945f931551bSRalph Campbell /* bitmap of send buffers which are being written to. */ 946f931551bSRalph Campbell unsigned long pio_writing[3]; 947f931551bSRalph Campbell /* kr_revision shadow */ 948f931551bSRalph Campbell u64 revision; 949f931551bSRalph Campbell /* Base GUID for device (from eeprom, network order) */ 950f931551bSRalph Campbell __be64 base_guid; 951f931551bSRalph Campbell 952f931551bSRalph Campbell /* 953f931551bSRalph Campbell * kr_sendpiobufbase value (chip offset of pio buffers), and the 954f931551bSRalph Campbell * base of the 2KB buffer s(user processes only use 2K) 955f931551bSRalph Campbell */ 956f931551bSRalph Campbell u64 piobufbase; 957f931551bSRalph Campbell u32 pio2k_bufbase; 958f931551bSRalph Campbell 959f931551bSRalph Campbell /* these are the "32 bit" regs */ 960f931551bSRalph Campbell 961f931551bSRalph Campbell /* number of GUIDs in the flash for this interface */ 962f931551bSRalph Campbell u32 nguid; 963f931551bSRalph Campbell /* 964f931551bSRalph Campbell * the following two are 32-bit bitmasks, but {test,clear,set}_bit 965f931551bSRalph Campbell * all expect bit fields to be "unsigned long" 966f931551bSRalph Campbell */ 967f931551bSRalph Campbell unsigned long rcvctrl; /* shadow per device rcvctrl */ 968f931551bSRalph Campbell unsigned long sendctrl; /* shadow per device sendctrl */ 969f931551bSRalph Campbell 970f931551bSRalph Campbell /* value we put in kr_rcvhdrcnt */ 971f931551bSRalph Campbell u32 rcvhdrcnt; 972f931551bSRalph Campbell /* value we put in kr_rcvhdrsize */ 973f931551bSRalph Campbell u32 rcvhdrsize; 974f931551bSRalph Campbell /* value we put in kr_rcvhdrentsize */ 975f931551bSRalph Campbell u32 rcvhdrentsize; 976f931551bSRalph Campbell /* kr_ctxtcnt value */ 977f931551bSRalph Campbell u32 ctxtcnt; 978f931551bSRalph Campbell /* kr_pagealign value */ 979f931551bSRalph Campbell u32 palign; 980f931551bSRalph Campbell /* number of "2KB" PIO buffers */ 981f931551bSRalph Campbell u32 piobcnt2k; 982f931551bSRalph Campbell /* size in bytes of "2KB" PIO buffers */ 983f931551bSRalph Campbell u32 piosize2k; 984f931551bSRalph Campbell /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */ 985f931551bSRalph Campbell u32 piosize2kmax_dwords; 986f931551bSRalph Campbell /* number of "4KB" PIO buffers */ 987f931551bSRalph Campbell u32 piobcnt4k; 988f931551bSRalph Campbell /* size in bytes of "4KB" PIO buffers */ 989f931551bSRalph Campbell u32 piosize4k; 990f931551bSRalph Campbell /* kr_rcvegrbase value */ 991f931551bSRalph Campbell u32 rcvegrbase; 992f931551bSRalph Campbell /* kr_rcvtidbase value */ 993f931551bSRalph Campbell u32 rcvtidbase; 994f931551bSRalph Campbell /* kr_rcvtidcnt value */ 995f931551bSRalph Campbell u32 rcvtidcnt; 996f931551bSRalph Campbell /* kr_userregbase */ 997f931551bSRalph Campbell u32 uregbase; 998f931551bSRalph Campbell /* shadow the control register contents */ 999f931551bSRalph Campbell u32 control; 1000f931551bSRalph Campbell 1001f931551bSRalph Campbell /* chip address space used by 4k pio buffers */ 1002f931551bSRalph Campbell u32 align4k; 1003f931551bSRalph Campbell /* size of each rcvegrbuffer */ 10049e1c0e43SMike Marciniszyn u16 rcvegrbufsize; 10059e1c0e43SMike Marciniszyn /* log2 of above */ 10069e1c0e43SMike Marciniszyn u16 rcvegrbufsize_shift; 1007f931551bSRalph Campbell /* localbus width (1, 2,4,8,16,32) from config space */ 1008f931551bSRalph Campbell u32 lbus_width; 1009f931551bSRalph Campbell /* localbus speed in MHz */ 1010f931551bSRalph Campbell u32 lbus_speed; 1011f931551bSRalph Campbell int unit; /* unit # of this chip */ 1012f931551bSRalph Campbell 1013f931551bSRalph Campbell /* start of CHIP_SPEC move to chipspec, but need code changes */ 1014f931551bSRalph Campbell /* low and high portions of MSI capability/vector */ 1015f931551bSRalph Campbell u32 msi_lo; 1016f931551bSRalph Campbell /* saved after PCIe init for restore after reset */ 1017f931551bSRalph Campbell u32 msi_hi; 1018f931551bSRalph Campbell /* MSI data (vector) saved for restore */ 1019f931551bSRalph Campbell u16 msi_data; 1020f931551bSRalph Campbell /* so we can rewrite it after a chip reset */ 1021f931551bSRalph Campbell u32 pcibar0; 1022f931551bSRalph Campbell /* so we can rewrite it after a chip reset */ 1023f931551bSRalph Campbell u32 pcibar1; 1024f931551bSRalph Campbell u64 rhdrhead_intr_off; 1025f931551bSRalph Campbell 1026f931551bSRalph Campbell /* 1027f931551bSRalph Campbell * ASCII serial number, from flash, large enough for original 1028f931551bSRalph Campbell * all digit strings, and longer QLogic serial number format 1029f931551bSRalph Campbell */ 1030f931551bSRalph Campbell u8 serial[16]; 1031f931551bSRalph Campbell /* human readable board version */ 1032f931551bSRalph Campbell u8 boardversion[96]; 1033f931551bSRalph Campbell u8 lbus_info[32]; /* human readable localbus info */ 1034f931551bSRalph Campbell /* chip major rev, from qib_revision */ 1035f931551bSRalph Campbell u8 majrev; 1036f931551bSRalph Campbell /* chip minor rev, from qib_revision */ 1037f931551bSRalph Campbell u8 minrev; 1038f931551bSRalph Campbell 1039f931551bSRalph Campbell /* Misc small ints */ 1040f931551bSRalph Campbell /* Number of physical ports available */ 1041f931551bSRalph Campbell u8 num_pports; 1042f931551bSRalph Campbell /* Lowest context number which can be used by user processes */ 1043f931551bSRalph Campbell u8 first_user_ctxt; 1044f931551bSRalph Campbell u8 n_krcv_queues; 1045f931551bSRalph Campbell u8 qpn_mask; 1046f931551bSRalph Campbell u8 skip_kctxt_mask; 1047f931551bSRalph Campbell 1048f931551bSRalph Campbell u16 rhf_offset; /* offset of RHF within receive header entry */ 1049f931551bSRalph Campbell 1050f931551bSRalph Campbell /* 1051f931551bSRalph Campbell * GPIO pins for twsi-connected devices, and device code for eeprom 1052f931551bSRalph Campbell */ 1053f931551bSRalph Campbell u8 gpio_sda_num; 1054f931551bSRalph Campbell u8 gpio_scl_num; 1055f931551bSRalph Campbell u8 twsi_eeprom_dev; 1056f931551bSRalph Campbell u8 board_atten; 1057f931551bSRalph Campbell 1058f931551bSRalph Campbell /* Support (including locks) for EEPROM logging of errors and time */ 1059f931551bSRalph Campbell /* control access to actual counters, timer */ 1060f931551bSRalph Campbell spinlock_t eep_st_lock; 1061f931551bSRalph Campbell /* control high-level access to EEPROM */ 1062f931551bSRalph Campbell struct mutex eep_lock; 1063f931551bSRalph Campbell uint64_t traffic_wds; 1064f931551bSRalph Campbell struct qib_diag_client *diag_client; 1065f931551bSRalph Campbell spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1066f931551bSRalph Campbell struct diag_observer_list_elt *diag_observer_list; 1067f931551bSRalph Campbell 1068f931551bSRalph Campbell u8 psxmitwait_supported; 1069f931551bSRalph Campbell /* cycle length of PS* counters in HW (in picoseconds) */ 1070f931551bSRalph Campbell u16 psxmitwait_check_rate; 1071e67306a3SMike Marciniszyn /* high volume overflow errors defered to tasklet */ 1072e67306a3SMike Marciniszyn struct tasklet_struct error_tasklet; 1073e0f30bacSRamkrishna Vepa 1074e0f30bacSRamkrishna Vepa int assigned_node_id; /* NUMA node closest to HCA */ 1075f931551bSRalph Campbell }; 1076f931551bSRalph Campbell 1077f931551bSRalph Campbell /* hol_state values */ 1078f931551bSRalph Campbell #define QIB_HOL_UP 0 1079f931551bSRalph Campbell #define QIB_HOL_INIT 1 1080f931551bSRalph Campbell 1081f931551bSRalph Campbell #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0) 1082f931551bSRalph Campbell #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1) 1083f931551bSRalph Campbell #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2) 1084f931551bSRalph Campbell #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3) 1085f931551bSRalph Campbell #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4) 1086f931551bSRalph Campbell 1087f931551bSRalph Campbell /* operation types for f_txchk_change() */ 1088f931551bSRalph Campbell #define TXCHK_CHG_TYPE_DIS1 3 1089f931551bSRalph Campbell #define TXCHK_CHG_TYPE_ENAB1 2 1090f931551bSRalph Campbell #define TXCHK_CHG_TYPE_KERN 1 1091f931551bSRalph Campbell #define TXCHK_CHG_TYPE_USER 0 1092f931551bSRalph Campbell 1093f931551bSRalph Campbell #define QIB_CHASE_TIME msecs_to_jiffies(145) 1094f931551bSRalph Campbell #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160) 1095f931551bSRalph Campbell 1096f931551bSRalph Campbell /* Private data for file operations */ 1097f931551bSRalph Campbell struct qib_filedata { 1098f931551bSRalph Campbell struct qib_ctxtdata *rcd; 1099f931551bSRalph Campbell unsigned subctxt; 1100f931551bSRalph Campbell unsigned tidcursor; 1101f931551bSRalph Campbell struct qib_user_sdma_queue *pq; 1102f931551bSRalph Campbell int rec_cpu_num; /* for cpu affinity; -1 if none */ 1103f931551bSRalph Campbell }; 1104f931551bSRalph Campbell 1105059d48fbSMatthew Wilcox extern struct xarray qib_dev_table; 1106f931551bSRalph Campbell extern struct qib_devdata *qib_lookup(int unit); 1107f931551bSRalph Campbell extern u32 qib_cpulist_count; 1108f931551bSRalph Campbell extern unsigned long *qib_cpulist; 110936a8f01cSMike Marciniszyn extern unsigned qib_cc_table_size; 111047c7ea6dSHarish Chegondi 1111f931551bSRalph Campbell int qib_init(struct qib_devdata *, int); 1112f931551bSRalph Campbell int init_chip_wc_pat(struct qib_devdata *dd, u32); 1113f931551bSRalph Campbell int qib_enable_wc(struct qib_devdata *dd); 1114f931551bSRalph Campbell void qib_disable_wc(struct qib_devdata *dd); 1115f931551bSRalph Campbell int qib_count_units(int *npresentp, int *nupp); 1116f931551bSRalph Campbell int qib_count_active_units(void); 1117f931551bSRalph Campbell 1118f931551bSRalph Campbell int qib_cdev_init(int minor, const char *name, 1119f931551bSRalph Campbell const struct file_operations *fops, 1120f931551bSRalph Campbell struct cdev **cdevp, struct device **devp); 1121f931551bSRalph Campbell void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp); 1122f931551bSRalph Campbell int qib_dev_init(void); 1123f931551bSRalph Campbell void qib_dev_cleanup(void); 1124f931551bSRalph Campbell 1125f931551bSRalph Campbell int qib_diag_add(struct qib_devdata *); 1126f931551bSRalph Campbell void qib_diag_remove(struct qib_devdata *); 1127f931551bSRalph Campbell void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64); 1128f931551bSRalph Campbell void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */ 1129f931551bSRalph Campbell 1130f931551bSRalph Campbell int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err); 1131f931551bSRalph Campbell void qib_bad_intrstatus(struct qib_devdata *); 1132f931551bSRalph Campbell void qib_handle_urcv(struct qib_devdata *, u64); 1133f931551bSRalph Campbell 1134f931551bSRalph Campbell /* clean up any per-chip chip-specific stuff */ 1135f931551bSRalph Campbell void qib_chip_cleanup(struct qib_devdata *); 1136f931551bSRalph Campbell /* clean up any chip type-specific stuff */ 1137f931551bSRalph Campbell void qib_chip_done(void); 1138f931551bSRalph Campbell 1139f931551bSRalph Campbell /* check to see if we have to force ordering for write combining */ 1140f931551bSRalph Campbell int qib_unordered_wc(void); 1141f931551bSRalph Campbell void qib_pio_copy(void __iomem *to, const void *from, size_t count); 1142f931551bSRalph Campbell 1143f931551bSRalph Campbell void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned); 1144f931551bSRalph Campbell int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *); 1145f931551bSRalph Campbell void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned); 1146f931551bSRalph Campbell void qib_cancel_sends(struct qib_pportdata *); 1147f931551bSRalph Campbell 1148f931551bSRalph Campbell int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *); 1149f931551bSRalph Campbell int qib_setup_eagerbufs(struct qib_ctxtdata *); 1150f931551bSRalph Campbell void qib_set_ctxtcnt(struct qib_devdata *); 1151f931551bSRalph Campbell int qib_create_ctxts(struct qib_devdata *dd); 1152e0f30bacSRamkrishna Vepa struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int); 11537d7632adSMike Marciniszyn int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8); 1154f931551bSRalph Campbell void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *); 1155f931551bSRalph Campbell 1156f931551bSRalph Campbell u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *); 1157f931551bSRalph Campbell int qib_reset_device(int); 1158f931551bSRalph Campbell int qib_wait_linkstate(struct qib_pportdata *, u32, int); 1159f931551bSRalph Campbell int qib_set_linkstate(struct qib_pportdata *, u8); 1160f931551bSRalph Campbell int qib_set_mtu(struct qib_pportdata *, u16); 1161f931551bSRalph Campbell int qib_set_lid(struct qib_pportdata *, u32, u8); 1162f931551bSRalph Campbell void qib_hol_down(struct qib_pportdata *); 1163f931551bSRalph Campbell void qib_hol_init(struct qib_pportdata *); 1164f931551bSRalph Campbell void qib_hol_up(struct qib_pportdata *); 11654037c92fSKees Cook void qib_hol_event(struct timer_list *); 1166f931551bSRalph Campbell void qib_disable_after_error(struct qib_devdata *); 1167f931551bSRalph Campbell int qib_set_uevent_bits(struct qib_pportdata *, const int); 1168f931551bSRalph Campbell 1169f931551bSRalph Campbell /* for use in system calls, where we want to know device type, etc. */ 1170f931551bSRalph Campbell #define ctxt_fp(fp) \ 1171f931551bSRalph Campbell (((struct qib_filedata *)(fp)->private_data)->rcd) 1172f931551bSRalph Campbell #define subctxt_fp(fp) \ 1173f931551bSRalph Campbell (((struct qib_filedata *)(fp)->private_data)->subctxt) 1174f931551bSRalph Campbell #define tidcursor_fp(fp) \ 1175f931551bSRalph Campbell (((struct qib_filedata *)(fp)->private_data)->tidcursor) 1176f931551bSRalph Campbell #define user_sdma_queue_fp(fp) \ 1177f931551bSRalph Campbell (((struct qib_filedata *)(fp)->private_data)->pq) 1178f931551bSRalph Campbell 1179f931551bSRalph Campbell static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd) 1180f931551bSRalph Campbell { 1181f931551bSRalph Campbell return ppd->dd; 1182f931551bSRalph Campbell } 1183f931551bSRalph Campbell 1184f931551bSRalph Campbell static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev) 1185f931551bSRalph Campbell { 1186f931551bSRalph Campbell return container_of(dev, struct qib_devdata, verbs_dev); 1187f931551bSRalph Campbell } 1188f931551bSRalph Campbell 1189f931551bSRalph Campbell static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev) 1190f931551bSRalph Campbell { 1191f931551bSRalph Campbell return dd_from_dev(to_idev(ibdev)); 1192f931551bSRalph Campbell } 1193f931551bSRalph Campbell 1194f931551bSRalph Campbell static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp) 1195f931551bSRalph Campbell { 1196f931551bSRalph Campbell return container_of(ibp, struct qib_pportdata, ibport_data); 1197f931551bSRalph Campbell } 1198f931551bSRalph Campbell 11991fb7f897SMark Bloch static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u32 port) 1200f931551bSRalph Campbell { 1201f931551bSRalph Campbell struct qib_devdata *dd = dd_from_ibdev(ibdev); 12021fb7f897SMark Bloch u32 pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1203f931551bSRalph Campbell 1204f931551bSRalph Campbell WARN_ON(pidx >= dd->num_pports); 1205f931551bSRalph Campbell return &dd->pport[pidx].ibport_data; 1206f931551bSRalph Campbell } 1207f931551bSRalph Campbell 1208f931551bSRalph Campbell /* 1209f931551bSRalph Campbell * values for dd->flags (_device_ related flags) and 1210f931551bSRalph Campbell */ 1211f931551bSRalph Campbell #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */ 1212f931551bSRalph Campbell #define QIB_INITTED 0x2 /* chip and driver up and initted */ 1213f931551bSRalph Campbell #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */ 1214f931551bSRalph Campbell #define QIB_PRESENT 0x8 /* chip accesses can be done */ 1215f931551bSRalph Campbell #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */ 1216f931551bSRalph Campbell #define QIB_HAS_THRESH_UPDATE 0x40 1217f931551bSRalph Campbell #define QIB_HAS_SDMA_TIMEOUT 0x80 1218f931551bSRalph Campbell #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */ 1219f931551bSRalph Campbell #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */ 1220f931551bSRalph Campbell #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */ 1221f931551bSRalph Campbell #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */ 1222f931551bSRalph Campbell #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */ 1223f931551bSRalph Campbell #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */ 1224f931551bSRalph Campbell #define QIB_BADINTR 0x8000 /* severe interrupt problems */ 1225f931551bSRalph Campbell #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */ 1226f931551bSRalph Campbell #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */ 12278d3e7113SAlex Estrin #define QIB_SHUTDOWN 0x40000 /* device is shutting down */ 1228f931551bSRalph Campbell 1229f931551bSRalph Campbell /* 1230f931551bSRalph Campbell * values for ppd->lflags (_ib_port_ related flags) 1231f931551bSRalph Campbell */ 1232f931551bSRalph Campbell #define QIBL_LINKV 0x1 /* IB link state valid */ 1233f931551bSRalph Campbell #define QIBL_LINKDOWN 0x8 /* IB link is down */ 1234f931551bSRalph Campbell #define QIBL_LINKINIT 0x10 /* IB link level is up */ 1235f931551bSRalph Campbell #define QIBL_LINKARMED 0x20 /* IB link is ARMED */ 1236f931551bSRalph Campbell #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */ 1237f931551bSRalph Campbell /* leave a gap for more IB-link state */ 1238f931551bSRalph Campbell #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */ 1239f931551bSRalph Campbell #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */ 1240f931551bSRalph Campbell #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced, 1241f931551bSRalph Campbell * Do not try to bring up */ 1242f931551bSRalph Campbell #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */ 1243f931551bSRalph Campbell 1244f931551bSRalph Campbell /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1245f931551bSRalph Campbell #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1) 1246f931551bSRalph Campbell 1247f931551bSRalph Campbell 1248f931551bSRalph Campbell /* ctxt_flag bit offsets */ 1249f931551bSRalph Campbell /* waiting for a packet to arrive */ 1250f931551bSRalph Campbell #define QIB_CTXT_WAITING_RCV 2 1251f931551bSRalph Campbell /* master has not finished initializing */ 1252f931551bSRalph Campbell #define QIB_CTXT_MASTER_UNINIT 4 1253f931551bSRalph Campbell /* waiting for an urgent packet to arrive */ 1254f931551bSRalph Campbell #define QIB_CTXT_WAITING_URG 5 1255f931551bSRalph Campbell 1256f931551bSRalph Campbell /* free up any allocated data at closes */ 1257f931551bSRalph Campbell void qib_free_data(struct qib_ctxtdata *dd); 1258f931551bSRalph Campbell void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned, 1259f931551bSRalph Campbell u32, struct qib_ctxtdata *); 1260f931551bSRalph Campbell struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *, 1261f931551bSRalph Campbell const struct pci_device_id *); 1262f931551bSRalph Campbell struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *, 1263f931551bSRalph Campbell const struct pci_device_id *); 1264f931551bSRalph Campbell struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *, 1265f931551bSRalph Campbell const struct pci_device_id *); 1266f931551bSRalph Campbell void qib_free_devdata(struct qib_devdata *); 1267f931551bSRalph Campbell struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra); 1268f931551bSRalph Campbell 1269f931551bSRalph Campbell #define QIB_TWSI_NO_DEV 0xFF 1270f931551bSRalph Campbell /* Below qib_twsi_ functions must be called with eep_lock held */ 1271f931551bSRalph Campbell int qib_twsi_reset(struct qib_devdata *dd); 1272f931551bSRalph Campbell int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer, 1273f931551bSRalph Campbell int len); 1274f931551bSRalph Campbell int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1275f931551bSRalph Campbell const void *buffer, int len); 1276f931551bSRalph Campbell void qib_get_eeprom_info(struct qib_devdata *); 1277f931551bSRalph Campbell void qib_dump_lookup_output_queue(struct qib_devdata *); 1278f931551bSRalph Campbell void qib_force_pio_avail_update(struct qib_devdata *); 12794037c92fSKees Cook void qib_clear_symerror_on_linkup(struct timer_list *t); 1280f931551bSRalph Campbell 1281f931551bSRalph Campbell /* 1282f931551bSRalph Campbell * Set LED override, only the two LSBs have "public" meaning, but 1283f931551bSRalph Campbell * any non-zero value substitutes them for the Link and LinkTrain 1284f931551bSRalph Campbell * LED states. 1285f931551bSRalph Campbell */ 1286f931551bSRalph Campbell #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ 1287f931551bSRalph Campbell #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */ 1288f931551bSRalph Campbell void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); 1289f931551bSRalph Campbell 1290f931551bSRalph Campbell /* send dma routines */ 1291f931551bSRalph Campbell int qib_setup_sdma(struct qib_pportdata *); 1292f931551bSRalph Campbell void qib_teardown_sdma(struct qib_pportdata *); 1293f931551bSRalph Campbell void __qib_sdma_intr(struct qib_pportdata *); 1294f931551bSRalph Campbell void qib_sdma_intr(struct qib_pportdata *); 12954668e4b5SCQ Tang void qib_user_sdma_send_desc(struct qib_pportdata *dd, 12964668e4b5SCQ Tang struct list_head *pktlist); 12977c2e11feSDennis Dalessandro int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *, 1298f931551bSRalph Campbell u32, struct qib_verbs_txreq *); 1299f931551bSRalph Campbell /* ppd->sdma_lock should be locked before calling this. */ 1300f931551bSRalph Campbell int qib_sdma_make_progress(struct qib_pportdata *dd); 1301f931551bSRalph Campbell 1302f931551bSRalph Campbell /* must be called under qib_sdma_lock */ 1303f931551bSRalph Campbell static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd) 1304f931551bSRalph Campbell { 1305f931551bSRalph Campbell return ppd->sdma_descq_cnt - 1306f931551bSRalph Campbell (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1; 1307f931551bSRalph Campbell } 1308f931551bSRalph Campbell 1309f931551bSRalph Campbell static inline int __qib_sdma_running(struct qib_pportdata *ppd) 1310f931551bSRalph Campbell { 1311f931551bSRalph Campbell return ppd->sdma_state.current_state == qib_sdma_state_s99_running; 1312f931551bSRalph Campbell } 1313f931551bSRalph Campbell int qib_sdma_running(struct qib_pportdata *); 13140b3ddf38SDean Luick void dump_sdma_state(struct qib_pportdata *ppd); 1315f931551bSRalph Campbell void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1316f931551bSRalph Campbell void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1317f931551bSRalph Campbell 1318f931551bSRalph Campbell /* 1319f931551bSRalph Campbell * number of words used for protocol header if not set by qib_userinit(); 1320f931551bSRalph Campbell */ 1321f931551bSRalph Campbell #define QIB_DFLT_RCVHDRSIZE 9 1322f931551bSRalph Campbell 1323f931551bSRalph Campbell /* 1324f931551bSRalph Campbell * We need to be able to handle an IB header of at least 24 dwords. 1325f931551bSRalph Campbell * We need the rcvhdrq large enough to handle largest IB header, but 1326f931551bSRalph Campbell * still have room for a 2KB MTU standard IB packet. 1327f931551bSRalph Campbell * Additionally, some processor/memory controller combinations 1328f931551bSRalph Campbell * benefit quite strongly from having the DMA'ed data be cacheline 1329f931551bSRalph Campbell * aligned and a cacheline multiple, so we set the size to 32 dwords 1330f931551bSRalph Campbell * (2 64-byte primary cachelines for pretty much all processors of 1331f931551bSRalph Campbell * interest). The alignment hurts nothing, other than using somewhat 1332f931551bSRalph Campbell * more memory. 1333f931551bSRalph Campbell */ 1334f931551bSRalph Campbell #define QIB_RCVHDR_ENTSIZE 32 1335f931551bSRalph Campbell 1336f931551bSRalph Campbell int qib_get_user_pages(unsigned long, size_t, struct page **); 1337f931551bSRalph Campbell void qib_release_user_pages(struct page **, size_t); 1338f931551bSRalph Campbell int qib_eeprom_read(struct qib_devdata *, u8, void *, int); 1339f931551bSRalph Campbell int qib_eeprom_write(struct qib_devdata *, u8, const void *, int); 1340f931551bSRalph Campbell u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32); 1341f931551bSRalph Campbell void qib_sendbuf_done(struct qib_devdata *, unsigned); 1342f931551bSRalph Campbell 1343f931551bSRalph Campbell static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd) 1344f931551bSRalph Campbell { 1345f931551bSRalph Campbell *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; 1346f931551bSRalph Campbell } 1347f931551bSRalph Campbell 1348f931551bSRalph Campbell static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd) 1349f931551bSRalph Campbell { 1350f931551bSRalph Campbell /* 1351f931551bSRalph Campbell * volatile because it's a DMA target from the chip, routine is 1352f931551bSRalph Campbell * inlined, and don't want register caching or reordering. 1353f931551bSRalph Campbell */ 1354f931551bSRalph Campbell return (u32) le64_to_cpu( 1355f931551bSRalph Campbell *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */ 1356f931551bSRalph Campbell } 1357f931551bSRalph Campbell 1358f931551bSRalph Campbell /* 1359f931551bSRalph Campbell * sysfs interface. 1360f931551bSRalph Campbell */ 1361f931551bSRalph Campbell 1362508a523fSParav Pandit extern const struct attribute_group qib_attr_group; 1363d7407d16SJason Gunthorpe extern const struct attribute_group *qib_attr_port_groups[]; 1364f931551bSRalph Campbell 1365f931551bSRalph Campbell int qib_device_create(struct qib_devdata *); 1366f931551bSRalph Campbell void qib_device_remove(struct qib_devdata *); 1367f931551bSRalph Campbell 1368f931551bSRalph Campbell /* Hook for sysfs read of QSFP */ 1369f931551bSRalph Campbell extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len); 1370f931551bSRalph Campbell 1371f931551bSRalph Campbell int __init qib_init_qibfs(void); 1372f931551bSRalph Campbell int __exit qib_exit_qibfs(void); 1373f931551bSRalph Campbell 1374f931551bSRalph Campbell int qibfs_add(struct qib_devdata *); 1375f931551bSRalph Campbell int qibfs_remove(struct qib_devdata *); 1376f931551bSRalph Campbell 1377f931551bSRalph Campbell int qib_pcie_init(struct pci_dev *, const struct pci_device_id *); 1378f931551bSRalph Campbell int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *, 1379f931551bSRalph Campbell const struct pci_device_id *); 1380f931551bSRalph Campbell void qib_pcie_ddcleanup(struct qib_devdata *); 1381581d01aaSMichael J. Ruhl int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent); 1382c4bc6156SMichael J. Ruhl void qib_free_irq(struct qib_devdata *dd); 1383c4bc6156SMichael J. Ruhl int qib_reinit_intr(struct qib_devdata *dd); 1384f931551bSRalph Campbell void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1385f931551bSRalph Campbell void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 13861ed88dd7SMike Marciniszyn /* interrupts for device */ 13871ed88dd7SMike Marciniszyn u64 qib_int_counter(struct qib_devdata *); 13881ed88dd7SMike Marciniszyn /* interrupt for all devices */ 13891ed88dd7SMike Marciniszyn u64 qib_sps_ints(void); 1390f931551bSRalph Campbell 1391f931551bSRalph Campbell /* 1392f931551bSRalph Campbell * dma_addr wrappers - all 0's invalid for hw 1393f931551bSRalph Campbell */ 13940252f733SMike Marciniszyn int qib_map_page(struct pci_dev *d, struct page *p, dma_addr_t *daddr); 13956a9df403SDennis Dalessandro struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi); 1396f931551bSRalph Campbell 1397f931551bSRalph Campbell /* 1398f931551bSRalph Campbell * Flush write combining store buffers (if present) and perform a write 1399f931551bSRalph Campbell * barrier. 1400f931551bSRalph Campbell */ 1401a46a2802SMike Marciniszyn static inline void qib_flush_wc(void) 1402a46a2802SMike Marciniszyn { 1403f931551bSRalph Campbell #if defined(CONFIG_X86_64) 1404a46a2802SMike Marciniszyn asm volatile("sfence" : : : "memory"); 1405f931551bSRalph Campbell #else 1406a46a2802SMike Marciniszyn wmb(); /* no reorder around wc flush */ 1407f931551bSRalph Campbell #endif 1408a46a2802SMike Marciniszyn } 1409f931551bSRalph Campbell 1410f931551bSRalph Campbell /* global module parameter variables */ 1411f931551bSRalph Campbell extern unsigned qib_ibmtu; 1412f931551bSRalph Campbell extern ushort qib_cfgctxts; 1413f931551bSRalph Campbell extern ushort qib_num_cfg_vls; 1414f931551bSRalph Campbell extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */ 1415f931551bSRalph Campbell extern unsigned qib_n_krcv_queues; 1416f931551bSRalph Campbell extern unsigned qib_sdma_fetch_arb; 1417f931551bSRalph Campbell extern unsigned qib_compat_ddr_negotiate; 1418f931551bSRalph Campbell extern int qib_special_trigger; 1419e0f30bacSRamkrishna Vepa extern unsigned qib_numa_aware; 1420f931551bSRalph Campbell 1421f931551bSRalph Campbell extern struct mutex qib_mutex; 1422f931551bSRalph Campbell 1423f931551bSRalph Campbell /* Number of seconds before our card status check... */ 1424f931551bSRalph Campbell #define STATUS_TIMEOUT 60 1425f931551bSRalph Campbell 1426f931551bSRalph Campbell #define QIB_DRV_NAME "ib_qib" 1427f931551bSRalph Campbell #define QIB_USER_MINOR_BASE 0 1428f931551bSRalph Campbell #define QIB_TRACE_MINOR 127 1429f931551bSRalph Campbell #define QIB_DIAGPKT_MINOR 128 1430f931551bSRalph Campbell #define QIB_DIAG_MINOR_BASE 129 1431f931551bSRalph Campbell #define QIB_NMINORS 255 1432f931551bSRalph Campbell 1433f931551bSRalph Campbell #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 1434f931551bSRalph Campbell #define PCI_VENDOR_ID_QLOGIC 0x1077 1435f931551bSRalph Campbell #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10 1436f931551bSRalph Campbell #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220 1437f931551bSRalph Campbell #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322 1438f931551bSRalph Campbell 1439f931551bSRalph Campbell /* 1440f931551bSRalph Campbell * qib_early_err is used (only!) to print early errors before devdata is 1441f931551bSRalph Campbell * allocated, or when dd->pcidev may not be valid, and at the tail end of 1442f931551bSRalph Campbell * cleanup when devdata may have been freed, etc. qib_dev_porterr is 1443f931551bSRalph Campbell * the same as qib_dev_err, but is used when the message really needs 1444f931551bSRalph Campbell * the IB port# to be definitive as to what's happening.. 1445f931551bSRalph Campbell * All of these go to the trace log, and the trace log entry is done 1446f931551bSRalph Campbell * first to avoid possible serial port delays from printk. 1447f931551bSRalph Campbell */ 1448f931551bSRalph Campbell #define qib_early_err(dev, fmt, ...) \ 1449ddb88765SMike Marciniszyn dev_err(dev, fmt, ##__VA_ARGS__) 1450f931551bSRalph Campbell 1451f931551bSRalph Campbell #define qib_dev_err(dd, fmt, ...) \ 1452f931551bSRalph Campbell dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 145311f0e897SMichael J. Ruhl rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 1454ddb88765SMike Marciniszyn 1455ddb88765SMike Marciniszyn #define qib_dev_warn(dd, fmt, ...) \ 1456ddb88765SMike Marciniszyn dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 145711f0e897SMichael J. Ruhl rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__) 1458f931551bSRalph Campbell 1459f931551bSRalph Campbell #define qib_dev_porterr(dd, port, fmt, ...) \ 1460f931551bSRalph Campbell dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ 146111f0e897SMichael J. Ruhl rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (dd)->unit, (port), \ 1462ddb88765SMike Marciniszyn ##__VA_ARGS__) 1463f931551bSRalph Campbell 1464f931551bSRalph Campbell #define qib_devinfo(pcidev, fmt, ...) \ 1465ddb88765SMike Marciniszyn dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__) 1466f931551bSRalph Campbell 1467f931551bSRalph Campbell /* 1468f931551bSRalph Campbell * this is used for formatting hw error messages... 1469f931551bSRalph Campbell */ 1470f931551bSRalph Campbell struct qib_hwerror_msgs { 1471f931551bSRalph Campbell u64 mask; 1472f931551bSRalph Campbell const char *msg; 1473e67306a3SMike Marciniszyn size_t sz; 1474f931551bSRalph Campbell }; 1475f931551bSRalph Campbell 1476f931551bSRalph Campbell #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } 1477f931551bSRalph Campbell 1478f931551bSRalph Campbell /* in qib_intr.c... */ 1479f931551bSRalph Campbell void qib_format_hwerrors(u64 hwerrs, 1480f931551bSRalph Campbell const struct qib_hwerror_msgs *hwerrmsgs, 1481f931551bSRalph Campbell size_t nhwerrmsgs, char *msg, size_t lmsg); 148270696ea7SHarish Chegondi 148320f333b6SHarish Chegondi void qib_stop_send_queue(struct rvt_qp *qp); 148420f333b6SHarish Chegondi void qib_quiesce_qp(struct rvt_qp *qp); 148520f333b6SHarish Chegondi void qib_flush_qp_waiters(struct rvt_qp *qp); 148620f333b6SHarish Chegondi int qib_mtu_to_path_mtu(u32 mtu); 148720f333b6SHarish Chegondi u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu); 148820f333b6SHarish Chegondi void qib_notify_error_qp(struct rvt_qp *qp); 148920f333b6SHarish Chegondi int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp, 149070696ea7SHarish Chegondi struct ib_qp_attr *attr); 149170696ea7SHarish Chegondi 1492f931551bSRalph Campbell #endif /* _QIB_KERNEL_H */ 1493