1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <rdma/ib_verbs.h> 34 #include <rdma/ib_addr.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/iw_cm.h> 37 #include <rdma/ib_mad.h> 38 #include <linux/netdevice.h> 39 #include <linux/iommu.h> 40 #include <linux/pci.h> 41 #include <net/addrconf.h> 42 #include <linux/idr.h> 43 44 #include <linux/qed/qed_chain.h> 45 #include <linux/qed/qed_if.h> 46 #include "qedr.h" 47 #include "verbs.h" 48 #include <rdma/qedr-abi.h> 49 #include "qedr_iw_cm.h" 50 51 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 52 MODULE_AUTHOR("QLogic Corporation"); 53 MODULE_LICENSE("Dual BSD/GPL"); 54 55 #define QEDR_WQ_MULTIPLIER_DFT (3) 56 57 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 58 enum ib_event_type type) 59 { 60 struct ib_event ibev; 61 62 ibev.device = &dev->ibdev; 63 ibev.element.port_num = port_num; 64 ibev.event = type; 65 66 ib_dispatch_event(&ibev); 67 } 68 69 static enum rdma_link_layer qedr_link_layer(struct ib_device *device, 70 u8 port_num) 71 { 72 return IB_LINK_LAYER_ETHERNET; 73 } 74 75 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str) 76 { 77 struct qedr_dev *qedr = get_qedr_dev(ibdev); 78 u32 fw_ver = (u32)qedr->attr.fw_ver; 79 80 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d", 81 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF, 82 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); 83 } 84 85 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num) 86 { 87 struct qedr_dev *qdev; 88 89 qdev = get_qedr_dev(dev); 90 dev_hold(qdev->ndev); 91 92 /* The HW vendor's device driver must guarantee 93 * that this function returns NULL before the net device has finished 94 * NETDEV_UNREGISTER state. 95 */ 96 return qdev->ndev; 97 } 98 99 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num, 100 struct ib_port_immutable *immutable) 101 { 102 struct ib_port_attr attr; 103 int err; 104 105 err = qedr_query_port(ibdev, port_num, &attr); 106 if (err) 107 return err; 108 109 immutable->pkey_tbl_len = attr.pkey_tbl_len; 110 immutable->gid_tbl_len = attr.gid_tbl_len; 111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 113 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 114 115 return 0; 116 } 117 118 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num, 119 struct ib_port_immutable *immutable) 120 { 121 struct ib_port_attr attr; 122 int err; 123 124 err = qedr_query_port(ibdev, port_num, &attr); 125 if (err) 126 return err; 127 128 immutable->pkey_tbl_len = 1; 129 immutable->gid_tbl_len = 1; 130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 131 immutable->max_mad_size = 0; 132 133 return 0; 134 } 135 136 /* QEDR sysfs interface */ 137 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 138 char *buf) 139 { 140 struct qedr_dev *dev = 141 rdma_device_to_drv_device(device, struct qedr_dev, ibdev); 142 143 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor); 144 } 145 static DEVICE_ATTR_RO(hw_rev); 146 147 static ssize_t hca_type_show(struct device *device, 148 struct device_attribute *attr, char *buf) 149 { 150 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET"); 151 } 152 static DEVICE_ATTR_RO(hca_type); 153 154 static struct attribute *qedr_attributes[] = { 155 &dev_attr_hw_rev.attr, 156 &dev_attr_hca_type.attr, 157 NULL 158 }; 159 160 static const struct attribute_group qedr_attr_group = { 161 .attrs = qedr_attributes, 162 }; 163 164 static const struct ib_device_ops qedr_iw_dev_ops = { 165 .get_port_immutable = qedr_iw_port_immutable, 166 .query_gid = qedr_iw_query_gid, 167 }; 168 169 static int qedr_iw_register_device(struct qedr_dev *dev) 170 { 171 dev->ibdev.node_type = RDMA_NODE_RNIC; 172 173 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops); 174 175 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL); 176 if (!dev->ibdev.iwcm) 177 return -ENOMEM; 178 179 dev->ibdev.iwcm->connect = qedr_iw_connect; 180 dev->ibdev.iwcm->accept = qedr_iw_accept; 181 dev->ibdev.iwcm->reject = qedr_iw_reject; 182 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen; 183 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen; 184 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref; 185 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref; 186 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp; 187 188 memcpy(dev->ibdev.iwcm->ifname, 189 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname)); 190 191 return 0; 192 } 193 194 static const struct ib_device_ops qedr_roce_dev_ops = { 195 .get_port_immutable = qedr_roce_port_immutable, 196 }; 197 198 static void qedr_roce_register_device(struct qedr_dev *dev) 199 { 200 dev->ibdev.node_type = RDMA_NODE_IB_CA; 201 202 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops); 203 } 204 205 static const struct ib_device_ops qedr_dev_ops = { 206 .alloc_mr = qedr_alloc_mr, 207 .alloc_pd = qedr_alloc_pd, 208 .alloc_ucontext = qedr_alloc_ucontext, 209 .create_ah = qedr_create_ah, 210 .create_cq = qedr_create_cq, 211 .create_qp = qedr_create_qp, 212 .create_srq = qedr_create_srq, 213 .dealloc_pd = qedr_dealloc_pd, 214 .dealloc_ucontext = qedr_dealloc_ucontext, 215 .dereg_mr = qedr_dereg_mr, 216 .destroy_ah = qedr_destroy_ah, 217 .destroy_cq = qedr_destroy_cq, 218 .destroy_qp = qedr_destroy_qp, 219 .destroy_srq = qedr_destroy_srq, 220 .get_dev_fw_str = qedr_get_dev_fw_str, 221 .get_dma_mr = qedr_get_dma_mr, 222 .get_link_layer = qedr_link_layer, 223 .get_netdev = qedr_get_netdev, 224 .map_mr_sg = qedr_map_mr_sg, 225 .mmap = qedr_mmap, 226 .modify_port = qedr_modify_port, 227 .modify_qp = qedr_modify_qp, 228 .modify_srq = qedr_modify_srq, 229 .poll_cq = qedr_poll_cq, 230 .post_recv = qedr_post_recv, 231 .post_send = qedr_post_send, 232 .post_srq_recv = qedr_post_srq_recv, 233 .process_mad = qedr_process_mad, 234 .query_device = qedr_query_device, 235 .query_pkey = qedr_query_pkey, 236 .query_port = qedr_query_port, 237 .query_qp = qedr_query_qp, 238 .query_srq = qedr_query_srq, 239 .reg_user_mr = qedr_reg_user_mr, 240 .req_notify_cq = qedr_arm_cq, 241 .resize_cq = qedr_resize_cq, 242 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd), 243 }; 244 245 static int qedr_register_device(struct qedr_dev *dev) 246 { 247 int rc; 248 249 dev->ibdev.node_guid = dev->attr.node_guid; 250 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC)); 251 dev->ibdev.owner = THIS_MODULE; 252 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION; 253 254 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) | 255 QEDR_UVERBS(QUERY_DEVICE) | 256 QEDR_UVERBS(QUERY_PORT) | 257 QEDR_UVERBS(ALLOC_PD) | 258 QEDR_UVERBS(DEALLOC_PD) | 259 QEDR_UVERBS(CREATE_COMP_CHANNEL) | 260 QEDR_UVERBS(CREATE_CQ) | 261 QEDR_UVERBS(RESIZE_CQ) | 262 QEDR_UVERBS(DESTROY_CQ) | 263 QEDR_UVERBS(REQ_NOTIFY_CQ) | 264 QEDR_UVERBS(CREATE_QP) | 265 QEDR_UVERBS(MODIFY_QP) | 266 QEDR_UVERBS(QUERY_QP) | 267 QEDR_UVERBS(DESTROY_QP) | 268 QEDR_UVERBS(CREATE_SRQ) | 269 QEDR_UVERBS(DESTROY_SRQ) | 270 QEDR_UVERBS(QUERY_SRQ) | 271 QEDR_UVERBS(MODIFY_SRQ) | 272 QEDR_UVERBS(POST_SRQ_RECV) | 273 QEDR_UVERBS(REG_MR) | 274 QEDR_UVERBS(DEREG_MR) | 275 QEDR_UVERBS(POLL_CQ) | 276 QEDR_UVERBS(POST_SEND) | 277 QEDR_UVERBS(POST_RECV); 278 279 if (IS_IWARP(dev)) { 280 rc = qedr_iw_register_device(dev); 281 if (rc) 282 return rc; 283 } else { 284 qedr_roce_register_device(dev); 285 } 286 287 dev->ibdev.phys_port_cnt = 1; 288 dev->ibdev.num_comp_vectors = dev->num_cnq; 289 dev->ibdev.dev.parent = &dev->pdev->dev; 290 291 rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group); 292 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops); 293 294 dev->ibdev.driver_id = RDMA_DRIVER_QEDR; 295 return ib_register_device(&dev->ibdev, "qedr%d"); 296 } 297 298 /* This function allocates fast-path status block memory */ 299 static int qedr_alloc_mem_sb(struct qedr_dev *dev, 300 struct qed_sb_info *sb_info, u16 sb_id) 301 { 302 struct status_block_e4 *sb_virt; 303 dma_addr_t sb_phys; 304 int rc; 305 306 sb_virt = dma_alloc_coherent(&dev->pdev->dev, 307 sizeof(*sb_virt), &sb_phys, GFP_KERNEL); 308 if (!sb_virt) 309 return -ENOMEM; 310 311 rc = dev->ops->common->sb_init(dev->cdev, sb_info, 312 sb_virt, sb_phys, sb_id, 313 QED_SB_TYPE_CNQ); 314 if (rc) { 315 pr_err("Status block initialization failed\n"); 316 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt), 317 sb_virt, sb_phys); 318 return rc; 319 } 320 321 return 0; 322 } 323 324 static void qedr_free_mem_sb(struct qedr_dev *dev, 325 struct qed_sb_info *sb_info, int sb_id) 326 { 327 if (sb_info->sb_virt) { 328 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id); 329 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt), 330 (void *)sb_info->sb_virt, sb_info->sb_phys); 331 } 332 } 333 334 static void qedr_free_resources(struct qedr_dev *dev) 335 { 336 int i; 337 338 if (IS_IWARP(dev)) 339 destroy_workqueue(dev->iwarp_wq); 340 341 for (i = 0; i < dev->num_cnq; i++) { 342 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 343 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 344 } 345 346 kfree(dev->cnq_array); 347 kfree(dev->sb_array); 348 kfree(dev->sgid_tbl); 349 } 350 351 static int qedr_alloc_resources(struct qedr_dev *dev) 352 { 353 struct qedr_cnq *cnq; 354 __le16 *cons_pi; 355 u16 n_entries; 356 int i, rc; 357 358 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid), 359 GFP_KERNEL); 360 if (!dev->sgid_tbl) 361 return -ENOMEM; 362 363 spin_lock_init(&dev->sgid_lock); 364 365 if (IS_IWARP(dev)) { 366 spin_lock_init(&dev->qpidr.idr_lock); 367 idr_init(&dev->qpidr.idr); 368 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq"); 369 } 370 371 /* Allocate Status blocks for CNQ */ 372 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 373 GFP_KERNEL); 374 if (!dev->sb_array) { 375 rc = -ENOMEM; 376 goto err1; 377 } 378 379 dev->cnq_array = kcalloc(dev->num_cnq, 380 sizeof(*dev->cnq_array), GFP_KERNEL); 381 if (!dev->cnq_array) { 382 rc = -ENOMEM; 383 goto err2; 384 } 385 386 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev); 387 388 /* Allocate CNQ PBLs */ 389 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE); 390 for (i = 0; i < dev->num_cnq; i++) { 391 cnq = &dev->cnq_array[i]; 392 393 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i], 394 dev->sb_start + i); 395 if (rc) 396 goto err3; 397 398 rc = dev->ops->common->chain_alloc(dev->cdev, 399 QED_CHAIN_USE_TO_CONSUME, 400 QED_CHAIN_MODE_PBL, 401 QED_CHAIN_CNT_TYPE_U16, 402 n_entries, 403 sizeof(struct regpair *), 404 &cnq->pbl, NULL); 405 if (rc) 406 goto err4; 407 408 cnq->dev = dev; 409 cnq->sb = &dev->sb_array[i]; 410 cons_pi = dev->sb_array[i].sb_virt->pi_array; 411 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX]; 412 cnq->index = i; 413 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev)); 414 415 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n", 416 i, qed_chain_get_cons_idx(&cnq->pbl)); 417 } 418 419 return 0; 420 err4: 421 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 422 err3: 423 for (--i; i >= 0; i--) { 424 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 425 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 426 } 427 kfree(dev->cnq_array); 428 err2: 429 kfree(dev->sb_array); 430 err1: 431 kfree(dev->sgid_tbl); 432 return rc; 433 } 434 435 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev) 436 { 437 int rc = pci_enable_atomic_ops_to_root(pdev, 438 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 439 440 if (rc) { 441 dev->atomic_cap = IB_ATOMIC_NONE; 442 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n"); 443 } else { 444 dev->atomic_cap = IB_ATOMIC_GLOB; 445 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n"); 446 } 447 } 448 449 static const struct qed_rdma_ops *qed_ops; 450 451 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 452 453 static irqreturn_t qedr_irq_handler(int irq, void *handle) 454 { 455 u16 hw_comp_cons, sw_comp_cons; 456 struct qedr_cnq *cnq = handle; 457 struct regpair *cq_handle; 458 struct qedr_cq *cq; 459 460 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0); 461 462 qed_sb_update_sb_idx(cnq->sb); 463 464 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 465 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 466 467 /* Align protocol-index and chain reads */ 468 rmb(); 469 470 while (sw_comp_cons != hw_comp_cons) { 471 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl); 472 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 473 cq_handle->lo); 474 475 if (cq == NULL) { 476 DP_ERR(cnq->dev, 477 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n", 478 cq_handle->hi, cq_handle->lo, sw_comp_cons, 479 hw_comp_cons); 480 481 break; 482 } 483 484 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) { 485 DP_ERR(cnq->dev, 486 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n", 487 cq_handle->hi, cq_handle->lo, cq); 488 break; 489 } 490 491 cq->arm_flags = 0; 492 493 if (!cq->destroyed && cq->ibcq.comp_handler) 494 (*cq->ibcq.comp_handler) 495 (&cq->ibcq, cq->ibcq.cq_context); 496 497 /* The CQ's CNQ notification counter is checked before 498 * destroying the CQ in a busy-wait loop that waits for all of 499 * the CQ's CNQ interrupts to be processed. It is increased 500 * here, only after the completion handler, to ensure that the 501 * the handler is not running when the CQ is destroyed. 502 */ 503 cq->cnq_notif++; 504 505 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 506 507 cnq->n_comp++; 508 } 509 510 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, 511 sw_comp_cons); 512 513 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1); 514 515 return IRQ_HANDLED; 516 } 517 518 static void qedr_sync_free_irqs(struct qedr_dev *dev) 519 { 520 u32 vector; 521 int i; 522 523 for (i = 0; i < dev->int_info.used_cnt; i++) { 524 if (dev->int_info.msix_cnt) { 525 vector = dev->int_info.msix[i * dev->num_hwfns].vector; 526 synchronize_irq(vector); 527 free_irq(vector, &dev->cnq_array[i]); 528 } 529 } 530 531 dev->int_info.used_cnt = 0; 532 } 533 534 static int qedr_req_msix_irqs(struct qedr_dev *dev) 535 { 536 int i, rc = 0; 537 538 if (dev->num_cnq > dev->int_info.msix_cnt) { 539 DP_ERR(dev, 540 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n", 541 dev->num_cnq, dev->int_info.msix_cnt); 542 return -EINVAL; 543 } 544 545 for (i = 0; i < dev->num_cnq; i++) { 546 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector, 547 qedr_irq_handler, 0, dev->cnq_array[i].name, 548 &dev->cnq_array[i]); 549 if (rc) { 550 DP_ERR(dev, "Request cnq %d irq failed\n", i); 551 qedr_sync_free_irqs(dev); 552 } else { 553 DP_DEBUG(dev, QEDR_MSG_INIT, 554 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n", 555 dev->cnq_array[i].name, i, 556 &dev->cnq_array[i]); 557 dev->int_info.used_cnt++; 558 } 559 } 560 561 return rc; 562 } 563 564 static int qedr_setup_irqs(struct qedr_dev *dev) 565 { 566 int rc; 567 568 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n"); 569 570 /* Learn Interrupt configuration */ 571 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq); 572 if (rc < 0) 573 return rc; 574 575 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info); 576 if (rc) { 577 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n"); 578 return rc; 579 } 580 581 if (dev->int_info.msix_cnt) { 582 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n", 583 dev->int_info.msix_cnt); 584 rc = qedr_req_msix_irqs(dev); 585 if (rc) 586 return rc; 587 } 588 589 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n"); 590 591 return 0; 592 } 593 594 static int qedr_set_device_attr(struct qedr_dev *dev) 595 { 596 struct qed_rdma_device *qed_attr; 597 struct qedr_device_attr *attr; 598 u32 page_size; 599 600 /* Part 1 - query core capabilities */ 601 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx); 602 603 /* Part 2 - check capabilities */ 604 page_size = ~dev->attr.page_size_caps + 1; 605 if (page_size > PAGE_SIZE) { 606 DP_ERR(dev, 607 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n", 608 PAGE_SIZE, page_size); 609 return -ENODEV; 610 } 611 612 /* Part 3 - copy and update capabilities */ 613 attr = &dev->attr; 614 attr->vendor_id = qed_attr->vendor_id; 615 attr->vendor_part_id = qed_attr->vendor_part_id; 616 attr->hw_ver = qed_attr->hw_ver; 617 attr->fw_ver = qed_attr->fw_ver; 618 attr->node_guid = qed_attr->node_guid; 619 attr->sys_image_guid = qed_attr->sys_image_guid; 620 attr->max_cnq = qed_attr->max_cnq; 621 attr->max_sge = qed_attr->max_sge; 622 attr->max_inline = qed_attr->max_inline; 623 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE); 624 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE); 625 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc; 626 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc; 627 attr->max_dev_resp_rd_atomic_resc = 628 qed_attr->max_dev_resp_rd_atomic_resc; 629 attr->max_cq = qed_attr->max_cq; 630 attr->max_qp = qed_attr->max_qp; 631 attr->max_mr = qed_attr->max_mr; 632 attr->max_mr_size = qed_attr->max_mr_size; 633 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES); 634 attr->max_mw = qed_attr->max_mw; 635 attr->max_fmr = qed_attr->max_fmr; 636 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl; 637 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size; 638 attr->max_pd = qed_attr->max_pd; 639 attr->max_ah = qed_attr->max_ah; 640 attr->max_pkey = qed_attr->max_pkey; 641 attr->max_srq = qed_attr->max_srq; 642 attr->max_srq_wr = qed_attr->max_srq_wr; 643 attr->dev_caps = qed_attr->dev_caps; 644 attr->page_size_caps = qed_attr->page_size_caps; 645 attr->dev_ack_delay = qed_attr->dev_ack_delay; 646 attr->reserved_lkey = qed_attr->reserved_lkey; 647 attr->bad_pkey_counter = qed_attr->bad_pkey_counter; 648 attr->max_stats_queues = qed_attr->max_stats_queues; 649 650 return 0; 651 } 652 653 static void qedr_unaffiliated_event(void *context, u8 event_code) 654 { 655 pr_err("unaffiliated event not implemented yet\n"); 656 } 657 658 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 659 { 660 #define EVENT_TYPE_NOT_DEFINED 0 661 #define EVENT_TYPE_CQ 1 662 #define EVENT_TYPE_QP 2 663 #define EVENT_TYPE_SRQ 3 664 struct qedr_dev *dev = (struct qedr_dev *)context; 665 struct regpair *async_handle = (struct regpair *)fw_handle; 666 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo; 667 u8 event_type = EVENT_TYPE_NOT_DEFINED; 668 struct ib_event event; 669 struct ib_srq *ibsrq; 670 struct qedr_srq *srq; 671 unsigned long flags; 672 struct ib_cq *ibcq; 673 struct ib_qp *ibqp; 674 struct qedr_cq *cq; 675 struct qedr_qp *qp; 676 u16 srq_id; 677 678 if (IS_ROCE(dev)) { 679 switch (e_code) { 680 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 681 event.event = IB_EVENT_CQ_ERR; 682 event_type = EVENT_TYPE_CQ; 683 break; 684 case ROCE_ASYNC_EVENT_SQ_DRAINED: 685 event.event = IB_EVENT_SQ_DRAINED; 686 event_type = EVENT_TYPE_QP; 687 break; 688 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 689 event.event = IB_EVENT_QP_FATAL; 690 event_type = EVENT_TYPE_QP; 691 break; 692 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 693 event.event = IB_EVENT_QP_REQ_ERR; 694 event_type = EVENT_TYPE_QP; 695 break; 696 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 697 event.event = IB_EVENT_QP_ACCESS_ERR; 698 event_type = EVENT_TYPE_QP; 699 break; 700 case ROCE_ASYNC_EVENT_SRQ_LIMIT: 701 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 702 event_type = EVENT_TYPE_SRQ; 703 break; 704 case ROCE_ASYNC_EVENT_SRQ_EMPTY: 705 event.event = IB_EVENT_SRQ_ERR; 706 event_type = EVENT_TYPE_SRQ; 707 break; 708 default: 709 DP_ERR(dev, "unsupported event %d on handle=%llx\n", 710 e_code, roce_handle64); 711 } 712 } else { 713 switch (e_code) { 714 case QED_IWARP_EVENT_SRQ_LIMIT: 715 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 716 event_type = EVENT_TYPE_SRQ; 717 break; 718 case QED_IWARP_EVENT_SRQ_EMPTY: 719 event.event = IB_EVENT_SRQ_ERR; 720 event_type = EVENT_TYPE_SRQ; 721 break; 722 default: 723 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code, 724 roce_handle64); 725 } 726 } 727 switch (event_type) { 728 case EVENT_TYPE_CQ: 729 cq = (struct qedr_cq *)(uintptr_t)roce_handle64; 730 if (cq) { 731 ibcq = &cq->ibcq; 732 if (ibcq->event_handler) { 733 event.device = ibcq->device; 734 event.element.cq = ibcq; 735 ibcq->event_handler(&event, ibcq->cq_context); 736 } 737 } else { 738 WARN(1, 739 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n", 740 roce_handle64); 741 } 742 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq); 743 break; 744 case EVENT_TYPE_QP: 745 qp = (struct qedr_qp *)(uintptr_t)roce_handle64; 746 if (qp) { 747 ibqp = &qp->ibqp; 748 if (ibqp->event_handler) { 749 event.device = ibqp->device; 750 event.element.qp = ibqp; 751 ibqp->event_handler(&event, ibqp->qp_context); 752 } 753 } else { 754 WARN(1, 755 "Error: QP event with NULL pointer ibqp. Handle=%llx\n", 756 roce_handle64); 757 } 758 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp); 759 break; 760 case EVENT_TYPE_SRQ: 761 srq_id = (u16)roce_handle64; 762 spin_lock_irqsave(&dev->srqidr.idr_lock, flags); 763 srq = idr_find(&dev->srqidr.idr, srq_id); 764 if (srq) { 765 ibsrq = &srq->ibsrq; 766 if (ibsrq->event_handler) { 767 event.device = ibsrq->device; 768 event.element.srq = ibsrq; 769 ibsrq->event_handler(&event, 770 ibsrq->srq_context); 771 } 772 } else { 773 DP_NOTICE(dev, 774 "SRQ event with NULL pointer ibsrq. Handle=%llx\n", 775 roce_handle64); 776 } 777 spin_unlock_irqrestore(&dev->srqidr.idr_lock, flags); 778 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq); 779 default: 780 break; 781 } 782 } 783 784 static int qedr_init_hw(struct qedr_dev *dev) 785 { 786 struct qed_rdma_add_user_out_params out_params; 787 struct qed_rdma_start_in_params *in_params; 788 struct qed_rdma_cnq_params *cur_pbl; 789 struct qed_rdma_events events; 790 dma_addr_t p_phys_table; 791 u32 page_cnt; 792 int rc = 0; 793 int i; 794 795 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 796 if (!in_params) { 797 rc = -ENOMEM; 798 goto out; 799 } 800 801 in_params->desired_cnq = dev->num_cnq; 802 for (i = 0; i < dev->num_cnq; i++) { 803 cur_pbl = &in_params->cnq_pbl_list[i]; 804 805 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl); 806 cur_pbl->num_pbl_pages = page_cnt; 807 808 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 809 cur_pbl->pbl_ptr = (u64)p_phys_table; 810 } 811 812 events.affiliated_event = qedr_affiliated_event; 813 events.unaffiliated_event = qedr_unaffiliated_event; 814 events.context = dev; 815 816 in_params->events = &events; 817 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 818 in_params->max_mtu = dev->ndev->mtu; 819 dev->iwarp_max_mtu = dev->ndev->mtu; 820 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 821 822 rc = dev->ops->rdma_init(dev->cdev, in_params); 823 if (rc) 824 goto out; 825 826 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params); 827 if (rc) 828 goto out; 829 830 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr; 831 dev->db_phys_addr = out_params.dpi_phys_addr; 832 dev->db_size = out_params.dpi_size; 833 dev->dpi = out_params.dpi; 834 835 rc = qedr_set_device_attr(dev); 836 out: 837 kfree(in_params); 838 if (rc) 839 DP_ERR(dev, "Init HW Failed rc = %d\n", rc); 840 841 return rc; 842 } 843 844 static void qedr_stop_hw(struct qedr_dev *dev) 845 { 846 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 847 dev->ops->rdma_stop(dev->rdma_ctx); 848 } 849 850 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev, 851 struct net_device *ndev) 852 { 853 struct qed_dev_rdma_info dev_info; 854 struct qedr_dev *dev; 855 int rc = 0; 856 857 dev = ib_alloc_device(qedr_dev, ibdev); 858 if (!dev) { 859 pr_err("Unable to allocate ib device\n"); 860 return NULL; 861 } 862 863 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n"); 864 865 dev->pdev = pdev; 866 dev->ndev = ndev; 867 dev->cdev = cdev; 868 869 qed_ops = qed_get_rdma_ops(); 870 if (!qed_ops) { 871 DP_ERR(dev, "Failed to get qed roce operations\n"); 872 goto init_err; 873 } 874 875 dev->ops = qed_ops; 876 rc = qed_ops->fill_dev_info(cdev, &dev_info); 877 if (rc) 878 goto init_err; 879 880 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 881 dev->rdma_type = dev_info.rdma_type; 882 dev->num_hwfns = dev_info.common.num_hwfns; 883 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 884 885 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev); 886 if (!dev->num_cnq) { 887 DP_ERR(dev, "Failed. At least one CNQ is required.\n"); 888 rc = -ENOMEM; 889 goto init_err; 890 } 891 892 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT; 893 894 qedr_pci_set_atomic(dev, pdev); 895 896 rc = qedr_alloc_resources(dev); 897 if (rc) 898 goto init_err; 899 900 rc = qedr_init_hw(dev); 901 if (rc) 902 goto alloc_err; 903 904 rc = qedr_setup_irqs(dev); 905 if (rc) 906 goto irq_err; 907 908 rc = qedr_register_device(dev); 909 if (rc) { 910 DP_ERR(dev, "Unable to allocate register device\n"); 911 goto reg_err; 912 } 913 914 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 915 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 916 917 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n"); 918 return dev; 919 920 reg_err: 921 qedr_sync_free_irqs(dev); 922 irq_err: 923 qedr_stop_hw(dev); 924 alloc_err: 925 qedr_free_resources(dev); 926 init_err: 927 ib_dealloc_device(&dev->ibdev); 928 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc); 929 930 return NULL; 931 } 932 933 static void qedr_remove(struct qedr_dev *dev) 934 { 935 /* First unregister with stack to stop all the active traffic 936 * of the registered clients. 937 */ 938 ib_unregister_device(&dev->ibdev); 939 940 qedr_stop_hw(dev); 941 qedr_sync_free_irqs(dev); 942 qedr_free_resources(dev); 943 ib_dealloc_device(&dev->ibdev); 944 } 945 946 static void qedr_close(struct qedr_dev *dev) 947 { 948 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 949 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR); 950 } 951 952 static void qedr_shutdown(struct qedr_dev *dev) 953 { 954 qedr_close(dev); 955 qedr_remove(dev); 956 } 957 958 static void qedr_open(struct qedr_dev *dev) 959 { 960 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 961 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 962 } 963 964 static void qedr_mac_address_change(struct qedr_dev *dev) 965 { 966 union ib_gid *sgid = &dev->sgid_tbl[0]; 967 u8 guid[8], mac_addr[6]; 968 int rc; 969 970 /* Update SGID */ 971 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr); 972 guid[0] = mac_addr[0] ^ 2; 973 guid[1] = mac_addr[1]; 974 guid[2] = mac_addr[2]; 975 guid[3] = 0xff; 976 guid[4] = 0xfe; 977 guid[5] = mac_addr[3]; 978 guid[6] = mac_addr[4]; 979 guid[7] = mac_addr[5]; 980 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL); 981 memcpy(&sgid->raw[8], guid, sizeof(guid)); 982 983 /* Update LL2 */ 984 rc = dev->ops->ll2_set_mac_filter(dev->cdev, 985 dev->gsi_ll2_mac_address, 986 dev->ndev->dev_addr); 987 988 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr); 989 990 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE); 991 992 if (rc) 993 DP_ERR(dev, "Error updating mac filter\n"); 994 } 995 996 /* event handling via NIC driver ensures that all the NIC specific 997 * initialization done before RoCE driver notifies 998 * event to stack. 999 */ 1000 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event) 1001 { 1002 switch (event) { 1003 case QEDE_UP: 1004 qedr_open(dev); 1005 break; 1006 case QEDE_DOWN: 1007 qedr_close(dev); 1008 break; 1009 case QEDE_CLOSE: 1010 qedr_shutdown(dev); 1011 break; 1012 case QEDE_CHANGE_ADDR: 1013 qedr_mac_address_change(dev); 1014 break; 1015 default: 1016 pr_err("Event not supported\n"); 1017 } 1018 } 1019 1020 static struct qedr_driver qedr_drv = { 1021 .name = "qedr_driver", 1022 .add = qedr_add, 1023 .remove = qedr_remove, 1024 .notify = qedr_notify, 1025 }; 1026 1027 static int __init qedr_init_module(void) 1028 { 1029 return qede_rdma_register_driver(&qedr_drv); 1030 } 1031 1032 static void __exit qedr_exit_module(void) 1033 { 1034 qede_rdma_unregister_driver(&qedr_drv); 1035 } 1036 1037 module_init(qedr_init_module); 1038 module_exit(qedr_exit_module); 1039