1 /******************************************************************* 2 * This file is part of the Emulex RoCE Device Driver for * 3 * RoCE (RDMA over Converged Ethernet) adapters. * 4 * Copyright (C) 2008-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 * 20 * Contact Information: 21 * linux-drivers@emulex.com 22 * 23 * Emulex 24 * 3333 Susan Street 25 * Costa Mesa, CA 92626 26 *******************************************************************/ 27 28 #ifndef __OCRDMA_H__ 29 #define __OCRDMA_H__ 30 31 #include <linux/mutex.h> 32 #include <linux/list.h> 33 #include <linux/spinlock.h> 34 #include <linux/pci.h> 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/ib_user_verbs.h> 38 #include <rdma/ib_addr.h> 39 40 #include <be_roce.h> 41 #include "ocrdma_sli.h" 42 43 #define OCRDMA_ROCE_DRV_VERSION "10.4.205.0u" 44 45 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver" 46 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA" 47 48 #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)" 49 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)" 50 51 #define OC_SKH_DEVICE_PF 0x720 52 #define OC_SKH_DEVICE_VF 0x728 53 #define OCRDMA_MAX_AH 512 54 55 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 56 57 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo) 58 #define EQ_INTR_PER_SEC_THRSH_HI 150000 59 #define EQ_INTR_PER_SEC_THRSH_LOW 100000 60 #define EQ_AIC_MAX_EQD 20 61 #define EQ_AIC_MIN_EQD 0 62 63 void ocrdma_eqd_set_task(struct work_struct *work); 64 65 struct ocrdma_dev_attr { 66 u8 fw_ver[32]; 67 u32 vendor_id; 68 u32 device_id; 69 u16 max_pd; 70 u16 max_dpp_pds; 71 u16 max_cq; 72 u16 max_cqe; 73 u16 max_qp; 74 u16 max_wqe; 75 u16 max_rqe; 76 u16 max_srq; 77 u32 max_inline_data; 78 int max_send_sge; 79 int max_recv_sge; 80 int max_srq_sge; 81 int max_rdma_sge; 82 int max_mr; 83 u64 max_mr_size; 84 u32 max_num_mr_pbl; 85 int max_mw; 86 int max_fmr; 87 int max_map_per_fmr; 88 int max_pages_per_frmr; 89 u16 max_ord_per_qp; 90 u16 max_ird_per_qp; 91 92 int device_cap_flags; 93 u8 cq_overflow_detect; 94 u8 srq_supported; 95 96 u32 wqe_size; 97 u32 rqe_size; 98 u32 ird_page_size; 99 u8 local_ca_ack_delay; 100 u8 ird; 101 u8 num_ird_pages; 102 }; 103 104 struct ocrdma_dma_mem { 105 void *va; 106 dma_addr_t pa; 107 u32 size; 108 }; 109 110 struct ocrdma_pbl { 111 void *va; 112 dma_addr_t pa; 113 }; 114 115 struct ocrdma_queue_info { 116 void *va; 117 dma_addr_t dma; 118 u32 size; 119 u16 len; 120 u16 entry_size; /* Size of an element in the queue */ 121 u16 id; /* qid, where to ring the doorbell. */ 122 u16 head, tail; 123 bool created; 124 }; 125 126 struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 127 u32 prev_eqd; 128 u64 eq_intr_cnt; 129 u64 prev_eq_intr_cnt; 130 }; 131 132 struct ocrdma_eq { 133 struct ocrdma_queue_info q; 134 u32 vector; 135 int cq_cnt; 136 struct ocrdma_dev *dev; 137 char irq_name[32]; 138 struct ocrdma_aic_obj aic_obj; 139 }; 140 141 struct ocrdma_mq { 142 struct ocrdma_queue_info sq; 143 struct ocrdma_queue_info cq; 144 bool rearm_cq; 145 }; 146 147 struct mqe_ctx { 148 struct mutex lock; /* for serializing mailbox commands on MQ */ 149 wait_queue_head_t cmd_wait; 150 u32 tag; 151 u16 cqe_status; 152 u16 ext_status; 153 bool cmd_done; 154 bool fw_error_state; 155 }; 156 157 struct ocrdma_hw_mr { 158 u32 lkey; 159 u8 fr_mr; 160 u8 remote_atomic; 161 u8 remote_rd; 162 u8 remote_wr; 163 u8 local_rd; 164 u8 local_wr; 165 u8 mw_bind; 166 u8 rsvd; 167 u64 len; 168 struct ocrdma_pbl *pbl_table; 169 u32 num_pbls; 170 u32 num_pbes; 171 u32 pbl_size; 172 u32 pbe_size; 173 u64 fbo; 174 u64 va; 175 }; 176 177 struct ocrdma_mr { 178 struct ib_mr ibmr; 179 struct ib_umem *umem; 180 struct ocrdma_hw_mr hwmr; 181 }; 182 183 struct ocrdma_stats { 184 u8 type; 185 struct ocrdma_dev *dev; 186 }; 187 188 struct ocrdma_pd_resource_mgr { 189 u32 pd_norm_start; 190 u16 pd_norm_count; 191 u16 pd_norm_thrsh; 192 u16 max_normal_pd; 193 u32 pd_dpp_start; 194 u16 pd_dpp_count; 195 u16 pd_dpp_thrsh; 196 u16 max_dpp_pd; 197 u16 dpp_page_index; 198 unsigned long *pd_norm_bitmap; 199 unsigned long *pd_dpp_bitmap; 200 bool pd_prealloc_valid; 201 }; 202 203 struct stats_mem { 204 struct ocrdma_mqe mqe; 205 void *va; 206 dma_addr_t pa; 207 u32 size; 208 char *debugfs_mem; 209 }; 210 211 struct phy_info { 212 u16 auto_speeds_supported; 213 u16 fixed_speeds_supported; 214 u16 phy_type; 215 u16 interface_type; 216 }; 217 218 struct ocrdma_dev { 219 struct ib_device ibdev; 220 struct ocrdma_dev_attr attr; 221 222 struct mutex dev_lock; /* provides syncronise access to device data */ 223 spinlock_t flush_q_lock ____cacheline_aligned; 224 225 struct ocrdma_cq **cq_tbl; 226 struct ocrdma_qp **qp_tbl; 227 228 struct ocrdma_eq *eq_tbl; 229 int eq_cnt; 230 struct delayed_work eqd_work; 231 u16 base_eqid; 232 u16 max_eq; 233 234 union ib_gid *sgid_tbl; 235 /* provided synchronization to sgid table for 236 * updating gid entries triggered by notifier. 237 */ 238 spinlock_t sgid_lock; 239 240 int gsi_qp_created; 241 struct ocrdma_cq *gsi_sqcq; 242 struct ocrdma_cq *gsi_rqcq; 243 244 struct { 245 struct ocrdma_av *va; 246 dma_addr_t pa; 247 u32 size; 248 u32 num_ah; 249 /* provide synchronization for av 250 * entry allocations. 251 */ 252 spinlock_t lock; 253 u32 ahid; 254 struct ocrdma_pbl pbl; 255 } av_tbl; 256 257 void *mbx_cmd; 258 struct ocrdma_mq mq; 259 struct mqe_ctx mqe_ctx; 260 261 struct be_dev_info nic_info; 262 struct phy_info phy; 263 char model_number[32]; 264 u32 hba_port_num; 265 266 struct list_head entry; 267 struct rcu_head rcu; 268 int id; 269 u64 *stag_arr; 270 u8 sl; /* service level */ 271 bool pfc_state; 272 atomic_t update_sl; 273 u16 pvid; 274 u32 asic_id; 275 276 ulong last_stats_time; 277 struct mutex stats_lock; /* provide synch for debugfs operations */ 278 struct stats_mem stats_mem; 279 struct ocrdma_stats rsrc_stats; 280 struct ocrdma_stats rx_stats; 281 struct ocrdma_stats wqe_stats; 282 struct ocrdma_stats tx_stats; 283 struct ocrdma_stats db_err_stats; 284 struct ocrdma_stats tx_qp_err_stats; 285 struct ocrdma_stats rx_qp_err_stats; 286 struct ocrdma_stats tx_dbg_stats; 287 struct ocrdma_stats rx_dbg_stats; 288 struct ocrdma_stats driver_stats; 289 struct ocrdma_stats reset_stats; 290 struct dentry *dir; 291 atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS]; 292 atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR]; 293 struct ocrdma_pd_resource_mgr *pd_mgr; 294 }; 295 296 struct ocrdma_cq { 297 struct ib_cq ibcq; 298 struct ocrdma_cqe *va; 299 u32 phase; 300 u32 getp; /* pointer to pending wrs to 301 * return to stack, wrap arounds 302 * at max_hw_cqe 303 */ 304 u32 max_hw_cqe; 305 bool phase_change; 306 bool deferred_arm, deferred_sol; 307 bool first_arm; 308 309 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization 310 * to cq polling 311 */ 312 /* syncronizes cq completion handler invoked from multiple context */ 313 spinlock_t comp_handler_lock ____cacheline_aligned; 314 u16 id; 315 u16 eqn; 316 317 struct ocrdma_ucontext *ucontext; 318 dma_addr_t pa; 319 u32 len; 320 u32 cqe_cnt; 321 322 /* head of all qp's sq and rq for which cqes need to be flushed 323 * by the software. 324 */ 325 struct list_head sq_head, rq_head; 326 }; 327 328 struct ocrdma_pd { 329 struct ib_pd ibpd; 330 struct ocrdma_ucontext *uctx; 331 u32 id; 332 int num_dpp_qp; 333 u32 dpp_page; 334 bool dpp_enabled; 335 }; 336 337 struct ocrdma_ah { 338 struct ib_ah ibah; 339 struct ocrdma_av *av; 340 u16 sgid_index; 341 u32 id; 342 }; 343 344 struct ocrdma_qp_hwq_info { 345 u8 *va; /* virtual address */ 346 u32 max_sges; 347 u32 head, tail; 348 u32 entry_size; 349 u32 max_cnt; 350 u32 max_wqe_idx; 351 u16 dbid; /* qid, where to ring the doorbell. */ 352 u32 len; 353 dma_addr_t pa; 354 }; 355 356 struct ocrdma_srq { 357 struct ib_srq ibsrq; 358 u8 __iomem *db; 359 struct ocrdma_qp_hwq_info rq; 360 u64 *rqe_wr_id_tbl; 361 u32 *idx_bit_fields; 362 u32 bit_fields_len; 363 364 /* provide synchronization to multiple context(s) posting rqe */ 365 spinlock_t q_lock ____cacheline_aligned; 366 367 struct ocrdma_pd *pd; 368 u32 id; 369 }; 370 371 struct ocrdma_qp { 372 struct ib_qp ibqp; 373 374 u8 __iomem *sq_db; 375 struct ocrdma_qp_hwq_info sq; 376 struct { 377 uint64_t wrid; 378 uint16_t dpp_wqe_idx; 379 uint16_t dpp_wqe; 380 uint8_t signaled; 381 uint8_t rsvd[3]; 382 } *wqe_wr_id_tbl; 383 u32 max_inline_data; 384 385 /* provide synchronization to multiple context(s) posting wqe, rqe */ 386 spinlock_t q_lock ____cacheline_aligned; 387 struct ocrdma_cq *sq_cq; 388 /* list maintained per CQ to flush SQ errors */ 389 struct list_head sq_entry; 390 391 u8 __iomem *rq_db; 392 struct ocrdma_qp_hwq_info rq; 393 u64 *rqe_wr_id_tbl; 394 struct ocrdma_cq *rq_cq; 395 struct ocrdma_srq *srq; 396 /* list maintained per CQ to flush RQ errors */ 397 struct list_head rq_entry; 398 399 enum ocrdma_qp_state state; /* QP state */ 400 int cap_flags; 401 u32 max_ord, max_ird; 402 403 u32 id; 404 struct ocrdma_pd *pd; 405 406 enum ib_qp_type qp_type; 407 408 int sgid_idx; 409 u32 qkey; 410 bool dpp_enabled; 411 u8 *ird_q_va; 412 bool signaled; 413 }; 414 415 struct ocrdma_ucontext { 416 struct ib_ucontext ibucontext; 417 418 struct list_head mm_head; 419 struct mutex mm_list_lock; /* protects list entries of mm type */ 420 struct ocrdma_pd *cntxt_pd; 421 int pd_in_use; 422 423 struct { 424 u32 *va; 425 dma_addr_t pa; 426 u32 len; 427 } ah_tbl; 428 }; 429 430 struct ocrdma_mm { 431 struct { 432 u64 phy_addr; 433 unsigned long len; 434 } key; 435 struct list_head entry; 436 }; 437 438 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev) 439 { 440 return container_of(ibdev, struct ocrdma_dev, ibdev); 441 } 442 443 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext 444 *ibucontext) 445 { 446 return container_of(ibucontext, struct ocrdma_ucontext, ibucontext); 447 } 448 449 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd) 450 { 451 return container_of(ibpd, struct ocrdma_pd, ibpd); 452 } 453 454 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq) 455 { 456 return container_of(ibcq, struct ocrdma_cq, ibcq); 457 } 458 459 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp) 460 { 461 return container_of(ibqp, struct ocrdma_qp, ibqp); 462 } 463 464 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr) 465 { 466 return container_of(ibmr, struct ocrdma_mr, ibmr); 467 } 468 469 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah) 470 { 471 return container_of(ibah, struct ocrdma_ah, ibah); 472 } 473 474 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq) 475 { 476 return container_of(ibsrq, struct ocrdma_srq, ibsrq); 477 } 478 479 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe) 480 { 481 int cqe_valid; 482 cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID; 483 return (cqe_valid == cq->phase); 484 } 485 486 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe) 487 { 488 return (le32_to_cpu(cqe->flags_status_srcqpn) & 489 OCRDMA_CQE_QTYPE) ? 0 : 1; 490 } 491 492 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe) 493 { 494 return (le32_to_cpu(cqe->flags_status_srcqpn) & 495 OCRDMA_CQE_INVALIDATE) ? 1 : 0; 496 } 497 498 static inline int is_cqe_imm(struct ocrdma_cqe *cqe) 499 { 500 return (le32_to_cpu(cqe->flags_status_srcqpn) & 501 OCRDMA_CQE_IMM) ? 1 : 0; 502 } 503 504 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe) 505 { 506 return (le32_to_cpu(cqe->flags_status_srcqpn) & 507 OCRDMA_CQE_WRITE_IMM) ? 1 : 0; 508 } 509 510 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev, 511 struct ib_ah_attr *ah_attr, u8 *mac_addr) 512 { 513 struct in6_addr in6; 514 515 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6)); 516 if (rdma_is_multicast_addr(&in6)) 517 rdma_get_mcast_mac(&in6, mac_addr); 518 else 519 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN); 520 return 0; 521 } 522 523 static inline char *hca_name(struct ocrdma_dev *dev) 524 { 525 switch (dev->nic_info.pdev->device) { 526 case OC_SKH_DEVICE_PF: 527 case OC_SKH_DEVICE_VF: 528 return OC_NAME_SH; 529 default: 530 return OC_NAME_UNKNOWN; 531 } 532 } 533 534 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev, 535 int eqid) 536 { 537 int indx; 538 539 for (indx = 0; indx < dev->eq_cnt; indx++) { 540 if (dev->eq_tbl[indx].q.id == eqid) 541 return indx; 542 } 543 544 return -EINVAL; 545 } 546 547 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev) 548 { 549 if (dev->nic_info.dev_family == 0xF && !dev->asic_id) { 550 pci_read_config_dword( 551 dev->nic_info.pdev, 552 OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id); 553 } 554 555 return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >> 556 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT; 557 } 558 559 static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio) 560 { 561 return *(pfc + prio); 562 } 563 564 static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio) 565 { 566 return *(app_prio + prio); 567 } 568 569 static inline u8 ocrdma_is_enabled_and_synced(u32 state) 570 { /* May also be used to interpret TC-state, QCN-state 571 * Appl-state and Logical-link-state in future. 572 */ 573 return (state & OCRDMA_STATE_FLAG_ENABLED) && 574 (state & OCRDMA_STATE_FLAG_SYNC); 575 } 576 577 #endif 578