1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 * 36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $ 37 */ 38 39 #ifndef MTHCA_DEV_H 40 #define MTHCA_DEV_H 41 42 #include <linux/spinlock.h> 43 #include <linux/kernel.h> 44 #include <linux/pci.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/timer.h> 47 #include <linux/mutex.h> 48 49 #include <asm/semaphore.h> 50 51 #include "mthca_provider.h" 52 #include "mthca_doorbell.h" 53 54 #define DRV_NAME "ib_mthca" 55 #define PFX DRV_NAME ": " 56 #define DRV_VERSION "0.08" 57 #define DRV_RELDATE "February 14, 2006" 58 59 enum { 60 MTHCA_FLAG_DDR_HIDDEN = 1 << 1, 61 MTHCA_FLAG_SRQ = 1 << 2, 62 MTHCA_FLAG_MSI = 1 << 3, 63 MTHCA_FLAG_MSI_X = 1 << 4, 64 MTHCA_FLAG_NO_LAM = 1 << 5, 65 MTHCA_FLAG_FMR = 1 << 6, 66 MTHCA_FLAG_MEMFREE = 1 << 7, 67 MTHCA_FLAG_PCIE = 1 << 8, 68 MTHCA_FLAG_SINAI_OPT = 1 << 9 69 }; 70 71 enum { 72 MTHCA_MAX_PORTS = 2 73 }; 74 75 enum { 76 MTHCA_BOARD_ID_LEN = 64 77 }; 78 79 enum { 80 MTHCA_EQ_CONTEXT_SIZE = 0x40, 81 MTHCA_CQ_CONTEXT_SIZE = 0x40, 82 MTHCA_QP_CONTEXT_SIZE = 0x200, 83 MTHCA_RDB_ENTRY_SIZE = 0x20, 84 MTHCA_AV_SIZE = 0x20, 85 MTHCA_MGM_ENTRY_SIZE = 0x40, 86 87 /* Arbel FW gives us these, but we need them for Tavor */ 88 MTHCA_MPT_ENTRY_SIZE = 0x40, 89 MTHCA_MTT_SEG_SIZE = 0x40, 90 91 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2) 92 }; 93 94 enum { 95 MTHCA_EQ_CMD, 96 MTHCA_EQ_ASYNC, 97 MTHCA_EQ_COMP, 98 MTHCA_NUM_EQ 99 }; 100 101 enum { 102 MTHCA_OPCODE_NOP = 0x00, 103 MTHCA_OPCODE_RDMA_WRITE = 0x08, 104 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09, 105 MTHCA_OPCODE_SEND = 0x0a, 106 MTHCA_OPCODE_SEND_IMM = 0x0b, 107 MTHCA_OPCODE_RDMA_READ = 0x10, 108 MTHCA_OPCODE_ATOMIC_CS = 0x11, 109 MTHCA_OPCODE_ATOMIC_FA = 0x12, 110 MTHCA_OPCODE_BIND_MW = 0x18, 111 MTHCA_OPCODE_INVALID = 0xff 112 }; 113 114 enum { 115 MTHCA_CMD_USE_EVENTS = 1 << 0, 116 MTHCA_CMD_POST_DOORBELLS = 1 << 1 117 }; 118 119 enum { 120 MTHCA_CMD_NUM_DBELL_DWORDS = 8 121 }; 122 123 struct mthca_cmd { 124 struct pci_pool *pool; 125 struct mutex hcr_mutex; 126 struct semaphore poll_sem; 127 struct semaphore event_sem; 128 int max_cmds; 129 spinlock_t context_lock; 130 int free_head; 131 struct mthca_cmd_context *context; 132 u16 token_mask; 133 u32 flags; 134 void __iomem *dbell_map; 135 u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS]; 136 }; 137 138 struct mthca_limits { 139 int num_ports; 140 int vl_cap; 141 int mtu_cap; 142 int gid_table_len; 143 int pkey_table_len; 144 int local_ca_ack_delay; 145 int num_uars; 146 int max_sg; 147 int num_qps; 148 int max_wqes; 149 int max_desc_sz; 150 int max_qp_init_rdma; 151 int reserved_qps; 152 int num_srqs; 153 int max_srq_wqes; 154 int reserved_srqs; 155 int num_eecs; 156 int reserved_eecs; 157 int num_cqs; 158 int max_cqes; 159 int reserved_cqs; 160 int num_eqs; 161 int reserved_eqs; 162 int num_mpts; 163 int num_mtt_segs; 164 int fmr_reserved_mtts; 165 int reserved_mtts; 166 int reserved_mrws; 167 int reserved_uars; 168 int num_mgms; 169 int num_amgms; 170 int reserved_mcgs; 171 int num_pds; 172 int reserved_pds; 173 u32 page_size_cap; 174 u32 flags; 175 u8 port_width_cap; 176 }; 177 178 struct mthca_alloc { 179 u32 last; 180 u32 top; 181 u32 max; 182 u32 mask; 183 spinlock_t lock; 184 unsigned long *table; 185 }; 186 187 struct mthca_array { 188 struct { 189 void **page; 190 int used; 191 } *page_list; 192 }; 193 194 struct mthca_uar_table { 195 struct mthca_alloc alloc; 196 u64 uarc_base; 197 int uarc_size; 198 }; 199 200 struct mthca_pd_table { 201 struct mthca_alloc alloc; 202 }; 203 204 struct mthca_buddy { 205 unsigned long **bits; 206 int max_order; 207 spinlock_t lock; 208 }; 209 210 struct mthca_mr_table { 211 struct mthca_alloc mpt_alloc; 212 struct mthca_buddy mtt_buddy; 213 struct mthca_buddy *fmr_mtt_buddy; 214 u64 mtt_base; 215 u64 mpt_base; 216 struct mthca_icm_table *mtt_table; 217 struct mthca_icm_table *mpt_table; 218 struct { 219 void __iomem *mpt_base; 220 void __iomem *mtt_base; 221 struct mthca_buddy mtt_buddy; 222 } tavor_fmr; 223 }; 224 225 struct mthca_eq_table { 226 struct mthca_alloc alloc; 227 void __iomem *clr_int; 228 u32 clr_mask; 229 u32 arm_mask; 230 struct mthca_eq eq[MTHCA_NUM_EQ]; 231 u64 icm_virt; 232 struct page *icm_page; 233 dma_addr_t icm_dma; 234 int have_irq; 235 u8 inta_pin; 236 }; 237 238 struct mthca_cq_table { 239 struct mthca_alloc alloc; 240 spinlock_t lock; 241 struct mthca_array cq; 242 struct mthca_icm_table *table; 243 }; 244 245 struct mthca_srq_table { 246 struct mthca_alloc alloc; 247 spinlock_t lock; 248 struct mthca_array srq; 249 struct mthca_icm_table *table; 250 }; 251 252 struct mthca_qp_table { 253 struct mthca_alloc alloc; 254 u32 rdb_base; 255 int rdb_shift; 256 int sqp_start; 257 spinlock_t lock; 258 struct mthca_array qp; 259 struct mthca_icm_table *qp_table; 260 struct mthca_icm_table *eqp_table; 261 struct mthca_icm_table *rdb_table; 262 }; 263 264 struct mthca_av_table { 265 struct pci_pool *pool; 266 int num_ddr_avs; 267 u64 ddr_av_base; 268 void __iomem *av_map; 269 struct mthca_alloc alloc; 270 }; 271 272 struct mthca_mcg_table { 273 struct mutex mutex; 274 struct mthca_alloc alloc; 275 struct mthca_icm_table *table; 276 }; 277 278 struct mthca_catas_err { 279 u64 addr; 280 u32 __iomem *map; 281 unsigned long stop; 282 u32 size; 283 struct timer_list timer; 284 }; 285 286 struct mthca_dev { 287 struct ib_device ib_dev; 288 struct pci_dev *pdev; 289 290 int hca_type; 291 unsigned long mthca_flags; 292 unsigned long device_cap_flags; 293 294 u32 rev_id; 295 char board_id[MTHCA_BOARD_ID_LEN]; 296 297 /* firmware info */ 298 u64 fw_ver; 299 union { 300 struct { 301 u64 fw_start; 302 u64 fw_end; 303 } tavor; 304 struct { 305 u64 clr_int_base; 306 u64 eq_arm_base; 307 u64 eq_set_ci_base; 308 struct mthca_icm *fw_icm; 309 struct mthca_icm *aux_icm; 310 u16 fw_pages; 311 } arbel; 312 } fw; 313 314 u64 ddr_start; 315 u64 ddr_end; 316 317 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock) 318 struct mutex cap_mask_mutex; 319 320 void __iomem *hcr; 321 void __iomem *kar; 322 void __iomem *clr_base; 323 union { 324 struct { 325 void __iomem *ecr_base; 326 } tavor; 327 struct { 328 void __iomem *eq_arm; 329 void __iomem *eq_set_ci_base; 330 } arbel; 331 } eq_regs; 332 333 struct mthca_cmd cmd; 334 struct mthca_limits limits; 335 336 struct mthca_uar_table uar_table; 337 struct mthca_pd_table pd_table; 338 struct mthca_mr_table mr_table; 339 struct mthca_eq_table eq_table; 340 struct mthca_cq_table cq_table; 341 struct mthca_srq_table srq_table; 342 struct mthca_qp_table qp_table; 343 struct mthca_av_table av_table; 344 struct mthca_mcg_table mcg_table; 345 346 struct mthca_catas_err catas_err; 347 348 struct mthca_uar driver_uar; 349 struct mthca_db_table *db_tab; 350 struct mthca_pd driver_pd; 351 struct mthca_mr driver_mr; 352 353 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2]; 354 struct ib_ah *sm_ah[MTHCA_MAX_PORTS]; 355 spinlock_t sm_lock; 356 }; 357 358 #define mthca_dbg(mdev, format, arg...) \ 359 dev_dbg(&mdev->pdev->dev, format, ## arg) 360 #define mthca_err(mdev, format, arg...) \ 361 dev_err(&mdev->pdev->dev, format, ## arg) 362 #define mthca_info(mdev, format, arg...) \ 363 dev_info(&mdev->pdev->dev, format, ## arg) 364 #define mthca_warn(mdev, format, arg...) \ 365 dev_warn(&mdev->pdev->dev, format, ## arg) 366 367 extern void __buggy_use_of_MTHCA_GET(void); 368 extern void __buggy_use_of_MTHCA_PUT(void); 369 370 #define MTHCA_GET(dest, source, offset) \ 371 do { \ 372 void *__p = (char *) (source) + (offset); \ 373 switch (sizeof (dest)) { \ 374 case 1: (dest) = *(u8 *) __p; break; \ 375 case 2: (dest) = be16_to_cpup(__p); break; \ 376 case 4: (dest) = be32_to_cpup(__p); break; \ 377 case 8: (dest) = be64_to_cpup(__p); break; \ 378 default: __buggy_use_of_MTHCA_GET(); \ 379 } \ 380 } while (0) 381 382 #define MTHCA_PUT(dest, source, offset) \ 383 do { \ 384 void *__d = ((char *) (dest) + (offset)); \ 385 switch (sizeof(source)) { \ 386 case 1: *(u8 *) __d = (source); break; \ 387 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 388 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 389 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 390 default: __buggy_use_of_MTHCA_PUT(); \ 391 } \ 392 } while (0) 393 394 int mthca_reset(struct mthca_dev *mdev); 395 396 u32 mthca_alloc(struct mthca_alloc *alloc); 397 void mthca_free(struct mthca_alloc *alloc, u32 obj); 398 int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask, 399 u32 reserved); 400 void mthca_alloc_cleanup(struct mthca_alloc *alloc); 401 void *mthca_array_get(struct mthca_array *array, int index); 402 int mthca_array_set(struct mthca_array *array, int index, void *value); 403 void mthca_array_clear(struct mthca_array *array, int index); 404 int mthca_array_init(struct mthca_array *array, int nent); 405 void mthca_array_cleanup(struct mthca_array *array, int nent); 406 int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct, 407 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd, 408 int hca_write, struct mthca_mr *mr); 409 void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf, 410 int is_direct, struct mthca_mr *mr); 411 412 int mthca_init_uar_table(struct mthca_dev *dev); 413 int mthca_init_pd_table(struct mthca_dev *dev); 414 int mthca_init_mr_table(struct mthca_dev *dev); 415 int mthca_init_eq_table(struct mthca_dev *dev); 416 int mthca_init_cq_table(struct mthca_dev *dev); 417 int mthca_init_srq_table(struct mthca_dev *dev); 418 int mthca_init_qp_table(struct mthca_dev *dev); 419 int mthca_init_av_table(struct mthca_dev *dev); 420 int mthca_init_mcg_table(struct mthca_dev *dev); 421 422 void mthca_cleanup_uar_table(struct mthca_dev *dev); 423 void mthca_cleanup_pd_table(struct mthca_dev *dev); 424 void mthca_cleanup_mr_table(struct mthca_dev *dev); 425 void mthca_cleanup_eq_table(struct mthca_dev *dev); 426 void mthca_cleanup_cq_table(struct mthca_dev *dev); 427 void mthca_cleanup_srq_table(struct mthca_dev *dev); 428 void mthca_cleanup_qp_table(struct mthca_dev *dev); 429 void mthca_cleanup_av_table(struct mthca_dev *dev); 430 void mthca_cleanup_mcg_table(struct mthca_dev *dev); 431 432 int mthca_register_device(struct mthca_dev *dev); 433 void mthca_unregister_device(struct mthca_dev *dev); 434 435 void mthca_start_catas_poll(struct mthca_dev *dev); 436 void mthca_stop_catas_poll(struct mthca_dev *dev); 437 438 int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar); 439 void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar); 440 441 int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd); 442 void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd); 443 444 struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size); 445 void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt); 446 int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt, 447 int start_index, u64 *buffer_list, int list_len); 448 int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift, 449 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr); 450 int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd, 451 u32 access, struct mthca_mr *mr); 452 int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd, 453 u64 *buffer_list, int buffer_size_shift, 454 int list_len, u64 iova, u64 total_size, 455 u32 access, struct mthca_mr *mr); 456 void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr); 457 458 int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd, 459 u32 access, struct mthca_fmr *fmr); 460 int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 461 int list_len, u64 iova); 462 void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 463 int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 464 int list_len, u64 iova); 465 void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 466 int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr); 467 468 int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt); 469 void mthca_unmap_eq_icm(struct mthca_dev *dev); 470 471 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 472 struct ib_wc *entry); 473 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 474 int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 475 int mthca_init_cq(struct mthca_dev *dev, int nent, 476 struct mthca_ucontext *ctx, u32 pdn, 477 struct mthca_cq *cq); 478 void mthca_free_cq(struct mthca_dev *dev, 479 struct mthca_cq *cq); 480 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn); 481 void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 482 enum ib_event_type event_type); 483 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn, 484 struct mthca_srq *srq); 485 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq); 486 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent); 487 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe); 488 489 int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd, 490 struct ib_srq_attr *attr, struct mthca_srq *srq); 491 void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq); 492 int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 493 enum ib_srq_attr_mask attr_mask); 494 int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr); 495 void mthca_srq_event(struct mthca_dev *dev, u32 srqn, 496 enum ib_event_type event_type); 497 void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr); 498 int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr, 499 struct ib_recv_wr **bad_wr); 500 int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr, 501 struct ib_recv_wr **bad_wr); 502 503 void mthca_qp_event(struct mthca_dev *dev, u32 qpn, 504 enum ib_event_type event_type); 505 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 506 struct ib_qp_init_attr *qp_init_attr); 507 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask); 508 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 509 struct ib_send_wr **bad_wr); 510 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 511 struct ib_recv_wr **bad_wr); 512 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 513 struct ib_send_wr **bad_wr); 514 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 515 struct ib_recv_wr **bad_wr); 516 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, 517 int index, int *dbd, __be32 *new_wqe); 518 int mthca_alloc_qp(struct mthca_dev *dev, 519 struct mthca_pd *pd, 520 struct mthca_cq *send_cq, 521 struct mthca_cq *recv_cq, 522 enum ib_qp_type type, 523 enum ib_sig_type send_policy, 524 struct ib_qp_cap *cap, 525 struct mthca_qp *qp); 526 int mthca_alloc_sqp(struct mthca_dev *dev, 527 struct mthca_pd *pd, 528 struct mthca_cq *send_cq, 529 struct mthca_cq *recv_cq, 530 enum ib_sig_type send_policy, 531 struct ib_qp_cap *cap, 532 int qpn, 533 int port, 534 struct mthca_sqp *sqp); 535 void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp); 536 int mthca_create_ah(struct mthca_dev *dev, 537 struct mthca_pd *pd, 538 struct ib_ah_attr *ah_attr, 539 struct mthca_ah *ah); 540 int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah); 541 int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah, 542 struct ib_ud_header *header); 543 int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr); 544 int mthca_ah_grh_present(struct mthca_ah *ah); 545 546 int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 547 int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 548 549 int mthca_process_mad(struct ib_device *ibdev, 550 int mad_flags, 551 u8 port_num, 552 struct ib_wc *in_wc, 553 struct ib_grh *in_grh, 554 struct ib_mad *in_mad, 555 struct ib_mad *out_mad); 556 int mthca_create_agents(struct mthca_dev *dev); 557 void mthca_free_agents(struct mthca_dev *dev); 558 559 static inline struct mthca_dev *to_mdev(struct ib_device *ibdev) 560 { 561 return container_of(ibdev, struct mthca_dev, ib_dev); 562 } 563 564 static inline int mthca_is_memfree(struct mthca_dev *dev) 565 { 566 return dev->mthca_flags & MTHCA_FLAG_MEMFREE; 567 } 568 569 #endif /* MTHCA_DEV_H */ 570