1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 * 36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $ 37 */ 38 39 #ifndef MTHCA_DEV_H 40 #define MTHCA_DEV_H 41 42 #include <linux/spinlock.h> 43 #include <linux/kernel.h> 44 #include <linux/pci.h> 45 #include <linux/dma-mapping.h> 46 #include <asm/semaphore.h> 47 48 #include "mthca_provider.h" 49 #include "mthca_doorbell.h" 50 51 #define DRV_NAME "ib_mthca" 52 #define PFX DRV_NAME ": " 53 #define DRV_VERSION "0.06" 54 #define DRV_RELDATE "June 23, 2005" 55 56 enum { 57 MTHCA_FLAG_DDR_HIDDEN = 1 << 1, 58 MTHCA_FLAG_SRQ = 1 << 2, 59 MTHCA_FLAG_MSI = 1 << 3, 60 MTHCA_FLAG_MSI_X = 1 << 4, 61 MTHCA_FLAG_NO_LAM = 1 << 5, 62 MTHCA_FLAG_FMR = 1 << 6, 63 MTHCA_FLAG_MEMFREE = 1 << 7, 64 MTHCA_FLAG_PCIE = 1 << 8 65 }; 66 67 enum { 68 MTHCA_MAX_PORTS = 2 69 }; 70 71 enum { 72 MTHCA_BOARD_ID_LEN = 64 73 }; 74 75 enum { 76 MTHCA_EQ_CONTEXT_SIZE = 0x40, 77 MTHCA_CQ_CONTEXT_SIZE = 0x40, 78 MTHCA_QP_CONTEXT_SIZE = 0x200, 79 MTHCA_RDB_ENTRY_SIZE = 0x20, 80 MTHCA_AV_SIZE = 0x20, 81 MTHCA_MGM_ENTRY_SIZE = 0x40, 82 83 /* Arbel FW gives us these, but we need them for Tavor */ 84 MTHCA_MPT_ENTRY_SIZE = 0x40, 85 MTHCA_MTT_SEG_SIZE = 0x40, 86 }; 87 88 enum { 89 MTHCA_EQ_CMD, 90 MTHCA_EQ_ASYNC, 91 MTHCA_EQ_COMP, 92 MTHCA_NUM_EQ 93 }; 94 95 enum { 96 MTHCA_OPCODE_NOP = 0x00, 97 MTHCA_OPCODE_RDMA_WRITE = 0x08, 98 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09, 99 MTHCA_OPCODE_SEND = 0x0a, 100 MTHCA_OPCODE_SEND_IMM = 0x0b, 101 MTHCA_OPCODE_RDMA_READ = 0x10, 102 MTHCA_OPCODE_ATOMIC_CS = 0x11, 103 MTHCA_OPCODE_ATOMIC_FA = 0x12, 104 MTHCA_OPCODE_BIND_MW = 0x18, 105 MTHCA_OPCODE_INVALID = 0xff 106 }; 107 108 struct mthca_cmd { 109 struct pci_pool *pool; 110 int use_events; 111 struct semaphore hcr_sem; 112 struct semaphore poll_sem; 113 struct semaphore event_sem; 114 int max_cmds; 115 spinlock_t context_lock; 116 int free_head; 117 struct mthca_cmd_context *context; 118 u16 token_mask; 119 }; 120 121 struct mthca_limits { 122 int num_ports; 123 int vl_cap; 124 int mtu_cap; 125 int gid_table_len; 126 int pkey_table_len; 127 int local_ca_ack_delay; 128 int num_uars; 129 int max_sg; 130 int num_qps; 131 int reserved_qps; 132 int num_srqs; 133 int reserved_srqs; 134 int num_eecs; 135 int reserved_eecs; 136 int num_cqs; 137 int reserved_cqs; 138 int num_eqs; 139 int reserved_eqs; 140 int num_mpts; 141 int num_mtt_segs; 142 int fmr_reserved_mtts; 143 int reserved_mtts; 144 int reserved_mrws; 145 int reserved_uars; 146 int num_mgms; 147 int num_amgms; 148 int reserved_mcgs; 149 int num_pds; 150 int reserved_pds; 151 u8 port_width_cap; 152 }; 153 154 struct mthca_alloc { 155 u32 last; 156 u32 top; 157 u32 max; 158 u32 mask; 159 spinlock_t lock; 160 unsigned long *table; 161 }; 162 163 struct mthca_array { 164 struct { 165 void **page; 166 int used; 167 } *page_list; 168 }; 169 170 struct mthca_uar_table { 171 struct mthca_alloc alloc; 172 u64 uarc_base; 173 int uarc_size; 174 }; 175 176 struct mthca_pd_table { 177 struct mthca_alloc alloc; 178 }; 179 180 struct mthca_buddy { 181 unsigned long **bits; 182 int max_order; 183 spinlock_t lock; 184 }; 185 186 struct mthca_mr_table { 187 struct mthca_alloc mpt_alloc; 188 struct mthca_buddy mtt_buddy; 189 struct mthca_buddy *fmr_mtt_buddy; 190 u64 mtt_base; 191 u64 mpt_base; 192 struct mthca_icm_table *mtt_table; 193 struct mthca_icm_table *mpt_table; 194 struct { 195 void __iomem *mpt_base; 196 void __iomem *mtt_base; 197 struct mthca_buddy mtt_buddy; 198 } tavor_fmr; 199 }; 200 201 struct mthca_eq_table { 202 struct mthca_alloc alloc; 203 void __iomem *clr_int; 204 u32 clr_mask; 205 u32 arm_mask; 206 struct mthca_eq eq[MTHCA_NUM_EQ]; 207 u64 icm_virt; 208 struct page *icm_page; 209 dma_addr_t icm_dma; 210 int have_irq; 211 u8 inta_pin; 212 }; 213 214 struct mthca_cq_table { 215 struct mthca_alloc alloc; 216 spinlock_t lock; 217 struct mthca_array cq; 218 struct mthca_icm_table *table; 219 }; 220 221 struct mthca_srq_table { 222 struct mthca_alloc alloc; 223 spinlock_t lock; 224 struct mthca_array srq; 225 struct mthca_icm_table *table; 226 }; 227 228 struct mthca_qp_table { 229 struct mthca_alloc alloc; 230 u32 rdb_base; 231 int rdb_shift; 232 int sqp_start; 233 spinlock_t lock; 234 struct mthca_array qp; 235 struct mthca_icm_table *qp_table; 236 struct mthca_icm_table *eqp_table; 237 struct mthca_icm_table *rdb_table; 238 }; 239 240 struct mthca_av_table { 241 struct pci_pool *pool; 242 int num_ddr_avs; 243 u64 ddr_av_base; 244 void __iomem *av_map; 245 struct mthca_alloc alloc; 246 }; 247 248 struct mthca_mcg_table { 249 struct semaphore sem; 250 struct mthca_alloc alloc; 251 struct mthca_icm_table *table; 252 }; 253 254 struct mthca_dev { 255 struct ib_device ib_dev; 256 struct pci_dev *pdev; 257 258 int hca_type; 259 unsigned long mthca_flags; 260 unsigned long device_cap_flags; 261 262 u32 rev_id; 263 char board_id[MTHCA_BOARD_ID_LEN]; 264 265 /* firmware info */ 266 u64 fw_ver; 267 union { 268 struct { 269 u64 fw_start; 270 u64 fw_end; 271 } tavor; 272 struct { 273 u64 clr_int_base; 274 u64 eq_arm_base; 275 u64 eq_set_ci_base; 276 struct mthca_icm *fw_icm; 277 struct mthca_icm *aux_icm; 278 u16 fw_pages; 279 } arbel; 280 } fw; 281 282 u64 ddr_start; 283 u64 ddr_end; 284 285 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock) 286 struct semaphore cap_mask_mutex; 287 288 void __iomem *hcr; 289 void __iomem *kar; 290 void __iomem *clr_base; 291 union { 292 struct { 293 void __iomem *ecr_base; 294 } tavor; 295 struct { 296 void __iomem *eq_arm; 297 void __iomem *eq_set_ci_base; 298 } arbel; 299 } eq_regs; 300 301 struct mthca_cmd cmd; 302 struct mthca_limits limits; 303 304 struct mthca_uar_table uar_table; 305 struct mthca_pd_table pd_table; 306 struct mthca_mr_table mr_table; 307 struct mthca_eq_table eq_table; 308 struct mthca_cq_table cq_table; 309 struct mthca_srq_table srq_table; 310 struct mthca_qp_table qp_table; 311 struct mthca_av_table av_table; 312 struct mthca_mcg_table mcg_table; 313 314 struct mthca_uar driver_uar; 315 struct mthca_db_table *db_tab; 316 struct mthca_pd driver_pd; 317 struct mthca_mr driver_mr; 318 319 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2]; 320 struct ib_ah *sm_ah[MTHCA_MAX_PORTS]; 321 spinlock_t sm_lock; 322 }; 323 324 #define mthca_dbg(mdev, format, arg...) \ 325 dev_dbg(&mdev->pdev->dev, format, ## arg) 326 #define mthca_err(mdev, format, arg...) \ 327 dev_err(&mdev->pdev->dev, format, ## arg) 328 #define mthca_info(mdev, format, arg...) \ 329 dev_info(&mdev->pdev->dev, format, ## arg) 330 #define mthca_warn(mdev, format, arg...) \ 331 dev_warn(&mdev->pdev->dev, format, ## arg) 332 333 extern void __buggy_use_of_MTHCA_GET(void); 334 extern void __buggy_use_of_MTHCA_PUT(void); 335 336 #define MTHCA_GET(dest, source, offset) \ 337 do { \ 338 void *__p = (char *) (source) + (offset); \ 339 switch (sizeof (dest)) { \ 340 case 1: (dest) = *(u8 *) __p; break; \ 341 case 2: (dest) = be16_to_cpup(__p); break; \ 342 case 4: (dest) = be32_to_cpup(__p); break; \ 343 case 8: (dest) = be64_to_cpup(__p); break; \ 344 default: __buggy_use_of_MTHCA_GET(); \ 345 } \ 346 } while (0) 347 348 #define MTHCA_PUT(dest, source, offset) \ 349 do { \ 350 void *__d = ((char *) (dest) + (offset)); \ 351 switch (sizeof(source)) { \ 352 case 1: *(u8 *) __d = (source); break; \ 353 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 354 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 355 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 356 default: __buggy_use_of_MTHCA_PUT(); \ 357 } \ 358 } while (0) 359 360 int mthca_reset(struct mthca_dev *mdev); 361 362 u32 mthca_alloc(struct mthca_alloc *alloc); 363 void mthca_free(struct mthca_alloc *alloc, u32 obj); 364 int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask, 365 u32 reserved); 366 void mthca_alloc_cleanup(struct mthca_alloc *alloc); 367 void *mthca_array_get(struct mthca_array *array, int index); 368 int mthca_array_set(struct mthca_array *array, int index, void *value); 369 void mthca_array_clear(struct mthca_array *array, int index); 370 int mthca_array_init(struct mthca_array *array, int nent); 371 void mthca_array_cleanup(struct mthca_array *array, int nent); 372 int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct, 373 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd, 374 int hca_write, struct mthca_mr *mr); 375 void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf, 376 int is_direct, struct mthca_mr *mr); 377 378 int mthca_init_uar_table(struct mthca_dev *dev); 379 int mthca_init_pd_table(struct mthca_dev *dev); 380 int mthca_init_mr_table(struct mthca_dev *dev); 381 int mthca_init_eq_table(struct mthca_dev *dev); 382 int mthca_init_cq_table(struct mthca_dev *dev); 383 int mthca_init_srq_table(struct mthca_dev *dev); 384 int mthca_init_qp_table(struct mthca_dev *dev); 385 int mthca_init_av_table(struct mthca_dev *dev); 386 int mthca_init_mcg_table(struct mthca_dev *dev); 387 388 void mthca_cleanup_uar_table(struct mthca_dev *dev); 389 void mthca_cleanup_pd_table(struct mthca_dev *dev); 390 void mthca_cleanup_mr_table(struct mthca_dev *dev); 391 void mthca_cleanup_eq_table(struct mthca_dev *dev); 392 void mthca_cleanup_cq_table(struct mthca_dev *dev); 393 void mthca_cleanup_srq_table(struct mthca_dev *dev); 394 void mthca_cleanup_qp_table(struct mthca_dev *dev); 395 void mthca_cleanup_av_table(struct mthca_dev *dev); 396 void mthca_cleanup_mcg_table(struct mthca_dev *dev); 397 398 int mthca_register_device(struct mthca_dev *dev); 399 void mthca_unregister_device(struct mthca_dev *dev); 400 401 int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar); 402 void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar); 403 404 int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd); 405 void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd); 406 407 struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size); 408 void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt); 409 int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt, 410 int start_index, u64 *buffer_list, int list_len); 411 int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift, 412 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr); 413 int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd, 414 u32 access, struct mthca_mr *mr); 415 int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd, 416 u64 *buffer_list, int buffer_size_shift, 417 int list_len, u64 iova, u64 total_size, 418 u32 access, struct mthca_mr *mr); 419 void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr); 420 421 int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd, 422 u32 access, struct mthca_fmr *fmr); 423 int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 424 int list_len, u64 iova); 425 void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 426 int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 427 int list_len, u64 iova); 428 void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 429 int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr); 430 431 int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt); 432 void mthca_unmap_eq_icm(struct mthca_dev *dev); 433 434 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 435 struct ib_wc *entry); 436 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 437 int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 438 int mthca_init_cq(struct mthca_dev *dev, int nent, 439 struct mthca_ucontext *ctx, u32 pdn, 440 struct mthca_cq *cq); 441 void mthca_free_cq(struct mthca_dev *dev, 442 struct mthca_cq *cq); 443 void mthca_cq_event(struct mthca_dev *dev, u32 cqn); 444 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn, 445 struct mthca_srq *srq); 446 447 int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd, 448 struct ib_srq_attr *attr, struct mthca_srq *srq); 449 void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq); 450 void mthca_srq_event(struct mthca_dev *dev, u32 srqn, 451 enum ib_event_type event_type); 452 void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr); 453 int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr, 454 struct ib_recv_wr **bad_wr); 455 int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr, 456 struct ib_recv_wr **bad_wr); 457 458 void mthca_qp_event(struct mthca_dev *dev, u32 qpn, 459 enum ib_event_type event_type); 460 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask); 461 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 462 struct ib_send_wr **bad_wr); 463 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 464 struct ib_recv_wr **bad_wr); 465 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 466 struct ib_send_wr **bad_wr); 467 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 468 struct ib_recv_wr **bad_wr); 469 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, 470 int index, int *dbd, __be32 *new_wqe); 471 int mthca_alloc_qp(struct mthca_dev *dev, 472 struct mthca_pd *pd, 473 struct mthca_cq *send_cq, 474 struct mthca_cq *recv_cq, 475 enum ib_qp_type type, 476 enum ib_sig_type send_policy, 477 struct ib_qp_cap *cap, 478 struct mthca_qp *qp); 479 int mthca_alloc_sqp(struct mthca_dev *dev, 480 struct mthca_pd *pd, 481 struct mthca_cq *send_cq, 482 struct mthca_cq *recv_cq, 483 enum ib_sig_type send_policy, 484 struct ib_qp_cap *cap, 485 int qpn, 486 int port, 487 struct mthca_sqp *sqp); 488 void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp); 489 int mthca_create_ah(struct mthca_dev *dev, 490 struct mthca_pd *pd, 491 struct ib_ah_attr *ah_attr, 492 struct mthca_ah *ah); 493 int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah); 494 int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah, 495 struct ib_ud_header *header); 496 497 int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 498 int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 499 500 int mthca_process_mad(struct ib_device *ibdev, 501 int mad_flags, 502 u8 port_num, 503 struct ib_wc *in_wc, 504 struct ib_grh *in_grh, 505 struct ib_mad *in_mad, 506 struct ib_mad *out_mad); 507 int mthca_create_agents(struct mthca_dev *dev); 508 void mthca_free_agents(struct mthca_dev *dev); 509 510 static inline struct mthca_dev *to_mdev(struct ib_device *ibdev) 511 { 512 return container_of(ibdev, struct mthca_dev, ib_dev); 513 } 514 515 static inline int mthca_is_memfree(struct mthca_dev *dev) 516 { 517 return dev->mthca_flags & MTHCA_FLAG_MEMFREE; 518 } 519 520 #endif /* MTHCA_DEV_H */ 521