1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 * 34 * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $ 35 */ 36 37 #include <linux/sched.h> 38 #include <linux/pci.h> 39 #include <linux/errno.h> 40 #include <asm/io.h> 41 #include <rdma/ib_mad.h> 42 43 #include "mthca_dev.h" 44 #include "mthca_config_reg.h" 45 #include "mthca_cmd.h" 46 #include "mthca_memfree.h" 47 48 #define CMD_POLL_TOKEN 0xffff 49 50 enum { 51 HCR_IN_PARAM_OFFSET = 0x00, 52 HCR_IN_MODIFIER_OFFSET = 0x08, 53 HCR_OUT_PARAM_OFFSET = 0x0c, 54 HCR_TOKEN_OFFSET = 0x14, 55 HCR_STATUS_OFFSET = 0x18, 56 57 HCR_OPMOD_SHIFT = 12, 58 HCA_E_BIT = 22, 59 HCR_GO_BIT = 23 60 }; 61 62 enum { 63 /* initialization and general commands */ 64 CMD_SYS_EN = 0x1, 65 CMD_SYS_DIS = 0x2, 66 CMD_MAP_FA = 0xfff, 67 CMD_UNMAP_FA = 0xffe, 68 CMD_RUN_FW = 0xff6, 69 CMD_MOD_STAT_CFG = 0x34, 70 CMD_QUERY_DEV_LIM = 0x3, 71 CMD_QUERY_FW = 0x4, 72 CMD_ENABLE_LAM = 0xff8, 73 CMD_DISABLE_LAM = 0xff7, 74 CMD_QUERY_DDR = 0x5, 75 CMD_QUERY_ADAPTER = 0x6, 76 CMD_INIT_HCA = 0x7, 77 CMD_CLOSE_HCA = 0x8, 78 CMD_INIT_IB = 0x9, 79 CMD_CLOSE_IB = 0xa, 80 CMD_QUERY_HCA = 0xb, 81 CMD_SET_IB = 0xc, 82 CMD_ACCESS_DDR = 0x2e, 83 CMD_MAP_ICM = 0xffa, 84 CMD_UNMAP_ICM = 0xff9, 85 CMD_MAP_ICM_AUX = 0xffc, 86 CMD_UNMAP_ICM_AUX = 0xffb, 87 CMD_SET_ICM_SIZE = 0xffd, 88 89 /* TPT commands */ 90 CMD_SW2HW_MPT = 0xd, 91 CMD_QUERY_MPT = 0xe, 92 CMD_HW2SW_MPT = 0xf, 93 CMD_READ_MTT = 0x10, 94 CMD_WRITE_MTT = 0x11, 95 CMD_SYNC_TPT = 0x2f, 96 97 /* EQ commands */ 98 CMD_MAP_EQ = 0x12, 99 CMD_SW2HW_EQ = 0x13, 100 CMD_HW2SW_EQ = 0x14, 101 CMD_QUERY_EQ = 0x15, 102 103 /* CQ commands */ 104 CMD_SW2HW_CQ = 0x16, 105 CMD_HW2SW_CQ = 0x17, 106 CMD_QUERY_CQ = 0x18, 107 CMD_RESIZE_CQ = 0x2c, 108 109 /* SRQ commands */ 110 CMD_SW2HW_SRQ = 0x35, 111 CMD_HW2SW_SRQ = 0x36, 112 CMD_QUERY_SRQ = 0x37, 113 CMD_ARM_SRQ = 0x40, 114 115 /* QP/EE commands */ 116 CMD_RST2INIT_QPEE = 0x19, 117 CMD_INIT2RTR_QPEE = 0x1a, 118 CMD_RTR2RTS_QPEE = 0x1b, 119 CMD_RTS2RTS_QPEE = 0x1c, 120 CMD_SQERR2RTS_QPEE = 0x1d, 121 CMD_2ERR_QPEE = 0x1e, 122 CMD_RTS2SQD_QPEE = 0x1f, 123 CMD_SQD2SQD_QPEE = 0x38, 124 CMD_SQD2RTS_QPEE = 0x20, 125 CMD_ERR2RST_QPEE = 0x21, 126 CMD_QUERY_QPEE = 0x22, 127 CMD_INIT2INIT_QPEE = 0x2d, 128 CMD_SUSPEND_QPEE = 0x32, 129 CMD_UNSUSPEND_QPEE = 0x33, 130 /* special QPs and management commands */ 131 CMD_CONF_SPECIAL_QP = 0x23, 132 CMD_MAD_IFC = 0x24, 133 134 /* multicast commands */ 135 CMD_READ_MGM = 0x25, 136 CMD_WRITE_MGM = 0x26, 137 CMD_MGID_HASH = 0x27, 138 139 /* miscellaneous commands */ 140 CMD_DIAG_RPRT = 0x30, 141 CMD_NOP = 0x31, 142 143 /* debug commands */ 144 CMD_QUERY_DEBUG_MSG = 0x2a, 145 CMD_SET_DEBUG_MSG = 0x2b, 146 }; 147 148 /* 149 * According to Mellanox code, FW may be starved and never complete 150 * commands. So we can't use strict timeouts described in PRM -- we 151 * just arbitrarily select 60 seconds for now. 152 */ 153 #if 0 154 /* 155 * Round up and add 1 to make sure we get the full wait time (since we 156 * will be starting in the middle of a jiffy) 157 */ 158 enum { 159 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, 160 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, 161 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1 162 }; 163 #else 164 enum { 165 CMD_TIME_CLASS_A = 60 * HZ, 166 CMD_TIME_CLASS_B = 60 * HZ, 167 CMD_TIME_CLASS_C = 60 * HZ 168 }; 169 #endif 170 171 enum { 172 GO_BIT_TIMEOUT = HZ * 10 173 }; 174 175 struct mthca_cmd_context { 176 struct completion done; 177 int result; 178 int next; 179 u64 out_param; 180 u16 token; 181 u8 status; 182 }; 183 184 static int fw_cmd_doorbell = 0; 185 module_param(fw_cmd_doorbell, int, 0644); 186 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero " 187 "(and supported by FW)"); 188 189 static inline int go_bit(struct mthca_dev *dev) 190 { 191 return readl(dev->hcr + HCR_STATUS_OFFSET) & 192 swab32(1 << HCR_GO_BIT); 193 } 194 195 static void mthca_cmd_post_dbell(struct mthca_dev *dev, 196 u64 in_param, 197 u64 out_param, 198 u32 in_modifier, 199 u8 op_modifier, 200 u16 op, 201 u16 token) 202 { 203 void __iomem *ptr = dev->cmd.dbell_map; 204 u16 *offs = dev->cmd.dbell_offsets; 205 206 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); 207 wmb(); 208 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); 209 wmb(); 210 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]); 211 wmb(); 212 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]); 213 wmb(); 214 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); 215 wmb(); 216 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]); 217 wmb(); 218 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 219 (1 << HCA_E_BIT) | 220 (op_modifier << HCR_OPMOD_SHIFT) | 221 op), ptr + offs[6]); 222 wmb(); 223 __raw_writel((__force u32) 0, ptr + offs[7]); 224 wmb(); 225 } 226 227 static int mthca_cmd_post_hcr(struct mthca_dev *dev, 228 u64 in_param, 229 u64 out_param, 230 u32 in_modifier, 231 u8 op_modifier, 232 u16 op, 233 u16 token, 234 int event) 235 { 236 if (event) { 237 unsigned long end = jiffies + GO_BIT_TIMEOUT; 238 239 while (go_bit(dev) && time_before(jiffies, end)) { 240 set_current_state(TASK_RUNNING); 241 schedule(); 242 } 243 } 244 245 if (go_bit(dev)) 246 return -EAGAIN; 247 248 /* 249 * We use writel (instead of something like memcpy_toio) 250 * because writes of less than 32 bits to the HCR don't work 251 * (and some architectures such as ia64 implement memcpy_toio 252 * in terms of writeb). 253 */ 254 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); 255 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); 256 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); 257 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); 258 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); 259 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); 260 261 /* __raw_writel may not order writes. */ 262 wmb(); 263 264 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 265 (event ? (1 << HCA_E_BIT) : 0) | 266 (op_modifier << HCR_OPMOD_SHIFT) | 267 op), dev->hcr + 6 * 4); 268 269 return 0; 270 } 271 272 static int mthca_cmd_post(struct mthca_dev *dev, 273 u64 in_param, 274 u64 out_param, 275 u32 in_modifier, 276 u8 op_modifier, 277 u16 op, 278 u16 token, 279 int event) 280 { 281 int err = 0; 282 283 mutex_lock(&dev->cmd.hcr_mutex); 284 285 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell) 286 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier, 287 op_modifier, op, token); 288 else 289 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier, 290 op_modifier, op, token, event); 291 292 mutex_unlock(&dev->cmd.hcr_mutex); 293 return err; 294 } 295 296 static int mthca_cmd_poll(struct mthca_dev *dev, 297 u64 in_param, 298 u64 *out_param, 299 int out_is_imm, 300 u32 in_modifier, 301 u8 op_modifier, 302 u16 op, 303 unsigned long timeout, 304 u8 *status) 305 { 306 int err = 0; 307 unsigned long end; 308 309 down(&dev->cmd.poll_sem); 310 311 err = mthca_cmd_post(dev, in_param, 312 out_param ? *out_param : 0, 313 in_modifier, op_modifier, 314 op, CMD_POLL_TOKEN, 0); 315 if (err) 316 goto out; 317 318 end = timeout + jiffies; 319 while (go_bit(dev) && time_before(jiffies, end)) { 320 set_current_state(TASK_RUNNING); 321 schedule(); 322 } 323 324 if (go_bit(dev)) { 325 err = -EBUSY; 326 goto out; 327 } 328 329 if (out_is_imm) 330 *out_param = 331 (u64) be32_to_cpu((__force __be32) 332 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 333 (u64) be32_to_cpu((__force __be32) 334 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); 335 336 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; 337 338 out: 339 up(&dev->cmd.poll_sem); 340 return err; 341 } 342 343 void mthca_cmd_event(struct mthca_dev *dev, 344 u16 token, 345 u8 status, 346 u64 out_param) 347 { 348 struct mthca_cmd_context *context = 349 &dev->cmd.context[token & dev->cmd.token_mask]; 350 351 /* previously timed out command completing at long last */ 352 if (token != context->token) 353 return; 354 355 context->result = 0; 356 context->status = status; 357 context->out_param = out_param; 358 359 context->token += dev->cmd.token_mask + 1; 360 361 complete(&context->done); 362 } 363 364 static int mthca_cmd_wait(struct mthca_dev *dev, 365 u64 in_param, 366 u64 *out_param, 367 int out_is_imm, 368 u32 in_modifier, 369 u8 op_modifier, 370 u16 op, 371 unsigned long timeout, 372 u8 *status) 373 { 374 int err = 0; 375 struct mthca_cmd_context *context; 376 377 down(&dev->cmd.event_sem); 378 379 spin_lock(&dev->cmd.context_lock); 380 BUG_ON(dev->cmd.free_head < 0); 381 context = &dev->cmd.context[dev->cmd.free_head]; 382 dev->cmd.free_head = context->next; 383 spin_unlock(&dev->cmd.context_lock); 384 385 init_completion(&context->done); 386 387 err = mthca_cmd_post(dev, in_param, 388 out_param ? *out_param : 0, 389 in_modifier, op_modifier, 390 op, context->token, 1); 391 if (err) 392 goto out; 393 394 if (!wait_for_completion_timeout(&context->done, timeout)) { 395 err = -EBUSY; 396 goto out; 397 } 398 399 err = context->result; 400 if (err) 401 goto out; 402 403 *status = context->status; 404 if (*status) 405 mthca_dbg(dev, "Command %02x completed with status %02x\n", 406 op, *status); 407 408 if (out_is_imm) 409 *out_param = context->out_param; 410 411 out: 412 spin_lock(&dev->cmd.context_lock); 413 context->next = dev->cmd.free_head; 414 dev->cmd.free_head = context - dev->cmd.context; 415 spin_unlock(&dev->cmd.context_lock); 416 417 up(&dev->cmd.event_sem); 418 return err; 419 } 420 421 /* Invoke a command with an output mailbox */ 422 static int mthca_cmd_box(struct mthca_dev *dev, 423 u64 in_param, 424 u64 out_param, 425 u32 in_modifier, 426 u8 op_modifier, 427 u16 op, 428 unsigned long timeout, 429 u8 *status) 430 { 431 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 432 return mthca_cmd_wait(dev, in_param, &out_param, 0, 433 in_modifier, op_modifier, op, 434 timeout, status); 435 else 436 return mthca_cmd_poll(dev, in_param, &out_param, 0, 437 in_modifier, op_modifier, op, 438 timeout, status); 439 } 440 441 /* Invoke a command with no output parameter */ 442 static int mthca_cmd(struct mthca_dev *dev, 443 u64 in_param, 444 u32 in_modifier, 445 u8 op_modifier, 446 u16 op, 447 unsigned long timeout, 448 u8 *status) 449 { 450 return mthca_cmd_box(dev, in_param, 0, in_modifier, 451 op_modifier, op, timeout, status); 452 } 453 454 /* 455 * Invoke a command with an immediate output parameter (and copy the 456 * output into the caller's out_param pointer after the command 457 * executes). 458 */ 459 static int mthca_cmd_imm(struct mthca_dev *dev, 460 u64 in_param, 461 u64 *out_param, 462 u32 in_modifier, 463 u8 op_modifier, 464 u16 op, 465 unsigned long timeout, 466 u8 *status) 467 { 468 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 469 return mthca_cmd_wait(dev, in_param, out_param, 1, 470 in_modifier, op_modifier, op, 471 timeout, status); 472 else 473 return mthca_cmd_poll(dev, in_param, out_param, 1, 474 in_modifier, op_modifier, op, 475 timeout, status); 476 } 477 478 int mthca_cmd_init(struct mthca_dev *dev) 479 { 480 mutex_init(&dev->cmd.hcr_mutex); 481 sema_init(&dev->cmd.poll_sem, 1); 482 dev->cmd.flags = 0; 483 484 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, 485 MTHCA_HCR_SIZE); 486 if (!dev->hcr) { 487 mthca_err(dev, "Couldn't map command register."); 488 return -ENOMEM; 489 } 490 491 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, 492 MTHCA_MAILBOX_SIZE, 493 MTHCA_MAILBOX_SIZE, 0); 494 if (!dev->cmd.pool) { 495 iounmap(dev->hcr); 496 return -ENOMEM; 497 } 498 499 return 0; 500 } 501 502 void mthca_cmd_cleanup(struct mthca_dev *dev) 503 { 504 pci_pool_destroy(dev->cmd.pool); 505 iounmap(dev->hcr); 506 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS) 507 iounmap(dev->cmd.dbell_map); 508 } 509 510 /* 511 * Switch to using events to issue FW commands (should be called after 512 * event queue to command events has been initialized). 513 */ 514 int mthca_cmd_use_events(struct mthca_dev *dev) 515 { 516 int i; 517 518 dev->cmd.context = kmalloc(dev->cmd.max_cmds * 519 sizeof (struct mthca_cmd_context), 520 GFP_KERNEL); 521 if (!dev->cmd.context) 522 return -ENOMEM; 523 524 for (i = 0; i < dev->cmd.max_cmds; ++i) { 525 dev->cmd.context[i].token = i; 526 dev->cmd.context[i].next = i + 1; 527 } 528 529 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; 530 dev->cmd.free_head = 0; 531 532 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); 533 spin_lock_init(&dev->cmd.context_lock); 534 535 for (dev->cmd.token_mask = 1; 536 dev->cmd.token_mask < dev->cmd.max_cmds; 537 dev->cmd.token_mask <<= 1) 538 ; /* nothing */ 539 --dev->cmd.token_mask; 540 541 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS; 542 543 down(&dev->cmd.poll_sem); 544 545 return 0; 546 } 547 548 /* 549 * Switch back to polling (used when shutting down the device) 550 */ 551 void mthca_cmd_use_polling(struct mthca_dev *dev) 552 { 553 int i; 554 555 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS; 556 557 for (i = 0; i < dev->cmd.max_cmds; ++i) 558 down(&dev->cmd.event_sem); 559 560 kfree(dev->cmd.context); 561 562 up(&dev->cmd.poll_sem); 563 } 564 565 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, 566 gfp_t gfp_mask) 567 { 568 struct mthca_mailbox *mailbox; 569 570 mailbox = kmalloc(sizeof *mailbox, gfp_mask); 571 if (!mailbox) 572 return ERR_PTR(-ENOMEM); 573 574 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); 575 if (!mailbox->buf) { 576 kfree(mailbox); 577 return ERR_PTR(-ENOMEM); 578 } 579 580 return mailbox; 581 } 582 583 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) 584 { 585 if (!mailbox) 586 return; 587 588 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); 589 kfree(mailbox); 590 } 591 592 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status) 593 { 594 u64 out; 595 int ret; 596 597 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status); 598 599 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) 600 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " 601 "sladdr=%d, SPD source=%s\n", 602 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, 603 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); 604 605 return ret; 606 } 607 608 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) 609 { 610 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status); 611 } 612 613 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, 614 u64 virt, u8 *status) 615 { 616 struct mthca_mailbox *mailbox; 617 struct mthca_icm_iter iter; 618 __be64 *pages; 619 int lg; 620 int nent = 0; 621 int i; 622 int err = 0; 623 int ts = 0, tc = 0; 624 625 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 626 if (IS_ERR(mailbox)) 627 return PTR_ERR(mailbox); 628 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); 629 pages = mailbox->buf; 630 631 for (mthca_icm_first(icm, &iter); 632 !mthca_icm_last(&iter); 633 mthca_icm_next(&iter)) { 634 /* 635 * We have to pass pages that are aligned to their 636 * size, so find the least significant 1 in the 637 * address or size and use that as our log2 size. 638 */ 639 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; 640 if (lg < MTHCA_ICM_PAGE_SHIFT) { 641 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 642 MTHCA_ICM_PAGE_SIZE, 643 (unsigned long long) mthca_icm_addr(&iter), 644 mthca_icm_size(&iter)); 645 err = -EINVAL; 646 goto out; 647 } 648 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { 649 if (virt != -1) { 650 pages[nent * 2] = cpu_to_be64(virt); 651 virt += 1 << lg; 652 } 653 654 pages[nent * 2 + 1] = 655 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) | 656 (lg - MTHCA_ICM_PAGE_SHIFT)); 657 ts += 1 << (lg - 10); 658 ++tc; 659 660 if (++nent == MTHCA_MAILBOX_SIZE / 16) { 661 err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 662 CMD_TIME_CLASS_B, status); 663 if (err || *status) 664 goto out; 665 nent = 0; 666 } 667 } 668 } 669 670 if (nent) 671 err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 672 CMD_TIME_CLASS_B, status); 673 674 switch (op) { 675 case CMD_MAP_FA: 676 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 677 break; 678 case CMD_MAP_ICM_AUX: 679 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 680 break; 681 case CMD_MAP_ICM: 682 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 683 tc, ts, (unsigned long long) virt - (ts << 10)); 684 break; 685 } 686 687 out: 688 mthca_free_mailbox(dev, mailbox); 689 return err; 690 } 691 692 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 693 { 694 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status); 695 } 696 697 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status) 698 { 699 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status); 700 } 701 702 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status) 703 { 704 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status); 705 } 706 707 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) 708 { 709 unsigned long addr; 710 u16 max_off = 0; 711 int i; 712 713 for (i = 0; i < 8; ++i) 714 max_off = max(max_off, dev->cmd.dbell_offsets[i]); 715 716 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { 717 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " 718 "length 0x%x crosses a page boundary\n", 719 (unsigned long long) base, max_off); 720 return; 721 } 722 723 addr = pci_resource_start(dev->pdev, 2) + 724 ((pci_resource_len(dev->pdev, 2) - 1) & base); 725 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32)); 726 if (!dev->cmd.dbell_map) 727 return; 728 729 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS; 730 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n"); 731 } 732 733 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status) 734 { 735 struct mthca_mailbox *mailbox; 736 u32 *outbox; 737 u64 base; 738 u32 tmp; 739 int err = 0; 740 u8 lg; 741 int i; 742 743 #define QUERY_FW_OUT_SIZE 0x100 744 #define QUERY_FW_VER_OFFSET 0x00 745 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 746 #define QUERY_FW_ERR_START_OFFSET 0x30 747 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 748 749 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10 750 #define QUERY_FW_CMD_DB_OFFSET 0x50 751 #define QUERY_FW_CMD_DB_BASE 0x60 752 753 #define QUERY_FW_START_OFFSET 0x20 754 #define QUERY_FW_END_OFFSET 0x28 755 756 #define QUERY_FW_SIZE_OFFSET 0x00 757 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 758 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 759 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 760 761 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 762 if (IS_ERR(mailbox)) 763 return PTR_ERR(mailbox); 764 outbox = mailbox->buf; 765 766 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, 767 CMD_TIME_CLASS_A, status); 768 769 if (err) 770 goto out; 771 772 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); 773 /* 774 * FW subminor version is at more signifant bits than minor 775 * version, so swap here. 776 */ 777 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | 778 ((dev->fw_ver & 0xffff0000ull) >> 16) | 779 ((dev->fw_ver & 0x0000ffffull) << 16); 780 781 mthca_dbg(dev, "FW version %012llx, max commands %d\n", 782 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); 783 784 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 785 dev->cmd.max_cmds = 1 << lg; 786 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); 787 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 788 789 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", 790 (unsigned long long) dev->catas_err.addr, dev->catas_err.size); 791 792 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET); 793 if (tmp & 0x1) { 794 mthca_dbg(dev, "FW supports commands through doorbells\n"); 795 796 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); 797 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) 798 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox, 799 QUERY_FW_CMD_DB_OFFSET + (i << 1)); 800 801 mthca_setup_cmd_doorbells(dev, base); 802 } 803 804 if (mthca_is_memfree(dev)) { 805 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 806 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 807 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); 808 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); 809 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); 810 811 /* 812 * Round up number of system pages needed in case 813 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 814 */ 815 dev->fw.arbel.fw_pages = 816 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 817 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 818 819 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", 820 (unsigned long long) dev->fw.arbel.clr_int_base, 821 (unsigned long long) dev->fw.arbel.eq_arm_base, 822 (unsigned long long) dev->fw.arbel.eq_set_ci_base); 823 } else { 824 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); 825 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); 826 827 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", 828 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), 829 (unsigned long long) dev->fw.tavor.fw_start, 830 (unsigned long long) dev->fw.tavor.fw_end); 831 } 832 833 out: 834 mthca_free_mailbox(dev, mailbox); 835 return err; 836 } 837 838 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status) 839 { 840 struct mthca_mailbox *mailbox; 841 u8 info; 842 u32 *outbox; 843 int err = 0; 844 845 #define ENABLE_LAM_OUT_SIZE 0x100 846 #define ENABLE_LAM_START_OFFSET 0x00 847 #define ENABLE_LAM_END_OFFSET 0x08 848 #define ENABLE_LAM_INFO_OFFSET 0x13 849 850 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) 851 #define ENABLE_LAM_INFO_ECC_MASK 0x3 852 853 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 854 if (IS_ERR(mailbox)) 855 return PTR_ERR(mailbox); 856 outbox = mailbox->buf; 857 858 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, 859 CMD_TIME_CLASS_C, status); 860 861 if (err) 862 goto out; 863 864 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE) 865 goto out; 866 867 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); 868 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); 869 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); 870 871 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != 872 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 873 mthca_info(dev, "FW reports that HCA-attached memory " 874 "is %s hidden; does not match PCI config\n", 875 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? 876 "" : "not"); 877 } 878 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) 879 mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 880 881 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 882 (int) ((dev->ddr_end - dev->ddr_start) >> 10), 883 (unsigned long long) dev->ddr_start, 884 (unsigned long long) dev->ddr_end); 885 886 out: 887 mthca_free_mailbox(dev, mailbox); 888 return err; 889 } 890 891 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status) 892 { 893 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); 894 } 895 896 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status) 897 { 898 struct mthca_mailbox *mailbox; 899 u8 info; 900 u32 *outbox; 901 int err = 0; 902 903 #define QUERY_DDR_OUT_SIZE 0x100 904 #define QUERY_DDR_START_OFFSET 0x00 905 #define QUERY_DDR_END_OFFSET 0x08 906 #define QUERY_DDR_INFO_OFFSET 0x13 907 908 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) 909 #define QUERY_DDR_INFO_ECC_MASK 0x3 910 911 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 912 if (IS_ERR(mailbox)) 913 return PTR_ERR(mailbox); 914 outbox = mailbox->buf; 915 916 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, 917 CMD_TIME_CLASS_A, status); 918 919 if (err) 920 goto out; 921 922 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); 923 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); 924 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); 925 926 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != 927 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 928 mthca_info(dev, "FW reports that HCA-attached memory " 929 "is %s hidden; does not match PCI config\n", 930 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? 931 "" : "not"); 932 } 933 if (info & QUERY_DDR_INFO_HIDDEN_FLAG) 934 mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 935 936 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 937 (int) ((dev->ddr_end - dev->ddr_start) >> 10), 938 (unsigned long long) dev->ddr_start, 939 (unsigned long long) dev->ddr_end); 940 941 out: 942 mthca_free_mailbox(dev, mailbox); 943 return err; 944 } 945 946 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, 947 struct mthca_dev_lim *dev_lim, u8 *status) 948 { 949 struct mthca_mailbox *mailbox; 950 u32 *outbox; 951 u8 field; 952 u16 size; 953 u16 stat_rate; 954 int err; 955 956 #define QUERY_DEV_LIM_OUT_SIZE 0x100 957 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 958 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 959 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 960 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 961 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 962 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 963 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 964 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 965 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 966 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a 967 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b 968 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d 969 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e 970 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f 971 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 972 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 973 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 974 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 975 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 976 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 977 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b 978 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f 979 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 980 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 981 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 982 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 983 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b 984 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c 985 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f 986 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 987 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 988 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 989 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b 990 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 991 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 992 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 993 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 994 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 995 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 996 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 997 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 998 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 999 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 1000 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 1001 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 1002 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 1003 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 1004 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 1005 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 1006 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a 1007 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c 1008 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e 1009 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 1010 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 1011 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 1012 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 1013 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 1014 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f 1015 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 1016 1017 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1018 if (IS_ERR(mailbox)) 1019 return PTR_ERR(mailbox); 1020 outbox = mailbox->buf; 1021 1022 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, 1023 CMD_TIME_CLASS_A, status); 1024 1025 if (err) 1026 goto out; 1027 1028 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); 1029 dev_lim->reserved_qps = 1 << (field & 0xf); 1030 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); 1031 dev_lim->max_qps = 1 << (field & 0x1f); 1032 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); 1033 dev_lim->reserved_srqs = 1 << (field >> 4); 1034 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); 1035 dev_lim->max_srqs = 1 << (field & 0x1f); 1036 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); 1037 dev_lim->reserved_eecs = 1 << (field & 0xf); 1038 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); 1039 dev_lim->max_eecs = 1 << (field & 0x1f); 1040 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); 1041 dev_lim->max_cq_sz = 1 << field; 1042 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); 1043 dev_lim->reserved_cqs = 1 << (field & 0xf); 1044 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); 1045 dev_lim->max_cqs = 1 << (field & 0x1f); 1046 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); 1047 dev_lim->max_mpts = 1 << (field & 0x3f); 1048 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); 1049 dev_lim->reserved_eqs = 1 << (field & 0xf); 1050 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); 1051 dev_lim->max_eqs = 1 << (field & 0x7); 1052 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); 1053 dev_lim->reserved_mtts = 1 << (field >> 4); 1054 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); 1055 dev_lim->max_mrw_sz = 1 << field; 1056 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); 1057 dev_lim->reserved_mrws = 1 << (field & 0xf); 1058 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); 1059 dev_lim->max_mtt_seg = 1 << (field & 0x3f); 1060 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); 1061 dev_lim->max_requester_per_qp = 1 << (field & 0x3f); 1062 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); 1063 dev_lim->max_responder_per_qp = 1 << (field & 0x3f); 1064 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); 1065 dev_lim->max_rdma_global = 1 << (field & 0x3f); 1066 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); 1067 dev_lim->local_ca_ack_delay = field & 0x1f; 1068 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); 1069 dev_lim->max_mtu = field >> 4; 1070 dev_lim->max_port_width = field & 0xf; 1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); 1072 dev_lim->max_vl = field >> 4; 1073 dev_lim->num_ports = field & 0xf; 1074 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); 1075 dev_lim->max_gids = 1 << (field & 0xf); 1076 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET); 1077 dev_lim->stat_rate_support = stat_rate; 1078 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); 1079 dev_lim->max_pkeys = 1 << (field & 0xf); 1080 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); 1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); 1082 dev_lim->reserved_uars = field >> 4; 1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); 1084 dev_lim->uar_size = 1 << ((field & 0x3f) + 20); 1085 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); 1086 dev_lim->min_page_sz = 1 << field; 1087 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); 1088 dev_lim->max_sg = field; 1089 1090 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); 1091 dev_lim->max_desc_sz = size; 1092 1093 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); 1094 dev_lim->max_qp_per_mcg = 1 << field; 1095 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); 1096 dev_lim->reserved_mgms = field & 0xf; 1097 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); 1098 dev_lim->max_mcgs = 1 << field; 1099 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); 1100 dev_lim->reserved_pds = field >> 4; 1101 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); 1102 dev_lim->max_pds = 1 << (field & 0x3f); 1103 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); 1104 dev_lim->reserved_rdds = field >> 4; 1105 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); 1106 dev_lim->max_rdds = 1 << (field & 0x3f); 1107 1108 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); 1109 dev_lim->eec_entry_sz = size; 1110 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); 1111 dev_lim->qpc_entry_sz = size; 1112 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); 1113 dev_lim->eeec_entry_sz = size; 1114 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); 1115 dev_lim->eqpc_entry_sz = size; 1116 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); 1117 dev_lim->eqc_entry_sz = size; 1118 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); 1119 dev_lim->cqc_entry_sz = size; 1120 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); 1121 dev_lim->srq_entry_sz = size; 1122 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); 1123 dev_lim->uar_scratch_entry_sz = size; 1124 1125 if (mthca_is_memfree(dev)) { 1126 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1127 dev_lim->max_srq_sz = 1 << field; 1128 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1129 dev_lim->max_qp_sz = 1 << field; 1130 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); 1131 dev_lim->hca.arbel.resize_srq = field & 1; 1132 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); 1133 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); 1134 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); 1135 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); 1136 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); 1137 dev_lim->mpt_entry_sz = size; 1138 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); 1139 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); 1140 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, 1141 QUERY_DEV_LIM_BMME_FLAGS_OFFSET); 1142 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, 1143 QUERY_DEV_LIM_RSVD_LKEY_OFFSET); 1144 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); 1145 dev_lim->hca.arbel.lam_required = field & 1; 1146 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, 1147 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); 1148 1149 if (dev_lim->hca.arbel.bmme_flags & 1) 1150 mthca_dbg(dev, "Base MM extensions: yes " 1151 "(flags %d, max PBL %d, rsvd L_Key %08x)\n", 1152 dev_lim->hca.arbel.bmme_flags, 1153 dev_lim->hca.arbel.max_pbl_sz, 1154 dev_lim->hca.arbel.reserved_lkey); 1155 else 1156 mthca_dbg(dev, "Base MM extensions: no\n"); 1157 1158 mthca_dbg(dev, "Max ICM size %lld MB\n", 1159 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); 1160 } else { 1161 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1162 dev_lim->max_srq_sz = (1 << field) - 1; 1163 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1164 dev_lim->max_qp_sz = (1 << field) - 1; 1165 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); 1166 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); 1167 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; 1168 } 1169 1170 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1171 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); 1172 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1173 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); 1174 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1175 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); 1176 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 1177 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); 1178 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1179 dev_lim->reserved_mrws, dev_lim->reserved_mtts); 1180 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1181 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); 1182 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1183 dev_lim->max_pds, dev_lim->reserved_mgms); 1184 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1185 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); 1186 1187 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); 1188 1189 out: 1190 mthca_free_mailbox(dev, mailbox); 1191 return err; 1192 } 1193 1194 static void get_board_id(void *vsd, char *board_id) 1195 { 1196 int i; 1197 1198 #define VSD_OFFSET_SIG1 0x00 1199 #define VSD_OFFSET_SIG2 0xde 1200 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1201 #define VSD_OFFSET_TS_BOARD_ID 0x20 1202 1203 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1204 1205 memset(board_id, 0, MTHCA_BOARD_ID_LEN); 1206 1207 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1208 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1209 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); 1210 } else { 1211 /* 1212 * The board ID is a string but the firmware byte 1213 * swaps each 4-byte word before passing it back to 1214 * us. Therefore we need to swab it before printing. 1215 */ 1216 for (i = 0; i < 4; ++i) 1217 ((u32 *) board_id)[i] = 1218 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1219 } 1220 } 1221 1222 int mthca_QUERY_ADAPTER(struct mthca_dev *dev, 1223 struct mthca_adapter *adapter, u8 *status) 1224 { 1225 struct mthca_mailbox *mailbox; 1226 u32 *outbox; 1227 int err; 1228 1229 #define QUERY_ADAPTER_OUT_SIZE 0x100 1230 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 1231 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 1232 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 1233 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1234 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1235 1236 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1237 if (IS_ERR(mailbox)) 1238 return PTR_ERR(mailbox); 1239 outbox = mailbox->buf; 1240 1241 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, 1242 CMD_TIME_CLASS_A, status); 1243 1244 if (err) 1245 goto out; 1246 1247 MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET); 1248 MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET); 1249 MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET); 1250 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1251 1252 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1253 adapter->board_id); 1254 1255 out: 1256 mthca_free_mailbox(dev, mailbox); 1257 return err; 1258 } 1259 1260 int mthca_INIT_HCA(struct mthca_dev *dev, 1261 struct mthca_init_hca_param *param, 1262 u8 *status) 1263 { 1264 struct mthca_mailbox *mailbox; 1265 __be32 *inbox; 1266 int err; 1267 1268 #define INIT_HCA_IN_SIZE 0x200 1269 #define INIT_HCA_FLAGS1_OFFSET 0x00c 1270 #define INIT_HCA_FLAGS2_OFFSET 0x014 1271 #define INIT_HCA_QPC_OFFSET 0x020 1272 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1273 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1274 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) 1275 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) 1276 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1277 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1278 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1279 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1280 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1281 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1282 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1283 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1284 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1285 #define INIT_HCA_UDAV_OFFSET 0x0b0 1286 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) 1287 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) 1288 #define INIT_HCA_MCAST_OFFSET 0x0c0 1289 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1290 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1291 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1292 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1293 #define INIT_HCA_TPT_OFFSET 0x0f0 1294 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1295 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) 1296 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1297 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1298 #define INIT_HCA_UAR_OFFSET 0x120 1299 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) 1300 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) 1301 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1302 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1303 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) 1304 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) 1305 1306 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1307 if (IS_ERR(mailbox)) 1308 return PTR_ERR(mailbox); 1309 inbox = mailbox->buf; 1310 1311 memset(inbox, 0, INIT_HCA_IN_SIZE); 1312 1313 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT) 1314 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); 1315 1316 #if defined(__LITTLE_ENDIAN) 1317 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1318 #elif defined(__BIG_ENDIAN) 1319 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1); 1320 #else 1321 #error Host endianness not defined 1322 #endif 1323 /* Check port for UD address vector: */ 1324 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1); 1325 1326 /* We leave wqe_quota, responder_exu, etc as 0 (default) */ 1327 1328 /* QPC/EEC/CQC/EQC/RDB attributes */ 1329 1330 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1331 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1332 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); 1333 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); 1334 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1335 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1336 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1337 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1338 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); 1339 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); 1340 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1341 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1342 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); 1343 1344 /* UD AV attributes */ 1345 1346 /* multicast attributes */ 1347 1348 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1349 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1350 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); 1351 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1352 1353 /* TPT attributes */ 1354 1355 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); 1356 if (!mthca_is_memfree(dev)) 1357 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); 1358 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1359 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1360 1361 /* UAR attributes */ 1362 { 1363 u8 uar_page_sz = PAGE_SHIFT - 12; 1364 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1365 } 1366 1367 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); 1368 1369 if (mthca_is_memfree(dev)) { 1370 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); 1371 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1372 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); 1373 } 1374 1375 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status); 1376 1377 mthca_free_mailbox(dev, mailbox); 1378 return err; 1379 } 1380 1381 int mthca_INIT_IB(struct mthca_dev *dev, 1382 struct mthca_init_ib_param *param, 1383 int port, u8 *status) 1384 { 1385 struct mthca_mailbox *mailbox; 1386 u32 *inbox; 1387 int err; 1388 u32 flags; 1389 1390 #define INIT_IB_IN_SIZE 56 1391 #define INIT_IB_FLAGS_OFFSET 0x00 1392 #define INIT_IB_FLAG_SIG (1 << 18) 1393 #define INIT_IB_FLAG_NG (1 << 17) 1394 #define INIT_IB_FLAG_G0 (1 << 16) 1395 #define INIT_IB_VL_SHIFT 4 1396 #define INIT_IB_PORT_WIDTH_SHIFT 8 1397 #define INIT_IB_MTU_SHIFT 12 1398 #define INIT_IB_MAX_GID_OFFSET 0x06 1399 #define INIT_IB_MAX_PKEY_OFFSET 0x0a 1400 #define INIT_IB_GUID0_OFFSET 0x10 1401 #define INIT_IB_NODE_GUID_OFFSET 0x18 1402 #define INIT_IB_SI_GUID_OFFSET 0x20 1403 1404 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1405 if (IS_ERR(mailbox)) 1406 return PTR_ERR(mailbox); 1407 inbox = mailbox->buf; 1408 1409 memset(inbox, 0, INIT_IB_IN_SIZE); 1410 1411 flags = 0; 1412 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; 1413 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; 1414 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; 1415 flags |= param->vl_cap << INIT_IB_VL_SHIFT; 1416 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; 1417 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; 1418 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); 1419 1420 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); 1421 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); 1422 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); 1423 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); 1424 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); 1425 1426 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, 1427 CMD_TIME_CLASS_A, status); 1428 1429 mthca_free_mailbox(dev, mailbox); 1430 return err; 1431 } 1432 1433 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) 1434 { 1435 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status); 1436 } 1437 1438 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) 1439 { 1440 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status); 1441 } 1442 1443 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, 1444 int port, u8 *status) 1445 { 1446 struct mthca_mailbox *mailbox; 1447 u32 *inbox; 1448 int err; 1449 u32 flags = 0; 1450 1451 #define SET_IB_IN_SIZE 0x40 1452 #define SET_IB_FLAGS_OFFSET 0x00 1453 #define SET_IB_FLAG_SIG (1 << 18) 1454 #define SET_IB_FLAG_RQK (1 << 0) 1455 #define SET_IB_CAP_MASK_OFFSET 0x04 1456 #define SET_IB_SI_GUID_OFFSET 0x08 1457 1458 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1459 if (IS_ERR(mailbox)) 1460 return PTR_ERR(mailbox); 1461 inbox = mailbox->buf; 1462 1463 memset(inbox, 0, SET_IB_IN_SIZE); 1464 1465 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; 1466 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; 1467 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); 1468 1469 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); 1470 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); 1471 1472 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, 1473 CMD_TIME_CLASS_B, status); 1474 1475 mthca_free_mailbox(dev, mailbox); 1476 return err; 1477 } 1478 1479 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status) 1480 { 1481 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status); 1482 } 1483 1484 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status) 1485 { 1486 struct mthca_mailbox *mailbox; 1487 __be64 *inbox; 1488 int err; 1489 1490 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1491 if (IS_ERR(mailbox)) 1492 return PTR_ERR(mailbox); 1493 inbox = mailbox->buf; 1494 1495 inbox[0] = cpu_to_be64(virt); 1496 inbox[1] = cpu_to_be64(dma_addr); 1497 1498 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, 1499 CMD_TIME_CLASS_B, status); 1500 1501 mthca_free_mailbox(dev, mailbox); 1502 1503 if (!err) 1504 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", 1505 (unsigned long long) dma_addr, (unsigned long long) virt); 1506 1507 return err; 1508 } 1509 1510 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status) 1511 { 1512 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", 1513 page_count, (unsigned long long) virt); 1514 1515 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status); 1516 } 1517 1518 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 1519 { 1520 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status); 1521 } 1522 1523 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status) 1524 { 1525 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status); 1526 } 1527 1528 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, 1529 u8 *status) 1530 { 1531 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE, 1532 CMD_TIME_CLASS_A, status); 1533 1534 if (ret || status) 1535 return ret; 1536 1537 /* 1538 * Round up number of system pages needed in case 1539 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 1540 */ 1541 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 1542 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 1543 1544 return 0; 1545 } 1546 1547 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1548 int mpt_index, u8 *status) 1549 { 1550 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, 1551 CMD_TIME_CLASS_B, status); 1552 } 1553 1554 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1555 int mpt_index, u8 *status) 1556 { 1557 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, 1558 !mailbox, CMD_HW2SW_MPT, 1559 CMD_TIME_CLASS_B, status); 1560 } 1561 1562 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1563 int num_mtt, u8 *status) 1564 { 1565 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, 1566 CMD_TIME_CLASS_B, status); 1567 } 1568 1569 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status) 1570 { 1571 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status); 1572 } 1573 1574 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, 1575 int eq_num, u8 *status) 1576 { 1577 mthca_dbg(dev, "%s mask %016llx for eqn %d\n", 1578 unmap ? "Clearing" : "Setting", 1579 (unsigned long long) event_mask, eq_num); 1580 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, 1581 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status); 1582 } 1583 1584 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1585 int eq_num, u8 *status) 1586 { 1587 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, 1588 CMD_TIME_CLASS_A, status); 1589 } 1590 1591 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1592 int eq_num, u8 *status) 1593 { 1594 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, 1595 CMD_HW2SW_EQ, 1596 CMD_TIME_CLASS_A, status); 1597 } 1598 1599 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1600 int cq_num, u8 *status) 1601 { 1602 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, 1603 CMD_TIME_CLASS_A, status); 1604 } 1605 1606 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1607 int cq_num, u8 *status) 1608 { 1609 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, 1610 CMD_HW2SW_CQ, 1611 CMD_TIME_CLASS_A, status); 1612 } 1613 1614 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size, 1615 u8 *status) 1616 { 1617 struct mthca_mailbox *mailbox; 1618 __be32 *inbox; 1619 int err; 1620 1621 #define RESIZE_CQ_IN_SIZE 0x40 1622 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c 1623 #define RESIZE_CQ_LKEY_OFFSET 0x1c 1624 1625 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1626 if (IS_ERR(mailbox)) 1627 return PTR_ERR(mailbox); 1628 inbox = mailbox->buf; 1629 1630 memset(inbox, 0, RESIZE_CQ_IN_SIZE); 1631 /* 1632 * Leave start address fields zeroed out -- mthca assumes that 1633 * MRs for CQs always start at virtual address 0. 1634 */ 1635 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); 1636 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); 1637 1638 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, 1639 CMD_TIME_CLASS_B, status); 1640 1641 mthca_free_mailbox(dev, mailbox); 1642 return err; 1643 } 1644 1645 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1646 int srq_num, u8 *status) 1647 { 1648 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, 1649 CMD_TIME_CLASS_A, status); 1650 } 1651 1652 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1653 int srq_num, u8 *status) 1654 { 1655 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, 1656 CMD_HW2SW_SRQ, 1657 CMD_TIME_CLASS_A, status); 1658 } 1659 1660 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, 1661 struct mthca_mailbox *mailbox, u8 *status) 1662 { 1663 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, 1664 CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status); 1665 } 1666 1667 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status) 1668 { 1669 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, 1670 CMD_TIME_CLASS_B, status); 1671 } 1672 1673 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, 1674 enum ib_qp_state next, u32 num, int is_ee, 1675 struct mthca_mailbox *mailbox, u32 optmask, 1676 u8 *status) 1677 { 1678 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { 1679 [IB_QPS_RESET] = { 1680 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1681 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1682 [IB_QPS_INIT] = CMD_RST2INIT_QPEE, 1683 }, 1684 [IB_QPS_INIT] = { 1685 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1686 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1687 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, 1688 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, 1689 }, 1690 [IB_QPS_RTR] = { 1691 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1692 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1693 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, 1694 }, 1695 [IB_QPS_RTS] = { 1696 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1697 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1698 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, 1699 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, 1700 }, 1701 [IB_QPS_SQD] = { 1702 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1703 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1704 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, 1705 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, 1706 }, 1707 [IB_QPS_SQE] = { 1708 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1709 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1710 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, 1711 }, 1712 [IB_QPS_ERR] = { 1713 [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1714 [IB_QPS_ERR] = CMD_2ERR_QPEE, 1715 } 1716 }; 1717 1718 u8 op_mod = 0; 1719 int my_mailbox = 0; 1720 int err; 1721 1722 if (op[cur][next] == CMD_ERR2RST_QPEE) { 1723 op_mod = 3; /* don't write outbox, any->reset */ 1724 1725 /* For debugging */ 1726 if (!mailbox) { 1727 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1728 if (!IS_ERR(mailbox)) { 1729 my_mailbox = 1; 1730 op_mod = 2; /* write outbox, any->reset */ 1731 } else 1732 mailbox = NULL; 1733 } 1734 1735 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, 1736 (!!is_ee << 24) | num, op_mod, 1737 op[cur][next], CMD_TIME_CLASS_C, status); 1738 1739 if (0 && mailbox) { 1740 int i; 1741 mthca_dbg(dev, "Dumping QP context:\n"); 1742 printk(" %08x\n", be32_to_cpup(mailbox->buf)); 1743 for (i = 0; i < 0x100 / 4; ++i) { 1744 if (i % 8 == 0) 1745 printk("[%02x] ", i * 4); 1746 printk(" %08x", 1747 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1748 if ((i + 1) % 8 == 0) 1749 printk("\n"); 1750 } 1751 } 1752 1753 if (my_mailbox) 1754 mthca_free_mailbox(dev, mailbox); 1755 } else { 1756 if (0) { 1757 int i; 1758 mthca_dbg(dev, "Dumping QP context:\n"); 1759 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); 1760 for (i = 0; i < 0x100 / 4; ++i) { 1761 if (i % 8 == 0) 1762 printk(" [%02x] ", i * 4); 1763 printk(" %08x", 1764 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1765 if ((i + 1) % 8 == 0) 1766 printk("\n"); 1767 } 1768 } 1769 1770 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num, 1771 op_mod, op[cur][next], CMD_TIME_CLASS_C, status); 1772 } 1773 1774 return err; 1775 } 1776 1777 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, 1778 struct mthca_mailbox *mailbox, u8 *status) 1779 { 1780 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, 1781 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status); 1782 } 1783 1784 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, 1785 u8 *status) 1786 { 1787 u8 op_mod; 1788 1789 switch (type) { 1790 case IB_QPT_SMI: 1791 op_mod = 0; 1792 break; 1793 case IB_QPT_GSI: 1794 op_mod = 1; 1795 break; 1796 case IB_QPT_RAW_IPV6: 1797 op_mod = 2; 1798 break; 1799 case IB_QPT_RAW_ETY: 1800 op_mod = 3; 1801 break; 1802 default: 1803 return -EINVAL; 1804 } 1805 1806 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, 1807 CMD_TIME_CLASS_B, status); 1808 } 1809 1810 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, 1811 int port, struct ib_wc *in_wc, struct ib_grh *in_grh, 1812 void *in_mad, void *response_mad, u8 *status) 1813 { 1814 struct mthca_mailbox *inmailbox, *outmailbox; 1815 void *inbox; 1816 int err; 1817 u32 in_modifier = port; 1818 u8 op_modifier = 0; 1819 1820 #define MAD_IFC_BOX_SIZE 0x400 1821 #define MAD_IFC_MY_QPN_OFFSET 0x100 1822 #define MAD_IFC_RQPN_OFFSET 0x104 1823 #define MAD_IFC_SL_OFFSET 0x108 1824 #define MAD_IFC_G_PATH_OFFSET 0x109 1825 #define MAD_IFC_RLID_OFFSET 0x10a 1826 #define MAD_IFC_PKEY_OFFSET 0x10e 1827 #define MAD_IFC_GRH_OFFSET 0x140 1828 1829 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1830 if (IS_ERR(inmailbox)) 1831 return PTR_ERR(inmailbox); 1832 inbox = inmailbox->buf; 1833 1834 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1835 if (IS_ERR(outmailbox)) { 1836 mthca_free_mailbox(dev, inmailbox); 1837 return PTR_ERR(outmailbox); 1838 } 1839 1840 memcpy(inbox, in_mad, 256); 1841 1842 /* 1843 * Key check traps can't be generated unless we have in_wc to 1844 * tell us where to send the trap. 1845 */ 1846 if (ignore_mkey || !in_wc) 1847 op_modifier |= 0x1; 1848 if (ignore_bkey || !in_wc) 1849 op_modifier |= 0x2; 1850 1851 if (in_wc) { 1852 u8 val; 1853 1854 memset(inbox + 256, 0, 256); 1855 1856 MTHCA_PUT(inbox, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET); 1857 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); 1858 1859 val = in_wc->sl << 4; 1860 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); 1861 1862 val = in_wc->dlid_path_bits | 1863 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 1864 MTHCA_PUT(inbox, val, MAD_IFC_GRH_OFFSET); 1865 1866 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); 1867 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); 1868 1869 if (in_grh) 1870 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); 1871 1872 op_modifier |= 0x10; 1873 1874 in_modifier |= in_wc->slid << 16; 1875 } 1876 1877 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, 1878 in_modifier, op_modifier, 1879 CMD_MAD_IFC, CMD_TIME_CLASS_C, status); 1880 1881 if (!err && !*status) 1882 memcpy(response_mad, outmailbox->buf, 256); 1883 1884 mthca_free_mailbox(dev, inmailbox); 1885 mthca_free_mailbox(dev, outmailbox); 1886 return err; 1887 } 1888 1889 int mthca_READ_MGM(struct mthca_dev *dev, int index, 1890 struct mthca_mailbox *mailbox, u8 *status) 1891 { 1892 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, 1893 CMD_READ_MGM, CMD_TIME_CLASS_A, status); 1894 } 1895 1896 int mthca_WRITE_MGM(struct mthca_dev *dev, int index, 1897 struct mthca_mailbox *mailbox, u8 *status) 1898 { 1899 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, 1900 CMD_TIME_CLASS_A, status); 1901 } 1902 1903 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1904 u16 *hash, u8 *status) 1905 { 1906 u64 imm; 1907 int err; 1908 1909 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, 1910 CMD_TIME_CLASS_A, status); 1911 1912 *hash = imm; 1913 return err; 1914 } 1915 1916 int mthca_NOP(struct mthca_dev *dev, u8 *status) 1917 { 1918 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status); 1919 } 1920