1 /* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 * $Id: mthca_av.c 1349 2004-12-16 21:09:43Z roland $ 34 */ 35 36 #include <linux/init.h> 37 #include <linux/string.h> 38 #include <linux/slab.h> 39 40 #include <rdma/ib_verbs.h> 41 #include <rdma/ib_cache.h> 42 43 #include "mthca_dev.h" 44 45 enum { 46 MTHCA_RATE_TAVOR_FULL = 0, 47 MTHCA_RATE_TAVOR_1X = 1, 48 MTHCA_RATE_TAVOR_4X = 2, 49 MTHCA_RATE_TAVOR_1X_DDR = 3 50 }; 51 52 enum { 53 MTHCA_RATE_MEMFREE_FULL = 0, 54 MTHCA_RATE_MEMFREE_QUARTER = 1, 55 MTHCA_RATE_MEMFREE_EIGHTH = 2, 56 MTHCA_RATE_MEMFREE_HALF = 3 57 }; 58 59 struct mthca_av { 60 __be32 port_pd; 61 u8 reserved1; 62 u8 g_slid; 63 __be16 dlid; 64 u8 reserved2; 65 u8 gid_index; 66 u8 msg_sr; 67 u8 hop_limit; 68 __be32 sl_tclass_flowlabel; 69 __be32 dgid[4]; 70 }; 71 72 static enum ib_rate memfree_rate_to_ib(u8 mthca_rate, u8 port_rate) 73 { 74 switch (mthca_rate) { 75 case MTHCA_RATE_MEMFREE_EIGHTH: 76 return mult_to_ib_rate(port_rate >> 3); 77 case MTHCA_RATE_MEMFREE_QUARTER: 78 return mult_to_ib_rate(port_rate >> 2); 79 case MTHCA_RATE_MEMFREE_HALF: 80 return mult_to_ib_rate(port_rate >> 1); 81 case MTHCA_RATE_MEMFREE_FULL: 82 default: 83 return mult_to_ib_rate(port_rate); 84 } 85 } 86 87 static enum ib_rate tavor_rate_to_ib(u8 mthca_rate, u8 port_rate) 88 { 89 switch (mthca_rate) { 90 case MTHCA_RATE_TAVOR_1X: return IB_RATE_2_5_GBPS; 91 case MTHCA_RATE_TAVOR_1X_DDR: return IB_RATE_5_GBPS; 92 case MTHCA_RATE_TAVOR_4X: return IB_RATE_10_GBPS; 93 default: return port_rate; 94 } 95 } 96 97 enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port) 98 { 99 if (mthca_is_memfree(dev)) { 100 /* Handle old Arbel FW */ 101 if (dev->limits.stat_rate_support == 0x3 && mthca_rate) 102 return IB_RATE_2_5_GBPS; 103 104 return memfree_rate_to_ib(mthca_rate, dev->rate[port - 1]); 105 } else 106 return tavor_rate_to_ib(mthca_rate, dev->rate[port - 1]); 107 } 108 109 static u8 ib_rate_to_memfree(u8 req_rate, u8 cur_rate) 110 { 111 if (cur_rate <= req_rate) 112 return 0; 113 114 /* 115 * Inter-packet delay (IPD) to get from rate X down to a rate 116 * no more than Y is (X - 1) / Y. 117 */ 118 switch ((cur_rate - 1) / req_rate) { 119 case 0: return MTHCA_RATE_MEMFREE_FULL; 120 case 1: return MTHCA_RATE_MEMFREE_HALF; 121 case 2: /* fall through */ 122 case 3: return MTHCA_RATE_MEMFREE_QUARTER; 123 default: return MTHCA_RATE_MEMFREE_EIGHTH; 124 } 125 } 126 127 static u8 ib_rate_to_tavor(u8 static_rate) 128 { 129 switch (static_rate) { 130 case IB_RATE_2_5_GBPS: return MTHCA_RATE_TAVOR_1X; 131 case IB_RATE_5_GBPS: return MTHCA_RATE_TAVOR_1X_DDR; 132 case IB_RATE_10_GBPS: return MTHCA_RATE_TAVOR_4X; 133 default: return MTHCA_RATE_TAVOR_FULL; 134 } 135 } 136 137 u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port) 138 { 139 u8 rate; 140 141 if (!static_rate || ib_rate_to_mult(static_rate) >= dev->rate[port - 1]) 142 return 0; 143 144 if (mthca_is_memfree(dev)) 145 rate = ib_rate_to_memfree(ib_rate_to_mult(static_rate), 146 dev->rate[port - 1]); 147 else 148 rate = ib_rate_to_tavor(static_rate); 149 150 if (!(dev->limits.stat_rate_support & (1 << rate))) 151 rate = 1; 152 153 return rate; 154 } 155 156 int mthca_create_ah(struct mthca_dev *dev, 157 struct mthca_pd *pd, 158 struct ib_ah_attr *ah_attr, 159 struct mthca_ah *ah) 160 { 161 u32 index = -1; 162 struct mthca_av *av = NULL; 163 164 ah->type = MTHCA_AH_PCI_POOL; 165 166 if (mthca_is_memfree(dev)) { 167 ah->av = kmalloc(sizeof *ah->av, GFP_ATOMIC); 168 if (!ah->av) 169 return -ENOMEM; 170 171 ah->type = MTHCA_AH_KMALLOC; 172 av = ah->av; 173 } else if (!atomic_read(&pd->sqp_count) && 174 !(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 175 index = mthca_alloc(&dev->av_table.alloc); 176 177 /* fall back to allocate in host memory */ 178 if (index == -1) 179 goto on_hca_fail; 180 181 av = kmalloc(sizeof *av, GFP_ATOMIC); 182 if (!av) 183 goto on_hca_fail; 184 185 ah->type = MTHCA_AH_ON_HCA; 186 ah->avdma = dev->av_table.ddr_av_base + 187 index * MTHCA_AV_SIZE; 188 } 189 190 on_hca_fail: 191 if (ah->type == MTHCA_AH_PCI_POOL) { 192 ah->av = pci_pool_alloc(dev->av_table.pool, 193 SLAB_ATOMIC, &ah->avdma); 194 if (!ah->av) 195 return -ENOMEM; 196 197 av = ah->av; 198 } 199 200 ah->key = pd->ntmr.ibmr.lkey; 201 202 memset(av, 0, MTHCA_AV_SIZE); 203 204 av->port_pd = cpu_to_be32(pd->pd_num | (ah_attr->port_num << 24)); 205 av->g_slid = ah_attr->src_path_bits; 206 av->dlid = cpu_to_be16(ah_attr->dlid); 207 av->msg_sr = (3 << 4) | /* 2K message */ 208 mthca_get_rate(dev, ah_attr->static_rate, ah_attr->port_num); 209 av->sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28); 210 if (ah_attr->ah_flags & IB_AH_GRH) { 211 av->g_slid |= 0x80; 212 av->gid_index = (ah_attr->port_num - 1) * dev->limits.gid_table_len + 213 ah_attr->grh.sgid_index; 214 av->hop_limit = ah_attr->grh.hop_limit; 215 av->sl_tclass_flowlabel |= 216 cpu_to_be32((ah_attr->grh.traffic_class << 20) | 217 ah_attr->grh.flow_label); 218 memcpy(av->dgid, ah_attr->grh.dgid.raw, 16); 219 } else { 220 /* Arbel workaround -- low byte of GID must be 2 */ 221 av->dgid[3] = cpu_to_be32(2); 222 } 223 224 if (0) { 225 int j; 226 227 mthca_dbg(dev, "Created UDAV at %p/%08lx:\n", 228 av, (unsigned long) ah->avdma); 229 for (j = 0; j < 8; ++j) 230 printk(KERN_DEBUG " [%2x] %08x\n", 231 j * 4, be32_to_cpu(((__be32 *) av)[j])); 232 } 233 234 if (ah->type == MTHCA_AH_ON_HCA) { 235 memcpy_toio(dev->av_table.av_map + index * MTHCA_AV_SIZE, 236 av, MTHCA_AV_SIZE); 237 kfree(av); 238 } 239 240 return 0; 241 } 242 243 int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah) 244 { 245 switch (ah->type) { 246 case MTHCA_AH_ON_HCA: 247 mthca_free(&dev->av_table.alloc, 248 (ah->avdma - dev->av_table.ddr_av_base) / 249 MTHCA_AV_SIZE); 250 break; 251 252 case MTHCA_AH_PCI_POOL: 253 pci_pool_free(dev->av_table.pool, ah->av, ah->avdma); 254 break; 255 256 case MTHCA_AH_KMALLOC: 257 kfree(ah->av); 258 break; 259 } 260 261 return 0; 262 } 263 264 int mthca_ah_grh_present(struct mthca_ah *ah) 265 { 266 return !!(ah->av->g_slid & 0x80); 267 } 268 269 int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah, 270 struct ib_ud_header *header) 271 { 272 if (ah->type == MTHCA_AH_ON_HCA) 273 return -EINVAL; 274 275 header->lrh.service_level = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28; 276 header->lrh.destination_lid = ah->av->dlid; 277 header->lrh.source_lid = cpu_to_be16(ah->av->g_slid & 0x7f); 278 if (mthca_ah_grh_present(ah)) { 279 header->grh.traffic_class = 280 (be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20) & 0xff; 281 header->grh.flow_label = 282 ah->av->sl_tclass_flowlabel & cpu_to_be32(0xfffff); 283 ib_get_cached_gid(&dev->ib_dev, 284 be32_to_cpu(ah->av->port_pd) >> 24, 285 ah->av->gid_index % dev->limits.gid_table_len, 286 &header->grh.source_gid); 287 memcpy(header->grh.destination_gid.raw, 288 ah->av->dgid, 16); 289 } 290 291 return 0; 292 } 293 294 int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr) 295 { 296 struct mthca_ah *ah = to_mah(ibah); 297 struct mthca_dev *dev = to_mdev(ibah->device); 298 299 /* Only implement for MAD and memfree ah for now. */ 300 if (ah->type == MTHCA_AH_ON_HCA) 301 return -ENOSYS; 302 303 memset(attr, 0, sizeof *attr); 304 attr->dlid = be16_to_cpu(ah->av->dlid); 305 attr->sl = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28; 306 attr->static_rate = ah->av->msg_sr & 0x7; 307 attr->src_path_bits = ah->av->g_slid & 0x7F; 308 attr->port_num = be32_to_cpu(ah->av->port_pd) >> 24; 309 attr->ah_flags = mthca_ah_grh_present(ah) ? IB_AH_GRH : 0; 310 311 if (attr->ah_flags) { 312 attr->grh.traffic_class = 313 be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20; 314 attr->grh.flow_label = 315 be32_to_cpu(ah->av->sl_tclass_flowlabel) & 0xfffff; 316 attr->grh.hop_limit = ah->av->hop_limit; 317 attr->grh.sgid_index = ah->av->gid_index & 318 (dev->limits.gid_table_len - 1); 319 memcpy(attr->grh.dgid.raw, ah->av->dgid, 16); 320 } 321 322 return 0; 323 } 324 325 int __devinit mthca_init_av_table(struct mthca_dev *dev) 326 { 327 int err; 328 329 if (mthca_is_memfree(dev)) 330 return 0; 331 332 err = mthca_alloc_init(&dev->av_table.alloc, 333 dev->av_table.num_ddr_avs, 334 dev->av_table.num_ddr_avs - 1, 335 0); 336 if (err) 337 return err; 338 339 dev->av_table.pool = pci_pool_create("mthca_av", dev->pdev, 340 MTHCA_AV_SIZE, 341 MTHCA_AV_SIZE, 0); 342 if (!dev->av_table.pool) 343 goto out_free_alloc; 344 345 if (!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 346 dev->av_table.av_map = ioremap(pci_resource_start(dev->pdev, 4) + 347 dev->av_table.ddr_av_base - 348 dev->ddr_start, 349 dev->av_table.num_ddr_avs * 350 MTHCA_AV_SIZE); 351 if (!dev->av_table.av_map) 352 goto out_free_pool; 353 } else 354 dev->av_table.av_map = NULL; 355 356 return 0; 357 358 out_free_pool: 359 pci_pool_destroy(dev->av_table.pool); 360 361 out_free_alloc: 362 mthca_alloc_cleanup(&dev->av_table.alloc); 363 return -ENOMEM; 364 } 365 366 void mthca_cleanup_av_table(struct mthca_dev *dev) 367 { 368 if (mthca_is_memfree(dev)) 369 return; 370 371 if (dev->av_table.av_map) 372 iounmap(dev->av_table.av_map); 373 pci_pool_destroy(dev->av_table.pool); 374 mthca_alloc_cleanup(&dev->av_table.alloc); 375 } 376