1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */ 3 4 #ifndef _MLX5_IB_UMR_H 5 #define _MLX5_IB_UMR_H 6 7 #include "mlx5_ib.h" 8 9 10 #define MLX5_MAX_UMR_SHIFT 16 11 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 12 #define MLX5_MAX_UMR_EXTENDED_SHIFT 43 13 14 #define MLX5_IB_UMR_OCTOWORD 16 15 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 16 17 int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev); 18 void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev); 19 20 int mlx5r_umr_init(struct mlx5_ib_dev *dev); 21 void mlx5r_umr_cleanup(struct mlx5_ib_dev *dev); 22 23 static inline bool mlx5r_umr_can_load_pas(struct mlx5_ib_dev *dev, 24 size_t length) 25 { 26 /* 27 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is 28 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka 29 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey 30 * can never be enabled without this capability. Simplify this weird 31 * quirky hardware by just saying it can't use PAS lists with UMR at 32 * all. 33 */ 34 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 35 return false; 36 37 /* 38 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is 39 * used. 40 */ 41 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 42 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE) 43 return false; 44 return true; 45 } 46 47 /* 48 * true if an existing MR can be reconfigured to new access_flags using UMR. 49 * Older HW cannot use UMR to update certain elements of the MKC. See 50 * get_umr_update_access_mask() and umr_check_mkey_mask() 51 */ 52 static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev, 53 unsigned int current_access_flags, 54 unsigned int target_access_flags) 55 { 56 unsigned int diffs = current_access_flags ^ target_access_flags; 57 58 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) && 59 MLX5_CAP_GEN(dev->mdev, atomic) && 60 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 61 return false; 62 63 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 64 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 65 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 66 return false; 67 68 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 69 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || 70 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) && 71 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 72 return false; 73 74 return true; 75 } 76 77 static inline u64 mlx5r_umr_get_xlt_octo(u64 bytes) 78 { 79 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 80 MLX5_IB_UMR_OCTOWORD; 81 } 82 83 struct mlx5r_umr_context { 84 struct ib_cqe cqe; 85 enum ib_wc_status status; 86 struct completion done; 87 }; 88 89 struct mlx5r_umr_wqe { 90 struct mlx5_wqe_umr_ctrl_seg ctrl_seg; 91 struct mlx5_mkey_seg mkey_seg; 92 struct mlx5_wqe_data_seg data_seg; 93 }; 94 95 int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr); 96 int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd, 97 int access_flags); 98 int mlx5r_umr_update_data_direct_ksm_pas_range(struct mlx5_ib_mr *mr, 99 unsigned int flags, 100 size_t start_block, 101 size_t nblocks); 102 int mlx5r_umr_update_data_direct_ksm_pas(struct mlx5_ib_mr *mr, unsigned int flags); 103 int mlx5r_umr_update_mr_pas_range(struct mlx5_ib_mr *mr, unsigned int flags, 104 size_t start_block, size_t nblocks); 105 int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags); 106 int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 107 int page_shift, int flags); 108 int mlx5r_umr_update_mr_page_shift(struct mlx5_ib_mr *mr, 109 unsigned int page_shift, 110 bool dd); 111 int mlx5r_umr_dmabuf_update_pgsz(struct mlx5_ib_mr *mr, u32 xlt_flags, 112 unsigned int page_shift); 113 114 #endif /* _MLX5_IB_UMR_H */ 115