1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */ 3 4 #include <rdma/ib_umem_odp.h> 5 #include "mlx5_ib.h" 6 #include "umr.h" 7 #include "wr.h" 8 9 /* 10 * We can't use an array for xlt_emergency_page because dma_map_single doesn't 11 * work on kernel modules memory 12 */ 13 void *xlt_emergency_page; 14 static DEFINE_MUTEX(xlt_emergency_page_mutex); 15 16 static __be64 get_umr_enable_mr_mask(void) 17 { 18 u64 result; 19 20 result = MLX5_MKEY_MASK_KEY | 21 MLX5_MKEY_MASK_FREE; 22 23 return cpu_to_be64(result); 24 } 25 26 static __be64 get_umr_disable_mr_mask(void) 27 { 28 u64 result; 29 30 result = MLX5_MKEY_MASK_FREE; 31 32 return cpu_to_be64(result); 33 } 34 35 static __be64 get_umr_update_translation_mask(void) 36 { 37 u64 result; 38 39 result = MLX5_MKEY_MASK_LEN | 40 MLX5_MKEY_MASK_PAGE_SIZE | 41 MLX5_MKEY_MASK_START_ADDR; 42 43 return cpu_to_be64(result); 44 } 45 46 static __be64 get_umr_update_access_mask(struct mlx5_ib_dev *dev) 47 { 48 u64 result; 49 50 result = MLX5_MKEY_MASK_LR | 51 MLX5_MKEY_MASK_LW | 52 MLX5_MKEY_MASK_RR | 53 MLX5_MKEY_MASK_RW; 54 55 if (MLX5_CAP_GEN(dev->mdev, atomic)) 56 result |= MLX5_MKEY_MASK_A; 57 58 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 59 result |= MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE; 60 61 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 62 result |= MLX5_MKEY_MASK_RELAXED_ORDERING_READ; 63 64 return cpu_to_be64(result); 65 } 66 67 static __be64 get_umr_update_pd_mask(void) 68 { 69 u64 result; 70 71 result = MLX5_MKEY_MASK_PD; 72 73 return cpu_to_be64(result); 74 } 75 76 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) 77 { 78 if (mask & MLX5_MKEY_MASK_PAGE_SIZE && 79 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 80 return -EPERM; 81 82 if (mask & MLX5_MKEY_MASK_A && 83 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 84 return -EPERM; 85 86 if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE && 87 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 88 return -EPERM; 89 90 if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_READ && 91 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 92 return -EPERM; 93 94 return 0; 95 } 96 97 enum { 98 MAX_UMR_WR = 128, 99 }; 100 101 static int mlx5r_umr_qp_rst2rts(struct mlx5_ib_dev *dev, struct ib_qp *qp) 102 { 103 struct ib_qp_attr attr = {}; 104 int ret; 105 106 attr.qp_state = IB_QPS_INIT; 107 attr.port_num = 1; 108 ret = ib_modify_qp(qp, &attr, 109 IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT); 110 if (ret) { 111 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 112 return ret; 113 } 114 115 memset(&attr, 0, sizeof(attr)); 116 attr.qp_state = IB_QPS_RTR; 117 118 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 119 if (ret) { 120 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 121 return ret; 122 } 123 124 memset(&attr, 0, sizeof(attr)); 125 attr.qp_state = IB_QPS_RTS; 126 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 127 if (ret) { 128 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 129 return ret; 130 } 131 132 return 0; 133 } 134 135 int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev) 136 { 137 struct ib_qp_init_attr init_attr = {}; 138 struct ib_cq *cq; 139 struct ib_qp *qp; 140 int ret = 0; 141 142 143 /* 144 * UMR qp is set once, never changed until device unload. 145 * Avoid taking the mutex if initialization is already done. 146 */ 147 if (dev->umrc.qp) 148 return 0; 149 150 mutex_lock(&dev->umrc.init_lock); 151 /* First user allocates the UMR resources. Skip if already allocated. */ 152 if (dev->umrc.qp) 153 goto unlock; 154 155 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 156 if (IS_ERR(cq)) { 157 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 158 ret = PTR_ERR(cq); 159 goto unlock; 160 } 161 162 init_attr.send_cq = cq; 163 init_attr.recv_cq = cq; 164 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 165 init_attr.cap.max_send_wr = MAX_UMR_WR; 166 init_attr.cap.max_send_sge = 1; 167 init_attr.qp_type = MLX5_IB_QPT_REG_UMR; 168 init_attr.port_num = 1; 169 qp = ib_create_qp(dev->umrc.pd, &init_attr); 170 if (IS_ERR(qp)) { 171 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 172 ret = PTR_ERR(qp); 173 goto destroy_cq; 174 } 175 176 ret = mlx5r_umr_qp_rst2rts(dev, qp); 177 if (ret) 178 goto destroy_qp; 179 180 dev->umrc.cq = cq; 181 182 sema_init(&dev->umrc.sem, MAX_UMR_WR); 183 mutex_init(&dev->umrc.lock); 184 dev->umrc.state = MLX5_UMR_STATE_ACTIVE; 185 dev->umrc.qp = qp; 186 187 mutex_unlock(&dev->umrc.init_lock); 188 return 0; 189 190 destroy_qp: 191 ib_destroy_qp(qp); 192 destroy_cq: 193 ib_free_cq(cq); 194 unlock: 195 mutex_unlock(&dev->umrc.init_lock); 196 return ret; 197 } 198 199 void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev) 200 { 201 if (dev->umrc.state == MLX5_UMR_STATE_UNINIT) 202 return; 203 mutex_destroy(&dev->umrc.lock); 204 /* After device init, UMR cp/qp are not unset during the lifetime. */ 205 ib_destroy_qp(dev->umrc.qp); 206 ib_free_cq(dev->umrc.cq); 207 } 208 209 int mlx5r_umr_init(struct mlx5_ib_dev *dev) 210 { 211 struct ib_pd *pd; 212 213 pd = ib_alloc_pd(&dev->ib_dev, 0); 214 if (IS_ERR(pd)) { 215 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 216 return PTR_ERR(pd); 217 } 218 dev->umrc.pd = pd; 219 220 mutex_init(&dev->umrc.init_lock); 221 222 return 0; 223 } 224 225 void mlx5r_umr_cleanup(struct mlx5_ib_dev *dev) 226 { 227 mutex_destroy(&dev->umrc.init_lock); 228 ib_dealloc_pd(dev->umrc.pd); 229 } 230 231 static int mlx5r_umr_recover(struct mlx5_ib_dev *dev) 232 { 233 struct umr_common *umrc = &dev->umrc; 234 struct ib_qp_attr attr; 235 int err; 236 237 attr.qp_state = IB_QPS_RESET; 238 err = ib_modify_qp(umrc->qp, &attr, IB_QP_STATE); 239 if (err) { 240 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 241 goto err; 242 } 243 244 err = mlx5r_umr_qp_rst2rts(dev, umrc->qp); 245 if (err) 246 goto err; 247 248 umrc->state = MLX5_UMR_STATE_ACTIVE; 249 return 0; 250 251 err: 252 umrc->state = MLX5_UMR_STATE_ERR; 253 return err; 254 } 255 256 static int mlx5r_umr_post_send(struct ib_qp *ibqp, u32 mkey, struct ib_cqe *cqe, 257 struct mlx5r_umr_wqe *wqe, bool with_data) 258 { 259 unsigned int wqe_size = 260 with_data ? sizeof(struct mlx5r_umr_wqe) : 261 sizeof(struct mlx5r_umr_wqe) - 262 sizeof(struct mlx5_wqe_data_seg); 263 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 264 struct mlx5_core_dev *mdev = dev->mdev; 265 struct mlx5_ib_qp *qp = to_mqp(ibqp); 266 struct mlx5_wqe_ctrl_seg *ctrl; 267 union { 268 struct ib_cqe *ib_cqe; 269 u64 wr_id; 270 } id; 271 void *cur_edge, *seg; 272 unsigned long flags; 273 unsigned int idx; 274 int size, err; 275 276 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)) 277 return -EIO; 278 279 spin_lock_irqsave(&qp->sq.lock, flags); 280 281 err = mlx5r_begin_wqe(qp, &seg, &ctrl, &idx, &size, &cur_edge, 0, 282 cpu_to_be32(mkey), false, false); 283 if (WARN_ON(err)) 284 goto out; 285 286 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 287 288 mlx5r_memcpy_send_wqe(&qp->sq, &cur_edge, &seg, &size, wqe, wqe_size); 289 290 id.ib_cqe = cqe; 291 mlx5r_finish_wqe(qp, ctrl, seg, size, cur_edge, idx, id.wr_id, 0, 292 MLX5_FENCE_MODE_INITIATOR_SMALL, MLX5_OPCODE_UMR); 293 294 mlx5r_ring_db(qp, 1, ctrl); 295 296 out: 297 spin_unlock_irqrestore(&qp->sq.lock, flags); 298 299 return err; 300 } 301 302 static void mlx5r_umr_done(struct ib_cq *cq, struct ib_wc *wc) 303 { 304 struct mlx5_ib_umr_context *context = 305 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); 306 307 context->status = wc->status; 308 complete(&context->done); 309 } 310 311 static inline void mlx5r_umr_init_context(struct mlx5r_umr_context *context) 312 { 313 context->cqe.done = mlx5r_umr_done; 314 init_completion(&context->done); 315 } 316 317 static int mlx5r_umr_post_send_wait(struct mlx5_ib_dev *dev, u32 mkey, 318 struct mlx5r_umr_wqe *wqe, bool with_data) 319 { 320 struct umr_common *umrc = &dev->umrc; 321 struct mlx5r_umr_context umr_context; 322 int err; 323 324 err = umr_check_mkey_mask(dev, be64_to_cpu(wqe->ctrl_seg.mkey_mask)); 325 if (WARN_ON(err)) 326 return err; 327 328 mlx5r_umr_init_context(&umr_context); 329 330 down(&umrc->sem); 331 while (true) { 332 mutex_lock(&umrc->lock); 333 if (umrc->state == MLX5_UMR_STATE_ERR) { 334 mutex_unlock(&umrc->lock); 335 err = -EFAULT; 336 break; 337 } 338 339 if (umrc->state == MLX5_UMR_STATE_RECOVER) { 340 mutex_unlock(&umrc->lock); 341 usleep_range(3000, 5000); 342 continue; 343 } 344 345 err = mlx5r_umr_post_send(umrc->qp, mkey, &umr_context.cqe, wqe, 346 with_data); 347 mutex_unlock(&umrc->lock); 348 if (err) { 349 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", 350 err); 351 break; 352 } 353 354 wait_for_completion(&umr_context.done); 355 356 if (umr_context.status == IB_WC_SUCCESS) 357 break; 358 359 if (umr_context.status == IB_WC_WR_FLUSH_ERR) 360 continue; 361 362 WARN_ON_ONCE(1); 363 mlx5_ib_warn(dev, 364 "reg umr failed (%u). Trying to recover and resubmit the flushed WQEs, mkey = %u\n", 365 umr_context.status, mkey); 366 mutex_lock(&umrc->lock); 367 err = mlx5r_umr_recover(dev); 368 mutex_unlock(&umrc->lock); 369 if (err) 370 mlx5_ib_warn(dev, "couldn't recover UMR, err %d\n", 371 err); 372 err = -EFAULT; 373 break; 374 } 375 up(&umrc->sem); 376 return err; 377 } 378 379 /** 380 * mlx5r_umr_revoke_mr - Fence all DMA on the MR 381 * @mr: The MR to fence 382 * 383 * Upon return the NIC will not be doing any DMA to the pages under the MR, 384 * and any DMA in progress will be completed. Failure of this function 385 * indicates the HW has failed catastrophically. 386 */ 387 int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr) 388 { 389 struct mlx5_ib_dev *dev = mr_to_mdev(mr); 390 struct mlx5r_umr_wqe wqe = {}; 391 392 if (dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 393 return 0; 394 395 wqe.ctrl_seg.mkey_mask |= get_umr_update_pd_mask(); 396 wqe.ctrl_seg.mkey_mask |= get_umr_disable_mr_mask(); 397 wqe.ctrl_seg.flags |= MLX5_UMR_INLINE; 398 399 MLX5_SET(mkc, &wqe.mkey_seg, free, 1); 400 MLX5_SET(mkc, &wqe.mkey_seg, pd, to_mpd(dev->umrc.pd)->pdn); 401 MLX5_SET(mkc, &wqe.mkey_seg, qpn, 0xffffff); 402 MLX5_SET(mkc, &wqe.mkey_seg, mkey_7_0, 403 mlx5_mkey_variant(mr->mmkey.key)); 404 405 return mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, false); 406 } 407 408 static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev, 409 struct mlx5_mkey_seg *seg, 410 unsigned int access_flags) 411 { 412 bool ro_read = (access_flags & IB_ACCESS_RELAXED_ORDERING) && 413 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || 414 pcie_relaxed_ordering_enabled(dev->mdev->pdev)); 415 416 MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 417 MLX5_SET(mkc, seg, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 418 MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); 419 MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); 420 MLX5_SET(mkc, seg, lr, 1); 421 MLX5_SET(mkc, seg, relaxed_ordering_write, 422 !!(access_flags & IB_ACCESS_RELAXED_ORDERING)); 423 MLX5_SET(mkc, seg, relaxed_ordering_read, ro_read); 424 } 425 426 int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd, 427 int access_flags) 428 { 429 struct mlx5_ib_dev *dev = mr_to_mdev(mr); 430 struct mlx5r_umr_wqe wqe = {}; 431 int err; 432 433 wqe.ctrl_seg.mkey_mask = get_umr_update_access_mask(dev); 434 wqe.ctrl_seg.mkey_mask |= get_umr_update_pd_mask(); 435 wqe.ctrl_seg.flags = MLX5_UMR_CHECK_FREE; 436 wqe.ctrl_seg.flags |= MLX5_UMR_INLINE; 437 438 mlx5r_umr_set_access_flags(dev, &wqe.mkey_seg, access_flags); 439 MLX5_SET(mkc, &wqe.mkey_seg, pd, to_mpd(pd)->pdn); 440 MLX5_SET(mkc, &wqe.mkey_seg, qpn, 0xffffff); 441 MLX5_SET(mkc, &wqe.mkey_seg, mkey_7_0, 442 mlx5_mkey_variant(mr->mmkey.key)); 443 444 err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, false); 445 if (err) 446 return err; 447 448 mr->access_flags = access_flags; 449 return 0; 450 } 451 452 #define MLX5_MAX_UMR_CHUNK \ 453 ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - MLX5_UMR_FLEX_ALIGNMENT) 454 #define MLX5_SPARE_UMR_CHUNK 0x10000 455 456 /* 457 * Allocate a temporary buffer to hold the per-page information to transfer to 458 * HW. For efficiency this should be as large as it can be, but buffer 459 * allocation failure is not allowed, so try smaller sizes. 460 */ 461 static void *mlx5r_umr_alloc_xlt(size_t *nents, size_t ent_size, gfp_t gfp_mask) 462 { 463 const size_t xlt_chunk_align = MLX5_UMR_FLEX_ALIGNMENT / ent_size; 464 size_t size; 465 void *res = NULL; 466 467 static_assert(PAGE_SIZE % MLX5_UMR_FLEX_ALIGNMENT == 0); 468 469 /* 470 * MLX5_IB_UPD_XLT_ATOMIC doesn't signal an atomic context just that the 471 * allocation can't trigger any kind of reclaim. 472 */ 473 might_sleep(); 474 475 gfp_mask |= __GFP_ZERO | __GFP_NORETRY; 476 477 /* 478 * If the system already has a suitable high order page then just use 479 * that, but don't try hard to create one. This max is about 1M, so a 480 * free x86 huge page will satisfy it. 481 */ 482 size = min_t(size_t, ent_size * ALIGN(*nents, xlt_chunk_align), 483 MLX5_MAX_UMR_CHUNK); 484 *nents = size / ent_size; 485 res = (void *)__get_free_pages(gfp_mask | __GFP_NOWARN, 486 get_order(size)); 487 if (res) 488 return res; 489 490 if (size > MLX5_SPARE_UMR_CHUNK) { 491 size = MLX5_SPARE_UMR_CHUNK; 492 *nents = size / ent_size; 493 res = (void *)__get_free_pages(gfp_mask | __GFP_NOWARN, 494 get_order(size)); 495 if (res) 496 return res; 497 } 498 499 *nents = PAGE_SIZE / ent_size; 500 res = (void *)__get_free_page(gfp_mask); 501 if (res) 502 return res; 503 504 mutex_lock(&xlt_emergency_page_mutex); 505 memset(xlt_emergency_page, 0, PAGE_SIZE); 506 return xlt_emergency_page; 507 } 508 509 static void mlx5r_umr_free_xlt(void *xlt, size_t length) 510 { 511 if (xlt == xlt_emergency_page) { 512 mutex_unlock(&xlt_emergency_page_mutex); 513 return; 514 } 515 516 free_pages((unsigned long)xlt, get_order(length)); 517 } 518 519 static void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt, 520 struct ib_sge *sg) 521 { 522 struct device *ddev = &dev->mdev->pdev->dev; 523 524 dma_unmap_single(ddev, sg->addr, sg->length, DMA_TO_DEVICE); 525 mlx5r_umr_free_xlt(xlt, sg->length); 526 } 527 528 /* 529 * Create an XLT buffer ready for submission. 530 */ 531 static void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg, 532 size_t nents, size_t ent_size, 533 unsigned int flags) 534 { 535 struct device *ddev = &dev->mdev->pdev->dev; 536 dma_addr_t dma; 537 void *xlt; 538 539 xlt = mlx5r_umr_alloc_xlt(&nents, ent_size, 540 flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : 541 GFP_KERNEL); 542 sg->length = nents * ent_size; 543 dma = dma_map_single(ddev, xlt, sg->length, DMA_TO_DEVICE); 544 if (dma_mapping_error(ddev, dma)) { 545 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); 546 mlx5r_umr_free_xlt(xlt, sg->length); 547 return NULL; 548 } 549 sg->addr = dma; 550 sg->lkey = dev->umrc.pd->local_dma_lkey; 551 552 return xlt; 553 } 554 555 static void 556 mlx5r_umr_set_update_xlt_ctrl_seg(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg, 557 unsigned int flags, struct ib_sge *sg) 558 { 559 if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) 560 /* fail if free */ 561 ctrl_seg->flags = MLX5_UMR_CHECK_FREE; 562 else 563 /* fail if not free */ 564 ctrl_seg->flags = MLX5_UMR_CHECK_NOT_FREE; 565 ctrl_seg->xlt_octowords = 566 cpu_to_be16(mlx5r_umr_get_xlt_octo(sg->length)); 567 } 568 569 static void mlx5r_umr_set_update_xlt_mkey_seg(struct mlx5_ib_dev *dev, 570 struct mlx5_mkey_seg *mkey_seg, 571 struct mlx5_ib_mr *mr, 572 unsigned int page_shift) 573 { 574 mlx5r_umr_set_access_flags(dev, mkey_seg, mr->access_flags); 575 MLX5_SET(mkc, mkey_seg, pd, to_mpd(mr->ibmr.pd)->pdn); 576 MLX5_SET64(mkc, mkey_seg, start_addr, mr->ibmr.iova); 577 MLX5_SET64(mkc, mkey_seg, len, mr->ibmr.length); 578 MLX5_SET(mkc, mkey_seg, log_page_size, page_shift); 579 MLX5_SET(mkc, mkey_seg, qpn, 0xffffff); 580 MLX5_SET(mkc, mkey_seg, mkey_7_0, mlx5_mkey_variant(mr->mmkey.key)); 581 } 582 583 static void 584 mlx5r_umr_set_update_xlt_data_seg(struct mlx5_wqe_data_seg *data_seg, 585 struct ib_sge *sg) 586 { 587 data_seg->byte_count = cpu_to_be32(sg->length); 588 data_seg->lkey = cpu_to_be32(sg->lkey); 589 data_seg->addr = cpu_to_be64(sg->addr); 590 } 591 592 static void mlx5r_umr_update_offset(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg, 593 u64 offset) 594 { 595 u64 octo_offset = mlx5r_umr_get_xlt_octo(offset); 596 597 ctrl_seg->xlt_offset = cpu_to_be16(octo_offset & 0xffff); 598 ctrl_seg->xlt_offset_47_16 = cpu_to_be32(octo_offset >> 16); 599 ctrl_seg->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 600 } 601 602 static void mlx5r_umr_final_update_xlt(struct mlx5_ib_dev *dev, 603 struct mlx5r_umr_wqe *wqe, 604 struct mlx5_ib_mr *mr, struct ib_sge *sg, 605 unsigned int flags) 606 { 607 bool update_pd_access, update_translation; 608 609 if (flags & MLX5_IB_UPD_XLT_ENABLE) 610 wqe->ctrl_seg.mkey_mask |= get_umr_enable_mr_mask(); 611 612 update_pd_access = flags & MLX5_IB_UPD_XLT_ENABLE || 613 flags & MLX5_IB_UPD_XLT_PD || 614 flags & MLX5_IB_UPD_XLT_ACCESS; 615 616 if (update_pd_access) { 617 wqe->ctrl_seg.mkey_mask |= get_umr_update_access_mask(dev); 618 wqe->ctrl_seg.mkey_mask |= get_umr_update_pd_mask(); 619 } 620 621 update_translation = 622 flags & MLX5_IB_UPD_XLT_ENABLE || flags & MLX5_IB_UPD_XLT_ADDR; 623 624 if (update_translation) { 625 wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask(); 626 if (!mr->ibmr.length) 627 MLX5_SET(mkc, &wqe->mkey_seg, length64, 1); 628 } 629 630 wqe->ctrl_seg.xlt_octowords = 631 cpu_to_be16(mlx5r_umr_get_xlt_octo(sg->length)); 632 wqe->data_seg.byte_count = cpu_to_be32(sg->length); 633 } 634 635 /* 636 * Send the DMA list to the HW for a normal MR using UMR. 637 * Dmabuf MR is handled in a similar way, except that the MLX5_IB_UPD_XLT_ZAP 638 * flag may be used. 639 */ 640 int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags) 641 { 642 struct mlx5_ib_dev *dev = mr_to_mdev(mr); 643 struct device *ddev = &dev->mdev->pdev->dev; 644 struct mlx5r_umr_wqe wqe = {}; 645 struct ib_block_iter biter; 646 struct mlx5_mtt *cur_mtt; 647 size_t orig_sg_length; 648 struct mlx5_mtt *mtt; 649 size_t final_size; 650 struct ib_sge sg; 651 u64 offset = 0; 652 int err = 0; 653 654 if (WARN_ON(mr->umem->is_odp)) 655 return -EINVAL; 656 657 mtt = mlx5r_umr_create_xlt( 658 dev, &sg, ib_umem_num_dma_blocks(mr->umem, 1 << mr->page_shift), 659 sizeof(*mtt), flags); 660 if (!mtt) 661 return -ENOMEM; 662 663 orig_sg_length = sg.length; 664 665 mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg); 666 mlx5r_umr_set_update_xlt_mkey_seg(dev, &wqe.mkey_seg, mr, 667 mr->page_shift); 668 mlx5r_umr_set_update_xlt_data_seg(&wqe.data_seg, &sg); 669 670 cur_mtt = mtt; 671 rdma_umem_for_each_dma_block(mr->umem, &biter, BIT(mr->page_shift)) { 672 if (cur_mtt == (void *)mtt + sg.length) { 673 dma_sync_single_for_device(ddev, sg.addr, sg.length, 674 DMA_TO_DEVICE); 675 676 err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, 677 true); 678 if (err) 679 goto err; 680 dma_sync_single_for_cpu(ddev, sg.addr, sg.length, 681 DMA_TO_DEVICE); 682 offset += sg.length; 683 mlx5r_umr_update_offset(&wqe.ctrl_seg, offset); 684 685 cur_mtt = mtt; 686 } 687 688 cur_mtt->ptag = 689 cpu_to_be64(rdma_block_iter_dma_address(&biter) | 690 MLX5_IB_MTT_PRESENT); 691 692 if (mr->umem->is_dmabuf && (flags & MLX5_IB_UPD_XLT_ZAP)) 693 cur_mtt->ptag = 0; 694 695 cur_mtt++; 696 } 697 698 final_size = (void *)cur_mtt - (void *)mtt; 699 sg.length = ALIGN(final_size, MLX5_UMR_FLEX_ALIGNMENT); 700 memset(cur_mtt, 0, sg.length - final_size); 701 mlx5r_umr_final_update_xlt(dev, &wqe, mr, &sg, flags); 702 703 dma_sync_single_for_device(ddev, sg.addr, sg.length, DMA_TO_DEVICE); 704 err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, true); 705 706 err: 707 sg.length = orig_sg_length; 708 mlx5r_umr_unmap_free_xlt(dev, mtt, &sg); 709 return err; 710 } 711 712 static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev) 713 { 714 return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); 715 } 716 717 int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 718 int page_shift, int flags) 719 { 720 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) 721 ? sizeof(struct mlx5_klm) 722 : sizeof(struct mlx5_mtt); 723 const int page_align = MLX5_UMR_FLEX_ALIGNMENT / desc_size; 724 struct mlx5_ib_dev *dev = mr_to_mdev(mr); 725 struct device *ddev = &dev->mdev->pdev->dev; 726 const int page_mask = page_align - 1; 727 struct mlx5r_umr_wqe wqe = {}; 728 size_t pages_mapped = 0; 729 size_t pages_to_map = 0; 730 size_t size_to_map = 0; 731 size_t orig_sg_length; 732 size_t pages_iter; 733 struct ib_sge sg; 734 int err = 0; 735 void *xlt; 736 737 if ((flags & MLX5_IB_UPD_XLT_INDIRECT) && 738 !umr_can_use_indirect_mkey(dev)) 739 return -EPERM; 740 741 if (WARN_ON(!mr->umem->is_odp)) 742 return -EINVAL; 743 744 /* UMR copies MTTs in units of MLX5_UMR_FLEX_ALIGNMENT bytes, 745 * so we need to align the offset and length accordingly 746 */ 747 if (idx & page_mask) { 748 npages += idx & page_mask; 749 idx &= ~page_mask; 750 } 751 pages_to_map = ALIGN(npages, page_align); 752 753 xlt = mlx5r_umr_create_xlt(dev, &sg, npages, desc_size, flags); 754 if (!xlt) 755 return -ENOMEM; 756 757 pages_iter = sg.length / desc_size; 758 orig_sg_length = sg.length; 759 760 if (!(flags & MLX5_IB_UPD_XLT_INDIRECT)) { 761 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem); 762 size_t max_pages = ib_umem_odp_num_pages(odp) - idx; 763 764 pages_to_map = min_t(size_t, pages_to_map, max_pages); 765 } 766 767 mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg); 768 mlx5r_umr_set_update_xlt_mkey_seg(dev, &wqe.mkey_seg, mr, page_shift); 769 mlx5r_umr_set_update_xlt_data_seg(&wqe.data_seg, &sg); 770 771 for (pages_mapped = 0; 772 pages_mapped < pages_to_map && !err; 773 pages_mapped += pages_iter, idx += pages_iter) { 774 npages = min_t(int, pages_iter, pages_to_map - pages_mapped); 775 size_to_map = npages * desc_size; 776 dma_sync_single_for_cpu(ddev, sg.addr, sg.length, 777 DMA_TO_DEVICE); 778 mlx5_odp_populate_xlt(xlt, idx, npages, mr, flags); 779 dma_sync_single_for_device(ddev, sg.addr, sg.length, 780 DMA_TO_DEVICE); 781 sg.length = ALIGN(size_to_map, MLX5_UMR_FLEX_ALIGNMENT); 782 783 if (pages_mapped + pages_iter >= pages_to_map) 784 mlx5r_umr_final_update_xlt(dev, &wqe, mr, &sg, flags); 785 mlx5r_umr_update_offset(&wqe.ctrl_seg, idx * desc_size); 786 err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, true); 787 } 788 sg.length = orig_sg_length; 789 mlx5r_umr_unmap_free_xlt(dev, xlt, &sg); 790 return err; 791 } 792