1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/etherdevice.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "umr.h" 44 #include "qp.h" 45 #include "wr.h" 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum raw_qp_set_mask_map { 59 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 60 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 61 }; 62 63 enum { 64 MLX5_QP_RM_GO_BACK_N = 0x1, 65 }; 66 67 struct mlx5_modify_raw_qp_param { 68 u16 operation; 69 70 u32 set_mask; /* raw_qp_set_mask_map */ 71 72 struct mlx5_rate_limit rl; 73 74 u8 rq_q_ctr_id; 75 u32 port; 76 }; 77 78 struct mlx5_ib_qp_event_work { 79 struct work_struct work; 80 struct mlx5_core_qp *qp; 81 int type; 82 }; 83 84 static struct workqueue_struct *mlx5_ib_qp_event_wq; 85 86 static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90 static int is_qp0(enum ib_qp_type qp_type) 91 { 92 return qp_type == IB_QPT_SMI; 93 } 94 95 static int is_sqp(enum ib_qp_type qp_type) 96 { 97 return is_qp0(qp_type) || is_qp1(qp_type); 98 } 99 100 /** 101 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 102 * to kernel buffer 103 * 104 * @umem: User space memory where the WQ is 105 * @buffer: buffer to copy to 106 * @buflen: buffer length 107 * @wqe_index: index of WQE to copy from 108 * @wq_offset: offset to start of WQ 109 * @wq_wqe_cnt: number of WQEs in WQ 110 * @wq_wqe_shift: log2 of WQE size 111 * @bcnt: number of bytes to copy 112 * @bytes_copied: number of bytes to copy (return value) 113 * 114 * Copies from start of WQE bcnt or less bytes. 115 * Does not gurantee to copy the entire WQE. 116 * 117 * Return: zero on success, or an error code. 118 */ 119 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 120 size_t buflen, int wqe_index, 121 int wq_offset, int wq_wqe_cnt, 122 int wq_wqe_shift, int bcnt, 123 size_t *bytes_copied) 124 { 125 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 126 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 127 size_t copy_length; 128 int ret; 129 130 /* don't copy more than requested, more than buffer length or 131 * beyond WQ end 132 */ 133 copy_length = min_t(u32, buflen, wq_end - offset); 134 copy_length = min_t(u32, copy_length, bcnt); 135 136 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 137 if (ret) 138 return ret; 139 140 if (!ret && bytes_copied) 141 *bytes_copied = copy_length; 142 143 return 0; 144 } 145 146 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 147 void *buffer, size_t buflen, size_t *bc) 148 { 149 struct mlx5_wqe_ctrl_seg *ctrl; 150 size_t bytes_copied = 0; 151 size_t wqe_length; 152 void *p; 153 int ds; 154 155 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 156 157 /* read the control segment first */ 158 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 159 ctrl = p; 160 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 161 wqe_length = ds * MLX5_WQE_DS_UNITS; 162 163 /* read rest of WQE if it spreads over more than one stride */ 164 while (bytes_copied < wqe_length) { 165 size_t copy_length = 166 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 167 168 if (!copy_length) 169 break; 170 171 memcpy(buffer + bytes_copied, p, copy_length); 172 bytes_copied += copy_length; 173 174 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 175 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 176 } 177 *bc = bytes_copied; 178 return 0; 179 } 180 181 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 182 void *buffer, size_t buflen, size_t *bc) 183 { 184 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 185 struct ib_umem *umem = base->ubuffer.umem; 186 struct mlx5_ib_wq *wq = &qp->sq; 187 struct mlx5_wqe_ctrl_seg *ctrl; 188 size_t bytes_copied; 189 size_t bytes_copied2; 190 size_t wqe_length; 191 int ret; 192 int ds; 193 194 /* at first read as much as possible */ 195 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 196 wq->offset, wq->wqe_cnt, 197 wq->wqe_shift, buflen, 198 &bytes_copied); 199 if (ret) 200 return ret; 201 202 /* we need at least control segment size to proceed */ 203 if (bytes_copied < sizeof(*ctrl)) 204 return -EINVAL; 205 206 ctrl = buffer; 207 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 208 wqe_length = ds * MLX5_WQE_DS_UNITS; 209 210 /* if we copied enough then we are done */ 211 if (bytes_copied >= wqe_length) { 212 *bc = bytes_copied; 213 return 0; 214 } 215 216 /* otherwise this a wrapped around wqe 217 * so read the remaining bytes starting 218 * from wqe_index 0 219 */ 220 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 221 buflen - bytes_copied, 0, wq->offset, 222 wq->wqe_cnt, wq->wqe_shift, 223 wqe_length - bytes_copied, 224 &bytes_copied2); 225 226 if (ret) 227 return ret; 228 *bc = bytes_copied + bytes_copied2; 229 return 0; 230 } 231 232 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 233 size_t buflen, size_t *bc) 234 { 235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 236 struct ib_umem *umem = base->ubuffer.umem; 237 238 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 239 return -EINVAL; 240 241 if (!umem) 242 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 243 buflen, bc); 244 245 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 246 } 247 248 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 249 void *buffer, size_t buflen, size_t *bc) 250 { 251 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 252 struct ib_umem *umem = base->ubuffer.umem; 253 struct mlx5_ib_wq *wq = &qp->rq; 254 size_t bytes_copied; 255 int ret; 256 257 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 258 wq->offset, wq->wqe_cnt, 259 wq->wqe_shift, buflen, 260 &bytes_copied); 261 262 if (ret) 263 return ret; 264 *bc = bytes_copied; 265 return 0; 266 } 267 268 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 269 size_t buflen, size_t *bc) 270 { 271 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 272 struct ib_umem *umem = base->ubuffer.umem; 273 struct mlx5_ib_wq *wq = &qp->rq; 274 size_t wqe_size = 1 << wq->wqe_shift; 275 276 if (buflen < wqe_size) 277 return -EINVAL; 278 279 if (!umem) 280 return -EOPNOTSUPP; 281 282 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 283 } 284 285 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 286 void *buffer, size_t buflen, size_t *bc) 287 { 288 struct ib_umem *umem = srq->umem; 289 size_t bytes_copied; 290 int ret; 291 292 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 293 srq->msrq.max, srq->msrq.wqe_shift, 294 buflen, &bytes_copied); 295 296 if (ret) 297 return ret; 298 *bc = bytes_copied; 299 return 0; 300 } 301 302 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 303 size_t buflen, size_t *bc) 304 { 305 struct ib_umem *umem = srq->umem; 306 size_t wqe_size = 1 << srq->msrq.wqe_shift; 307 308 if (buflen < wqe_size) 309 return -EINVAL; 310 311 if (!umem) 312 return -EOPNOTSUPP; 313 314 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 315 } 316 317 static void mlx5_ib_qp_err_syndrome(struct ib_qp *ibqp) 318 { 319 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 320 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 321 struct mlx5_ib_qp *qp = to_mqp(ibqp); 322 void *pas_ext_union, *err_syn; 323 u32 *outb; 324 int err; 325 326 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || 327 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) 328 return; 329 330 outb = kzalloc(outlen, GFP_KERNEL); 331 if (!outb) 332 return; 333 334 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 335 true); 336 if (err) 337 goto out; 338 339 pas_ext_union = 340 MLX5_ADDR_OF(query_qp_out, outb, qp_pas_or_qpc_ext_and_pas); 341 err_syn = MLX5_ADDR_OF(qpc_extension_and_pas_list_in, pas_ext_union, 342 qpc_data_extension.error_syndrome); 343 344 pr_err("%s/%d: QP %d error: %s (0x%x 0x%x 0x%x)\n", 345 ibqp->device->name, ibqp->port, ibqp->qp_num, 346 ib_wc_status_msg( 347 MLX5_GET(cqe_error_syndrome, err_syn, syndrome)), 348 MLX5_GET(cqe_error_syndrome, err_syn, vendor_error_syndrome), 349 MLX5_GET(cqe_error_syndrome, err_syn, hw_syndrome_type), 350 MLX5_GET(cqe_error_syndrome, err_syn, hw_error_syndrome)); 351 out: 352 kfree(outb); 353 } 354 355 static void mlx5_ib_handle_qp_event(struct work_struct *_work) 356 { 357 struct mlx5_ib_qp_event_work *qpe_work = 358 container_of(_work, struct mlx5_ib_qp_event_work, work); 359 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 360 struct ib_event event = {}; 361 362 event.device = ibqp->device; 363 event.element.qp = ibqp; 364 switch (qpe_work->type) { 365 case MLX5_EVENT_TYPE_PATH_MIG: 366 event.event = IB_EVENT_PATH_MIG; 367 break; 368 case MLX5_EVENT_TYPE_COMM_EST: 369 event.event = IB_EVENT_COMM_EST; 370 break; 371 case MLX5_EVENT_TYPE_SQ_DRAINED: 372 event.event = IB_EVENT_SQ_DRAINED; 373 break; 374 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 375 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 376 break; 377 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 378 event.event = IB_EVENT_QP_FATAL; 379 break; 380 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 381 event.event = IB_EVENT_PATH_MIG_ERR; 382 break; 383 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 384 event.event = IB_EVENT_QP_REQ_ERR; 385 break; 386 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 387 event.event = IB_EVENT_QP_ACCESS_ERR; 388 break; 389 default: 390 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", 391 qpe_work->type, qpe_work->qp->qpn); 392 goto out; 393 } 394 395 if ((event.event == IB_EVENT_QP_FATAL) || 396 (event.event == IB_EVENT_QP_ACCESS_ERR)) 397 mlx5_ib_qp_err_syndrome(ibqp); 398 399 ibqp->event_handler(&event, ibqp->qp_context); 400 401 out: 402 mlx5_core_res_put(&qpe_work->qp->common); 403 kfree(qpe_work); 404 } 405 406 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 407 { 408 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 409 struct mlx5_ib_qp_event_work *qpe_work; 410 411 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 412 /* This event is only valid for trans_qps */ 413 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 414 } 415 416 if (!ibqp->event_handler) 417 goto out_no_handler; 418 419 qpe_work = kzalloc_obj(*qpe_work, GFP_ATOMIC); 420 if (!qpe_work) 421 goto out_no_handler; 422 423 qpe_work->qp = qp; 424 qpe_work->type = type; 425 INIT_WORK(&qpe_work->work, mlx5_ib_handle_qp_event); 426 queue_work(mlx5_ib_qp_event_wq, &qpe_work->work); 427 return; 428 429 out_no_handler: 430 mlx5_core_res_put(&qp->common); 431 } 432 433 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 434 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 435 { 436 int wqe_size; 437 int wq_size; 438 439 /* Sanity check RQ size before proceeding */ 440 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 441 return -EINVAL; 442 443 if (!has_rq) { 444 qp->rq.max_gs = 0; 445 qp->rq.wqe_cnt = 0; 446 qp->rq.wqe_shift = 0; 447 cap->max_recv_wr = 0; 448 cap->max_recv_sge = 0; 449 } else { 450 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 451 452 if (ucmd) { 453 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 454 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 455 return -EINVAL; 456 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 457 if ((1 << qp->rq.wqe_shift) / 458 sizeof(struct mlx5_wqe_data_seg) < 459 wq_sig) 460 return -EINVAL; 461 qp->rq.max_gs = 462 (1 << qp->rq.wqe_shift) / 463 sizeof(struct mlx5_wqe_data_seg) - 464 wq_sig; 465 qp->rq.max_post = qp->rq.wqe_cnt; 466 } else { 467 wqe_size = 468 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 469 0; 470 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 471 wqe_size = roundup_pow_of_two(wqe_size); 472 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 473 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 474 qp->rq.wqe_cnt = wq_size / wqe_size; 475 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 476 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 477 wqe_size, 478 MLX5_CAP_GEN(dev->mdev, 479 max_wqe_sz_rq)); 480 return -EINVAL; 481 } 482 qp->rq.wqe_shift = ilog2(wqe_size); 483 qp->rq.max_gs = 484 (1 << qp->rq.wqe_shift) / 485 sizeof(struct mlx5_wqe_data_seg) - 486 wq_sig; 487 qp->rq.max_post = qp->rq.wqe_cnt; 488 } 489 } 490 491 return 0; 492 } 493 494 static int sq_overhead(struct ib_qp_init_attr *attr) 495 { 496 int size = 0; 497 498 switch (attr->qp_type) { 499 case IB_QPT_XRC_INI: 500 size += sizeof(struct mlx5_wqe_xrc_seg); 501 fallthrough; 502 case IB_QPT_RC: 503 size += sizeof(struct mlx5_wqe_ctrl_seg) + 504 max(sizeof(struct mlx5_wqe_atomic_seg) + 505 sizeof(struct mlx5_wqe_raddr_seg), 506 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 507 sizeof(struct mlx5_mkey_seg) + 508 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 509 MLX5_IB_UMR_OCTOWORD); 510 break; 511 512 case IB_QPT_XRC_TGT: 513 return 0; 514 515 case IB_QPT_UC: 516 size += sizeof(struct mlx5_wqe_ctrl_seg) + 517 max(sizeof(struct mlx5_wqe_raddr_seg), 518 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 519 sizeof(struct mlx5_mkey_seg)); 520 break; 521 522 case IB_QPT_UD: 523 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 524 size += sizeof(struct mlx5_wqe_eth_pad) + 525 sizeof(struct mlx5_wqe_eth_seg); 526 fallthrough; 527 case IB_QPT_SMI: 528 case MLX5_IB_QPT_HW_GSI: 529 size += sizeof(struct mlx5_wqe_ctrl_seg) + 530 sizeof(struct mlx5_wqe_datagram_seg); 531 break; 532 533 case MLX5_IB_QPT_REG_UMR: 534 size += sizeof(struct mlx5_wqe_ctrl_seg) + 535 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 536 sizeof(struct mlx5_mkey_seg); 537 break; 538 539 default: 540 return -EINVAL; 541 } 542 543 return size; 544 } 545 546 static int calc_send_wqe(struct ib_qp_init_attr *attr) 547 { 548 int inl_size = 0; 549 int size; 550 551 size = sq_overhead(attr); 552 if (size < 0) 553 return size; 554 555 if (attr->cap.max_inline_data) { 556 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 557 attr->cap.max_inline_data; 558 } 559 560 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 561 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 562 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 563 return MLX5_SIG_WQE_SIZE; 564 else 565 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 566 } 567 568 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 569 { 570 int max_sge; 571 572 if (attr->qp_type == IB_QPT_RC) 573 max_sge = (min_t(int, wqe_size, 512) - 574 sizeof(struct mlx5_wqe_ctrl_seg) - 575 sizeof(struct mlx5_wqe_raddr_seg)) / 576 sizeof(struct mlx5_wqe_data_seg); 577 else if (attr->qp_type == IB_QPT_XRC_INI) 578 max_sge = (min_t(int, wqe_size, 512) - 579 sizeof(struct mlx5_wqe_ctrl_seg) - 580 sizeof(struct mlx5_wqe_xrc_seg) - 581 sizeof(struct mlx5_wqe_raddr_seg)) / 582 sizeof(struct mlx5_wqe_data_seg); 583 else 584 max_sge = (wqe_size - sq_overhead(attr)) / 585 sizeof(struct mlx5_wqe_data_seg); 586 587 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 588 sizeof(struct mlx5_wqe_data_seg)); 589 } 590 591 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 592 struct mlx5_ib_qp *qp) 593 { 594 int wqe_size; 595 int wq_size; 596 597 if (!attr->cap.max_send_wr) 598 return 0; 599 600 wqe_size = calc_send_wqe(attr); 601 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 602 if (wqe_size < 0) 603 return wqe_size; 604 605 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 606 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 607 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 608 return -EINVAL; 609 } 610 611 qp->max_inline_data = wqe_size - sq_overhead(attr) - 612 sizeof(struct mlx5_wqe_inline_seg); 613 attr->cap.max_inline_data = qp->max_inline_data; 614 615 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 616 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 617 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 618 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 619 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 620 qp->sq.wqe_cnt, 621 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 622 return -ENOMEM; 623 } 624 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 625 qp->sq.max_gs = get_send_sge(attr, wqe_size); 626 if (qp->sq.max_gs < attr->cap.max_send_sge) 627 return -ENOMEM; 628 629 attr->cap.max_send_sge = qp->sq.max_gs; 630 qp->sq.max_post = wq_size / wqe_size; 631 attr->cap.max_send_wr = qp->sq.max_post; 632 633 return wq_size; 634 } 635 636 static int set_user_buf_size(struct mlx5_ib_dev *dev, 637 struct mlx5_ib_qp *qp, 638 struct mlx5_ib_create_qp *ucmd, 639 struct mlx5_ib_qp_base *base, 640 struct ib_qp_init_attr *attr) 641 { 642 int desc_sz = 1 << qp->sq.wqe_shift; 643 644 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 645 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 646 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 647 return -EINVAL; 648 } 649 650 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 651 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 652 ucmd->sq_wqe_count); 653 return -EINVAL; 654 } 655 656 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 657 658 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 659 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 660 qp->sq.wqe_cnt, 661 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 662 return -EINVAL; 663 } 664 665 if (attr->qp_type == IB_QPT_RAW_PACKET || 666 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 667 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 668 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 669 } else { 670 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 671 (qp->sq.wqe_cnt << 6); 672 } 673 674 return 0; 675 } 676 677 static int qp_has_rq(struct ib_qp_init_attr *attr) 678 { 679 if (attr->qp_type == IB_QPT_XRC_INI || 680 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 681 attr->qp_type == MLX5_IB_QPT_REG_UMR || 682 !attr->cap.max_recv_wr) 683 return 0; 684 685 return 1; 686 } 687 688 enum { 689 /* this is the first blue flame register in the array of bfregs assigned 690 * to a processes. Since we do not use it for blue flame but rather 691 * regular 64 bit doorbells, we do not need a lock for maintaiing 692 * "odd/even" order 693 */ 694 NUM_NON_BLUE_FLAME_BFREGS = 1, 695 }; 696 697 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 698 { 699 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 700 bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR; 701 } 702 703 static int num_med_bfreg(struct mlx5_ib_dev *dev, 704 struct mlx5_bfreg_info *bfregi) 705 { 706 int n; 707 708 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 709 NUM_NON_BLUE_FLAME_BFREGS; 710 711 return n >= 0 ? n : 0; 712 } 713 714 static int first_med_bfreg(struct mlx5_ib_dev *dev, 715 struct mlx5_bfreg_info *bfregi) 716 { 717 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 718 } 719 720 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 721 struct mlx5_bfreg_info *bfregi) 722 { 723 int med; 724 725 med = num_med_bfreg(dev, bfregi); 726 return ++med; 727 } 728 729 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 730 struct mlx5_bfreg_info *bfregi) 731 { 732 int i; 733 734 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 735 if (!bfregi->count[i]) { 736 bfregi->count[i]++; 737 return i; 738 } 739 } 740 741 return -ENOMEM; 742 } 743 744 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 745 struct mlx5_bfreg_info *bfregi) 746 { 747 int minidx = first_med_bfreg(dev, bfregi); 748 int i; 749 750 if (minidx < 0) 751 return minidx; 752 753 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 754 if (bfregi->count[i] < bfregi->count[minidx]) 755 minidx = i; 756 if (!bfregi->count[minidx]) 757 break; 758 } 759 760 bfregi->count[minidx]++; 761 return minidx; 762 } 763 764 static int alloc_bfreg(struct mlx5_ib_dev *dev, 765 struct mlx5_bfreg_info *bfregi) 766 { 767 int bfregn = -ENOMEM; 768 769 if (bfregi->lib_uar_dyn) 770 return -EINVAL; 771 772 mutex_lock(&bfregi->lock); 773 if (bfregi->ver >= 2) { 774 bfregn = alloc_high_class_bfreg(dev, bfregi); 775 if (bfregn < 0) 776 bfregn = alloc_med_class_bfreg(dev, bfregi); 777 } 778 779 if (bfregn < 0) { 780 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 781 bfregn = 0; 782 bfregi->count[bfregn]++; 783 } 784 mutex_unlock(&bfregi->lock); 785 786 return bfregn; 787 } 788 789 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 790 { 791 mutex_lock(&bfregi->lock); 792 bfregi->count[bfregn]--; 793 mutex_unlock(&bfregi->lock); 794 } 795 796 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 797 { 798 switch (state) { 799 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 800 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 801 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 802 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 803 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 804 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 805 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 806 default: return -1; 807 } 808 } 809 810 static int to_mlx5_st(enum ib_qp_type type) 811 { 812 switch (type) { 813 case IB_QPT_RC: return MLX5_QP_ST_RC; 814 case IB_QPT_UC: return MLX5_QP_ST_UC; 815 case IB_QPT_UD: return MLX5_QP_ST_UD; 816 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 817 case IB_QPT_XRC_INI: 818 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 819 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 820 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 821 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 822 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 823 default: return -EINVAL; 824 } 825 } 826 827 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 828 struct mlx5_ib_cq *recv_cq); 829 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 830 struct mlx5_ib_cq *recv_cq); 831 832 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 833 struct mlx5_bfreg_info *bfregi, u32 bfregn, 834 bool dyn_bfreg) 835 { 836 unsigned int bfregs_per_sys_page; 837 u32 index_of_sys_page; 838 u32 offset; 839 840 if (bfregi->lib_uar_dyn) 841 return -EINVAL; 842 843 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 844 MLX5_NON_FP_BFREGS_PER_UAR; 845 index_of_sys_page = bfregn / bfregs_per_sys_page; 846 847 if (dyn_bfreg) { 848 index_of_sys_page += bfregi->num_static_sys_pages; 849 850 if (index_of_sys_page >= bfregi->num_sys_pages) 851 return -EINVAL; 852 853 if (bfregn > bfregi->num_dyn_bfregs || 854 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 855 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 856 return -EINVAL; 857 } 858 } 859 860 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 861 return bfregi->sys_pages[index_of_sys_page] + offset; 862 } 863 864 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 865 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 866 { 867 struct mlx5_ib_ucontext *context = 868 rdma_udata_to_drv_context( 869 udata, 870 struct mlx5_ib_ucontext, 871 ibucontext); 872 873 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 874 atomic_dec(&dev->delay_drop.rqs_cnt); 875 876 mlx5_ib_db_unmap_user(context, &rwq->db); 877 ib_umem_release(rwq->umem); 878 } 879 880 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 881 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 882 struct mlx5_ib_create_wq *ucmd) 883 { 884 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 885 udata, struct mlx5_ib_ucontext, ibucontext); 886 unsigned long page_size = 0; 887 u32 offset = 0; 888 int err; 889 890 if (!ucmd->buf_addr) 891 return -EINVAL; 892 893 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 894 if (IS_ERR(rwq->umem)) { 895 mlx5_ib_dbg(dev, "umem_get failed\n"); 896 err = PTR_ERR(rwq->umem); 897 return err; 898 } 899 900 page_size = mlx5_umem_find_best_quantized_pgoff( 901 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 902 page_offset, 64, &rwq->rq_page_offset); 903 if (!page_size) { 904 mlx5_ib_warn(dev, "bad offset\n"); 905 err = -EINVAL; 906 goto err_umem; 907 } 908 909 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 910 rwq->page_shift = order_base_2(page_size); 911 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 912 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 913 914 mlx5_ib_dbg( 915 dev, 916 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 917 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 918 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 919 offset); 920 921 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 922 if (err) { 923 mlx5_ib_dbg(dev, "map failed\n"); 924 goto err_umem; 925 } 926 927 return 0; 928 929 err_umem: 930 ib_umem_release(rwq->umem); 931 return err; 932 } 933 934 static int adjust_bfregn(struct mlx5_ib_dev *dev, 935 struct mlx5_bfreg_info *bfregi, int bfregn) 936 { 937 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 938 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 939 } 940 941 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 942 struct mlx5_ib_qp *qp, struct ib_udata *udata, 943 struct ib_qp_init_attr *attr, u32 **in, 944 struct mlx5_ib_create_qp_resp *resp, int *inlen, 945 struct mlx5_ib_qp_base *base, 946 struct mlx5_ib_create_qp *ucmd) 947 { 948 struct mlx5_ib_ucontext *context; 949 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 950 unsigned int page_offset_quantized = 0; 951 unsigned long page_size = 0; 952 int uar_index = 0; 953 int bfregn; 954 int ncont = 0; 955 __be64 *pas; 956 void *qpc; 957 int err; 958 u16 uid; 959 u32 uar_flags; 960 961 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 962 ibucontext); 963 uar_flags = qp->flags_en & 964 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 965 switch (uar_flags) { 966 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 967 uar_index = ucmd->bfreg_index; 968 bfregn = MLX5_IB_INVALID_BFREG; 969 break; 970 case MLX5_QP_FLAG_BFREG_INDEX: 971 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 972 ucmd->bfreg_index, true); 973 if (uar_index < 0) 974 return uar_index; 975 bfregn = MLX5_IB_INVALID_BFREG; 976 break; 977 case 0: 978 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 979 return -EINVAL; 980 bfregn = alloc_bfreg(dev, &context->bfregi); 981 if (bfregn < 0) 982 return bfregn; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 989 if (bfregn != MLX5_IB_INVALID_BFREG) 990 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 991 false); 992 993 qp->rq.offset = 0; 994 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 995 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 996 997 err = set_user_buf_size(dev, qp, ucmd, base, attr); 998 if (err) 999 goto err_bfreg; 1000 1001 if (ucmd->buf_addr && ubuffer->buf_size) { 1002 ubuffer->buf_addr = ucmd->buf_addr; 1003 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1004 ubuffer->buf_size, 0); 1005 if (IS_ERR(ubuffer->umem)) { 1006 err = PTR_ERR(ubuffer->umem); 1007 goto err_bfreg; 1008 } 1009 page_size = mlx5_umem_find_best_quantized_pgoff( 1010 ubuffer->umem, qpc, log_page_size, 1011 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1012 &page_offset_quantized); 1013 if (!page_size) { 1014 err = -EINVAL; 1015 goto err_umem; 1016 } 1017 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 1018 } else { 1019 ubuffer->umem = NULL; 1020 } 1021 1022 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1023 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 1024 *in = kvzalloc(*inlen, GFP_KERNEL); 1025 if (!*in) { 1026 err = -ENOMEM; 1027 goto err_umem; 1028 } 1029 1030 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 1031 MLX5_SET(create_qp_in, *in, uid, uid); 1032 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1033 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1034 if (ubuffer->umem) { 1035 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 1036 MLX5_SET(qpc, qpc, log_page_size, 1037 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1038 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 1039 } 1040 MLX5_SET(qpc, qpc, uar_page, uar_index); 1041 if (bfregn != MLX5_IB_INVALID_BFREG) 1042 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1043 else 1044 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1045 qp->bfregn = bfregn; 1046 1047 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 1048 if (err) { 1049 mlx5_ib_dbg(dev, "map failed\n"); 1050 goto err_free; 1051 } 1052 1053 return 0; 1054 1055 err_free: 1056 kvfree(*in); 1057 1058 err_umem: 1059 ib_umem_release(ubuffer->umem); 1060 1061 err_bfreg: 1062 if (bfregn != MLX5_IB_INVALID_BFREG) 1063 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1064 return err; 1065 } 1066 1067 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1068 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1069 { 1070 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1071 udata, struct mlx5_ib_ucontext, ibucontext); 1072 1073 if (udata) { 1074 /* User QP */ 1075 mlx5_ib_db_unmap_user(context, &qp->db); 1076 ib_umem_release(base->ubuffer.umem); 1077 1078 /* 1079 * Free only the BFREGs which are handled by the kernel. 1080 * BFREGs of UARs allocated dynamically are handled by user. 1081 */ 1082 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1083 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1084 return; 1085 } 1086 1087 /* Kernel QP */ 1088 kvfree(qp->sq.wqe_head); 1089 kvfree(qp->sq.w_list); 1090 kvfree(qp->sq.wrid); 1091 kvfree(qp->sq.wr_data); 1092 kvfree(qp->rq.wrid); 1093 if (qp->db.db) 1094 mlx5_db_free(dev->mdev, &qp->db); 1095 if (qp->buf.frags) 1096 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1097 } 1098 1099 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1100 struct ib_qp_init_attr *init_attr, 1101 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1102 struct mlx5_ib_qp_base *base) 1103 { 1104 int uar_index; 1105 void *qpc; 1106 int err; 1107 1108 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1109 qp->bf.bfreg = &dev->fp_bfreg; 1110 else 1111 qp->bf.bfreg = &dev->bfreg; 1112 1113 /* We need to divide by two since each register is comprised of 1114 * two buffers of identical size, namely odd and even 1115 */ 1116 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1117 uar_index = qp->bf.bfreg->index; 1118 1119 err = calc_sq_size(dev, init_attr, qp); 1120 if (err < 0) { 1121 mlx5_ib_dbg(dev, "err %d\n", err); 1122 return err; 1123 } 1124 1125 qp->rq.offset = 0; 1126 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1127 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1128 1129 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1130 &qp->buf, dev->mdev->priv.numa_node); 1131 if (err) { 1132 mlx5_ib_dbg(dev, "err %d\n", err); 1133 return err; 1134 } 1135 1136 if (qp->rq.wqe_cnt) 1137 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1138 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1139 1140 if (qp->sq.wqe_cnt) { 1141 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1142 MLX5_SEND_WQE_BB; 1143 mlx5_init_fbc_offset(qp->buf.frags + 1144 (qp->sq.offset / PAGE_SIZE), 1145 ilog2(MLX5_SEND_WQE_BB), 1146 ilog2(qp->sq.wqe_cnt), 1147 sq_strides_offset, &qp->sq.fbc); 1148 1149 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1150 } 1151 1152 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1153 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1154 *in = kvzalloc(*inlen, GFP_KERNEL); 1155 if (!*in) { 1156 err = -ENOMEM; 1157 goto err_buf; 1158 } 1159 1160 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1161 MLX5_SET(qpc, qpc, uar_page, uar_index); 1162 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1163 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1164 1165 /* Set "fast registration enabled" for all kernel QPs */ 1166 MLX5_SET(qpc, qpc, fre, 1); 1167 MLX5_SET(qpc, qpc, rlky, 1); 1168 1169 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1170 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1171 1172 mlx5_fill_page_frag_array(&qp->buf, 1173 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1174 *in, pas)); 1175 1176 err = mlx5_db_alloc(dev->mdev, &qp->db); 1177 if (err) { 1178 mlx5_ib_dbg(dev, "err %d\n", err); 1179 goto err_free; 1180 } 1181 1182 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1183 sizeof(*qp->sq.wrid), GFP_KERNEL); 1184 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1185 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1186 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1187 sizeof(*qp->rq.wrid), GFP_KERNEL); 1188 qp->sq.w_list = kvmalloc_objs(*qp->sq.w_list, qp->sq.wqe_cnt); 1189 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1190 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1191 1192 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1193 !qp->sq.w_list || !qp->sq.wqe_head) { 1194 err = -ENOMEM; 1195 goto err_wrid; 1196 } 1197 1198 return 0; 1199 1200 err_wrid: 1201 kvfree(qp->sq.wqe_head); 1202 kvfree(qp->sq.w_list); 1203 kvfree(qp->sq.wrid); 1204 kvfree(qp->sq.wr_data); 1205 kvfree(qp->rq.wrid); 1206 mlx5_db_free(dev->mdev, &qp->db); 1207 1208 err_free: 1209 kvfree(*in); 1210 1211 err_buf: 1212 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1213 return err; 1214 } 1215 1216 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1217 { 1218 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1219 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1220 return MLX5_SRQ_RQ; 1221 else if (!qp->has_rq) 1222 return MLX5_ZERO_LEN_RQ; 1223 1224 return MLX5_NON_ZERO_RQ; 1225 } 1226 1227 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1228 struct mlx5_ib_qp *qp, 1229 struct mlx5_ib_sq *sq, u32 tdn, 1230 struct ib_pd *pd) 1231 { 1232 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1233 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1234 1235 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1236 MLX5_SET(tisc, tisc, transport_domain, tdn); 1237 if (!mlx5_ib_lag_should_assign_affinity(dev) && 1238 mlx5_lag_is_lacp_owner(dev->mdev)) 1239 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 1240 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1241 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1242 1243 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1244 } 1245 1246 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1247 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1248 { 1249 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1250 } 1251 1252 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1253 { 1254 if (sq->flow_rule) 1255 mlx5_del_flow_rules(sq->flow_rule); 1256 sq->flow_rule = NULL; 1257 } 1258 1259 static bool fr_supported(int ts_cap) 1260 { 1261 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1262 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1263 } 1264 1265 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1266 bool fr_sup, bool rt_sup) 1267 { 1268 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1269 if (!rt_sup) { 1270 mlx5_ib_dbg(dev, 1271 "Real time TS format is not supported\n"); 1272 return -EOPNOTSUPP; 1273 } 1274 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1275 } 1276 if (cq->private_flags & MLX5_IB_CQ_PR_TIMESTAMP_COMPLETION) { 1277 if (!fr_sup) { 1278 mlx5_ib_dbg(dev, 1279 "Free running TS format is not supported\n"); 1280 return -EOPNOTSUPP; 1281 } 1282 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1283 } 1284 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1285 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1286 } 1287 1288 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1289 { 1290 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1291 1292 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1293 rt_supported(ts_cap)); 1294 } 1295 1296 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1297 { 1298 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1299 1300 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1301 rt_supported(ts_cap)); 1302 } 1303 1304 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1305 struct mlx5_ib_cq *recv_cq) 1306 { 1307 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1308 bool fr_sup = fr_supported(ts_cap); 1309 bool rt_sup = rt_supported(ts_cap); 1310 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1311 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1312 int send_ts_format = 1313 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1314 default_ts; 1315 int recv_ts_format = 1316 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1317 default_ts; 1318 1319 if (send_ts_format < 0 || recv_ts_format < 0) 1320 return -EOPNOTSUPP; 1321 1322 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1323 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1324 send_ts_format != recv_ts_format) { 1325 mlx5_ib_dbg( 1326 dev, 1327 "The send ts_format does not match the receive ts_format\n"); 1328 return -EOPNOTSUPP; 1329 } 1330 1331 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1332 } 1333 1334 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1335 struct ib_udata *udata, 1336 struct mlx5_ib_sq *sq, void *qpin, 1337 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1338 { 1339 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1340 __be64 *pas; 1341 void *in; 1342 void *sqc; 1343 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1344 void *wq; 1345 int inlen; 1346 int err; 1347 unsigned int page_offset_quantized; 1348 unsigned long page_size; 1349 int ts_format; 1350 1351 ts_format = get_sq_ts_format(dev, cq); 1352 if (ts_format < 0) 1353 return ts_format; 1354 1355 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1356 ubuffer->buf_size, 0); 1357 if (IS_ERR(sq->ubuffer.umem)) 1358 return PTR_ERR(sq->ubuffer.umem); 1359 page_size = mlx5_umem_find_best_quantized_pgoff( 1360 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1361 page_offset, 64, &page_offset_quantized); 1362 if (!page_size) { 1363 err = -EINVAL; 1364 goto err_umem; 1365 } 1366 1367 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1368 sizeof(u64) * 1369 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1370 in = kvzalloc(inlen, GFP_KERNEL); 1371 if (!in) { 1372 err = -ENOMEM; 1373 goto err_umem; 1374 } 1375 1376 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1377 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1378 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1379 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1380 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1381 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1382 MLX5_SET(sqc, sqc, ts_format, ts_format); 1383 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1384 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1385 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1386 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1387 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1388 MLX5_CAP_ETH(dev->mdev, swp)) 1389 MLX5_SET(sqc, sqc, allow_swp, 1); 1390 1391 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1392 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1393 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1394 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1395 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1396 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1397 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1398 MLX5_SET(wq, wq, log_wq_pg_sz, 1399 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1400 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1401 1402 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1403 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1404 1405 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1406 1407 kvfree(in); 1408 1409 if (err) 1410 goto err_umem; 1411 1412 return 0; 1413 1414 err_umem: 1415 ib_umem_release(sq->ubuffer.umem); 1416 sq->ubuffer.umem = NULL; 1417 1418 return err; 1419 } 1420 1421 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1422 struct mlx5_ib_sq *sq) 1423 { 1424 destroy_flow_rule_vport_sq(sq); 1425 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1426 ib_umem_release(sq->ubuffer.umem); 1427 } 1428 1429 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1430 struct mlx5_ib_rq *rq, void *qpin, 1431 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1432 { 1433 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1434 __be64 *pas; 1435 void *in; 1436 void *rqc; 1437 void *wq; 1438 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1439 struct ib_umem *umem = rq->base.ubuffer.umem; 1440 unsigned int page_offset_quantized; 1441 unsigned long page_size = 0; 1442 int ts_format; 1443 size_t inlen; 1444 int err; 1445 1446 ts_format = get_rq_ts_format(dev, cq); 1447 if (ts_format < 0) 1448 return ts_format; 1449 1450 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1451 MLX5_ADAPTER_PAGE_SHIFT, 1452 page_offset, 64, 1453 &page_offset_quantized); 1454 if (!page_size) 1455 return -EINVAL; 1456 1457 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1458 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1459 in = kvzalloc(inlen, GFP_KERNEL); 1460 if (!in) 1461 return -ENOMEM; 1462 1463 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1464 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1465 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1466 MLX5_SET(rqc, rqc, vsd, 1); 1467 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1468 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1469 MLX5_SET(rqc, rqc, ts_format, ts_format); 1470 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1471 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1472 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1473 1474 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1475 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1476 1477 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1478 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1479 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1480 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1481 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1482 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1483 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1484 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1485 MLX5_SET(wq, wq, log_wq_pg_sz, 1486 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1487 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1488 1489 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1490 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1491 1492 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1493 1494 kvfree(in); 1495 1496 return err; 1497 } 1498 1499 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1500 struct mlx5_ib_rq *rq) 1501 { 1502 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1503 } 1504 1505 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1506 struct mlx5_ib_rq *rq, 1507 u32 qp_flags_en, 1508 struct ib_pd *pd) 1509 { 1510 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1511 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1512 mlx5_ib_disable_lb(dev, false, true); 1513 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1514 } 1515 1516 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1517 struct mlx5_ib_rq *rq, u32 tdn, 1518 u32 *qp_flags_en, struct ib_pd *pd, 1519 u32 *out) 1520 { 1521 u8 lb_flag = 0; 1522 u32 *in; 1523 void *tirc; 1524 int inlen; 1525 int err; 1526 1527 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1528 in = kvzalloc(inlen, GFP_KERNEL); 1529 if (!in) 1530 return -ENOMEM; 1531 1532 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1533 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1534 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1535 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1536 MLX5_SET(tirc, tirc, transport_domain, tdn); 1537 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1538 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1539 1540 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1541 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1542 1543 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1544 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1545 1546 if (dev->is_rep) { 1547 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1548 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1549 } 1550 1551 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1552 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1553 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1554 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1555 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1556 err = mlx5_ib_enable_lb(dev, false, true); 1557 1558 if (err) 1559 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1560 } 1561 kvfree(in); 1562 1563 return err; 1564 } 1565 1566 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1567 u32 *in, size_t inlen, struct ib_pd *pd, 1568 struct ib_udata *udata, 1569 struct mlx5_ib_create_qp_resp *resp, 1570 struct ib_qp_init_attr *init_attr) 1571 { 1572 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1573 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1574 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1575 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1576 udata, struct mlx5_ib_ucontext, ibucontext); 1577 int err; 1578 u32 tdn = mucontext->tdn; 1579 u16 uid = to_mpd(pd)->uid; 1580 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1581 1582 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1583 return -EINVAL; 1584 if (qp->sq.wqe_cnt) { 1585 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1586 if (err) 1587 return err; 1588 1589 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1590 to_mcq(init_attr->send_cq)); 1591 if (err) 1592 goto err_destroy_tis; 1593 1594 if (uid) { 1595 resp->tisn = sq->tisn; 1596 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1597 resp->sqn = sq->base.mqp.qpn; 1598 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1599 } 1600 1601 sq->base.container_mibqp = qp; 1602 sq->base.mqp.event = mlx5_ib_qp_event; 1603 } 1604 1605 if (qp->rq.wqe_cnt) { 1606 if (!rq->base.ubuffer.umem) { 1607 err = -EINVAL; 1608 goto err_destroy_sq; 1609 } 1610 1611 rq->base.container_mibqp = qp; 1612 1613 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1614 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1615 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1616 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1617 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1618 to_mcq(init_attr->recv_cq)); 1619 if (err) 1620 goto err_destroy_sq; 1621 1622 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1623 out); 1624 if (err) 1625 goto err_destroy_rq; 1626 1627 if (uid) { 1628 resp->rqn = rq->base.mqp.qpn; 1629 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1630 resp->tirn = rq->tirn; 1631 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1632 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1633 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1634 resp->tir_icm_addr = MLX5_GET( 1635 create_tir_out, out, icm_address_31_0); 1636 resp->tir_icm_addr |= 1637 (u64)MLX5_GET(create_tir_out, out, 1638 icm_address_39_32) 1639 << 32; 1640 resp->tir_icm_addr |= 1641 (u64)MLX5_GET(create_tir_out, out, 1642 icm_address_63_40) 1643 << 40; 1644 resp->comp_mask |= 1645 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1646 } 1647 } 1648 } 1649 1650 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1651 rq->base.mqp.qpn; 1652 return 0; 1653 1654 err_destroy_rq: 1655 destroy_raw_packet_qp_rq(dev, rq); 1656 err_destroy_sq: 1657 if (!qp->sq.wqe_cnt) 1658 return err; 1659 destroy_raw_packet_qp_sq(dev, sq); 1660 err_destroy_tis: 1661 destroy_raw_packet_qp_tis(dev, sq, pd); 1662 1663 return err; 1664 } 1665 1666 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1667 struct mlx5_ib_qp *qp) 1668 { 1669 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1670 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1671 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1672 1673 if (qp->rq.wqe_cnt) { 1674 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1675 destroy_raw_packet_qp_rq(dev, rq); 1676 } 1677 1678 if (qp->sq.wqe_cnt) { 1679 destroy_raw_packet_qp_sq(dev, sq); 1680 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1681 } 1682 } 1683 1684 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1685 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1686 { 1687 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1688 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1689 1690 sq->sq = &qp->sq; 1691 rq->rq = &qp->rq; 1692 sq->doorbell = &qp->db; 1693 rq->doorbell = &qp->db; 1694 } 1695 1696 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1697 { 1698 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1699 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1700 mlx5_ib_disable_lb(dev, false, true); 1701 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1702 to_mpd(qp->ibqp.pd)->uid); 1703 } 1704 1705 struct mlx5_create_qp_params { 1706 struct ib_udata *udata; 1707 size_t inlen; 1708 size_t outlen; 1709 size_t ucmd_size; 1710 void *ucmd; 1711 u8 is_rss_raw : 1; 1712 struct ib_qp_init_attr *attr; 1713 u32 uidx; 1714 struct mlx5_ib_create_qp_resp resp; 1715 }; 1716 1717 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1718 struct mlx5_ib_qp *qp, 1719 struct mlx5_create_qp_params *params) 1720 { 1721 struct ib_qp_init_attr *init_attr = params->attr; 1722 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1723 struct ib_udata *udata = params->udata; 1724 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1725 udata, struct mlx5_ib_ucontext, ibucontext); 1726 int inlen; 1727 int outlen; 1728 int err; 1729 u32 *in; 1730 u32 *out; 1731 void *tirc; 1732 void *hfso; 1733 u32 selected_fields = 0; 1734 u32 outer_l4; 1735 u32 tdn = mucontext->tdn; 1736 u8 lb_flag = 0; 1737 1738 if (ucmd->comp_mask) { 1739 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1740 return -EOPNOTSUPP; 1741 } 1742 1743 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1744 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1745 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1746 return -EOPNOTSUPP; 1747 } 1748 1749 if (dev->is_rep) 1750 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1751 1752 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1753 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1754 1755 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1756 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1757 1758 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1759 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1760 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1761 if (!in) 1762 return -ENOMEM; 1763 1764 out = in + MLX5_ST_SZ_DW(create_tir_in); 1765 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1766 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1767 MLX5_SET(tirc, tirc, disp_type, 1768 MLX5_TIRC_DISP_TYPE_INDIRECT); 1769 MLX5_SET(tirc, tirc, indirect_table, 1770 init_attr->rwq_ind_tbl->ind_tbl_num); 1771 MLX5_SET(tirc, tirc, transport_domain, tdn); 1772 1773 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1774 1775 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1776 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1777 1778 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1779 1780 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1781 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1782 else 1783 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1784 1785 switch (ucmd->rx_hash_function) { 1786 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1787 { 1788 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1789 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1790 1791 if (len != ucmd->rx_key_len) { 1792 err = -EINVAL; 1793 goto err; 1794 } 1795 1796 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1797 memcpy(rss_key, ucmd->rx_hash_key, len); 1798 break; 1799 } 1800 default: 1801 err = -EOPNOTSUPP; 1802 goto err; 1803 } 1804 1805 if (!ucmd->rx_hash_fields_mask) { 1806 /* special case when this TIR serves as steering entry without hashing */ 1807 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1808 goto create_tir; 1809 err = -EINVAL; 1810 goto err; 1811 } 1812 1813 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1814 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1815 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1816 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1817 err = -EINVAL; 1818 goto err; 1819 } 1820 1821 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1822 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1823 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1824 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1825 MLX5_L3_PROT_TYPE_IPV4); 1826 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1827 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1828 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1829 MLX5_L3_PROT_TYPE_IPV6); 1830 1831 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1832 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1833 << 0 | 1834 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1835 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1836 << 1 | 1837 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1838 1839 /* Check that only one l4 protocol is set */ 1840 if (outer_l4 & (outer_l4 - 1)) { 1841 err = -EINVAL; 1842 goto err; 1843 } 1844 1845 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1846 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1847 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1848 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1849 MLX5_L4_PROT_TYPE_TCP); 1850 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1851 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1852 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1853 MLX5_L4_PROT_TYPE_UDP); 1854 1855 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1856 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1857 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1858 1859 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1860 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1861 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1862 1863 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1864 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1865 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1866 1867 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1868 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1869 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1870 1871 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1872 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1873 1874 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1875 1876 create_tir: 1877 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1878 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1879 1880 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1881 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1882 err = mlx5_ib_enable_lb(dev, false, true); 1883 1884 if (err) 1885 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1886 to_mpd(pd)->uid); 1887 } 1888 1889 if (err) 1890 goto err; 1891 1892 if (mucontext->devx_uid) { 1893 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1894 params->resp.tirn = qp->rss_qp.tirn; 1895 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1896 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1897 params->resp.tir_icm_addr = 1898 MLX5_GET(create_tir_out, out, icm_address_31_0); 1899 params->resp.tir_icm_addr |= 1900 (u64)MLX5_GET(create_tir_out, out, 1901 icm_address_39_32) 1902 << 32; 1903 params->resp.tir_icm_addr |= 1904 (u64)MLX5_GET(create_tir_out, out, 1905 icm_address_63_40) 1906 << 40; 1907 params->resp.comp_mask |= 1908 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1909 } 1910 } 1911 1912 kvfree(in); 1913 /* qpn is reserved for that QP */ 1914 qp->trans_qp.base.mqp.qpn = 0; 1915 qp->is_rss = true; 1916 return 0; 1917 1918 err: 1919 kvfree(in); 1920 return err; 1921 } 1922 1923 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1924 struct mlx5_ib_qp *qp, 1925 struct ib_qp_init_attr *init_attr, 1926 void *qpc) 1927 { 1928 int scqe_sz; 1929 bool allow_scat_cqe = false; 1930 1931 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1932 1933 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1934 return; 1935 1936 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1937 if (scqe_sz == 128) { 1938 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1939 return; 1940 } 1941 1942 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1943 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1944 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1945 } 1946 1947 static int atomic_size_to_mode(int size_mask) 1948 { 1949 /* driver does not support atomic_size > 256B 1950 * and does not know how to translate bigger sizes 1951 */ 1952 int supported_size_mask = size_mask & 0x1ff; 1953 int log_max_size; 1954 1955 if (!supported_size_mask) 1956 return -EOPNOTSUPP; 1957 1958 log_max_size = __fls(supported_size_mask); 1959 1960 if (log_max_size > 3) 1961 return log_max_size; 1962 1963 return MLX5_ATOMIC_MODE_8B; 1964 } 1965 1966 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1967 struct mlx5_ib_qp *qp) 1968 { 1969 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1970 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1971 int atomic_mode = -EOPNOTSUPP; 1972 int atomic_size_mask; 1973 1974 if (!atomic) 1975 return -EOPNOTSUPP; 1976 1977 if (qp->type == MLX5_IB_QPT_DCT) 1978 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1979 else 1980 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1981 1982 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1983 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1984 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1985 1986 if (atomic_mode <= 0 && 1987 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1988 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1989 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1990 1991 /* OOO DP QPs do not support larger than 8-Bytes atomic operations */ 1992 if (atomic_mode > MLX5_ATOMIC_MODE_8B && qp->is_ooo_rq) 1993 atomic_mode = MLX5_ATOMIC_MODE_8B; 1994 1995 return atomic_mode; 1996 } 1997 1998 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1999 struct mlx5_create_qp_params *params) 2000 { 2001 struct ib_qp_init_attr *attr = params->attr; 2002 u32 uidx = params->uidx; 2003 struct mlx5_ib_resources *devr = &dev->devr; 2004 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2005 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2006 struct mlx5_core_dev *mdev = dev->mdev; 2007 struct mlx5_ib_qp_base *base; 2008 unsigned long flags; 2009 void *qpc; 2010 u32 *in; 2011 int err; 2012 2013 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2014 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2015 2016 in = kvzalloc(inlen, GFP_KERNEL); 2017 if (!in) 2018 return -ENOMEM; 2019 2020 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2021 2022 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 2023 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2024 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 2025 2026 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2027 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2028 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2029 MLX5_SET(qpc, qpc, cd_master, 1); 2030 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2031 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2032 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2033 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2034 2035 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 2036 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 2037 MLX5_SET(qpc, qpc, no_sq, 1); 2038 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2039 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2040 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2041 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 2042 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2043 2044 /* 0xffffff means we ask to work with cqe version 0 */ 2045 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2046 MLX5_SET(qpc, qpc, user_index, uidx); 2047 2048 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2049 MLX5_SET(qpc, qpc, end_padding_mode, 2050 MLX5_WQ_END_PAD_MODE_ALIGN); 2051 /* Special case to clean flag */ 2052 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2053 } 2054 2055 base = &qp->trans_qp.base; 2056 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2057 kvfree(in); 2058 if (err) 2059 return err; 2060 2061 base->container_mibqp = qp; 2062 base->mqp.event = mlx5_ib_qp_event; 2063 if (MLX5_CAP_GEN(mdev, ece_support)) 2064 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2065 2066 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2067 list_add_tail(&qp->qps_list, &dev->qp_list); 2068 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2069 2070 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 2071 return 0; 2072 } 2073 2074 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2075 struct mlx5_ib_qp *qp, 2076 struct mlx5_create_qp_params *params) 2077 { 2078 struct ib_qp_init_attr *init_attr = params->attr; 2079 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2080 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2081 struct ib_udata *udata = params->udata; 2082 u32 uidx = params->uidx; 2083 struct mlx5_ib_resources *devr = &dev->devr; 2084 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2085 struct mlx5_core_dev *mdev = dev->mdev; 2086 struct mlx5_ib_cq *send_cq; 2087 struct mlx5_ib_cq *recv_cq; 2088 unsigned long flags; 2089 struct mlx5_ib_qp_base *base; 2090 int ts_format; 2091 int mlx5_st; 2092 void *qpc; 2093 u32 *in; 2094 int err; 2095 2096 spin_lock_init(&qp->sq.lock); 2097 spin_lock_init(&qp->rq.lock); 2098 2099 mlx5_st = to_mlx5_st(qp->type); 2100 if (mlx5_st < 0) 2101 return -EINVAL; 2102 2103 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2104 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2105 2106 base = &qp->trans_qp.base; 2107 2108 qp->has_rq = qp_has_rq(init_attr); 2109 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2110 if (err) { 2111 mlx5_ib_dbg(dev, "err %d\n", err); 2112 return err; 2113 } 2114 2115 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2116 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2117 return -EINVAL; 2118 2119 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2120 return -EINVAL; 2121 2122 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2123 to_mcq(init_attr->recv_cq)); 2124 2125 if (ts_format < 0) 2126 return ts_format; 2127 2128 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2129 &inlen, base, ucmd); 2130 if (err) 2131 return err; 2132 2133 if (MLX5_CAP_GEN(mdev, ece_support)) 2134 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2135 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2136 2137 MLX5_SET(qpc, qpc, st, mlx5_st); 2138 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2139 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2140 2141 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2142 MLX5_SET(qpc, qpc, wq_signature, 1); 2143 2144 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2145 MLX5_SET(qpc, qpc, cd_master, 1); 2146 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2147 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2148 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2149 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2150 2151 if (qp->rq.wqe_cnt) { 2152 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2153 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2154 } 2155 2156 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2157 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2158 ucmd->dci_streams.log_num_concurent); 2159 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2160 ucmd->dci_streams.log_num_errored); 2161 } 2162 2163 MLX5_SET(qpc, qpc, ts_format, ts_format); 2164 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2165 2166 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2167 2168 /* Set default resources */ 2169 if (init_attr->srq) { 2170 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2171 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2172 to_msrq(init_attr->srq)->msrq.srqn); 2173 } else { 2174 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2175 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2176 to_msrq(devr->s1)->msrq.srqn); 2177 } 2178 2179 if (init_attr->send_cq) 2180 MLX5_SET(qpc, qpc, cqn_snd, 2181 to_mcq(init_attr->send_cq)->mcq.cqn); 2182 2183 if (init_attr->recv_cq) 2184 MLX5_SET(qpc, qpc, cqn_rcv, 2185 to_mcq(init_attr->recv_cq)->mcq.cqn); 2186 2187 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2188 2189 /* 0xffffff means we ask to work with cqe version 0 */ 2190 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2191 MLX5_SET(qpc, qpc, user_index, uidx); 2192 2193 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2194 MLX5_SET(qpc, qpc, end_padding_mode, 2195 MLX5_WQ_END_PAD_MODE_ALIGN); 2196 /* Special case to clean flag */ 2197 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2198 } 2199 2200 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2201 2202 kvfree(in); 2203 if (err) 2204 goto err_create; 2205 2206 base->container_mibqp = qp; 2207 base->mqp.event = mlx5_ib_qp_event; 2208 if (MLX5_CAP_GEN(mdev, ece_support)) 2209 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2210 2211 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2212 &send_cq, &recv_cq); 2213 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2214 mlx5_ib_lock_cqs(send_cq, recv_cq); 2215 /* Maintain device to QPs access, needed for further handling via reset 2216 * flow 2217 */ 2218 list_add_tail(&qp->qps_list, &dev->qp_list); 2219 /* Maintain CQ to QPs access, needed for further handling via reset flow 2220 */ 2221 if (send_cq) 2222 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2223 if (recv_cq) 2224 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2225 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2226 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2227 2228 return 0; 2229 2230 err_create: 2231 destroy_qp(dev, qp, base, udata); 2232 return err; 2233 } 2234 2235 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2236 struct mlx5_ib_qp *qp, 2237 struct mlx5_create_qp_params *params) 2238 { 2239 struct ib_qp_init_attr *init_attr = params->attr; 2240 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2241 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2242 struct ib_udata *udata = params->udata; 2243 u32 uidx = params->uidx; 2244 struct mlx5_ib_resources *devr = &dev->devr; 2245 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2246 struct mlx5_core_dev *mdev = dev->mdev; 2247 struct mlx5_ib_cq *send_cq; 2248 struct mlx5_ib_cq *recv_cq; 2249 unsigned long flags; 2250 struct mlx5_ib_qp_base *base; 2251 int ts_format; 2252 int mlx5_st; 2253 void *qpc; 2254 u32 *in; 2255 int err; 2256 2257 spin_lock_init(&qp->sq.lock); 2258 spin_lock_init(&qp->rq.lock); 2259 2260 mlx5_st = to_mlx5_st(qp->type); 2261 if (mlx5_st < 0) 2262 return -EINVAL; 2263 2264 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2265 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2266 2267 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2268 qp->underlay_qpn = init_attr->source_qpn; 2269 2270 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2271 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2272 &qp->raw_packet_qp.rq.base : 2273 &qp->trans_qp.base; 2274 2275 qp->has_rq = qp_has_rq(init_attr); 2276 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2277 if (err) { 2278 mlx5_ib_dbg(dev, "err %d\n", err); 2279 return err; 2280 } 2281 2282 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2283 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2284 return -EINVAL; 2285 2286 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2287 return -EINVAL; 2288 2289 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2290 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2291 to_mcq(init_attr->recv_cq)); 2292 if (ts_format < 0) 2293 return ts_format; 2294 } 2295 2296 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2297 &inlen, base, ucmd); 2298 if (err) 2299 return err; 2300 2301 if (is_sqp(init_attr->qp_type)) 2302 qp->port = init_attr->port_num; 2303 2304 if (MLX5_CAP_GEN(mdev, ece_support)) 2305 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2306 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2307 2308 MLX5_SET(qpc, qpc, st, mlx5_st); 2309 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2310 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2311 2312 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2313 MLX5_SET(qpc, qpc, wq_signature, 1); 2314 2315 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2316 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2317 2318 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2319 MLX5_SET(qpc, qpc, cd_master, 1); 2320 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2321 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2322 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2323 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2324 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2325 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2326 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2327 (init_attr->qp_type == IB_QPT_RC || 2328 init_attr->qp_type == IB_QPT_UC)) { 2329 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2330 2331 MLX5_SET(qpc, qpc, cs_res, 2332 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2333 MLX5_RES_SCAT_DATA32_CQE); 2334 } 2335 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2336 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2337 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2338 2339 if (qp->rq.wqe_cnt) { 2340 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2341 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2342 } 2343 2344 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2345 MLX5_SET(qpc, qpc, ts_format, ts_format); 2346 2347 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2348 2349 if (qp->sq.wqe_cnt) { 2350 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2351 } else { 2352 MLX5_SET(qpc, qpc, no_sq, 1); 2353 if (init_attr->srq && 2354 init_attr->srq->srq_type == IB_SRQT_TM) 2355 MLX5_SET(qpc, qpc, offload_type, 2356 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2357 } 2358 2359 /* Set default resources */ 2360 switch (init_attr->qp_type) { 2361 case IB_QPT_XRC_INI: 2362 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2363 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2364 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2365 break; 2366 default: 2367 if (init_attr->srq) { 2368 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2369 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2370 } else { 2371 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2372 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2373 } 2374 } 2375 2376 if (init_attr->send_cq) 2377 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2378 2379 if (init_attr->recv_cq) 2380 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2381 2382 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2383 2384 /* 0xffffff means we ask to work with cqe version 0 */ 2385 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2386 MLX5_SET(qpc, qpc, user_index, uidx); 2387 2388 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2389 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2390 MLX5_SET(qpc, qpc, end_padding_mode, 2391 MLX5_WQ_END_PAD_MODE_ALIGN); 2392 /* Special case to clean flag */ 2393 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2394 } 2395 2396 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2397 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2398 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2399 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2400 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2401 ¶ms->resp, init_attr); 2402 } else 2403 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2404 2405 kvfree(in); 2406 if (err) 2407 goto err_create; 2408 2409 base->container_mibqp = qp; 2410 base->mqp.event = mlx5_ib_qp_event; 2411 if (MLX5_CAP_GEN(mdev, ece_support)) 2412 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2413 2414 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2415 &send_cq, &recv_cq); 2416 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2417 mlx5_ib_lock_cqs(send_cq, recv_cq); 2418 /* Maintain device to QPs access, needed for further handling via reset 2419 * flow 2420 */ 2421 list_add_tail(&qp->qps_list, &dev->qp_list); 2422 /* Maintain CQ to QPs access, needed for further handling via reset flow 2423 */ 2424 if (send_cq) 2425 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2426 if (recv_cq) 2427 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2428 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2429 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2430 2431 return 0; 2432 2433 err_create: 2434 destroy_qp(dev, qp, base, udata); 2435 return err; 2436 } 2437 2438 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2439 struct mlx5_ib_qp *qp, 2440 struct mlx5_create_qp_params *params) 2441 { 2442 struct ib_qp_init_attr *attr = params->attr; 2443 u32 uidx = params->uidx; 2444 struct mlx5_ib_resources *devr = &dev->devr; 2445 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2446 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2447 struct mlx5_core_dev *mdev = dev->mdev; 2448 struct mlx5_ib_cq *send_cq; 2449 struct mlx5_ib_cq *recv_cq; 2450 unsigned long flags; 2451 struct mlx5_ib_qp_base *base; 2452 int mlx5_st; 2453 void *qpc; 2454 u32 *in; 2455 int err; 2456 2457 spin_lock_init(&qp->sq.lock); 2458 spin_lock_init(&qp->rq.lock); 2459 2460 mlx5_st = to_mlx5_st(qp->type); 2461 if (mlx5_st < 0) 2462 return -EINVAL; 2463 2464 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2465 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2466 2467 base = &qp->trans_qp.base; 2468 2469 qp->has_rq = qp_has_rq(attr); 2470 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2471 if (err) { 2472 mlx5_ib_dbg(dev, "err %d\n", err); 2473 return err; 2474 } 2475 2476 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2477 if (err) 2478 return err; 2479 2480 if (is_sqp(attr->qp_type)) 2481 qp->port = attr->port_num; 2482 2483 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2484 2485 MLX5_SET(qpc, qpc, st, mlx5_st); 2486 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2487 2488 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2489 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2490 else 2491 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2492 2493 2494 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2495 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2496 2497 if (qp->rq.wqe_cnt) { 2498 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2499 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2500 } 2501 2502 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2503 2504 if (qp->sq.wqe_cnt) 2505 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2506 else 2507 MLX5_SET(qpc, qpc, no_sq, 1); 2508 2509 if (attr->srq) { 2510 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2511 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2512 to_msrq(attr->srq)->msrq.srqn); 2513 } else { 2514 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2515 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2516 to_msrq(devr->s1)->msrq.srqn); 2517 } 2518 2519 if (attr->send_cq) 2520 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2521 2522 if (attr->recv_cq) 2523 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2524 2525 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2526 2527 /* 0xffffff means we ask to work with cqe version 0 */ 2528 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2529 MLX5_SET(qpc, qpc, user_index, uidx); 2530 2531 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2532 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2533 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2534 2535 if (qp->flags & IB_QP_CREATE_INTEGRITY_EN && 2536 MLX5_CAP_GEN(mdev, go_back_n)) 2537 MLX5_SET(qpc, qpc, retry_mode, MLX5_QP_RM_GO_BACK_N); 2538 2539 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2540 kvfree(in); 2541 if (err) 2542 goto err_create; 2543 2544 base->container_mibqp = qp; 2545 base->mqp.event = mlx5_ib_qp_event; 2546 2547 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2548 &send_cq, &recv_cq); 2549 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2550 mlx5_ib_lock_cqs(send_cq, recv_cq); 2551 /* Maintain device to QPs access, needed for further handling via reset 2552 * flow 2553 */ 2554 list_add_tail(&qp->qps_list, &dev->qp_list); 2555 /* Maintain CQ to QPs access, needed for further handling via reset flow 2556 */ 2557 if (send_cq) 2558 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2559 if (recv_cq) 2560 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2561 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2562 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2563 2564 return 0; 2565 2566 err_create: 2567 destroy_qp(dev, qp, base, NULL); 2568 return err; 2569 } 2570 2571 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2572 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2573 { 2574 if (send_cq) { 2575 if (recv_cq) { 2576 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2577 spin_lock(&send_cq->lock); 2578 spin_lock_nested(&recv_cq->lock, 2579 SINGLE_DEPTH_NESTING); 2580 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2581 spin_lock(&send_cq->lock); 2582 __acquire(&recv_cq->lock); 2583 } else { 2584 spin_lock(&recv_cq->lock); 2585 spin_lock_nested(&send_cq->lock, 2586 SINGLE_DEPTH_NESTING); 2587 } 2588 } else { 2589 spin_lock(&send_cq->lock); 2590 __acquire(&recv_cq->lock); 2591 } 2592 } else if (recv_cq) { 2593 spin_lock(&recv_cq->lock); 2594 __acquire(&send_cq->lock); 2595 } else { 2596 __acquire(&send_cq->lock); 2597 __acquire(&recv_cq->lock); 2598 } 2599 } 2600 2601 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2602 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2603 { 2604 if (send_cq) { 2605 if (recv_cq) { 2606 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2607 spin_unlock(&recv_cq->lock); 2608 spin_unlock(&send_cq->lock); 2609 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2610 __release(&recv_cq->lock); 2611 spin_unlock(&send_cq->lock); 2612 } else { 2613 spin_unlock(&send_cq->lock); 2614 spin_unlock(&recv_cq->lock); 2615 } 2616 } else { 2617 __release(&recv_cq->lock); 2618 spin_unlock(&send_cq->lock); 2619 } 2620 } else if (recv_cq) { 2621 __release(&send_cq->lock); 2622 spin_unlock(&recv_cq->lock); 2623 } else { 2624 __release(&recv_cq->lock); 2625 __release(&send_cq->lock); 2626 } 2627 } 2628 2629 static void get_cqs(enum ib_qp_type qp_type, 2630 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2631 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2632 { 2633 switch (qp_type) { 2634 case IB_QPT_XRC_TGT: 2635 *send_cq = NULL; 2636 *recv_cq = NULL; 2637 break; 2638 case MLX5_IB_QPT_REG_UMR: 2639 case IB_QPT_XRC_INI: 2640 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2641 *recv_cq = NULL; 2642 break; 2643 2644 case IB_QPT_SMI: 2645 case MLX5_IB_QPT_HW_GSI: 2646 case IB_QPT_RC: 2647 case IB_QPT_UC: 2648 case IB_QPT_UD: 2649 case IB_QPT_RAW_PACKET: 2650 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2651 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2652 break; 2653 default: 2654 *send_cq = NULL; 2655 *recv_cq = NULL; 2656 break; 2657 } 2658 } 2659 2660 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2661 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2662 u8 lag_tx_affinity); 2663 2664 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2665 struct ib_udata *udata) 2666 { 2667 struct mlx5_ib_cq *send_cq, *recv_cq; 2668 struct mlx5_ib_qp_base *base; 2669 unsigned long flags; 2670 int err; 2671 2672 if (qp->is_rss) { 2673 destroy_rss_raw_qp_tir(dev, qp); 2674 return; 2675 } 2676 2677 base = (qp->type == IB_QPT_RAW_PACKET || 2678 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2679 &qp->raw_packet_qp.rq.base : 2680 &qp->trans_qp.base; 2681 2682 if (qp->state != IB_QPS_RESET) { 2683 if (qp->type != IB_QPT_RAW_PACKET && 2684 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2685 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2686 NULL, &base->mqp, NULL); 2687 } else { 2688 struct mlx5_modify_raw_qp_param raw_qp_param = { 2689 .operation = MLX5_CMD_OP_2RST_QP 2690 }; 2691 2692 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2693 } 2694 if (err) 2695 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2696 base->mqp.qpn); 2697 } 2698 2699 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2700 &recv_cq); 2701 2702 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2703 mlx5_ib_lock_cqs(send_cq, recv_cq); 2704 /* del from lists under both locks above to protect reset flow paths */ 2705 list_del(&qp->qps_list); 2706 if (send_cq) 2707 list_del(&qp->cq_send_list); 2708 2709 if (recv_cq) 2710 list_del(&qp->cq_recv_list); 2711 2712 if (!udata) { 2713 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2714 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2715 if (send_cq != recv_cq) 2716 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2717 NULL); 2718 } 2719 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2720 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2721 2722 if (qp->type == IB_QPT_RAW_PACKET || 2723 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2724 destroy_raw_packet_qp(dev, qp); 2725 } else { 2726 err = mlx5_core_destroy_qp(dev, &base->mqp); 2727 if (err) 2728 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2729 base->mqp.qpn); 2730 } 2731 2732 destroy_qp(dev, qp, base, udata); 2733 } 2734 2735 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2736 struct mlx5_ib_qp *qp, 2737 struct mlx5_create_qp_params *params) 2738 { 2739 struct ib_qp_init_attr *attr = params->attr; 2740 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2741 u32 uidx = params->uidx; 2742 void *dctc; 2743 2744 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2745 return -EOPNOTSUPP; 2746 2747 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2748 if (!qp->dct.in) 2749 return -ENOMEM; 2750 2751 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2752 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2753 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2754 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2755 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2756 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2757 MLX5_SET(dctc, dctc, user_index, uidx); 2758 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2759 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2760 2761 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2762 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2763 2764 if (rcqe_sz == 128) 2765 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2766 } 2767 2768 qp->state = IB_QPS_RESET; 2769 return 0; 2770 } 2771 2772 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2773 enum ib_qp_type *type) 2774 { 2775 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2776 goto out; 2777 2778 switch (attr->qp_type) { 2779 case IB_QPT_XRC_TGT: 2780 case IB_QPT_XRC_INI: 2781 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2782 goto out; 2783 fallthrough; 2784 case IB_QPT_RC: 2785 case IB_QPT_UC: 2786 case IB_QPT_SMI: 2787 case MLX5_IB_QPT_HW_GSI: 2788 case IB_QPT_DRIVER: 2789 case IB_QPT_GSI: 2790 case IB_QPT_RAW_PACKET: 2791 case IB_QPT_UD: 2792 case MLX5_IB_QPT_REG_UMR: 2793 break; 2794 default: 2795 goto out; 2796 } 2797 2798 *type = attr->qp_type; 2799 return 0; 2800 2801 out: 2802 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2803 return -EOPNOTSUPP; 2804 } 2805 2806 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2807 struct ib_qp_init_attr *attr, 2808 struct ib_udata *udata) 2809 { 2810 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2811 udata, struct mlx5_ib_ucontext, ibucontext); 2812 2813 if (!udata) { 2814 /* Kernel create_qp callers */ 2815 if (attr->rwq_ind_tbl) 2816 return -EOPNOTSUPP; 2817 2818 switch (attr->qp_type) { 2819 case IB_QPT_RAW_PACKET: 2820 case IB_QPT_DRIVER: 2821 return -EOPNOTSUPP; 2822 default: 2823 return 0; 2824 } 2825 } 2826 2827 /* Userspace create_qp callers */ 2828 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2829 mlx5_ib_dbg(dev, 2830 "Raw Packet QP is only supported for CQE version > 0\n"); 2831 return -EINVAL; 2832 } 2833 2834 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2835 mlx5_ib_dbg(dev, 2836 "Wrong QP type %d for the RWQ indirect table\n", 2837 attr->qp_type); 2838 return -EINVAL; 2839 } 2840 2841 /* 2842 * We don't need to see this warning, it means that kernel code 2843 * missing ib_pd. Placed here to catch developer's mistakes. 2844 */ 2845 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2846 "There is a missing PD pointer assignment\n"); 2847 return 0; 2848 } 2849 2850 static bool get_dp_ooo_cap(struct mlx5_core_dev *mdev, enum ib_qp_type qp_type) 2851 { 2852 if (!MLX5_CAP_GEN_2(mdev, dp_ordering_force)) 2853 return false; 2854 2855 switch (qp_type) { 2856 case IB_QPT_RC: 2857 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc); 2858 case IB_QPT_XRC_INI: 2859 case IB_QPT_XRC_TGT: 2860 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc); 2861 case IB_QPT_UC: 2862 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc); 2863 case IB_QPT_UD: 2864 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud); 2865 case MLX5_IB_QPT_DCI: 2866 case MLX5_IB_QPT_DCT: 2867 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc); 2868 default: 2869 return false; 2870 } 2871 } 2872 2873 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2874 bool cond, struct mlx5_ib_qp *qp) 2875 { 2876 if (!(*flags & flag)) 2877 return; 2878 2879 if (cond) { 2880 qp->flags_en |= flag; 2881 *flags &= ~flag; 2882 return; 2883 } 2884 2885 switch (flag) { 2886 case MLX5_QP_FLAG_SCATTER_CQE: 2887 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2888 /* 2889 * We don't return error if these flags were provided, 2890 * and mlx5 doesn't have right capability. 2891 */ 2892 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2893 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2894 return; 2895 default: 2896 break; 2897 } 2898 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2899 } 2900 2901 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2902 void *ucmd, struct ib_qp_init_attr *attr) 2903 { 2904 struct mlx5_core_dev *mdev = dev->mdev; 2905 bool cond; 2906 int flags; 2907 2908 if (attr->rwq_ind_tbl) 2909 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2910 else 2911 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2912 2913 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2914 case MLX5_QP_FLAG_TYPE_DCI: 2915 qp->type = MLX5_IB_QPT_DCI; 2916 break; 2917 case MLX5_QP_FLAG_TYPE_DCT: 2918 qp->type = MLX5_IB_QPT_DCT; 2919 break; 2920 default: 2921 if (qp->type != IB_QPT_DRIVER) 2922 break; 2923 /* 2924 * It is IB_QPT_DRIVER and or no subtype or 2925 * wrong subtype were provided. 2926 */ 2927 return -EINVAL; 2928 } 2929 2930 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2931 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2932 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2933 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2934 qp); 2935 2936 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2937 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2938 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2939 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2940 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2941 2942 if (qp->type == IB_QPT_RAW_PACKET) { 2943 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2944 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2945 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2946 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2947 cond, qp); 2948 process_vendor_flag(dev, &flags, 2949 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2950 qp); 2951 process_vendor_flag(dev, &flags, 2952 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2953 qp); 2954 } 2955 2956 if (qp->type == IB_QPT_RC) 2957 process_vendor_flag(dev, &flags, 2958 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2959 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2960 2961 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2962 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2963 2964 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2965 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2966 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2967 if (attr->rwq_ind_tbl && cond) { 2968 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2969 cond); 2970 return -EINVAL; 2971 } 2972 2973 if (flags) 2974 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2975 2976 return (flags) ? -EINVAL : 0; 2977 } 2978 2979 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2980 bool cond, struct mlx5_ib_qp *qp) 2981 { 2982 if (!(*flags & flag)) 2983 return; 2984 2985 if (cond) { 2986 qp->flags |= flag; 2987 *flags &= ~flag; 2988 return; 2989 } 2990 2991 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2992 } 2993 2994 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2995 struct ib_qp_init_attr *attr) 2996 { 2997 enum ib_qp_type qp_type = qp->type; 2998 struct mlx5_core_dev *mdev = dev->mdev; 2999 int create_flags = attr->create_flags; 3000 bool cond; 3001 3002 if (qp_type == MLX5_IB_QPT_DCT) 3003 return (create_flags) ? -EINVAL : 0; 3004 3005 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 3006 return (create_flags) ? -EINVAL : 0; 3007 3008 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 3009 mlx5_get_flow_namespace(dev->mdev, 3010 MLX5_FLOW_NAMESPACE_BYPASS), 3011 qp); 3012 process_create_flag(dev, &create_flags, 3013 IB_QP_CREATE_INTEGRITY_EN, 3014 MLX5_CAP_GEN(mdev, sho), qp); 3015 process_create_flag(dev, &create_flags, 3016 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 3017 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 3018 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 3019 MLX5_CAP_GEN(mdev, cd), qp); 3020 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 3021 MLX5_CAP_GEN(mdev, cd), qp); 3022 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 3023 MLX5_CAP_GEN(mdev, cd), qp); 3024 3025 if (qp_type == IB_QPT_UD) { 3026 process_create_flag(dev, &create_flags, 3027 IB_QP_CREATE_IPOIB_UD_LSO, 3028 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 3029 qp); 3030 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 3031 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 3032 cond, qp); 3033 } 3034 3035 if (qp_type == IB_QPT_RAW_PACKET) { 3036 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3037 MLX5_CAP_ETH(mdev, scatter_fcs); 3038 process_create_flag(dev, &create_flags, 3039 IB_QP_CREATE_SCATTER_FCS, cond, qp); 3040 3041 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3042 MLX5_CAP_ETH(mdev, vlan_cap); 3043 process_create_flag(dev, &create_flags, 3044 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 3045 } 3046 3047 process_create_flag(dev, &create_flags, 3048 IB_QP_CREATE_PCI_WRITE_END_PADDING, 3049 MLX5_CAP_GEN(mdev, end_pad), qp); 3050 3051 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 3052 true, qp); 3053 3054 if (create_flags) { 3055 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 3056 create_flags); 3057 return -EOPNOTSUPP; 3058 } 3059 return 0; 3060 } 3061 3062 static int process_udata_size(struct mlx5_ib_dev *dev, 3063 struct mlx5_create_qp_params *params) 3064 { 3065 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 3066 struct ib_udata *udata = params->udata; 3067 size_t outlen = udata->outlen; 3068 size_t inlen = udata->inlen; 3069 3070 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 3071 params->ucmd_size = ucmd; 3072 if (!params->is_rss_raw) { 3073 /* User has old rdma-core, which doesn't support ECE */ 3074 size_t min_inlen = 3075 offsetof(struct mlx5_ib_create_qp, ece_options); 3076 3077 /* 3078 * We will check in check_ucmd_data() that user 3079 * cleared everything after inlen. 3080 */ 3081 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 3082 goto out; 3083 } 3084 3085 /* RSS RAW QP */ 3086 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 3087 return -EINVAL; 3088 3089 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 3090 return -EINVAL; 3091 3092 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 3093 params->ucmd_size = ucmd; 3094 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 3095 return -EINVAL; 3096 3097 params->inlen = min(ucmd, inlen); 3098 out: 3099 if (!params->inlen) 3100 mlx5_ib_dbg(dev, "udata is too small\n"); 3101 3102 return (params->inlen) ? 0 : -EINVAL; 3103 } 3104 3105 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 3106 struct mlx5_ib_qp *qp, 3107 struct mlx5_create_qp_params *params) 3108 { 3109 int err; 3110 3111 if (params->is_rss_raw) { 3112 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3113 goto out; 3114 } 3115 3116 switch (qp->type) { 3117 case MLX5_IB_QPT_DCT: 3118 err = create_dct(dev, pd, qp, params); 3119 break; 3120 case MLX5_IB_QPT_DCI: 3121 err = create_dci(dev, pd, qp, params); 3122 break; 3123 case IB_QPT_XRC_TGT: 3124 err = create_xrc_tgt_qp(dev, qp, params); 3125 break; 3126 case IB_QPT_GSI: 3127 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3128 break; 3129 case MLX5_IB_QPT_HW_GSI: 3130 rdma_restrack_no_track(&qp->ibqp.res); 3131 fallthrough; 3132 case MLX5_IB_QPT_REG_UMR: 3133 default: 3134 if (params->udata) 3135 err = create_user_qp(dev, pd, qp, params); 3136 else 3137 err = create_kernel_qp(dev, pd, qp, params); 3138 } 3139 3140 out: 3141 if (err) { 3142 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3143 return err; 3144 } 3145 3146 if (is_qp0(qp->type)) 3147 qp->ibqp.qp_num = 0; 3148 else if (is_qp1(qp->type)) 3149 qp->ibqp.qp_num = 1; 3150 else 3151 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3152 3153 mlx5_ib_dbg(dev, 3154 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3155 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3156 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3157 -1, 3158 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3159 -1, 3160 params->resp.ece_options); 3161 3162 return 0; 3163 } 3164 3165 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3166 struct ib_qp_init_attr *attr) 3167 { 3168 int ret = 0; 3169 3170 switch (qp->type) { 3171 case MLX5_IB_QPT_DCT: 3172 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3173 break; 3174 case MLX5_IB_QPT_DCI: 3175 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3176 -EINVAL : 3177 0; 3178 break; 3179 case IB_QPT_RAW_PACKET: 3180 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3181 break; 3182 default: 3183 break; 3184 } 3185 3186 if (ret) 3187 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3188 3189 return ret; 3190 } 3191 3192 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3193 struct mlx5_create_qp_params *params) 3194 { 3195 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3196 struct ib_udata *udata = params->udata; 3197 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3198 udata, struct mlx5_ib_ucontext, ibucontext); 3199 3200 if (params->is_rss_raw) 3201 return 0; 3202 3203 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3204 } 3205 3206 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3207 { 3208 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3209 3210 if (mqp->state == IB_QPS_RTR) { 3211 int err; 3212 3213 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3214 if (err) { 3215 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3216 return err; 3217 } 3218 } 3219 3220 kfree(mqp->dct.in); 3221 return 0; 3222 } 3223 3224 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3225 struct mlx5_create_qp_params *params) 3226 { 3227 struct ib_udata *udata = params->udata; 3228 size_t size, last; 3229 int ret; 3230 3231 if (params->is_rss_raw) 3232 /* 3233 * These QPs don't have "reserved" field in their 3234 * create_qp input struct, so their data is always valid. 3235 */ 3236 last = sizeof(struct mlx5_ib_create_qp_rss); 3237 else 3238 last = offsetof(struct mlx5_ib_create_qp, reserved); 3239 3240 if (udata->inlen <= last) 3241 return 0; 3242 3243 /* 3244 * User provides different create_qp structures based on the 3245 * flow and we need to know if he cleared memory after our 3246 * struct create_qp ends. 3247 */ 3248 size = udata->inlen - last; 3249 ret = ib_is_udata_cleared(params->udata, last, size); 3250 if (!ret) 3251 mlx5_ib_dbg( 3252 dev, 3253 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3254 udata->inlen, params->ucmd_size, last, size); 3255 return ret ? 0 : -EINVAL; 3256 } 3257 3258 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3259 struct ib_udata *udata) 3260 { 3261 struct mlx5_create_qp_params params = {}; 3262 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3263 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3264 struct ib_pd *pd = ibqp->pd; 3265 enum ib_qp_type type; 3266 int err; 3267 3268 err = mlx5_ib_dev_res_srq_init(dev); 3269 if (err) 3270 return err; 3271 3272 err = check_qp_type(dev, attr, &type); 3273 if (err) 3274 return err; 3275 3276 err = check_valid_flow(dev, pd, attr, udata); 3277 if (err) 3278 return err; 3279 3280 params.udata = udata; 3281 params.uidx = MLX5_IB_DEFAULT_UIDX; 3282 params.attr = attr; 3283 params.is_rss_raw = !!attr->rwq_ind_tbl; 3284 3285 if (udata) { 3286 err = process_udata_size(dev, ¶ms); 3287 if (err) 3288 return err; 3289 3290 err = check_ucmd_data(dev, ¶ms); 3291 if (err) 3292 return err; 3293 3294 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3295 if (!params.ucmd) 3296 return -ENOMEM; 3297 3298 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3299 if (err) 3300 goto free_ucmd; 3301 } 3302 3303 mutex_init(&qp->mutex); 3304 qp->type = type; 3305 if (udata) { 3306 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3307 if (err) 3308 goto free_ucmd; 3309 3310 err = get_qp_uidx(qp, ¶ms); 3311 if (err) 3312 goto free_ucmd; 3313 } 3314 err = process_create_flags(dev, qp, attr); 3315 if (err) 3316 goto free_ucmd; 3317 3318 err = check_qp_attr(dev, qp, attr); 3319 if (err) 3320 goto free_ucmd; 3321 3322 err = create_qp(dev, pd, qp, ¶ms); 3323 if (err) 3324 goto free_ucmd; 3325 3326 kfree(params.ucmd); 3327 params.ucmd = NULL; 3328 3329 if (udata) 3330 /* 3331 * It is safe to copy response for all user create QP flows, 3332 * including MLX5_IB_QPT_DCT, which doesn't need it. 3333 * In that case, resp will be filled with zeros. 3334 */ 3335 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3336 if (err) 3337 goto destroy_qp; 3338 3339 return 0; 3340 3341 destroy_qp: 3342 switch (qp->type) { 3343 case MLX5_IB_QPT_DCT: 3344 mlx5_ib_destroy_dct(qp); 3345 break; 3346 case IB_QPT_GSI: 3347 mlx5_ib_destroy_gsi(qp); 3348 break; 3349 default: 3350 destroy_qp_common(dev, qp, udata); 3351 } 3352 3353 free_ucmd: 3354 kfree(params.ucmd); 3355 return err; 3356 } 3357 3358 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3359 { 3360 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3361 struct mlx5_ib_qp *mqp = to_mqp(qp); 3362 3363 if (mqp->type == IB_QPT_GSI) 3364 return mlx5_ib_destroy_gsi(mqp); 3365 3366 if (mqp->type == MLX5_IB_QPT_DCT) 3367 return mlx5_ib_destroy_dct(mqp); 3368 3369 destroy_qp_common(dev, mqp, udata); 3370 return 0; 3371 } 3372 3373 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3374 const struct ib_qp_attr *attr, int attr_mask, 3375 void *qpc) 3376 { 3377 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3378 u8 dest_rd_atomic; 3379 u32 access_flags; 3380 3381 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3382 dest_rd_atomic = attr->max_dest_rd_atomic; 3383 else 3384 dest_rd_atomic = qp->trans_qp.resp_depth; 3385 3386 if (attr_mask & IB_QP_ACCESS_FLAGS) 3387 access_flags = attr->qp_access_flags; 3388 else 3389 access_flags = qp->trans_qp.atomic_rd_en; 3390 3391 if (!dest_rd_atomic) 3392 access_flags &= IB_ACCESS_REMOTE_WRITE; 3393 3394 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3395 3396 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3397 int atomic_mode; 3398 3399 atomic_mode = get_atomic_mode(dev, qp); 3400 if (atomic_mode < 0) 3401 return -EOPNOTSUPP; 3402 3403 MLX5_SET(qpc, qpc, rae, 1); 3404 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3405 } 3406 3407 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3408 return 0; 3409 } 3410 3411 enum { 3412 MLX5_PATH_FLAG_FL = 1 << 0, 3413 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3414 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3415 }; 3416 3417 static int mlx5_to_ib_rate_map(u8 rate) 3418 { 3419 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3420 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3421 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3422 IB_RATE_400_GBPS }; 3423 3424 if (rate < ARRAY_SIZE(rates)) 3425 return rates[rate]; 3426 3427 return rate - MLX5_STAT_RATE_OFFSET; 3428 } 3429 3430 static int ib_to_mlx5_rate_map(u8 rate) 3431 { 3432 switch (rate) { 3433 case IB_RATE_PORT_CURRENT: 3434 return 0; 3435 case IB_RATE_56_GBPS: 3436 return 1; 3437 case IB_RATE_25_GBPS: 3438 return 2; 3439 case IB_RATE_100_GBPS: 3440 return 3; 3441 case IB_RATE_200_GBPS: 3442 return 4; 3443 case IB_RATE_50_GBPS: 3444 return 5; 3445 case IB_RATE_400_GBPS: 3446 return 6; 3447 default: 3448 return rate + MLX5_STAT_RATE_OFFSET; 3449 } 3450 3451 return 0; 3452 } 3453 3454 int mlx5r_ib_rate(struct mlx5_ib_dev *dev, u8 rate) 3455 { 3456 u32 stat_rate_support; 3457 3458 if (rate == IB_RATE_PORT_CURRENT || rate == IB_RATE_800_GBPS || 3459 rate == IB_RATE_1600_GBPS) 3460 return 0; 3461 3462 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_1600_GBPS) 3463 return -EINVAL; 3464 3465 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3466 while (rate != IB_RATE_PORT_CURRENT && 3467 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3468 --rate; 3469 3470 return ib_to_mlx5_rate_map(rate); 3471 } 3472 3473 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3474 struct mlx5_ib_sq *sq, u8 sl, 3475 struct ib_pd *pd) 3476 { 3477 void *in; 3478 void *tisc; 3479 int inlen; 3480 int err; 3481 3482 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3483 in = kvzalloc(inlen, GFP_KERNEL); 3484 if (!in) 3485 return -ENOMEM; 3486 3487 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3488 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3489 3490 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3491 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3492 3493 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3494 3495 kvfree(in); 3496 3497 return err; 3498 } 3499 3500 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3501 struct mlx5_ib_sq *sq, u8 tx_affinity, 3502 struct ib_pd *pd) 3503 { 3504 void *in; 3505 void *tisc; 3506 int inlen; 3507 int err; 3508 3509 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3510 in = kvzalloc(inlen, GFP_KERNEL); 3511 if (!in) 3512 return -ENOMEM; 3513 3514 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3515 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3516 3517 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3518 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3519 3520 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3521 3522 kvfree(in); 3523 3524 return err; 3525 } 3526 3527 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3528 u32 lqpn, u32 rqpn) 3529 3530 { 3531 u32 fl = ah->grh.flow_label; 3532 3533 if (!fl) 3534 fl = rdma_calc_flow_label(lqpn, rqpn); 3535 3536 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3537 } 3538 3539 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3540 const struct rdma_ah_attr *ah, void *path, u8 port, 3541 int attr_mask, u32 path_flags, 3542 const struct ib_qp_attr *attr, bool alt) 3543 { 3544 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3545 int err; 3546 enum ib_gid_type gid_type; 3547 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3548 u8 sl = rdma_ah_get_sl(ah); 3549 3550 if (attr_mask & IB_QP_PKEY_INDEX) 3551 MLX5_SET(ads, path, pkey_index, 3552 alt ? attr->alt_pkey_index : attr->pkey_index); 3553 3554 if (ah_flags & IB_AH_GRH) { 3555 const struct ib_port_immutable *immutable; 3556 3557 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3558 if (grh->sgid_index >= immutable->gid_tbl_len) { 3559 pr_err("sgid_index (%u) too large. max is %d\n", 3560 grh->sgid_index, 3561 immutable->gid_tbl_len); 3562 return -EINVAL; 3563 } 3564 } 3565 3566 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3567 if (!(ah_flags & IB_AH_GRH)) 3568 return -EINVAL; 3569 3570 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3571 ah->roce.dmac); 3572 if ((qp->type == IB_QPT_RC || 3573 qp->type == IB_QPT_UC || 3574 qp->type == IB_QPT_XRC_INI || 3575 qp->type == IB_QPT_XRC_TGT) && 3576 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3577 (attr_mask & IB_QP_DEST_QPN)) 3578 mlx5_set_path_udp_sport(path, ah, 3579 qp->ibqp.qp_num, 3580 attr->dest_qp_num); 3581 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3582 gid_type = ah->grh.sgid_attr->gid_type; 3583 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3584 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3585 } else { 3586 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3587 MLX5_SET(ads, path, free_ar, 3588 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3589 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3590 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3591 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3592 MLX5_SET(ads, path, sl, sl); 3593 } 3594 3595 if (ah_flags & IB_AH_GRH) { 3596 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3597 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3598 MLX5_SET(ads, path, tclass, grh->traffic_class); 3599 MLX5_SET(ads, path, flow_label, grh->flow_label); 3600 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3601 sizeof(grh->dgid.raw)); 3602 } 3603 3604 err = mlx5r_ib_rate(dev, rdma_ah_get_static_rate(ah)); 3605 if (err < 0) 3606 return err; 3607 MLX5_SET(ads, path, stat_rate, err); 3608 MLX5_SET(ads, path, vhca_port_num, port); 3609 3610 if (attr_mask & IB_QP_TIMEOUT) 3611 MLX5_SET(ads, path, ack_timeout, 3612 alt ? attr->alt_timeout : attr->timeout); 3613 3614 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3615 return modify_raw_packet_eth_prio(dev->mdev, 3616 &qp->raw_packet_qp.sq, 3617 sl & 0xf, qp->ibqp.pd); 3618 3619 return 0; 3620 } 3621 3622 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3623 [MLX5_QP_STATE_INIT] = { 3624 [MLX5_QP_STATE_INIT] = { 3625 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3626 MLX5_QP_OPTPAR_RAE | 3627 MLX5_QP_OPTPAR_RWE | 3628 MLX5_QP_OPTPAR_PKEY_INDEX | 3629 MLX5_QP_OPTPAR_PRI_PORT | 3630 MLX5_QP_OPTPAR_LAG_TX_AFF, 3631 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3632 MLX5_QP_OPTPAR_PKEY_INDEX | 3633 MLX5_QP_OPTPAR_PRI_PORT | 3634 MLX5_QP_OPTPAR_LAG_TX_AFF, 3635 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3636 MLX5_QP_OPTPAR_Q_KEY | 3637 MLX5_QP_OPTPAR_PRI_PORT, 3638 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3639 MLX5_QP_OPTPAR_RAE | 3640 MLX5_QP_OPTPAR_RWE | 3641 MLX5_QP_OPTPAR_PKEY_INDEX | 3642 MLX5_QP_OPTPAR_PRI_PORT | 3643 MLX5_QP_OPTPAR_LAG_TX_AFF, 3644 }, 3645 [MLX5_QP_STATE_RTR] = { 3646 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3647 MLX5_QP_OPTPAR_RRE | 3648 MLX5_QP_OPTPAR_RAE | 3649 MLX5_QP_OPTPAR_RWE | 3650 MLX5_QP_OPTPAR_PKEY_INDEX | 3651 MLX5_QP_OPTPAR_LAG_TX_AFF, 3652 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3653 MLX5_QP_OPTPAR_RWE | 3654 MLX5_QP_OPTPAR_PKEY_INDEX | 3655 MLX5_QP_OPTPAR_LAG_TX_AFF, 3656 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3657 MLX5_QP_OPTPAR_Q_KEY, 3658 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3659 MLX5_QP_OPTPAR_Q_KEY, 3660 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3661 MLX5_QP_OPTPAR_RRE | 3662 MLX5_QP_OPTPAR_RAE | 3663 MLX5_QP_OPTPAR_RWE | 3664 MLX5_QP_OPTPAR_PKEY_INDEX | 3665 MLX5_QP_OPTPAR_LAG_TX_AFF, 3666 }, 3667 }, 3668 [MLX5_QP_STATE_RTR] = { 3669 [MLX5_QP_STATE_RTS] = { 3670 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3671 MLX5_QP_OPTPAR_RRE | 3672 MLX5_QP_OPTPAR_RAE | 3673 MLX5_QP_OPTPAR_RWE | 3674 MLX5_QP_OPTPAR_PM_STATE | 3675 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3676 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3677 MLX5_QP_OPTPAR_RWE | 3678 MLX5_QP_OPTPAR_PM_STATE, 3679 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3680 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3681 MLX5_QP_OPTPAR_RRE | 3682 MLX5_QP_OPTPAR_RAE | 3683 MLX5_QP_OPTPAR_RWE | 3684 MLX5_QP_OPTPAR_PM_STATE | 3685 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3686 }, 3687 }, 3688 [MLX5_QP_STATE_RTS] = { 3689 [MLX5_QP_STATE_RTS] = { 3690 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3691 MLX5_QP_OPTPAR_RAE | 3692 MLX5_QP_OPTPAR_RWE | 3693 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3694 MLX5_QP_OPTPAR_PM_STATE | 3695 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3696 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3697 MLX5_QP_OPTPAR_PM_STATE | 3698 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3699 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3700 MLX5_QP_OPTPAR_SRQN | 3701 MLX5_QP_OPTPAR_CQN_RCV, 3702 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3703 MLX5_QP_OPTPAR_RAE | 3704 MLX5_QP_OPTPAR_RWE | 3705 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3706 MLX5_QP_OPTPAR_PM_STATE | 3707 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3708 }, 3709 }, 3710 [MLX5_QP_STATE_SQER] = { 3711 [MLX5_QP_STATE_RTS] = { 3712 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3713 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3714 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3715 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3716 MLX5_QP_OPTPAR_RWE | 3717 MLX5_QP_OPTPAR_RAE | 3718 MLX5_QP_OPTPAR_RRE, 3719 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3720 MLX5_QP_OPTPAR_RWE | 3721 MLX5_QP_OPTPAR_RAE | 3722 MLX5_QP_OPTPAR_RRE, 3723 }, 3724 }, 3725 [MLX5_QP_STATE_SQD] = { 3726 [MLX5_QP_STATE_RTS] = { 3727 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3728 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3729 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3730 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3731 MLX5_QP_OPTPAR_RWE | 3732 MLX5_QP_OPTPAR_RAE | 3733 MLX5_QP_OPTPAR_RRE, 3734 }, 3735 }, 3736 }; 3737 3738 static int ib_nr_to_mlx5_nr(int ib_mask) 3739 { 3740 switch (ib_mask) { 3741 case IB_QP_STATE: 3742 return 0; 3743 case IB_QP_CUR_STATE: 3744 return 0; 3745 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3746 return 0; 3747 case IB_QP_ACCESS_FLAGS: 3748 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3749 MLX5_QP_OPTPAR_RAE; 3750 case IB_QP_PKEY_INDEX: 3751 return MLX5_QP_OPTPAR_PKEY_INDEX; 3752 case IB_QP_PORT: 3753 return MLX5_QP_OPTPAR_PRI_PORT; 3754 case IB_QP_QKEY: 3755 return MLX5_QP_OPTPAR_Q_KEY; 3756 case IB_QP_AV: 3757 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3758 MLX5_QP_OPTPAR_PRI_PORT; 3759 case IB_QP_PATH_MTU: 3760 return 0; 3761 case IB_QP_TIMEOUT: 3762 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3763 case IB_QP_RETRY_CNT: 3764 return MLX5_QP_OPTPAR_RETRY_COUNT; 3765 case IB_QP_RNR_RETRY: 3766 return MLX5_QP_OPTPAR_RNR_RETRY; 3767 case IB_QP_RQ_PSN: 3768 return 0; 3769 case IB_QP_MAX_QP_RD_ATOMIC: 3770 return MLX5_QP_OPTPAR_SRA_MAX; 3771 case IB_QP_ALT_PATH: 3772 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3773 case IB_QP_MIN_RNR_TIMER: 3774 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3775 case IB_QP_SQ_PSN: 3776 return 0; 3777 case IB_QP_MAX_DEST_RD_ATOMIC: 3778 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3779 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3780 case IB_QP_PATH_MIG_STATE: 3781 return MLX5_QP_OPTPAR_PM_STATE; 3782 case IB_QP_CAP: 3783 return 0; 3784 case IB_QP_DEST_QPN: 3785 return 0; 3786 } 3787 return 0; 3788 } 3789 3790 static int ib_mask_to_mlx5_opt(int ib_mask) 3791 { 3792 int result = 0; 3793 int i; 3794 3795 for (i = 0; i < 8 * sizeof(int); i++) { 3796 if ((1 << i) & ib_mask) 3797 result |= ib_nr_to_mlx5_nr(1 << i); 3798 } 3799 3800 return result; 3801 } 3802 3803 static int modify_raw_packet_qp_rq( 3804 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3805 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3806 { 3807 void *in; 3808 void *rqc; 3809 int inlen; 3810 int err; 3811 3812 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3813 in = kvzalloc(inlen, GFP_KERNEL); 3814 if (!in) 3815 return -ENOMEM; 3816 3817 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3818 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3819 3820 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3821 MLX5_SET(rqc, rqc, state, new_state); 3822 3823 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3824 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3825 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3826 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3827 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3828 } else 3829 dev_info_once( 3830 &dev->ib_dev.dev, 3831 "RAW PACKET QP counters are not supported on current FW\n"); 3832 } 3833 3834 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3835 if (err) 3836 goto out; 3837 3838 rq->state = new_state; 3839 3840 out: 3841 kvfree(in); 3842 return err; 3843 } 3844 3845 static int modify_raw_packet_qp_sq( 3846 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3847 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3848 { 3849 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3850 struct mlx5_rate_limit old_rl = ibqp->rl; 3851 struct mlx5_rate_limit new_rl = old_rl; 3852 bool new_rate_added = false; 3853 u16 rl_index = 0; 3854 void *in; 3855 void *sqc; 3856 int inlen; 3857 int err; 3858 3859 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3860 in = kvzalloc(inlen, GFP_KERNEL); 3861 if (!in) 3862 return -ENOMEM; 3863 3864 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3865 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3866 3867 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3868 MLX5_SET(sqc, sqc, state, new_state); 3869 3870 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3871 if (new_state != MLX5_SQC_STATE_RDY) 3872 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3873 __func__); 3874 else 3875 new_rl = raw_qp_param->rl; 3876 } 3877 3878 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3879 if (new_rl.rate) { 3880 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3881 if (err) { 3882 pr_err("Failed configuring rate limit(err %d): \ 3883 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3884 err, new_rl.rate, new_rl.max_burst_sz, 3885 new_rl.typical_pkt_sz); 3886 3887 goto out; 3888 } 3889 new_rate_added = true; 3890 } 3891 3892 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3893 /* index 0 means no limit */ 3894 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3895 } 3896 3897 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3898 if (err) { 3899 /* Remove new rate from table if failed */ 3900 if (new_rate_added) 3901 mlx5_rl_remove_rate(dev, &new_rl); 3902 goto out; 3903 } 3904 3905 /* Only remove the old rate after new rate was set */ 3906 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3907 (new_state != MLX5_SQC_STATE_RDY)) { 3908 mlx5_rl_remove_rate(dev, &old_rl); 3909 if (new_state != MLX5_SQC_STATE_RDY) 3910 memset(&new_rl, 0, sizeof(new_rl)); 3911 } 3912 3913 ibqp->rl = new_rl; 3914 sq->state = new_state; 3915 3916 out: 3917 kvfree(in); 3918 return err; 3919 } 3920 3921 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3922 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3923 u8 tx_affinity) 3924 { 3925 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3926 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3927 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3928 int modify_rq = !!qp->rq.wqe_cnt; 3929 int modify_sq = !!qp->sq.wqe_cnt; 3930 int rq_state; 3931 int sq_state; 3932 int err; 3933 3934 switch (raw_qp_param->operation) { 3935 case MLX5_CMD_OP_RST2INIT_QP: 3936 rq_state = MLX5_RQC_STATE_RDY; 3937 sq_state = MLX5_SQC_STATE_RST; 3938 break; 3939 case MLX5_CMD_OP_2ERR_QP: 3940 rq_state = MLX5_RQC_STATE_ERR; 3941 sq_state = MLX5_SQC_STATE_ERR; 3942 break; 3943 case MLX5_CMD_OP_2RST_QP: 3944 rq_state = MLX5_RQC_STATE_RST; 3945 sq_state = MLX5_SQC_STATE_RST; 3946 break; 3947 case MLX5_CMD_OP_RTR2RTS_QP: 3948 case MLX5_CMD_OP_RTS2RTS_QP: 3949 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3950 return -EINVAL; 3951 3952 modify_rq = 0; 3953 sq_state = MLX5_SQC_STATE_RDY; 3954 break; 3955 case MLX5_CMD_OP_INIT2INIT_QP: 3956 case MLX5_CMD_OP_INIT2RTR_QP: 3957 if (raw_qp_param->set_mask) 3958 return -EINVAL; 3959 else 3960 return 0; 3961 default: 3962 WARN_ON(1); 3963 return -EINVAL; 3964 } 3965 3966 if (modify_rq) { 3967 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3968 qp->ibqp.pd); 3969 if (err) 3970 return err; 3971 } 3972 3973 if (modify_sq) { 3974 struct mlx5_flow_handle *flow_rule; 3975 3976 if (tx_affinity) { 3977 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3978 tx_affinity, 3979 qp->ibqp.pd); 3980 if (err) 3981 return err; 3982 } 3983 3984 flow_rule = create_flow_rule_vport_sq(dev, sq, 3985 raw_qp_param->port); 3986 if (IS_ERR(flow_rule)) 3987 return PTR_ERR(flow_rule); 3988 3989 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3990 raw_qp_param, qp->ibqp.pd); 3991 if (err) { 3992 if (flow_rule) 3993 mlx5_del_flow_rules(flow_rule); 3994 return err; 3995 } 3996 3997 if (flow_rule) { 3998 destroy_flow_rule_vport_sq(sq); 3999 sq->flow_rule = flow_rule; 4000 } 4001 4002 return err; 4003 } 4004 4005 return 0; 4006 } 4007 4008 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 4009 struct ib_udata *udata) 4010 { 4011 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4012 udata, struct mlx5_ib_ucontext, ibucontext); 4013 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4014 atomic_t *tx_port_affinity; 4015 4016 if (ucontext) 4017 tx_port_affinity = &ucontext->tx_port_affinity; 4018 else 4019 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 4020 4021 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 4022 (dev->lag_active ? dev->lag_ports : MLX5_CAP_GEN(dev->mdev, num_lag_ports)) + 1; 4023 } 4024 4025 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 4026 { 4027 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 4028 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 4029 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 4030 (qp->type == MLX5_IB_QPT_DCI)) 4031 return true; 4032 return false; 4033 } 4034 4035 static unsigned int get_tx_affinity(struct ib_qp *qp, 4036 const struct ib_qp_attr *attr, 4037 int attr_mask, u8 init, 4038 struct ib_udata *udata) 4039 { 4040 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4041 udata, struct mlx5_ib_ucontext, ibucontext); 4042 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4043 struct mlx5_ib_qp *mqp = to_mqp(qp); 4044 struct mlx5_ib_qp_base *qp_base; 4045 unsigned int tx_affinity; 4046 4047 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 4048 qp_supports_affinity(mqp))) 4049 return 0; 4050 4051 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4052 tx_affinity = mqp->gsi_lag_port; 4053 else if (init) 4054 tx_affinity = get_tx_affinity_rr(dev, udata); 4055 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 4056 tx_affinity = 4057 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 4058 else 4059 return 0; 4060 4061 qp_base = &mqp->trans_qp.base; 4062 if (ucontext) 4063 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 4064 tx_affinity, qp_base->mqp.qpn, ucontext); 4065 else 4066 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 4067 tx_affinity, qp_base->mqp.qpn); 4068 return tx_affinity; 4069 } 4070 4071 static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id, 4072 struct mlx5_core_dev *mdev) 4073 { 4074 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4075 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4076 u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; 4077 void *rqc; 4078 4079 if (!qp->rq.wqe_cnt) 4080 return 0; 4081 4082 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 4083 MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid); 4084 4085 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4086 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 4087 4088 MLX5_SET64(modify_rq_in, in, modify_bitmask, 4089 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 4090 MLX5_SET(rqc, rqc, counter_set_id, set_id); 4091 4092 return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in); 4093 } 4094 4095 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4096 struct rdma_counter *counter) 4097 { 4098 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4099 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 4100 struct mlx5_ib_qp *mqp = to_mqp(qp); 4101 struct mlx5_ib_qp_base *base; 4102 u32 set_id; 4103 u32 *qpc; 4104 4105 if (counter) 4106 set_id = counter->id; 4107 else 4108 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4109 4110 if (mqp->type == IB_QPT_RAW_PACKET) 4111 return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev); 4112 4113 base = &mqp->trans_qp.base; 4114 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 4115 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 4116 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 4117 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 4118 MLX5_QP_OPTPAR_COUNTER_SET_ID); 4119 4120 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 4121 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4122 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 4123 } 4124 4125 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 4126 const struct ib_qp_attr *attr, int attr_mask, 4127 enum ib_qp_state cur_state, 4128 enum ib_qp_state new_state, 4129 const struct mlx5_ib_modify_qp *ucmd, 4130 struct mlx5_ib_modify_qp_resp *resp, 4131 struct ib_udata *udata) 4132 { 4133 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 4134 [MLX5_QP_STATE_RST] = { 4135 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4136 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4137 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 4138 }, 4139 [MLX5_QP_STATE_INIT] = { 4140 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4141 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4142 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4143 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4144 }, 4145 [MLX5_QP_STATE_RTR] = { 4146 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4147 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4148 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4149 }, 4150 [MLX5_QP_STATE_RTS] = { 4151 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4152 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4153 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4154 }, 4155 [MLX5_QP_STATE_SQD] = { 4156 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4157 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4158 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4159 }, 4160 [MLX5_QP_STATE_SQER] = { 4161 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4162 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4163 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4164 }, 4165 [MLX5_QP_STATE_ERR] = { 4166 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4167 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4168 } 4169 }; 4170 4171 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4172 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4173 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4174 struct mlx5_ib_cq *send_cq, *recv_cq; 4175 struct mlx5_ib_pd *pd; 4176 enum mlx5_qp_state mlx5_cur, mlx5_new; 4177 void *qpc, *pri_path, *alt_path; 4178 enum mlx5_qp_optpar optpar = 0; 4179 u32 set_id = 0; 4180 int mlx5_st; 4181 int err; 4182 u16 op; 4183 u8 tx_affinity = 0; 4184 4185 mlx5_st = to_mlx5_st(qp->type); 4186 if (mlx5_st < 0) 4187 return -EINVAL; 4188 4189 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4190 if (!qpc) 4191 return -ENOMEM; 4192 4193 pd = to_mpd(qp->ibqp.pd); 4194 MLX5_SET(qpc, qpc, st, mlx5_st); 4195 4196 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4197 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4198 } else { 4199 switch (attr->path_mig_state) { 4200 case IB_MIG_MIGRATED: 4201 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4202 break; 4203 case IB_MIG_REARM: 4204 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4205 break; 4206 case IB_MIG_ARMED: 4207 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4208 break; 4209 } 4210 } 4211 4212 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4213 cur_state == IB_QPS_RESET && 4214 new_state == IB_QPS_INIT, udata); 4215 4216 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4217 if (tx_affinity && new_state == IB_QPS_RTR && 4218 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4219 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4220 4221 if (is_sqp(qp->type)) { 4222 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4223 MLX5_SET(qpc, qpc, log_msg_max, 8); 4224 } else if ((qp->type == IB_QPT_UD && 4225 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4226 qp->type == MLX5_IB_QPT_REG_UMR) { 4227 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4228 MLX5_SET(qpc, qpc, log_msg_max, 12); 4229 } else if (attr_mask & IB_QP_PATH_MTU) { 4230 if (attr->path_mtu < IB_MTU_256 || 4231 attr->path_mtu > IB_MTU_4096) { 4232 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4233 err = -EINVAL; 4234 goto out; 4235 } 4236 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4237 MLX5_SET(qpc, qpc, log_msg_max, 4238 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4239 } 4240 4241 if (attr_mask & IB_QP_DEST_QPN) 4242 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4243 4244 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4245 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4246 4247 if (attr_mask & IB_QP_PKEY_INDEX) 4248 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4249 4250 /* todo implement counter_index functionality */ 4251 4252 if (dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI && is_qp0(qp->type)) { 4253 MLX5_SET(ads, pri_path, vhca_port_num, 4254 smi_to_native_portnum(dev, qp->port)); 4255 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) 4256 MLX5_SET(ads, pri_path, plane_index, qp->port); 4257 } else if (is_sqp(qp->type)) 4258 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4259 4260 if (attr_mask & IB_QP_PORT) 4261 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4262 4263 if (attr_mask & IB_QP_AV) { 4264 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4265 attr_mask & IB_QP_PORT ? attr->port_num : 4266 qp->port, 4267 attr_mask, 0, attr, false); 4268 if (err) 4269 goto out; 4270 } 4271 4272 if (attr_mask & IB_QP_TIMEOUT) 4273 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4274 4275 if (attr_mask & IB_QP_ALT_PATH) { 4276 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4277 attr->alt_port_num, 4278 attr_mask | IB_QP_PKEY_INDEX | 4279 IB_QP_TIMEOUT, 4280 0, attr, true); 4281 if (err) 4282 goto out; 4283 } 4284 4285 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4286 &send_cq, &recv_cq); 4287 4288 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4289 if (send_cq) 4290 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4291 if (recv_cq) 4292 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4293 4294 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4295 4296 if (attr_mask & IB_QP_RNR_RETRY) 4297 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4298 4299 if (attr_mask & IB_QP_RETRY_CNT) 4300 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4301 4302 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4303 MLX5_SET(qpc, qpc, log_sra_max, fls(attr->max_rd_atomic - 1)); 4304 4305 if (attr_mask & IB_QP_SQ_PSN) 4306 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4307 4308 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4309 MLX5_SET(qpc, qpc, log_rra_max, 4310 fls(attr->max_dest_rd_atomic - 1)); 4311 4312 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4313 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4314 if (err) 4315 goto out; 4316 } 4317 4318 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4319 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4320 4321 if (attr_mask & IB_QP_RQ_PSN) 4322 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4323 4324 if (attr_mask & IB_QP_QKEY) 4325 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4326 4327 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4328 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4329 4330 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4331 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4332 qp->port) - 1; 4333 4334 /* Underlay port should be used - index 0 function per port */ 4335 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4336 port_num = 0; 4337 4338 if (ibqp->counter) 4339 set_id = ibqp->counter->id; 4340 else 4341 set_id = mlx5_ib_get_counters_id(dev, port_num); 4342 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4343 } 4344 4345 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4346 MLX5_SET(qpc, qpc, rlky, 1); 4347 4348 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4349 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4350 4351 if (qp->is_ooo_rq && cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4352 MLX5_SET(qpc, qpc, dp_ordering_1, 1); 4353 MLX5_SET(qpc, qpc, dp_ordering_force, 1); 4354 } 4355 4356 mlx5_cur = to_mlx5_state(cur_state); 4357 mlx5_new = to_mlx5_state(new_state); 4358 4359 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4360 !optab[mlx5_cur][mlx5_new]) { 4361 err = -EINVAL; 4362 goto out; 4363 } 4364 4365 op = optab[mlx5_cur][mlx5_new]; 4366 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4367 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4368 4369 if (attr_mask & IB_QP_RATE_LIMIT && qp->type != IB_QPT_RAW_PACKET) { 4370 err = -EOPNOTSUPP; 4371 goto out; 4372 } 4373 4374 if (qp->type == IB_QPT_RAW_PACKET || 4375 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4376 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4377 4378 raw_qp_param.operation = op; 4379 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4380 raw_qp_param.rq_q_ctr_id = set_id; 4381 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4382 } 4383 4384 if (attr_mask & IB_QP_PORT) 4385 raw_qp_param.port = attr->port_num; 4386 4387 if (attr_mask & IB_QP_RATE_LIMIT) { 4388 raw_qp_param.rl.rate = attr->rate_limit; 4389 4390 if (ucmd->burst_info.max_burst_sz) { 4391 if (attr->rate_limit && 4392 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4393 raw_qp_param.rl.max_burst_sz = 4394 ucmd->burst_info.max_burst_sz; 4395 } else { 4396 err = -EINVAL; 4397 goto out; 4398 } 4399 } 4400 4401 if (ucmd->burst_info.typical_pkt_sz) { 4402 if (attr->rate_limit && 4403 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4404 raw_qp_param.rl.typical_pkt_sz = 4405 ucmd->burst_info.typical_pkt_sz; 4406 } else { 4407 err = -EINVAL; 4408 goto out; 4409 } 4410 } 4411 4412 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4413 } 4414 4415 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4416 } else { 4417 if (udata) { 4418 /* For the kernel flows, the resp will stay zero */ 4419 resp->ece_options = 4420 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4421 ucmd->ece_options : 0; 4422 resp->response_length = sizeof(*resp); 4423 } 4424 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4425 &resp->ece_options); 4426 } 4427 4428 if (err) 4429 goto out; 4430 4431 qp->state = new_state; 4432 4433 if (attr_mask & IB_QP_ACCESS_FLAGS) 4434 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4435 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4436 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4437 if (attr_mask & IB_QP_PORT) 4438 qp->port = attr->port_num; 4439 if (attr_mask & IB_QP_ALT_PATH) 4440 qp->trans_qp.alt_port = attr->alt_port_num; 4441 4442 /* 4443 * If we moved a kernel QP to RESET, clean up all old CQ 4444 * entries and reinitialize the QP. 4445 */ 4446 if (new_state == IB_QPS_RESET && 4447 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4448 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4449 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4450 if (send_cq != recv_cq) 4451 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4452 4453 qp->rq.head = 0; 4454 qp->rq.tail = 0; 4455 qp->sq.head = 0; 4456 qp->sq.tail = 0; 4457 qp->sq.cur_post = 0; 4458 if (qp->sq.wqe_cnt) 4459 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4460 qp->sq.last_poll = 0; 4461 qp->db.db[MLX5_RCV_DBR] = 0; 4462 qp->db.db[MLX5_SND_DBR] = 0; 4463 } 4464 4465 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4466 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4467 if (!err) 4468 qp->counter_pending = 0; 4469 } 4470 4471 out: 4472 kfree(qpc); 4473 return err; 4474 } 4475 4476 static inline bool is_valid_mask(int mask, int req, int opt) 4477 { 4478 if ((mask & req) != req) 4479 return false; 4480 4481 if (mask & ~(req | opt)) 4482 return false; 4483 4484 return true; 4485 } 4486 4487 /* check valid transition for driver QP types 4488 * for now the only QP type that this function supports is DCI 4489 */ 4490 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4491 enum ib_qp_attr_mask attr_mask) 4492 { 4493 int req = IB_QP_STATE; 4494 int opt = 0; 4495 4496 if (new_state == IB_QPS_RESET) { 4497 return is_valid_mask(attr_mask, req, opt); 4498 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4499 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4500 return is_valid_mask(attr_mask, req, opt); 4501 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4502 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4503 return is_valid_mask(attr_mask, req, opt); 4504 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4505 req |= IB_QP_PATH_MTU; 4506 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4507 return is_valid_mask(attr_mask, req, opt); 4508 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4509 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4510 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4511 opt = IB_QP_MIN_RNR_TIMER; 4512 return is_valid_mask(attr_mask, req, opt); 4513 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4514 opt = IB_QP_MIN_RNR_TIMER; 4515 return is_valid_mask(attr_mask, req, opt); 4516 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4517 return is_valid_mask(attr_mask, req, opt); 4518 } 4519 return false; 4520 } 4521 4522 /* mlx5_ib_modify_dct: modify a DCT QP 4523 * valid transitions are: 4524 * RESET to INIT: must set access_flags, pkey_index and port 4525 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4526 * mtu, gid_index and hop_limit 4527 * Other transitions and attributes are illegal 4528 */ 4529 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4530 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4531 struct ib_udata *udata) 4532 { 4533 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4534 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4535 enum ib_qp_state cur_state, new_state; 4536 int required = IB_QP_STATE; 4537 void *dctc; 4538 int err; 4539 4540 if (!(attr_mask & IB_QP_STATE)) 4541 return -EINVAL; 4542 4543 cur_state = qp->state; 4544 new_state = attr->qp_state; 4545 4546 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4547 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4548 /* 4549 * DCT doesn't initialize QP till modify command is executed, 4550 * so we need to overwrite previously set ECE field if user 4551 * provided any value except zero, which means not set/not 4552 * valid. 4553 */ 4554 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4555 4556 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4557 u16 set_id; 4558 4559 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4560 if (!is_valid_mask(attr_mask, required, 0)) 4561 return -EINVAL; 4562 4563 if (attr->port_num == 0 || 4564 attr->port_num > dev->num_ports) { 4565 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4566 attr->port_num, dev->num_ports); 4567 return -EINVAL; 4568 } 4569 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4570 MLX5_SET(dctc, dctc, rre, 1); 4571 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4572 MLX5_SET(dctc, dctc, rwe, 1); 4573 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4574 int atomic_mode; 4575 4576 atomic_mode = get_atomic_mode(dev, qp); 4577 if (atomic_mode < 0) 4578 return -EOPNOTSUPP; 4579 4580 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4581 MLX5_SET(dctc, dctc, rae, 1); 4582 } 4583 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4584 if (mlx5_lag_is_active(dev->mdev)) 4585 MLX5_SET(dctc, dctc, port, 4586 get_tx_affinity_rr(dev, udata)); 4587 else 4588 MLX5_SET(dctc, dctc, port, attr->port_num); 4589 4590 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4591 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4592 4593 qp->port = attr->port_num; 4594 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4595 struct mlx5_ib_modify_qp_resp resp = {}; 4596 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4597 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4598 4599 if (udata->outlen < min_resp_len) 4600 return -EINVAL; 4601 /* 4602 * If we don't have enough space for the ECE options, 4603 * simply indicate it with resp.response_length. 4604 */ 4605 resp.response_length = (udata->outlen < sizeof(resp)) ? 4606 min_resp_len : 4607 sizeof(resp); 4608 4609 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4610 if (!is_valid_mask(attr_mask, required, 0)) 4611 return -EINVAL; 4612 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4613 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4614 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4615 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4616 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4617 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4618 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) 4619 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7); 4620 if (qp->is_ooo_rq) { 4621 MLX5_SET(dctc, dctc, dp_ordering_1, 1); 4622 MLX5_SET(dctc, dctc, dp_ordering_force, 1); 4623 } 4624 4625 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4626 MLX5_ST_SZ_BYTES(create_dct_in), out, 4627 sizeof(out)); 4628 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); 4629 if (err) 4630 return err; 4631 resp.dctn = qp->dct.mdct.mqp.qpn; 4632 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4633 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4634 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4635 if (err) { 4636 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4637 return err; 4638 } 4639 } else { 4640 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4641 return -EINVAL; 4642 } 4643 4644 qp->state = new_state; 4645 return 0; 4646 } 4647 4648 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4649 struct mlx5_ib_qp *qp) 4650 { 4651 if (dev->profile != &raw_eth_profile) 4652 return true; 4653 4654 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4655 return true; 4656 4657 return false; 4658 } 4659 4660 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr, 4661 int attr_mask, enum ib_qp_type qp_type) 4662 { 4663 int log_max_ra_res; 4664 int log_max_ra_req; 4665 4666 if (qp_type == MLX5_IB_QPT_DCI) { 4667 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4668 log_max_ra_res_dc); 4669 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4670 log_max_ra_req_dc); 4671 } else { 4672 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4673 log_max_ra_res_qp); 4674 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4675 log_max_ra_req_qp); 4676 } 4677 4678 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4679 attr->max_rd_atomic > log_max_ra_res) { 4680 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4681 attr->max_rd_atomic); 4682 return false; 4683 } 4684 4685 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4686 attr->max_dest_rd_atomic > log_max_ra_req) { 4687 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4688 attr->max_dest_rd_atomic); 4689 return false; 4690 } 4691 return true; 4692 } 4693 4694 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4695 int attr_mask, struct ib_udata *udata) 4696 { 4697 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4698 struct mlx5_ib_modify_qp_resp resp = {}; 4699 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4700 struct mlx5_ib_modify_qp ucmd = {}; 4701 enum ib_qp_type qp_type; 4702 enum ib_qp_state cur_state, new_state; 4703 int err = -EINVAL; 4704 4705 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4706 return -EOPNOTSUPP; 4707 4708 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4709 return -EOPNOTSUPP; 4710 4711 if (ibqp->rwq_ind_tbl) 4712 return -ENOSYS; 4713 4714 if (udata && udata->inlen) { 4715 err = ib_copy_validate_udata_in_cm(udata, ucmd, ece_options, 4716 MLX5_IB_MODIFY_QP_OOO_DP); 4717 if (err) 4718 return err; 4719 4720 if (memchr_inv(&ucmd.burst_info.reserved, 0, 4721 sizeof(ucmd.burst_info.reserved))) 4722 return -EOPNOTSUPP; 4723 4724 if (ucmd.comp_mask & MLX5_IB_MODIFY_QP_OOO_DP) { 4725 if (!get_dp_ooo_cap(dev->mdev, qp->type)) 4726 return -EOPNOTSUPP; 4727 qp->is_ooo_rq = 1; 4728 } 4729 } 4730 4731 if (qp->type == IB_QPT_GSI) 4732 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4733 4734 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4735 4736 if (qp_type == MLX5_IB_QPT_DCT) 4737 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4738 4739 mutex_lock(&qp->mutex); 4740 4741 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4742 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4743 4744 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4745 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4746 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4747 attr_mask); 4748 goto out; 4749 } 4750 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4751 qp_type != MLX5_IB_QPT_DCI && 4752 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4753 attr_mask)) { 4754 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4755 cur_state, new_state, qp->type, attr_mask); 4756 goto out; 4757 } else if (qp_type == MLX5_IB_QPT_DCI && 4758 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4759 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4760 cur_state, new_state, qp_type, attr_mask); 4761 goto out; 4762 } 4763 4764 if ((attr_mask & IB_QP_PORT) && 4765 (attr->port_num == 0 || 4766 attr->port_num > dev->num_ports)) { 4767 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4768 attr->port_num, dev->num_ports); 4769 goto out; 4770 } 4771 4772 if ((attr_mask & IB_QP_PKEY_INDEX) && 4773 attr->pkey_index >= dev->pkey_table_len) { 4774 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4775 goto out; 4776 } 4777 4778 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type)) 4779 goto out; 4780 4781 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4782 err = 0; 4783 goto out; 4784 } 4785 4786 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4787 new_state, &ucmd, &resp, udata); 4788 4789 /* resp.response_length is set in ECE supported flows only */ 4790 if (!err && resp.response_length && 4791 udata->outlen >= resp.response_length) 4792 /* Return -EFAULT to the user and expect him to destroy QP. */ 4793 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4794 4795 out: 4796 mutex_unlock(&qp->mutex); 4797 return err; 4798 } 4799 4800 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4801 { 4802 switch (mlx5_state) { 4803 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4804 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4805 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4806 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4807 case MLX5_QP_STATE_SQ_DRAINING: 4808 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4809 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4810 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4811 default: return -1; 4812 } 4813 } 4814 4815 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4816 { 4817 switch (mlx5_mig_state) { 4818 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4819 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4820 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4821 default: return -1; 4822 } 4823 } 4824 4825 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4826 struct rdma_ah_attr *ah_attr, void *path) 4827 { 4828 int port = MLX5_GET(ads, path, vhca_port_num); 4829 int static_rate; 4830 4831 memset(ah_attr, 0, sizeof(*ah_attr)); 4832 4833 if (!port || port > ibdev->num_ports) 4834 return; 4835 4836 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4837 4838 rdma_ah_set_port_num(ah_attr, port); 4839 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4840 4841 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4842 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4843 4844 static_rate = MLX5_GET(ads, path, stat_rate); 4845 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4846 if (MLX5_GET(ads, path, grh) || 4847 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4848 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4849 MLX5_GET(ads, path, src_addr_index), 4850 MLX5_GET(ads, path, hop_limit), 4851 MLX5_GET(ads, path, tclass)); 4852 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4853 } 4854 } 4855 4856 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4857 struct mlx5_ib_sq *sq, 4858 u8 *sq_state) 4859 { 4860 int err; 4861 4862 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4863 if (err) 4864 goto out; 4865 sq->state = *sq_state; 4866 4867 out: 4868 return err; 4869 } 4870 4871 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4872 struct mlx5_ib_rq *rq, 4873 u8 *rq_state) 4874 { 4875 void *out; 4876 void *rqc; 4877 int inlen; 4878 int err; 4879 4880 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4881 out = kvzalloc(inlen, GFP_KERNEL); 4882 if (!out) 4883 return -ENOMEM; 4884 4885 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4886 if (err) 4887 goto out; 4888 4889 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4890 *rq_state = MLX5_GET(rqc, rqc, state); 4891 rq->state = *rq_state; 4892 4893 out: 4894 kvfree(out); 4895 return err; 4896 } 4897 4898 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4899 struct mlx5_ib_qp *qp, u8 *qp_state) 4900 { 4901 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4902 [MLX5_RQC_STATE_RST] = { 4903 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4904 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4905 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4906 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4907 }, 4908 [MLX5_RQC_STATE_RDY] = { 4909 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4910 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4911 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4912 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4913 }, 4914 [MLX5_RQC_STATE_ERR] = { 4915 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4916 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4917 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4918 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4919 }, 4920 [MLX5_RQ_STATE_NA] = { 4921 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4922 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4923 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4924 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4925 }, 4926 }; 4927 4928 *qp_state = sqrq_trans[rq_state][sq_state]; 4929 4930 if (*qp_state == MLX5_QP_STATE_BAD) { 4931 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4932 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4933 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4934 return -EINVAL; 4935 } 4936 4937 if (*qp_state == MLX5_QP_STATE) 4938 *qp_state = qp->state; 4939 4940 return 0; 4941 } 4942 4943 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4944 struct mlx5_ib_qp *qp, 4945 u8 *raw_packet_qp_state) 4946 { 4947 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4948 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4949 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4950 int err; 4951 u8 sq_state = MLX5_SQ_STATE_NA; 4952 u8 rq_state = MLX5_RQ_STATE_NA; 4953 4954 if (qp->sq.wqe_cnt) { 4955 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4956 if (err) 4957 return err; 4958 } 4959 4960 if (qp->rq.wqe_cnt) { 4961 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4962 if (err) 4963 return err; 4964 } 4965 4966 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4967 raw_packet_qp_state); 4968 } 4969 4970 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4971 struct ib_qp_attr *qp_attr) 4972 { 4973 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4974 void *qpc, *pri_path, *alt_path; 4975 u32 *outb; 4976 int err; 4977 4978 outb = kzalloc(outlen, GFP_KERNEL); 4979 if (!outb) 4980 return -ENOMEM; 4981 4982 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 4983 false); 4984 if (err) 4985 goto out; 4986 4987 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4988 4989 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4990 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4991 qp_attr->sq_draining = 1; 4992 4993 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4994 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4995 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4996 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4997 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4998 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4999 5000 if (MLX5_GET(qpc, qpc, rre)) 5001 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 5002 if (MLX5_GET(qpc, qpc, rwe)) 5003 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 5004 if (MLX5_GET(qpc, qpc, rae)) 5005 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5006 5007 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 5008 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 5009 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 5010 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 5011 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 5012 5013 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 5014 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 5015 5016 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 5017 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 5018 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 5019 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 5020 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 5021 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 5022 } 5023 5024 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 5025 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 5026 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 5027 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 5028 5029 out: 5030 kfree(outb); 5031 return err; 5032 } 5033 5034 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5035 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5036 struct ib_qp_init_attr *qp_init_attr) 5037 { 5038 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5039 u32 *out; 5040 u32 access_flags = 0; 5041 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5042 void *dctc; 5043 int err; 5044 int supported_mask = IB_QP_STATE | 5045 IB_QP_ACCESS_FLAGS | 5046 IB_QP_PORT | 5047 IB_QP_MIN_RNR_TIMER | 5048 IB_QP_AV | 5049 IB_QP_PATH_MTU | 5050 IB_QP_PKEY_INDEX; 5051 5052 if (qp_attr_mask & ~supported_mask) 5053 return -EINVAL; 5054 if (mqp->state != IB_QPS_RTR) 5055 return -EINVAL; 5056 5057 out = kzalloc(outlen, GFP_KERNEL); 5058 if (!out) 5059 return -ENOMEM; 5060 5061 err = mlx5_core_dct_query(dev, dct, out, outlen); 5062 if (err) 5063 goto out; 5064 5065 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5066 5067 if (qp_attr_mask & IB_QP_STATE) 5068 qp_attr->qp_state = IB_QPS_RTR; 5069 5070 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5071 if (MLX5_GET(dctc, dctc, rre)) 5072 access_flags |= IB_ACCESS_REMOTE_READ; 5073 if (MLX5_GET(dctc, dctc, rwe)) 5074 access_flags |= IB_ACCESS_REMOTE_WRITE; 5075 if (MLX5_GET(dctc, dctc, rae)) 5076 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5077 qp_attr->qp_access_flags = access_flags; 5078 } 5079 5080 if (qp_attr_mask & IB_QP_PORT) 5081 qp_attr->port_num = mqp->port; 5082 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5083 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5084 if (qp_attr_mask & IB_QP_AV) { 5085 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5086 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5087 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5088 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5089 } 5090 if (qp_attr_mask & IB_QP_PATH_MTU) 5091 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5092 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5093 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5094 out: 5095 kfree(out); 5096 return err; 5097 } 5098 5099 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5100 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5101 { 5102 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5103 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5104 int err = 0; 5105 u8 raw_packet_qp_state; 5106 5107 if (ibqp->rwq_ind_tbl) 5108 return -ENOSYS; 5109 5110 if (qp->type == IB_QPT_GSI) 5111 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5112 qp_init_attr); 5113 5114 /* Not all of output fields are applicable, make sure to zero them */ 5115 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5116 memset(qp_attr, 0, sizeof(*qp_attr)); 5117 5118 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 5119 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5120 qp_attr_mask, qp_init_attr); 5121 5122 mutex_lock(&qp->mutex); 5123 5124 if (qp->type == IB_QPT_RAW_PACKET || 5125 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 5126 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5127 if (err) 5128 goto out; 5129 qp->state = raw_packet_qp_state; 5130 qp_attr->port_num = 1; 5131 } else { 5132 err = query_qp_attr(dev, qp, qp_attr); 5133 if (err) 5134 goto out; 5135 } 5136 5137 qp_attr->qp_state = qp->state; 5138 qp_attr->cur_qp_state = qp_attr->qp_state; 5139 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5140 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5141 5142 if (!ibqp->uobject) { 5143 qp_attr->cap.max_send_wr = qp->sq.max_post; 5144 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5145 qp_init_attr->qp_context = ibqp->qp_context; 5146 } else { 5147 qp_attr->cap.max_send_wr = 0; 5148 qp_attr->cap.max_send_sge = 0; 5149 } 5150 5151 qp_init_attr->qp_type = qp->type; 5152 qp_init_attr->recv_cq = ibqp->recv_cq; 5153 qp_init_attr->send_cq = ibqp->send_cq; 5154 qp_init_attr->srq = ibqp->srq; 5155 qp_attr->cap.max_inline_data = qp->max_inline_data; 5156 5157 qp_init_attr->cap = qp_attr->cap; 5158 5159 qp_init_attr->create_flags = qp->flags; 5160 5161 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5162 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5163 5164 out: 5165 mutex_unlock(&qp->mutex); 5166 return err; 5167 } 5168 5169 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 5170 { 5171 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 5172 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 5173 5174 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5175 return -EOPNOTSUPP; 5176 5177 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5178 } 5179 5180 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5181 { 5182 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5183 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5184 5185 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5186 } 5187 5188 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5189 { 5190 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5191 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5192 struct ib_event event; 5193 5194 if (rwq->ibwq.event_handler) { 5195 event.device = rwq->ibwq.device; 5196 event.element.wq = &rwq->ibwq; 5197 switch (type) { 5198 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5199 event.event = IB_EVENT_WQ_FATAL; 5200 break; 5201 default: 5202 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5203 return; 5204 } 5205 5206 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5207 } 5208 } 5209 5210 static int set_delay_drop(struct mlx5_ib_dev *dev) 5211 { 5212 int err = 0; 5213 5214 mutex_lock(&dev->delay_drop.lock); 5215 if (dev->delay_drop.activate) 5216 goto out; 5217 5218 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5219 if (err) 5220 goto out; 5221 5222 dev->delay_drop.activate = true; 5223 out: 5224 mutex_unlock(&dev->delay_drop.lock); 5225 5226 if (!err) 5227 atomic_inc(&dev->delay_drop.rqs_cnt); 5228 return err; 5229 } 5230 5231 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5232 struct ib_wq_init_attr *init_attr) 5233 { 5234 struct mlx5_ib_dev *dev; 5235 int has_net_offloads; 5236 __be64 *rq_pas0; 5237 int ts_format; 5238 void *in; 5239 void *rqc; 5240 void *wq; 5241 int inlen; 5242 int err; 5243 5244 dev = to_mdev(pd->device); 5245 5246 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5247 if (ts_format < 0) 5248 return ts_format; 5249 5250 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5251 in = kvzalloc(inlen, GFP_KERNEL); 5252 if (!in) 5253 return -ENOMEM; 5254 5255 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5256 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5257 MLX5_SET(rqc, rqc, mem_rq_type, 5258 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5259 MLX5_SET(rqc, rqc, ts_format, ts_format); 5260 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5261 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5262 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5263 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5264 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5265 MLX5_SET(wq, wq, wq_type, 5266 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5267 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5268 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5269 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5270 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5271 err = -EOPNOTSUPP; 5272 goto out; 5273 } else { 5274 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5275 } 5276 } 5277 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5278 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5279 /* 5280 * In Firmware number of strides in each WQE is: 5281 * "512 * 2^single_wqe_log_num_of_strides" 5282 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5283 * accepted as 0 to 9 5284 */ 5285 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5286 2, 3, 4, 5, 6, 7, 8, 9 }; 5287 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5288 MLX5_SET(wq, wq, log_wqe_stride_size, 5289 rwq->single_stride_log_num_of_bytes - 5290 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5291 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5292 fw_map[rwq->log_num_strides - 5293 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5294 } 5295 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5296 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5297 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5298 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5299 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5300 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5301 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5302 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5303 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5304 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5305 err = -EOPNOTSUPP; 5306 goto out; 5307 } 5308 } else { 5309 MLX5_SET(rqc, rqc, vsd, 1); 5310 } 5311 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5312 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5313 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5314 err = -EOPNOTSUPP; 5315 goto out; 5316 } 5317 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5318 } 5319 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5320 if (!(dev->ib_dev.attrs.raw_packet_caps & 5321 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5322 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5323 err = -EOPNOTSUPP; 5324 goto out; 5325 } 5326 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5327 } 5328 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5329 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5330 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5331 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5332 err = set_delay_drop(dev); 5333 if (err) { 5334 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5335 err); 5336 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5337 } else { 5338 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5339 } 5340 } 5341 out: 5342 kvfree(in); 5343 return err; 5344 } 5345 5346 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5347 struct ib_wq_init_attr *wq_init_attr, 5348 struct mlx5_ib_create_wq *ucmd, 5349 struct mlx5_ib_rwq *rwq) 5350 { 5351 /* Sanity check RQ size before proceeding */ 5352 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5353 return -EINVAL; 5354 5355 if (!ucmd->rq_wqe_count) 5356 return -EINVAL; 5357 5358 rwq->wqe_count = ucmd->rq_wqe_count; 5359 rwq->wqe_shift = ucmd->rq_wqe_shift; 5360 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5361 return -EINVAL; 5362 5363 rwq->log_rq_stride = rwq->wqe_shift; 5364 rwq->log_rq_size = ilog2(rwq->wqe_count); 5365 return 0; 5366 } 5367 5368 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5369 { 5370 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5371 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5372 return false; 5373 5374 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5375 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5376 return false; 5377 5378 return true; 5379 } 5380 5381 static int prepare_user_rq(struct ib_pd *pd, 5382 struct ib_wq_init_attr *init_attr, 5383 struct ib_udata *udata, 5384 struct mlx5_ib_rwq *rwq) 5385 { 5386 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5387 struct mlx5_ib_create_wq ucmd; 5388 int err; 5389 5390 err = ib_copy_validate_udata_in_cm(udata, ucmd, 5391 single_stride_log_num_of_bytes, 5392 MLX5_IB_CREATE_WQ_STRIDING_RQ); 5393 if (err) { 5394 mlx5_ib_dbg(dev, "copy failed\n"); 5395 return err; 5396 } 5397 5398 if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5399 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5400 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5401 return -EOPNOTSUPP; 5402 } 5403 if ((ucmd.single_stride_log_num_of_bytes < 5404 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5405 (ucmd.single_stride_log_num_of_bytes > 5406 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5407 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5408 ucmd.single_stride_log_num_of_bytes, 5409 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5410 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5411 return -EINVAL; 5412 } 5413 if (!log_of_strides_valid(dev, 5414 ucmd.single_wqe_log_num_of_strides)) { 5415 mlx5_ib_dbg( 5416 dev, 5417 "Invalid log num strides (%u. Range is %u - %u)\n", 5418 ucmd.single_wqe_log_num_of_strides, 5419 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5420 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5421 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5422 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5423 return -EINVAL; 5424 } 5425 rwq->single_stride_log_num_of_bytes = 5426 ucmd.single_stride_log_num_of_bytes; 5427 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5428 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5429 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5430 } 5431 5432 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5433 if (err) { 5434 mlx5_ib_dbg(dev, "err %d\n", err); 5435 return err; 5436 } 5437 5438 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5439 if (err) { 5440 mlx5_ib_dbg(dev, "err %d\n", err); 5441 return err; 5442 } 5443 5444 rwq->user_index = ucmd.user_index; 5445 return 0; 5446 } 5447 5448 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5449 struct ib_wq_init_attr *init_attr, 5450 struct ib_udata *udata) 5451 { 5452 struct mlx5_ib_dev *dev; 5453 struct mlx5_ib_rwq *rwq; 5454 struct mlx5_ib_create_wq_resp resp = {}; 5455 size_t min_resp_len; 5456 int err; 5457 5458 if (!udata) 5459 return ERR_PTR(-ENOSYS); 5460 5461 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5462 if (udata->outlen && udata->outlen < min_resp_len) 5463 return ERR_PTR(-EINVAL); 5464 5465 if (!capable(CAP_SYS_RAWIO) && 5466 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5467 return ERR_PTR(-EPERM); 5468 5469 dev = to_mdev(pd->device); 5470 switch (init_attr->wq_type) { 5471 case IB_WQT_RQ: 5472 rwq = kzalloc_obj(*rwq); 5473 if (!rwq) 5474 return ERR_PTR(-ENOMEM); 5475 err = prepare_user_rq(pd, init_attr, udata, rwq); 5476 if (err) 5477 goto err; 5478 err = create_rq(rwq, pd, init_attr); 5479 if (err) 5480 goto err_user_rq; 5481 break; 5482 default: 5483 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5484 init_attr->wq_type); 5485 return ERR_PTR(-EINVAL); 5486 } 5487 5488 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5489 rwq->ibwq.state = IB_WQS_RESET; 5490 if (udata->outlen) { 5491 resp.response_length = offsetofend( 5492 struct mlx5_ib_create_wq_resp, response_length); 5493 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5494 if (err) 5495 goto err_copy; 5496 } 5497 5498 rwq->core_qp.event = mlx5_ib_wq_event; 5499 rwq->ibwq.event_handler = init_attr->event_handler; 5500 return &rwq->ibwq; 5501 5502 err_copy: 5503 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5504 err_user_rq: 5505 destroy_user_rq(dev, pd, rwq, udata); 5506 err: 5507 kfree(rwq); 5508 return ERR_PTR(err); 5509 } 5510 5511 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5512 { 5513 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5514 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5515 int ret; 5516 5517 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5518 if (ret) 5519 return ret; 5520 destroy_user_rq(dev, wq->pd, rwq, udata); 5521 kfree(rwq); 5522 return 0; 5523 } 5524 5525 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5526 struct ib_rwq_ind_table_init_attr *init_attr, 5527 struct ib_udata *udata) 5528 { 5529 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5530 to_mrwq_ind_table(ib_rwq_ind_table); 5531 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5532 int sz = 1 << init_attr->log_ind_tbl_size; 5533 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5534 size_t min_resp_len; 5535 int inlen; 5536 int err; 5537 int i; 5538 u32 *in; 5539 void *rqtc; 5540 5541 if (udata->inlen > 0 && 5542 !ib_is_udata_cleared(udata, 0, 5543 udata->inlen)) 5544 return -EOPNOTSUPP; 5545 5546 if (init_attr->log_ind_tbl_size > 5547 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5548 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5549 init_attr->log_ind_tbl_size, 5550 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5551 return -EINVAL; 5552 } 5553 5554 min_resp_len = 5555 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5556 if (udata->outlen && udata->outlen < min_resp_len) 5557 return -EINVAL; 5558 5559 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5560 in = kvzalloc(inlen, GFP_KERNEL); 5561 if (!in) 5562 return -ENOMEM; 5563 5564 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5565 5566 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5567 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5568 5569 for (i = 0; i < sz; i++) 5570 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5571 5572 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5573 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5574 5575 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5576 kvfree(in); 5577 if (err) 5578 return err; 5579 5580 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5581 if (udata->outlen) { 5582 resp.response_length = 5583 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5584 response_length); 5585 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5586 if (err) 5587 goto err_copy; 5588 } 5589 5590 return 0; 5591 5592 err_copy: 5593 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5594 return err; 5595 } 5596 5597 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5598 { 5599 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5600 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5601 5602 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5603 } 5604 5605 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5606 u32 wq_attr_mask, struct ib_udata *udata) 5607 { 5608 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5609 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5610 struct mlx5_ib_modify_wq ucmd = {}; 5611 int curr_wq_state; 5612 int wq_state; 5613 int inlen; 5614 int err; 5615 void *rqc; 5616 void *in; 5617 5618 err = ib_copy_validate_udata_in_cm(udata, ucmd, reserved, 0); 5619 if (err) 5620 return err; 5621 5622 if (ucmd.reserved) 5623 return -EOPNOTSUPP; 5624 5625 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5626 in = kvzalloc(inlen, GFP_KERNEL); 5627 if (!in) 5628 return -ENOMEM; 5629 5630 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5631 5632 curr_wq_state = wq_attr->curr_wq_state; 5633 wq_state = wq_attr->wq_state; 5634 if (curr_wq_state == IB_WQS_ERR) 5635 curr_wq_state = MLX5_RQC_STATE_ERR; 5636 if (wq_state == IB_WQS_ERR) 5637 wq_state = MLX5_RQC_STATE_ERR; 5638 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5639 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5640 MLX5_SET(rqc, rqc, state, wq_state); 5641 5642 if (wq_attr_mask & IB_WQ_FLAGS) { 5643 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5644 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5645 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5646 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5647 err = -EOPNOTSUPP; 5648 goto out; 5649 } 5650 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5651 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5652 MLX5_SET(rqc, rqc, vsd, 5653 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5654 } 5655 5656 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5657 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5658 err = -EOPNOTSUPP; 5659 goto out; 5660 } 5661 } 5662 5663 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5664 u16 set_id; 5665 5666 set_id = mlx5_ib_get_counters_id(dev, 0); 5667 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5668 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5669 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5670 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5671 } else 5672 dev_info_once( 5673 &dev->ib_dev.dev, 5674 "Receive WQ counters are not supported on current FW\n"); 5675 } 5676 5677 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5678 if (!err) 5679 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5680 5681 out: 5682 kvfree(in); 5683 return err; 5684 } 5685 5686 struct mlx5_ib_drain_cqe { 5687 struct ib_cqe cqe; 5688 struct completion done; 5689 }; 5690 5691 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5692 { 5693 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5694 struct mlx5_ib_drain_cqe, 5695 cqe); 5696 5697 complete(&cqe->done); 5698 } 5699 5700 /* This function returns only once the drained WR was completed */ 5701 static void handle_drain_completion(struct ib_cq *cq, 5702 struct mlx5_ib_drain_cqe *sdrain, 5703 struct mlx5_ib_dev *dev) 5704 { 5705 struct mlx5_core_dev *mdev = dev->mdev; 5706 5707 if (cq->poll_ctx == IB_POLL_DIRECT) { 5708 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5709 ib_process_cq_direct(cq, -1); 5710 return; 5711 } 5712 5713 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5714 struct mlx5_ib_cq *mcq = to_mcq(cq); 5715 bool triggered = false; 5716 unsigned long flags; 5717 5718 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5719 /* Make sure that the CQ handler won't run if wasn't run yet */ 5720 if (!mcq->mcq.reset_notify_added) 5721 mcq->mcq.reset_notify_added = 1; 5722 else 5723 triggered = true; 5724 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5725 5726 if (triggered) { 5727 /* Wait for any scheduled/running task to be ended */ 5728 switch (cq->poll_ctx) { 5729 case IB_POLL_SOFTIRQ: 5730 irq_poll_disable(&cq->iop); 5731 irq_poll_enable(&cq->iop); 5732 break; 5733 case IB_POLL_WORKQUEUE: 5734 cancel_work_sync(&cq->work); 5735 break; 5736 default: 5737 WARN_ON_ONCE(1); 5738 } 5739 } 5740 5741 /* Run the CQ handler - this makes sure that the drain WR will 5742 * be processed if wasn't processed yet. 5743 */ 5744 mcq->mcq.comp(&mcq->mcq, NULL); 5745 } 5746 5747 wait_for_completion(&sdrain->done); 5748 } 5749 5750 void mlx5_ib_drain_sq(struct ib_qp *qp) 5751 { 5752 struct ib_cq *cq = qp->send_cq; 5753 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5754 struct mlx5_ib_drain_cqe sdrain; 5755 const struct ib_send_wr *bad_swr; 5756 struct ib_rdma_wr swr = { 5757 .wr = { 5758 .next = NULL, 5759 { .wr_cqe = &sdrain.cqe, }, 5760 .opcode = IB_WR_RDMA_WRITE, 5761 }, 5762 }; 5763 int ret; 5764 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5765 struct mlx5_core_dev *mdev = dev->mdev; 5766 5767 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5768 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5769 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5770 return; 5771 } 5772 5773 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5774 init_completion(&sdrain.done); 5775 5776 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5777 if (ret) { 5778 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5779 return; 5780 } 5781 5782 handle_drain_completion(cq, &sdrain, dev); 5783 } 5784 5785 void mlx5_ib_drain_rq(struct ib_qp *qp) 5786 { 5787 struct ib_cq *cq = qp->recv_cq; 5788 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5789 struct mlx5_ib_drain_cqe rdrain; 5790 struct ib_recv_wr rwr = {}; 5791 const struct ib_recv_wr *bad_rwr; 5792 int ret; 5793 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5794 struct mlx5_core_dev *mdev = dev->mdev; 5795 5796 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5797 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5798 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5799 return; 5800 } 5801 5802 rwr.wr_cqe = &rdrain.cqe; 5803 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5804 init_completion(&rdrain.done); 5805 5806 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5807 if (ret) { 5808 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5809 return; 5810 } 5811 5812 handle_drain_completion(cq, &rdrain, dev); 5813 } 5814 5815 /* 5816 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5817 * the default counter 5818 */ 5819 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5820 { 5821 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5822 struct mlx5_ib_qp *mqp = to_mqp(qp); 5823 int err = 0; 5824 5825 mutex_lock(&mqp->mutex); 5826 if (mqp->state == IB_QPS_RESET) { 5827 qp->counter = counter; 5828 goto out; 5829 } 5830 5831 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5832 err = -EOPNOTSUPP; 5833 goto out; 5834 } 5835 5836 if (mqp->state == IB_QPS_RTS) { 5837 err = __mlx5_ib_qp_set_counter(qp, counter); 5838 if (!err) 5839 qp->counter = counter; 5840 5841 goto out; 5842 } 5843 5844 mqp->counter_pending = 1; 5845 qp->counter = counter; 5846 5847 out: 5848 mutex_unlock(&mqp->mutex); 5849 return err; 5850 } 5851 5852 int mlx5_ib_qp_event_init(void) 5853 { 5854 mlx5_ib_qp_event_wq = alloc_ordered_workqueue("mlx5_ib_qp_event_wq", 0); 5855 if (!mlx5_ib_qp_event_wq) 5856 return -ENOMEM; 5857 5858 return 0; 5859 } 5860 5861 void mlx5_ib_qp_event_cleanup(void) 5862 { 5863 destroy_workqueue(mlx5_ib_qp_event_wq); 5864 } 5865