1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include "mlx5_ib.h" 38 #include "user.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 MLX5_IB_CACHE_LINE_SIZE = 64, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 static void get_cqs(enum ib_qp_type qp_type, 81 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 82 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 83 84 static int is_qp0(enum ib_qp_type qp_type) 85 { 86 return qp_type == IB_QPT_SMI; 87 } 88 89 static int is_sqp(enum ib_qp_type qp_type) 90 { 91 return is_qp0(qp_type) || is_qp1(qp_type); 92 } 93 94 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 95 { 96 return mlx5_buf_offset(&qp->buf, offset); 97 } 98 99 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 100 { 101 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 102 } 103 104 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 105 { 106 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 107 } 108 109 /** 110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 111 * 112 * @qp: QP to copy from. 113 * @send: copy from the send queue when non-zero, use the receive queue 114 * otherwise. 115 * @wqe_index: index to start copying from. For send work queues, the 116 * wqe_index is in units of MLX5_SEND_WQE_BB. 117 * For receive work queue, it is the number of work queue 118 * element in the queue. 119 * @buffer: destination buffer. 120 * @length: maximum number of bytes to copy. 121 * 122 * Copies at least a single WQE, but may copy more data. 123 * 124 * Return: the number of bytes copied, or an error code. 125 */ 126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 127 void *buffer, u32 length, 128 struct mlx5_ib_qp_base *base) 129 { 130 struct ib_device *ibdev = qp->ibqp.device; 131 struct mlx5_ib_dev *dev = to_mdev(ibdev); 132 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 133 size_t offset; 134 size_t wq_end; 135 struct ib_umem *umem = base->ubuffer.umem; 136 u32 first_copy_length; 137 int wqe_length; 138 int ret; 139 140 if (wq->wqe_cnt == 0) { 141 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 142 qp->ibqp.qp_type); 143 return -EINVAL; 144 } 145 146 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 147 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 148 149 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 150 return -EINVAL; 151 152 if (offset > umem->length || 153 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 154 return -EINVAL; 155 156 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 157 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 158 if (ret) 159 return ret; 160 161 if (send) { 162 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 163 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 164 165 wqe_length = ds * MLX5_WQE_DS_UNITS; 166 } else { 167 wqe_length = 1 << wq->wqe_shift; 168 } 169 170 if (wqe_length <= first_copy_length) 171 return first_copy_length; 172 173 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 174 wqe_length - first_copy_length); 175 if (ret) 176 return ret; 177 178 return wqe_length; 179 } 180 181 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 182 { 183 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 184 struct ib_event event; 185 186 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 187 /* This event is only valid for trans_qps */ 188 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 189 } 190 191 if (ibqp->event_handler) { 192 event.device = ibqp->device; 193 event.element.qp = ibqp; 194 switch (type) { 195 case MLX5_EVENT_TYPE_PATH_MIG: 196 event.event = IB_EVENT_PATH_MIG; 197 break; 198 case MLX5_EVENT_TYPE_COMM_EST: 199 event.event = IB_EVENT_COMM_EST; 200 break; 201 case MLX5_EVENT_TYPE_SQ_DRAINED: 202 event.event = IB_EVENT_SQ_DRAINED; 203 break; 204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 205 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 206 break; 207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 208 event.event = IB_EVENT_QP_FATAL; 209 break; 210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 211 event.event = IB_EVENT_PATH_MIG_ERR; 212 break; 213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 214 event.event = IB_EVENT_QP_REQ_ERR; 215 break; 216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 217 event.event = IB_EVENT_QP_ACCESS_ERR; 218 break; 219 default: 220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 221 return; 222 } 223 224 ibqp->event_handler(&event, ibqp->qp_context); 225 } 226 } 227 228 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 229 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 230 { 231 int wqe_size; 232 int wq_size; 233 234 /* Sanity check RQ size before proceeding */ 235 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 236 return -EINVAL; 237 238 if (!has_rq) { 239 qp->rq.max_gs = 0; 240 qp->rq.wqe_cnt = 0; 241 qp->rq.wqe_shift = 0; 242 cap->max_recv_wr = 0; 243 cap->max_recv_sge = 0; 244 } else { 245 if (ucmd) { 246 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 247 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 248 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 249 qp->rq.max_post = qp->rq.wqe_cnt; 250 } else { 251 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 252 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 253 wqe_size = roundup_pow_of_two(wqe_size); 254 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 255 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 256 qp->rq.wqe_cnt = wq_size / wqe_size; 257 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 258 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 259 wqe_size, 260 MLX5_CAP_GEN(dev->mdev, 261 max_wqe_sz_rq)); 262 return -EINVAL; 263 } 264 qp->rq.wqe_shift = ilog2(wqe_size); 265 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 266 qp->rq.max_post = qp->rq.wqe_cnt; 267 } 268 } 269 270 return 0; 271 } 272 273 static int sq_overhead(struct ib_qp_init_attr *attr) 274 { 275 int size = 0; 276 277 switch (attr->qp_type) { 278 case IB_QPT_XRC_INI: 279 size += sizeof(struct mlx5_wqe_xrc_seg); 280 /* fall through */ 281 case IB_QPT_RC: 282 size += sizeof(struct mlx5_wqe_ctrl_seg) + 283 max(sizeof(struct mlx5_wqe_atomic_seg) + 284 sizeof(struct mlx5_wqe_raddr_seg), 285 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 286 sizeof(struct mlx5_mkey_seg)); 287 break; 288 289 case IB_QPT_XRC_TGT: 290 return 0; 291 292 case IB_QPT_UC: 293 size += sizeof(struct mlx5_wqe_ctrl_seg) + 294 max(sizeof(struct mlx5_wqe_raddr_seg), 295 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 296 sizeof(struct mlx5_mkey_seg)); 297 break; 298 299 case IB_QPT_UD: 300 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 301 size += sizeof(struct mlx5_wqe_eth_pad) + 302 sizeof(struct mlx5_wqe_eth_seg); 303 /* fall through */ 304 case IB_QPT_SMI: 305 case MLX5_IB_QPT_HW_GSI: 306 size += sizeof(struct mlx5_wqe_ctrl_seg) + 307 sizeof(struct mlx5_wqe_datagram_seg); 308 break; 309 310 case MLX5_IB_QPT_REG_UMR: 311 size += sizeof(struct mlx5_wqe_ctrl_seg) + 312 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 313 sizeof(struct mlx5_mkey_seg); 314 break; 315 316 default: 317 return -EINVAL; 318 } 319 320 return size; 321 } 322 323 static int calc_send_wqe(struct ib_qp_init_attr *attr) 324 { 325 int inl_size = 0; 326 int size; 327 328 size = sq_overhead(attr); 329 if (size < 0) 330 return size; 331 332 if (attr->cap.max_inline_data) { 333 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 334 attr->cap.max_inline_data; 335 } 336 337 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 338 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 339 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 340 return MLX5_SIG_WQE_SIZE; 341 else 342 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 343 } 344 345 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 346 struct mlx5_ib_qp *qp) 347 { 348 int wqe_size; 349 int wq_size; 350 351 if (!attr->cap.max_send_wr) 352 return 0; 353 354 wqe_size = calc_send_wqe(attr); 355 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 356 if (wqe_size < 0) 357 return wqe_size; 358 359 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 360 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 361 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 362 return -EINVAL; 363 } 364 365 qp->max_inline_data = wqe_size - sq_overhead(attr) - 366 sizeof(struct mlx5_wqe_inline_seg); 367 attr->cap.max_inline_data = qp->max_inline_data; 368 369 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 370 qp->signature_en = true; 371 372 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 373 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 374 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 375 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 376 qp->sq.wqe_cnt, 377 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 378 return -ENOMEM; 379 } 380 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 381 qp->sq.max_gs = attr->cap.max_send_sge; 382 qp->sq.max_post = wq_size / wqe_size; 383 attr->cap.max_send_wr = qp->sq.max_post; 384 385 return wq_size; 386 } 387 388 static int set_user_buf_size(struct mlx5_ib_dev *dev, 389 struct mlx5_ib_qp *qp, 390 struct mlx5_ib_create_qp *ucmd, 391 struct mlx5_ib_qp_base *base, 392 struct ib_qp_init_attr *attr) 393 { 394 int desc_sz = 1 << qp->sq.wqe_shift; 395 396 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 397 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 398 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 399 return -EINVAL; 400 } 401 402 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 403 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 404 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 405 return -EINVAL; 406 } 407 408 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 409 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 411 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -EINVAL; 415 } 416 417 if (attr->qp_type == IB_QPT_RAW_PACKET) { 418 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 419 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 420 } else { 421 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 422 (qp->sq.wqe_cnt << 6); 423 } 424 425 return 0; 426 } 427 428 static int qp_has_rq(struct ib_qp_init_attr *attr) 429 { 430 if (attr->qp_type == IB_QPT_XRC_INI || 431 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 432 attr->qp_type == MLX5_IB_QPT_REG_UMR || 433 !attr->cap.max_recv_wr) 434 return 0; 435 436 return 1; 437 } 438 439 static int first_med_uuar(void) 440 { 441 return 1; 442 } 443 444 static int next_uuar(int n) 445 { 446 n++; 447 448 while (((n % 4) & 2)) 449 n++; 450 451 return n; 452 } 453 454 static int num_med_uuar(struct mlx5_uuar_info *uuari) 455 { 456 int n; 457 458 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 459 uuari->num_low_latency_uuars - 1; 460 461 return n >= 0 ? n : 0; 462 } 463 464 static int max_uuari(struct mlx5_uuar_info *uuari) 465 { 466 return uuari->num_uars * 4; 467 } 468 469 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 470 { 471 int med; 472 int i; 473 int t; 474 475 med = num_med_uuar(uuari); 476 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 477 t++; 478 if (t == med) 479 return next_uuar(i); 480 } 481 482 return 0; 483 } 484 485 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 486 { 487 int i; 488 489 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 490 if (!test_bit(i, uuari->bitmap)) { 491 set_bit(i, uuari->bitmap); 492 uuari->count[i]++; 493 return i; 494 } 495 } 496 497 return -ENOMEM; 498 } 499 500 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 501 { 502 int minidx = first_med_uuar(); 503 int i; 504 505 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 506 if (uuari->count[i] < uuari->count[minidx]) 507 minidx = i; 508 } 509 510 uuari->count[minidx]++; 511 return minidx; 512 } 513 514 static int alloc_uuar(struct mlx5_uuar_info *uuari, 515 enum mlx5_ib_latency_class lat) 516 { 517 int uuarn = -EINVAL; 518 519 mutex_lock(&uuari->lock); 520 switch (lat) { 521 case MLX5_IB_LATENCY_CLASS_LOW: 522 uuarn = 0; 523 uuari->count[uuarn]++; 524 break; 525 526 case MLX5_IB_LATENCY_CLASS_MEDIUM: 527 if (uuari->ver < 2) 528 uuarn = -ENOMEM; 529 else 530 uuarn = alloc_med_class_uuar(uuari); 531 break; 532 533 case MLX5_IB_LATENCY_CLASS_HIGH: 534 if (uuari->ver < 2) 535 uuarn = -ENOMEM; 536 else 537 uuarn = alloc_high_class_uuar(uuari); 538 break; 539 540 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 541 uuarn = 2; 542 break; 543 } 544 mutex_unlock(&uuari->lock); 545 546 return uuarn; 547 } 548 549 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 550 { 551 clear_bit(uuarn, uuari->bitmap); 552 --uuari->count[uuarn]; 553 } 554 555 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 556 { 557 clear_bit(uuarn, uuari->bitmap); 558 --uuari->count[uuarn]; 559 } 560 561 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 562 { 563 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 564 int high_uuar = nuuars - uuari->num_low_latency_uuars; 565 566 mutex_lock(&uuari->lock); 567 if (uuarn == 0) { 568 --uuari->count[uuarn]; 569 goto out; 570 } 571 572 if (uuarn < high_uuar) { 573 free_med_class_uuar(uuari, uuarn); 574 goto out; 575 } 576 577 free_high_class_uuar(uuari, uuarn); 578 579 out: 580 mutex_unlock(&uuari->lock); 581 } 582 583 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 584 { 585 switch (state) { 586 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 587 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 588 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 589 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 590 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 591 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 592 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 593 default: return -1; 594 } 595 } 596 597 static int to_mlx5_st(enum ib_qp_type type) 598 { 599 switch (type) { 600 case IB_QPT_RC: return MLX5_QP_ST_RC; 601 case IB_QPT_UC: return MLX5_QP_ST_UC; 602 case IB_QPT_UD: return MLX5_QP_ST_UD; 603 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 604 case IB_QPT_XRC_INI: 605 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 606 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 607 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 608 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 609 case IB_QPT_RAW_PACKET: 610 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 611 case IB_QPT_MAX: 612 default: return -EINVAL; 613 } 614 } 615 616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 619 struct mlx5_ib_cq *recv_cq); 620 621 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 622 { 623 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 624 } 625 626 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 627 struct ib_pd *pd, 628 unsigned long addr, size_t size, 629 struct ib_umem **umem, 630 int *npages, int *page_shift, int *ncont, 631 u32 *offset) 632 { 633 int err; 634 635 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 636 if (IS_ERR(*umem)) { 637 mlx5_ib_dbg(dev, "umem_get failed\n"); 638 return PTR_ERR(*umem); 639 } 640 641 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL); 642 643 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 644 if (err) { 645 mlx5_ib_warn(dev, "bad offset\n"); 646 goto err_umem; 647 } 648 649 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 650 addr, size, *npages, *page_shift, *ncont, *offset); 651 652 return 0; 653 654 err_umem: 655 ib_umem_release(*umem); 656 *umem = NULL; 657 658 return err; 659 } 660 661 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq) 662 { 663 struct mlx5_ib_ucontext *context; 664 665 context = to_mucontext(pd->uobject->context); 666 mlx5_ib_db_unmap_user(context, &rwq->db); 667 if (rwq->umem) 668 ib_umem_release(rwq->umem); 669 } 670 671 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 672 struct mlx5_ib_rwq *rwq, 673 struct mlx5_ib_create_wq *ucmd) 674 { 675 struct mlx5_ib_ucontext *context; 676 int page_shift = 0; 677 int npages; 678 u32 offset = 0; 679 int ncont = 0; 680 int err; 681 682 if (!ucmd->buf_addr) 683 return -EINVAL; 684 685 context = to_mucontext(pd->uobject->context); 686 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 687 rwq->buf_size, 0, 0); 688 if (IS_ERR(rwq->umem)) { 689 mlx5_ib_dbg(dev, "umem_get failed\n"); 690 err = PTR_ERR(rwq->umem); 691 return err; 692 } 693 694 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift, 695 &ncont, NULL); 696 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 697 &rwq->rq_page_offset); 698 if (err) { 699 mlx5_ib_warn(dev, "bad offset\n"); 700 goto err_umem; 701 } 702 703 rwq->rq_num_pas = ncont; 704 rwq->page_shift = page_shift; 705 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 706 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 707 708 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 709 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 710 npages, page_shift, ncont, offset); 711 712 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 713 if (err) { 714 mlx5_ib_dbg(dev, "map failed\n"); 715 goto err_umem; 716 } 717 718 rwq->create_type = MLX5_WQ_USER; 719 return 0; 720 721 err_umem: 722 ib_umem_release(rwq->umem); 723 return err; 724 } 725 726 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 727 struct mlx5_ib_qp *qp, struct ib_udata *udata, 728 struct ib_qp_init_attr *attr, 729 struct mlx5_create_qp_mbox_in **in, 730 struct mlx5_ib_create_qp_resp *resp, int *inlen, 731 struct mlx5_ib_qp_base *base) 732 { 733 struct mlx5_ib_ucontext *context; 734 struct mlx5_ib_create_qp ucmd; 735 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 736 int page_shift = 0; 737 int uar_index; 738 int npages; 739 u32 offset = 0; 740 int uuarn; 741 int ncont = 0; 742 int err; 743 744 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 745 if (err) { 746 mlx5_ib_dbg(dev, "copy failed\n"); 747 return err; 748 } 749 750 context = to_mucontext(pd->uobject->context); 751 /* 752 * TBD: should come from the verbs when we have the API 753 */ 754 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 755 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 756 uuarn = MLX5_CROSS_CHANNEL_UUAR; 757 else { 758 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 759 if (uuarn < 0) { 760 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 761 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 762 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 763 if (uuarn < 0) { 764 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 765 mlx5_ib_dbg(dev, "reverting to high latency\n"); 766 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 767 if (uuarn < 0) { 768 mlx5_ib_warn(dev, "uuar allocation failed\n"); 769 return uuarn; 770 } 771 } 772 } 773 } 774 775 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 776 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 777 778 qp->rq.offset = 0; 779 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 780 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 781 782 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 783 if (err) 784 goto err_uuar; 785 786 if (ucmd.buf_addr && ubuffer->buf_size) { 787 ubuffer->buf_addr = ucmd.buf_addr; 788 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 789 ubuffer->buf_size, 790 &ubuffer->umem, &npages, &page_shift, 791 &ncont, &offset); 792 if (err) 793 goto err_uuar; 794 } else { 795 ubuffer->umem = NULL; 796 } 797 798 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 799 *in = mlx5_vzalloc(*inlen); 800 if (!*in) { 801 err = -ENOMEM; 802 goto err_umem; 803 } 804 if (ubuffer->umem) 805 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, 806 (*in)->pas, 0); 807 (*in)->ctx.log_pg_sz_remote_qpn = 808 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 809 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 810 811 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 812 resp->uuar_index = uuarn; 813 qp->uuarn = uuarn; 814 815 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 816 if (err) { 817 mlx5_ib_dbg(dev, "map failed\n"); 818 goto err_free; 819 } 820 821 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 822 if (err) { 823 mlx5_ib_dbg(dev, "copy failed\n"); 824 goto err_unmap; 825 } 826 qp->create_type = MLX5_QP_USER; 827 828 return 0; 829 830 err_unmap: 831 mlx5_ib_db_unmap_user(context, &qp->db); 832 833 err_free: 834 kvfree(*in); 835 836 err_umem: 837 if (ubuffer->umem) 838 ib_umem_release(ubuffer->umem); 839 840 err_uuar: 841 free_uuar(&context->uuari, uuarn); 842 return err; 843 } 844 845 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp, 846 struct mlx5_ib_qp_base *base) 847 { 848 struct mlx5_ib_ucontext *context; 849 850 context = to_mucontext(pd->uobject->context); 851 mlx5_ib_db_unmap_user(context, &qp->db); 852 if (base->ubuffer.umem) 853 ib_umem_release(base->ubuffer.umem); 854 free_uuar(&context->uuari, qp->uuarn); 855 } 856 857 static int create_kernel_qp(struct mlx5_ib_dev *dev, 858 struct ib_qp_init_attr *init_attr, 859 struct mlx5_ib_qp *qp, 860 struct mlx5_create_qp_mbox_in **in, int *inlen, 861 struct mlx5_ib_qp_base *base) 862 { 863 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 864 struct mlx5_uuar_info *uuari; 865 int uar_index; 866 int uuarn; 867 int err; 868 869 uuari = &dev->mdev->priv.uuari; 870 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 871 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 872 IB_QP_CREATE_IPOIB_UD_LSO | 873 mlx5_ib_create_qp_sqpn_qp1())) 874 return -EINVAL; 875 876 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 877 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 878 879 uuarn = alloc_uuar(uuari, lc); 880 if (uuarn < 0) { 881 mlx5_ib_dbg(dev, "\n"); 882 return -ENOMEM; 883 } 884 885 qp->bf = &uuari->bfs[uuarn]; 886 uar_index = qp->bf->uar->index; 887 888 err = calc_sq_size(dev, init_attr, qp); 889 if (err < 0) { 890 mlx5_ib_dbg(dev, "err %d\n", err); 891 goto err_uuar; 892 } 893 894 qp->rq.offset = 0; 895 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 896 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 897 898 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 899 if (err) { 900 mlx5_ib_dbg(dev, "err %d\n", err); 901 goto err_uuar; 902 } 903 904 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 905 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 906 *in = mlx5_vzalloc(*inlen); 907 if (!*in) { 908 err = -ENOMEM; 909 goto err_buf; 910 } 911 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 912 (*in)->ctx.log_pg_sz_remote_qpn = 913 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 914 /* Set "fast registration enabled" for all kernel QPs */ 915 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 916 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 917 918 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 919 (*in)->ctx.deth_sqpn = cpu_to_be32(1); 920 qp->flags |= MLX5_IB_QP_SQPN_QP1; 921 } 922 923 mlx5_fill_page_array(&qp->buf, (*in)->pas); 924 925 err = mlx5_db_alloc(dev->mdev, &qp->db); 926 if (err) { 927 mlx5_ib_dbg(dev, "err %d\n", err); 928 goto err_free; 929 } 930 931 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 932 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 933 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 934 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 935 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 936 937 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 938 !qp->sq.w_list || !qp->sq.wqe_head) { 939 err = -ENOMEM; 940 goto err_wrid; 941 } 942 qp->create_type = MLX5_QP_KERNEL; 943 944 return 0; 945 946 err_wrid: 947 mlx5_db_free(dev->mdev, &qp->db); 948 kfree(qp->sq.wqe_head); 949 kfree(qp->sq.w_list); 950 kfree(qp->sq.wrid); 951 kfree(qp->sq.wr_data); 952 kfree(qp->rq.wrid); 953 954 err_free: 955 kvfree(*in); 956 957 err_buf: 958 mlx5_buf_free(dev->mdev, &qp->buf); 959 960 err_uuar: 961 free_uuar(&dev->mdev->priv.uuari, uuarn); 962 return err; 963 } 964 965 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 966 { 967 mlx5_db_free(dev->mdev, &qp->db); 968 kfree(qp->sq.wqe_head); 969 kfree(qp->sq.w_list); 970 kfree(qp->sq.wrid); 971 kfree(qp->sq.wr_data); 972 kfree(qp->rq.wrid); 973 mlx5_buf_free(dev->mdev, &qp->buf); 974 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 975 } 976 977 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 978 { 979 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 980 (attr->qp_type == IB_QPT_XRC_INI)) 981 return cpu_to_be32(MLX5_SRQ_RQ); 982 else if (!qp->has_rq) 983 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 984 else 985 return cpu_to_be32(MLX5_NON_ZERO_RQ); 986 } 987 988 static int is_connected(enum ib_qp_type qp_type) 989 { 990 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 991 return 1; 992 993 return 0; 994 } 995 996 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 997 struct mlx5_ib_sq *sq, u32 tdn) 998 { 999 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 1000 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1001 1002 memset(in, 0, sizeof(in)); 1003 1004 MLX5_SET(tisc, tisc, transport_domain, tdn); 1005 1006 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1007 } 1008 1009 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1010 struct mlx5_ib_sq *sq) 1011 { 1012 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1013 } 1014 1015 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1016 struct mlx5_ib_sq *sq, void *qpin, 1017 struct ib_pd *pd) 1018 { 1019 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1020 __be64 *pas; 1021 void *in; 1022 void *sqc; 1023 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1024 void *wq; 1025 int inlen; 1026 int err; 1027 int page_shift = 0; 1028 int npages; 1029 int ncont = 0; 1030 u32 offset = 0; 1031 1032 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1033 &sq->ubuffer.umem, &npages, &page_shift, 1034 &ncont, &offset); 1035 if (err) 1036 return err; 1037 1038 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1039 in = mlx5_vzalloc(inlen); 1040 if (!in) { 1041 err = -ENOMEM; 1042 goto err_umem; 1043 } 1044 1045 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1046 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1047 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1048 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1049 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1050 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1051 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1052 1053 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1054 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1055 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1056 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1057 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1058 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1059 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1060 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1061 MLX5_SET(wq, wq, page_offset, offset); 1062 1063 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1064 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1065 1066 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1067 1068 kvfree(in); 1069 1070 if (err) 1071 goto err_umem; 1072 1073 return 0; 1074 1075 err_umem: 1076 ib_umem_release(sq->ubuffer.umem); 1077 sq->ubuffer.umem = NULL; 1078 1079 return err; 1080 } 1081 1082 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1083 struct mlx5_ib_sq *sq) 1084 { 1085 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1086 ib_umem_release(sq->ubuffer.umem); 1087 } 1088 1089 static int get_rq_pas_size(void *qpc) 1090 { 1091 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1092 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1093 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1094 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1095 u32 po_quanta = 1 << (log_page_size - 6); 1096 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1097 u32 page_size = 1 << log_page_size; 1098 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1099 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1100 1101 return rq_num_pas * sizeof(u64); 1102 } 1103 1104 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1105 struct mlx5_ib_rq *rq, void *qpin) 1106 { 1107 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1108 __be64 *pas; 1109 __be64 *qp_pas; 1110 void *in; 1111 void *rqc; 1112 void *wq; 1113 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1114 int inlen; 1115 int err; 1116 u32 rq_pas_size = get_rq_pas_size(qpc); 1117 1118 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1119 in = mlx5_vzalloc(inlen); 1120 if (!in) 1121 return -ENOMEM; 1122 1123 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1124 MLX5_SET(rqc, rqc, vsd, 1); 1125 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1126 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1127 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1128 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1129 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1130 1131 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1132 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1133 1134 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1135 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1136 MLX5_SET(wq, wq, end_padding_mode, 1137 MLX5_GET(qpc, qpc, end_padding_mode)); 1138 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1139 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1140 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1141 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1142 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1143 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1144 1145 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1146 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1147 memcpy(pas, qp_pas, rq_pas_size); 1148 1149 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1150 1151 kvfree(in); 1152 1153 return err; 1154 } 1155 1156 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1157 struct mlx5_ib_rq *rq) 1158 { 1159 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1160 } 1161 1162 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1163 struct mlx5_ib_rq *rq, u32 tdn) 1164 { 1165 u32 *in; 1166 void *tirc; 1167 int inlen; 1168 int err; 1169 1170 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1171 in = mlx5_vzalloc(inlen); 1172 if (!in) 1173 return -ENOMEM; 1174 1175 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1176 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1177 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1178 MLX5_SET(tirc, tirc, transport_domain, tdn); 1179 1180 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1181 1182 kvfree(in); 1183 1184 return err; 1185 } 1186 1187 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1188 struct mlx5_ib_rq *rq) 1189 { 1190 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1191 } 1192 1193 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1194 struct mlx5_create_qp_mbox_in *in, 1195 struct ib_pd *pd) 1196 { 1197 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1198 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1199 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1200 struct ib_uobject *uobj = pd->uobject; 1201 struct ib_ucontext *ucontext = uobj->context; 1202 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1203 int err; 1204 u32 tdn = mucontext->tdn; 1205 1206 if (qp->sq.wqe_cnt) { 1207 err = create_raw_packet_qp_tis(dev, sq, tdn); 1208 if (err) 1209 return err; 1210 1211 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1212 if (err) 1213 goto err_destroy_tis; 1214 1215 sq->base.container_mibqp = qp; 1216 } 1217 1218 if (qp->rq.wqe_cnt) { 1219 rq->base.container_mibqp = qp; 1220 1221 err = create_raw_packet_qp_rq(dev, rq, in); 1222 if (err) 1223 goto err_destroy_sq; 1224 1225 1226 err = create_raw_packet_qp_tir(dev, rq, tdn); 1227 if (err) 1228 goto err_destroy_rq; 1229 } 1230 1231 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1232 rq->base.mqp.qpn; 1233 1234 return 0; 1235 1236 err_destroy_rq: 1237 destroy_raw_packet_qp_rq(dev, rq); 1238 err_destroy_sq: 1239 if (!qp->sq.wqe_cnt) 1240 return err; 1241 destroy_raw_packet_qp_sq(dev, sq); 1242 err_destroy_tis: 1243 destroy_raw_packet_qp_tis(dev, sq); 1244 1245 return err; 1246 } 1247 1248 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1249 struct mlx5_ib_qp *qp) 1250 { 1251 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1252 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1253 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1254 1255 if (qp->rq.wqe_cnt) { 1256 destroy_raw_packet_qp_tir(dev, rq); 1257 destroy_raw_packet_qp_rq(dev, rq); 1258 } 1259 1260 if (qp->sq.wqe_cnt) { 1261 destroy_raw_packet_qp_sq(dev, sq); 1262 destroy_raw_packet_qp_tis(dev, sq); 1263 } 1264 } 1265 1266 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1267 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1268 { 1269 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1270 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1271 1272 sq->sq = &qp->sq; 1273 rq->rq = &qp->rq; 1274 sq->doorbell = &qp->db; 1275 rq->doorbell = &qp->db; 1276 } 1277 1278 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1279 { 1280 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1281 } 1282 1283 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1284 struct ib_pd *pd, 1285 struct ib_qp_init_attr *init_attr, 1286 struct ib_udata *udata) 1287 { 1288 struct ib_uobject *uobj = pd->uobject; 1289 struct ib_ucontext *ucontext = uobj->context; 1290 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1291 struct mlx5_ib_create_qp_resp resp = {}; 1292 int inlen; 1293 int err; 1294 u32 *in; 1295 void *tirc; 1296 void *hfso; 1297 u32 selected_fields = 0; 1298 size_t min_resp_len; 1299 u32 tdn = mucontext->tdn; 1300 struct mlx5_ib_create_qp_rss ucmd = {}; 1301 size_t required_cmd_sz; 1302 1303 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1304 return -EOPNOTSUPP; 1305 1306 if (init_attr->create_flags || init_attr->send_cq) 1307 return -EINVAL; 1308 1309 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index); 1310 if (udata->outlen < min_resp_len) 1311 return -EINVAL; 1312 1313 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1314 if (udata->inlen < required_cmd_sz) { 1315 mlx5_ib_dbg(dev, "invalid inlen\n"); 1316 return -EINVAL; 1317 } 1318 1319 if (udata->inlen > sizeof(ucmd) && 1320 !ib_is_udata_cleared(udata, sizeof(ucmd), 1321 udata->inlen - sizeof(ucmd))) { 1322 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1323 return -EOPNOTSUPP; 1324 } 1325 1326 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1327 mlx5_ib_dbg(dev, "copy failed\n"); 1328 return -EFAULT; 1329 } 1330 1331 if (ucmd.comp_mask) { 1332 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1333 return -EOPNOTSUPP; 1334 } 1335 1336 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1337 mlx5_ib_dbg(dev, "invalid reserved\n"); 1338 return -EOPNOTSUPP; 1339 } 1340 1341 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1342 if (err) { 1343 mlx5_ib_dbg(dev, "copy failed\n"); 1344 return -EINVAL; 1345 } 1346 1347 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1348 in = mlx5_vzalloc(inlen); 1349 if (!in) 1350 return -ENOMEM; 1351 1352 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1353 MLX5_SET(tirc, tirc, disp_type, 1354 MLX5_TIRC_DISP_TYPE_INDIRECT); 1355 MLX5_SET(tirc, tirc, indirect_table, 1356 init_attr->rwq_ind_tbl->ind_tbl_num); 1357 MLX5_SET(tirc, tirc, transport_domain, tdn); 1358 1359 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1360 switch (ucmd.rx_hash_function) { 1361 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1362 { 1363 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1364 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1365 1366 if (len != ucmd.rx_key_len) { 1367 err = -EINVAL; 1368 goto err; 1369 } 1370 1371 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1372 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1373 memcpy(rss_key, ucmd.rx_hash_key, len); 1374 break; 1375 } 1376 default: 1377 err = -EOPNOTSUPP; 1378 goto err; 1379 } 1380 1381 if (!ucmd.rx_hash_fields_mask) { 1382 /* special case when this TIR serves as steering entry without hashing */ 1383 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1384 goto create_tir; 1385 err = -EINVAL; 1386 goto err; 1387 } 1388 1389 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1390 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1391 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1392 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1393 err = -EINVAL; 1394 goto err; 1395 } 1396 1397 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1398 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1399 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1400 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1401 MLX5_L3_PROT_TYPE_IPV4); 1402 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1403 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1404 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1405 MLX5_L3_PROT_TYPE_IPV6); 1406 1407 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1408 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1409 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1410 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1411 err = -EINVAL; 1412 goto err; 1413 } 1414 1415 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1416 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1417 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1418 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1419 MLX5_L4_PROT_TYPE_TCP); 1420 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1421 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1422 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1423 MLX5_L4_PROT_TYPE_UDP); 1424 1425 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1426 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1427 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1428 1429 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1430 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1431 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1432 1433 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1435 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1436 1437 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1439 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1440 1441 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1442 1443 create_tir: 1444 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1445 1446 if (err) 1447 goto err; 1448 1449 kvfree(in); 1450 /* qpn is reserved for that QP */ 1451 qp->trans_qp.base.mqp.qpn = 0; 1452 return 0; 1453 1454 err: 1455 kvfree(in); 1456 return err; 1457 } 1458 1459 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1460 struct ib_qp_init_attr *init_attr, 1461 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1462 { 1463 struct mlx5_ib_resources *devr = &dev->devr; 1464 struct mlx5_core_dev *mdev = dev->mdev; 1465 struct mlx5_ib_qp_base *base; 1466 struct mlx5_ib_create_qp_resp resp; 1467 struct mlx5_create_qp_mbox_in *in; 1468 struct mlx5_ib_create_qp ucmd; 1469 struct mlx5_ib_cq *send_cq; 1470 struct mlx5_ib_cq *recv_cq; 1471 unsigned long flags; 1472 int inlen = sizeof(*in); 1473 int err; 1474 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1475 void *qpc; 1476 1477 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1478 &qp->raw_packet_qp.rq.base : 1479 &qp->trans_qp.base; 1480 1481 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1482 mlx5_ib_odp_create_qp(qp); 1483 1484 mutex_init(&qp->mutex); 1485 spin_lock_init(&qp->sq.lock); 1486 spin_lock_init(&qp->rq.lock); 1487 1488 if (init_attr->rwq_ind_tbl) { 1489 if (!udata) 1490 return -ENOSYS; 1491 1492 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1493 return err; 1494 } 1495 1496 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1497 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1498 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1499 return -EINVAL; 1500 } else { 1501 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1502 } 1503 } 1504 1505 if (init_attr->create_flags & 1506 (IB_QP_CREATE_CROSS_CHANNEL | 1507 IB_QP_CREATE_MANAGED_SEND | 1508 IB_QP_CREATE_MANAGED_RECV)) { 1509 if (!MLX5_CAP_GEN(mdev, cd)) { 1510 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1511 return -EINVAL; 1512 } 1513 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1514 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1515 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1516 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1517 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1518 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1519 } 1520 1521 if (init_attr->qp_type == IB_QPT_UD && 1522 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1523 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1524 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1525 return -EOPNOTSUPP; 1526 } 1527 1528 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1529 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1530 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1531 return -EOPNOTSUPP; 1532 } 1533 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1534 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1535 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1536 return -EOPNOTSUPP; 1537 } 1538 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1539 } 1540 1541 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1542 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1543 1544 if (pd && pd->uobject) { 1545 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1546 mlx5_ib_dbg(dev, "copy failed\n"); 1547 return -EFAULT; 1548 } 1549 1550 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1551 &ucmd, udata->inlen, &uidx); 1552 if (err) 1553 return err; 1554 1555 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1556 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1557 } else { 1558 qp->wq_sig = !!wq_signature; 1559 } 1560 1561 qp->has_rq = qp_has_rq(init_attr); 1562 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1563 qp, (pd && pd->uobject) ? &ucmd : NULL); 1564 if (err) { 1565 mlx5_ib_dbg(dev, "err %d\n", err); 1566 return err; 1567 } 1568 1569 if (pd) { 1570 if (pd->uobject) { 1571 __u32 max_wqes = 1572 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1573 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1574 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1575 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1576 mlx5_ib_dbg(dev, "invalid rq params\n"); 1577 return -EINVAL; 1578 } 1579 if (ucmd.sq_wqe_count > max_wqes) { 1580 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1581 ucmd.sq_wqe_count, max_wqes); 1582 return -EINVAL; 1583 } 1584 if (init_attr->create_flags & 1585 mlx5_ib_create_qp_sqpn_qp1()) { 1586 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1587 return -EINVAL; 1588 } 1589 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1590 &resp, &inlen, base); 1591 if (err) 1592 mlx5_ib_dbg(dev, "err %d\n", err); 1593 } else { 1594 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1595 base); 1596 if (err) 1597 mlx5_ib_dbg(dev, "err %d\n", err); 1598 } 1599 1600 if (err) 1601 return err; 1602 } else { 1603 in = mlx5_vzalloc(sizeof(*in)); 1604 if (!in) 1605 return -ENOMEM; 1606 1607 qp->create_type = MLX5_QP_EMPTY; 1608 } 1609 1610 if (is_sqp(init_attr->qp_type)) 1611 qp->port = init_attr->port_num; 1612 1613 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 1614 MLX5_QP_PM_MIGRATED << 11); 1615 1616 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1617 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 1618 else 1619 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 1620 1621 if (qp->wq_sig) 1622 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 1623 1624 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1625 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST); 1626 1627 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1628 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER); 1629 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1630 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND); 1631 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1632 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV); 1633 1634 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1635 int rcqe_sz; 1636 int scqe_sz; 1637 1638 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1639 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1640 1641 if (rcqe_sz == 128) 1642 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 1643 else 1644 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 1645 1646 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1647 if (scqe_sz == 128) 1648 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 1649 else 1650 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 1651 } 1652 } 1653 1654 if (qp->rq.wqe_cnt) { 1655 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 1656 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 1657 } 1658 1659 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 1660 1661 if (qp->sq.wqe_cnt) 1662 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 1663 else 1664 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 1665 1666 /* Set default resources */ 1667 switch (init_attr->qp_type) { 1668 case IB_QPT_XRC_TGT: 1669 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1670 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1671 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1672 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 1673 break; 1674 case IB_QPT_XRC_INI: 1675 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1676 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1677 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1678 break; 1679 default: 1680 if (init_attr->srq) { 1681 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 1682 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 1683 } else { 1684 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1685 in->ctx.rq_type_srqn |= 1686 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn); 1687 } 1688 } 1689 1690 if (init_attr->send_cq) 1691 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 1692 1693 if (init_attr->recv_cq) 1694 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 1695 1696 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 1697 1698 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) { 1699 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1700 /* 0xffffff means we ask to work with cqe version 0 */ 1701 MLX5_SET(qpc, qpc, user_index, uidx); 1702 } 1703 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1704 if (init_attr->qp_type == IB_QPT_UD && 1705 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1706 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1707 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1708 qp->flags |= MLX5_IB_QP_LSO; 1709 } 1710 1711 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1712 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1713 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1714 err = create_raw_packet_qp(dev, qp, in, pd); 1715 } else { 1716 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1717 } 1718 1719 if (err) { 1720 mlx5_ib_dbg(dev, "create qp failed\n"); 1721 goto err_create; 1722 } 1723 1724 kvfree(in); 1725 1726 base->container_mibqp = qp; 1727 base->mqp.event = mlx5_ib_qp_event; 1728 1729 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1730 &send_cq, &recv_cq); 1731 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1732 mlx5_ib_lock_cqs(send_cq, recv_cq); 1733 /* Maintain device to QPs access, needed for further handling via reset 1734 * flow 1735 */ 1736 list_add_tail(&qp->qps_list, &dev->qp_list); 1737 /* Maintain CQ to QPs access, needed for further handling via reset flow 1738 */ 1739 if (send_cq) 1740 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1741 if (recv_cq) 1742 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1743 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1744 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1745 1746 return 0; 1747 1748 err_create: 1749 if (qp->create_type == MLX5_QP_USER) 1750 destroy_qp_user(pd, qp, base); 1751 else if (qp->create_type == MLX5_QP_KERNEL) 1752 destroy_qp_kernel(dev, qp); 1753 1754 kvfree(in); 1755 return err; 1756 } 1757 1758 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1759 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1760 { 1761 if (send_cq) { 1762 if (recv_cq) { 1763 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1764 spin_lock(&send_cq->lock); 1765 spin_lock_nested(&recv_cq->lock, 1766 SINGLE_DEPTH_NESTING); 1767 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1768 spin_lock(&send_cq->lock); 1769 __acquire(&recv_cq->lock); 1770 } else { 1771 spin_lock(&recv_cq->lock); 1772 spin_lock_nested(&send_cq->lock, 1773 SINGLE_DEPTH_NESTING); 1774 } 1775 } else { 1776 spin_lock(&send_cq->lock); 1777 __acquire(&recv_cq->lock); 1778 } 1779 } else if (recv_cq) { 1780 spin_lock(&recv_cq->lock); 1781 __acquire(&send_cq->lock); 1782 } else { 1783 __acquire(&send_cq->lock); 1784 __acquire(&recv_cq->lock); 1785 } 1786 } 1787 1788 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1789 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1790 { 1791 if (send_cq) { 1792 if (recv_cq) { 1793 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1794 spin_unlock(&recv_cq->lock); 1795 spin_unlock(&send_cq->lock); 1796 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1797 __release(&recv_cq->lock); 1798 spin_unlock(&send_cq->lock); 1799 } else { 1800 spin_unlock(&send_cq->lock); 1801 spin_unlock(&recv_cq->lock); 1802 } 1803 } else { 1804 __release(&recv_cq->lock); 1805 spin_unlock(&send_cq->lock); 1806 } 1807 } else if (recv_cq) { 1808 __release(&send_cq->lock); 1809 spin_unlock(&recv_cq->lock); 1810 } else { 1811 __release(&recv_cq->lock); 1812 __release(&send_cq->lock); 1813 } 1814 } 1815 1816 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1817 { 1818 return to_mpd(qp->ibqp.pd); 1819 } 1820 1821 static void get_cqs(enum ib_qp_type qp_type, 1822 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1823 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1824 { 1825 switch (qp_type) { 1826 case IB_QPT_XRC_TGT: 1827 *send_cq = NULL; 1828 *recv_cq = NULL; 1829 break; 1830 case MLX5_IB_QPT_REG_UMR: 1831 case IB_QPT_XRC_INI: 1832 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1833 *recv_cq = NULL; 1834 break; 1835 1836 case IB_QPT_SMI: 1837 case MLX5_IB_QPT_HW_GSI: 1838 case IB_QPT_RC: 1839 case IB_QPT_UC: 1840 case IB_QPT_UD: 1841 case IB_QPT_RAW_IPV6: 1842 case IB_QPT_RAW_ETHERTYPE: 1843 case IB_QPT_RAW_PACKET: 1844 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1845 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1846 break; 1847 1848 case IB_QPT_MAX: 1849 default: 1850 *send_cq = NULL; 1851 *recv_cq = NULL; 1852 break; 1853 } 1854 } 1855 1856 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1857 u16 operation); 1858 1859 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1860 { 1861 struct mlx5_ib_cq *send_cq, *recv_cq; 1862 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1863 struct mlx5_modify_qp_mbox_in *in; 1864 unsigned long flags; 1865 int err; 1866 1867 if (qp->ibqp.rwq_ind_tbl) { 1868 destroy_rss_raw_qp_tir(dev, qp); 1869 return; 1870 } 1871 1872 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1873 &qp->raw_packet_qp.rq.base : 1874 &qp->trans_qp.base; 1875 1876 in = kzalloc(sizeof(*in), GFP_KERNEL); 1877 if (!in) 1878 return; 1879 1880 if (qp->state != IB_QPS_RESET) { 1881 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1882 mlx5_ib_qp_disable_pagefaults(qp); 1883 err = mlx5_core_qp_modify(dev->mdev, 1884 MLX5_CMD_OP_2RST_QP, in, 0, 1885 &base->mqp); 1886 } else { 1887 err = modify_raw_packet_qp(dev, qp, 1888 MLX5_CMD_OP_2RST_QP); 1889 } 1890 if (err) 1891 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1892 base->mqp.qpn); 1893 } 1894 1895 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 1896 &send_cq, &recv_cq); 1897 1898 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1899 mlx5_ib_lock_cqs(send_cq, recv_cq); 1900 /* del from lists under both locks above to protect reset flow paths */ 1901 list_del(&qp->qps_list); 1902 if (send_cq) 1903 list_del(&qp->cq_send_list); 1904 1905 if (recv_cq) 1906 list_del(&qp->cq_recv_list); 1907 1908 if (qp->create_type == MLX5_QP_KERNEL) { 1909 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1910 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1911 if (send_cq != recv_cq) 1912 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1913 NULL); 1914 } 1915 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1916 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1917 1918 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1919 destroy_raw_packet_qp(dev, qp); 1920 } else { 1921 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1922 if (err) 1923 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1924 base->mqp.qpn); 1925 } 1926 1927 kfree(in); 1928 1929 if (qp->create_type == MLX5_QP_KERNEL) 1930 destroy_qp_kernel(dev, qp); 1931 else if (qp->create_type == MLX5_QP_USER) 1932 destroy_qp_user(&get_pd(qp)->ibpd, qp, base); 1933 } 1934 1935 static const char *ib_qp_type_str(enum ib_qp_type type) 1936 { 1937 switch (type) { 1938 case IB_QPT_SMI: 1939 return "IB_QPT_SMI"; 1940 case IB_QPT_GSI: 1941 return "IB_QPT_GSI"; 1942 case IB_QPT_RC: 1943 return "IB_QPT_RC"; 1944 case IB_QPT_UC: 1945 return "IB_QPT_UC"; 1946 case IB_QPT_UD: 1947 return "IB_QPT_UD"; 1948 case IB_QPT_RAW_IPV6: 1949 return "IB_QPT_RAW_IPV6"; 1950 case IB_QPT_RAW_ETHERTYPE: 1951 return "IB_QPT_RAW_ETHERTYPE"; 1952 case IB_QPT_XRC_INI: 1953 return "IB_QPT_XRC_INI"; 1954 case IB_QPT_XRC_TGT: 1955 return "IB_QPT_XRC_TGT"; 1956 case IB_QPT_RAW_PACKET: 1957 return "IB_QPT_RAW_PACKET"; 1958 case MLX5_IB_QPT_REG_UMR: 1959 return "MLX5_IB_QPT_REG_UMR"; 1960 case IB_QPT_MAX: 1961 default: 1962 return "Invalid QP type"; 1963 } 1964 } 1965 1966 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1967 struct ib_qp_init_attr *init_attr, 1968 struct ib_udata *udata) 1969 { 1970 struct mlx5_ib_dev *dev; 1971 struct mlx5_ib_qp *qp; 1972 u16 xrcdn = 0; 1973 int err; 1974 1975 if (pd) { 1976 dev = to_mdev(pd->device); 1977 1978 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1979 if (!pd->uobject) { 1980 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 1981 return ERR_PTR(-EINVAL); 1982 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 1983 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 1984 return ERR_PTR(-EINVAL); 1985 } 1986 } 1987 } else { 1988 /* being cautious here */ 1989 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1990 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1991 pr_warn("%s: no PD for transport %s\n", __func__, 1992 ib_qp_type_str(init_attr->qp_type)); 1993 return ERR_PTR(-EINVAL); 1994 } 1995 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1996 } 1997 1998 switch (init_attr->qp_type) { 1999 case IB_QPT_XRC_TGT: 2000 case IB_QPT_XRC_INI: 2001 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2002 mlx5_ib_dbg(dev, "XRC not supported\n"); 2003 return ERR_PTR(-ENOSYS); 2004 } 2005 init_attr->recv_cq = NULL; 2006 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2007 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2008 init_attr->send_cq = NULL; 2009 } 2010 2011 /* fall through */ 2012 case IB_QPT_RAW_PACKET: 2013 case IB_QPT_RC: 2014 case IB_QPT_UC: 2015 case IB_QPT_UD: 2016 case IB_QPT_SMI: 2017 case MLX5_IB_QPT_HW_GSI: 2018 case MLX5_IB_QPT_REG_UMR: 2019 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2020 if (!qp) 2021 return ERR_PTR(-ENOMEM); 2022 2023 err = create_qp_common(dev, pd, init_attr, udata, qp); 2024 if (err) { 2025 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2026 kfree(qp); 2027 return ERR_PTR(err); 2028 } 2029 2030 if (is_qp0(init_attr->qp_type)) 2031 qp->ibqp.qp_num = 0; 2032 else if (is_qp1(init_attr->qp_type)) 2033 qp->ibqp.qp_num = 1; 2034 else 2035 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2036 2037 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2038 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2039 to_mcq(init_attr->recv_cq)->mcq.cqn, 2040 to_mcq(init_attr->send_cq)->mcq.cqn); 2041 2042 qp->trans_qp.xrcdn = xrcdn; 2043 2044 break; 2045 2046 case IB_QPT_GSI: 2047 return mlx5_ib_gsi_create_qp(pd, init_attr); 2048 2049 case IB_QPT_RAW_IPV6: 2050 case IB_QPT_RAW_ETHERTYPE: 2051 case IB_QPT_MAX: 2052 default: 2053 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2054 init_attr->qp_type); 2055 /* Don't support raw QPs */ 2056 return ERR_PTR(-EINVAL); 2057 } 2058 2059 return &qp->ibqp; 2060 } 2061 2062 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2063 { 2064 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2065 struct mlx5_ib_qp *mqp = to_mqp(qp); 2066 2067 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2068 return mlx5_ib_gsi_destroy_qp(qp); 2069 2070 destroy_qp_common(dev, mqp); 2071 2072 kfree(mqp); 2073 2074 return 0; 2075 } 2076 2077 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2078 int attr_mask) 2079 { 2080 u32 hw_access_flags = 0; 2081 u8 dest_rd_atomic; 2082 u32 access_flags; 2083 2084 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2085 dest_rd_atomic = attr->max_dest_rd_atomic; 2086 else 2087 dest_rd_atomic = qp->trans_qp.resp_depth; 2088 2089 if (attr_mask & IB_QP_ACCESS_FLAGS) 2090 access_flags = attr->qp_access_flags; 2091 else 2092 access_flags = qp->trans_qp.atomic_rd_en; 2093 2094 if (!dest_rd_atomic) 2095 access_flags &= IB_ACCESS_REMOTE_WRITE; 2096 2097 if (access_flags & IB_ACCESS_REMOTE_READ) 2098 hw_access_flags |= MLX5_QP_BIT_RRE; 2099 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2100 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2101 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2102 hw_access_flags |= MLX5_QP_BIT_RWE; 2103 2104 return cpu_to_be32(hw_access_flags); 2105 } 2106 2107 enum { 2108 MLX5_PATH_FLAG_FL = 1 << 0, 2109 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2110 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2111 }; 2112 2113 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2114 { 2115 if (rate == IB_RATE_PORT_CURRENT) { 2116 return 0; 2117 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2118 return -EINVAL; 2119 } else { 2120 while (rate != IB_RATE_2_5_GBPS && 2121 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2122 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2123 --rate; 2124 } 2125 2126 return rate + MLX5_STAT_RATE_OFFSET; 2127 } 2128 2129 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2130 struct mlx5_ib_sq *sq, u8 sl) 2131 { 2132 void *in; 2133 void *tisc; 2134 int inlen; 2135 int err; 2136 2137 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2138 in = mlx5_vzalloc(inlen); 2139 if (!in) 2140 return -ENOMEM; 2141 2142 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2143 2144 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2145 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2146 2147 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2148 2149 kvfree(in); 2150 2151 return err; 2152 } 2153 2154 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2155 const struct ib_ah_attr *ah, 2156 struct mlx5_qp_path *path, u8 port, int attr_mask, 2157 u32 path_flags, const struct ib_qp_attr *attr, 2158 bool alt) 2159 { 2160 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2161 int err; 2162 2163 if (attr_mask & IB_QP_PKEY_INDEX) 2164 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2165 attr->pkey_index); 2166 2167 if (ah->ah_flags & IB_AH_GRH) { 2168 if (ah->grh.sgid_index >= 2169 dev->mdev->port_caps[port - 1].gid_table_len) { 2170 pr_err("sgid_index (%u) too large. max is %d\n", 2171 ah->grh.sgid_index, 2172 dev->mdev->port_caps[port - 1].gid_table_len); 2173 return -EINVAL; 2174 } 2175 } 2176 2177 if (ll == IB_LINK_LAYER_ETHERNET) { 2178 if (!(ah->ah_flags & IB_AH_GRH)) 2179 return -EINVAL; 2180 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2181 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2182 ah->grh.sgid_index); 2183 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2184 } else { 2185 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2186 path->fl_free_ar |= 2187 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2188 path->rlid = cpu_to_be16(ah->dlid); 2189 path->grh_mlid = ah->src_path_bits & 0x7f; 2190 if (ah->ah_flags & IB_AH_GRH) 2191 path->grh_mlid |= 1 << 7; 2192 path->dci_cfi_prio_sl = ah->sl & 0xf; 2193 } 2194 2195 if (ah->ah_flags & IB_AH_GRH) { 2196 path->mgid_index = ah->grh.sgid_index; 2197 path->hop_limit = ah->grh.hop_limit; 2198 path->tclass_flowlabel = 2199 cpu_to_be32((ah->grh.traffic_class << 20) | 2200 (ah->grh.flow_label)); 2201 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2202 } 2203 2204 err = ib_rate_to_mlx5(dev, ah->static_rate); 2205 if (err < 0) 2206 return err; 2207 path->static_rate = err; 2208 path->port = port; 2209 2210 if (attr_mask & IB_QP_TIMEOUT) 2211 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2212 2213 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2214 return modify_raw_packet_eth_prio(dev->mdev, 2215 &qp->raw_packet_qp.sq, 2216 ah->sl & 0xf); 2217 2218 return 0; 2219 } 2220 2221 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2222 [MLX5_QP_STATE_INIT] = { 2223 [MLX5_QP_STATE_INIT] = { 2224 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2225 MLX5_QP_OPTPAR_RAE | 2226 MLX5_QP_OPTPAR_RWE | 2227 MLX5_QP_OPTPAR_PKEY_INDEX | 2228 MLX5_QP_OPTPAR_PRI_PORT, 2229 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2230 MLX5_QP_OPTPAR_PKEY_INDEX | 2231 MLX5_QP_OPTPAR_PRI_PORT, 2232 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2233 MLX5_QP_OPTPAR_Q_KEY | 2234 MLX5_QP_OPTPAR_PRI_PORT, 2235 }, 2236 [MLX5_QP_STATE_RTR] = { 2237 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2238 MLX5_QP_OPTPAR_RRE | 2239 MLX5_QP_OPTPAR_RAE | 2240 MLX5_QP_OPTPAR_RWE | 2241 MLX5_QP_OPTPAR_PKEY_INDEX, 2242 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2243 MLX5_QP_OPTPAR_RWE | 2244 MLX5_QP_OPTPAR_PKEY_INDEX, 2245 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2246 MLX5_QP_OPTPAR_Q_KEY, 2247 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2248 MLX5_QP_OPTPAR_Q_KEY, 2249 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2250 MLX5_QP_OPTPAR_RRE | 2251 MLX5_QP_OPTPAR_RAE | 2252 MLX5_QP_OPTPAR_RWE | 2253 MLX5_QP_OPTPAR_PKEY_INDEX, 2254 }, 2255 }, 2256 [MLX5_QP_STATE_RTR] = { 2257 [MLX5_QP_STATE_RTS] = { 2258 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2259 MLX5_QP_OPTPAR_RRE | 2260 MLX5_QP_OPTPAR_RAE | 2261 MLX5_QP_OPTPAR_RWE | 2262 MLX5_QP_OPTPAR_PM_STATE | 2263 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2264 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2265 MLX5_QP_OPTPAR_RWE | 2266 MLX5_QP_OPTPAR_PM_STATE, 2267 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2268 }, 2269 }, 2270 [MLX5_QP_STATE_RTS] = { 2271 [MLX5_QP_STATE_RTS] = { 2272 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2273 MLX5_QP_OPTPAR_RAE | 2274 MLX5_QP_OPTPAR_RWE | 2275 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2276 MLX5_QP_OPTPAR_PM_STATE | 2277 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2278 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2279 MLX5_QP_OPTPAR_PM_STATE | 2280 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2281 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2282 MLX5_QP_OPTPAR_SRQN | 2283 MLX5_QP_OPTPAR_CQN_RCV, 2284 }, 2285 }, 2286 [MLX5_QP_STATE_SQER] = { 2287 [MLX5_QP_STATE_RTS] = { 2288 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2289 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2290 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2291 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2292 MLX5_QP_OPTPAR_RWE | 2293 MLX5_QP_OPTPAR_RAE | 2294 MLX5_QP_OPTPAR_RRE, 2295 }, 2296 }, 2297 }; 2298 2299 static int ib_nr_to_mlx5_nr(int ib_mask) 2300 { 2301 switch (ib_mask) { 2302 case IB_QP_STATE: 2303 return 0; 2304 case IB_QP_CUR_STATE: 2305 return 0; 2306 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2307 return 0; 2308 case IB_QP_ACCESS_FLAGS: 2309 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2310 MLX5_QP_OPTPAR_RAE; 2311 case IB_QP_PKEY_INDEX: 2312 return MLX5_QP_OPTPAR_PKEY_INDEX; 2313 case IB_QP_PORT: 2314 return MLX5_QP_OPTPAR_PRI_PORT; 2315 case IB_QP_QKEY: 2316 return MLX5_QP_OPTPAR_Q_KEY; 2317 case IB_QP_AV: 2318 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2319 MLX5_QP_OPTPAR_PRI_PORT; 2320 case IB_QP_PATH_MTU: 2321 return 0; 2322 case IB_QP_TIMEOUT: 2323 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2324 case IB_QP_RETRY_CNT: 2325 return MLX5_QP_OPTPAR_RETRY_COUNT; 2326 case IB_QP_RNR_RETRY: 2327 return MLX5_QP_OPTPAR_RNR_RETRY; 2328 case IB_QP_RQ_PSN: 2329 return 0; 2330 case IB_QP_MAX_QP_RD_ATOMIC: 2331 return MLX5_QP_OPTPAR_SRA_MAX; 2332 case IB_QP_ALT_PATH: 2333 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2334 case IB_QP_MIN_RNR_TIMER: 2335 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2336 case IB_QP_SQ_PSN: 2337 return 0; 2338 case IB_QP_MAX_DEST_RD_ATOMIC: 2339 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2340 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2341 case IB_QP_PATH_MIG_STATE: 2342 return MLX5_QP_OPTPAR_PM_STATE; 2343 case IB_QP_CAP: 2344 return 0; 2345 case IB_QP_DEST_QPN: 2346 return 0; 2347 } 2348 return 0; 2349 } 2350 2351 static int ib_mask_to_mlx5_opt(int ib_mask) 2352 { 2353 int result = 0; 2354 int i; 2355 2356 for (i = 0; i < 8 * sizeof(int); i++) { 2357 if ((1 << i) & ib_mask) 2358 result |= ib_nr_to_mlx5_nr(1 << i); 2359 } 2360 2361 return result; 2362 } 2363 2364 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev, 2365 struct mlx5_ib_rq *rq, int new_state) 2366 { 2367 void *in; 2368 void *rqc; 2369 int inlen; 2370 int err; 2371 2372 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2373 in = mlx5_vzalloc(inlen); 2374 if (!in) 2375 return -ENOMEM; 2376 2377 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2378 2379 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2380 MLX5_SET(rqc, rqc, state, new_state); 2381 2382 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen); 2383 if (err) 2384 goto out; 2385 2386 rq->state = new_state; 2387 2388 out: 2389 kvfree(in); 2390 return err; 2391 } 2392 2393 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2394 struct mlx5_ib_sq *sq, int new_state) 2395 { 2396 void *in; 2397 void *sqc; 2398 int inlen; 2399 int err; 2400 2401 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2402 in = mlx5_vzalloc(inlen); 2403 if (!in) 2404 return -ENOMEM; 2405 2406 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2407 2408 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2409 MLX5_SET(sqc, sqc, state, new_state); 2410 2411 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2412 if (err) 2413 goto out; 2414 2415 sq->state = new_state; 2416 2417 out: 2418 kvfree(in); 2419 return err; 2420 } 2421 2422 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2423 u16 operation) 2424 { 2425 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2426 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2427 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2428 int rq_state; 2429 int sq_state; 2430 int err; 2431 2432 switch (operation) { 2433 case MLX5_CMD_OP_RST2INIT_QP: 2434 rq_state = MLX5_RQC_STATE_RDY; 2435 sq_state = MLX5_SQC_STATE_RDY; 2436 break; 2437 case MLX5_CMD_OP_2ERR_QP: 2438 rq_state = MLX5_RQC_STATE_ERR; 2439 sq_state = MLX5_SQC_STATE_ERR; 2440 break; 2441 case MLX5_CMD_OP_2RST_QP: 2442 rq_state = MLX5_RQC_STATE_RST; 2443 sq_state = MLX5_SQC_STATE_RST; 2444 break; 2445 case MLX5_CMD_OP_INIT2INIT_QP: 2446 case MLX5_CMD_OP_INIT2RTR_QP: 2447 case MLX5_CMD_OP_RTR2RTS_QP: 2448 case MLX5_CMD_OP_RTS2RTS_QP: 2449 /* Nothing to do here... */ 2450 return 0; 2451 default: 2452 WARN_ON(1); 2453 return -EINVAL; 2454 } 2455 2456 if (qp->rq.wqe_cnt) { 2457 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state); 2458 if (err) 2459 return err; 2460 } 2461 2462 if (qp->sq.wqe_cnt) 2463 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2464 2465 return 0; 2466 } 2467 2468 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2469 const struct ib_qp_attr *attr, int attr_mask, 2470 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2471 { 2472 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2473 [MLX5_QP_STATE_RST] = { 2474 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2475 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2476 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2477 }, 2478 [MLX5_QP_STATE_INIT] = { 2479 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2480 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2481 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2482 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2483 }, 2484 [MLX5_QP_STATE_RTR] = { 2485 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2486 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2487 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2488 }, 2489 [MLX5_QP_STATE_RTS] = { 2490 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2491 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2492 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2493 }, 2494 [MLX5_QP_STATE_SQD] = { 2495 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2496 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2497 }, 2498 [MLX5_QP_STATE_SQER] = { 2499 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2500 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2501 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2502 }, 2503 [MLX5_QP_STATE_ERR] = { 2504 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2505 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2506 } 2507 }; 2508 2509 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2510 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2511 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2512 struct mlx5_ib_cq *send_cq, *recv_cq; 2513 struct mlx5_qp_context *context; 2514 struct mlx5_modify_qp_mbox_in *in; 2515 struct mlx5_ib_pd *pd; 2516 enum mlx5_qp_state mlx5_cur, mlx5_new; 2517 enum mlx5_qp_optpar optpar; 2518 int sqd_event; 2519 int mlx5_st; 2520 int err; 2521 u16 op; 2522 2523 in = kzalloc(sizeof(*in), GFP_KERNEL); 2524 if (!in) 2525 return -ENOMEM; 2526 2527 context = &in->ctx; 2528 err = to_mlx5_st(ibqp->qp_type); 2529 if (err < 0) { 2530 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2531 goto out; 2532 } 2533 2534 context->flags = cpu_to_be32(err << 16); 2535 2536 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2537 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2538 } else { 2539 switch (attr->path_mig_state) { 2540 case IB_MIG_MIGRATED: 2541 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2542 break; 2543 case IB_MIG_REARM: 2544 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2545 break; 2546 case IB_MIG_ARMED: 2547 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2548 break; 2549 } 2550 } 2551 2552 if (is_sqp(ibqp->qp_type)) { 2553 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2554 } else if (ibqp->qp_type == IB_QPT_UD || 2555 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2556 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2557 } else if (attr_mask & IB_QP_PATH_MTU) { 2558 if (attr->path_mtu < IB_MTU_256 || 2559 attr->path_mtu > IB_MTU_4096) { 2560 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2561 err = -EINVAL; 2562 goto out; 2563 } 2564 context->mtu_msgmax = (attr->path_mtu << 5) | 2565 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2566 } 2567 2568 if (attr_mask & IB_QP_DEST_QPN) 2569 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2570 2571 if (attr_mask & IB_QP_PKEY_INDEX) 2572 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2573 2574 /* todo implement counter_index functionality */ 2575 2576 if (is_sqp(ibqp->qp_type)) 2577 context->pri_path.port = qp->port; 2578 2579 if (attr_mask & IB_QP_PORT) 2580 context->pri_path.port = attr->port_num; 2581 2582 if (attr_mask & IB_QP_AV) { 2583 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2584 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2585 attr_mask, 0, attr, false); 2586 if (err) 2587 goto out; 2588 } 2589 2590 if (attr_mask & IB_QP_TIMEOUT) 2591 context->pri_path.ackto_lt |= attr->timeout << 3; 2592 2593 if (attr_mask & IB_QP_ALT_PATH) { 2594 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2595 &context->alt_path, 2596 attr->alt_port_num, 2597 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2598 0, attr, true); 2599 if (err) 2600 goto out; 2601 } 2602 2603 pd = get_pd(qp); 2604 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2605 &send_cq, &recv_cq); 2606 2607 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2608 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2609 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2610 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2611 2612 if (attr_mask & IB_QP_RNR_RETRY) 2613 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2614 2615 if (attr_mask & IB_QP_RETRY_CNT) 2616 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2617 2618 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2619 if (attr->max_rd_atomic) 2620 context->params1 |= 2621 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2622 } 2623 2624 if (attr_mask & IB_QP_SQ_PSN) 2625 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2626 2627 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2628 if (attr->max_dest_rd_atomic) 2629 context->params2 |= 2630 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2631 } 2632 2633 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2634 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2635 2636 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2637 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2638 2639 if (attr_mask & IB_QP_RQ_PSN) 2640 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2641 2642 if (attr_mask & IB_QP_QKEY) 2643 context->qkey = cpu_to_be32(attr->qkey); 2644 2645 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2646 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2647 2648 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2649 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2650 sqd_event = 1; 2651 else 2652 sqd_event = 0; 2653 2654 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2655 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2656 qp->port) - 1; 2657 struct mlx5_ib_port *mibport = &dev->port[port_num]; 2658 2659 context->qp_counter_set_usr_page |= 2660 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2661 } 2662 2663 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2664 context->sq_crq_size |= cpu_to_be16(1 << 4); 2665 2666 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2667 context->deth_sqpn = cpu_to_be32(1); 2668 2669 mlx5_cur = to_mlx5_state(cur_state); 2670 mlx5_new = to_mlx5_state(new_state); 2671 mlx5_st = to_mlx5_st(ibqp->qp_type); 2672 if (mlx5_st < 0) 2673 goto out; 2674 2675 /* If moving to a reset or error state, we must disable page faults on 2676 * this QP and flush all current page faults. Otherwise a stale page 2677 * fault may attempt to work on this QP after it is reset and moved 2678 * again to RTS, and may cause the driver and the device to get out of 2679 * sync. */ 2680 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2681 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2682 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2683 mlx5_ib_qp_disable_pagefaults(qp); 2684 2685 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2686 !optab[mlx5_cur][mlx5_new]) 2687 goto out; 2688 2689 op = optab[mlx5_cur][mlx5_new]; 2690 optpar = ib_mask_to_mlx5_opt(attr_mask); 2691 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2692 in->optparam = cpu_to_be32(optpar); 2693 2694 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) 2695 err = modify_raw_packet_qp(dev, qp, op); 2696 else 2697 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event, 2698 &base->mqp); 2699 if (err) 2700 goto out; 2701 2702 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2703 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2704 mlx5_ib_qp_enable_pagefaults(qp); 2705 2706 qp->state = new_state; 2707 2708 if (attr_mask & IB_QP_ACCESS_FLAGS) 2709 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2710 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2711 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2712 if (attr_mask & IB_QP_PORT) 2713 qp->port = attr->port_num; 2714 if (attr_mask & IB_QP_ALT_PATH) 2715 qp->trans_qp.alt_port = attr->alt_port_num; 2716 2717 /* 2718 * If we moved a kernel QP to RESET, clean up all old CQ 2719 * entries and reinitialize the QP. 2720 */ 2721 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2722 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2723 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2724 if (send_cq != recv_cq) 2725 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2726 2727 qp->rq.head = 0; 2728 qp->rq.tail = 0; 2729 qp->sq.head = 0; 2730 qp->sq.tail = 0; 2731 qp->sq.cur_post = 0; 2732 qp->sq.last_poll = 0; 2733 qp->db.db[MLX5_RCV_DBR] = 0; 2734 qp->db.db[MLX5_SND_DBR] = 0; 2735 } 2736 2737 out: 2738 kfree(in); 2739 return err; 2740 } 2741 2742 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2743 int attr_mask, struct ib_udata *udata) 2744 { 2745 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2746 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2747 enum ib_qp_type qp_type; 2748 enum ib_qp_state cur_state, new_state; 2749 int err = -EINVAL; 2750 int port; 2751 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2752 2753 if (ibqp->rwq_ind_tbl) 2754 return -ENOSYS; 2755 2756 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2757 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2758 2759 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2760 IB_QPT_GSI : ibqp->qp_type; 2761 2762 mutex_lock(&qp->mutex); 2763 2764 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2765 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2766 2767 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2768 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2769 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2770 } 2771 2772 if (qp_type != MLX5_IB_QPT_REG_UMR && 2773 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2774 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2775 cur_state, new_state, ibqp->qp_type, attr_mask); 2776 goto out; 2777 } 2778 2779 if ((attr_mask & IB_QP_PORT) && 2780 (attr->port_num == 0 || 2781 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2782 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2783 attr->port_num, dev->num_ports); 2784 goto out; 2785 } 2786 2787 if (attr_mask & IB_QP_PKEY_INDEX) { 2788 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2789 if (attr->pkey_index >= 2790 dev->mdev->port_caps[port - 1].pkey_table_len) { 2791 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2792 attr->pkey_index); 2793 goto out; 2794 } 2795 } 2796 2797 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2798 attr->max_rd_atomic > 2799 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2800 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2801 attr->max_rd_atomic); 2802 goto out; 2803 } 2804 2805 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2806 attr->max_dest_rd_atomic > 2807 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 2808 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 2809 attr->max_dest_rd_atomic); 2810 goto out; 2811 } 2812 2813 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2814 err = 0; 2815 goto out; 2816 } 2817 2818 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2819 2820 out: 2821 mutex_unlock(&qp->mutex); 2822 return err; 2823 } 2824 2825 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2826 { 2827 struct mlx5_ib_cq *cq; 2828 unsigned cur; 2829 2830 cur = wq->head - wq->tail; 2831 if (likely(cur + nreq < wq->max_post)) 2832 return 0; 2833 2834 cq = to_mcq(ib_cq); 2835 spin_lock(&cq->lock); 2836 cur = wq->head - wq->tail; 2837 spin_unlock(&cq->lock); 2838 2839 return cur + nreq >= wq->max_post; 2840 } 2841 2842 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 2843 u64 remote_addr, u32 rkey) 2844 { 2845 rseg->raddr = cpu_to_be64(remote_addr); 2846 rseg->rkey = cpu_to_be32(rkey); 2847 rseg->reserved = 0; 2848 } 2849 2850 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 2851 struct ib_send_wr *wr, void *qend, 2852 struct mlx5_ib_qp *qp, int *size) 2853 { 2854 void *seg = eseg; 2855 2856 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 2857 2858 if (wr->send_flags & IB_SEND_IP_CSUM) 2859 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 2860 MLX5_ETH_WQE_L4_CSUM; 2861 2862 seg += sizeof(struct mlx5_wqe_eth_seg); 2863 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 2864 2865 if (wr->opcode == IB_WR_LSO) { 2866 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 2867 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 2868 u64 left, leftlen, copysz; 2869 void *pdata = ud_wr->header; 2870 2871 left = ud_wr->hlen; 2872 eseg->mss = cpu_to_be16(ud_wr->mss); 2873 eseg->inline_hdr_sz = cpu_to_be16(left); 2874 2875 /* 2876 * check if there is space till the end of queue, if yes, 2877 * copy all in one shot, otherwise copy till the end of queue, 2878 * rollback and than the copy the left 2879 */ 2880 leftlen = qend - (void *)eseg->inline_hdr_start; 2881 copysz = min_t(u64, leftlen, left); 2882 2883 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 2884 2885 if (likely(copysz > size_of_inl_hdr_start)) { 2886 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 2887 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 2888 } 2889 2890 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 2891 seg = mlx5_get_send_wqe(qp, 0); 2892 left -= copysz; 2893 pdata += copysz; 2894 memcpy(seg, pdata, left); 2895 seg += ALIGN(left, 16); 2896 *size += ALIGN(left, 16) / 16; 2897 } 2898 } 2899 2900 return seg; 2901 } 2902 2903 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 2904 struct ib_send_wr *wr) 2905 { 2906 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 2907 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 2908 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 2909 } 2910 2911 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 2912 { 2913 dseg->byte_count = cpu_to_be32(sg->length); 2914 dseg->lkey = cpu_to_be32(sg->lkey); 2915 dseg->addr = cpu_to_be64(sg->addr); 2916 } 2917 2918 static __be16 get_klm_octo(int npages) 2919 { 2920 return cpu_to_be16(ALIGN(npages, 8) / 2); 2921 } 2922 2923 static __be64 frwr_mkey_mask(void) 2924 { 2925 u64 result; 2926 2927 result = MLX5_MKEY_MASK_LEN | 2928 MLX5_MKEY_MASK_PAGE_SIZE | 2929 MLX5_MKEY_MASK_START_ADDR | 2930 MLX5_MKEY_MASK_EN_RINVAL | 2931 MLX5_MKEY_MASK_KEY | 2932 MLX5_MKEY_MASK_LR | 2933 MLX5_MKEY_MASK_LW | 2934 MLX5_MKEY_MASK_RR | 2935 MLX5_MKEY_MASK_RW | 2936 MLX5_MKEY_MASK_A | 2937 MLX5_MKEY_MASK_SMALL_FENCE | 2938 MLX5_MKEY_MASK_FREE; 2939 2940 return cpu_to_be64(result); 2941 } 2942 2943 static __be64 sig_mkey_mask(void) 2944 { 2945 u64 result; 2946 2947 result = MLX5_MKEY_MASK_LEN | 2948 MLX5_MKEY_MASK_PAGE_SIZE | 2949 MLX5_MKEY_MASK_START_ADDR | 2950 MLX5_MKEY_MASK_EN_SIGERR | 2951 MLX5_MKEY_MASK_EN_RINVAL | 2952 MLX5_MKEY_MASK_KEY | 2953 MLX5_MKEY_MASK_LR | 2954 MLX5_MKEY_MASK_LW | 2955 MLX5_MKEY_MASK_RR | 2956 MLX5_MKEY_MASK_RW | 2957 MLX5_MKEY_MASK_SMALL_FENCE | 2958 MLX5_MKEY_MASK_FREE | 2959 MLX5_MKEY_MASK_BSF_EN; 2960 2961 return cpu_to_be64(result); 2962 } 2963 2964 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 2965 struct mlx5_ib_mr *mr) 2966 { 2967 int ndescs = mr->ndescs; 2968 2969 memset(umr, 0, sizeof(*umr)); 2970 2971 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 2972 /* KLMs take twice the size of MTTs */ 2973 ndescs *= 2; 2974 2975 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 2976 umr->klm_octowords = get_klm_octo(ndescs); 2977 umr->mkey_mask = frwr_mkey_mask(); 2978 } 2979 2980 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 2981 { 2982 memset(umr, 0, sizeof(*umr)); 2983 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 2984 umr->flags = 1 << 7; 2985 } 2986 2987 static __be64 get_umr_reg_mr_mask(void) 2988 { 2989 u64 result; 2990 2991 result = MLX5_MKEY_MASK_LEN | 2992 MLX5_MKEY_MASK_PAGE_SIZE | 2993 MLX5_MKEY_MASK_START_ADDR | 2994 MLX5_MKEY_MASK_PD | 2995 MLX5_MKEY_MASK_LR | 2996 MLX5_MKEY_MASK_LW | 2997 MLX5_MKEY_MASK_KEY | 2998 MLX5_MKEY_MASK_RR | 2999 MLX5_MKEY_MASK_RW | 3000 MLX5_MKEY_MASK_A | 3001 MLX5_MKEY_MASK_FREE; 3002 3003 return cpu_to_be64(result); 3004 } 3005 3006 static __be64 get_umr_unreg_mr_mask(void) 3007 { 3008 u64 result; 3009 3010 result = MLX5_MKEY_MASK_FREE; 3011 3012 return cpu_to_be64(result); 3013 } 3014 3015 static __be64 get_umr_update_mtt_mask(void) 3016 { 3017 u64 result; 3018 3019 result = MLX5_MKEY_MASK_FREE; 3020 3021 return cpu_to_be64(result); 3022 } 3023 3024 static __be64 get_umr_update_translation_mask(void) 3025 { 3026 u64 result; 3027 3028 result = MLX5_MKEY_MASK_LEN | 3029 MLX5_MKEY_MASK_PAGE_SIZE | 3030 MLX5_MKEY_MASK_START_ADDR | 3031 MLX5_MKEY_MASK_KEY | 3032 MLX5_MKEY_MASK_FREE; 3033 3034 return cpu_to_be64(result); 3035 } 3036 3037 static __be64 get_umr_update_access_mask(void) 3038 { 3039 u64 result; 3040 3041 result = MLX5_MKEY_MASK_LW | 3042 MLX5_MKEY_MASK_RR | 3043 MLX5_MKEY_MASK_RW | 3044 MLX5_MKEY_MASK_A | 3045 MLX5_MKEY_MASK_KEY | 3046 MLX5_MKEY_MASK_FREE; 3047 3048 return cpu_to_be64(result); 3049 } 3050 3051 static __be64 get_umr_update_pd_mask(void) 3052 { 3053 u64 result; 3054 3055 result = MLX5_MKEY_MASK_PD | 3056 MLX5_MKEY_MASK_KEY | 3057 MLX5_MKEY_MASK_FREE; 3058 3059 return cpu_to_be64(result); 3060 } 3061 3062 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3063 struct ib_send_wr *wr) 3064 { 3065 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3066 3067 memset(umr, 0, sizeof(*umr)); 3068 3069 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3070 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3071 else 3072 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3073 3074 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3075 umr->klm_octowords = get_klm_octo(umrwr->npages); 3076 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3077 umr->mkey_mask = get_umr_update_mtt_mask(); 3078 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3079 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3080 } 3081 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3082 umr->mkey_mask |= get_umr_update_translation_mask(); 3083 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3084 umr->mkey_mask |= get_umr_update_access_mask(); 3085 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3086 umr->mkey_mask |= get_umr_update_pd_mask(); 3087 if (!umr->mkey_mask) 3088 umr->mkey_mask = get_umr_reg_mr_mask(); 3089 } else { 3090 umr->mkey_mask = get_umr_unreg_mr_mask(); 3091 } 3092 3093 if (!wr->num_sge) 3094 umr->flags |= MLX5_UMR_INLINE; 3095 } 3096 3097 static u8 get_umr_flags(int acc) 3098 { 3099 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3100 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3101 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3102 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3103 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3104 } 3105 3106 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3107 struct mlx5_ib_mr *mr, 3108 u32 key, int access) 3109 { 3110 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3111 3112 memset(seg, 0, sizeof(*seg)); 3113 3114 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3115 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3116 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3117 /* KLMs take twice the size of MTTs */ 3118 ndescs *= 2; 3119 3120 seg->flags = get_umr_flags(access) | mr->access_mode; 3121 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3122 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3123 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3124 seg->len = cpu_to_be64(mr->ibmr.length); 3125 seg->xlt_oct_size = cpu_to_be32(ndescs); 3126 } 3127 3128 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3129 { 3130 memset(seg, 0, sizeof(*seg)); 3131 seg->status = MLX5_MKEY_STATUS_FREE; 3132 } 3133 3134 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3135 { 3136 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3137 3138 memset(seg, 0, sizeof(*seg)); 3139 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3140 seg->status = MLX5_MKEY_STATUS_FREE; 3141 return; 3142 } 3143 3144 seg->flags = convert_access(umrwr->access_flags); 3145 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3146 if (umrwr->pd) 3147 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3148 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3149 } 3150 seg->len = cpu_to_be64(umrwr->length); 3151 seg->log2_page_size = umrwr->page_shift; 3152 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3153 mlx5_mkey_variant(umrwr->mkey)); 3154 } 3155 3156 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3157 struct mlx5_ib_mr *mr, 3158 struct mlx5_ib_pd *pd) 3159 { 3160 int bcount = mr->desc_size * mr->ndescs; 3161 3162 dseg->addr = cpu_to_be64(mr->desc_map); 3163 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3164 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3165 } 3166 3167 static __be32 send_ieth(struct ib_send_wr *wr) 3168 { 3169 switch (wr->opcode) { 3170 case IB_WR_SEND_WITH_IMM: 3171 case IB_WR_RDMA_WRITE_WITH_IMM: 3172 return wr->ex.imm_data; 3173 3174 case IB_WR_SEND_WITH_INV: 3175 return cpu_to_be32(wr->ex.invalidate_rkey); 3176 3177 default: 3178 return 0; 3179 } 3180 } 3181 3182 static u8 calc_sig(void *wqe, int size) 3183 { 3184 u8 *p = wqe; 3185 u8 res = 0; 3186 int i; 3187 3188 for (i = 0; i < size; i++) 3189 res ^= p[i]; 3190 3191 return ~res; 3192 } 3193 3194 static u8 wq_sig(void *wqe) 3195 { 3196 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3197 } 3198 3199 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3200 void *wqe, int *sz) 3201 { 3202 struct mlx5_wqe_inline_seg *seg; 3203 void *qend = qp->sq.qend; 3204 void *addr; 3205 int inl = 0; 3206 int copy; 3207 int len; 3208 int i; 3209 3210 seg = wqe; 3211 wqe += sizeof(*seg); 3212 for (i = 0; i < wr->num_sge; i++) { 3213 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3214 len = wr->sg_list[i].length; 3215 inl += len; 3216 3217 if (unlikely(inl > qp->max_inline_data)) 3218 return -ENOMEM; 3219 3220 if (unlikely(wqe + len > qend)) { 3221 copy = qend - wqe; 3222 memcpy(wqe, addr, copy); 3223 addr += copy; 3224 len -= copy; 3225 wqe = mlx5_get_send_wqe(qp, 0); 3226 } 3227 memcpy(wqe, addr, len); 3228 wqe += len; 3229 } 3230 3231 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3232 3233 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3234 3235 return 0; 3236 } 3237 3238 static u16 prot_field_size(enum ib_signature_type type) 3239 { 3240 switch (type) { 3241 case IB_SIG_TYPE_T10_DIF: 3242 return MLX5_DIF_SIZE; 3243 default: 3244 return 0; 3245 } 3246 } 3247 3248 static u8 bs_selector(int block_size) 3249 { 3250 switch (block_size) { 3251 case 512: return 0x1; 3252 case 520: return 0x2; 3253 case 4096: return 0x3; 3254 case 4160: return 0x4; 3255 case 1073741824: return 0x5; 3256 default: return 0; 3257 } 3258 } 3259 3260 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3261 struct mlx5_bsf_inl *inl) 3262 { 3263 /* Valid inline section and allow BSF refresh */ 3264 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3265 MLX5_BSF_REFRESH_DIF); 3266 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3267 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3268 /* repeating block */ 3269 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3270 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3271 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3272 3273 if (domain->sig.dif.ref_remap) 3274 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3275 3276 if (domain->sig.dif.app_escape) { 3277 if (domain->sig.dif.ref_escape) 3278 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3279 else 3280 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3281 } 3282 3283 inl->dif_app_bitmask_check = 3284 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3285 } 3286 3287 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3288 struct ib_sig_attrs *sig_attrs, 3289 struct mlx5_bsf *bsf, u32 data_size) 3290 { 3291 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3292 struct mlx5_bsf_basic *basic = &bsf->basic; 3293 struct ib_sig_domain *mem = &sig_attrs->mem; 3294 struct ib_sig_domain *wire = &sig_attrs->wire; 3295 3296 memset(bsf, 0, sizeof(*bsf)); 3297 3298 /* Basic + Extended + Inline */ 3299 basic->bsf_size_sbs = 1 << 7; 3300 /* Input domain check byte mask */ 3301 basic->check_byte_mask = sig_attrs->check_mask; 3302 basic->raw_data_size = cpu_to_be32(data_size); 3303 3304 /* Memory domain */ 3305 switch (sig_attrs->mem.sig_type) { 3306 case IB_SIG_TYPE_NONE: 3307 break; 3308 case IB_SIG_TYPE_T10_DIF: 3309 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3310 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3311 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3312 break; 3313 default: 3314 return -EINVAL; 3315 } 3316 3317 /* Wire domain */ 3318 switch (sig_attrs->wire.sig_type) { 3319 case IB_SIG_TYPE_NONE: 3320 break; 3321 case IB_SIG_TYPE_T10_DIF: 3322 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3323 mem->sig_type == wire->sig_type) { 3324 /* Same block structure */ 3325 basic->bsf_size_sbs |= 1 << 4; 3326 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3327 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3328 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3329 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3330 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3331 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3332 } else 3333 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3334 3335 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3336 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3337 break; 3338 default: 3339 return -EINVAL; 3340 } 3341 3342 return 0; 3343 } 3344 3345 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3346 struct mlx5_ib_qp *qp, void **seg, int *size) 3347 { 3348 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3349 struct ib_mr *sig_mr = wr->sig_mr; 3350 struct mlx5_bsf *bsf; 3351 u32 data_len = wr->wr.sg_list->length; 3352 u32 data_key = wr->wr.sg_list->lkey; 3353 u64 data_va = wr->wr.sg_list->addr; 3354 int ret; 3355 int wqe_size; 3356 3357 if (!wr->prot || 3358 (data_key == wr->prot->lkey && 3359 data_va == wr->prot->addr && 3360 data_len == wr->prot->length)) { 3361 /** 3362 * Source domain doesn't contain signature information 3363 * or data and protection are interleaved in memory. 3364 * So need construct: 3365 * ------------------ 3366 * | data_klm | 3367 * ------------------ 3368 * | BSF | 3369 * ------------------ 3370 **/ 3371 struct mlx5_klm *data_klm = *seg; 3372 3373 data_klm->bcount = cpu_to_be32(data_len); 3374 data_klm->key = cpu_to_be32(data_key); 3375 data_klm->va = cpu_to_be64(data_va); 3376 wqe_size = ALIGN(sizeof(*data_klm), 64); 3377 } else { 3378 /** 3379 * Source domain contains signature information 3380 * So need construct a strided block format: 3381 * --------------------------- 3382 * | stride_block_ctrl | 3383 * --------------------------- 3384 * | data_klm | 3385 * --------------------------- 3386 * | prot_klm | 3387 * --------------------------- 3388 * | BSF | 3389 * --------------------------- 3390 **/ 3391 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3392 struct mlx5_stride_block_entry *data_sentry; 3393 struct mlx5_stride_block_entry *prot_sentry; 3394 u32 prot_key = wr->prot->lkey; 3395 u64 prot_va = wr->prot->addr; 3396 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3397 int prot_size; 3398 3399 sblock_ctrl = *seg; 3400 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3401 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3402 3403 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3404 if (!prot_size) { 3405 pr_err("Bad block size given: %u\n", block_size); 3406 return -EINVAL; 3407 } 3408 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3409 prot_size); 3410 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3411 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3412 sblock_ctrl->num_entries = cpu_to_be16(2); 3413 3414 data_sentry->bcount = cpu_to_be16(block_size); 3415 data_sentry->key = cpu_to_be32(data_key); 3416 data_sentry->va = cpu_to_be64(data_va); 3417 data_sentry->stride = cpu_to_be16(block_size); 3418 3419 prot_sentry->bcount = cpu_to_be16(prot_size); 3420 prot_sentry->key = cpu_to_be32(prot_key); 3421 prot_sentry->va = cpu_to_be64(prot_va); 3422 prot_sentry->stride = cpu_to_be16(prot_size); 3423 3424 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3425 sizeof(*prot_sentry), 64); 3426 } 3427 3428 *seg += wqe_size; 3429 *size += wqe_size / 16; 3430 if (unlikely((*seg == qp->sq.qend))) 3431 *seg = mlx5_get_send_wqe(qp, 0); 3432 3433 bsf = *seg; 3434 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3435 if (ret) 3436 return -EINVAL; 3437 3438 *seg += sizeof(*bsf); 3439 *size += sizeof(*bsf) / 16; 3440 if (unlikely((*seg == qp->sq.qend))) 3441 *seg = mlx5_get_send_wqe(qp, 0); 3442 3443 return 0; 3444 } 3445 3446 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3447 struct ib_sig_handover_wr *wr, u32 nelements, 3448 u32 length, u32 pdn) 3449 { 3450 struct ib_mr *sig_mr = wr->sig_mr; 3451 u32 sig_key = sig_mr->rkey; 3452 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3453 3454 memset(seg, 0, sizeof(*seg)); 3455 3456 seg->flags = get_umr_flags(wr->access_flags) | 3457 MLX5_ACCESS_MODE_KLM; 3458 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3459 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3460 MLX5_MKEY_BSF_EN | pdn); 3461 seg->len = cpu_to_be64(length); 3462 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3463 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3464 } 3465 3466 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3467 u32 nelements) 3468 { 3469 memset(umr, 0, sizeof(*umr)); 3470 3471 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3472 umr->klm_octowords = get_klm_octo(nelements); 3473 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3474 umr->mkey_mask = sig_mkey_mask(); 3475 } 3476 3477 3478 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3479 void **seg, int *size) 3480 { 3481 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3482 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3483 u32 pdn = get_pd(qp)->pdn; 3484 u32 klm_oct_size; 3485 int region_len, ret; 3486 3487 if (unlikely(wr->wr.num_sge != 1) || 3488 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3489 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3490 unlikely(!sig_mr->sig->sig_status_checked)) 3491 return -EINVAL; 3492 3493 /* length of the protected region, data + protection */ 3494 region_len = wr->wr.sg_list->length; 3495 if (wr->prot && 3496 (wr->prot->lkey != wr->wr.sg_list->lkey || 3497 wr->prot->addr != wr->wr.sg_list->addr || 3498 wr->prot->length != wr->wr.sg_list->length)) 3499 region_len += wr->prot->length; 3500 3501 /** 3502 * KLM octoword size - if protection was provided 3503 * then we use strided block format (3 octowords), 3504 * else we use single KLM (1 octoword) 3505 **/ 3506 klm_oct_size = wr->prot ? 3 : 1; 3507 3508 set_sig_umr_segment(*seg, klm_oct_size); 3509 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3510 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3511 if (unlikely((*seg == qp->sq.qend))) 3512 *seg = mlx5_get_send_wqe(qp, 0); 3513 3514 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3515 *seg += sizeof(struct mlx5_mkey_seg); 3516 *size += sizeof(struct mlx5_mkey_seg) / 16; 3517 if (unlikely((*seg == qp->sq.qend))) 3518 *seg = mlx5_get_send_wqe(qp, 0); 3519 3520 ret = set_sig_data_segment(wr, qp, seg, size); 3521 if (ret) 3522 return ret; 3523 3524 sig_mr->sig->sig_status_checked = false; 3525 return 0; 3526 } 3527 3528 static int set_psv_wr(struct ib_sig_domain *domain, 3529 u32 psv_idx, void **seg, int *size) 3530 { 3531 struct mlx5_seg_set_psv *psv_seg = *seg; 3532 3533 memset(psv_seg, 0, sizeof(*psv_seg)); 3534 psv_seg->psv_num = cpu_to_be32(psv_idx); 3535 switch (domain->sig_type) { 3536 case IB_SIG_TYPE_NONE: 3537 break; 3538 case IB_SIG_TYPE_T10_DIF: 3539 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3540 domain->sig.dif.app_tag); 3541 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3542 break; 3543 default: 3544 pr_err("Bad signature type given.\n"); 3545 return 1; 3546 } 3547 3548 *seg += sizeof(*psv_seg); 3549 *size += sizeof(*psv_seg) / 16; 3550 3551 return 0; 3552 } 3553 3554 static int set_reg_wr(struct mlx5_ib_qp *qp, 3555 struct ib_reg_wr *wr, 3556 void **seg, int *size) 3557 { 3558 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3559 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3560 3561 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3562 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3563 "Invalid IB_SEND_INLINE send flag\n"); 3564 return -EINVAL; 3565 } 3566 3567 set_reg_umr_seg(*seg, mr); 3568 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3569 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3570 if (unlikely((*seg == qp->sq.qend))) 3571 *seg = mlx5_get_send_wqe(qp, 0); 3572 3573 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3574 *seg += sizeof(struct mlx5_mkey_seg); 3575 *size += sizeof(struct mlx5_mkey_seg) / 16; 3576 if (unlikely((*seg == qp->sq.qend))) 3577 *seg = mlx5_get_send_wqe(qp, 0); 3578 3579 set_reg_data_seg(*seg, mr, pd); 3580 *seg += sizeof(struct mlx5_wqe_data_seg); 3581 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3582 3583 return 0; 3584 } 3585 3586 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3587 { 3588 set_linv_umr_seg(*seg); 3589 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3590 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3591 if (unlikely((*seg == qp->sq.qend))) 3592 *seg = mlx5_get_send_wqe(qp, 0); 3593 set_linv_mkey_seg(*seg); 3594 *seg += sizeof(struct mlx5_mkey_seg); 3595 *size += sizeof(struct mlx5_mkey_seg) / 16; 3596 if (unlikely((*seg == qp->sq.qend))) 3597 *seg = mlx5_get_send_wqe(qp, 0); 3598 } 3599 3600 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3601 { 3602 __be32 *p = NULL; 3603 int tidx = idx; 3604 int i, j; 3605 3606 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3607 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3608 if ((i & 0xf) == 0) { 3609 void *buf = mlx5_get_send_wqe(qp, tidx); 3610 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3611 p = buf; 3612 j = 0; 3613 } 3614 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3615 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3616 be32_to_cpu(p[j + 3])); 3617 } 3618 } 3619 3620 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 3621 unsigned bytecnt, struct mlx5_ib_qp *qp) 3622 { 3623 while (bytecnt > 0) { 3624 __iowrite64_copy(dst++, src++, 8); 3625 __iowrite64_copy(dst++, src++, 8); 3626 __iowrite64_copy(dst++, src++, 8); 3627 __iowrite64_copy(dst++, src++, 8); 3628 __iowrite64_copy(dst++, src++, 8); 3629 __iowrite64_copy(dst++, src++, 8); 3630 __iowrite64_copy(dst++, src++, 8); 3631 __iowrite64_copy(dst++, src++, 8); 3632 bytecnt -= 64; 3633 if (unlikely(src == qp->sq.qend)) 3634 src = mlx5_get_send_wqe(qp, 0); 3635 } 3636 } 3637 3638 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 3639 { 3640 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3641 wr->send_flags & IB_SEND_FENCE)) 3642 return MLX5_FENCE_MODE_STRONG_ORDERING; 3643 3644 if (unlikely(fence)) { 3645 if (wr->send_flags & IB_SEND_FENCE) 3646 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3647 else 3648 return fence; 3649 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3650 return MLX5_FENCE_MODE_FENCE; 3651 } 3652 3653 return 0; 3654 } 3655 3656 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3657 struct mlx5_wqe_ctrl_seg **ctrl, 3658 struct ib_send_wr *wr, unsigned *idx, 3659 int *size, int nreq) 3660 { 3661 int err = 0; 3662 3663 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 3664 err = -ENOMEM; 3665 return err; 3666 } 3667 3668 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3669 *seg = mlx5_get_send_wqe(qp, *idx); 3670 *ctrl = *seg; 3671 *(uint32_t *)(*seg + 8) = 0; 3672 (*ctrl)->imm = send_ieth(wr); 3673 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3674 (wr->send_flags & IB_SEND_SIGNALED ? 3675 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3676 (wr->send_flags & IB_SEND_SOLICITED ? 3677 MLX5_WQE_CTRL_SOLICITED : 0); 3678 3679 *seg += sizeof(**ctrl); 3680 *size = sizeof(**ctrl) / 16; 3681 3682 return err; 3683 } 3684 3685 static void finish_wqe(struct mlx5_ib_qp *qp, 3686 struct mlx5_wqe_ctrl_seg *ctrl, 3687 u8 size, unsigned idx, u64 wr_id, 3688 int nreq, u8 fence, u8 next_fence, 3689 u32 mlx5_opcode) 3690 { 3691 u8 opmod = 0; 3692 3693 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3694 mlx5_opcode | ((u32)opmod << 24)); 3695 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3696 ctrl->fm_ce_se |= fence; 3697 qp->fm_cache = next_fence; 3698 if (unlikely(qp->wq_sig)) 3699 ctrl->signature = wq_sig(ctrl); 3700 3701 qp->sq.wrid[idx] = wr_id; 3702 qp->sq.w_list[idx].opcode = mlx5_opcode; 3703 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3704 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3705 qp->sq.w_list[idx].next = qp->sq.cur_post; 3706 } 3707 3708 3709 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3710 struct ib_send_wr **bad_wr) 3711 { 3712 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3713 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3714 struct mlx5_core_dev *mdev = dev->mdev; 3715 struct mlx5_ib_qp *qp; 3716 struct mlx5_ib_mr *mr; 3717 struct mlx5_wqe_data_seg *dpseg; 3718 struct mlx5_wqe_xrc_seg *xrc; 3719 struct mlx5_bf *bf; 3720 int uninitialized_var(size); 3721 void *qend; 3722 unsigned long flags; 3723 unsigned idx; 3724 int err = 0; 3725 int inl = 0; 3726 int num_sge; 3727 void *seg; 3728 int nreq; 3729 int i; 3730 u8 next_fence = 0; 3731 u8 fence; 3732 3733 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3734 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3735 3736 qp = to_mqp(ibqp); 3737 bf = qp->bf; 3738 qend = qp->sq.qend; 3739 3740 spin_lock_irqsave(&qp->sq.lock, flags); 3741 3742 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3743 err = -EIO; 3744 *bad_wr = wr; 3745 nreq = 0; 3746 goto out; 3747 } 3748 3749 for (nreq = 0; wr; nreq++, wr = wr->next) { 3750 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3751 mlx5_ib_warn(dev, "\n"); 3752 err = -EINVAL; 3753 *bad_wr = wr; 3754 goto out; 3755 } 3756 3757 fence = qp->fm_cache; 3758 num_sge = wr->num_sge; 3759 if (unlikely(num_sge > qp->sq.max_gs)) { 3760 mlx5_ib_warn(dev, "\n"); 3761 err = -ENOMEM; 3762 *bad_wr = wr; 3763 goto out; 3764 } 3765 3766 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3767 if (err) { 3768 mlx5_ib_warn(dev, "\n"); 3769 err = -ENOMEM; 3770 *bad_wr = wr; 3771 goto out; 3772 } 3773 3774 switch (ibqp->qp_type) { 3775 case IB_QPT_XRC_INI: 3776 xrc = seg; 3777 seg += sizeof(*xrc); 3778 size += sizeof(*xrc) / 16; 3779 /* fall through */ 3780 case IB_QPT_RC: 3781 switch (wr->opcode) { 3782 case IB_WR_RDMA_READ: 3783 case IB_WR_RDMA_WRITE: 3784 case IB_WR_RDMA_WRITE_WITH_IMM: 3785 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3786 rdma_wr(wr)->rkey); 3787 seg += sizeof(struct mlx5_wqe_raddr_seg); 3788 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3789 break; 3790 3791 case IB_WR_ATOMIC_CMP_AND_SWP: 3792 case IB_WR_ATOMIC_FETCH_AND_ADD: 3793 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3794 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3795 err = -ENOSYS; 3796 *bad_wr = wr; 3797 goto out; 3798 3799 case IB_WR_LOCAL_INV: 3800 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3801 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3802 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3803 set_linv_wr(qp, &seg, &size); 3804 num_sge = 0; 3805 break; 3806 3807 case IB_WR_REG_MR: 3808 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3809 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3810 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3811 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3812 if (err) { 3813 *bad_wr = wr; 3814 goto out; 3815 } 3816 num_sge = 0; 3817 break; 3818 3819 case IB_WR_REG_SIG_MR: 3820 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3821 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3822 3823 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3824 err = set_sig_umr_wr(wr, qp, &seg, &size); 3825 if (err) { 3826 mlx5_ib_warn(dev, "\n"); 3827 *bad_wr = wr; 3828 goto out; 3829 } 3830 3831 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3832 nreq, get_fence(fence, wr), 3833 next_fence, MLX5_OPCODE_UMR); 3834 /* 3835 * SET_PSV WQEs are not signaled and solicited 3836 * on error 3837 */ 3838 wr->send_flags &= ~IB_SEND_SIGNALED; 3839 wr->send_flags |= IB_SEND_SOLICITED; 3840 err = begin_wqe(qp, &seg, &ctrl, wr, 3841 &idx, &size, nreq); 3842 if (err) { 3843 mlx5_ib_warn(dev, "\n"); 3844 err = -ENOMEM; 3845 *bad_wr = wr; 3846 goto out; 3847 } 3848 3849 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3850 mr->sig->psv_memory.psv_idx, &seg, 3851 &size); 3852 if (err) { 3853 mlx5_ib_warn(dev, "\n"); 3854 *bad_wr = wr; 3855 goto out; 3856 } 3857 3858 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3859 nreq, get_fence(fence, wr), 3860 next_fence, MLX5_OPCODE_SET_PSV); 3861 err = begin_wqe(qp, &seg, &ctrl, wr, 3862 &idx, &size, nreq); 3863 if (err) { 3864 mlx5_ib_warn(dev, "\n"); 3865 err = -ENOMEM; 3866 *bad_wr = wr; 3867 goto out; 3868 } 3869 3870 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3871 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 3872 mr->sig->psv_wire.psv_idx, &seg, 3873 &size); 3874 if (err) { 3875 mlx5_ib_warn(dev, "\n"); 3876 *bad_wr = wr; 3877 goto out; 3878 } 3879 3880 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3881 nreq, get_fence(fence, wr), 3882 next_fence, MLX5_OPCODE_SET_PSV); 3883 num_sge = 0; 3884 goto skip_psv; 3885 3886 default: 3887 break; 3888 } 3889 break; 3890 3891 case IB_QPT_UC: 3892 switch (wr->opcode) { 3893 case IB_WR_RDMA_WRITE: 3894 case IB_WR_RDMA_WRITE_WITH_IMM: 3895 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3896 rdma_wr(wr)->rkey); 3897 seg += sizeof(struct mlx5_wqe_raddr_seg); 3898 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3899 break; 3900 3901 default: 3902 break; 3903 } 3904 break; 3905 3906 case IB_QPT_SMI: 3907 case MLX5_IB_QPT_HW_GSI: 3908 set_datagram_seg(seg, wr); 3909 seg += sizeof(struct mlx5_wqe_datagram_seg); 3910 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3911 if (unlikely((seg == qend))) 3912 seg = mlx5_get_send_wqe(qp, 0); 3913 break; 3914 case IB_QPT_UD: 3915 set_datagram_seg(seg, wr); 3916 seg += sizeof(struct mlx5_wqe_datagram_seg); 3917 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3918 3919 if (unlikely((seg == qend))) 3920 seg = mlx5_get_send_wqe(qp, 0); 3921 3922 /* handle qp that supports ud offload */ 3923 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 3924 struct mlx5_wqe_eth_pad *pad; 3925 3926 pad = seg; 3927 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 3928 seg += sizeof(struct mlx5_wqe_eth_pad); 3929 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 3930 3931 seg = set_eth_seg(seg, wr, qend, qp, &size); 3932 3933 if (unlikely((seg == qend))) 3934 seg = mlx5_get_send_wqe(qp, 0); 3935 } 3936 break; 3937 case MLX5_IB_QPT_REG_UMR: 3938 if (wr->opcode != MLX5_IB_WR_UMR) { 3939 err = -EINVAL; 3940 mlx5_ib_warn(dev, "bad opcode\n"); 3941 goto out; 3942 } 3943 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 3944 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 3945 set_reg_umr_segment(seg, wr); 3946 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3947 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3948 if (unlikely((seg == qend))) 3949 seg = mlx5_get_send_wqe(qp, 0); 3950 set_reg_mkey_segment(seg, wr); 3951 seg += sizeof(struct mlx5_mkey_seg); 3952 size += sizeof(struct mlx5_mkey_seg) / 16; 3953 if (unlikely((seg == qend))) 3954 seg = mlx5_get_send_wqe(qp, 0); 3955 break; 3956 3957 default: 3958 break; 3959 } 3960 3961 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 3962 int uninitialized_var(sz); 3963 3964 err = set_data_inl_seg(qp, wr, seg, &sz); 3965 if (unlikely(err)) { 3966 mlx5_ib_warn(dev, "\n"); 3967 *bad_wr = wr; 3968 goto out; 3969 } 3970 inl = 1; 3971 size += sz; 3972 } else { 3973 dpseg = seg; 3974 for (i = 0; i < num_sge; i++) { 3975 if (unlikely(dpseg == qend)) { 3976 seg = mlx5_get_send_wqe(qp, 0); 3977 dpseg = seg; 3978 } 3979 if (likely(wr->sg_list[i].length)) { 3980 set_data_ptr_seg(dpseg, wr->sg_list + i); 3981 size += sizeof(struct mlx5_wqe_data_seg) / 16; 3982 dpseg++; 3983 } 3984 } 3985 } 3986 3987 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3988 get_fence(fence, wr), next_fence, 3989 mlx5_ib_opcode[wr->opcode]); 3990 skip_psv: 3991 if (0) 3992 dump_wqe(qp, idx, size); 3993 } 3994 3995 out: 3996 if (likely(nreq)) { 3997 qp->sq.head += nreq; 3998 3999 /* Make sure that descriptors are written before 4000 * updating doorbell record and ringing the doorbell 4001 */ 4002 wmb(); 4003 4004 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4005 4006 /* Make sure doorbell record is visible to the HCA before 4007 * we hit doorbell */ 4008 wmb(); 4009 4010 if (bf->need_lock) 4011 spin_lock(&bf->lock); 4012 else 4013 __acquire(&bf->lock); 4014 4015 /* TBD enable WC */ 4016 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 4017 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 4018 /* wc_wmb(); */ 4019 } else { 4020 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 4021 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4022 /* Make sure doorbells don't leak out of SQ spinlock 4023 * and reach the HCA out of order. 4024 */ 4025 mmiowb(); 4026 } 4027 bf->offset ^= bf->buf_size; 4028 if (bf->need_lock) 4029 spin_unlock(&bf->lock); 4030 else 4031 __release(&bf->lock); 4032 } 4033 4034 spin_unlock_irqrestore(&qp->sq.lock, flags); 4035 4036 return err; 4037 } 4038 4039 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4040 { 4041 sig->signature = calc_sig(sig, size); 4042 } 4043 4044 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4045 struct ib_recv_wr **bad_wr) 4046 { 4047 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4048 struct mlx5_wqe_data_seg *scat; 4049 struct mlx5_rwqe_sig *sig; 4050 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4051 struct mlx5_core_dev *mdev = dev->mdev; 4052 unsigned long flags; 4053 int err = 0; 4054 int nreq; 4055 int ind; 4056 int i; 4057 4058 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4059 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4060 4061 spin_lock_irqsave(&qp->rq.lock, flags); 4062 4063 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4064 err = -EIO; 4065 *bad_wr = wr; 4066 nreq = 0; 4067 goto out; 4068 } 4069 4070 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4071 4072 for (nreq = 0; wr; nreq++, wr = wr->next) { 4073 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4074 err = -ENOMEM; 4075 *bad_wr = wr; 4076 goto out; 4077 } 4078 4079 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4080 err = -EINVAL; 4081 *bad_wr = wr; 4082 goto out; 4083 } 4084 4085 scat = get_recv_wqe(qp, ind); 4086 if (qp->wq_sig) 4087 scat++; 4088 4089 for (i = 0; i < wr->num_sge; i++) 4090 set_data_ptr_seg(scat + i, wr->sg_list + i); 4091 4092 if (i < qp->rq.max_gs) { 4093 scat[i].byte_count = 0; 4094 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4095 scat[i].addr = 0; 4096 } 4097 4098 if (qp->wq_sig) { 4099 sig = (struct mlx5_rwqe_sig *)scat; 4100 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4101 } 4102 4103 qp->rq.wrid[ind] = wr->wr_id; 4104 4105 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4106 } 4107 4108 out: 4109 if (likely(nreq)) { 4110 qp->rq.head += nreq; 4111 4112 /* Make sure that descriptors are written before 4113 * doorbell record. 4114 */ 4115 wmb(); 4116 4117 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4118 } 4119 4120 spin_unlock_irqrestore(&qp->rq.lock, flags); 4121 4122 return err; 4123 } 4124 4125 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4126 { 4127 switch (mlx5_state) { 4128 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4129 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4130 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4131 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4132 case MLX5_QP_STATE_SQ_DRAINING: 4133 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4134 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4135 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4136 default: return -1; 4137 } 4138 } 4139 4140 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4141 { 4142 switch (mlx5_mig_state) { 4143 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4144 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4145 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4146 default: return -1; 4147 } 4148 } 4149 4150 static int to_ib_qp_access_flags(int mlx5_flags) 4151 { 4152 int ib_flags = 0; 4153 4154 if (mlx5_flags & MLX5_QP_BIT_RRE) 4155 ib_flags |= IB_ACCESS_REMOTE_READ; 4156 if (mlx5_flags & MLX5_QP_BIT_RWE) 4157 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4158 if (mlx5_flags & MLX5_QP_BIT_RAE) 4159 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4160 4161 return ib_flags; 4162 } 4163 4164 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4165 struct mlx5_qp_path *path) 4166 { 4167 struct mlx5_core_dev *dev = ibdev->mdev; 4168 4169 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4170 ib_ah_attr->port_num = path->port; 4171 4172 if (ib_ah_attr->port_num == 0 || 4173 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4174 return; 4175 4176 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4177 4178 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4179 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4180 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4181 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4182 if (ib_ah_attr->ah_flags) { 4183 ib_ah_attr->grh.sgid_index = path->mgid_index; 4184 ib_ah_attr->grh.hop_limit = path->hop_limit; 4185 ib_ah_attr->grh.traffic_class = 4186 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4187 ib_ah_attr->grh.flow_label = 4188 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4189 memcpy(ib_ah_attr->grh.dgid.raw, 4190 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4191 } 4192 } 4193 4194 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4195 struct mlx5_ib_sq *sq, 4196 u8 *sq_state) 4197 { 4198 void *out; 4199 void *sqc; 4200 int inlen; 4201 int err; 4202 4203 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4204 out = mlx5_vzalloc(inlen); 4205 if (!out) 4206 return -ENOMEM; 4207 4208 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4209 if (err) 4210 goto out; 4211 4212 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4213 *sq_state = MLX5_GET(sqc, sqc, state); 4214 sq->state = *sq_state; 4215 4216 out: 4217 kvfree(out); 4218 return err; 4219 } 4220 4221 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4222 struct mlx5_ib_rq *rq, 4223 u8 *rq_state) 4224 { 4225 void *out; 4226 void *rqc; 4227 int inlen; 4228 int err; 4229 4230 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4231 out = mlx5_vzalloc(inlen); 4232 if (!out) 4233 return -ENOMEM; 4234 4235 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4236 if (err) 4237 goto out; 4238 4239 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4240 *rq_state = MLX5_GET(rqc, rqc, state); 4241 rq->state = *rq_state; 4242 4243 out: 4244 kvfree(out); 4245 return err; 4246 } 4247 4248 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4249 struct mlx5_ib_qp *qp, u8 *qp_state) 4250 { 4251 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4252 [MLX5_RQC_STATE_RST] = { 4253 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4254 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4255 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4256 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4257 }, 4258 [MLX5_RQC_STATE_RDY] = { 4259 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4260 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4261 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4262 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4263 }, 4264 [MLX5_RQC_STATE_ERR] = { 4265 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4266 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4267 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4268 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4269 }, 4270 [MLX5_RQ_STATE_NA] = { 4271 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4272 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4273 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4274 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4275 }, 4276 }; 4277 4278 *qp_state = sqrq_trans[rq_state][sq_state]; 4279 4280 if (*qp_state == MLX5_QP_STATE_BAD) { 4281 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4282 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4283 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4284 return -EINVAL; 4285 } 4286 4287 if (*qp_state == MLX5_QP_STATE) 4288 *qp_state = qp->state; 4289 4290 return 0; 4291 } 4292 4293 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4294 struct mlx5_ib_qp *qp, 4295 u8 *raw_packet_qp_state) 4296 { 4297 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4298 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4299 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4300 int err; 4301 u8 sq_state = MLX5_SQ_STATE_NA; 4302 u8 rq_state = MLX5_RQ_STATE_NA; 4303 4304 if (qp->sq.wqe_cnt) { 4305 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4306 if (err) 4307 return err; 4308 } 4309 4310 if (qp->rq.wqe_cnt) { 4311 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4312 if (err) 4313 return err; 4314 } 4315 4316 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4317 raw_packet_qp_state); 4318 } 4319 4320 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4321 struct ib_qp_attr *qp_attr) 4322 { 4323 struct mlx5_query_qp_mbox_out *outb; 4324 struct mlx5_qp_context *context; 4325 int mlx5_state; 4326 int err = 0; 4327 4328 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 4329 if (!outb) 4330 return -ENOMEM; 4331 4332 context = &outb->ctx; 4333 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4334 sizeof(*outb)); 4335 if (err) 4336 goto out; 4337 4338 mlx5_state = be32_to_cpu(context->flags) >> 28; 4339 4340 qp->state = to_ib_qp_state(mlx5_state); 4341 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4342 qp_attr->path_mig_state = 4343 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4344 qp_attr->qkey = be32_to_cpu(context->qkey); 4345 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4346 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4347 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4348 qp_attr->qp_access_flags = 4349 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4350 4351 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4352 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4353 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4354 qp_attr->alt_pkey_index = 4355 be16_to_cpu(context->alt_path.pkey_index); 4356 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4357 } 4358 4359 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4360 qp_attr->port_num = context->pri_path.port; 4361 4362 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4363 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4364 4365 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4366 4367 qp_attr->max_dest_rd_atomic = 4368 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4369 qp_attr->min_rnr_timer = 4370 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4371 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4372 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4373 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4374 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4375 4376 out: 4377 kfree(outb); 4378 return err; 4379 } 4380 4381 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4382 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4383 { 4384 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4385 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4386 int err = 0; 4387 u8 raw_packet_qp_state; 4388 4389 if (ibqp->rwq_ind_tbl) 4390 return -ENOSYS; 4391 4392 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4393 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4394 qp_init_attr); 4395 4396 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4397 /* 4398 * Wait for any outstanding page faults, in case the user frees memory 4399 * based upon this query's result. 4400 */ 4401 flush_workqueue(mlx5_ib_page_fault_wq); 4402 #endif 4403 4404 mutex_lock(&qp->mutex); 4405 4406 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4407 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4408 if (err) 4409 goto out; 4410 qp->state = raw_packet_qp_state; 4411 qp_attr->port_num = 1; 4412 } else { 4413 err = query_qp_attr(dev, qp, qp_attr); 4414 if (err) 4415 goto out; 4416 } 4417 4418 qp_attr->qp_state = qp->state; 4419 qp_attr->cur_qp_state = qp_attr->qp_state; 4420 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4421 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4422 4423 if (!ibqp->uobject) { 4424 qp_attr->cap.max_send_wr = qp->sq.max_post; 4425 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4426 qp_init_attr->qp_context = ibqp->qp_context; 4427 } else { 4428 qp_attr->cap.max_send_wr = 0; 4429 qp_attr->cap.max_send_sge = 0; 4430 } 4431 4432 qp_init_attr->qp_type = ibqp->qp_type; 4433 qp_init_attr->recv_cq = ibqp->recv_cq; 4434 qp_init_attr->send_cq = ibqp->send_cq; 4435 qp_init_attr->srq = ibqp->srq; 4436 qp_attr->cap.max_inline_data = qp->max_inline_data; 4437 4438 qp_init_attr->cap = qp_attr->cap; 4439 4440 qp_init_attr->create_flags = 0; 4441 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4442 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4443 4444 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4445 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4446 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4447 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4448 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4449 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4450 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4451 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4452 4453 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4454 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4455 4456 out: 4457 mutex_unlock(&qp->mutex); 4458 return err; 4459 } 4460 4461 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4462 struct ib_ucontext *context, 4463 struct ib_udata *udata) 4464 { 4465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4466 struct mlx5_ib_xrcd *xrcd; 4467 int err; 4468 4469 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4470 return ERR_PTR(-ENOSYS); 4471 4472 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4473 if (!xrcd) 4474 return ERR_PTR(-ENOMEM); 4475 4476 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4477 if (err) { 4478 kfree(xrcd); 4479 return ERR_PTR(-ENOMEM); 4480 } 4481 4482 return &xrcd->ibxrcd; 4483 } 4484 4485 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4486 { 4487 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4488 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4489 int err; 4490 4491 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4492 if (err) { 4493 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4494 return err; 4495 } 4496 4497 kfree(xrcd); 4498 4499 return 0; 4500 } 4501 4502 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4503 struct ib_wq_init_attr *init_attr) 4504 { 4505 struct mlx5_ib_dev *dev; 4506 __be64 *rq_pas0; 4507 void *in; 4508 void *rqc; 4509 void *wq; 4510 int inlen; 4511 int err; 4512 4513 dev = to_mdev(pd->device); 4514 4515 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4516 in = mlx5_vzalloc(inlen); 4517 if (!in) 4518 return -ENOMEM; 4519 4520 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4521 MLX5_SET(rqc, rqc, mem_rq_type, 4522 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4523 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4524 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4525 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4526 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4527 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4528 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4529 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4530 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4531 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4532 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4533 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4534 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4535 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4536 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4537 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4538 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4539 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn); 4540 kvfree(in); 4541 return err; 4542 } 4543 4544 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4545 struct ib_wq_init_attr *wq_init_attr, 4546 struct mlx5_ib_create_wq *ucmd, 4547 struct mlx5_ib_rwq *rwq) 4548 { 4549 /* Sanity check RQ size before proceeding */ 4550 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4551 return -EINVAL; 4552 4553 if (!ucmd->rq_wqe_count) 4554 return -EINVAL; 4555 4556 rwq->wqe_count = ucmd->rq_wqe_count; 4557 rwq->wqe_shift = ucmd->rq_wqe_shift; 4558 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4559 rwq->log_rq_stride = rwq->wqe_shift; 4560 rwq->log_rq_size = ilog2(rwq->wqe_count); 4561 return 0; 4562 } 4563 4564 static int prepare_user_rq(struct ib_pd *pd, 4565 struct ib_wq_init_attr *init_attr, 4566 struct ib_udata *udata, 4567 struct mlx5_ib_rwq *rwq) 4568 { 4569 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4570 struct mlx5_ib_create_wq ucmd = {}; 4571 int err; 4572 size_t required_cmd_sz; 4573 4574 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4575 if (udata->inlen < required_cmd_sz) { 4576 mlx5_ib_dbg(dev, "invalid inlen\n"); 4577 return -EINVAL; 4578 } 4579 4580 if (udata->inlen > sizeof(ucmd) && 4581 !ib_is_udata_cleared(udata, sizeof(ucmd), 4582 udata->inlen - sizeof(ucmd))) { 4583 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4584 return -EOPNOTSUPP; 4585 } 4586 4587 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4588 mlx5_ib_dbg(dev, "copy failed\n"); 4589 return -EFAULT; 4590 } 4591 4592 if (ucmd.comp_mask) { 4593 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4594 return -EOPNOTSUPP; 4595 } 4596 4597 if (ucmd.reserved) { 4598 mlx5_ib_dbg(dev, "invalid reserved\n"); 4599 return -EOPNOTSUPP; 4600 } 4601 4602 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4603 if (err) { 4604 mlx5_ib_dbg(dev, "err %d\n", err); 4605 return err; 4606 } 4607 4608 err = create_user_rq(dev, pd, rwq, &ucmd); 4609 if (err) { 4610 mlx5_ib_dbg(dev, "err %d\n", err); 4611 if (err) 4612 return err; 4613 } 4614 4615 rwq->user_index = ucmd.user_index; 4616 return 0; 4617 } 4618 4619 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4620 struct ib_wq_init_attr *init_attr, 4621 struct ib_udata *udata) 4622 { 4623 struct mlx5_ib_dev *dev; 4624 struct mlx5_ib_rwq *rwq; 4625 struct mlx5_ib_create_wq_resp resp = {}; 4626 size_t min_resp_len; 4627 int err; 4628 4629 if (!udata) 4630 return ERR_PTR(-ENOSYS); 4631 4632 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4633 if (udata->outlen && udata->outlen < min_resp_len) 4634 return ERR_PTR(-EINVAL); 4635 4636 dev = to_mdev(pd->device); 4637 switch (init_attr->wq_type) { 4638 case IB_WQT_RQ: 4639 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4640 if (!rwq) 4641 return ERR_PTR(-ENOMEM); 4642 err = prepare_user_rq(pd, init_attr, udata, rwq); 4643 if (err) 4644 goto err; 4645 err = create_rq(rwq, pd, init_attr); 4646 if (err) 4647 goto err_user_rq; 4648 break; 4649 default: 4650 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4651 init_attr->wq_type); 4652 return ERR_PTR(-EINVAL); 4653 } 4654 4655 rwq->ibwq.wq_num = rwq->rqn; 4656 rwq->ibwq.state = IB_WQS_RESET; 4657 if (udata->outlen) { 4658 resp.response_length = offsetof(typeof(resp), response_length) + 4659 sizeof(resp.response_length); 4660 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4661 if (err) 4662 goto err_copy; 4663 } 4664 4665 return &rwq->ibwq; 4666 4667 err_copy: 4668 mlx5_core_destroy_rq(dev->mdev, rwq->rqn); 4669 err_user_rq: 4670 destroy_user_rq(pd, rwq); 4671 err: 4672 kfree(rwq); 4673 return ERR_PTR(err); 4674 } 4675 4676 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4677 { 4678 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4679 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4680 4681 mlx5_core_destroy_rq(dev->mdev, rwq->rqn); 4682 destroy_user_rq(wq->pd, rwq); 4683 kfree(rwq); 4684 4685 return 0; 4686 } 4687 4688 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4689 struct ib_rwq_ind_table_init_attr *init_attr, 4690 struct ib_udata *udata) 4691 { 4692 struct mlx5_ib_dev *dev = to_mdev(device); 4693 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4694 int sz = 1 << init_attr->log_ind_tbl_size; 4695 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4696 size_t min_resp_len; 4697 int inlen; 4698 int err; 4699 int i; 4700 u32 *in; 4701 void *rqtc; 4702 4703 if (udata->inlen > 0 && 4704 !ib_is_udata_cleared(udata, 0, 4705 udata->inlen)) 4706 return ERR_PTR(-EOPNOTSUPP); 4707 4708 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4709 if (udata->outlen && udata->outlen < min_resp_len) 4710 return ERR_PTR(-EINVAL); 4711 4712 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4713 if (!rwq_ind_tbl) 4714 return ERR_PTR(-ENOMEM); 4715 4716 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4717 in = mlx5_vzalloc(inlen); 4718 if (!in) { 4719 err = -ENOMEM; 4720 goto err; 4721 } 4722 4723 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4724 4725 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4726 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4727 4728 for (i = 0; i < sz; i++) 4729 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4730 4731 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4732 kvfree(in); 4733 4734 if (err) 4735 goto err; 4736 4737 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4738 if (udata->outlen) { 4739 resp.response_length = offsetof(typeof(resp), response_length) + 4740 sizeof(resp.response_length); 4741 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4742 if (err) 4743 goto err_copy; 4744 } 4745 4746 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4747 4748 err_copy: 4749 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4750 err: 4751 kfree(rwq_ind_tbl); 4752 return ERR_PTR(err); 4753 } 4754 4755 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4756 { 4757 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4758 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4759 4760 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4761 4762 kfree(rwq_ind_tbl); 4763 return 0; 4764 } 4765 4766 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4767 u32 wq_attr_mask, struct ib_udata *udata) 4768 { 4769 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4770 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4771 struct mlx5_ib_modify_wq ucmd = {}; 4772 size_t required_cmd_sz; 4773 int curr_wq_state; 4774 int wq_state; 4775 int inlen; 4776 int err; 4777 void *rqc; 4778 void *in; 4779 4780 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4781 if (udata->inlen < required_cmd_sz) 4782 return -EINVAL; 4783 4784 if (udata->inlen > sizeof(ucmd) && 4785 !ib_is_udata_cleared(udata, sizeof(ucmd), 4786 udata->inlen - sizeof(ucmd))) 4787 return -EOPNOTSUPP; 4788 4789 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4790 return -EFAULT; 4791 4792 if (ucmd.comp_mask || ucmd.reserved) 4793 return -EOPNOTSUPP; 4794 4795 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4796 in = mlx5_vzalloc(inlen); 4797 if (!in) 4798 return -ENOMEM; 4799 4800 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4801 4802 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 4803 wq_attr->curr_wq_state : wq->state; 4804 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 4805 wq_attr->wq_state : curr_wq_state; 4806 if (curr_wq_state == IB_WQS_ERR) 4807 curr_wq_state = MLX5_RQC_STATE_ERR; 4808 if (wq_state == IB_WQS_ERR) 4809 wq_state = MLX5_RQC_STATE_ERR; 4810 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 4811 MLX5_SET(rqc, rqc, state, wq_state); 4812 4813 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen); 4814 kvfree(in); 4815 if (!err) 4816 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 4817 4818 return err; 4819 } 4820