1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 }; 57 58 static const u32 mlx5_ib_opcode[] = { 59 [IB_WR_SEND] = MLX5_OPCODE_SEND, 60 [IB_WR_LSO] = MLX5_OPCODE_LSO, 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 73 }; 74 75 struct mlx5_wqe_eth_pad { 76 u8 rsvd0[16]; 77 }; 78 79 enum raw_qp_set_mask_map { 80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 82 }; 83 84 struct mlx5_modify_raw_qp_param { 85 u16 operation; 86 87 u32 set_mask; /* raw_qp_set_mask_map */ 88 u32 rate_limit; 89 u8 rq_q_ctr_id; 90 }; 91 92 static void get_cqs(enum ib_qp_type qp_type, 93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 95 96 static int is_qp0(enum ib_qp_type qp_type) 97 { 98 return qp_type == IB_QPT_SMI; 99 } 100 101 static int is_sqp(enum ib_qp_type qp_type) 102 { 103 return is_qp0(qp_type) || is_qp1(qp_type); 104 } 105 106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 107 { 108 return mlx5_buf_offset(&qp->buf, offset); 109 } 110 111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 112 { 113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 114 } 115 116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 117 { 118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 119 } 120 121 /** 122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 123 * 124 * @qp: QP to copy from. 125 * @send: copy from the send queue when non-zero, use the receive queue 126 * otherwise. 127 * @wqe_index: index to start copying from. For send work queues, the 128 * wqe_index is in units of MLX5_SEND_WQE_BB. 129 * For receive work queue, it is the number of work queue 130 * element in the queue. 131 * @buffer: destination buffer. 132 * @length: maximum number of bytes to copy. 133 * 134 * Copies at least a single WQE, but may copy more data. 135 * 136 * Return: the number of bytes copied, or an error code. 137 */ 138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 139 void *buffer, u32 length, 140 struct mlx5_ib_qp_base *base) 141 { 142 struct ib_device *ibdev = qp->ibqp.device; 143 struct mlx5_ib_dev *dev = to_mdev(ibdev); 144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 145 size_t offset; 146 size_t wq_end; 147 struct ib_umem *umem = base->ubuffer.umem; 148 u32 first_copy_length; 149 int wqe_length; 150 int ret; 151 152 if (wq->wqe_cnt == 0) { 153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 154 qp->ibqp.qp_type); 155 return -EINVAL; 156 } 157 158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 160 161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 162 return -EINVAL; 163 164 if (offset > umem->length || 165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 166 return -EINVAL; 167 168 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 170 if (ret) 171 return ret; 172 173 if (send) { 174 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 176 177 wqe_length = ds * MLX5_WQE_DS_UNITS; 178 } else { 179 wqe_length = 1 << wq->wqe_shift; 180 } 181 182 if (wqe_length <= first_copy_length) 183 return first_copy_length; 184 185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 186 wqe_length - first_copy_length); 187 if (ret) 188 return ret; 189 190 return wqe_length; 191 } 192 193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 194 { 195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 196 struct ib_event event; 197 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 199 /* This event is only valid for trans_qps */ 200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 201 } 202 203 if (ibqp->event_handler) { 204 event.device = ibqp->device; 205 event.element.qp = ibqp; 206 switch (type) { 207 case MLX5_EVENT_TYPE_PATH_MIG: 208 event.event = IB_EVENT_PATH_MIG; 209 break; 210 case MLX5_EVENT_TYPE_COMM_EST: 211 event.event = IB_EVENT_COMM_EST; 212 break; 213 case MLX5_EVENT_TYPE_SQ_DRAINED: 214 event.event = IB_EVENT_SQ_DRAINED; 215 break; 216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 217 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 218 break; 219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 220 event.event = IB_EVENT_QP_FATAL; 221 break; 222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 223 event.event = IB_EVENT_PATH_MIG_ERR; 224 break; 225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 226 event.event = IB_EVENT_QP_REQ_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 229 event.event = IB_EVENT_QP_ACCESS_ERR; 230 break; 231 default: 232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 233 return; 234 } 235 236 ibqp->event_handler(&event, ibqp->qp_context); 237 } 238 } 239 240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 242 { 243 int wqe_size; 244 int wq_size; 245 246 /* Sanity check RQ size before proceeding */ 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 248 return -EINVAL; 249 250 if (!has_rq) { 251 qp->rq.max_gs = 0; 252 qp->rq.wqe_cnt = 0; 253 qp->rq.wqe_shift = 0; 254 cap->max_recv_wr = 0; 255 cap->max_recv_sge = 0; 256 } else { 257 if (ucmd) { 258 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 259 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 261 qp->rq.max_post = qp->rq.wqe_cnt; 262 } else { 263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 265 wqe_size = roundup_pow_of_two(wqe_size); 266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 268 qp->rq.wqe_cnt = wq_size / wqe_size; 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 271 wqe_size, 272 MLX5_CAP_GEN(dev->mdev, 273 max_wqe_sz_rq)); 274 return -EINVAL; 275 } 276 qp->rq.wqe_shift = ilog2(wqe_size); 277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 278 qp->rq.max_post = qp->rq.wqe_cnt; 279 } 280 } 281 282 return 0; 283 } 284 285 static int sq_overhead(struct ib_qp_init_attr *attr) 286 { 287 int size = 0; 288 289 switch (attr->qp_type) { 290 case IB_QPT_XRC_INI: 291 size += sizeof(struct mlx5_wqe_xrc_seg); 292 /* fall through */ 293 case IB_QPT_RC: 294 size += sizeof(struct mlx5_wqe_ctrl_seg) + 295 max(sizeof(struct mlx5_wqe_atomic_seg) + 296 sizeof(struct mlx5_wqe_raddr_seg), 297 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 298 sizeof(struct mlx5_mkey_seg)); 299 break; 300 301 case IB_QPT_XRC_TGT: 302 return 0; 303 304 case IB_QPT_UC: 305 size += sizeof(struct mlx5_wqe_ctrl_seg) + 306 max(sizeof(struct mlx5_wqe_raddr_seg), 307 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 308 sizeof(struct mlx5_mkey_seg)); 309 break; 310 311 case IB_QPT_UD: 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 313 size += sizeof(struct mlx5_wqe_eth_pad) + 314 sizeof(struct mlx5_wqe_eth_seg); 315 /* fall through */ 316 case IB_QPT_SMI: 317 case MLX5_IB_QPT_HW_GSI: 318 size += sizeof(struct mlx5_wqe_ctrl_seg) + 319 sizeof(struct mlx5_wqe_datagram_seg); 320 break; 321 322 case MLX5_IB_QPT_REG_UMR: 323 size += sizeof(struct mlx5_wqe_ctrl_seg) + 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 325 sizeof(struct mlx5_mkey_seg); 326 break; 327 328 default: 329 return -EINVAL; 330 } 331 332 return size; 333 } 334 335 static int calc_send_wqe(struct ib_qp_init_attr *attr) 336 { 337 int inl_size = 0; 338 int size; 339 340 size = sq_overhead(attr); 341 if (size < 0) 342 return size; 343 344 if (attr->cap.max_inline_data) { 345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 346 attr->cap.max_inline_data; 347 } 348 349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 352 return MLX5_SIG_WQE_SIZE; 353 else 354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 355 } 356 357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 358 { 359 int max_sge; 360 361 if (attr->qp_type == IB_QPT_RC) 362 max_sge = (min_t(int, wqe_size, 512) - 363 sizeof(struct mlx5_wqe_ctrl_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else if (attr->qp_type == IB_QPT_XRC_INI) 367 max_sge = (min_t(int, wqe_size, 512) - 368 sizeof(struct mlx5_wqe_ctrl_seg) - 369 sizeof(struct mlx5_wqe_xrc_seg) - 370 sizeof(struct mlx5_wqe_raddr_seg)) / 371 sizeof(struct mlx5_wqe_data_seg); 372 else 373 max_sge = (wqe_size - sq_overhead(attr)) / 374 sizeof(struct mlx5_wqe_data_seg); 375 376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 377 sizeof(struct mlx5_wqe_data_seg)); 378 } 379 380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 381 struct mlx5_ib_qp *qp) 382 { 383 int wqe_size; 384 int wq_size; 385 386 if (!attr->cap.max_send_wr) 387 return 0; 388 389 wqe_size = calc_send_wqe(attr); 390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 391 if (wqe_size < 0) 392 return wqe_size; 393 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 397 return -EINVAL; 398 } 399 400 qp->max_inline_data = wqe_size - sq_overhead(attr) - 401 sizeof(struct mlx5_wqe_inline_seg); 402 attr->cap.max_inline_data = qp->max_inline_data; 403 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 405 qp->signature_en = true; 406 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -ENOMEM; 415 } 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 417 qp->sq.max_gs = get_send_sge(attr, wqe_size); 418 if (qp->sq.max_gs < attr->cap.max_send_sge) 419 return -ENOMEM; 420 421 attr->cap.max_send_sge = qp->sq.max_gs; 422 qp->sq.max_post = wq_size / wqe_size; 423 attr->cap.max_send_wr = qp->sq.max_post; 424 425 return wq_size; 426 } 427 428 static int set_user_buf_size(struct mlx5_ib_dev *dev, 429 struct mlx5_ib_qp *qp, 430 struct mlx5_ib_create_qp *ucmd, 431 struct mlx5_ib_qp_base *base, 432 struct ib_qp_init_attr *attr) 433 { 434 int desc_sz = 1 << qp->sq.wqe_shift; 435 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 439 return -EINVAL; 440 } 441 442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 444 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 445 return -EINVAL; 446 } 447 448 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 449 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 452 qp->sq.wqe_cnt, 453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 454 return -EINVAL; 455 } 456 457 if (attr->qp_type == IB_QPT_RAW_PACKET || 458 qp->flags & MLX5_IB_QP_UNDERLAY) { 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 461 } else { 462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 463 (qp->sq.wqe_cnt << 6); 464 } 465 466 return 0; 467 } 468 469 static int qp_has_rq(struct ib_qp_init_attr *attr) 470 { 471 if (attr->qp_type == IB_QPT_XRC_INI || 472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 473 attr->qp_type == MLX5_IB_QPT_REG_UMR || 474 !attr->cap.max_recv_wr) 475 return 0; 476 477 return 1; 478 } 479 480 static int first_med_bfreg(void) 481 { 482 return 1; 483 } 484 485 enum { 486 /* this is the first blue flame register in the array of bfregs assigned 487 * to a processes. Since we do not use it for blue flame but rather 488 * regular 64 bit doorbells, we do not need a lock for maintaiing 489 * "odd/even" order 490 */ 491 NUM_NON_BLUE_FLAME_BFREGS = 1, 492 }; 493 494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 495 { 496 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 497 } 498 499 static int num_med_bfreg(struct mlx5_ib_dev *dev, 500 struct mlx5_bfreg_info *bfregi) 501 { 502 int n; 503 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 505 NUM_NON_BLUE_FLAME_BFREGS; 506 507 return n >= 0 ? n : 0; 508 } 509 510 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 511 struct mlx5_bfreg_info *bfregi) 512 { 513 int med; 514 515 med = num_med_bfreg(dev, bfregi); 516 return ++med; 517 } 518 519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 520 struct mlx5_bfreg_info *bfregi) 521 { 522 int i; 523 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 525 if (!bfregi->count[i]) { 526 bfregi->count[i]++; 527 return i; 528 } 529 } 530 531 return -ENOMEM; 532 } 533 534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 535 struct mlx5_bfreg_info *bfregi) 536 { 537 int minidx = first_med_bfreg(); 538 int i; 539 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi, 553 enum mlx5_ib_latency_class lat) 554 { 555 int bfregn = -EINVAL; 556 557 mutex_lock(&bfregi->lock); 558 switch (lat) { 559 case MLX5_IB_LATENCY_CLASS_LOW: 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 561 bfregn = 0; 562 bfregi->count[bfregn]++; 563 break; 564 565 case MLX5_IB_LATENCY_CLASS_MEDIUM: 566 if (bfregi->ver < 2) 567 bfregn = -ENOMEM; 568 else 569 bfregn = alloc_med_class_bfreg(dev, bfregi); 570 break; 571 572 case MLX5_IB_LATENCY_CLASS_HIGH: 573 if (bfregi->ver < 2) 574 bfregn = -ENOMEM; 575 else 576 bfregn = alloc_high_class_bfreg(dev, bfregi); 577 break; 578 } 579 mutex_unlock(&bfregi->lock); 580 581 return bfregn; 582 } 583 584 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 585 { 586 mutex_lock(&bfregi->lock); 587 bfregi->count[bfregn]--; 588 mutex_unlock(&bfregi->lock); 589 } 590 591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 592 { 593 switch (state) { 594 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 601 default: return -1; 602 } 603 } 604 605 static int to_mlx5_st(enum ib_qp_type type) 606 { 607 switch (type) { 608 case IB_QPT_RC: return MLX5_QP_ST_RC; 609 case IB_QPT_UC: return MLX5_QP_ST_UC; 610 case IB_QPT_UD: return MLX5_QP_ST_UD; 611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 612 case IB_QPT_XRC_INI: 613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 614 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 616 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 617 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 618 case IB_QPT_RAW_PACKET: 619 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 620 case IB_QPT_MAX: 621 default: return -EINVAL; 622 } 623 } 624 625 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 626 struct mlx5_ib_cq *recv_cq); 627 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 628 struct mlx5_ib_cq *recv_cq); 629 630 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 631 struct mlx5_bfreg_info *bfregi, int bfregn, 632 bool dyn_bfreg) 633 { 634 int bfregs_per_sys_page; 635 int index_of_sys_page; 636 int offset; 637 638 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 639 MLX5_NON_FP_BFREGS_PER_UAR; 640 index_of_sys_page = bfregn / bfregs_per_sys_page; 641 642 if (dyn_bfreg) { 643 index_of_sys_page += bfregi->num_static_sys_pages; 644 if (bfregn > bfregi->num_dyn_bfregs || 645 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 646 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 647 return -EINVAL; 648 } 649 } 650 651 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 652 return bfregi->sys_pages[index_of_sys_page] + offset; 653 } 654 655 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 656 struct ib_pd *pd, 657 unsigned long addr, size_t size, 658 struct ib_umem **umem, 659 int *npages, int *page_shift, int *ncont, 660 u32 *offset) 661 { 662 int err; 663 664 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 665 if (IS_ERR(*umem)) { 666 mlx5_ib_dbg(dev, "umem_get failed\n"); 667 return PTR_ERR(*umem); 668 } 669 670 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 671 672 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 673 if (err) { 674 mlx5_ib_warn(dev, "bad offset\n"); 675 goto err_umem; 676 } 677 678 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 679 addr, size, *npages, *page_shift, *ncont, *offset); 680 681 return 0; 682 683 err_umem: 684 ib_umem_release(*umem); 685 *umem = NULL; 686 687 return err; 688 } 689 690 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 691 struct mlx5_ib_rwq *rwq) 692 { 693 struct mlx5_ib_ucontext *context; 694 695 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 696 atomic_dec(&dev->delay_drop.rqs_cnt); 697 698 context = to_mucontext(pd->uobject->context); 699 mlx5_ib_db_unmap_user(context, &rwq->db); 700 if (rwq->umem) 701 ib_umem_release(rwq->umem); 702 } 703 704 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 705 struct mlx5_ib_rwq *rwq, 706 struct mlx5_ib_create_wq *ucmd) 707 { 708 struct mlx5_ib_ucontext *context; 709 int page_shift = 0; 710 int npages; 711 u32 offset = 0; 712 int ncont = 0; 713 int err; 714 715 if (!ucmd->buf_addr) 716 return -EINVAL; 717 718 context = to_mucontext(pd->uobject->context); 719 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 720 rwq->buf_size, 0, 0); 721 if (IS_ERR(rwq->umem)) { 722 mlx5_ib_dbg(dev, "umem_get failed\n"); 723 err = PTR_ERR(rwq->umem); 724 return err; 725 } 726 727 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 728 &ncont, NULL); 729 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 730 &rwq->rq_page_offset); 731 if (err) { 732 mlx5_ib_warn(dev, "bad offset\n"); 733 goto err_umem; 734 } 735 736 rwq->rq_num_pas = ncont; 737 rwq->page_shift = page_shift; 738 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 739 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 740 741 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 742 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 743 npages, page_shift, ncont, offset); 744 745 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 746 if (err) { 747 mlx5_ib_dbg(dev, "map failed\n"); 748 goto err_umem; 749 } 750 751 rwq->create_type = MLX5_WQ_USER; 752 return 0; 753 754 err_umem: 755 ib_umem_release(rwq->umem); 756 return err; 757 } 758 759 static int adjust_bfregn(struct mlx5_ib_dev *dev, 760 struct mlx5_bfreg_info *bfregi, int bfregn) 761 { 762 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 763 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 764 } 765 766 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 767 struct mlx5_ib_qp *qp, struct ib_udata *udata, 768 struct ib_qp_init_attr *attr, 769 u32 **in, 770 struct mlx5_ib_create_qp_resp *resp, int *inlen, 771 struct mlx5_ib_qp_base *base) 772 { 773 struct mlx5_ib_ucontext *context; 774 struct mlx5_ib_create_qp ucmd; 775 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 776 int page_shift = 0; 777 int uar_index = 0; 778 int npages; 779 u32 offset = 0; 780 int bfregn; 781 int ncont = 0; 782 __be64 *pas; 783 void *qpc; 784 int err; 785 786 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 787 if (err) { 788 mlx5_ib_dbg(dev, "copy failed\n"); 789 return err; 790 } 791 792 context = to_mucontext(pd->uobject->context); 793 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 794 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 795 ucmd.bfreg_index, true); 796 if (uar_index < 0) 797 return uar_index; 798 799 bfregn = MLX5_IB_INVALID_BFREG; 800 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 801 /* 802 * TBD: should come from the verbs when we have the API 803 */ 804 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 805 bfregn = MLX5_CROSS_CHANNEL_BFREG; 806 } 807 else { 808 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 809 if (bfregn < 0) { 810 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 811 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 812 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 813 if (bfregn < 0) { 814 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 815 mlx5_ib_dbg(dev, "reverting to high latency\n"); 816 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 817 if (bfregn < 0) { 818 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 819 return bfregn; 820 } 821 } 822 } 823 } 824 825 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 826 if (bfregn != MLX5_IB_INVALID_BFREG) 827 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 828 false); 829 830 qp->rq.offset = 0; 831 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 832 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 833 834 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 835 if (err) 836 goto err_bfreg; 837 838 if (ucmd.buf_addr && ubuffer->buf_size) { 839 ubuffer->buf_addr = ucmd.buf_addr; 840 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 841 ubuffer->buf_size, 842 &ubuffer->umem, &npages, &page_shift, 843 &ncont, &offset); 844 if (err) 845 goto err_bfreg; 846 } else { 847 ubuffer->umem = NULL; 848 } 849 850 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 851 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 852 *in = kvzalloc(*inlen, GFP_KERNEL); 853 if (!*in) { 854 err = -ENOMEM; 855 goto err_umem; 856 } 857 858 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 859 if (ubuffer->umem) 860 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 861 862 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 863 864 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 865 MLX5_SET(qpc, qpc, page_offset, offset); 866 867 MLX5_SET(qpc, qpc, uar_page, uar_index); 868 if (bfregn != MLX5_IB_INVALID_BFREG) 869 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 870 else 871 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 872 qp->bfregn = bfregn; 873 874 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 875 if (err) { 876 mlx5_ib_dbg(dev, "map failed\n"); 877 goto err_free; 878 } 879 880 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 881 if (err) { 882 mlx5_ib_dbg(dev, "copy failed\n"); 883 goto err_unmap; 884 } 885 qp->create_type = MLX5_QP_USER; 886 887 return 0; 888 889 err_unmap: 890 mlx5_ib_db_unmap_user(context, &qp->db); 891 892 err_free: 893 kvfree(*in); 894 895 err_umem: 896 if (ubuffer->umem) 897 ib_umem_release(ubuffer->umem); 898 899 err_bfreg: 900 if (bfregn != MLX5_IB_INVALID_BFREG) 901 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 902 return err; 903 } 904 905 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 906 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 907 { 908 struct mlx5_ib_ucontext *context; 909 910 context = to_mucontext(pd->uobject->context); 911 mlx5_ib_db_unmap_user(context, &qp->db); 912 if (base->ubuffer.umem) 913 ib_umem_release(base->ubuffer.umem); 914 915 /* 916 * Free only the BFREGs which are handled by the kernel. 917 * BFREGs of UARs allocated dynamically are handled by user. 918 */ 919 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 920 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 921 } 922 923 static int create_kernel_qp(struct mlx5_ib_dev *dev, 924 struct ib_qp_init_attr *init_attr, 925 struct mlx5_ib_qp *qp, 926 u32 **in, int *inlen, 927 struct mlx5_ib_qp_base *base) 928 { 929 int uar_index; 930 void *qpc; 931 int err; 932 933 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 934 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 935 IB_QP_CREATE_IPOIB_UD_LSO | 936 IB_QP_CREATE_NETIF_QP | 937 mlx5_ib_create_qp_sqpn_qp1())) 938 return -EINVAL; 939 940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 941 qp->bf.bfreg = &dev->fp_bfreg; 942 else 943 qp->bf.bfreg = &dev->bfreg; 944 945 /* We need to divide by two since each register is comprised of 946 * two buffers of identical size, namely odd and even 947 */ 948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 949 uar_index = qp->bf.bfreg->index; 950 951 err = calc_sq_size(dev, init_attr, qp); 952 if (err < 0) { 953 mlx5_ib_dbg(dev, "err %d\n", err); 954 return err; 955 } 956 957 qp->rq.offset = 0; 958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 960 961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 962 if (err) { 963 mlx5_ib_dbg(dev, "err %d\n", err); 964 return err; 965 } 966 967 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 968 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 969 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 970 *in = kvzalloc(*inlen, GFP_KERNEL); 971 if (!*in) { 972 err = -ENOMEM; 973 goto err_buf; 974 } 975 976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 977 MLX5_SET(qpc, qpc, uar_page, uar_index); 978 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 979 980 /* Set "fast registration enabled" for all kernel QPs */ 981 MLX5_SET(qpc, qpc, fre, 1); 982 MLX5_SET(qpc, qpc, rlky, 1); 983 984 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 985 MLX5_SET(qpc, qpc, deth_sqpn, 1); 986 qp->flags |= MLX5_IB_QP_SQPN_QP1; 987 } 988 989 mlx5_fill_page_array(&qp->buf, 990 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 991 992 err = mlx5_db_alloc(dev->mdev, &qp->db); 993 if (err) { 994 mlx5_ib_dbg(dev, "err %d\n", err); 995 goto err_free; 996 } 997 998 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 999 sizeof(*qp->sq.wrid), GFP_KERNEL); 1000 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1001 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1002 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1003 sizeof(*qp->rq.wrid), GFP_KERNEL); 1004 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1005 sizeof(*qp->sq.w_list), GFP_KERNEL); 1006 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1007 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1008 1009 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1010 !qp->sq.w_list || !qp->sq.wqe_head) { 1011 err = -ENOMEM; 1012 goto err_wrid; 1013 } 1014 qp->create_type = MLX5_QP_KERNEL; 1015 1016 return 0; 1017 1018 err_wrid: 1019 kvfree(qp->sq.wqe_head); 1020 kvfree(qp->sq.w_list); 1021 kvfree(qp->sq.wrid); 1022 kvfree(qp->sq.wr_data); 1023 kvfree(qp->rq.wrid); 1024 mlx5_db_free(dev->mdev, &qp->db); 1025 1026 err_free: 1027 kvfree(*in); 1028 1029 err_buf: 1030 mlx5_buf_free(dev->mdev, &qp->buf); 1031 return err; 1032 } 1033 1034 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1035 { 1036 kvfree(qp->sq.wqe_head); 1037 kvfree(qp->sq.w_list); 1038 kvfree(qp->sq.wrid); 1039 kvfree(qp->sq.wr_data); 1040 kvfree(qp->rq.wrid); 1041 mlx5_db_free(dev->mdev, &qp->db); 1042 mlx5_buf_free(dev->mdev, &qp->buf); 1043 } 1044 1045 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1046 { 1047 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1048 (attr->qp_type == MLX5_IB_QPT_DCI) || 1049 (attr->qp_type == IB_QPT_XRC_INI)) 1050 return MLX5_SRQ_RQ; 1051 else if (!qp->has_rq) 1052 return MLX5_ZERO_LEN_RQ; 1053 else 1054 return MLX5_NON_ZERO_RQ; 1055 } 1056 1057 static int is_connected(enum ib_qp_type qp_type) 1058 { 1059 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1060 return 1; 1061 1062 return 0; 1063 } 1064 1065 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1066 struct mlx5_ib_qp *qp, 1067 struct mlx5_ib_sq *sq, u32 tdn) 1068 { 1069 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1070 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1071 1072 MLX5_SET(tisc, tisc, transport_domain, tdn); 1073 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1074 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1075 1076 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1077 } 1078 1079 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1080 struct mlx5_ib_sq *sq) 1081 { 1082 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1083 } 1084 1085 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1086 struct mlx5_ib_sq *sq, void *qpin, 1087 struct ib_pd *pd) 1088 { 1089 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1090 __be64 *pas; 1091 void *in; 1092 void *sqc; 1093 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1094 void *wq; 1095 int inlen; 1096 int err; 1097 int page_shift = 0; 1098 int npages; 1099 int ncont = 0; 1100 u32 offset = 0; 1101 1102 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1103 &sq->ubuffer.umem, &npages, &page_shift, 1104 &ncont, &offset); 1105 if (err) 1106 return err; 1107 1108 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1109 in = kvzalloc(inlen, GFP_KERNEL); 1110 if (!in) { 1111 err = -ENOMEM; 1112 goto err_umem; 1113 } 1114 1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1117 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1118 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1119 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1120 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1121 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1122 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1123 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1124 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1125 MLX5_CAP_ETH(dev->mdev, swp)) 1126 MLX5_SET(sqc, sqc, allow_swp, 1); 1127 1128 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1129 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1130 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1131 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1132 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1134 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1135 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1136 MLX5_SET(wq, wq, page_offset, offset); 1137 1138 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1139 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1140 1141 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1142 1143 kvfree(in); 1144 1145 if (err) 1146 goto err_umem; 1147 1148 return 0; 1149 1150 err_umem: 1151 ib_umem_release(sq->ubuffer.umem); 1152 sq->ubuffer.umem = NULL; 1153 1154 return err; 1155 } 1156 1157 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1158 struct mlx5_ib_sq *sq) 1159 { 1160 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1161 ib_umem_release(sq->ubuffer.umem); 1162 } 1163 1164 static size_t get_rq_pas_size(void *qpc) 1165 { 1166 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1167 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1168 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1169 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1170 u32 po_quanta = 1 << (log_page_size - 6); 1171 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1172 u32 page_size = 1 << log_page_size; 1173 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1174 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1175 1176 return rq_num_pas * sizeof(u64); 1177 } 1178 1179 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1180 struct mlx5_ib_rq *rq, void *qpin, 1181 size_t qpinlen) 1182 { 1183 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1184 __be64 *pas; 1185 __be64 *qp_pas; 1186 void *in; 1187 void *rqc; 1188 void *wq; 1189 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1190 size_t rq_pas_size = get_rq_pas_size(qpc); 1191 size_t inlen; 1192 int err; 1193 1194 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1195 return -EINVAL; 1196 1197 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1198 in = kvzalloc(inlen, GFP_KERNEL); 1199 if (!in) 1200 return -ENOMEM; 1201 1202 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1203 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1204 MLX5_SET(rqc, rqc, vsd, 1); 1205 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1206 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1207 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1208 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1209 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1210 1211 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1212 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1213 1214 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1215 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1216 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1217 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1218 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1219 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1220 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1221 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1222 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1223 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1224 1225 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1226 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1227 memcpy(pas, qp_pas, rq_pas_size); 1228 1229 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1230 1231 kvfree(in); 1232 1233 return err; 1234 } 1235 1236 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1237 struct mlx5_ib_rq *rq) 1238 { 1239 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1240 } 1241 1242 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1243 { 1244 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1245 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1246 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1247 } 1248 1249 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1250 struct mlx5_ib_rq *rq, u32 tdn, 1251 bool tunnel_offload_en) 1252 { 1253 u32 *in; 1254 void *tirc; 1255 int inlen; 1256 int err; 1257 1258 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1259 in = kvzalloc(inlen, GFP_KERNEL); 1260 if (!in) 1261 return -ENOMEM; 1262 1263 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1264 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1265 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1266 MLX5_SET(tirc, tirc, transport_domain, tdn); 1267 if (tunnel_offload_en) 1268 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1269 1270 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1271 1272 kvfree(in); 1273 1274 return err; 1275 } 1276 1277 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1278 struct mlx5_ib_rq *rq) 1279 { 1280 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1281 } 1282 1283 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1284 u32 *in, size_t inlen, 1285 struct ib_pd *pd) 1286 { 1287 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1288 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1289 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1290 struct ib_uobject *uobj = pd->uobject; 1291 struct ib_ucontext *ucontext = uobj->context; 1292 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1293 int err; 1294 u32 tdn = mucontext->tdn; 1295 1296 if (qp->sq.wqe_cnt) { 1297 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1298 if (err) 1299 return err; 1300 1301 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1302 if (err) 1303 goto err_destroy_tis; 1304 1305 sq->base.container_mibqp = qp; 1306 sq->base.mqp.event = mlx5_ib_qp_event; 1307 } 1308 1309 if (qp->rq.wqe_cnt) { 1310 rq->base.container_mibqp = qp; 1311 1312 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1313 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1314 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1315 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1316 err = create_raw_packet_qp_rq(dev, rq, in, inlen); 1317 if (err) 1318 goto err_destroy_sq; 1319 1320 1321 err = create_raw_packet_qp_tir(dev, rq, tdn, 1322 qp->tunnel_offload_en); 1323 if (err) 1324 goto err_destroy_rq; 1325 } 1326 1327 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1328 rq->base.mqp.qpn; 1329 1330 return 0; 1331 1332 err_destroy_rq: 1333 destroy_raw_packet_qp_rq(dev, rq); 1334 err_destroy_sq: 1335 if (!qp->sq.wqe_cnt) 1336 return err; 1337 destroy_raw_packet_qp_sq(dev, sq); 1338 err_destroy_tis: 1339 destroy_raw_packet_qp_tis(dev, sq); 1340 1341 return err; 1342 } 1343 1344 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1345 struct mlx5_ib_qp *qp) 1346 { 1347 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1348 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1349 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1350 1351 if (qp->rq.wqe_cnt) { 1352 destroy_raw_packet_qp_tir(dev, rq); 1353 destroy_raw_packet_qp_rq(dev, rq); 1354 } 1355 1356 if (qp->sq.wqe_cnt) { 1357 destroy_raw_packet_qp_sq(dev, sq); 1358 destroy_raw_packet_qp_tis(dev, sq); 1359 } 1360 } 1361 1362 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1363 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1364 { 1365 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1366 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1367 1368 sq->sq = &qp->sq; 1369 rq->rq = &qp->rq; 1370 sq->doorbell = &qp->db; 1371 rq->doorbell = &qp->db; 1372 } 1373 1374 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1375 { 1376 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1377 } 1378 1379 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1380 struct ib_pd *pd, 1381 struct ib_qp_init_attr *init_attr, 1382 struct ib_udata *udata) 1383 { 1384 struct ib_uobject *uobj = pd->uobject; 1385 struct ib_ucontext *ucontext = uobj->context; 1386 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1387 struct mlx5_ib_create_qp_resp resp = {}; 1388 int inlen; 1389 int err; 1390 u32 *in; 1391 void *tirc; 1392 void *hfso; 1393 u32 selected_fields = 0; 1394 size_t min_resp_len; 1395 u32 tdn = mucontext->tdn; 1396 struct mlx5_ib_create_qp_rss ucmd = {}; 1397 size_t required_cmd_sz; 1398 1399 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1400 return -EOPNOTSUPP; 1401 1402 if (init_attr->create_flags || init_attr->send_cq) 1403 return -EINVAL; 1404 1405 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1406 if (udata->outlen < min_resp_len) 1407 return -EINVAL; 1408 1409 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1410 if (udata->inlen < required_cmd_sz) { 1411 mlx5_ib_dbg(dev, "invalid inlen\n"); 1412 return -EINVAL; 1413 } 1414 1415 if (udata->inlen > sizeof(ucmd) && 1416 !ib_is_udata_cleared(udata, sizeof(ucmd), 1417 udata->inlen - sizeof(ucmd))) { 1418 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1419 return -EOPNOTSUPP; 1420 } 1421 1422 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1423 mlx5_ib_dbg(dev, "copy failed\n"); 1424 return -EFAULT; 1425 } 1426 1427 if (ucmd.comp_mask) { 1428 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1429 return -EOPNOTSUPP; 1430 } 1431 1432 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1433 mlx5_ib_dbg(dev, "invalid flags\n"); 1434 return -EOPNOTSUPP; 1435 } 1436 1437 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1438 !tunnel_offload_supported(dev->mdev)) { 1439 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1440 return -EOPNOTSUPP; 1441 } 1442 1443 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1444 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1445 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1446 return -EOPNOTSUPP; 1447 } 1448 1449 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1450 if (err) { 1451 mlx5_ib_dbg(dev, "copy failed\n"); 1452 return -EINVAL; 1453 } 1454 1455 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1456 in = kvzalloc(inlen, GFP_KERNEL); 1457 if (!in) 1458 return -ENOMEM; 1459 1460 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1461 MLX5_SET(tirc, tirc, disp_type, 1462 MLX5_TIRC_DISP_TYPE_INDIRECT); 1463 MLX5_SET(tirc, tirc, indirect_table, 1464 init_attr->rwq_ind_tbl->ind_tbl_num); 1465 MLX5_SET(tirc, tirc, transport_domain, tdn); 1466 1467 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1468 1469 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1470 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1471 1472 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1473 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1474 else 1475 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1476 1477 switch (ucmd.rx_hash_function) { 1478 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1479 { 1480 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1481 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1482 1483 if (len != ucmd.rx_key_len) { 1484 err = -EINVAL; 1485 goto err; 1486 } 1487 1488 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1489 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1490 memcpy(rss_key, ucmd.rx_hash_key, len); 1491 break; 1492 } 1493 default: 1494 err = -EOPNOTSUPP; 1495 goto err; 1496 } 1497 1498 if (!ucmd.rx_hash_fields_mask) { 1499 /* special case when this TIR serves as steering entry without hashing */ 1500 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1501 goto create_tir; 1502 err = -EINVAL; 1503 goto err; 1504 } 1505 1506 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1507 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1508 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1509 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1510 err = -EINVAL; 1511 goto err; 1512 } 1513 1514 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1515 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1517 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1518 MLX5_L3_PROT_TYPE_IPV4); 1519 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1520 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1521 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1522 MLX5_L3_PROT_TYPE_IPV6); 1523 1524 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1525 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1526 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1527 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1528 err = -EINVAL; 1529 goto err; 1530 } 1531 1532 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1533 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1534 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1535 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1536 MLX5_L4_PROT_TYPE_TCP); 1537 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1538 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1539 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1540 MLX5_L4_PROT_TYPE_UDP); 1541 1542 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1544 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1545 1546 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1548 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1549 1550 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1552 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1553 1554 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1555 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1556 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1557 1558 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1559 1560 create_tir: 1561 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1562 1563 if (err) 1564 goto err; 1565 1566 kvfree(in); 1567 /* qpn is reserved for that QP */ 1568 qp->trans_qp.base.mqp.qpn = 0; 1569 qp->flags |= MLX5_IB_QP_RSS; 1570 return 0; 1571 1572 err: 1573 kvfree(in); 1574 return err; 1575 } 1576 1577 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1578 struct ib_qp_init_attr *init_attr, 1579 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1580 { 1581 struct mlx5_ib_resources *devr = &dev->devr; 1582 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1583 struct mlx5_core_dev *mdev = dev->mdev; 1584 struct mlx5_ib_create_qp_resp resp; 1585 struct mlx5_ib_cq *send_cq; 1586 struct mlx5_ib_cq *recv_cq; 1587 unsigned long flags; 1588 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1589 struct mlx5_ib_create_qp ucmd; 1590 struct mlx5_ib_qp_base *base; 1591 int mlx5_st; 1592 void *qpc; 1593 u32 *in; 1594 int err; 1595 1596 mutex_init(&qp->mutex); 1597 spin_lock_init(&qp->sq.lock); 1598 spin_lock_init(&qp->rq.lock); 1599 1600 mlx5_st = to_mlx5_st(init_attr->qp_type); 1601 if (mlx5_st < 0) 1602 return -EINVAL; 1603 1604 if (init_attr->rwq_ind_tbl) { 1605 if (!udata) 1606 return -ENOSYS; 1607 1608 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1609 return err; 1610 } 1611 1612 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1613 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1614 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1615 return -EINVAL; 1616 } else { 1617 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1618 } 1619 } 1620 1621 if (init_attr->create_flags & 1622 (IB_QP_CREATE_CROSS_CHANNEL | 1623 IB_QP_CREATE_MANAGED_SEND | 1624 IB_QP_CREATE_MANAGED_RECV)) { 1625 if (!MLX5_CAP_GEN(mdev, cd)) { 1626 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1627 return -EINVAL; 1628 } 1629 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1630 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1631 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1632 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1633 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1634 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1635 } 1636 1637 if (init_attr->qp_type == IB_QPT_UD && 1638 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1639 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1640 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1641 return -EOPNOTSUPP; 1642 } 1643 1644 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1645 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1646 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1647 return -EOPNOTSUPP; 1648 } 1649 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1650 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1651 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1652 return -EOPNOTSUPP; 1653 } 1654 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1655 } 1656 1657 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1658 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1659 1660 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1661 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1662 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1663 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1664 return -EOPNOTSUPP; 1665 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1666 } 1667 1668 if (pd && pd->uobject) { 1669 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1670 mlx5_ib_dbg(dev, "copy failed\n"); 1671 return -EFAULT; 1672 } 1673 1674 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1675 &ucmd, udata->inlen, &uidx); 1676 if (err) 1677 return err; 1678 1679 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1680 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1681 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1682 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1683 !tunnel_offload_supported(mdev)) { 1684 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1685 return -EOPNOTSUPP; 1686 } 1687 qp->tunnel_offload_en = true; 1688 } 1689 1690 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1691 if (init_attr->qp_type != IB_QPT_UD || 1692 (MLX5_CAP_GEN(dev->mdev, port_type) != 1693 MLX5_CAP_PORT_TYPE_IB) || 1694 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1695 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1696 return -EOPNOTSUPP; 1697 } 1698 1699 qp->flags |= MLX5_IB_QP_UNDERLAY; 1700 qp->underlay_qpn = init_attr->source_qpn; 1701 } 1702 } else { 1703 qp->wq_sig = !!wq_signature; 1704 } 1705 1706 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1707 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1708 &qp->raw_packet_qp.rq.base : 1709 &qp->trans_qp.base; 1710 1711 qp->has_rq = qp_has_rq(init_attr); 1712 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1713 qp, (pd && pd->uobject) ? &ucmd : NULL); 1714 if (err) { 1715 mlx5_ib_dbg(dev, "err %d\n", err); 1716 return err; 1717 } 1718 1719 if (pd) { 1720 if (pd->uobject) { 1721 __u32 max_wqes = 1722 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1723 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1724 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1725 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1726 mlx5_ib_dbg(dev, "invalid rq params\n"); 1727 return -EINVAL; 1728 } 1729 if (ucmd.sq_wqe_count > max_wqes) { 1730 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1731 ucmd.sq_wqe_count, max_wqes); 1732 return -EINVAL; 1733 } 1734 if (init_attr->create_flags & 1735 mlx5_ib_create_qp_sqpn_qp1()) { 1736 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1737 return -EINVAL; 1738 } 1739 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1740 &resp, &inlen, base); 1741 if (err) 1742 mlx5_ib_dbg(dev, "err %d\n", err); 1743 } else { 1744 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1745 base); 1746 if (err) 1747 mlx5_ib_dbg(dev, "err %d\n", err); 1748 } 1749 1750 if (err) 1751 return err; 1752 } else { 1753 in = kvzalloc(inlen, GFP_KERNEL); 1754 if (!in) 1755 return -ENOMEM; 1756 1757 qp->create_type = MLX5_QP_EMPTY; 1758 } 1759 1760 if (is_sqp(init_attr->qp_type)) 1761 qp->port = init_attr->port_num; 1762 1763 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1764 1765 MLX5_SET(qpc, qpc, st, mlx5_st); 1766 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1767 1768 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1769 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1770 else 1771 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1772 1773 1774 if (qp->wq_sig) 1775 MLX5_SET(qpc, qpc, wq_signature, 1); 1776 1777 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1778 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1779 1780 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1781 MLX5_SET(qpc, qpc, cd_master, 1); 1782 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1783 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1784 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1785 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1786 1787 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1788 int rcqe_sz; 1789 int scqe_sz; 1790 1791 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1792 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1793 1794 if (rcqe_sz == 128) 1795 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1796 else 1797 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1798 1799 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1800 if (scqe_sz == 128) 1801 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1802 else 1803 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1804 } 1805 } 1806 1807 if (qp->rq.wqe_cnt) { 1808 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1809 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1810 } 1811 1812 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1813 1814 if (qp->sq.wqe_cnt) { 1815 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1816 } else { 1817 MLX5_SET(qpc, qpc, no_sq, 1); 1818 if (init_attr->srq && 1819 init_attr->srq->srq_type == IB_SRQT_TM) 1820 MLX5_SET(qpc, qpc, offload_type, 1821 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1822 } 1823 1824 /* Set default resources */ 1825 switch (init_attr->qp_type) { 1826 case IB_QPT_XRC_TGT: 1827 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1828 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1829 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1830 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1831 break; 1832 case IB_QPT_XRC_INI: 1833 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1834 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1835 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1836 break; 1837 default: 1838 if (init_attr->srq) { 1839 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1840 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1841 } else { 1842 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1843 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1844 } 1845 } 1846 1847 if (init_attr->send_cq) 1848 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1849 1850 if (init_attr->recv_cq) 1851 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1852 1853 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1854 1855 /* 0xffffff means we ask to work with cqe version 0 */ 1856 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1857 MLX5_SET(qpc, qpc, user_index, uidx); 1858 1859 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1860 if (init_attr->qp_type == IB_QPT_UD && 1861 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1862 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1863 qp->flags |= MLX5_IB_QP_LSO; 1864 } 1865 1866 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1867 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1868 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1869 err = -EOPNOTSUPP; 1870 goto err; 1871 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1872 MLX5_SET(qpc, qpc, end_padding_mode, 1873 MLX5_WQ_END_PAD_MODE_ALIGN); 1874 } else { 1875 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1876 } 1877 } 1878 1879 if (inlen < 0) { 1880 err = -EINVAL; 1881 goto err; 1882 } 1883 1884 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1885 qp->flags & MLX5_IB_QP_UNDERLAY) { 1886 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1887 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1888 err = create_raw_packet_qp(dev, qp, in, inlen, pd); 1889 } else { 1890 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1891 } 1892 1893 if (err) { 1894 mlx5_ib_dbg(dev, "create qp failed\n"); 1895 goto err_create; 1896 } 1897 1898 kvfree(in); 1899 1900 base->container_mibqp = qp; 1901 base->mqp.event = mlx5_ib_qp_event; 1902 1903 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1904 &send_cq, &recv_cq); 1905 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1906 mlx5_ib_lock_cqs(send_cq, recv_cq); 1907 /* Maintain device to QPs access, needed for further handling via reset 1908 * flow 1909 */ 1910 list_add_tail(&qp->qps_list, &dev->qp_list); 1911 /* Maintain CQ to QPs access, needed for further handling via reset flow 1912 */ 1913 if (send_cq) 1914 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1915 if (recv_cq) 1916 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1917 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1918 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1919 1920 return 0; 1921 1922 err_create: 1923 if (qp->create_type == MLX5_QP_USER) 1924 destroy_qp_user(dev, pd, qp, base); 1925 else if (qp->create_type == MLX5_QP_KERNEL) 1926 destroy_qp_kernel(dev, qp); 1927 1928 err: 1929 kvfree(in); 1930 return err; 1931 } 1932 1933 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1934 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1935 { 1936 if (send_cq) { 1937 if (recv_cq) { 1938 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1939 spin_lock(&send_cq->lock); 1940 spin_lock_nested(&recv_cq->lock, 1941 SINGLE_DEPTH_NESTING); 1942 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1943 spin_lock(&send_cq->lock); 1944 __acquire(&recv_cq->lock); 1945 } else { 1946 spin_lock(&recv_cq->lock); 1947 spin_lock_nested(&send_cq->lock, 1948 SINGLE_DEPTH_NESTING); 1949 } 1950 } else { 1951 spin_lock(&send_cq->lock); 1952 __acquire(&recv_cq->lock); 1953 } 1954 } else if (recv_cq) { 1955 spin_lock(&recv_cq->lock); 1956 __acquire(&send_cq->lock); 1957 } else { 1958 __acquire(&send_cq->lock); 1959 __acquire(&recv_cq->lock); 1960 } 1961 } 1962 1963 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1964 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1965 { 1966 if (send_cq) { 1967 if (recv_cq) { 1968 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1969 spin_unlock(&recv_cq->lock); 1970 spin_unlock(&send_cq->lock); 1971 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1972 __release(&recv_cq->lock); 1973 spin_unlock(&send_cq->lock); 1974 } else { 1975 spin_unlock(&send_cq->lock); 1976 spin_unlock(&recv_cq->lock); 1977 } 1978 } else { 1979 __release(&recv_cq->lock); 1980 spin_unlock(&send_cq->lock); 1981 } 1982 } else if (recv_cq) { 1983 __release(&send_cq->lock); 1984 spin_unlock(&recv_cq->lock); 1985 } else { 1986 __release(&recv_cq->lock); 1987 __release(&send_cq->lock); 1988 } 1989 } 1990 1991 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1992 { 1993 return to_mpd(qp->ibqp.pd); 1994 } 1995 1996 static void get_cqs(enum ib_qp_type qp_type, 1997 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1998 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1999 { 2000 switch (qp_type) { 2001 case IB_QPT_XRC_TGT: 2002 *send_cq = NULL; 2003 *recv_cq = NULL; 2004 break; 2005 case MLX5_IB_QPT_REG_UMR: 2006 case IB_QPT_XRC_INI: 2007 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2008 *recv_cq = NULL; 2009 break; 2010 2011 case IB_QPT_SMI: 2012 case MLX5_IB_QPT_HW_GSI: 2013 case IB_QPT_RC: 2014 case IB_QPT_UC: 2015 case IB_QPT_UD: 2016 case IB_QPT_RAW_IPV6: 2017 case IB_QPT_RAW_ETHERTYPE: 2018 case IB_QPT_RAW_PACKET: 2019 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2020 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2021 break; 2022 2023 case IB_QPT_MAX: 2024 default: 2025 *send_cq = NULL; 2026 *recv_cq = NULL; 2027 break; 2028 } 2029 } 2030 2031 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2032 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2033 u8 lag_tx_affinity); 2034 2035 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2036 { 2037 struct mlx5_ib_cq *send_cq, *recv_cq; 2038 struct mlx5_ib_qp_base *base; 2039 unsigned long flags; 2040 int err; 2041 2042 if (qp->ibqp.rwq_ind_tbl) { 2043 destroy_rss_raw_qp_tir(dev, qp); 2044 return; 2045 } 2046 2047 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2048 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2049 &qp->raw_packet_qp.rq.base : 2050 &qp->trans_qp.base; 2051 2052 if (qp->state != IB_QPS_RESET) { 2053 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2054 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2055 err = mlx5_core_qp_modify(dev->mdev, 2056 MLX5_CMD_OP_2RST_QP, 0, 2057 NULL, &base->mqp); 2058 } else { 2059 struct mlx5_modify_raw_qp_param raw_qp_param = { 2060 .operation = MLX5_CMD_OP_2RST_QP 2061 }; 2062 2063 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2064 } 2065 if (err) 2066 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2067 base->mqp.qpn); 2068 } 2069 2070 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2071 &send_cq, &recv_cq); 2072 2073 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2074 mlx5_ib_lock_cqs(send_cq, recv_cq); 2075 /* del from lists under both locks above to protect reset flow paths */ 2076 list_del(&qp->qps_list); 2077 if (send_cq) 2078 list_del(&qp->cq_send_list); 2079 2080 if (recv_cq) 2081 list_del(&qp->cq_recv_list); 2082 2083 if (qp->create_type == MLX5_QP_KERNEL) { 2084 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2085 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2086 if (send_cq != recv_cq) 2087 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2088 NULL); 2089 } 2090 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2091 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2092 2093 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2094 qp->flags & MLX5_IB_QP_UNDERLAY) { 2095 destroy_raw_packet_qp(dev, qp); 2096 } else { 2097 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2098 if (err) 2099 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2100 base->mqp.qpn); 2101 } 2102 2103 if (qp->create_type == MLX5_QP_KERNEL) 2104 destroy_qp_kernel(dev, qp); 2105 else if (qp->create_type == MLX5_QP_USER) 2106 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2107 } 2108 2109 static const char *ib_qp_type_str(enum ib_qp_type type) 2110 { 2111 switch (type) { 2112 case IB_QPT_SMI: 2113 return "IB_QPT_SMI"; 2114 case IB_QPT_GSI: 2115 return "IB_QPT_GSI"; 2116 case IB_QPT_RC: 2117 return "IB_QPT_RC"; 2118 case IB_QPT_UC: 2119 return "IB_QPT_UC"; 2120 case IB_QPT_UD: 2121 return "IB_QPT_UD"; 2122 case IB_QPT_RAW_IPV6: 2123 return "IB_QPT_RAW_IPV6"; 2124 case IB_QPT_RAW_ETHERTYPE: 2125 return "IB_QPT_RAW_ETHERTYPE"; 2126 case IB_QPT_XRC_INI: 2127 return "IB_QPT_XRC_INI"; 2128 case IB_QPT_XRC_TGT: 2129 return "IB_QPT_XRC_TGT"; 2130 case IB_QPT_RAW_PACKET: 2131 return "IB_QPT_RAW_PACKET"; 2132 case MLX5_IB_QPT_REG_UMR: 2133 return "MLX5_IB_QPT_REG_UMR"; 2134 case IB_QPT_DRIVER: 2135 return "IB_QPT_DRIVER"; 2136 case IB_QPT_MAX: 2137 default: 2138 return "Invalid QP type"; 2139 } 2140 } 2141 2142 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2143 struct ib_qp_init_attr *attr, 2144 struct mlx5_ib_create_qp *ucmd) 2145 { 2146 struct mlx5_ib_dev *dev; 2147 struct mlx5_ib_qp *qp; 2148 int err = 0; 2149 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2150 void *dctc; 2151 2152 if (!attr->srq || !attr->recv_cq) 2153 return ERR_PTR(-EINVAL); 2154 2155 dev = to_mdev(pd->device); 2156 2157 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2158 ucmd, sizeof(*ucmd), &uidx); 2159 if (err) 2160 return ERR_PTR(err); 2161 2162 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2163 if (!qp) 2164 return ERR_PTR(-ENOMEM); 2165 2166 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2167 if (!qp->dct.in) { 2168 err = -ENOMEM; 2169 goto err_free; 2170 } 2171 2172 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2173 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2174 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2175 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2176 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2177 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2178 MLX5_SET(dctc, dctc, user_index, uidx); 2179 2180 qp->state = IB_QPS_RESET; 2181 2182 return &qp->ibqp; 2183 err_free: 2184 kfree(qp); 2185 return ERR_PTR(err); 2186 } 2187 2188 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2189 struct ib_qp_init_attr *init_attr, 2190 struct mlx5_ib_create_qp *ucmd, 2191 struct ib_udata *udata) 2192 { 2193 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2194 int err; 2195 2196 if (!udata) 2197 return -EINVAL; 2198 2199 if (udata->inlen < sizeof(*ucmd)) { 2200 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2201 return -EINVAL; 2202 } 2203 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2204 if (err) 2205 return err; 2206 2207 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2208 init_attr->qp_type = MLX5_IB_QPT_DCI; 2209 } else { 2210 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2211 init_attr->qp_type = MLX5_IB_QPT_DCT; 2212 } else { 2213 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2214 return -EINVAL; 2215 } 2216 } 2217 2218 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2219 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2220 return -EOPNOTSUPP; 2221 } 2222 2223 return 0; 2224 } 2225 2226 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2227 struct ib_qp_init_attr *verbs_init_attr, 2228 struct ib_udata *udata) 2229 { 2230 struct mlx5_ib_dev *dev; 2231 struct mlx5_ib_qp *qp; 2232 u16 xrcdn = 0; 2233 int err; 2234 struct ib_qp_init_attr mlx_init_attr; 2235 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2236 2237 if (pd) { 2238 dev = to_mdev(pd->device); 2239 2240 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2241 if (!pd->uobject) { 2242 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2243 return ERR_PTR(-EINVAL); 2244 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2245 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2246 return ERR_PTR(-EINVAL); 2247 } 2248 } 2249 } else { 2250 /* being cautious here */ 2251 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2252 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2253 pr_warn("%s: no PD for transport %s\n", __func__, 2254 ib_qp_type_str(init_attr->qp_type)); 2255 return ERR_PTR(-EINVAL); 2256 } 2257 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2258 } 2259 2260 if (init_attr->qp_type == IB_QPT_DRIVER) { 2261 struct mlx5_ib_create_qp ucmd; 2262 2263 init_attr = &mlx_init_attr; 2264 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2265 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2266 if (err) 2267 return ERR_PTR(err); 2268 2269 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2270 if (init_attr->cap.max_recv_wr || 2271 init_attr->cap.max_recv_sge) { 2272 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2273 return ERR_PTR(-EINVAL); 2274 } 2275 } else { 2276 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2277 } 2278 } 2279 2280 switch (init_attr->qp_type) { 2281 case IB_QPT_XRC_TGT: 2282 case IB_QPT_XRC_INI: 2283 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2284 mlx5_ib_dbg(dev, "XRC not supported\n"); 2285 return ERR_PTR(-ENOSYS); 2286 } 2287 init_attr->recv_cq = NULL; 2288 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2289 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2290 init_attr->send_cq = NULL; 2291 } 2292 2293 /* fall through */ 2294 case IB_QPT_RAW_PACKET: 2295 case IB_QPT_RC: 2296 case IB_QPT_UC: 2297 case IB_QPT_UD: 2298 case IB_QPT_SMI: 2299 case MLX5_IB_QPT_HW_GSI: 2300 case MLX5_IB_QPT_REG_UMR: 2301 case MLX5_IB_QPT_DCI: 2302 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2303 if (!qp) 2304 return ERR_PTR(-ENOMEM); 2305 2306 err = create_qp_common(dev, pd, init_attr, udata, qp); 2307 if (err) { 2308 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2309 kfree(qp); 2310 return ERR_PTR(err); 2311 } 2312 2313 if (is_qp0(init_attr->qp_type)) 2314 qp->ibqp.qp_num = 0; 2315 else if (is_qp1(init_attr->qp_type)) 2316 qp->ibqp.qp_num = 1; 2317 else 2318 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2319 2320 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2321 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2322 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2323 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2324 2325 qp->trans_qp.xrcdn = xrcdn; 2326 2327 break; 2328 2329 case IB_QPT_GSI: 2330 return mlx5_ib_gsi_create_qp(pd, init_attr); 2331 2332 case IB_QPT_RAW_IPV6: 2333 case IB_QPT_RAW_ETHERTYPE: 2334 case IB_QPT_MAX: 2335 default: 2336 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2337 init_attr->qp_type); 2338 /* Don't support raw QPs */ 2339 return ERR_PTR(-EINVAL); 2340 } 2341 2342 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2343 qp->qp_sub_type = init_attr->qp_type; 2344 2345 return &qp->ibqp; 2346 } 2347 2348 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2349 { 2350 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2351 2352 if (mqp->state == IB_QPS_RTR) { 2353 int err; 2354 2355 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2356 if (err) { 2357 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2358 return err; 2359 } 2360 } 2361 2362 kfree(mqp->dct.in); 2363 kfree(mqp); 2364 return 0; 2365 } 2366 2367 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2368 { 2369 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2370 struct mlx5_ib_qp *mqp = to_mqp(qp); 2371 2372 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2373 return mlx5_ib_gsi_destroy_qp(qp); 2374 2375 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2376 return mlx5_ib_destroy_dct(mqp); 2377 2378 destroy_qp_common(dev, mqp); 2379 2380 kfree(mqp); 2381 2382 return 0; 2383 } 2384 2385 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2386 int attr_mask) 2387 { 2388 u32 hw_access_flags = 0; 2389 u8 dest_rd_atomic; 2390 u32 access_flags; 2391 2392 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2393 dest_rd_atomic = attr->max_dest_rd_atomic; 2394 else 2395 dest_rd_atomic = qp->trans_qp.resp_depth; 2396 2397 if (attr_mask & IB_QP_ACCESS_FLAGS) 2398 access_flags = attr->qp_access_flags; 2399 else 2400 access_flags = qp->trans_qp.atomic_rd_en; 2401 2402 if (!dest_rd_atomic) 2403 access_flags &= IB_ACCESS_REMOTE_WRITE; 2404 2405 if (access_flags & IB_ACCESS_REMOTE_READ) 2406 hw_access_flags |= MLX5_QP_BIT_RRE; 2407 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2408 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2409 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2410 hw_access_flags |= MLX5_QP_BIT_RWE; 2411 2412 return cpu_to_be32(hw_access_flags); 2413 } 2414 2415 enum { 2416 MLX5_PATH_FLAG_FL = 1 << 0, 2417 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2418 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2419 }; 2420 2421 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2422 { 2423 if (rate == IB_RATE_PORT_CURRENT) { 2424 return 0; 2425 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2426 return -EINVAL; 2427 } else { 2428 while (rate != IB_RATE_2_5_GBPS && 2429 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2430 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2431 --rate; 2432 } 2433 2434 return rate + MLX5_STAT_RATE_OFFSET; 2435 } 2436 2437 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2438 struct mlx5_ib_sq *sq, u8 sl) 2439 { 2440 void *in; 2441 void *tisc; 2442 int inlen; 2443 int err; 2444 2445 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2446 in = kvzalloc(inlen, GFP_KERNEL); 2447 if (!in) 2448 return -ENOMEM; 2449 2450 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2451 2452 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2453 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2454 2455 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2456 2457 kvfree(in); 2458 2459 return err; 2460 } 2461 2462 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2463 struct mlx5_ib_sq *sq, u8 tx_affinity) 2464 { 2465 void *in; 2466 void *tisc; 2467 int inlen; 2468 int err; 2469 2470 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2471 in = kvzalloc(inlen, GFP_KERNEL); 2472 if (!in) 2473 return -ENOMEM; 2474 2475 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2476 2477 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2478 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2479 2480 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2481 2482 kvfree(in); 2483 2484 return err; 2485 } 2486 2487 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2488 const struct rdma_ah_attr *ah, 2489 struct mlx5_qp_path *path, u8 port, int attr_mask, 2490 u32 path_flags, const struct ib_qp_attr *attr, 2491 bool alt) 2492 { 2493 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2494 int err; 2495 enum ib_gid_type gid_type; 2496 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2497 u8 sl = rdma_ah_get_sl(ah); 2498 2499 if (attr_mask & IB_QP_PKEY_INDEX) 2500 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2501 attr->pkey_index); 2502 2503 if (ah_flags & IB_AH_GRH) { 2504 if (grh->sgid_index >= 2505 dev->mdev->port_caps[port - 1].gid_table_len) { 2506 pr_err("sgid_index (%u) too large. max is %d\n", 2507 grh->sgid_index, 2508 dev->mdev->port_caps[port - 1].gid_table_len); 2509 return -EINVAL; 2510 } 2511 } 2512 2513 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2514 if (!(ah_flags & IB_AH_GRH)) 2515 return -EINVAL; 2516 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2517 &gid_type); 2518 if (err) 2519 return err; 2520 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2521 if (qp->ibqp.qp_type == IB_QPT_RC || 2522 qp->ibqp.qp_type == IB_QPT_UC || 2523 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2524 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2525 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2526 grh->sgid_index); 2527 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2528 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2529 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2530 } else { 2531 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2532 path->fl_free_ar |= 2533 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2534 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2535 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2536 if (ah_flags & IB_AH_GRH) 2537 path->grh_mlid |= 1 << 7; 2538 path->dci_cfi_prio_sl = sl & 0xf; 2539 } 2540 2541 if (ah_flags & IB_AH_GRH) { 2542 path->mgid_index = grh->sgid_index; 2543 path->hop_limit = grh->hop_limit; 2544 path->tclass_flowlabel = 2545 cpu_to_be32((grh->traffic_class << 20) | 2546 (grh->flow_label)); 2547 memcpy(path->rgid, grh->dgid.raw, 16); 2548 } 2549 2550 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2551 if (err < 0) 2552 return err; 2553 path->static_rate = err; 2554 path->port = port; 2555 2556 if (attr_mask & IB_QP_TIMEOUT) 2557 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2558 2559 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2560 return modify_raw_packet_eth_prio(dev->mdev, 2561 &qp->raw_packet_qp.sq, 2562 sl & 0xf); 2563 2564 return 0; 2565 } 2566 2567 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2568 [MLX5_QP_STATE_INIT] = { 2569 [MLX5_QP_STATE_INIT] = { 2570 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2571 MLX5_QP_OPTPAR_RAE | 2572 MLX5_QP_OPTPAR_RWE | 2573 MLX5_QP_OPTPAR_PKEY_INDEX | 2574 MLX5_QP_OPTPAR_PRI_PORT, 2575 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2576 MLX5_QP_OPTPAR_PKEY_INDEX | 2577 MLX5_QP_OPTPAR_PRI_PORT, 2578 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2579 MLX5_QP_OPTPAR_Q_KEY | 2580 MLX5_QP_OPTPAR_PRI_PORT, 2581 }, 2582 [MLX5_QP_STATE_RTR] = { 2583 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2584 MLX5_QP_OPTPAR_RRE | 2585 MLX5_QP_OPTPAR_RAE | 2586 MLX5_QP_OPTPAR_RWE | 2587 MLX5_QP_OPTPAR_PKEY_INDEX, 2588 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2589 MLX5_QP_OPTPAR_RWE | 2590 MLX5_QP_OPTPAR_PKEY_INDEX, 2591 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2592 MLX5_QP_OPTPAR_Q_KEY, 2593 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2594 MLX5_QP_OPTPAR_Q_KEY, 2595 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2596 MLX5_QP_OPTPAR_RRE | 2597 MLX5_QP_OPTPAR_RAE | 2598 MLX5_QP_OPTPAR_RWE | 2599 MLX5_QP_OPTPAR_PKEY_INDEX, 2600 }, 2601 }, 2602 [MLX5_QP_STATE_RTR] = { 2603 [MLX5_QP_STATE_RTS] = { 2604 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2605 MLX5_QP_OPTPAR_RRE | 2606 MLX5_QP_OPTPAR_RAE | 2607 MLX5_QP_OPTPAR_RWE | 2608 MLX5_QP_OPTPAR_PM_STATE | 2609 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2610 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2611 MLX5_QP_OPTPAR_RWE | 2612 MLX5_QP_OPTPAR_PM_STATE, 2613 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2614 }, 2615 }, 2616 [MLX5_QP_STATE_RTS] = { 2617 [MLX5_QP_STATE_RTS] = { 2618 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2619 MLX5_QP_OPTPAR_RAE | 2620 MLX5_QP_OPTPAR_RWE | 2621 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2622 MLX5_QP_OPTPAR_PM_STATE | 2623 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2624 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2625 MLX5_QP_OPTPAR_PM_STATE | 2626 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2627 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2628 MLX5_QP_OPTPAR_SRQN | 2629 MLX5_QP_OPTPAR_CQN_RCV, 2630 }, 2631 }, 2632 [MLX5_QP_STATE_SQER] = { 2633 [MLX5_QP_STATE_RTS] = { 2634 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2635 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2636 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2637 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2638 MLX5_QP_OPTPAR_RWE | 2639 MLX5_QP_OPTPAR_RAE | 2640 MLX5_QP_OPTPAR_RRE, 2641 }, 2642 }, 2643 }; 2644 2645 static int ib_nr_to_mlx5_nr(int ib_mask) 2646 { 2647 switch (ib_mask) { 2648 case IB_QP_STATE: 2649 return 0; 2650 case IB_QP_CUR_STATE: 2651 return 0; 2652 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2653 return 0; 2654 case IB_QP_ACCESS_FLAGS: 2655 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2656 MLX5_QP_OPTPAR_RAE; 2657 case IB_QP_PKEY_INDEX: 2658 return MLX5_QP_OPTPAR_PKEY_INDEX; 2659 case IB_QP_PORT: 2660 return MLX5_QP_OPTPAR_PRI_PORT; 2661 case IB_QP_QKEY: 2662 return MLX5_QP_OPTPAR_Q_KEY; 2663 case IB_QP_AV: 2664 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2665 MLX5_QP_OPTPAR_PRI_PORT; 2666 case IB_QP_PATH_MTU: 2667 return 0; 2668 case IB_QP_TIMEOUT: 2669 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2670 case IB_QP_RETRY_CNT: 2671 return MLX5_QP_OPTPAR_RETRY_COUNT; 2672 case IB_QP_RNR_RETRY: 2673 return MLX5_QP_OPTPAR_RNR_RETRY; 2674 case IB_QP_RQ_PSN: 2675 return 0; 2676 case IB_QP_MAX_QP_RD_ATOMIC: 2677 return MLX5_QP_OPTPAR_SRA_MAX; 2678 case IB_QP_ALT_PATH: 2679 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2680 case IB_QP_MIN_RNR_TIMER: 2681 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2682 case IB_QP_SQ_PSN: 2683 return 0; 2684 case IB_QP_MAX_DEST_RD_ATOMIC: 2685 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2686 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2687 case IB_QP_PATH_MIG_STATE: 2688 return MLX5_QP_OPTPAR_PM_STATE; 2689 case IB_QP_CAP: 2690 return 0; 2691 case IB_QP_DEST_QPN: 2692 return 0; 2693 } 2694 return 0; 2695 } 2696 2697 static int ib_mask_to_mlx5_opt(int ib_mask) 2698 { 2699 int result = 0; 2700 int i; 2701 2702 for (i = 0; i < 8 * sizeof(int); i++) { 2703 if ((1 << i) & ib_mask) 2704 result |= ib_nr_to_mlx5_nr(1 << i); 2705 } 2706 2707 return result; 2708 } 2709 2710 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2711 struct mlx5_ib_rq *rq, int new_state, 2712 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2713 { 2714 void *in; 2715 void *rqc; 2716 int inlen; 2717 int err; 2718 2719 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2720 in = kvzalloc(inlen, GFP_KERNEL); 2721 if (!in) 2722 return -ENOMEM; 2723 2724 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2725 2726 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2727 MLX5_SET(rqc, rqc, state, new_state); 2728 2729 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2730 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2731 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2732 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2733 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2734 } else 2735 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2736 dev->ib_dev.name); 2737 } 2738 2739 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2740 if (err) 2741 goto out; 2742 2743 rq->state = new_state; 2744 2745 out: 2746 kvfree(in); 2747 return err; 2748 } 2749 2750 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2751 struct mlx5_ib_sq *sq, 2752 int new_state, 2753 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2754 { 2755 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2756 u32 old_rate = ibqp->rate_limit; 2757 u32 new_rate = old_rate; 2758 u16 rl_index = 0; 2759 void *in; 2760 void *sqc; 2761 int inlen; 2762 int err; 2763 2764 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2765 in = kvzalloc(inlen, GFP_KERNEL); 2766 if (!in) 2767 return -ENOMEM; 2768 2769 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2770 2771 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2772 MLX5_SET(sqc, sqc, state, new_state); 2773 2774 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2775 if (new_state != MLX5_SQC_STATE_RDY) 2776 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2777 __func__); 2778 else 2779 new_rate = raw_qp_param->rate_limit; 2780 } 2781 2782 if (old_rate != new_rate) { 2783 if (new_rate) { 2784 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2785 if (err) { 2786 pr_err("Failed configuring rate %u: %d\n", 2787 new_rate, err); 2788 goto out; 2789 } 2790 } 2791 2792 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2793 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2794 } 2795 2796 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2797 if (err) { 2798 /* Remove new rate from table if failed */ 2799 if (new_rate && 2800 old_rate != new_rate) 2801 mlx5_rl_remove_rate(dev, new_rate); 2802 goto out; 2803 } 2804 2805 /* Only remove the old rate after new rate was set */ 2806 if ((old_rate && 2807 (old_rate != new_rate)) || 2808 (new_state != MLX5_SQC_STATE_RDY)) 2809 mlx5_rl_remove_rate(dev, old_rate); 2810 2811 ibqp->rate_limit = new_rate; 2812 sq->state = new_state; 2813 2814 out: 2815 kvfree(in); 2816 return err; 2817 } 2818 2819 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2820 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2821 u8 tx_affinity) 2822 { 2823 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2824 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2825 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2826 int modify_rq = !!qp->rq.wqe_cnt; 2827 int modify_sq = !!qp->sq.wqe_cnt; 2828 int rq_state; 2829 int sq_state; 2830 int err; 2831 2832 switch (raw_qp_param->operation) { 2833 case MLX5_CMD_OP_RST2INIT_QP: 2834 rq_state = MLX5_RQC_STATE_RDY; 2835 sq_state = MLX5_SQC_STATE_RDY; 2836 break; 2837 case MLX5_CMD_OP_2ERR_QP: 2838 rq_state = MLX5_RQC_STATE_ERR; 2839 sq_state = MLX5_SQC_STATE_ERR; 2840 break; 2841 case MLX5_CMD_OP_2RST_QP: 2842 rq_state = MLX5_RQC_STATE_RST; 2843 sq_state = MLX5_SQC_STATE_RST; 2844 break; 2845 case MLX5_CMD_OP_RTR2RTS_QP: 2846 case MLX5_CMD_OP_RTS2RTS_QP: 2847 if (raw_qp_param->set_mask == 2848 MLX5_RAW_QP_RATE_LIMIT) { 2849 modify_rq = 0; 2850 sq_state = sq->state; 2851 } else { 2852 return raw_qp_param->set_mask ? -EINVAL : 0; 2853 } 2854 break; 2855 case MLX5_CMD_OP_INIT2INIT_QP: 2856 case MLX5_CMD_OP_INIT2RTR_QP: 2857 if (raw_qp_param->set_mask) 2858 return -EINVAL; 2859 else 2860 return 0; 2861 default: 2862 WARN_ON(1); 2863 return -EINVAL; 2864 } 2865 2866 if (modify_rq) { 2867 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2868 if (err) 2869 return err; 2870 } 2871 2872 if (modify_sq) { 2873 if (tx_affinity) { 2874 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2875 tx_affinity); 2876 if (err) 2877 return err; 2878 } 2879 2880 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2881 } 2882 2883 return 0; 2884 } 2885 2886 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2887 const struct ib_qp_attr *attr, int attr_mask, 2888 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2889 { 2890 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2891 [MLX5_QP_STATE_RST] = { 2892 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2893 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2894 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2895 }, 2896 [MLX5_QP_STATE_INIT] = { 2897 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2898 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2899 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2900 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2901 }, 2902 [MLX5_QP_STATE_RTR] = { 2903 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2904 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2905 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2906 }, 2907 [MLX5_QP_STATE_RTS] = { 2908 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2909 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2910 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2911 }, 2912 [MLX5_QP_STATE_SQD] = { 2913 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2914 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2915 }, 2916 [MLX5_QP_STATE_SQER] = { 2917 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2918 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2919 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2920 }, 2921 [MLX5_QP_STATE_ERR] = { 2922 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2923 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2924 } 2925 }; 2926 2927 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2928 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2929 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2930 struct mlx5_ib_cq *send_cq, *recv_cq; 2931 struct mlx5_qp_context *context; 2932 struct mlx5_ib_pd *pd; 2933 struct mlx5_ib_port *mibport = NULL; 2934 enum mlx5_qp_state mlx5_cur, mlx5_new; 2935 enum mlx5_qp_optpar optpar; 2936 int mlx5_st; 2937 int err; 2938 u16 op; 2939 u8 tx_affinity = 0; 2940 2941 context = kzalloc(sizeof(*context), GFP_KERNEL); 2942 if (!context) 2943 return -ENOMEM; 2944 2945 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 2946 qp->qp_sub_type : ibqp->qp_type); 2947 if (err < 0) { 2948 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2949 goto out; 2950 } 2951 2952 context->flags = cpu_to_be32(err << 16); 2953 2954 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2955 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2956 } else { 2957 switch (attr->path_mig_state) { 2958 case IB_MIG_MIGRATED: 2959 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2960 break; 2961 case IB_MIG_REARM: 2962 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2963 break; 2964 case IB_MIG_ARMED: 2965 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2966 break; 2967 } 2968 } 2969 2970 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2971 if ((ibqp->qp_type == IB_QPT_RC) || 2972 (ibqp->qp_type == IB_QPT_UD && 2973 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2974 (ibqp->qp_type == IB_QPT_UC) || 2975 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2976 (ibqp->qp_type == IB_QPT_XRC_INI) || 2977 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2978 if (mlx5_lag_is_active(dev->mdev)) { 2979 u8 p = mlx5_core_native_port_num(dev->mdev); 2980 tx_affinity = (unsigned int)atomic_add_return(1, 2981 &dev->roce[p].next_port) % 2982 MLX5_MAX_PORTS + 1; 2983 context->flags |= cpu_to_be32(tx_affinity << 24); 2984 } 2985 } 2986 } 2987 2988 if (is_sqp(ibqp->qp_type)) { 2989 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2990 } else if ((ibqp->qp_type == IB_QPT_UD && 2991 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 2992 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2993 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2994 } else if (attr_mask & IB_QP_PATH_MTU) { 2995 if (attr->path_mtu < IB_MTU_256 || 2996 attr->path_mtu > IB_MTU_4096) { 2997 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2998 err = -EINVAL; 2999 goto out; 3000 } 3001 context->mtu_msgmax = (attr->path_mtu << 5) | 3002 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3003 } 3004 3005 if (attr_mask & IB_QP_DEST_QPN) 3006 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3007 3008 if (attr_mask & IB_QP_PKEY_INDEX) 3009 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3010 3011 /* todo implement counter_index functionality */ 3012 3013 if (is_sqp(ibqp->qp_type)) 3014 context->pri_path.port = qp->port; 3015 3016 if (attr_mask & IB_QP_PORT) 3017 context->pri_path.port = attr->port_num; 3018 3019 if (attr_mask & IB_QP_AV) { 3020 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3021 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3022 attr_mask, 0, attr, false); 3023 if (err) 3024 goto out; 3025 } 3026 3027 if (attr_mask & IB_QP_TIMEOUT) 3028 context->pri_path.ackto_lt |= attr->timeout << 3; 3029 3030 if (attr_mask & IB_QP_ALT_PATH) { 3031 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3032 &context->alt_path, 3033 attr->alt_port_num, 3034 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3035 0, attr, true); 3036 if (err) 3037 goto out; 3038 } 3039 3040 pd = get_pd(qp); 3041 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3042 &send_cq, &recv_cq); 3043 3044 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3045 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3046 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3047 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3048 3049 if (attr_mask & IB_QP_RNR_RETRY) 3050 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3051 3052 if (attr_mask & IB_QP_RETRY_CNT) 3053 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3054 3055 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3056 if (attr->max_rd_atomic) 3057 context->params1 |= 3058 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3059 } 3060 3061 if (attr_mask & IB_QP_SQ_PSN) 3062 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3063 3064 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3065 if (attr->max_dest_rd_atomic) 3066 context->params2 |= 3067 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3068 } 3069 3070 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3071 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 3072 3073 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3074 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3075 3076 if (attr_mask & IB_QP_RQ_PSN) 3077 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3078 3079 if (attr_mask & IB_QP_QKEY) 3080 context->qkey = cpu_to_be32(attr->qkey); 3081 3082 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3083 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3084 3085 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3086 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3087 qp->port) - 1; 3088 3089 /* Underlay port should be used - index 0 function per port */ 3090 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3091 port_num = 0; 3092 3093 mibport = &dev->port[port_num]; 3094 context->qp_counter_set_usr_page |= 3095 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3096 } 3097 3098 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3099 context->sq_crq_size |= cpu_to_be16(1 << 4); 3100 3101 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3102 context->deth_sqpn = cpu_to_be32(1); 3103 3104 mlx5_cur = to_mlx5_state(cur_state); 3105 mlx5_new = to_mlx5_state(new_state); 3106 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3107 qp->qp_sub_type : ibqp->qp_type); 3108 if (mlx5_st < 0) 3109 goto out; 3110 3111 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3112 !optab[mlx5_cur][mlx5_new]) { 3113 err = -EINVAL; 3114 goto out; 3115 } 3116 3117 op = optab[mlx5_cur][mlx5_new]; 3118 optpar = ib_mask_to_mlx5_opt(attr_mask); 3119 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3120 3121 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3122 qp->flags & MLX5_IB_QP_UNDERLAY) { 3123 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3124 3125 raw_qp_param.operation = op; 3126 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3127 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3128 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3129 } 3130 3131 if (attr_mask & IB_QP_RATE_LIMIT) { 3132 raw_qp_param.rate_limit = attr->rate_limit; 3133 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3134 } 3135 3136 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3137 } else { 3138 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3139 &base->mqp); 3140 } 3141 3142 if (err) 3143 goto out; 3144 3145 qp->state = new_state; 3146 3147 if (attr_mask & IB_QP_ACCESS_FLAGS) 3148 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3149 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3150 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3151 if (attr_mask & IB_QP_PORT) 3152 qp->port = attr->port_num; 3153 if (attr_mask & IB_QP_ALT_PATH) 3154 qp->trans_qp.alt_port = attr->alt_port_num; 3155 3156 /* 3157 * If we moved a kernel QP to RESET, clean up all old CQ 3158 * entries and reinitialize the QP. 3159 */ 3160 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3161 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3162 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3163 if (send_cq != recv_cq) 3164 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3165 3166 qp->rq.head = 0; 3167 qp->rq.tail = 0; 3168 qp->sq.head = 0; 3169 qp->sq.tail = 0; 3170 qp->sq.cur_post = 0; 3171 qp->sq.last_poll = 0; 3172 qp->db.db[MLX5_RCV_DBR] = 0; 3173 qp->db.db[MLX5_SND_DBR] = 0; 3174 } 3175 3176 out: 3177 kfree(context); 3178 return err; 3179 } 3180 3181 static inline bool is_valid_mask(int mask, int req, int opt) 3182 { 3183 if ((mask & req) != req) 3184 return false; 3185 3186 if (mask & ~(req | opt)) 3187 return false; 3188 3189 return true; 3190 } 3191 3192 /* check valid transition for driver QP types 3193 * for now the only QP type that this function supports is DCI 3194 */ 3195 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3196 enum ib_qp_attr_mask attr_mask) 3197 { 3198 int req = IB_QP_STATE; 3199 int opt = 0; 3200 3201 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3202 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3203 return is_valid_mask(attr_mask, req, opt); 3204 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3205 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3206 return is_valid_mask(attr_mask, req, opt); 3207 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3208 req |= IB_QP_PATH_MTU; 3209 opt = IB_QP_PKEY_INDEX; 3210 return is_valid_mask(attr_mask, req, opt); 3211 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3212 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3213 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3214 opt = IB_QP_MIN_RNR_TIMER; 3215 return is_valid_mask(attr_mask, req, opt); 3216 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3217 opt = IB_QP_MIN_RNR_TIMER; 3218 return is_valid_mask(attr_mask, req, opt); 3219 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3220 return is_valid_mask(attr_mask, req, opt); 3221 } 3222 return false; 3223 } 3224 3225 /* mlx5_ib_modify_dct: modify a DCT QP 3226 * valid transitions are: 3227 * RESET to INIT: must set access_flags, pkey_index and port 3228 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3229 * mtu, gid_index and hop_limit 3230 * Other transitions and attributes are illegal 3231 */ 3232 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3233 int attr_mask, struct ib_udata *udata) 3234 { 3235 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3236 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3237 enum ib_qp_state cur_state, new_state; 3238 int err = 0; 3239 int required = IB_QP_STATE; 3240 void *dctc; 3241 3242 if (!(attr_mask & IB_QP_STATE)) 3243 return -EINVAL; 3244 3245 cur_state = qp->state; 3246 new_state = attr->qp_state; 3247 3248 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3249 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3250 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3251 if (!is_valid_mask(attr_mask, required, 0)) 3252 return -EINVAL; 3253 3254 if (attr->port_num == 0 || 3255 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3256 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3257 attr->port_num, dev->num_ports); 3258 return -EINVAL; 3259 } 3260 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3261 MLX5_SET(dctc, dctc, rre, 1); 3262 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3263 MLX5_SET(dctc, dctc, rwe, 1); 3264 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3265 if (!mlx5_ib_dc_atomic_is_supported(dev)) 3266 return -EOPNOTSUPP; 3267 MLX5_SET(dctc, dctc, rae, 1); 3268 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); 3269 } 3270 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3271 MLX5_SET(dctc, dctc, port, attr->port_num); 3272 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3273 3274 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3275 struct mlx5_ib_modify_qp_resp resp = {}; 3276 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3277 sizeof(resp.dctn); 3278 3279 if (udata->outlen < min_resp_len) 3280 return -EINVAL; 3281 resp.response_length = min_resp_len; 3282 3283 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3284 if (!is_valid_mask(attr_mask, required, 0)) 3285 return -EINVAL; 3286 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3287 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3288 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3289 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3290 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3291 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3292 3293 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3294 MLX5_ST_SZ_BYTES(create_dct_in)); 3295 if (err) 3296 return err; 3297 resp.dctn = qp->dct.mdct.mqp.qpn; 3298 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3299 if (err) { 3300 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3301 return err; 3302 } 3303 } else { 3304 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3305 return -EINVAL; 3306 } 3307 if (err) 3308 qp->state = IB_QPS_ERR; 3309 else 3310 qp->state = new_state; 3311 return err; 3312 } 3313 3314 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3315 int attr_mask, struct ib_udata *udata) 3316 { 3317 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3318 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3319 enum ib_qp_type qp_type; 3320 enum ib_qp_state cur_state, new_state; 3321 int err = -EINVAL; 3322 int port; 3323 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3324 3325 if (ibqp->rwq_ind_tbl) 3326 return -ENOSYS; 3327 3328 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3329 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3330 3331 if (ibqp->qp_type == IB_QPT_DRIVER) 3332 qp_type = qp->qp_sub_type; 3333 else 3334 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3335 IB_QPT_GSI : ibqp->qp_type; 3336 3337 if (qp_type == MLX5_IB_QPT_DCT) 3338 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3339 3340 mutex_lock(&qp->mutex); 3341 3342 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3343 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3344 3345 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3346 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3347 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3348 } 3349 3350 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3351 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3352 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3353 attr_mask); 3354 goto out; 3355 } 3356 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3357 qp_type != MLX5_IB_QPT_DCI && 3358 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3359 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3360 cur_state, new_state, ibqp->qp_type, attr_mask); 3361 goto out; 3362 } else if (qp_type == MLX5_IB_QPT_DCI && 3363 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3364 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3365 cur_state, new_state, qp_type, attr_mask); 3366 goto out; 3367 } 3368 3369 if ((attr_mask & IB_QP_PORT) && 3370 (attr->port_num == 0 || 3371 attr->port_num > dev->num_ports)) { 3372 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3373 attr->port_num, dev->num_ports); 3374 goto out; 3375 } 3376 3377 if (attr_mask & IB_QP_PKEY_INDEX) { 3378 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3379 if (attr->pkey_index >= 3380 dev->mdev->port_caps[port - 1].pkey_table_len) { 3381 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3382 attr->pkey_index); 3383 goto out; 3384 } 3385 } 3386 3387 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3388 attr->max_rd_atomic > 3389 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3390 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3391 attr->max_rd_atomic); 3392 goto out; 3393 } 3394 3395 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3396 attr->max_dest_rd_atomic > 3397 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3398 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3399 attr->max_dest_rd_atomic); 3400 goto out; 3401 } 3402 3403 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3404 err = 0; 3405 goto out; 3406 } 3407 3408 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3409 3410 out: 3411 mutex_unlock(&qp->mutex); 3412 return err; 3413 } 3414 3415 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3416 { 3417 struct mlx5_ib_cq *cq; 3418 unsigned cur; 3419 3420 cur = wq->head - wq->tail; 3421 if (likely(cur + nreq < wq->max_post)) 3422 return 0; 3423 3424 cq = to_mcq(ib_cq); 3425 spin_lock(&cq->lock); 3426 cur = wq->head - wq->tail; 3427 spin_unlock(&cq->lock); 3428 3429 return cur + nreq >= wq->max_post; 3430 } 3431 3432 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3433 u64 remote_addr, u32 rkey) 3434 { 3435 rseg->raddr = cpu_to_be64(remote_addr); 3436 rseg->rkey = cpu_to_be32(rkey); 3437 rseg->reserved = 0; 3438 } 3439 3440 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3441 struct ib_send_wr *wr, void *qend, 3442 struct mlx5_ib_qp *qp, int *size) 3443 { 3444 void *seg = eseg; 3445 3446 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3447 3448 if (wr->send_flags & IB_SEND_IP_CSUM) 3449 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3450 MLX5_ETH_WQE_L4_CSUM; 3451 3452 seg += sizeof(struct mlx5_wqe_eth_seg); 3453 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3454 3455 if (wr->opcode == IB_WR_LSO) { 3456 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3457 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3458 u64 left, leftlen, copysz; 3459 void *pdata = ud_wr->header; 3460 3461 left = ud_wr->hlen; 3462 eseg->mss = cpu_to_be16(ud_wr->mss); 3463 eseg->inline_hdr.sz = cpu_to_be16(left); 3464 3465 /* 3466 * check if there is space till the end of queue, if yes, 3467 * copy all in one shot, otherwise copy till the end of queue, 3468 * rollback and than the copy the left 3469 */ 3470 leftlen = qend - (void *)eseg->inline_hdr.start; 3471 copysz = min_t(u64, leftlen, left); 3472 3473 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3474 3475 if (likely(copysz > size_of_inl_hdr_start)) { 3476 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3477 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3478 } 3479 3480 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3481 seg = mlx5_get_send_wqe(qp, 0); 3482 left -= copysz; 3483 pdata += copysz; 3484 memcpy(seg, pdata, left); 3485 seg += ALIGN(left, 16); 3486 *size += ALIGN(left, 16) / 16; 3487 } 3488 } 3489 3490 return seg; 3491 } 3492 3493 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3494 struct ib_send_wr *wr) 3495 { 3496 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3497 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3498 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3499 } 3500 3501 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3502 { 3503 dseg->byte_count = cpu_to_be32(sg->length); 3504 dseg->lkey = cpu_to_be32(sg->lkey); 3505 dseg->addr = cpu_to_be64(sg->addr); 3506 } 3507 3508 static u64 get_xlt_octo(u64 bytes) 3509 { 3510 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3511 MLX5_IB_UMR_OCTOWORD; 3512 } 3513 3514 static __be64 frwr_mkey_mask(void) 3515 { 3516 u64 result; 3517 3518 result = MLX5_MKEY_MASK_LEN | 3519 MLX5_MKEY_MASK_PAGE_SIZE | 3520 MLX5_MKEY_MASK_START_ADDR | 3521 MLX5_MKEY_MASK_EN_RINVAL | 3522 MLX5_MKEY_MASK_KEY | 3523 MLX5_MKEY_MASK_LR | 3524 MLX5_MKEY_MASK_LW | 3525 MLX5_MKEY_MASK_RR | 3526 MLX5_MKEY_MASK_RW | 3527 MLX5_MKEY_MASK_A | 3528 MLX5_MKEY_MASK_SMALL_FENCE | 3529 MLX5_MKEY_MASK_FREE; 3530 3531 return cpu_to_be64(result); 3532 } 3533 3534 static __be64 sig_mkey_mask(void) 3535 { 3536 u64 result; 3537 3538 result = MLX5_MKEY_MASK_LEN | 3539 MLX5_MKEY_MASK_PAGE_SIZE | 3540 MLX5_MKEY_MASK_START_ADDR | 3541 MLX5_MKEY_MASK_EN_SIGERR | 3542 MLX5_MKEY_MASK_EN_RINVAL | 3543 MLX5_MKEY_MASK_KEY | 3544 MLX5_MKEY_MASK_LR | 3545 MLX5_MKEY_MASK_LW | 3546 MLX5_MKEY_MASK_RR | 3547 MLX5_MKEY_MASK_RW | 3548 MLX5_MKEY_MASK_SMALL_FENCE | 3549 MLX5_MKEY_MASK_FREE | 3550 MLX5_MKEY_MASK_BSF_EN; 3551 3552 return cpu_to_be64(result); 3553 } 3554 3555 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3556 struct mlx5_ib_mr *mr) 3557 { 3558 int size = mr->ndescs * mr->desc_size; 3559 3560 memset(umr, 0, sizeof(*umr)); 3561 3562 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3563 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3564 umr->mkey_mask = frwr_mkey_mask(); 3565 } 3566 3567 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3568 { 3569 memset(umr, 0, sizeof(*umr)); 3570 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3571 umr->flags = MLX5_UMR_INLINE; 3572 } 3573 3574 static __be64 get_umr_enable_mr_mask(void) 3575 { 3576 u64 result; 3577 3578 result = MLX5_MKEY_MASK_KEY | 3579 MLX5_MKEY_MASK_FREE; 3580 3581 return cpu_to_be64(result); 3582 } 3583 3584 static __be64 get_umr_disable_mr_mask(void) 3585 { 3586 u64 result; 3587 3588 result = MLX5_MKEY_MASK_FREE; 3589 3590 return cpu_to_be64(result); 3591 } 3592 3593 static __be64 get_umr_update_translation_mask(void) 3594 { 3595 u64 result; 3596 3597 result = MLX5_MKEY_MASK_LEN | 3598 MLX5_MKEY_MASK_PAGE_SIZE | 3599 MLX5_MKEY_MASK_START_ADDR; 3600 3601 return cpu_to_be64(result); 3602 } 3603 3604 static __be64 get_umr_update_access_mask(int atomic) 3605 { 3606 u64 result; 3607 3608 result = MLX5_MKEY_MASK_LR | 3609 MLX5_MKEY_MASK_LW | 3610 MLX5_MKEY_MASK_RR | 3611 MLX5_MKEY_MASK_RW; 3612 3613 if (atomic) 3614 result |= MLX5_MKEY_MASK_A; 3615 3616 return cpu_to_be64(result); 3617 } 3618 3619 static __be64 get_umr_update_pd_mask(void) 3620 { 3621 u64 result; 3622 3623 result = MLX5_MKEY_MASK_PD; 3624 3625 return cpu_to_be64(result); 3626 } 3627 3628 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3629 struct ib_send_wr *wr, int atomic) 3630 { 3631 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3632 3633 memset(umr, 0, sizeof(*umr)); 3634 3635 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3636 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3637 else 3638 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3639 3640 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3641 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3642 u64 offset = get_xlt_octo(umrwr->offset); 3643 3644 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3645 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3646 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3647 } 3648 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3649 umr->mkey_mask |= get_umr_update_translation_mask(); 3650 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3651 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3652 umr->mkey_mask |= get_umr_update_pd_mask(); 3653 } 3654 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3655 umr->mkey_mask |= get_umr_enable_mr_mask(); 3656 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3657 umr->mkey_mask |= get_umr_disable_mr_mask(); 3658 3659 if (!wr->num_sge) 3660 umr->flags |= MLX5_UMR_INLINE; 3661 } 3662 3663 static u8 get_umr_flags(int acc) 3664 { 3665 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3666 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3667 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3668 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3669 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3670 } 3671 3672 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3673 struct mlx5_ib_mr *mr, 3674 u32 key, int access) 3675 { 3676 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3677 3678 memset(seg, 0, sizeof(*seg)); 3679 3680 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3681 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3682 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3683 /* KLMs take twice the size of MTTs */ 3684 ndescs *= 2; 3685 3686 seg->flags = get_umr_flags(access) | mr->access_mode; 3687 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3688 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3689 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3690 seg->len = cpu_to_be64(mr->ibmr.length); 3691 seg->xlt_oct_size = cpu_to_be32(ndescs); 3692 } 3693 3694 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3695 { 3696 memset(seg, 0, sizeof(*seg)); 3697 seg->status = MLX5_MKEY_STATUS_FREE; 3698 } 3699 3700 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3701 { 3702 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3703 3704 memset(seg, 0, sizeof(*seg)); 3705 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3706 seg->status = MLX5_MKEY_STATUS_FREE; 3707 3708 seg->flags = convert_access(umrwr->access_flags); 3709 if (umrwr->pd) 3710 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3711 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3712 !umrwr->length) 3713 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3714 3715 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3716 seg->len = cpu_to_be64(umrwr->length); 3717 seg->log2_page_size = umrwr->page_shift; 3718 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3719 mlx5_mkey_variant(umrwr->mkey)); 3720 } 3721 3722 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3723 struct mlx5_ib_mr *mr, 3724 struct mlx5_ib_pd *pd) 3725 { 3726 int bcount = mr->desc_size * mr->ndescs; 3727 3728 dseg->addr = cpu_to_be64(mr->desc_map); 3729 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3730 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3731 } 3732 3733 static __be32 send_ieth(struct ib_send_wr *wr) 3734 { 3735 switch (wr->opcode) { 3736 case IB_WR_SEND_WITH_IMM: 3737 case IB_WR_RDMA_WRITE_WITH_IMM: 3738 return wr->ex.imm_data; 3739 3740 case IB_WR_SEND_WITH_INV: 3741 return cpu_to_be32(wr->ex.invalidate_rkey); 3742 3743 default: 3744 return 0; 3745 } 3746 } 3747 3748 static u8 calc_sig(void *wqe, int size) 3749 { 3750 u8 *p = wqe; 3751 u8 res = 0; 3752 int i; 3753 3754 for (i = 0; i < size; i++) 3755 res ^= p[i]; 3756 3757 return ~res; 3758 } 3759 3760 static u8 wq_sig(void *wqe) 3761 { 3762 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3763 } 3764 3765 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3766 void *wqe, int *sz) 3767 { 3768 struct mlx5_wqe_inline_seg *seg; 3769 void *qend = qp->sq.qend; 3770 void *addr; 3771 int inl = 0; 3772 int copy; 3773 int len; 3774 int i; 3775 3776 seg = wqe; 3777 wqe += sizeof(*seg); 3778 for (i = 0; i < wr->num_sge; i++) { 3779 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3780 len = wr->sg_list[i].length; 3781 inl += len; 3782 3783 if (unlikely(inl > qp->max_inline_data)) 3784 return -ENOMEM; 3785 3786 if (unlikely(wqe + len > qend)) { 3787 copy = qend - wqe; 3788 memcpy(wqe, addr, copy); 3789 addr += copy; 3790 len -= copy; 3791 wqe = mlx5_get_send_wqe(qp, 0); 3792 } 3793 memcpy(wqe, addr, len); 3794 wqe += len; 3795 } 3796 3797 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3798 3799 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3800 3801 return 0; 3802 } 3803 3804 static u16 prot_field_size(enum ib_signature_type type) 3805 { 3806 switch (type) { 3807 case IB_SIG_TYPE_T10_DIF: 3808 return MLX5_DIF_SIZE; 3809 default: 3810 return 0; 3811 } 3812 } 3813 3814 static u8 bs_selector(int block_size) 3815 { 3816 switch (block_size) { 3817 case 512: return 0x1; 3818 case 520: return 0x2; 3819 case 4096: return 0x3; 3820 case 4160: return 0x4; 3821 case 1073741824: return 0x5; 3822 default: return 0; 3823 } 3824 } 3825 3826 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3827 struct mlx5_bsf_inl *inl) 3828 { 3829 /* Valid inline section and allow BSF refresh */ 3830 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3831 MLX5_BSF_REFRESH_DIF); 3832 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3833 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3834 /* repeating block */ 3835 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3836 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3837 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3838 3839 if (domain->sig.dif.ref_remap) 3840 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3841 3842 if (domain->sig.dif.app_escape) { 3843 if (domain->sig.dif.ref_escape) 3844 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3845 else 3846 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3847 } 3848 3849 inl->dif_app_bitmask_check = 3850 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3851 } 3852 3853 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3854 struct ib_sig_attrs *sig_attrs, 3855 struct mlx5_bsf *bsf, u32 data_size) 3856 { 3857 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3858 struct mlx5_bsf_basic *basic = &bsf->basic; 3859 struct ib_sig_domain *mem = &sig_attrs->mem; 3860 struct ib_sig_domain *wire = &sig_attrs->wire; 3861 3862 memset(bsf, 0, sizeof(*bsf)); 3863 3864 /* Basic + Extended + Inline */ 3865 basic->bsf_size_sbs = 1 << 7; 3866 /* Input domain check byte mask */ 3867 basic->check_byte_mask = sig_attrs->check_mask; 3868 basic->raw_data_size = cpu_to_be32(data_size); 3869 3870 /* Memory domain */ 3871 switch (sig_attrs->mem.sig_type) { 3872 case IB_SIG_TYPE_NONE: 3873 break; 3874 case IB_SIG_TYPE_T10_DIF: 3875 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3876 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3877 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3878 break; 3879 default: 3880 return -EINVAL; 3881 } 3882 3883 /* Wire domain */ 3884 switch (sig_attrs->wire.sig_type) { 3885 case IB_SIG_TYPE_NONE: 3886 break; 3887 case IB_SIG_TYPE_T10_DIF: 3888 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3889 mem->sig_type == wire->sig_type) { 3890 /* Same block structure */ 3891 basic->bsf_size_sbs |= 1 << 4; 3892 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3893 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3894 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3895 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3896 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3897 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3898 } else 3899 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3900 3901 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3902 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3903 break; 3904 default: 3905 return -EINVAL; 3906 } 3907 3908 return 0; 3909 } 3910 3911 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3912 struct mlx5_ib_qp *qp, void **seg, int *size) 3913 { 3914 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3915 struct ib_mr *sig_mr = wr->sig_mr; 3916 struct mlx5_bsf *bsf; 3917 u32 data_len = wr->wr.sg_list->length; 3918 u32 data_key = wr->wr.sg_list->lkey; 3919 u64 data_va = wr->wr.sg_list->addr; 3920 int ret; 3921 int wqe_size; 3922 3923 if (!wr->prot || 3924 (data_key == wr->prot->lkey && 3925 data_va == wr->prot->addr && 3926 data_len == wr->prot->length)) { 3927 /** 3928 * Source domain doesn't contain signature information 3929 * or data and protection are interleaved in memory. 3930 * So need construct: 3931 * ------------------ 3932 * | data_klm | 3933 * ------------------ 3934 * | BSF | 3935 * ------------------ 3936 **/ 3937 struct mlx5_klm *data_klm = *seg; 3938 3939 data_klm->bcount = cpu_to_be32(data_len); 3940 data_klm->key = cpu_to_be32(data_key); 3941 data_klm->va = cpu_to_be64(data_va); 3942 wqe_size = ALIGN(sizeof(*data_klm), 64); 3943 } else { 3944 /** 3945 * Source domain contains signature information 3946 * So need construct a strided block format: 3947 * --------------------------- 3948 * | stride_block_ctrl | 3949 * --------------------------- 3950 * | data_klm | 3951 * --------------------------- 3952 * | prot_klm | 3953 * --------------------------- 3954 * | BSF | 3955 * --------------------------- 3956 **/ 3957 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3958 struct mlx5_stride_block_entry *data_sentry; 3959 struct mlx5_stride_block_entry *prot_sentry; 3960 u32 prot_key = wr->prot->lkey; 3961 u64 prot_va = wr->prot->addr; 3962 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3963 int prot_size; 3964 3965 sblock_ctrl = *seg; 3966 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3967 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3968 3969 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3970 if (!prot_size) { 3971 pr_err("Bad block size given: %u\n", block_size); 3972 return -EINVAL; 3973 } 3974 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3975 prot_size); 3976 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3977 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3978 sblock_ctrl->num_entries = cpu_to_be16(2); 3979 3980 data_sentry->bcount = cpu_to_be16(block_size); 3981 data_sentry->key = cpu_to_be32(data_key); 3982 data_sentry->va = cpu_to_be64(data_va); 3983 data_sentry->stride = cpu_to_be16(block_size); 3984 3985 prot_sentry->bcount = cpu_to_be16(prot_size); 3986 prot_sentry->key = cpu_to_be32(prot_key); 3987 prot_sentry->va = cpu_to_be64(prot_va); 3988 prot_sentry->stride = cpu_to_be16(prot_size); 3989 3990 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3991 sizeof(*prot_sentry), 64); 3992 } 3993 3994 *seg += wqe_size; 3995 *size += wqe_size / 16; 3996 if (unlikely((*seg == qp->sq.qend))) 3997 *seg = mlx5_get_send_wqe(qp, 0); 3998 3999 bsf = *seg; 4000 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4001 if (ret) 4002 return -EINVAL; 4003 4004 *seg += sizeof(*bsf); 4005 *size += sizeof(*bsf) / 16; 4006 if (unlikely((*seg == qp->sq.qend))) 4007 *seg = mlx5_get_send_wqe(qp, 0); 4008 4009 return 0; 4010 } 4011 4012 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4013 struct ib_sig_handover_wr *wr, u32 size, 4014 u32 length, u32 pdn) 4015 { 4016 struct ib_mr *sig_mr = wr->sig_mr; 4017 u32 sig_key = sig_mr->rkey; 4018 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4019 4020 memset(seg, 0, sizeof(*seg)); 4021 4022 seg->flags = get_umr_flags(wr->access_flags) | 4023 MLX5_MKC_ACCESS_MODE_KLMS; 4024 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4025 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4026 MLX5_MKEY_BSF_EN | pdn); 4027 seg->len = cpu_to_be64(length); 4028 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4029 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4030 } 4031 4032 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4033 u32 size) 4034 { 4035 memset(umr, 0, sizeof(*umr)); 4036 4037 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4038 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4039 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4040 umr->mkey_mask = sig_mkey_mask(); 4041 } 4042 4043 4044 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 4045 void **seg, int *size) 4046 { 4047 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4048 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4049 u32 pdn = get_pd(qp)->pdn; 4050 u32 xlt_size; 4051 int region_len, ret; 4052 4053 if (unlikely(wr->wr.num_sge != 1) || 4054 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4055 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4056 unlikely(!sig_mr->sig->sig_status_checked)) 4057 return -EINVAL; 4058 4059 /* length of the protected region, data + protection */ 4060 region_len = wr->wr.sg_list->length; 4061 if (wr->prot && 4062 (wr->prot->lkey != wr->wr.sg_list->lkey || 4063 wr->prot->addr != wr->wr.sg_list->addr || 4064 wr->prot->length != wr->wr.sg_list->length)) 4065 region_len += wr->prot->length; 4066 4067 /** 4068 * KLM octoword size - if protection was provided 4069 * then we use strided block format (3 octowords), 4070 * else we use single KLM (1 octoword) 4071 **/ 4072 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4073 4074 set_sig_umr_segment(*seg, xlt_size); 4075 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4076 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4077 if (unlikely((*seg == qp->sq.qend))) 4078 *seg = mlx5_get_send_wqe(qp, 0); 4079 4080 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4081 *seg += sizeof(struct mlx5_mkey_seg); 4082 *size += sizeof(struct mlx5_mkey_seg) / 16; 4083 if (unlikely((*seg == qp->sq.qend))) 4084 *seg = mlx5_get_send_wqe(qp, 0); 4085 4086 ret = set_sig_data_segment(wr, qp, seg, size); 4087 if (ret) 4088 return ret; 4089 4090 sig_mr->sig->sig_status_checked = false; 4091 return 0; 4092 } 4093 4094 static int set_psv_wr(struct ib_sig_domain *domain, 4095 u32 psv_idx, void **seg, int *size) 4096 { 4097 struct mlx5_seg_set_psv *psv_seg = *seg; 4098 4099 memset(psv_seg, 0, sizeof(*psv_seg)); 4100 psv_seg->psv_num = cpu_to_be32(psv_idx); 4101 switch (domain->sig_type) { 4102 case IB_SIG_TYPE_NONE: 4103 break; 4104 case IB_SIG_TYPE_T10_DIF: 4105 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4106 domain->sig.dif.app_tag); 4107 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4108 break; 4109 default: 4110 pr_err("Bad signature type (%d) is given.\n", 4111 domain->sig_type); 4112 return -EINVAL; 4113 } 4114 4115 *seg += sizeof(*psv_seg); 4116 *size += sizeof(*psv_seg) / 16; 4117 4118 return 0; 4119 } 4120 4121 static int set_reg_wr(struct mlx5_ib_qp *qp, 4122 struct ib_reg_wr *wr, 4123 void **seg, int *size) 4124 { 4125 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4126 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4127 4128 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4129 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4130 "Invalid IB_SEND_INLINE send flag\n"); 4131 return -EINVAL; 4132 } 4133 4134 set_reg_umr_seg(*seg, mr); 4135 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4136 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4137 if (unlikely((*seg == qp->sq.qend))) 4138 *seg = mlx5_get_send_wqe(qp, 0); 4139 4140 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4141 *seg += sizeof(struct mlx5_mkey_seg); 4142 *size += sizeof(struct mlx5_mkey_seg) / 16; 4143 if (unlikely((*seg == qp->sq.qend))) 4144 *seg = mlx5_get_send_wqe(qp, 0); 4145 4146 set_reg_data_seg(*seg, mr, pd); 4147 *seg += sizeof(struct mlx5_wqe_data_seg); 4148 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4149 4150 return 0; 4151 } 4152 4153 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 4154 { 4155 set_linv_umr_seg(*seg); 4156 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4157 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4158 if (unlikely((*seg == qp->sq.qend))) 4159 *seg = mlx5_get_send_wqe(qp, 0); 4160 set_linv_mkey_seg(*seg); 4161 *seg += sizeof(struct mlx5_mkey_seg); 4162 *size += sizeof(struct mlx5_mkey_seg) / 16; 4163 if (unlikely((*seg == qp->sq.qend))) 4164 *seg = mlx5_get_send_wqe(qp, 0); 4165 } 4166 4167 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 4168 { 4169 __be32 *p = NULL; 4170 int tidx = idx; 4171 int i, j; 4172 4173 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 4174 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4175 if ((i & 0xf) == 0) { 4176 void *buf = mlx5_get_send_wqe(qp, tidx); 4177 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4178 p = buf; 4179 j = 0; 4180 } 4181 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4182 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4183 be32_to_cpu(p[j + 3])); 4184 } 4185 } 4186 4187 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4188 struct mlx5_wqe_ctrl_seg **ctrl, 4189 struct ib_send_wr *wr, unsigned *idx, 4190 int *size, int nreq) 4191 { 4192 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4193 return -ENOMEM; 4194 4195 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4196 *seg = mlx5_get_send_wqe(qp, *idx); 4197 *ctrl = *seg; 4198 *(uint32_t *)(*seg + 8) = 0; 4199 (*ctrl)->imm = send_ieth(wr); 4200 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4201 (wr->send_flags & IB_SEND_SIGNALED ? 4202 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4203 (wr->send_flags & IB_SEND_SOLICITED ? 4204 MLX5_WQE_CTRL_SOLICITED : 0); 4205 4206 *seg += sizeof(**ctrl); 4207 *size = sizeof(**ctrl) / 16; 4208 4209 return 0; 4210 } 4211 4212 static void finish_wqe(struct mlx5_ib_qp *qp, 4213 struct mlx5_wqe_ctrl_seg *ctrl, 4214 u8 size, unsigned idx, u64 wr_id, 4215 int nreq, u8 fence, u32 mlx5_opcode) 4216 { 4217 u8 opmod = 0; 4218 4219 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4220 mlx5_opcode | ((u32)opmod << 24)); 4221 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4222 ctrl->fm_ce_se |= fence; 4223 if (unlikely(qp->wq_sig)) 4224 ctrl->signature = wq_sig(ctrl); 4225 4226 qp->sq.wrid[idx] = wr_id; 4227 qp->sq.w_list[idx].opcode = mlx5_opcode; 4228 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4229 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4230 qp->sq.w_list[idx].next = qp->sq.cur_post; 4231 } 4232 4233 4234 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 4235 struct ib_send_wr **bad_wr) 4236 { 4237 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4238 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4239 struct mlx5_core_dev *mdev = dev->mdev; 4240 struct mlx5_ib_qp *qp; 4241 struct mlx5_ib_mr *mr; 4242 struct mlx5_wqe_data_seg *dpseg; 4243 struct mlx5_wqe_xrc_seg *xrc; 4244 struct mlx5_bf *bf; 4245 int uninitialized_var(size); 4246 void *qend; 4247 unsigned long flags; 4248 unsigned idx; 4249 int err = 0; 4250 int num_sge; 4251 void *seg; 4252 int nreq; 4253 int i; 4254 u8 next_fence = 0; 4255 u8 fence; 4256 4257 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4258 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4259 4260 qp = to_mqp(ibqp); 4261 bf = &qp->bf; 4262 qend = qp->sq.qend; 4263 4264 spin_lock_irqsave(&qp->sq.lock, flags); 4265 4266 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4267 err = -EIO; 4268 *bad_wr = wr; 4269 nreq = 0; 4270 goto out; 4271 } 4272 4273 for (nreq = 0; wr; nreq++, wr = wr->next) { 4274 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4275 mlx5_ib_warn(dev, "\n"); 4276 err = -EINVAL; 4277 *bad_wr = wr; 4278 goto out; 4279 } 4280 4281 num_sge = wr->num_sge; 4282 if (unlikely(num_sge > qp->sq.max_gs)) { 4283 mlx5_ib_warn(dev, "\n"); 4284 err = -EINVAL; 4285 *bad_wr = wr; 4286 goto out; 4287 } 4288 4289 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 4290 if (err) { 4291 mlx5_ib_warn(dev, "\n"); 4292 err = -ENOMEM; 4293 *bad_wr = wr; 4294 goto out; 4295 } 4296 4297 if (wr->opcode == IB_WR_LOCAL_INV || 4298 wr->opcode == IB_WR_REG_MR) { 4299 fence = dev->umr_fence; 4300 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4301 } else if (wr->send_flags & IB_SEND_FENCE) { 4302 if (qp->next_fence) 4303 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4304 else 4305 fence = MLX5_FENCE_MODE_FENCE; 4306 } else { 4307 fence = qp->next_fence; 4308 } 4309 4310 switch (ibqp->qp_type) { 4311 case IB_QPT_XRC_INI: 4312 xrc = seg; 4313 seg += sizeof(*xrc); 4314 size += sizeof(*xrc) / 16; 4315 /* fall through */ 4316 case IB_QPT_RC: 4317 switch (wr->opcode) { 4318 case IB_WR_RDMA_READ: 4319 case IB_WR_RDMA_WRITE: 4320 case IB_WR_RDMA_WRITE_WITH_IMM: 4321 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4322 rdma_wr(wr)->rkey); 4323 seg += sizeof(struct mlx5_wqe_raddr_seg); 4324 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4325 break; 4326 4327 case IB_WR_ATOMIC_CMP_AND_SWP: 4328 case IB_WR_ATOMIC_FETCH_AND_ADD: 4329 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4330 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4331 err = -ENOSYS; 4332 *bad_wr = wr; 4333 goto out; 4334 4335 case IB_WR_LOCAL_INV: 4336 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4337 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4338 set_linv_wr(qp, &seg, &size); 4339 num_sge = 0; 4340 break; 4341 4342 case IB_WR_REG_MR: 4343 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4344 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4345 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4346 if (err) { 4347 *bad_wr = wr; 4348 goto out; 4349 } 4350 num_sge = 0; 4351 break; 4352 4353 case IB_WR_REG_SIG_MR: 4354 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4355 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4356 4357 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4358 err = set_sig_umr_wr(wr, qp, &seg, &size); 4359 if (err) { 4360 mlx5_ib_warn(dev, "\n"); 4361 *bad_wr = wr; 4362 goto out; 4363 } 4364 4365 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4366 fence, MLX5_OPCODE_UMR); 4367 /* 4368 * SET_PSV WQEs are not signaled and solicited 4369 * on error 4370 */ 4371 wr->send_flags &= ~IB_SEND_SIGNALED; 4372 wr->send_flags |= IB_SEND_SOLICITED; 4373 err = begin_wqe(qp, &seg, &ctrl, wr, 4374 &idx, &size, nreq); 4375 if (err) { 4376 mlx5_ib_warn(dev, "\n"); 4377 err = -ENOMEM; 4378 *bad_wr = wr; 4379 goto out; 4380 } 4381 4382 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4383 mr->sig->psv_memory.psv_idx, &seg, 4384 &size); 4385 if (err) { 4386 mlx5_ib_warn(dev, "\n"); 4387 *bad_wr = wr; 4388 goto out; 4389 } 4390 4391 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4392 fence, MLX5_OPCODE_SET_PSV); 4393 err = begin_wqe(qp, &seg, &ctrl, wr, 4394 &idx, &size, nreq); 4395 if (err) { 4396 mlx5_ib_warn(dev, "\n"); 4397 err = -ENOMEM; 4398 *bad_wr = wr; 4399 goto out; 4400 } 4401 4402 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4403 mr->sig->psv_wire.psv_idx, &seg, 4404 &size); 4405 if (err) { 4406 mlx5_ib_warn(dev, "\n"); 4407 *bad_wr = wr; 4408 goto out; 4409 } 4410 4411 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4412 fence, MLX5_OPCODE_SET_PSV); 4413 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4414 num_sge = 0; 4415 goto skip_psv; 4416 4417 default: 4418 break; 4419 } 4420 break; 4421 4422 case IB_QPT_UC: 4423 switch (wr->opcode) { 4424 case IB_WR_RDMA_WRITE: 4425 case IB_WR_RDMA_WRITE_WITH_IMM: 4426 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4427 rdma_wr(wr)->rkey); 4428 seg += sizeof(struct mlx5_wqe_raddr_seg); 4429 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4430 break; 4431 4432 default: 4433 break; 4434 } 4435 break; 4436 4437 case IB_QPT_SMI: 4438 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4439 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4440 err = -EPERM; 4441 *bad_wr = wr; 4442 goto out; 4443 } 4444 /* fall through */ 4445 case MLX5_IB_QPT_HW_GSI: 4446 set_datagram_seg(seg, wr); 4447 seg += sizeof(struct mlx5_wqe_datagram_seg); 4448 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4449 if (unlikely((seg == qend))) 4450 seg = mlx5_get_send_wqe(qp, 0); 4451 break; 4452 case IB_QPT_UD: 4453 set_datagram_seg(seg, wr); 4454 seg += sizeof(struct mlx5_wqe_datagram_seg); 4455 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4456 4457 if (unlikely((seg == qend))) 4458 seg = mlx5_get_send_wqe(qp, 0); 4459 4460 /* handle qp that supports ud offload */ 4461 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4462 struct mlx5_wqe_eth_pad *pad; 4463 4464 pad = seg; 4465 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4466 seg += sizeof(struct mlx5_wqe_eth_pad); 4467 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4468 4469 seg = set_eth_seg(seg, wr, qend, qp, &size); 4470 4471 if (unlikely((seg == qend))) 4472 seg = mlx5_get_send_wqe(qp, 0); 4473 } 4474 break; 4475 case MLX5_IB_QPT_REG_UMR: 4476 if (wr->opcode != MLX5_IB_WR_UMR) { 4477 err = -EINVAL; 4478 mlx5_ib_warn(dev, "bad opcode\n"); 4479 goto out; 4480 } 4481 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4482 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4483 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4484 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4485 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4486 if (unlikely((seg == qend))) 4487 seg = mlx5_get_send_wqe(qp, 0); 4488 set_reg_mkey_segment(seg, wr); 4489 seg += sizeof(struct mlx5_mkey_seg); 4490 size += sizeof(struct mlx5_mkey_seg) / 16; 4491 if (unlikely((seg == qend))) 4492 seg = mlx5_get_send_wqe(qp, 0); 4493 break; 4494 4495 default: 4496 break; 4497 } 4498 4499 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4500 int uninitialized_var(sz); 4501 4502 err = set_data_inl_seg(qp, wr, seg, &sz); 4503 if (unlikely(err)) { 4504 mlx5_ib_warn(dev, "\n"); 4505 *bad_wr = wr; 4506 goto out; 4507 } 4508 size += sz; 4509 } else { 4510 dpseg = seg; 4511 for (i = 0; i < num_sge; i++) { 4512 if (unlikely(dpseg == qend)) { 4513 seg = mlx5_get_send_wqe(qp, 0); 4514 dpseg = seg; 4515 } 4516 if (likely(wr->sg_list[i].length)) { 4517 set_data_ptr_seg(dpseg, wr->sg_list + i); 4518 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4519 dpseg++; 4520 } 4521 } 4522 } 4523 4524 qp->next_fence = next_fence; 4525 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4526 mlx5_ib_opcode[wr->opcode]); 4527 skip_psv: 4528 if (0) 4529 dump_wqe(qp, idx, size); 4530 } 4531 4532 out: 4533 if (likely(nreq)) { 4534 qp->sq.head += nreq; 4535 4536 /* Make sure that descriptors are written before 4537 * updating doorbell record and ringing the doorbell 4538 */ 4539 wmb(); 4540 4541 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4542 4543 /* Make sure doorbell record is visible to the HCA before 4544 * we hit doorbell */ 4545 wmb(); 4546 4547 /* currently we support only regular doorbells */ 4548 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4549 /* Make sure doorbells don't leak out of SQ spinlock 4550 * and reach the HCA out of order. 4551 */ 4552 mmiowb(); 4553 bf->offset ^= bf->buf_size; 4554 } 4555 4556 spin_unlock_irqrestore(&qp->sq.lock, flags); 4557 4558 return err; 4559 } 4560 4561 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4562 { 4563 sig->signature = calc_sig(sig, size); 4564 } 4565 4566 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4567 struct ib_recv_wr **bad_wr) 4568 { 4569 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4570 struct mlx5_wqe_data_seg *scat; 4571 struct mlx5_rwqe_sig *sig; 4572 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4573 struct mlx5_core_dev *mdev = dev->mdev; 4574 unsigned long flags; 4575 int err = 0; 4576 int nreq; 4577 int ind; 4578 int i; 4579 4580 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4581 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4582 4583 spin_lock_irqsave(&qp->rq.lock, flags); 4584 4585 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4586 err = -EIO; 4587 *bad_wr = wr; 4588 nreq = 0; 4589 goto out; 4590 } 4591 4592 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4593 4594 for (nreq = 0; wr; nreq++, wr = wr->next) { 4595 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4596 err = -ENOMEM; 4597 *bad_wr = wr; 4598 goto out; 4599 } 4600 4601 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4602 err = -EINVAL; 4603 *bad_wr = wr; 4604 goto out; 4605 } 4606 4607 scat = get_recv_wqe(qp, ind); 4608 if (qp->wq_sig) 4609 scat++; 4610 4611 for (i = 0; i < wr->num_sge; i++) 4612 set_data_ptr_seg(scat + i, wr->sg_list + i); 4613 4614 if (i < qp->rq.max_gs) { 4615 scat[i].byte_count = 0; 4616 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4617 scat[i].addr = 0; 4618 } 4619 4620 if (qp->wq_sig) { 4621 sig = (struct mlx5_rwqe_sig *)scat; 4622 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4623 } 4624 4625 qp->rq.wrid[ind] = wr->wr_id; 4626 4627 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4628 } 4629 4630 out: 4631 if (likely(nreq)) { 4632 qp->rq.head += nreq; 4633 4634 /* Make sure that descriptors are written before 4635 * doorbell record. 4636 */ 4637 wmb(); 4638 4639 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4640 } 4641 4642 spin_unlock_irqrestore(&qp->rq.lock, flags); 4643 4644 return err; 4645 } 4646 4647 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4648 { 4649 switch (mlx5_state) { 4650 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4651 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4652 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4653 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4654 case MLX5_QP_STATE_SQ_DRAINING: 4655 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4656 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4657 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4658 default: return -1; 4659 } 4660 } 4661 4662 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4663 { 4664 switch (mlx5_mig_state) { 4665 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4666 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4667 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4668 default: return -1; 4669 } 4670 } 4671 4672 static int to_ib_qp_access_flags(int mlx5_flags) 4673 { 4674 int ib_flags = 0; 4675 4676 if (mlx5_flags & MLX5_QP_BIT_RRE) 4677 ib_flags |= IB_ACCESS_REMOTE_READ; 4678 if (mlx5_flags & MLX5_QP_BIT_RWE) 4679 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4680 if (mlx5_flags & MLX5_QP_BIT_RAE) 4681 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4682 4683 return ib_flags; 4684 } 4685 4686 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4687 struct rdma_ah_attr *ah_attr, 4688 struct mlx5_qp_path *path) 4689 { 4690 4691 memset(ah_attr, 0, sizeof(*ah_attr)); 4692 4693 if (!path->port || path->port > ibdev->num_ports) 4694 return; 4695 4696 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4697 4698 rdma_ah_set_port_num(ah_attr, path->port); 4699 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4700 4701 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4702 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4703 rdma_ah_set_static_rate(ah_attr, 4704 path->static_rate ? path->static_rate - 5 : 0); 4705 if (path->grh_mlid & (1 << 7)) { 4706 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4707 4708 rdma_ah_set_grh(ah_attr, NULL, 4709 tc_fl & 0xfffff, 4710 path->mgid_index, 4711 path->hop_limit, 4712 (tc_fl >> 20) & 0xff); 4713 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4714 } 4715 } 4716 4717 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4718 struct mlx5_ib_sq *sq, 4719 u8 *sq_state) 4720 { 4721 void *out; 4722 void *sqc; 4723 int inlen; 4724 int err; 4725 4726 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4727 out = kvzalloc(inlen, GFP_KERNEL); 4728 if (!out) 4729 return -ENOMEM; 4730 4731 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4732 if (err) 4733 goto out; 4734 4735 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4736 *sq_state = MLX5_GET(sqc, sqc, state); 4737 sq->state = *sq_state; 4738 4739 out: 4740 kvfree(out); 4741 return err; 4742 } 4743 4744 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4745 struct mlx5_ib_rq *rq, 4746 u8 *rq_state) 4747 { 4748 void *out; 4749 void *rqc; 4750 int inlen; 4751 int err; 4752 4753 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4754 out = kvzalloc(inlen, GFP_KERNEL); 4755 if (!out) 4756 return -ENOMEM; 4757 4758 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4759 if (err) 4760 goto out; 4761 4762 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4763 *rq_state = MLX5_GET(rqc, rqc, state); 4764 rq->state = *rq_state; 4765 4766 out: 4767 kvfree(out); 4768 return err; 4769 } 4770 4771 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4772 struct mlx5_ib_qp *qp, u8 *qp_state) 4773 { 4774 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4775 [MLX5_RQC_STATE_RST] = { 4776 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4777 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4778 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4779 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4780 }, 4781 [MLX5_RQC_STATE_RDY] = { 4782 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4783 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4784 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4785 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4786 }, 4787 [MLX5_RQC_STATE_ERR] = { 4788 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4789 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4790 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4791 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4792 }, 4793 [MLX5_RQ_STATE_NA] = { 4794 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4795 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4796 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4797 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4798 }, 4799 }; 4800 4801 *qp_state = sqrq_trans[rq_state][sq_state]; 4802 4803 if (*qp_state == MLX5_QP_STATE_BAD) { 4804 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4805 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4806 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4807 return -EINVAL; 4808 } 4809 4810 if (*qp_state == MLX5_QP_STATE) 4811 *qp_state = qp->state; 4812 4813 return 0; 4814 } 4815 4816 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4817 struct mlx5_ib_qp *qp, 4818 u8 *raw_packet_qp_state) 4819 { 4820 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4821 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4822 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4823 int err; 4824 u8 sq_state = MLX5_SQ_STATE_NA; 4825 u8 rq_state = MLX5_RQ_STATE_NA; 4826 4827 if (qp->sq.wqe_cnt) { 4828 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4829 if (err) 4830 return err; 4831 } 4832 4833 if (qp->rq.wqe_cnt) { 4834 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4835 if (err) 4836 return err; 4837 } 4838 4839 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4840 raw_packet_qp_state); 4841 } 4842 4843 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4844 struct ib_qp_attr *qp_attr) 4845 { 4846 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4847 struct mlx5_qp_context *context; 4848 int mlx5_state; 4849 u32 *outb; 4850 int err = 0; 4851 4852 outb = kzalloc(outlen, GFP_KERNEL); 4853 if (!outb) 4854 return -ENOMEM; 4855 4856 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4857 outlen); 4858 if (err) 4859 goto out; 4860 4861 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4862 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4863 4864 mlx5_state = be32_to_cpu(context->flags) >> 28; 4865 4866 qp->state = to_ib_qp_state(mlx5_state); 4867 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4868 qp_attr->path_mig_state = 4869 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4870 qp_attr->qkey = be32_to_cpu(context->qkey); 4871 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4872 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4873 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4874 qp_attr->qp_access_flags = 4875 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4876 4877 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4878 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4879 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4880 qp_attr->alt_pkey_index = 4881 be16_to_cpu(context->alt_path.pkey_index); 4882 qp_attr->alt_port_num = 4883 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4884 } 4885 4886 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4887 qp_attr->port_num = context->pri_path.port; 4888 4889 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4890 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4891 4892 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4893 4894 qp_attr->max_dest_rd_atomic = 4895 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4896 qp_attr->min_rnr_timer = 4897 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4898 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4899 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4900 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4901 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4902 4903 out: 4904 kfree(outb); 4905 return err; 4906 } 4907 4908 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4909 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4910 struct ib_qp_init_attr *qp_init_attr) 4911 { 4912 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4913 u32 *out; 4914 u32 access_flags = 0; 4915 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4916 void *dctc; 4917 int err; 4918 int supported_mask = IB_QP_STATE | 4919 IB_QP_ACCESS_FLAGS | 4920 IB_QP_PORT | 4921 IB_QP_MIN_RNR_TIMER | 4922 IB_QP_AV | 4923 IB_QP_PATH_MTU | 4924 IB_QP_PKEY_INDEX; 4925 4926 if (qp_attr_mask & ~supported_mask) 4927 return -EINVAL; 4928 if (mqp->state != IB_QPS_RTR) 4929 return -EINVAL; 4930 4931 out = kzalloc(outlen, GFP_KERNEL); 4932 if (!out) 4933 return -ENOMEM; 4934 4935 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 4936 if (err) 4937 goto out; 4938 4939 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4940 4941 if (qp_attr_mask & IB_QP_STATE) 4942 qp_attr->qp_state = IB_QPS_RTR; 4943 4944 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4945 if (MLX5_GET(dctc, dctc, rre)) 4946 access_flags |= IB_ACCESS_REMOTE_READ; 4947 if (MLX5_GET(dctc, dctc, rwe)) 4948 access_flags |= IB_ACCESS_REMOTE_WRITE; 4949 if (MLX5_GET(dctc, dctc, rae)) 4950 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4951 qp_attr->qp_access_flags = access_flags; 4952 } 4953 4954 if (qp_attr_mask & IB_QP_PORT) 4955 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4956 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4957 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4958 if (qp_attr_mask & IB_QP_AV) { 4959 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4960 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4961 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4962 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4963 } 4964 if (qp_attr_mask & IB_QP_PATH_MTU) 4965 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4966 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4967 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4968 out: 4969 kfree(out); 4970 return err; 4971 } 4972 4973 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4974 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4975 { 4976 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4977 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4978 int err = 0; 4979 u8 raw_packet_qp_state; 4980 4981 if (ibqp->rwq_ind_tbl) 4982 return -ENOSYS; 4983 4984 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4985 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4986 qp_init_attr); 4987 4988 /* Not all of output fields are applicable, make sure to zero them */ 4989 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4990 memset(qp_attr, 0, sizeof(*qp_attr)); 4991 4992 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 4993 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4994 qp_attr_mask, qp_init_attr); 4995 4996 mutex_lock(&qp->mutex); 4997 4998 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4999 qp->flags & MLX5_IB_QP_UNDERLAY) { 5000 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5001 if (err) 5002 goto out; 5003 qp->state = raw_packet_qp_state; 5004 qp_attr->port_num = 1; 5005 } else { 5006 err = query_qp_attr(dev, qp, qp_attr); 5007 if (err) 5008 goto out; 5009 } 5010 5011 qp_attr->qp_state = qp->state; 5012 qp_attr->cur_qp_state = qp_attr->qp_state; 5013 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5014 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5015 5016 if (!ibqp->uobject) { 5017 qp_attr->cap.max_send_wr = qp->sq.max_post; 5018 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5019 qp_init_attr->qp_context = ibqp->qp_context; 5020 } else { 5021 qp_attr->cap.max_send_wr = 0; 5022 qp_attr->cap.max_send_sge = 0; 5023 } 5024 5025 qp_init_attr->qp_type = ibqp->qp_type; 5026 qp_init_attr->recv_cq = ibqp->recv_cq; 5027 qp_init_attr->send_cq = ibqp->send_cq; 5028 qp_init_attr->srq = ibqp->srq; 5029 qp_attr->cap.max_inline_data = qp->max_inline_data; 5030 5031 qp_init_attr->cap = qp_attr->cap; 5032 5033 qp_init_attr->create_flags = 0; 5034 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5035 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5036 5037 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5038 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5039 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5040 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5041 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5042 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5043 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5044 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5045 5046 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5047 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5048 5049 out: 5050 mutex_unlock(&qp->mutex); 5051 return err; 5052 } 5053 5054 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5055 struct ib_ucontext *context, 5056 struct ib_udata *udata) 5057 { 5058 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5059 struct mlx5_ib_xrcd *xrcd; 5060 int err; 5061 5062 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5063 return ERR_PTR(-ENOSYS); 5064 5065 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5066 if (!xrcd) 5067 return ERR_PTR(-ENOMEM); 5068 5069 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 5070 if (err) { 5071 kfree(xrcd); 5072 return ERR_PTR(-ENOMEM); 5073 } 5074 5075 return &xrcd->ibxrcd; 5076 } 5077 5078 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5079 { 5080 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5081 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5082 int err; 5083 5084 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 5085 if (err) 5086 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5087 5088 kfree(xrcd); 5089 return 0; 5090 } 5091 5092 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5093 { 5094 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5095 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5096 struct ib_event event; 5097 5098 if (rwq->ibwq.event_handler) { 5099 event.device = rwq->ibwq.device; 5100 event.element.wq = &rwq->ibwq; 5101 switch (type) { 5102 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5103 event.event = IB_EVENT_WQ_FATAL; 5104 break; 5105 default: 5106 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5107 return; 5108 } 5109 5110 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5111 } 5112 } 5113 5114 static int set_delay_drop(struct mlx5_ib_dev *dev) 5115 { 5116 int err = 0; 5117 5118 mutex_lock(&dev->delay_drop.lock); 5119 if (dev->delay_drop.activate) 5120 goto out; 5121 5122 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5123 if (err) 5124 goto out; 5125 5126 dev->delay_drop.activate = true; 5127 out: 5128 mutex_unlock(&dev->delay_drop.lock); 5129 5130 if (!err) 5131 atomic_inc(&dev->delay_drop.rqs_cnt); 5132 return err; 5133 } 5134 5135 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5136 struct ib_wq_init_attr *init_attr) 5137 { 5138 struct mlx5_ib_dev *dev; 5139 int has_net_offloads; 5140 __be64 *rq_pas0; 5141 void *in; 5142 void *rqc; 5143 void *wq; 5144 int inlen; 5145 int err; 5146 5147 dev = to_mdev(pd->device); 5148 5149 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5150 in = kvzalloc(inlen, GFP_KERNEL); 5151 if (!in) 5152 return -ENOMEM; 5153 5154 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5155 MLX5_SET(rqc, rqc, mem_rq_type, 5156 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5157 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5158 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5159 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5160 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5161 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5162 MLX5_SET(wq, wq, wq_type, 5163 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5164 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5165 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5166 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5167 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5168 err = -EOPNOTSUPP; 5169 goto out; 5170 } else { 5171 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5172 } 5173 } 5174 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5175 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5176 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5177 MLX5_SET(wq, wq, log_wqe_stride_size, 5178 rwq->single_stride_log_num_of_bytes - 5179 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5180 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5181 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5182 } 5183 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5184 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5185 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5186 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5187 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5188 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5189 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5190 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5191 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5192 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5193 err = -EOPNOTSUPP; 5194 goto out; 5195 } 5196 } else { 5197 MLX5_SET(rqc, rqc, vsd, 1); 5198 } 5199 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5200 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5201 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5202 err = -EOPNOTSUPP; 5203 goto out; 5204 } 5205 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5206 } 5207 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5208 if (!(dev->ib_dev.attrs.raw_packet_caps & 5209 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5210 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5211 err = -EOPNOTSUPP; 5212 goto out; 5213 } 5214 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5215 } 5216 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5217 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5218 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5219 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5220 err = set_delay_drop(dev); 5221 if (err) { 5222 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5223 err); 5224 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5225 } else { 5226 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5227 } 5228 } 5229 out: 5230 kvfree(in); 5231 return err; 5232 } 5233 5234 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5235 struct ib_wq_init_attr *wq_init_attr, 5236 struct mlx5_ib_create_wq *ucmd, 5237 struct mlx5_ib_rwq *rwq) 5238 { 5239 /* Sanity check RQ size before proceeding */ 5240 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5241 return -EINVAL; 5242 5243 if (!ucmd->rq_wqe_count) 5244 return -EINVAL; 5245 5246 rwq->wqe_count = ucmd->rq_wqe_count; 5247 rwq->wqe_shift = ucmd->rq_wqe_shift; 5248 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 5249 rwq->log_rq_stride = rwq->wqe_shift; 5250 rwq->log_rq_size = ilog2(rwq->wqe_count); 5251 return 0; 5252 } 5253 5254 static int prepare_user_rq(struct ib_pd *pd, 5255 struct ib_wq_init_attr *init_attr, 5256 struct ib_udata *udata, 5257 struct mlx5_ib_rwq *rwq) 5258 { 5259 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5260 struct mlx5_ib_create_wq ucmd = {}; 5261 int err; 5262 size_t required_cmd_sz; 5263 5264 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5265 + sizeof(ucmd.single_stride_log_num_of_bytes); 5266 if (udata->inlen < required_cmd_sz) { 5267 mlx5_ib_dbg(dev, "invalid inlen\n"); 5268 return -EINVAL; 5269 } 5270 5271 if (udata->inlen > sizeof(ucmd) && 5272 !ib_is_udata_cleared(udata, sizeof(ucmd), 5273 udata->inlen - sizeof(ucmd))) { 5274 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5275 return -EOPNOTSUPP; 5276 } 5277 5278 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5279 mlx5_ib_dbg(dev, "copy failed\n"); 5280 return -EFAULT; 5281 } 5282 5283 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5284 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5285 return -EOPNOTSUPP; 5286 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5287 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5288 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5289 return -EOPNOTSUPP; 5290 } 5291 if ((ucmd.single_stride_log_num_of_bytes < 5292 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5293 (ucmd.single_stride_log_num_of_bytes > 5294 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5295 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5296 ucmd.single_stride_log_num_of_bytes, 5297 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5298 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5299 return -EINVAL; 5300 } 5301 if ((ucmd.single_wqe_log_num_of_strides > 5302 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5303 (ucmd.single_wqe_log_num_of_strides < 5304 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5305 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5306 ucmd.single_wqe_log_num_of_strides, 5307 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5308 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5309 return -EINVAL; 5310 } 5311 rwq->single_stride_log_num_of_bytes = 5312 ucmd.single_stride_log_num_of_bytes; 5313 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5314 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5315 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5316 } 5317 5318 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5319 if (err) { 5320 mlx5_ib_dbg(dev, "err %d\n", err); 5321 return err; 5322 } 5323 5324 err = create_user_rq(dev, pd, rwq, &ucmd); 5325 if (err) { 5326 mlx5_ib_dbg(dev, "err %d\n", err); 5327 if (err) 5328 return err; 5329 } 5330 5331 rwq->user_index = ucmd.user_index; 5332 return 0; 5333 } 5334 5335 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5336 struct ib_wq_init_attr *init_attr, 5337 struct ib_udata *udata) 5338 { 5339 struct mlx5_ib_dev *dev; 5340 struct mlx5_ib_rwq *rwq; 5341 struct mlx5_ib_create_wq_resp resp = {}; 5342 size_t min_resp_len; 5343 int err; 5344 5345 if (!udata) 5346 return ERR_PTR(-ENOSYS); 5347 5348 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5349 if (udata->outlen && udata->outlen < min_resp_len) 5350 return ERR_PTR(-EINVAL); 5351 5352 dev = to_mdev(pd->device); 5353 switch (init_attr->wq_type) { 5354 case IB_WQT_RQ: 5355 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5356 if (!rwq) 5357 return ERR_PTR(-ENOMEM); 5358 err = prepare_user_rq(pd, init_attr, udata, rwq); 5359 if (err) 5360 goto err; 5361 err = create_rq(rwq, pd, init_attr); 5362 if (err) 5363 goto err_user_rq; 5364 break; 5365 default: 5366 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5367 init_attr->wq_type); 5368 return ERR_PTR(-EINVAL); 5369 } 5370 5371 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5372 rwq->ibwq.state = IB_WQS_RESET; 5373 if (udata->outlen) { 5374 resp.response_length = offsetof(typeof(resp), response_length) + 5375 sizeof(resp.response_length); 5376 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5377 if (err) 5378 goto err_copy; 5379 } 5380 5381 rwq->core_qp.event = mlx5_ib_wq_event; 5382 rwq->ibwq.event_handler = init_attr->event_handler; 5383 return &rwq->ibwq; 5384 5385 err_copy: 5386 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5387 err_user_rq: 5388 destroy_user_rq(dev, pd, rwq); 5389 err: 5390 kfree(rwq); 5391 return ERR_PTR(err); 5392 } 5393 5394 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5395 { 5396 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5397 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5398 5399 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5400 destroy_user_rq(dev, wq->pd, rwq); 5401 kfree(rwq); 5402 5403 return 0; 5404 } 5405 5406 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5407 struct ib_rwq_ind_table_init_attr *init_attr, 5408 struct ib_udata *udata) 5409 { 5410 struct mlx5_ib_dev *dev = to_mdev(device); 5411 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5412 int sz = 1 << init_attr->log_ind_tbl_size; 5413 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5414 size_t min_resp_len; 5415 int inlen; 5416 int err; 5417 int i; 5418 u32 *in; 5419 void *rqtc; 5420 5421 if (udata->inlen > 0 && 5422 !ib_is_udata_cleared(udata, 0, 5423 udata->inlen)) 5424 return ERR_PTR(-EOPNOTSUPP); 5425 5426 if (init_attr->log_ind_tbl_size > 5427 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5428 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5429 init_attr->log_ind_tbl_size, 5430 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5431 return ERR_PTR(-EINVAL); 5432 } 5433 5434 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5435 if (udata->outlen && udata->outlen < min_resp_len) 5436 return ERR_PTR(-EINVAL); 5437 5438 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5439 if (!rwq_ind_tbl) 5440 return ERR_PTR(-ENOMEM); 5441 5442 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5443 in = kvzalloc(inlen, GFP_KERNEL); 5444 if (!in) { 5445 err = -ENOMEM; 5446 goto err; 5447 } 5448 5449 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5450 5451 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5452 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5453 5454 for (i = 0; i < sz; i++) 5455 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5456 5457 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5458 kvfree(in); 5459 5460 if (err) 5461 goto err; 5462 5463 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5464 if (udata->outlen) { 5465 resp.response_length = offsetof(typeof(resp), response_length) + 5466 sizeof(resp.response_length); 5467 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5468 if (err) 5469 goto err_copy; 5470 } 5471 5472 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5473 5474 err_copy: 5475 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5476 err: 5477 kfree(rwq_ind_tbl); 5478 return ERR_PTR(err); 5479 } 5480 5481 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5482 { 5483 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5484 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5485 5486 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5487 5488 kfree(rwq_ind_tbl); 5489 return 0; 5490 } 5491 5492 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5493 u32 wq_attr_mask, struct ib_udata *udata) 5494 { 5495 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5496 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5497 struct mlx5_ib_modify_wq ucmd = {}; 5498 size_t required_cmd_sz; 5499 int curr_wq_state; 5500 int wq_state; 5501 int inlen; 5502 int err; 5503 void *rqc; 5504 void *in; 5505 5506 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5507 if (udata->inlen < required_cmd_sz) 5508 return -EINVAL; 5509 5510 if (udata->inlen > sizeof(ucmd) && 5511 !ib_is_udata_cleared(udata, sizeof(ucmd), 5512 udata->inlen - sizeof(ucmd))) 5513 return -EOPNOTSUPP; 5514 5515 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5516 return -EFAULT; 5517 5518 if (ucmd.comp_mask || ucmd.reserved) 5519 return -EOPNOTSUPP; 5520 5521 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5522 in = kvzalloc(inlen, GFP_KERNEL); 5523 if (!in) 5524 return -ENOMEM; 5525 5526 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5527 5528 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5529 wq_attr->curr_wq_state : wq->state; 5530 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5531 wq_attr->wq_state : curr_wq_state; 5532 if (curr_wq_state == IB_WQS_ERR) 5533 curr_wq_state = MLX5_RQC_STATE_ERR; 5534 if (wq_state == IB_WQS_ERR) 5535 wq_state = MLX5_RQC_STATE_ERR; 5536 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5537 MLX5_SET(rqc, rqc, state, wq_state); 5538 5539 if (wq_attr_mask & IB_WQ_FLAGS) { 5540 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5541 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5542 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5543 mlx5_ib_dbg(dev, "VLAN offloads are not " 5544 "supported\n"); 5545 err = -EOPNOTSUPP; 5546 goto out; 5547 } 5548 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5549 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5550 MLX5_SET(rqc, rqc, vsd, 5551 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5552 } 5553 5554 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5555 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5556 err = -EOPNOTSUPP; 5557 goto out; 5558 } 5559 } 5560 5561 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5562 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5563 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5564 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5565 MLX5_SET(rqc, rqc, counter_set_id, 5566 dev->port->cnts.set_id); 5567 } else 5568 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5569 dev->ib_dev.name); 5570 } 5571 5572 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5573 if (!err) 5574 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5575 5576 out: 5577 kvfree(in); 5578 return err; 5579 } 5580