1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include "mlx5_ib.h" 38 #include "user.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 MLX5_IB_CACHE_LINE_SIZE = 64, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 static void get_cqs(enum ib_qp_type qp_type, 81 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 82 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 83 84 static int is_qp0(enum ib_qp_type qp_type) 85 { 86 return qp_type == IB_QPT_SMI; 87 } 88 89 static int is_sqp(enum ib_qp_type qp_type) 90 { 91 return is_qp0(qp_type) || is_qp1(qp_type); 92 } 93 94 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 95 { 96 return mlx5_buf_offset(&qp->buf, offset); 97 } 98 99 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 100 { 101 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 102 } 103 104 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 105 { 106 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 107 } 108 109 /** 110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 111 * 112 * @qp: QP to copy from. 113 * @send: copy from the send queue when non-zero, use the receive queue 114 * otherwise. 115 * @wqe_index: index to start copying from. For send work queues, the 116 * wqe_index is in units of MLX5_SEND_WQE_BB. 117 * For receive work queue, it is the number of work queue 118 * element in the queue. 119 * @buffer: destination buffer. 120 * @length: maximum number of bytes to copy. 121 * 122 * Copies at least a single WQE, but may copy more data. 123 * 124 * Return: the number of bytes copied, or an error code. 125 */ 126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 127 void *buffer, u32 length, 128 struct mlx5_ib_qp_base *base) 129 { 130 struct ib_device *ibdev = qp->ibqp.device; 131 struct mlx5_ib_dev *dev = to_mdev(ibdev); 132 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 133 size_t offset; 134 size_t wq_end; 135 struct ib_umem *umem = base->ubuffer.umem; 136 u32 first_copy_length; 137 int wqe_length; 138 int ret; 139 140 if (wq->wqe_cnt == 0) { 141 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 142 qp->ibqp.qp_type); 143 return -EINVAL; 144 } 145 146 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 147 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 148 149 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 150 return -EINVAL; 151 152 if (offset > umem->length || 153 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 154 return -EINVAL; 155 156 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 157 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 158 if (ret) 159 return ret; 160 161 if (send) { 162 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 163 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 164 165 wqe_length = ds * MLX5_WQE_DS_UNITS; 166 } else { 167 wqe_length = 1 << wq->wqe_shift; 168 } 169 170 if (wqe_length <= first_copy_length) 171 return first_copy_length; 172 173 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 174 wqe_length - first_copy_length); 175 if (ret) 176 return ret; 177 178 return wqe_length; 179 } 180 181 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 182 { 183 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 184 struct ib_event event; 185 186 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 187 /* This event is only valid for trans_qps */ 188 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 189 } 190 191 if (ibqp->event_handler) { 192 event.device = ibqp->device; 193 event.element.qp = ibqp; 194 switch (type) { 195 case MLX5_EVENT_TYPE_PATH_MIG: 196 event.event = IB_EVENT_PATH_MIG; 197 break; 198 case MLX5_EVENT_TYPE_COMM_EST: 199 event.event = IB_EVENT_COMM_EST; 200 break; 201 case MLX5_EVENT_TYPE_SQ_DRAINED: 202 event.event = IB_EVENT_SQ_DRAINED; 203 break; 204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 205 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 206 break; 207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 208 event.event = IB_EVENT_QP_FATAL; 209 break; 210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 211 event.event = IB_EVENT_PATH_MIG_ERR; 212 break; 213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 214 event.event = IB_EVENT_QP_REQ_ERR; 215 break; 216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 217 event.event = IB_EVENT_QP_ACCESS_ERR; 218 break; 219 default: 220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 221 return; 222 } 223 224 ibqp->event_handler(&event, ibqp->qp_context); 225 } 226 } 227 228 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 229 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 230 { 231 int wqe_size; 232 int wq_size; 233 234 /* Sanity check RQ size before proceeding */ 235 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 236 return -EINVAL; 237 238 if (!has_rq) { 239 qp->rq.max_gs = 0; 240 qp->rq.wqe_cnt = 0; 241 qp->rq.wqe_shift = 0; 242 cap->max_recv_wr = 0; 243 cap->max_recv_sge = 0; 244 } else { 245 if (ucmd) { 246 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 247 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 248 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 249 qp->rq.max_post = qp->rq.wqe_cnt; 250 } else { 251 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 252 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 253 wqe_size = roundup_pow_of_two(wqe_size); 254 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 255 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 256 qp->rq.wqe_cnt = wq_size / wqe_size; 257 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 258 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 259 wqe_size, 260 MLX5_CAP_GEN(dev->mdev, 261 max_wqe_sz_rq)); 262 return -EINVAL; 263 } 264 qp->rq.wqe_shift = ilog2(wqe_size); 265 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 266 qp->rq.max_post = qp->rq.wqe_cnt; 267 } 268 } 269 270 return 0; 271 } 272 273 static int sq_overhead(struct ib_qp_init_attr *attr) 274 { 275 int size = 0; 276 277 switch (attr->qp_type) { 278 case IB_QPT_XRC_INI: 279 size += sizeof(struct mlx5_wqe_xrc_seg); 280 /* fall through */ 281 case IB_QPT_RC: 282 size += sizeof(struct mlx5_wqe_ctrl_seg) + 283 max(sizeof(struct mlx5_wqe_atomic_seg) + 284 sizeof(struct mlx5_wqe_raddr_seg), 285 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 286 sizeof(struct mlx5_mkey_seg)); 287 break; 288 289 case IB_QPT_XRC_TGT: 290 return 0; 291 292 case IB_QPT_UC: 293 size += sizeof(struct mlx5_wqe_ctrl_seg) + 294 max(sizeof(struct mlx5_wqe_raddr_seg), 295 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 296 sizeof(struct mlx5_mkey_seg)); 297 break; 298 299 case IB_QPT_UD: 300 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 301 size += sizeof(struct mlx5_wqe_eth_pad) + 302 sizeof(struct mlx5_wqe_eth_seg); 303 /* fall through */ 304 case IB_QPT_SMI: 305 case MLX5_IB_QPT_HW_GSI: 306 size += sizeof(struct mlx5_wqe_ctrl_seg) + 307 sizeof(struct mlx5_wqe_datagram_seg); 308 break; 309 310 case MLX5_IB_QPT_REG_UMR: 311 size += sizeof(struct mlx5_wqe_ctrl_seg) + 312 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 313 sizeof(struct mlx5_mkey_seg); 314 break; 315 316 default: 317 return -EINVAL; 318 } 319 320 return size; 321 } 322 323 static int calc_send_wqe(struct ib_qp_init_attr *attr) 324 { 325 int inl_size = 0; 326 int size; 327 328 size = sq_overhead(attr); 329 if (size < 0) 330 return size; 331 332 if (attr->cap.max_inline_data) { 333 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 334 attr->cap.max_inline_data; 335 } 336 337 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 338 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 339 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 340 return MLX5_SIG_WQE_SIZE; 341 else 342 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 343 } 344 345 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 346 struct mlx5_ib_qp *qp) 347 { 348 int wqe_size; 349 int wq_size; 350 351 if (!attr->cap.max_send_wr) 352 return 0; 353 354 wqe_size = calc_send_wqe(attr); 355 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 356 if (wqe_size < 0) 357 return wqe_size; 358 359 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 360 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 361 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 362 return -EINVAL; 363 } 364 365 qp->max_inline_data = wqe_size - sq_overhead(attr) - 366 sizeof(struct mlx5_wqe_inline_seg); 367 attr->cap.max_inline_data = qp->max_inline_data; 368 369 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 370 qp->signature_en = true; 371 372 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 373 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 374 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 375 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 376 qp->sq.wqe_cnt, 377 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 378 return -ENOMEM; 379 } 380 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 381 qp->sq.max_gs = attr->cap.max_send_sge; 382 qp->sq.max_post = wq_size / wqe_size; 383 attr->cap.max_send_wr = qp->sq.max_post; 384 385 return wq_size; 386 } 387 388 static int set_user_buf_size(struct mlx5_ib_dev *dev, 389 struct mlx5_ib_qp *qp, 390 struct mlx5_ib_create_qp *ucmd, 391 struct mlx5_ib_qp_base *base, 392 struct ib_qp_init_attr *attr) 393 { 394 int desc_sz = 1 << qp->sq.wqe_shift; 395 396 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 397 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 398 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 399 return -EINVAL; 400 } 401 402 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 403 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 404 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 405 return -EINVAL; 406 } 407 408 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 409 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 411 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -EINVAL; 415 } 416 417 if (attr->qp_type == IB_QPT_RAW_PACKET) { 418 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 419 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 420 } else { 421 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 422 (qp->sq.wqe_cnt << 6); 423 } 424 425 return 0; 426 } 427 428 static int qp_has_rq(struct ib_qp_init_attr *attr) 429 { 430 if (attr->qp_type == IB_QPT_XRC_INI || 431 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 432 attr->qp_type == MLX5_IB_QPT_REG_UMR || 433 !attr->cap.max_recv_wr) 434 return 0; 435 436 return 1; 437 } 438 439 static int first_med_uuar(void) 440 { 441 return 1; 442 } 443 444 static int next_uuar(int n) 445 { 446 n++; 447 448 while (((n % 4) & 2)) 449 n++; 450 451 return n; 452 } 453 454 static int num_med_uuar(struct mlx5_uuar_info *uuari) 455 { 456 int n; 457 458 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 459 uuari->num_low_latency_uuars - 1; 460 461 return n >= 0 ? n : 0; 462 } 463 464 static int max_uuari(struct mlx5_uuar_info *uuari) 465 { 466 return uuari->num_uars * 4; 467 } 468 469 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 470 { 471 int med; 472 int i; 473 int t; 474 475 med = num_med_uuar(uuari); 476 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 477 t++; 478 if (t == med) 479 return next_uuar(i); 480 } 481 482 return 0; 483 } 484 485 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 486 { 487 int i; 488 489 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 490 if (!test_bit(i, uuari->bitmap)) { 491 set_bit(i, uuari->bitmap); 492 uuari->count[i]++; 493 return i; 494 } 495 } 496 497 return -ENOMEM; 498 } 499 500 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 501 { 502 int minidx = first_med_uuar(); 503 int i; 504 505 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 506 if (uuari->count[i] < uuari->count[minidx]) 507 minidx = i; 508 } 509 510 uuari->count[minidx]++; 511 return minidx; 512 } 513 514 static int alloc_uuar(struct mlx5_uuar_info *uuari, 515 enum mlx5_ib_latency_class lat) 516 { 517 int uuarn = -EINVAL; 518 519 mutex_lock(&uuari->lock); 520 switch (lat) { 521 case MLX5_IB_LATENCY_CLASS_LOW: 522 uuarn = 0; 523 uuari->count[uuarn]++; 524 break; 525 526 case MLX5_IB_LATENCY_CLASS_MEDIUM: 527 if (uuari->ver < 2) 528 uuarn = -ENOMEM; 529 else 530 uuarn = alloc_med_class_uuar(uuari); 531 break; 532 533 case MLX5_IB_LATENCY_CLASS_HIGH: 534 if (uuari->ver < 2) 535 uuarn = -ENOMEM; 536 else 537 uuarn = alloc_high_class_uuar(uuari); 538 break; 539 540 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 541 uuarn = 2; 542 break; 543 } 544 mutex_unlock(&uuari->lock); 545 546 return uuarn; 547 } 548 549 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 550 { 551 clear_bit(uuarn, uuari->bitmap); 552 --uuari->count[uuarn]; 553 } 554 555 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 556 { 557 clear_bit(uuarn, uuari->bitmap); 558 --uuari->count[uuarn]; 559 } 560 561 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 562 { 563 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 564 int high_uuar = nuuars - uuari->num_low_latency_uuars; 565 566 mutex_lock(&uuari->lock); 567 if (uuarn == 0) { 568 --uuari->count[uuarn]; 569 goto out; 570 } 571 572 if (uuarn < high_uuar) { 573 free_med_class_uuar(uuari, uuarn); 574 goto out; 575 } 576 577 free_high_class_uuar(uuari, uuarn); 578 579 out: 580 mutex_unlock(&uuari->lock); 581 } 582 583 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 584 { 585 switch (state) { 586 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 587 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 588 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 589 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 590 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 591 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 592 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 593 default: return -1; 594 } 595 } 596 597 static int to_mlx5_st(enum ib_qp_type type) 598 { 599 switch (type) { 600 case IB_QPT_RC: return MLX5_QP_ST_RC; 601 case IB_QPT_UC: return MLX5_QP_ST_UC; 602 case IB_QPT_UD: return MLX5_QP_ST_UD; 603 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 604 case IB_QPT_XRC_INI: 605 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 606 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 607 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 608 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 609 case IB_QPT_RAW_PACKET: 610 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 611 case IB_QPT_MAX: 612 default: return -EINVAL; 613 } 614 } 615 616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 619 struct mlx5_ib_cq *recv_cq); 620 621 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 622 { 623 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 624 } 625 626 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 627 struct ib_pd *pd, 628 unsigned long addr, size_t size, 629 struct ib_umem **umem, 630 int *npages, int *page_shift, int *ncont, 631 u32 *offset) 632 { 633 int err; 634 635 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 636 if (IS_ERR(*umem)) { 637 mlx5_ib_dbg(dev, "umem_get failed\n"); 638 return PTR_ERR(*umem); 639 } 640 641 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL); 642 643 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 644 if (err) { 645 mlx5_ib_warn(dev, "bad offset\n"); 646 goto err_umem; 647 } 648 649 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 650 addr, size, *npages, *page_shift, *ncont, *offset); 651 652 return 0; 653 654 err_umem: 655 ib_umem_release(*umem); 656 *umem = NULL; 657 658 return err; 659 } 660 661 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq) 662 { 663 struct mlx5_ib_ucontext *context; 664 665 context = to_mucontext(pd->uobject->context); 666 mlx5_ib_db_unmap_user(context, &rwq->db); 667 if (rwq->umem) 668 ib_umem_release(rwq->umem); 669 } 670 671 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 672 struct mlx5_ib_rwq *rwq, 673 struct mlx5_ib_create_wq *ucmd) 674 { 675 struct mlx5_ib_ucontext *context; 676 int page_shift = 0; 677 int npages; 678 u32 offset = 0; 679 int ncont = 0; 680 int err; 681 682 if (!ucmd->buf_addr) 683 return -EINVAL; 684 685 context = to_mucontext(pd->uobject->context); 686 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 687 rwq->buf_size, 0, 0); 688 if (IS_ERR(rwq->umem)) { 689 mlx5_ib_dbg(dev, "umem_get failed\n"); 690 err = PTR_ERR(rwq->umem); 691 return err; 692 } 693 694 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift, 695 &ncont, NULL); 696 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 697 &rwq->rq_page_offset); 698 if (err) { 699 mlx5_ib_warn(dev, "bad offset\n"); 700 goto err_umem; 701 } 702 703 rwq->rq_num_pas = ncont; 704 rwq->page_shift = page_shift; 705 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 706 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 707 708 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 709 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 710 npages, page_shift, ncont, offset); 711 712 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 713 if (err) { 714 mlx5_ib_dbg(dev, "map failed\n"); 715 goto err_umem; 716 } 717 718 rwq->create_type = MLX5_WQ_USER; 719 return 0; 720 721 err_umem: 722 ib_umem_release(rwq->umem); 723 return err; 724 } 725 726 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 727 struct mlx5_ib_qp *qp, struct ib_udata *udata, 728 struct ib_qp_init_attr *attr, 729 u32 **in, 730 struct mlx5_ib_create_qp_resp *resp, int *inlen, 731 struct mlx5_ib_qp_base *base) 732 { 733 struct mlx5_ib_ucontext *context; 734 struct mlx5_ib_create_qp ucmd; 735 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 736 int page_shift = 0; 737 int uar_index; 738 int npages; 739 u32 offset = 0; 740 int uuarn; 741 int ncont = 0; 742 __be64 *pas; 743 void *qpc; 744 int err; 745 746 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 747 if (err) { 748 mlx5_ib_dbg(dev, "copy failed\n"); 749 return err; 750 } 751 752 context = to_mucontext(pd->uobject->context); 753 /* 754 * TBD: should come from the verbs when we have the API 755 */ 756 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 757 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 758 uuarn = MLX5_CROSS_CHANNEL_UUAR; 759 else { 760 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 761 if (uuarn < 0) { 762 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 763 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 764 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 765 if (uuarn < 0) { 766 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 767 mlx5_ib_dbg(dev, "reverting to high latency\n"); 768 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 769 if (uuarn < 0) { 770 mlx5_ib_warn(dev, "uuar allocation failed\n"); 771 return uuarn; 772 } 773 } 774 } 775 } 776 777 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 778 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 779 780 qp->rq.offset = 0; 781 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 782 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 783 784 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 785 if (err) 786 goto err_uuar; 787 788 if (ucmd.buf_addr && ubuffer->buf_size) { 789 ubuffer->buf_addr = ucmd.buf_addr; 790 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 791 ubuffer->buf_size, 792 &ubuffer->umem, &npages, &page_shift, 793 &ncont, &offset); 794 if (err) 795 goto err_uuar; 796 } else { 797 ubuffer->umem = NULL; 798 } 799 800 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 801 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 802 *in = mlx5_vzalloc(*inlen); 803 if (!*in) { 804 err = -ENOMEM; 805 goto err_umem; 806 } 807 808 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 809 if (ubuffer->umem) 810 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 811 812 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 813 814 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 815 MLX5_SET(qpc, qpc, page_offset, offset); 816 817 MLX5_SET(qpc, qpc, uar_page, uar_index); 818 resp->uuar_index = uuarn; 819 qp->uuarn = uuarn; 820 821 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 822 if (err) { 823 mlx5_ib_dbg(dev, "map failed\n"); 824 goto err_free; 825 } 826 827 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 828 if (err) { 829 mlx5_ib_dbg(dev, "copy failed\n"); 830 goto err_unmap; 831 } 832 qp->create_type = MLX5_QP_USER; 833 834 return 0; 835 836 err_unmap: 837 mlx5_ib_db_unmap_user(context, &qp->db); 838 839 err_free: 840 kvfree(*in); 841 842 err_umem: 843 if (ubuffer->umem) 844 ib_umem_release(ubuffer->umem); 845 846 err_uuar: 847 free_uuar(&context->uuari, uuarn); 848 return err; 849 } 850 851 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp, 852 struct mlx5_ib_qp_base *base) 853 { 854 struct mlx5_ib_ucontext *context; 855 856 context = to_mucontext(pd->uobject->context); 857 mlx5_ib_db_unmap_user(context, &qp->db); 858 if (base->ubuffer.umem) 859 ib_umem_release(base->ubuffer.umem); 860 free_uuar(&context->uuari, qp->uuarn); 861 } 862 863 static int create_kernel_qp(struct mlx5_ib_dev *dev, 864 struct ib_qp_init_attr *init_attr, 865 struct mlx5_ib_qp *qp, 866 u32 **in, int *inlen, 867 struct mlx5_ib_qp_base *base) 868 { 869 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 870 struct mlx5_uuar_info *uuari; 871 int uar_index; 872 void *qpc; 873 int uuarn; 874 int err; 875 876 uuari = &dev->mdev->priv.uuari; 877 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 878 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 879 IB_QP_CREATE_IPOIB_UD_LSO | 880 mlx5_ib_create_qp_sqpn_qp1())) 881 return -EINVAL; 882 883 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 884 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 885 886 uuarn = alloc_uuar(uuari, lc); 887 if (uuarn < 0) { 888 mlx5_ib_dbg(dev, "\n"); 889 return -ENOMEM; 890 } 891 892 qp->bf = &uuari->bfs[uuarn]; 893 uar_index = qp->bf->uar->index; 894 895 err = calc_sq_size(dev, init_attr, qp); 896 if (err < 0) { 897 mlx5_ib_dbg(dev, "err %d\n", err); 898 goto err_uuar; 899 } 900 901 qp->rq.offset = 0; 902 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 903 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 904 905 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 906 if (err) { 907 mlx5_ib_dbg(dev, "err %d\n", err); 908 goto err_uuar; 909 } 910 911 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 912 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 913 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 914 *in = mlx5_vzalloc(*inlen); 915 if (!*in) { 916 err = -ENOMEM; 917 goto err_buf; 918 } 919 920 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 921 MLX5_SET(qpc, qpc, uar_page, uar_index); 922 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 923 924 /* Set "fast registration enabled" for all kernel QPs */ 925 MLX5_SET(qpc, qpc, fre, 1); 926 MLX5_SET(qpc, qpc, rlky, 1); 927 928 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 929 MLX5_SET(qpc, qpc, deth_sqpn, 1); 930 qp->flags |= MLX5_IB_QP_SQPN_QP1; 931 } 932 933 mlx5_fill_page_array(&qp->buf, 934 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 935 936 err = mlx5_db_alloc(dev->mdev, &qp->db); 937 if (err) { 938 mlx5_ib_dbg(dev, "err %d\n", err); 939 goto err_free; 940 } 941 942 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 943 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 944 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 945 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 946 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 947 948 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 949 !qp->sq.w_list || !qp->sq.wqe_head) { 950 err = -ENOMEM; 951 goto err_wrid; 952 } 953 qp->create_type = MLX5_QP_KERNEL; 954 955 return 0; 956 957 err_wrid: 958 mlx5_db_free(dev->mdev, &qp->db); 959 kfree(qp->sq.wqe_head); 960 kfree(qp->sq.w_list); 961 kfree(qp->sq.wrid); 962 kfree(qp->sq.wr_data); 963 kfree(qp->rq.wrid); 964 965 err_free: 966 kvfree(*in); 967 968 err_buf: 969 mlx5_buf_free(dev->mdev, &qp->buf); 970 971 err_uuar: 972 free_uuar(&dev->mdev->priv.uuari, uuarn); 973 return err; 974 } 975 976 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 977 { 978 mlx5_db_free(dev->mdev, &qp->db); 979 kfree(qp->sq.wqe_head); 980 kfree(qp->sq.w_list); 981 kfree(qp->sq.wrid); 982 kfree(qp->sq.wr_data); 983 kfree(qp->rq.wrid); 984 mlx5_buf_free(dev->mdev, &qp->buf); 985 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 986 } 987 988 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 989 { 990 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 991 (attr->qp_type == IB_QPT_XRC_INI)) 992 return MLX5_SRQ_RQ; 993 else if (!qp->has_rq) 994 return MLX5_ZERO_LEN_RQ; 995 else 996 return MLX5_NON_ZERO_RQ; 997 } 998 999 static int is_connected(enum ib_qp_type qp_type) 1000 { 1001 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1002 return 1; 1003 1004 return 0; 1005 } 1006 1007 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1008 struct mlx5_ib_sq *sq, u32 tdn) 1009 { 1010 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1011 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1012 1013 MLX5_SET(tisc, tisc, transport_domain, tdn); 1014 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1015 } 1016 1017 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1018 struct mlx5_ib_sq *sq) 1019 { 1020 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1021 } 1022 1023 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1024 struct mlx5_ib_sq *sq, void *qpin, 1025 struct ib_pd *pd) 1026 { 1027 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1028 __be64 *pas; 1029 void *in; 1030 void *sqc; 1031 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1032 void *wq; 1033 int inlen; 1034 int err; 1035 int page_shift = 0; 1036 int npages; 1037 int ncont = 0; 1038 u32 offset = 0; 1039 1040 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1041 &sq->ubuffer.umem, &npages, &page_shift, 1042 &ncont, &offset); 1043 if (err) 1044 return err; 1045 1046 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1047 in = mlx5_vzalloc(inlen); 1048 if (!in) { 1049 err = -ENOMEM; 1050 goto err_umem; 1051 } 1052 1053 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1054 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1055 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1056 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1057 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1058 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1059 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1060 1061 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1062 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1063 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1064 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1065 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1066 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1067 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1068 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1069 MLX5_SET(wq, wq, page_offset, offset); 1070 1071 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1072 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1073 1074 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1075 1076 kvfree(in); 1077 1078 if (err) 1079 goto err_umem; 1080 1081 return 0; 1082 1083 err_umem: 1084 ib_umem_release(sq->ubuffer.umem); 1085 sq->ubuffer.umem = NULL; 1086 1087 return err; 1088 } 1089 1090 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1091 struct mlx5_ib_sq *sq) 1092 { 1093 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1094 ib_umem_release(sq->ubuffer.umem); 1095 } 1096 1097 static int get_rq_pas_size(void *qpc) 1098 { 1099 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1100 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1101 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1102 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1103 u32 po_quanta = 1 << (log_page_size - 6); 1104 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1105 u32 page_size = 1 << log_page_size; 1106 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1107 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1108 1109 return rq_num_pas * sizeof(u64); 1110 } 1111 1112 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1113 struct mlx5_ib_rq *rq, void *qpin) 1114 { 1115 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1116 __be64 *pas; 1117 __be64 *qp_pas; 1118 void *in; 1119 void *rqc; 1120 void *wq; 1121 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1122 int inlen; 1123 int err; 1124 u32 rq_pas_size = get_rq_pas_size(qpc); 1125 1126 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1127 in = mlx5_vzalloc(inlen); 1128 if (!in) 1129 return -ENOMEM; 1130 1131 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1132 MLX5_SET(rqc, rqc, vsd, 1); 1133 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1134 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1135 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1136 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1137 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1138 1139 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1140 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1141 1142 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1143 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1144 MLX5_SET(wq, wq, end_padding_mode, 1145 MLX5_GET(qpc, qpc, end_padding_mode)); 1146 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1147 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1148 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1149 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1150 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1151 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1152 1153 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1154 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1155 memcpy(pas, qp_pas, rq_pas_size); 1156 1157 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1158 1159 kvfree(in); 1160 1161 return err; 1162 } 1163 1164 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1165 struct mlx5_ib_rq *rq) 1166 { 1167 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1168 } 1169 1170 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1171 struct mlx5_ib_rq *rq, u32 tdn) 1172 { 1173 u32 *in; 1174 void *tirc; 1175 int inlen; 1176 int err; 1177 1178 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1179 in = mlx5_vzalloc(inlen); 1180 if (!in) 1181 return -ENOMEM; 1182 1183 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1184 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1185 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1186 MLX5_SET(tirc, tirc, transport_domain, tdn); 1187 1188 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1189 1190 kvfree(in); 1191 1192 return err; 1193 } 1194 1195 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1196 struct mlx5_ib_rq *rq) 1197 { 1198 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1199 } 1200 1201 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1202 u32 *in, 1203 struct ib_pd *pd) 1204 { 1205 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1206 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1207 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1208 struct ib_uobject *uobj = pd->uobject; 1209 struct ib_ucontext *ucontext = uobj->context; 1210 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1211 int err; 1212 u32 tdn = mucontext->tdn; 1213 1214 if (qp->sq.wqe_cnt) { 1215 err = create_raw_packet_qp_tis(dev, sq, tdn); 1216 if (err) 1217 return err; 1218 1219 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1220 if (err) 1221 goto err_destroy_tis; 1222 1223 sq->base.container_mibqp = qp; 1224 } 1225 1226 if (qp->rq.wqe_cnt) { 1227 rq->base.container_mibqp = qp; 1228 1229 err = create_raw_packet_qp_rq(dev, rq, in); 1230 if (err) 1231 goto err_destroy_sq; 1232 1233 1234 err = create_raw_packet_qp_tir(dev, rq, tdn); 1235 if (err) 1236 goto err_destroy_rq; 1237 } 1238 1239 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1240 rq->base.mqp.qpn; 1241 1242 return 0; 1243 1244 err_destroy_rq: 1245 destroy_raw_packet_qp_rq(dev, rq); 1246 err_destroy_sq: 1247 if (!qp->sq.wqe_cnt) 1248 return err; 1249 destroy_raw_packet_qp_sq(dev, sq); 1250 err_destroy_tis: 1251 destroy_raw_packet_qp_tis(dev, sq); 1252 1253 return err; 1254 } 1255 1256 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1257 struct mlx5_ib_qp *qp) 1258 { 1259 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1260 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1261 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1262 1263 if (qp->rq.wqe_cnt) { 1264 destroy_raw_packet_qp_tir(dev, rq); 1265 destroy_raw_packet_qp_rq(dev, rq); 1266 } 1267 1268 if (qp->sq.wqe_cnt) { 1269 destroy_raw_packet_qp_sq(dev, sq); 1270 destroy_raw_packet_qp_tis(dev, sq); 1271 } 1272 } 1273 1274 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1275 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1276 { 1277 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1278 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1279 1280 sq->sq = &qp->sq; 1281 rq->rq = &qp->rq; 1282 sq->doorbell = &qp->db; 1283 rq->doorbell = &qp->db; 1284 } 1285 1286 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1287 { 1288 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1289 } 1290 1291 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1292 struct ib_pd *pd, 1293 struct ib_qp_init_attr *init_attr, 1294 struct ib_udata *udata) 1295 { 1296 struct ib_uobject *uobj = pd->uobject; 1297 struct ib_ucontext *ucontext = uobj->context; 1298 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1299 struct mlx5_ib_create_qp_resp resp = {}; 1300 int inlen; 1301 int err; 1302 u32 *in; 1303 void *tirc; 1304 void *hfso; 1305 u32 selected_fields = 0; 1306 size_t min_resp_len; 1307 u32 tdn = mucontext->tdn; 1308 struct mlx5_ib_create_qp_rss ucmd = {}; 1309 size_t required_cmd_sz; 1310 1311 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1312 return -EOPNOTSUPP; 1313 1314 if (init_attr->create_flags || init_attr->send_cq) 1315 return -EINVAL; 1316 1317 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index); 1318 if (udata->outlen < min_resp_len) 1319 return -EINVAL; 1320 1321 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1322 if (udata->inlen < required_cmd_sz) { 1323 mlx5_ib_dbg(dev, "invalid inlen\n"); 1324 return -EINVAL; 1325 } 1326 1327 if (udata->inlen > sizeof(ucmd) && 1328 !ib_is_udata_cleared(udata, sizeof(ucmd), 1329 udata->inlen - sizeof(ucmd))) { 1330 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1331 return -EOPNOTSUPP; 1332 } 1333 1334 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1335 mlx5_ib_dbg(dev, "copy failed\n"); 1336 return -EFAULT; 1337 } 1338 1339 if (ucmd.comp_mask) { 1340 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1341 return -EOPNOTSUPP; 1342 } 1343 1344 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1345 mlx5_ib_dbg(dev, "invalid reserved\n"); 1346 return -EOPNOTSUPP; 1347 } 1348 1349 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1350 if (err) { 1351 mlx5_ib_dbg(dev, "copy failed\n"); 1352 return -EINVAL; 1353 } 1354 1355 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1356 in = mlx5_vzalloc(inlen); 1357 if (!in) 1358 return -ENOMEM; 1359 1360 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1361 MLX5_SET(tirc, tirc, disp_type, 1362 MLX5_TIRC_DISP_TYPE_INDIRECT); 1363 MLX5_SET(tirc, tirc, indirect_table, 1364 init_attr->rwq_ind_tbl->ind_tbl_num); 1365 MLX5_SET(tirc, tirc, transport_domain, tdn); 1366 1367 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1368 switch (ucmd.rx_hash_function) { 1369 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1370 { 1371 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1372 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1373 1374 if (len != ucmd.rx_key_len) { 1375 err = -EINVAL; 1376 goto err; 1377 } 1378 1379 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1380 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1381 memcpy(rss_key, ucmd.rx_hash_key, len); 1382 break; 1383 } 1384 default: 1385 err = -EOPNOTSUPP; 1386 goto err; 1387 } 1388 1389 if (!ucmd.rx_hash_fields_mask) { 1390 /* special case when this TIR serves as steering entry without hashing */ 1391 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1392 goto create_tir; 1393 err = -EINVAL; 1394 goto err; 1395 } 1396 1397 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1398 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1399 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1400 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1401 err = -EINVAL; 1402 goto err; 1403 } 1404 1405 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1406 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1407 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1409 MLX5_L3_PROT_TYPE_IPV4); 1410 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1411 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1413 MLX5_L3_PROT_TYPE_IPV6); 1414 1415 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1416 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1417 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1418 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1419 err = -EINVAL; 1420 goto err; 1421 } 1422 1423 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1424 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1425 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1426 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1427 MLX5_L4_PROT_TYPE_TCP); 1428 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1429 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1430 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1431 MLX5_L4_PROT_TYPE_UDP); 1432 1433 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1435 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1436 1437 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1439 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1440 1441 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1442 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1443 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1444 1445 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1447 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1448 1449 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1450 1451 create_tir: 1452 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1453 1454 if (err) 1455 goto err; 1456 1457 kvfree(in); 1458 /* qpn is reserved for that QP */ 1459 qp->trans_qp.base.mqp.qpn = 0; 1460 qp->flags |= MLX5_IB_QP_RSS; 1461 return 0; 1462 1463 err: 1464 kvfree(in); 1465 return err; 1466 } 1467 1468 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1469 struct ib_qp_init_attr *init_attr, 1470 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1471 { 1472 struct mlx5_ib_resources *devr = &dev->devr; 1473 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1474 struct mlx5_core_dev *mdev = dev->mdev; 1475 struct mlx5_ib_create_qp_resp resp; 1476 struct mlx5_ib_cq *send_cq; 1477 struct mlx5_ib_cq *recv_cq; 1478 unsigned long flags; 1479 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1480 struct mlx5_ib_create_qp ucmd; 1481 struct mlx5_ib_qp_base *base; 1482 void *qpc; 1483 u32 *in; 1484 int err; 1485 1486 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1487 &qp->raw_packet_qp.rq.base : 1488 &qp->trans_qp.base; 1489 1490 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1491 mlx5_ib_odp_create_qp(qp); 1492 1493 mutex_init(&qp->mutex); 1494 spin_lock_init(&qp->sq.lock); 1495 spin_lock_init(&qp->rq.lock); 1496 1497 if (init_attr->rwq_ind_tbl) { 1498 if (!udata) 1499 return -ENOSYS; 1500 1501 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1502 return err; 1503 } 1504 1505 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1506 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1507 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1508 return -EINVAL; 1509 } else { 1510 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1511 } 1512 } 1513 1514 if (init_attr->create_flags & 1515 (IB_QP_CREATE_CROSS_CHANNEL | 1516 IB_QP_CREATE_MANAGED_SEND | 1517 IB_QP_CREATE_MANAGED_RECV)) { 1518 if (!MLX5_CAP_GEN(mdev, cd)) { 1519 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1520 return -EINVAL; 1521 } 1522 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1523 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1524 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1525 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1526 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1527 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1528 } 1529 1530 if (init_attr->qp_type == IB_QPT_UD && 1531 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1532 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1533 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1534 return -EOPNOTSUPP; 1535 } 1536 1537 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1538 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1539 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1540 return -EOPNOTSUPP; 1541 } 1542 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1543 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1544 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1545 return -EOPNOTSUPP; 1546 } 1547 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1548 } 1549 1550 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1551 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1552 1553 if (pd && pd->uobject) { 1554 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1555 mlx5_ib_dbg(dev, "copy failed\n"); 1556 return -EFAULT; 1557 } 1558 1559 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1560 &ucmd, udata->inlen, &uidx); 1561 if (err) 1562 return err; 1563 1564 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1565 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1566 } else { 1567 qp->wq_sig = !!wq_signature; 1568 } 1569 1570 qp->has_rq = qp_has_rq(init_attr); 1571 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1572 qp, (pd && pd->uobject) ? &ucmd : NULL); 1573 if (err) { 1574 mlx5_ib_dbg(dev, "err %d\n", err); 1575 return err; 1576 } 1577 1578 if (pd) { 1579 if (pd->uobject) { 1580 __u32 max_wqes = 1581 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1582 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1583 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1584 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1585 mlx5_ib_dbg(dev, "invalid rq params\n"); 1586 return -EINVAL; 1587 } 1588 if (ucmd.sq_wqe_count > max_wqes) { 1589 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1590 ucmd.sq_wqe_count, max_wqes); 1591 return -EINVAL; 1592 } 1593 if (init_attr->create_flags & 1594 mlx5_ib_create_qp_sqpn_qp1()) { 1595 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1596 return -EINVAL; 1597 } 1598 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1599 &resp, &inlen, base); 1600 if (err) 1601 mlx5_ib_dbg(dev, "err %d\n", err); 1602 } else { 1603 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1604 base); 1605 if (err) 1606 mlx5_ib_dbg(dev, "err %d\n", err); 1607 } 1608 1609 if (err) 1610 return err; 1611 } else { 1612 in = mlx5_vzalloc(inlen); 1613 if (!in) 1614 return -ENOMEM; 1615 1616 qp->create_type = MLX5_QP_EMPTY; 1617 } 1618 1619 if (is_sqp(init_attr->qp_type)) 1620 qp->port = init_attr->port_num; 1621 1622 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1623 1624 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1625 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1626 1627 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1628 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1629 else 1630 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1631 1632 1633 if (qp->wq_sig) 1634 MLX5_SET(qpc, qpc, wq_signature, 1); 1635 1636 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1637 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1638 1639 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1640 MLX5_SET(qpc, qpc, cd_master, 1); 1641 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1642 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1643 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1644 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1645 1646 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1647 int rcqe_sz; 1648 int scqe_sz; 1649 1650 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1651 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1652 1653 if (rcqe_sz == 128) 1654 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1655 else 1656 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1657 1658 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1659 if (scqe_sz == 128) 1660 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1661 else 1662 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1663 } 1664 } 1665 1666 if (qp->rq.wqe_cnt) { 1667 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1668 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1669 } 1670 1671 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1672 1673 if (qp->sq.wqe_cnt) 1674 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1675 else 1676 MLX5_SET(qpc, qpc, no_sq, 1); 1677 1678 /* Set default resources */ 1679 switch (init_attr->qp_type) { 1680 case IB_QPT_XRC_TGT: 1681 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1682 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1683 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1684 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1685 break; 1686 case IB_QPT_XRC_INI: 1687 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1688 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1689 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1690 break; 1691 default: 1692 if (init_attr->srq) { 1693 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1694 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1695 } else { 1696 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1697 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1698 } 1699 } 1700 1701 if (init_attr->send_cq) 1702 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1703 1704 if (init_attr->recv_cq) 1705 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1706 1707 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1708 1709 /* 0xffffff means we ask to work with cqe version 0 */ 1710 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1711 MLX5_SET(qpc, qpc, user_index, uidx); 1712 1713 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1714 if (init_attr->qp_type == IB_QPT_UD && 1715 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1716 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1717 qp->flags |= MLX5_IB_QP_LSO; 1718 } 1719 1720 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1721 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1722 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1723 err = create_raw_packet_qp(dev, qp, in, pd); 1724 } else { 1725 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1726 } 1727 1728 if (err) { 1729 mlx5_ib_dbg(dev, "create qp failed\n"); 1730 goto err_create; 1731 } 1732 1733 kvfree(in); 1734 1735 base->container_mibqp = qp; 1736 base->mqp.event = mlx5_ib_qp_event; 1737 1738 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1739 &send_cq, &recv_cq); 1740 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1741 mlx5_ib_lock_cqs(send_cq, recv_cq); 1742 /* Maintain device to QPs access, needed for further handling via reset 1743 * flow 1744 */ 1745 list_add_tail(&qp->qps_list, &dev->qp_list); 1746 /* Maintain CQ to QPs access, needed for further handling via reset flow 1747 */ 1748 if (send_cq) 1749 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1750 if (recv_cq) 1751 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1752 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1753 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1754 1755 return 0; 1756 1757 err_create: 1758 if (qp->create_type == MLX5_QP_USER) 1759 destroy_qp_user(pd, qp, base); 1760 else if (qp->create_type == MLX5_QP_KERNEL) 1761 destroy_qp_kernel(dev, qp); 1762 1763 kvfree(in); 1764 return err; 1765 } 1766 1767 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1768 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1769 { 1770 if (send_cq) { 1771 if (recv_cq) { 1772 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1773 spin_lock(&send_cq->lock); 1774 spin_lock_nested(&recv_cq->lock, 1775 SINGLE_DEPTH_NESTING); 1776 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1777 spin_lock(&send_cq->lock); 1778 __acquire(&recv_cq->lock); 1779 } else { 1780 spin_lock(&recv_cq->lock); 1781 spin_lock_nested(&send_cq->lock, 1782 SINGLE_DEPTH_NESTING); 1783 } 1784 } else { 1785 spin_lock(&send_cq->lock); 1786 __acquire(&recv_cq->lock); 1787 } 1788 } else if (recv_cq) { 1789 spin_lock(&recv_cq->lock); 1790 __acquire(&send_cq->lock); 1791 } else { 1792 __acquire(&send_cq->lock); 1793 __acquire(&recv_cq->lock); 1794 } 1795 } 1796 1797 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1798 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1799 { 1800 if (send_cq) { 1801 if (recv_cq) { 1802 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1803 spin_unlock(&recv_cq->lock); 1804 spin_unlock(&send_cq->lock); 1805 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1806 __release(&recv_cq->lock); 1807 spin_unlock(&send_cq->lock); 1808 } else { 1809 spin_unlock(&send_cq->lock); 1810 spin_unlock(&recv_cq->lock); 1811 } 1812 } else { 1813 __release(&recv_cq->lock); 1814 spin_unlock(&send_cq->lock); 1815 } 1816 } else if (recv_cq) { 1817 __release(&send_cq->lock); 1818 spin_unlock(&recv_cq->lock); 1819 } else { 1820 __release(&recv_cq->lock); 1821 __release(&send_cq->lock); 1822 } 1823 } 1824 1825 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1826 { 1827 return to_mpd(qp->ibqp.pd); 1828 } 1829 1830 static void get_cqs(enum ib_qp_type qp_type, 1831 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1832 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1833 { 1834 switch (qp_type) { 1835 case IB_QPT_XRC_TGT: 1836 *send_cq = NULL; 1837 *recv_cq = NULL; 1838 break; 1839 case MLX5_IB_QPT_REG_UMR: 1840 case IB_QPT_XRC_INI: 1841 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1842 *recv_cq = NULL; 1843 break; 1844 1845 case IB_QPT_SMI: 1846 case MLX5_IB_QPT_HW_GSI: 1847 case IB_QPT_RC: 1848 case IB_QPT_UC: 1849 case IB_QPT_UD: 1850 case IB_QPT_RAW_IPV6: 1851 case IB_QPT_RAW_ETHERTYPE: 1852 case IB_QPT_RAW_PACKET: 1853 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1854 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1855 break; 1856 1857 case IB_QPT_MAX: 1858 default: 1859 *send_cq = NULL; 1860 *recv_cq = NULL; 1861 break; 1862 } 1863 } 1864 1865 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1866 u16 operation); 1867 1868 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1869 { 1870 struct mlx5_ib_cq *send_cq, *recv_cq; 1871 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1872 unsigned long flags; 1873 int err; 1874 1875 if (qp->ibqp.rwq_ind_tbl) { 1876 destroy_rss_raw_qp_tir(dev, qp); 1877 return; 1878 } 1879 1880 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1881 &qp->raw_packet_qp.rq.base : 1882 &qp->trans_qp.base; 1883 1884 if (qp->state != IB_QPS_RESET) { 1885 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1886 mlx5_ib_qp_disable_pagefaults(qp); 1887 err = mlx5_core_qp_modify(dev->mdev, 1888 MLX5_CMD_OP_2RST_QP, 0, 1889 NULL, &base->mqp); 1890 } else { 1891 err = modify_raw_packet_qp(dev, qp, 1892 MLX5_CMD_OP_2RST_QP); 1893 } 1894 if (err) 1895 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1896 base->mqp.qpn); 1897 } 1898 1899 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 1900 &send_cq, &recv_cq); 1901 1902 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1903 mlx5_ib_lock_cqs(send_cq, recv_cq); 1904 /* del from lists under both locks above to protect reset flow paths */ 1905 list_del(&qp->qps_list); 1906 if (send_cq) 1907 list_del(&qp->cq_send_list); 1908 1909 if (recv_cq) 1910 list_del(&qp->cq_recv_list); 1911 1912 if (qp->create_type == MLX5_QP_KERNEL) { 1913 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1914 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1915 if (send_cq != recv_cq) 1916 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1917 NULL); 1918 } 1919 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1920 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1921 1922 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1923 destroy_raw_packet_qp(dev, qp); 1924 } else { 1925 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1926 if (err) 1927 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1928 base->mqp.qpn); 1929 } 1930 1931 if (qp->create_type == MLX5_QP_KERNEL) 1932 destroy_qp_kernel(dev, qp); 1933 else if (qp->create_type == MLX5_QP_USER) 1934 destroy_qp_user(&get_pd(qp)->ibpd, qp, base); 1935 } 1936 1937 static const char *ib_qp_type_str(enum ib_qp_type type) 1938 { 1939 switch (type) { 1940 case IB_QPT_SMI: 1941 return "IB_QPT_SMI"; 1942 case IB_QPT_GSI: 1943 return "IB_QPT_GSI"; 1944 case IB_QPT_RC: 1945 return "IB_QPT_RC"; 1946 case IB_QPT_UC: 1947 return "IB_QPT_UC"; 1948 case IB_QPT_UD: 1949 return "IB_QPT_UD"; 1950 case IB_QPT_RAW_IPV6: 1951 return "IB_QPT_RAW_IPV6"; 1952 case IB_QPT_RAW_ETHERTYPE: 1953 return "IB_QPT_RAW_ETHERTYPE"; 1954 case IB_QPT_XRC_INI: 1955 return "IB_QPT_XRC_INI"; 1956 case IB_QPT_XRC_TGT: 1957 return "IB_QPT_XRC_TGT"; 1958 case IB_QPT_RAW_PACKET: 1959 return "IB_QPT_RAW_PACKET"; 1960 case MLX5_IB_QPT_REG_UMR: 1961 return "MLX5_IB_QPT_REG_UMR"; 1962 case IB_QPT_MAX: 1963 default: 1964 return "Invalid QP type"; 1965 } 1966 } 1967 1968 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1969 struct ib_qp_init_attr *init_attr, 1970 struct ib_udata *udata) 1971 { 1972 struct mlx5_ib_dev *dev; 1973 struct mlx5_ib_qp *qp; 1974 u16 xrcdn = 0; 1975 int err; 1976 1977 if (pd) { 1978 dev = to_mdev(pd->device); 1979 1980 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1981 if (!pd->uobject) { 1982 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 1983 return ERR_PTR(-EINVAL); 1984 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 1985 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 1986 return ERR_PTR(-EINVAL); 1987 } 1988 } 1989 } else { 1990 /* being cautious here */ 1991 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1992 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1993 pr_warn("%s: no PD for transport %s\n", __func__, 1994 ib_qp_type_str(init_attr->qp_type)); 1995 return ERR_PTR(-EINVAL); 1996 } 1997 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1998 } 1999 2000 switch (init_attr->qp_type) { 2001 case IB_QPT_XRC_TGT: 2002 case IB_QPT_XRC_INI: 2003 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2004 mlx5_ib_dbg(dev, "XRC not supported\n"); 2005 return ERR_PTR(-ENOSYS); 2006 } 2007 init_attr->recv_cq = NULL; 2008 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2009 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2010 init_attr->send_cq = NULL; 2011 } 2012 2013 /* fall through */ 2014 case IB_QPT_RAW_PACKET: 2015 case IB_QPT_RC: 2016 case IB_QPT_UC: 2017 case IB_QPT_UD: 2018 case IB_QPT_SMI: 2019 case MLX5_IB_QPT_HW_GSI: 2020 case MLX5_IB_QPT_REG_UMR: 2021 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2022 if (!qp) 2023 return ERR_PTR(-ENOMEM); 2024 2025 err = create_qp_common(dev, pd, init_attr, udata, qp); 2026 if (err) { 2027 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2028 kfree(qp); 2029 return ERR_PTR(err); 2030 } 2031 2032 if (is_qp0(init_attr->qp_type)) 2033 qp->ibqp.qp_num = 0; 2034 else if (is_qp1(init_attr->qp_type)) 2035 qp->ibqp.qp_num = 1; 2036 else 2037 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2038 2039 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2040 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2041 to_mcq(init_attr->recv_cq)->mcq.cqn, 2042 to_mcq(init_attr->send_cq)->mcq.cqn); 2043 2044 qp->trans_qp.xrcdn = xrcdn; 2045 2046 break; 2047 2048 case IB_QPT_GSI: 2049 return mlx5_ib_gsi_create_qp(pd, init_attr); 2050 2051 case IB_QPT_RAW_IPV6: 2052 case IB_QPT_RAW_ETHERTYPE: 2053 case IB_QPT_MAX: 2054 default: 2055 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2056 init_attr->qp_type); 2057 /* Don't support raw QPs */ 2058 return ERR_PTR(-EINVAL); 2059 } 2060 2061 return &qp->ibqp; 2062 } 2063 2064 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2065 { 2066 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2067 struct mlx5_ib_qp *mqp = to_mqp(qp); 2068 2069 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2070 return mlx5_ib_gsi_destroy_qp(qp); 2071 2072 destroy_qp_common(dev, mqp); 2073 2074 kfree(mqp); 2075 2076 return 0; 2077 } 2078 2079 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2080 int attr_mask) 2081 { 2082 u32 hw_access_flags = 0; 2083 u8 dest_rd_atomic; 2084 u32 access_flags; 2085 2086 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2087 dest_rd_atomic = attr->max_dest_rd_atomic; 2088 else 2089 dest_rd_atomic = qp->trans_qp.resp_depth; 2090 2091 if (attr_mask & IB_QP_ACCESS_FLAGS) 2092 access_flags = attr->qp_access_flags; 2093 else 2094 access_flags = qp->trans_qp.atomic_rd_en; 2095 2096 if (!dest_rd_atomic) 2097 access_flags &= IB_ACCESS_REMOTE_WRITE; 2098 2099 if (access_flags & IB_ACCESS_REMOTE_READ) 2100 hw_access_flags |= MLX5_QP_BIT_RRE; 2101 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2102 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2103 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2104 hw_access_flags |= MLX5_QP_BIT_RWE; 2105 2106 return cpu_to_be32(hw_access_flags); 2107 } 2108 2109 enum { 2110 MLX5_PATH_FLAG_FL = 1 << 0, 2111 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2112 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2113 }; 2114 2115 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2116 { 2117 if (rate == IB_RATE_PORT_CURRENT) { 2118 return 0; 2119 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2120 return -EINVAL; 2121 } else { 2122 while (rate != IB_RATE_2_5_GBPS && 2123 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2124 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2125 --rate; 2126 } 2127 2128 return rate + MLX5_STAT_RATE_OFFSET; 2129 } 2130 2131 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2132 struct mlx5_ib_sq *sq, u8 sl) 2133 { 2134 void *in; 2135 void *tisc; 2136 int inlen; 2137 int err; 2138 2139 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2140 in = mlx5_vzalloc(inlen); 2141 if (!in) 2142 return -ENOMEM; 2143 2144 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2145 2146 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2147 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2148 2149 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2150 2151 kvfree(in); 2152 2153 return err; 2154 } 2155 2156 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2157 const struct ib_ah_attr *ah, 2158 struct mlx5_qp_path *path, u8 port, int attr_mask, 2159 u32 path_flags, const struct ib_qp_attr *attr, 2160 bool alt) 2161 { 2162 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2163 int err; 2164 2165 if (attr_mask & IB_QP_PKEY_INDEX) 2166 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2167 attr->pkey_index); 2168 2169 if (ah->ah_flags & IB_AH_GRH) { 2170 if (ah->grh.sgid_index >= 2171 dev->mdev->port_caps[port - 1].gid_table_len) { 2172 pr_err("sgid_index (%u) too large. max is %d\n", 2173 ah->grh.sgid_index, 2174 dev->mdev->port_caps[port - 1].gid_table_len); 2175 return -EINVAL; 2176 } 2177 } 2178 2179 if (ll == IB_LINK_LAYER_ETHERNET) { 2180 if (!(ah->ah_flags & IB_AH_GRH)) 2181 return -EINVAL; 2182 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2183 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2184 ah->grh.sgid_index); 2185 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2186 } else { 2187 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2188 path->fl_free_ar |= 2189 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2190 path->rlid = cpu_to_be16(ah->dlid); 2191 path->grh_mlid = ah->src_path_bits & 0x7f; 2192 if (ah->ah_flags & IB_AH_GRH) 2193 path->grh_mlid |= 1 << 7; 2194 path->dci_cfi_prio_sl = ah->sl & 0xf; 2195 } 2196 2197 if (ah->ah_flags & IB_AH_GRH) { 2198 path->mgid_index = ah->grh.sgid_index; 2199 path->hop_limit = ah->grh.hop_limit; 2200 path->tclass_flowlabel = 2201 cpu_to_be32((ah->grh.traffic_class << 20) | 2202 (ah->grh.flow_label)); 2203 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2204 } 2205 2206 err = ib_rate_to_mlx5(dev, ah->static_rate); 2207 if (err < 0) 2208 return err; 2209 path->static_rate = err; 2210 path->port = port; 2211 2212 if (attr_mask & IB_QP_TIMEOUT) 2213 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2214 2215 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2216 return modify_raw_packet_eth_prio(dev->mdev, 2217 &qp->raw_packet_qp.sq, 2218 ah->sl & 0xf); 2219 2220 return 0; 2221 } 2222 2223 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2224 [MLX5_QP_STATE_INIT] = { 2225 [MLX5_QP_STATE_INIT] = { 2226 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2227 MLX5_QP_OPTPAR_RAE | 2228 MLX5_QP_OPTPAR_RWE | 2229 MLX5_QP_OPTPAR_PKEY_INDEX | 2230 MLX5_QP_OPTPAR_PRI_PORT, 2231 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2232 MLX5_QP_OPTPAR_PKEY_INDEX | 2233 MLX5_QP_OPTPAR_PRI_PORT, 2234 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2235 MLX5_QP_OPTPAR_Q_KEY | 2236 MLX5_QP_OPTPAR_PRI_PORT, 2237 }, 2238 [MLX5_QP_STATE_RTR] = { 2239 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2240 MLX5_QP_OPTPAR_RRE | 2241 MLX5_QP_OPTPAR_RAE | 2242 MLX5_QP_OPTPAR_RWE | 2243 MLX5_QP_OPTPAR_PKEY_INDEX, 2244 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2245 MLX5_QP_OPTPAR_RWE | 2246 MLX5_QP_OPTPAR_PKEY_INDEX, 2247 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2248 MLX5_QP_OPTPAR_Q_KEY, 2249 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2250 MLX5_QP_OPTPAR_Q_KEY, 2251 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2252 MLX5_QP_OPTPAR_RRE | 2253 MLX5_QP_OPTPAR_RAE | 2254 MLX5_QP_OPTPAR_RWE | 2255 MLX5_QP_OPTPAR_PKEY_INDEX, 2256 }, 2257 }, 2258 [MLX5_QP_STATE_RTR] = { 2259 [MLX5_QP_STATE_RTS] = { 2260 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2261 MLX5_QP_OPTPAR_RRE | 2262 MLX5_QP_OPTPAR_RAE | 2263 MLX5_QP_OPTPAR_RWE | 2264 MLX5_QP_OPTPAR_PM_STATE | 2265 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2266 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2267 MLX5_QP_OPTPAR_RWE | 2268 MLX5_QP_OPTPAR_PM_STATE, 2269 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2270 }, 2271 }, 2272 [MLX5_QP_STATE_RTS] = { 2273 [MLX5_QP_STATE_RTS] = { 2274 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2275 MLX5_QP_OPTPAR_RAE | 2276 MLX5_QP_OPTPAR_RWE | 2277 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2278 MLX5_QP_OPTPAR_PM_STATE | 2279 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2280 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2281 MLX5_QP_OPTPAR_PM_STATE | 2282 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2283 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2284 MLX5_QP_OPTPAR_SRQN | 2285 MLX5_QP_OPTPAR_CQN_RCV, 2286 }, 2287 }, 2288 [MLX5_QP_STATE_SQER] = { 2289 [MLX5_QP_STATE_RTS] = { 2290 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2291 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2292 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2293 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2294 MLX5_QP_OPTPAR_RWE | 2295 MLX5_QP_OPTPAR_RAE | 2296 MLX5_QP_OPTPAR_RRE, 2297 }, 2298 }, 2299 }; 2300 2301 static int ib_nr_to_mlx5_nr(int ib_mask) 2302 { 2303 switch (ib_mask) { 2304 case IB_QP_STATE: 2305 return 0; 2306 case IB_QP_CUR_STATE: 2307 return 0; 2308 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2309 return 0; 2310 case IB_QP_ACCESS_FLAGS: 2311 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2312 MLX5_QP_OPTPAR_RAE; 2313 case IB_QP_PKEY_INDEX: 2314 return MLX5_QP_OPTPAR_PKEY_INDEX; 2315 case IB_QP_PORT: 2316 return MLX5_QP_OPTPAR_PRI_PORT; 2317 case IB_QP_QKEY: 2318 return MLX5_QP_OPTPAR_Q_KEY; 2319 case IB_QP_AV: 2320 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2321 MLX5_QP_OPTPAR_PRI_PORT; 2322 case IB_QP_PATH_MTU: 2323 return 0; 2324 case IB_QP_TIMEOUT: 2325 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2326 case IB_QP_RETRY_CNT: 2327 return MLX5_QP_OPTPAR_RETRY_COUNT; 2328 case IB_QP_RNR_RETRY: 2329 return MLX5_QP_OPTPAR_RNR_RETRY; 2330 case IB_QP_RQ_PSN: 2331 return 0; 2332 case IB_QP_MAX_QP_RD_ATOMIC: 2333 return MLX5_QP_OPTPAR_SRA_MAX; 2334 case IB_QP_ALT_PATH: 2335 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2336 case IB_QP_MIN_RNR_TIMER: 2337 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2338 case IB_QP_SQ_PSN: 2339 return 0; 2340 case IB_QP_MAX_DEST_RD_ATOMIC: 2341 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2342 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2343 case IB_QP_PATH_MIG_STATE: 2344 return MLX5_QP_OPTPAR_PM_STATE; 2345 case IB_QP_CAP: 2346 return 0; 2347 case IB_QP_DEST_QPN: 2348 return 0; 2349 } 2350 return 0; 2351 } 2352 2353 static int ib_mask_to_mlx5_opt(int ib_mask) 2354 { 2355 int result = 0; 2356 int i; 2357 2358 for (i = 0; i < 8 * sizeof(int); i++) { 2359 if ((1 << i) & ib_mask) 2360 result |= ib_nr_to_mlx5_nr(1 << i); 2361 } 2362 2363 return result; 2364 } 2365 2366 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev, 2367 struct mlx5_ib_rq *rq, int new_state) 2368 { 2369 void *in; 2370 void *rqc; 2371 int inlen; 2372 int err; 2373 2374 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2375 in = mlx5_vzalloc(inlen); 2376 if (!in) 2377 return -ENOMEM; 2378 2379 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2380 2381 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2382 MLX5_SET(rqc, rqc, state, new_state); 2383 2384 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen); 2385 if (err) 2386 goto out; 2387 2388 rq->state = new_state; 2389 2390 out: 2391 kvfree(in); 2392 return err; 2393 } 2394 2395 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2396 struct mlx5_ib_sq *sq, int new_state) 2397 { 2398 void *in; 2399 void *sqc; 2400 int inlen; 2401 int err; 2402 2403 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2404 in = mlx5_vzalloc(inlen); 2405 if (!in) 2406 return -ENOMEM; 2407 2408 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2409 2410 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2411 MLX5_SET(sqc, sqc, state, new_state); 2412 2413 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2414 if (err) 2415 goto out; 2416 2417 sq->state = new_state; 2418 2419 out: 2420 kvfree(in); 2421 return err; 2422 } 2423 2424 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2425 u16 operation) 2426 { 2427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2428 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2429 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2430 int rq_state; 2431 int sq_state; 2432 int err; 2433 2434 switch (operation) { 2435 case MLX5_CMD_OP_RST2INIT_QP: 2436 rq_state = MLX5_RQC_STATE_RDY; 2437 sq_state = MLX5_SQC_STATE_RDY; 2438 break; 2439 case MLX5_CMD_OP_2ERR_QP: 2440 rq_state = MLX5_RQC_STATE_ERR; 2441 sq_state = MLX5_SQC_STATE_ERR; 2442 break; 2443 case MLX5_CMD_OP_2RST_QP: 2444 rq_state = MLX5_RQC_STATE_RST; 2445 sq_state = MLX5_SQC_STATE_RST; 2446 break; 2447 case MLX5_CMD_OP_INIT2INIT_QP: 2448 case MLX5_CMD_OP_INIT2RTR_QP: 2449 case MLX5_CMD_OP_RTR2RTS_QP: 2450 case MLX5_CMD_OP_RTS2RTS_QP: 2451 /* Nothing to do here... */ 2452 return 0; 2453 default: 2454 WARN_ON(1); 2455 return -EINVAL; 2456 } 2457 2458 if (qp->rq.wqe_cnt) { 2459 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state); 2460 if (err) 2461 return err; 2462 } 2463 2464 if (qp->sq.wqe_cnt) 2465 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2466 2467 return 0; 2468 } 2469 2470 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2471 const struct ib_qp_attr *attr, int attr_mask, 2472 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2473 { 2474 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2475 [MLX5_QP_STATE_RST] = { 2476 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2477 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2478 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2479 }, 2480 [MLX5_QP_STATE_INIT] = { 2481 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2482 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2483 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2484 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2485 }, 2486 [MLX5_QP_STATE_RTR] = { 2487 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2488 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2489 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2490 }, 2491 [MLX5_QP_STATE_RTS] = { 2492 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2493 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2494 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2495 }, 2496 [MLX5_QP_STATE_SQD] = { 2497 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2498 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2499 }, 2500 [MLX5_QP_STATE_SQER] = { 2501 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2502 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2503 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2504 }, 2505 [MLX5_QP_STATE_ERR] = { 2506 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2507 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2508 } 2509 }; 2510 2511 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2512 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2513 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2514 struct mlx5_ib_cq *send_cq, *recv_cq; 2515 struct mlx5_qp_context *context; 2516 struct mlx5_ib_pd *pd; 2517 enum mlx5_qp_state mlx5_cur, mlx5_new; 2518 enum mlx5_qp_optpar optpar; 2519 int sqd_event; 2520 int mlx5_st; 2521 int err; 2522 u16 op; 2523 2524 context = kzalloc(sizeof(*context), GFP_KERNEL); 2525 if (!context) 2526 return -ENOMEM; 2527 2528 err = to_mlx5_st(ibqp->qp_type); 2529 if (err < 0) { 2530 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2531 goto out; 2532 } 2533 2534 context->flags = cpu_to_be32(err << 16); 2535 2536 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2537 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2538 } else { 2539 switch (attr->path_mig_state) { 2540 case IB_MIG_MIGRATED: 2541 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2542 break; 2543 case IB_MIG_REARM: 2544 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2545 break; 2546 case IB_MIG_ARMED: 2547 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2548 break; 2549 } 2550 } 2551 2552 if (is_sqp(ibqp->qp_type)) { 2553 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2554 } else if (ibqp->qp_type == IB_QPT_UD || 2555 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2556 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2557 } else if (attr_mask & IB_QP_PATH_MTU) { 2558 if (attr->path_mtu < IB_MTU_256 || 2559 attr->path_mtu > IB_MTU_4096) { 2560 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2561 err = -EINVAL; 2562 goto out; 2563 } 2564 context->mtu_msgmax = (attr->path_mtu << 5) | 2565 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2566 } 2567 2568 if (attr_mask & IB_QP_DEST_QPN) 2569 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2570 2571 if (attr_mask & IB_QP_PKEY_INDEX) 2572 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2573 2574 /* todo implement counter_index functionality */ 2575 2576 if (is_sqp(ibqp->qp_type)) 2577 context->pri_path.port = qp->port; 2578 2579 if (attr_mask & IB_QP_PORT) 2580 context->pri_path.port = attr->port_num; 2581 2582 if (attr_mask & IB_QP_AV) { 2583 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2584 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2585 attr_mask, 0, attr, false); 2586 if (err) 2587 goto out; 2588 } 2589 2590 if (attr_mask & IB_QP_TIMEOUT) 2591 context->pri_path.ackto_lt |= attr->timeout << 3; 2592 2593 if (attr_mask & IB_QP_ALT_PATH) { 2594 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2595 &context->alt_path, 2596 attr->alt_port_num, 2597 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2598 0, attr, true); 2599 if (err) 2600 goto out; 2601 } 2602 2603 pd = get_pd(qp); 2604 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2605 &send_cq, &recv_cq); 2606 2607 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2608 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2609 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2610 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2611 2612 if (attr_mask & IB_QP_RNR_RETRY) 2613 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2614 2615 if (attr_mask & IB_QP_RETRY_CNT) 2616 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2617 2618 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2619 if (attr->max_rd_atomic) 2620 context->params1 |= 2621 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2622 } 2623 2624 if (attr_mask & IB_QP_SQ_PSN) 2625 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2626 2627 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2628 if (attr->max_dest_rd_atomic) 2629 context->params2 |= 2630 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2631 } 2632 2633 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2634 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2635 2636 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2637 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2638 2639 if (attr_mask & IB_QP_RQ_PSN) 2640 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2641 2642 if (attr_mask & IB_QP_QKEY) 2643 context->qkey = cpu_to_be32(attr->qkey); 2644 2645 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2646 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2647 2648 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2649 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2650 sqd_event = 1; 2651 else 2652 sqd_event = 0; 2653 2654 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2655 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2656 qp->port) - 1; 2657 struct mlx5_ib_port *mibport = &dev->port[port_num]; 2658 2659 context->qp_counter_set_usr_page |= 2660 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2661 } 2662 2663 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2664 context->sq_crq_size |= cpu_to_be16(1 << 4); 2665 2666 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2667 context->deth_sqpn = cpu_to_be32(1); 2668 2669 mlx5_cur = to_mlx5_state(cur_state); 2670 mlx5_new = to_mlx5_state(new_state); 2671 mlx5_st = to_mlx5_st(ibqp->qp_type); 2672 if (mlx5_st < 0) 2673 goto out; 2674 2675 /* If moving to a reset or error state, we must disable page faults on 2676 * this QP and flush all current page faults. Otherwise a stale page 2677 * fault may attempt to work on this QP after it is reset and moved 2678 * again to RTS, and may cause the driver and the device to get out of 2679 * sync. */ 2680 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2681 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2682 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2683 mlx5_ib_qp_disable_pagefaults(qp); 2684 2685 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2686 !optab[mlx5_cur][mlx5_new]) 2687 goto out; 2688 2689 op = optab[mlx5_cur][mlx5_new]; 2690 optpar = ib_mask_to_mlx5_opt(attr_mask); 2691 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2692 2693 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) 2694 err = modify_raw_packet_qp(dev, qp, op); 2695 else 2696 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2697 &base->mqp); 2698 if (err) 2699 goto out; 2700 2701 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2702 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2703 mlx5_ib_qp_enable_pagefaults(qp); 2704 2705 qp->state = new_state; 2706 2707 if (attr_mask & IB_QP_ACCESS_FLAGS) 2708 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2709 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2710 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2711 if (attr_mask & IB_QP_PORT) 2712 qp->port = attr->port_num; 2713 if (attr_mask & IB_QP_ALT_PATH) 2714 qp->trans_qp.alt_port = attr->alt_port_num; 2715 2716 /* 2717 * If we moved a kernel QP to RESET, clean up all old CQ 2718 * entries and reinitialize the QP. 2719 */ 2720 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2721 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2722 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2723 if (send_cq != recv_cq) 2724 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2725 2726 qp->rq.head = 0; 2727 qp->rq.tail = 0; 2728 qp->sq.head = 0; 2729 qp->sq.tail = 0; 2730 qp->sq.cur_post = 0; 2731 qp->sq.last_poll = 0; 2732 qp->db.db[MLX5_RCV_DBR] = 0; 2733 qp->db.db[MLX5_SND_DBR] = 0; 2734 } 2735 2736 out: 2737 kfree(context); 2738 return err; 2739 } 2740 2741 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2742 int attr_mask, struct ib_udata *udata) 2743 { 2744 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2745 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2746 enum ib_qp_type qp_type; 2747 enum ib_qp_state cur_state, new_state; 2748 int err = -EINVAL; 2749 int port; 2750 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2751 2752 if (ibqp->rwq_ind_tbl) 2753 return -ENOSYS; 2754 2755 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2756 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2757 2758 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2759 IB_QPT_GSI : ibqp->qp_type; 2760 2761 mutex_lock(&qp->mutex); 2762 2763 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2764 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2765 2766 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2767 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2768 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2769 } 2770 2771 if (qp_type != MLX5_IB_QPT_REG_UMR && 2772 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2773 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2774 cur_state, new_state, ibqp->qp_type, attr_mask); 2775 goto out; 2776 } 2777 2778 if ((attr_mask & IB_QP_PORT) && 2779 (attr->port_num == 0 || 2780 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2781 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2782 attr->port_num, dev->num_ports); 2783 goto out; 2784 } 2785 2786 if (attr_mask & IB_QP_PKEY_INDEX) { 2787 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2788 if (attr->pkey_index >= 2789 dev->mdev->port_caps[port - 1].pkey_table_len) { 2790 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2791 attr->pkey_index); 2792 goto out; 2793 } 2794 } 2795 2796 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2797 attr->max_rd_atomic > 2798 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2799 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2800 attr->max_rd_atomic); 2801 goto out; 2802 } 2803 2804 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2805 attr->max_dest_rd_atomic > 2806 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 2807 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 2808 attr->max_dest_rd_atomic); 2809 goto out; 2810 } 2811 2812 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2813 err = 0; 2814 goto out; 2815 } 2816 2817 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2818 2819 out: 2820 mutex_unlock(&qp->mutex); 2821 return err; 2822 } 2823 2824 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2825 { 2826 struct mlx5_ib_cq *cq; 2827 unsigned cur; 2828 2829 cur = wq->head - wq->tail; 2830 if (likely(cur + nreq < wq->max_post)) 2831 return 0; 2832 2833 cq = to_mcq(ib_cq); 2834 spin_lock(&cq->lock); 2835 cur = wq->head - wq->tail; 2836 spin_unlock(&cq->lock); 2837 2838 return cur + nreq >= wq->max_post; 2839 } 2840 2841 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 2842 u64 remote_addr, u32 rkey) 2843 { 2844 rseg->raddr = cpu_to_be64(remote_addr); 2845 rseg->rkey = cpu_to_be32(rkey); 2846 rseg->reserved = 0; 2847 } 2848 2849 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 2850 struct ib_send_wr *wr, void *qend, 2851 struct mlx5_ib_qp *qp, int *size) 2852 { 2853 void *seg = eseg; 2854 2855 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 2856 2857 if (wr->send_flags & IB_SEND_IP_CSUM) 2858 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 2859 MLX5_ETH_WQE_L4_CSUM; 2860 2861 seg += sizeof(struct mlx5_wqe_eth_seg); 2862 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 2863 2864 if (wr->opcode == IB_WR_LSO) { 2865 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 2866 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 2867 u64 left, leftlen, copysz; 2868 void *pdata = ud_wr->header; 2869 2870 left = ud_wr->hlen; 2871 eseg->mss = cpu_to_be16(ud_wr->mss); 2872 eseg->inline_hdr_sz = cpu_to_be16(left); 2873 2874 /* 2875 * check if there is space till the end of queue, if yes, 2876 * copy all in one shot, otherwise copy till the end of queue, 2877 * rollback and than the copy the left 2878 */ 2879 leftlen = qend - (void *)eseg->inline_hdr_start; 2880 copysz = min_t(u64, leftlen, left); 2881 2882 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 2883 2884 if (likely(copysz > size_of_inl_hdr_start)) { 2885 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 2886 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 2887 } 2888 2889 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 2890 seg = mlx5_get_send_wqe(qp, 0); 2891 left -= copysz; 2892 pdata += copysz; 2893 memcpy(seg, pdata, left); 2894 seg += ALIGN(left, 16); 2895 *size += ALIGN(left, 16) / 16; 2896 } 2897 } 2898 2899 return seg; 2900 } 2901 2902 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 2903 struct ib_send_wr *wr) 2904 { 2905 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 2906 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 2907 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 2908 } 2909 2910 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 2911 { 2912 dseg->byte_count = cpu_to_be32(sg->length); 2913 dseg->lkey = cpu_to_be32(sg->lkey); 2914 dseg->addr = cpu_to_be64(sg->addr); 2915 } 2916 2917 static __be16 get_klm_octo(int npages) 2918 { 2919 return cpu_to_be16(ALIGN(npages, 8) / 2); 2920 } 2921 2922 static __be64 frwr_mkey_mask(void) 2923 { 2924 u64 result; 2925 2926 result = MLX5_MKEY_MASK_LEN | 2927 MLX5_MKEY_MASK_PAGE_SIZE | 2928 MLX5_MKEY_MASK_START_ADDR | 2929 MLX5_MKEY_MASK_EN_RINVAL | 2930 MLX5_MKEY_MASK_KEY | 2931 MLX5_MKEY_MASK_LR | 2932 MLX5_MKEY_MASK_LW | 2933 MLX5_MKEY_MASK_RR | 2934 MLX5_MKEY_MASK_RW | 2935 MLX5_MKEY_MASK_A | 2936 MLX5_MKEY_MASK_SMALL_FENCE | 2937 MLX5_MKEY_MASK_FREE; 2938 2939 return cpu_to_be64(result); 2940 } 2941 2942 static __be64 sig_mkey_mask(void) 2943 { 2944 u64 result; 2945 2946 result = MLX5_MKEY_MASK_LEN | 2947 MLX5_MKEY_MASK_PAGE_SIZE | 2948 MLX5_MKEY_MASK_START_ADDR | 2949 MLX5_MKEY_MASK_EN_SIGERR | 2950 MLX5_MKEY_MASK_EN_RINVAL | 2951 MLX5_MKEY_MASK_KEY | 2952 MLX5_MKEY_MASK_LR | 2953 MLX5_MKEY_MASK_LW | 2954 MLX5_MKEY_MASK_RR | 2955 MLX5_MKEY_MASK_RW | 2956 MLX5_MKEY_MASK_SMALL_FENCE | 2957 MLX5_MKEY_MASK_FREE | 2958 MLX5_MKEY_MASK_BSF_EN; 2959 2960 return cpu_to_be64(result); 2961 } 2962 2963 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 2964 struct mlx5_ib_mr *mr) 2965 { 2966 int ndescs = mr->ndescs; 2967 2968 memset(umr, 0, sizeof(*umr)); 2969 2970 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 2971 /* KLMs take twice the size of MTTs */ 2972 ndescs *= 2; 2973 2974 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 2975 umr->klm_octowords = get_klm_octo(ndescs); 2976 umr->mkey_mask = frwr_mkey_mask(); 2977 } 2978 2979 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 2980 { 2981 memset(umr, 0, sizeof(*umr)); 2982 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 2983 umr->flags = 1 << 7; 2984 } 2985 2986 static __be64 get_umr_reg_mr_mask(void) 2987 { 2988 u64 result; 2989 2990 result = MLX5_MKEY_MASK_LEN | 2991 MLX5_MKEY_MASK_PAGE_SIZE | 2992 MLX5_MKEY_MASK_START_ADDR | 2993 MLX5_MKEY_MASK_PD | 2994 MLX5_MKEY_MASK_LR | 2995 MLX5_MKEY_MASK_LW | 2996 MLX5_MKEY_MASK_KEY | 2997 MLX5_MKEY_MASK_RR | 2998 MLX5_MKEY_MASK_RW | 2999 MLX5_MKEY_MASK_A | 3000 MLX5_MKEY_MASK_FREE; 3001 3002 return cpu_to_be64(result); 3003 } 3004 3005 static __be64 get_umr_unreg_mr_mask(void) 3006 { 3007 u64 result; 3008 3009 result = MLX5_MKEY_MASK_FREE; 3010 3011 return cpu_to_be64(result); 3012 } 3013 3014 static __be64 get_umr_update_mtt_mask(void) 3015 { 3016 u64 result; 3017 3018 result = MLX5_MKEY_MASK_FREE; 3019 3020 return cpu_to_be64(result); 3021 } 3022 3023 static __be64 get_umr_update_translation_mask(void) 3024 { 3025 u64 result; 3026 3027 result = MLX5_MKEY_MASK_LEN | 3028 MLX5_MKEY_MASK_PAGE_SIZE | 3029 MLX5_MKEY_MASK_START_ADDR | 3030 MLX5_MKEY_MASK_KEY | 3031 MLX5_MKEY_MASK_FREE; 3032 3033 return cpu_to_be64(result); 3034 } 3035 3036 static __be64 get_umr_update_access_mask(void) 3037 { 3038 u64 result; 3039 3040 result = MLX5_MKEY_MASK_LW | 3041 MLX5_MKEY_MASK_RR | 3042 MLX5_MKEY_MASK_RW | 3043 MLX5_MKEY_MASK_A | 3044 MLX5_MKEY_MASK_KEY | 3045 MLX5_MKEY_MASK_FREE; 3046 3047 return cpu_to_be64(result); 3048 } 3049 3050 static __be64 get_umr_update_pd_mask(void) 3051 { 3052 u64 result; 3053 3054 result = MLX5_MKEY_MASK_PD | 3055 MLX5_MKEY_MASK_KEY | 3056 MLX5_MKEY_MASK_FREE; 3057 3058 return cpu_to_be64(result); 3059 } 3060 3061 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3062 struct ib_send_wr *wr) 3063 { 3064 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3065 3066 memset(umr, 0, sizeof(*umr)); 3067 3068 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3069 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3070 else 3071 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3072 3073 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3074 umr->klm_octowords = get_klm_octo(umrwr->npages); 3075 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3076 umr->mkey_mask = get_umr_update_mtt_mask(); 3077 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3078 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3079 } 3080 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3081 umr->mkey_mask |= get_umr_update_translation_mask(); 3082 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3083 umr->mkey_mask |= get_umr_update_access_mask(); 3084 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3085 umr->mkey_mask |= get_umr_update_pd_mask(); 3086 if (!umr->mkey_mask) 3087 umr->mkey_mask = get_umr_reg_mr_mask(); 3088 } else { 3089 umr->mkey_mask = get_umr_unreg_mr_mask(); 3090 } 3091 3092 if (!wr->num_sge) 3093 umr->flags |= MLX5_UMR_INLINE; 3094 } 3095 3096 static u8 get_umr_flags(int acc) 3097 { 3098 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3099 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3100 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3101 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3102 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3103 } 3104 3105 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3106 struct mlx5_ib_mr *mr, 3107 u32 key, int access) 3108 { 3109 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3110 3111 memset(seg, 0, sizeof(*seg)); 3112 3113 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3114 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3115 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3116 /* KLMs take twice the size of MTTs */ 3117 ndescs *= 2; 3118 3119 seg->flags = get_umr_flags(access) | mr->access_mode; 3120 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3121 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3122 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3123 seg->len = cpu_to_be64(mr->ibmr.length); 3124 seg->xlt_oct_size = cpu_to_be32(ndescs); 3125 } 3126 3127 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3128 { 3129 memset(seg, 0, sizeof(*seg)); 3130 seg->status = MLX5_MKEY_STATUS_FREE; 3131 } 3132 3133 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3134 { 3135 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3136 3137 memset(seg, 0, sizeof(*seg)); 3138 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3139 seg->status = MLX5_MKEY_STATUS_FREE; 3140 return; 3141 } 3142 3143 seg->flags = convert_access(umrwr->access_flags); 3144 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3145 if (umrwr->pd) 3146 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3147 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3148 } 3149 seg->len = cpu_to_be64(umrwr->length); 3150 seg->log2_page_size = umrwr->page_shift; 3151 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3152 mlx5_mkey_variant(umrwr->mkey)); 3153 } 3154 3155 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3156 struct mlx5_ib_mr *mr, 3157 struct mlx5_ib_pd *pd) 3158 { 3159 int bcount = mr->desc_size * mr->ndescs; 3160 3161 dseg->addr = cpu_to_be64(mr->desc_map); 3162 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3163 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3164 } 3165 3166 static __be32 send_ieth(struct ib_send_wr *wr) 3167 { 3168 switch (wr->opcode) { 3169 case IB_WR_SEND_WITH_IMM: 3170 case IB_WR_RDMA_WRITE_WITH_IMM: 3171 return wr->ex.imm_data; 3172 3173 case IB_WR_SEND_WITH_INV: 3174 return cpu_to_be32(wr->ex.invalidate_rkey); 3175 3176 default: 3177 return 0; 3178 } 3179 } 3180 3181 static u8 calc_sig(void *wqe, int size) 3182 { 3183 u8 *p = wqe; 3184 u8 res = 0; 3185 int i; 3186 3187 for (i = 0; i < size; i++) 3188 res ^= p[i]; 3189 3190 return ~res; 3191 } 3192 3193 static u8 wq_sig(void *wqe) 3194 { 3195 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3196 } 3197 3198 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3199 void *wqe, int *sz) 3200 { 3201 struct mlx5_wqe_inline_seg *seg; 3202 void *qend = qp->sq.qend; 3203 void *addr; 3204 int inl = 0; 3205 int copy; 3206 int len; 3207 int i; 3208 3209 seg = wqe; 3210 wqe += sizeof(*seg); 3211 for (i = 0; i < wr->num_sge; i++) { 3212 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3213 len = wr->sg_list[i].length; 3214 inl += len; 3215 3216 if (unlikely(inl > qp->max_inline_data)) 3217 return -ENOMEM; 3218 3219 if (unlikely(wqe + len > qend)) { 3220 copy = qend - wqe; 3221 memcpy(wqe, addr, copy); 3222 addr += copy; 3223 len -= copy; 3224 wqe = mlx5_get_send_wqe(qp, 0); 3225 } 3226 memcpy(wqe, addr, len); 3227 wqe += len; 3228 } 3229 3230 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3231 3232 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3233 3234 return 0; 3235 } 3236 3237 static u16 prot_field_size(enum ib_signature_type type) 3238 { 3239 switch (type) { 3240 case IB_SIG_TYPE_T10_DIF: 3241 return MLX5_DIF_SIZE; 3242 default: 3243 return 0; 3244 } 3245 } 3246 3247 static u8 bs_selector(int block_size) 3248 { 3249 switch (block_size) { 3250 case 512: return 0x1; 3251 case 520: return 0x2; 3252 case 4096: return 0x3; 3253 case 4160: return 0x4; 3254 case 1073741824: return 0x5; 3255 default: return 0; 3256 } 3257 } 3258 3259 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3260 struct mlx5_bsf_inl *inl) 3261 { 3262 /* Valid inline section and allow BSF refresh */ 3263 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3264 MLX5_BSF_REFRESH_DIF); 3265 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3266 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3267 /* repeating block */ 3268 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3269 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3270 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3271 3272 if (domain->sig.dif.ref_remap) 3273 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3274 3275 if (domain->sig.dif.app_escape) { 3276 if (domain->sig.dif.ref_escape) 3277 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3278 else 3279 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3280 } 3281 3282 inl->dif_app_bitmask_check = 3283 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3284 } 3285 3286 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3287 struct ib_sig_attrs *sig_attrs, 3288 struct mlx5_bsf *bsf, u32 data_size) 3289 { 3290 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3291 struct mlx5_bsf_basic *basic = &bsf->basic; 3292 struct ib_sig_domain *mem = &sig_attrs->mem; 3293 struct ib_sig_domain *wire = &sig_attrs->wire; 3294 3295 memset(bsf, 0, sizeof(*bsf)); 3296 3297 /* Basic + Extended + Inline */ 3298 basic->bsf_size_sbs = 1 << 7; 3299 /* Input domain check byte mask */ 3300 basic->check_byte_mask = sig_attrs->check_mask; 3301 basic->raw_data_size = cpu_to_be32(data_size); 3302 3303 /* Memory domain */ 3304 switch (sig_attrs->mem.sig_type) { 3305 case IB_SIG_TYPE_NONE: 3306 break; 3307 case IB_SIG_TYPE_T10_DIF: 3308 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3309 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3310 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3311 break; 3312 default: 3313 return -EINVAL; 3314 } 3315 3316 /* Wire domain */ 3317 switch (sig_attrs->wire.sig_type) { 3318 case IB_SIG_TYPE_NONE: 3319 break; 3320 case IB_SIG_TYPE_T10_DIF: 3321 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3322 mem->sig_type == wire->sig_type) { 3323 /* Same block structure */ 3324 basic->bsf_size_sbs |= 1 << 4; 3325 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3326 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3327 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3328 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3329 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3330 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3331 } else 3332 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3333 3334 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3335 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3336 break; 3337 default: 3338 return -EINVAL; 3339 } 3340 3341 return 0; 3342 } 3343 3344 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3345 struct mlx5_ib_qp *qp, void **seg, int *size) 3346 { 3347 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3348 struct ib_mr *sig_mr = wr->sig_mr; 3349 struct mlx5_bsf *bsf; 3350 u32 data_len = wr->wr.sg_list->length; 3351 u32 data_key = wr->wr.sg_list->lkey; 3352 u64 data_va = wr->wr.sg_list->addr; 3353 int ret; 3354 int wqe_size; 3355 3356 if (!wr->prot || 3357 (data_key == wr->prot->lkey && 3358 data_va == wr->prot->addr && 3359 data_len == wr->prot->length)) { 3360 /** 3361 * Source domain doesn't contain signature information 3362 * or data and protection are interleaved in memory. 3363 * So need construct: 3364 * ------------------ 3365 * | data_klm | 3366 * ------------------ 3367 * | BSF | 3368 * ------------------ 3369 **/ 3370 struct mlx5_klm *data_klm = *seg; 3371 3372 data_klm->bcount = cpu_to_be32(data_len); 3373 data_klm->key = cpu_to_be32(data_key); 3374 data_klm->va = cpu_to_be64(data_va); 3375 wqe_size = ALIGN(sizeof(*data_klm), 64); 3376 } else { 3377 /** 3378 * Source domain contains signature information 3379 * So need construct a strided block format: 3380 * --------------------------- 3381 * | stride_block_ctrl | 3382 * --------------------------- 3383 * | data_klm | 3384 * --------------------------- 3385 * | prot_klm | 3386 * --------------------------- 3387 * | BSF | 3388 * --------------------------- 3389 **/ 3390 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3391 struct mlx5_stride_block_entry *data_sentry; 3392 struct mlx5_stride_block_entry *prot_sentry; 3393 u32 prot_key = wr->prot->lkey; 3394 u64 prot_va = wr->prot->addr; 3395 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3396 int prot_size; 3397 3398 sblock_ctrl = *seg; 3399 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3400 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3401 3402 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3403 if (!prot_size) { 3404 pr_err("Bad block size given: %u\n", block_size); 3405 return -EINVAL; 3406 } 3407 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3408 prot_size); 3409 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3410 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3411 sblock_ctrl->num_entries = cpu_to_be16(2); 3412 3413 data_sentry->bcount = cpu_to_be16(block_size); 3414 data_sentry->key = cpu_to_be32(data_key); 3415 data_sentry->va = cpu_to_be64(data_va); 3416 data_sentry->stride = cpu_to_be16(block_size); 3417 3418 prot_sentry->bcount = cpu_to_be16(prot_size); 3419 prot_sentry->key = cpu_to_be32(prot_key); 3420 prot_sentry->va = cpu_to_be64(prot_va); 3421 prot_sentry->stride = cpu_to_be16(prot_size); 3422 3423 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3424 sizeof(*prot_sentry), 64); 3425 } 3426 3427 *seg += wqe_size; 3428 *size += wqe_size / 16; 3429 if (unlikely((*seg == qp->sq.qend))) 3430 *seg = mlx5_get_send_wqe(qp, 0); 3431 3432 bsf = *seg; 3433 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3434 if (ret) 3435 return -EINVAL; 3436 3437 *seg += sizeof(*bsf); 3438 *size += sizeof(*bsf) / 16; 3439 if (unlikely((*seg == qp->sq.qend))) 3440 *seg = mlx5_get_send_wqe(qp, 0); 3441 3442 return 0; 3443 } 3444 3445 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3446 struct ib_sig_handover_wr *wr, u32 nelements, 3447 u32 length, u32 pdn) 3448 { 3449 struct ib_mr *sig_mr = wr->sig_mr; 3450 u32 sig_key = sig_mr->rkey; 3451 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3452 3453 memset(seg, 0, sizeof(*seg)); 3454 3455 seg->flags = get_umr_flags(wr->access_flags) | 3456 MLX5_MKC_ACCESS_MODE_KLMS; 3457 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3458 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3459 MLX5_MKEY_BSF_EN | pdn); 3460 seg->len = cpu_to_be64(length); 3461 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3462 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3463 } 3464 3465 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3466 u32 nelements) 3467 { 3468 memset(umr, 0, sizeof(*umr)); 3469 3470 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3471 umr->klm_octowords = get_klm_octo(nelements); 3472 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3473 umr->mkey_mask = sig_mkey_mask(); 3474 } 3475 3476 3477 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3478 void **seg, int *size) 3479 { 3480 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3481 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3482 u32 pdn = get_pd(qp)->pdn; 3483 u32 klm_oct_size; 3484 int region_len, ret; 3485 3486 if (unlikely(wr->wr.num_sge != 1) || 3487 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3488 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3489 unlikely(!sig_mr->sig->sig_status_checked)) 3490 return -EINVAL; 3491 3492 /* length of the protected region, data + protection */ 3493 region_len = wr->wr.sg_list->length; 3494 if (wr->prot && 3495 (wr->prot->lkey != wr->wr.sg_list->lkey || 3496 wr->prot->addr != wr->wr.sg_list->addr || 3497 wr->prot->length != wr->wr.sg_list->length)) 3498 region_len += wr->prot->length; 3499 3500 /** 3501 * KLM octoword size - if protection was provided 3502 * then we use strided block format (3 octowords), 3503 * else we use single KLM (1 octoword) 3504 **/ 3505 klm_oct_size = wr->prot ? 3 : 1; 3506 3507 set_sig_umr_segment(*seg, klm_oct_size); 3508 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3509 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3510 if (unlikely((*seg == qp->sq.qend))) 3511 *seg = mlx5_get_send_wqe(qp, 0); 3512 3513 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3514 *seg += sizeof(struct mlx5_mkey_seg); 3515 *size += sizeof(struct mlx5_mkey_seg) / 16; 3516 if (unlikely((*seg == qp->sq.qend))) 3517 *seg = mlx5_get_send_wqe(qp, 0); 3518 3519 ret = set_sig_data_segment(wr, qp, seg, size); 3520 if (ret) 3521 return ret; 3522 3523 sig_mr->sig->sig_status_checked = false; 3524 return 0; 3525 } 3526 3527 static int set_psv_wr(struct ib_sig_domain *domain, 3528 u32 psv_idx, void **seg, int *size) 3529 { 3530 struct mlx5_seg_set_psv *psv_seg = *seg; 3531 3532 memset(psv_seg, 0, sizeof(*psv_seg)); 3533 psv_seg->psv_num = cpu_to_be32(psv_idx); 3534 switch (domain->sig_type) { 3535 case IB_SIG_TYPE_NONE: 3536 break; 3537 case IB_SIG_TYPE_T10_DIF: 3538 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3539 domain->sig.dif.app_tag); 3540 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3541 break; 3542 default: 3543 pr_err("Bad signature type given.\n"); 3544 return 1; 3545 } 3546 3547 *seg += sizeof(*psv_seg); 3548 *size += sizeof(*psv_seg) / 16; 3549 3550 return 0; 3551 } 3552 3553 static int set_reg_wr(struct mlx5_ib_qp *qp, 3554 struct ib_reg_wr *wr, 3555 void **seg, int *size) 3556 { 3557 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3558 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3559 3560 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3561 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3562 "Invalid IB_SEND_INLINE send flag\n"); 3563 return -EINVAL; 3564 } 3565 3566 set_reg_umr_seg(*seg, mr); 3567 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3568 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3569 if (unlikely((*seg == qp->sq.qend))) 3570 *seg = mlx5_get_send_wqe(qp, 0); 3571 3572 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3573 *seg += sizeof(struct mlx5_mkey_seg); 3574 *size += sizeof(struct mlx5_mkey_seg) / 16; 3575 if (unlikely((*seg == qp->sq.qend))) 3576 *seg = mlx5_get_send_wqe(qp, 0); 3577 3578 set_reg_data_seg(*seg, mr, pd); 3579 *seg += sizeof(struct mlx5_wqe_data_seg); 3580 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3581 3582 return 0; 3583 } 3584 3585 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3586 { 3587 set_linv_umr_seg(*seg); 3588 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3589 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3590 if (unlikely((*seg == qp->sq.qend))) 3591 *seg = mlx5_get_send_wqe(qp, 0); 3592 set_linv_mkey_seg(*seg); 3593 *seg += sizeof(struct mlx5_mkey_seg); 3594 *size += sizeof(struct mlx5_mkey_seg) / 16; 3595 if (unlikely((*seg == qp->sq.qend))) 3596 *seg = mlx5_get_send_wqe(qp, 0); 3597 } 3598 3599 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3600 { 3601 __be32 *p = NULL; 3602 int tidx = idx; 3603 int i, j; 3604 3605 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3606 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3607 if ((i & 0xf) == 0) { 3608 void *buf = mlx5_get_send_wqe(qp, tidx); 3609 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3610 p = buf; 3611 j = 0; 3612 } 3613 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3614 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3615 be32_to_cpu(p[j + 3])); 3616 } 3617 } 3618 3619 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 3620 unsigned bytecnt, struct mlx5_ib_qp *qp) 3621 { 3622 while (bytecnt > 0) { 3623 __iowrite64_copy(dst++, src++, 8); 3624 __iowrite64_copy(dst++, src++, 8); 3625 __iowrite64_copy(dst++, src++, 8); 3626 __iowrite64_copy(dst++, src++, 8); 3627 __iowrite64_copy(dst++, src++, 8); 3628 __iowrite64_copy(dst++, src++, 8); 3629 __iowrite64_copy(dst++, src++, 8); 3630 __iowrite64_copy(dst++, src++, 8); 3631 bytecnt -= 64; 3632 if (unlikely(src == qp->sq.qend)) 3633 src = mlx5_get_send_wqe(qp, 0); 3634 } 3635 } 3636 3637 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 3638 { 3639 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3640 wr->send_flags & IB_SEND_FENCE)) 3641 return MLX5_FENCE_MODE_STRONG_ORDERING; 3642 3643 if (unlikely(fence)) { 3644 if (wr->send_flags & IB_SEND_FENCE) 3645 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3646 else 3647 return fence; 3648 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3649 return MLX5_FENCE_MODE_FENCE; 3650 } 3651 3652 return 0; 3653 } 3654 3655 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3656 struct mlx5_wqe_ctrl_seg **ctrl, 3657 struct ib_send_wr *wr, unsigned *idx, 3658 int *size, int nreq) 3659 { 3660 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3661 return -ENOMEM; 3662 3663 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3664 *seg = mlx5_get_send_wqe(qp, *idx); 3665 *ctrl = *seg; 3666 *(uint32_t *)(*seg + 8) = 0; 3667 (*ctrl)->imm = send_ieth(wr); 3668 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3669 (wr->send_flags & IB_SEND_SIGNALED ? 3670 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3671 (wr->send_flags & IB_SEND_SOLICITED ? 3672 MLX5_WQE_CTRL_SOLICITED : 0); 3673 3674 *seg += sizeof(**ctrl); 3675 *size = sizeof(**ctrl) / 16; 3676 3677 return 0; 3678 } 3679 3680 static void finish_wqe(struct mlx5_ib_qp *qp, 3681 struct mlx5_wqe_ctrl_seg *ctrl, 3682 u8 size, unsigned idx, u64 wr_id, 3683 int nreq, u8 fence, u8 next_fence, 3684 u32 mlx5_opcode) 3685 { 3686 u8 opmod = 0; 3687 3688 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3689 mlx5_opcode | ((u32)opmod << 24)); 3690 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3691 ctrl->fm_ce_se |= fence; 3692 qp->fm_cache = next_fence; 3693 if (unlikely(qp->wq_sig)) 3694 ctrl->signature = wq_sig(ctrl); 3695 3696 qp->sq.wrid[idx] = wr_id; 3697 qp->sq.w_list[idx].opcode = mlx5_opcode; 3698 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3699 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3700 qp->sq.w_list[idx].next = qp->sq.cur_post; 3701 } 3702 3703 3704 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3705 struct ib_send_wr **bad_wr) 3706 { 3707 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3708 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3709 struct mlx5_core_dev *mdev = dev->mdev; 3710 struct mlx5_ib_qp *qp; 3711 struct mlx5_ib_mr *mr; 3712 struct mlx5_wqe_data_seg *dpseg; 3713 struct mlx5_wqe_xrc_seg *xrc; 3714 struct mlx5_bf *bf; 3715 int uninitialized_var(size); 3716 void *qend; 3717 unsigned long flags; 3718 unsigned idx; 3719 int err = 0; 3720 int inl = 0; 3721 int num_sge; 3722 void *seg; 3723 int nreq; 3724 int i; 3725 u8 next_fence = 0; 3726 u8 fence; 3727 3728 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3729 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3730 3731 qp = to_mqp(ibqp); 3732 bf = qp->bf; 3733 qend = qp->sq.qend; 3734 3735 spin_lock_irqsave(&qp->sq.lock, flags); 3736 3737 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3738 err = -EIO; 3739 *bad_wr = wr; 3740 nreq = 0; 3741 goto out; 3742 } 3743 3744 for (nreq = 0; wr; nreq++, wr = wr->next) { 3745 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3746 mlx5_ib_warn(dev, "\n"); 3747 err = -EINVAL; 3748 *bad_wr = wr; 3749 goto out; 3750 } 3751 3752 fence = qp->fm_cache; 3753 num_sge = wr->num_sge; 3754 if (unlikely(num_sge > qp->sq.max_gs)) { 3755 mlx5_ib_warn(dev, "\n"); 3756 err = -EINVAL; 3757 *bad_wr = wr; 3758 goto out; 3759 } 3760 3761 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3762 if (err) { 3763 mlx5_ib_warn(dev, "\n"); 3764 err = -ENOMEM; 3765 *bad_wr = wr; 3766 goto out; 3767 } 3768 3769 switch (ibqp->qp_type) { 3770 case IB_QPT_XRC_INI: 3771 xrc = seg; 3772 seg += sizeof(*xrc); 3773 size += sizeof(*xrc) / 16; 3774 /* fall through */ 3775 case IB_QPT_RC: 3776 switch (wr->opcode) { 3777 case IB_WR_RDMA_READ: 3778 case IB_WR_RDMA_WRITE: 3779 case IB_WR_RDMA_WRITE_WITH_IMM: 3780 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3781 rdma_wr(wr)->rkey); 3782 seg += sizeof(struct mlx5_wqe_raddr_seg); 3783 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3784 break; 3785 3786 case IB_WR_ATOMIC_CMP_AND_SWP: 3787 case IB_WR_ATOMIC_FETCH_AND_ADD: 3788 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3789 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3790 err = -ENOSYS; 3791 *bad_wr = wr; 3792 goto out; 3793 3794 case IB_WR_LOCAL_INV: 3795 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3796 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3797 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3798 set_linv_wr(qp, &seg, &size); 3799 num_sge = 0; 3800 break; 3801 3802 case IB_WR_REG_MR: 3803 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3804 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3805 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3806 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3807 if (err) { 3808 *bad_wr = wr; 3809 goto out; 3810 } 3811 num_sge = 0; 3812 break; 3813 3814 case IB_WR_REG_SIG_MR: 3815 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3816 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3817 3818 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3819 err = set_sig_umr_wr(wr, qp, &seg, &size); 3820 if (err) { 3821 mlx5_ib_warn(dev, "\n"); 3822 *bad_wr = wr; 3823 goto out; 3824 } 3825 3826 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3827 nreq, get_fence(fence, wr), 3828 next_fence, MLX5_OPCODE_UMR); 3829 /* 3830 * SET_PSV WQEs are not signaled and solicited 3831 * on error 3832 */ 3833 wr->send_flags &= ~IB_SEND_SIGNALED; 3834 wr->send_flags |= IB_SEND_SOLICITED; 3835 err = begin_wqe(qp, &seg, &ctrl, wr, 3836 &idx, &size, nreq); 3837 if (err) { 3838 mlx5_ib_warn(dev, "\n"); 3839 err = -ENOMEM; 3840 *bad_wr = wr; 3841 goto out; 3842 } 3843 3844 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3845 mr->sig->psv_memory.psv_idx, &seg, 3846 &size); 3847 if (err) { 3848 mlx5_ib_warn(dev, "\n"); 3849 *bad_wr = wr; 3850 goto out; 3851 } 3852 3853 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3854 nreq, get_fence(fence, wr), 3855 next_fence, MLX5_OPCODE_SET_PSV); 3856 err = begin_wqe(qp, &seg, &ctrl, wr, 3857 &idx, &size, nreq); 3858 if (err) { 3859 mlx5_ib_warn(dev, "\n"); 3860 err = -ENOMEM; 3861 *bad_wr = wr; 3862 goto out; 3863 } 3864 3865 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3866 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 3867 mr->sig->psv_wire.psv_idx, &seg, 3868 &size); 3869 if (err) { 3870 mlx5_ib_warn(dev, "\n"); 3871 *bad_wr = wr; 3872 goto out; 3873 } 3874 3875 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3876 nreq, get_fence(fence, wr), 3877 next_fence, MLX5_OPCODE_SET_PSV); 3878 num_sge = 0; 3879 goto skip_psv; 3880 3881 default: 3882 break; 3883 } 3884 break; 3885 3886 case IB_QPT_UC: 3887 switch (wr->opcode) { 3888 case IB_WR_RDMA_WRITE: 3889 case IB_WR_RDMA_WRITE_WITH_IMM: 3890 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3891 rdma_wr(wr)->rkey); 3892 seg += sizeof(struct mlx5_wqe_raddr_seg); 3893 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3894 break; 3895 3896 default: 3897 break; 3898 } 3899 break; 3900 3901 case IB_QPT_SMI: 3902 case MLX5_IB_QPT_HW_GSI: 3903 set_datagram_seg(seg, wr); 3904 seg += sizeof(struct mlx5_wqe_datagram_seg); 3905 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3906 if (unlikely((seg == qend))) 3907 seg = mlx5_get_send_wqe(qp, 0); 3908 break; 3909 case IB_QPT_UD: 3910 set_datagram_seg(seg, wr); 3911 seg += sizeof(struct mlx5_wqe_datagram_seg); 3912 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 3913 3914 if (unlikely((seg == qend))) 3915 seg = mlx5_get_send_wqe(qp, 0); 3916 3917 /* handle qp that supports ud offload */ 3918 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 3919 struct mlx5_wqe_eth_pad *pad; 3920 3921 pad = seg; 3922 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 3923 seg += sizeof(struct mlx5_wqe_eth_pad); 3924 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 3925 3926 seg = set_eth_seg(seg, wr, qend, qp, &size); 3927 3928 if (unlikely((seg == qend))) 3929 seg = mlx5_get_send_wqe(qp, 0); 3930 } 3931 break; 3932 case MLX5_IB_QPT_REG_UMR: 3933 if (wr->opcode != MLX5_IB_WR_UMR) { 3934 err = -EINVAL; 3935 mlx5_ib_warn(dev, "bad opcode\n"); 3936 goto out; 3937 } 3938 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 3939 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 3940 set_reg_umr_segment(seg, wr); 3941 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3942 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3943 if (unlikely((seg == qend))) 3944 seg = mlx5_get_send_wqe(qp, 0); 3945 set_reg_mkey_segment(seg, wr); 3946 seg += sizeof(struct mlx5_mkey_seg); 3947 size += sizeof(struct mlx5_mkey_seg) / 16; 3948 if (unlikely((seg == qend))) 3949 seg = mlx5_get_send_wqe(qp, 0); 3950 break; 3951 3952 default: 3953 break; 3954 } 3955 3956 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 3957 int uninitialized_var(sz); 3958 3959 err = set_data_inl_seg(qp, wr, seg, &sz); 3960 if (unlikely(err)) { 3961 mlx5_ib_warn(dev, "\n"); 3962 *bad_wr = wr; 3963 goto out; 3964 } 3965 inl = 1; 3966 size += sz; 3967 } else { 3968 dpseg = seg; 3969 for (i = 0; i < num_sge; i++) { 3970 if (unlikely(dpseg == qend)) { 3971 seg = mlx5_get_send_wqe(qp, 0); 3972 dpseg = seg; 3973 } 3974 if (likely(wr->sg_list[i].length)) { 3975 set_data_ptr_seg(dpseg, wr->sg_list + i); 3976 size += sizeof(struct mlx5_wqe_data_seg) / 16; 3977 dpseg++; 3978 } 3979 } 3980 } 3981 3982 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3983 get_fence(fence, wr), next_fence, 3984 mlx5_ib_opcode[wr->opcode]); 3985 skip_psv: 3986 if (0) 3987 dump_wqe(qp, idx, size); 3988 } 3989 3990 out: 3991 if (likely(nreq)) { 3992 qp->sq.head += nreq; 3993 3994 /* Make sure that descriptors are written before 3995 * updating doorbell record and ringing the doorbell 3996 */ 3997 wmb(); 3998 3999 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4000 4001 /* Make sure doorbell record is visible to the HCA before 4002 * we hit doorbell */ 4003 wmb(); 4004 4005 if (bf->need_lock) 4006 spin_lock(&bf->lock); 4007 else 4008 __acquire(&bf->lock); 4009 4010 /* TBD enable WC */ 4011 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 4012 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 4013 /* wc_wmb(); */ 4014 } else { 4015 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 4016 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4017 /* Make sure doorbells don't leak out of SQ spinlock 4018 * and reach the HCA out of order. 4019 */ 4020 mmiowb(); 4021 } 4022 bf->offset ^= bf->buf_size; 4023 if (bf->need_lock) 4024 spin_unlock(&bf->lock); 4025 else 4026 __release(&bf->lock); 4027 } 4028 4029 spin_unlock_irqrestore(&qp->sq.lock, flags); 4030 4031 return err; 4032 } 4033 4034 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4035 { 4036 sig->signature = calc_sig(sig, size); 4037 } 4038 4039 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4040 struct ib_recv_wr **bad_wr) 4041 { 4042 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4043 struct mlx5_wqe_data_seg *scat; 4044 struct mlx5_rwqe_sig *sig; 4045 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4046 struct mlx5_core_dev *mdev = dev->mdev; 4047 unsigned long flags; 4048 int err = 0; 4049 int nreq; 4050 int ind; 4051 int i; 4052 4053 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4054 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4055 4056 spin_lock_irqsave(&qp->rq.lock, flags); 4057 4058 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4059 err = -EIO; 4060 *bad_wr = wr; 4061 nreq = 0; 4062 goto out; 4063 } 4064 4065 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4066 4067 for (nreq = 0; wr; nreq++, wr = wr->next) { 4068 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4069 err = -ENOMEM; 4070 *bad_wr = wr; 4071 goto out; 4072 } 4073 4074 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4075 err = -EINVAL; 4076 *bad_wr = wr; 4077 goto out; 4078 } 4079 4080 scat = get_recv_wqe(qp, ind); 4081 if (qp->wq_sig) 4082 scat++; 4083 4084 for (i = 0; i < wr->num_sge; i++) 4085 set_data_ptr_seg(scat + i, wr->sg_list + i); 4086 4087 if (i < qp->rq.max_gs) { 4088 scat[i].byte_count = 0; 4089 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4090 scat[i].addr = 0; 4091 } 4092 4093 if (qp->wq_sig) { 4094 sig = (struct mlx5_rwqe_sig *)scat; 4095 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4096 } 4097 4098 qp->rq.wrid[ind] = wr->wr_id; 4099 4100 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4101 } 4102 4103 out: 4104 if (likely(nreq)) { 4105 qp->rq.head += nreq; 4106 4107 /* Make sure that descriptors are written before 4108 * doorbell record. 4109 */ 4110 wmb(); 4111 4112 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4113 } 4114 4115 spin_unlock_irqrestore(&qp->rq.lock, flags); 4116 4117 return err; 4118 } 4119 4120 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4121 { 4122 switch (mlx5_state) { 4123 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4124 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4125 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4126 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4127 case MLX5_QP_STATE_SQ_DRAINING: 4128 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4129 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4130 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4131 default: return -1; 4132 } 4133 } 4134 4135 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4136 { 4137 switch (mlx5_mig_state) { 4138 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4139 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4140 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4141 default: return -1; 4142 } 4143 } 4144 4145 static int to_ib_qp_access_flags(int mlx5_flags) 4146 { 4147 int ib_flags = 0; 4148 4149 if (mlx5_flags & MLX5_QP_BIT_RRE) 4150 ib_flags |= IB_ACCESS_REMOTE_READ; 4151 if (mlx5_flags & MLX5_QP_BIT_RWE) 4152 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4153 if (mlx5_flags & MLX5_QP_BIT_RAE) 4154 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4155 4156 return ib_flags; 4157 } 4158 4159 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4160 struct mlx5_qp_path *path) 4161 { 4162 struct mlx5_core_dev *dev = ibdev->mdev; 4163 4164 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4165 ib_ah_attr->port_num = path->port; 4166 4167 if (ib_ah_attr->port_num == 0 || 4168 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4169 return; 4170 4171 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4172 4173 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4174 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4175 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4176 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4177 if (ib_ah_attr->ah_flags) { 4178 ib_ah_attr->grh.sgid_index = path->mgid_index; 4179 ib_ah_attr->grh.hop_limit = path->hop_limit; 4180 ib_ah_attr->grh.traffic_class = 4181 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4182 ib_ah_attr->grh.flow_label = 4183 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4184 memcpy(ib_ah_attr->grh.dgid.raw, 4185 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4186 } 4187 } 4188 4189 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4190 struct mlx5_ib_sq *sq, 4191 u8 *sq_state) 4192 { 4193 void *out; 4194 void *sqc; 4195 int inlen; 4196 int err; 4197 4198 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4199 out = mlx5_vzalloc(inlen); 4200 if (!out) 4201 return -ENOMEM; 4202 4203 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4204 if (err) 4205 goto out; 4206 4207 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4208 *sq_state = MLX5_GET(sqc, sqc, state); 4209 sq->state = *sq_state; 4210 4211 out: 4212 kvfree(out); 4213 return err; 4214 } 4215 4216 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4217 struct mlx5_ib_rq *rq, 4218 u8 *rq_state) 4219 { 4220 void *out; 4221 void *rqc; 4222 int inlen; 4223 int err; 4224 4225 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4226 out = mlx5_vzalloc(inlen); 4227 if (!out) 4228 return -ENOMEM; 4229 4230 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4231 if (err) 4232 goto out; 4233 4234 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4235 *rq_state = MLX5_GET(rqc, rqc, state); 4236 rq->state = *rq_state; 4237 4238 out: 4239 kvfree(out); 4240 return err; 4241 } 4242 4243 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4244 struct mlx5_ib_qp *qp, u8 *qp_state) 4245 { 4246 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4247 [MLX5_RQC_STATE_RST] = { 4248 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4249 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4250 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4251 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4252 }, 4253 [MLX5_RQC_STATE_RDY] = { 4254 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4255 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4256 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4257 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4258 }, 4259 [MLX5_RQC_STATE_ERR] = { 4260 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4261 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4262 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4263 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4264 }, 4265 [MLX5_RQ_STATE_NA] = { 4266 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4267 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4268 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4269 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4270 }, 4271 }; 4272 4273 *qp_state = sqrq_trans[rq_state][sq_state]; 4274 4275 if (*qp_state == MLX5_QP_STATE_BAD) { 4276 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4277 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4278 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4279 return -EINVAL; 4280 } 4281 4282 if (*qp_state == MLX5_QP_STATE) 4283 *qp_state = qp->state; 4284 4285 return 0; 4286 } 4287 4288 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4289 struct mlx5_ib_qp *qp, 4290 u8 *raw_packet_qp_state) 4291 { 4292 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4293 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4294 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4295 int err; 4296 u8 sq_state = MLX5_SQ_STATE_NA; 4297 u8 rq_state = MLX5_RQ_STATE_NA; 4298 4299 if (qp->sq.wqe_cnt) { 4300 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4301 if (err) 4302 return err; 4303 } 4304 4305 if (qp->rq.wqe_cnt) { 4306 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4307 if (err) 4308 return err; 4309 } 4310 4311 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4312 raw_packet_qp_state); 4313 } 4314 4315 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4316 struct ib_qp_attr *qp_attr) 4317 { 4318 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4319 struct mlx5_qp_context *context; 4320 int mlx5_state; 4321 u32 *outb; 4322 int err = 0; 4323 4324 outb = kzalloc(outlen, GFP_KERNEL); 4325 if (!outb) 4326 return -ENOMEM; 4327 4328 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4329 outlen); 4330 if (err) 4331 goto out; 4332 4333 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4334 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4335 4336 mlx5_state = be32_to_cpu(context->flags) >> 28; 4337 4338 qp->state = to_ib_qp_state(mlx5_state); 4339 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4340 qp_attr->path_mig_state = 4341 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4342 qp_attr->qkey = be32_to_cpu(context->qkey); 4343 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4344 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4345 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4346 qp_attr->qp_access_flags = 4347 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4348 4349 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4350 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4351 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4352 qp_attr->alt_pkey_index = 4353 be16_to_cpu(context->alt_path.pkey_index); 4354 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4355 } 4356 4357 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4358 qp_attr->port_num = context->pri_path.port; 4359 4360 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4361 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4362 4363 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4364 4365 qp_attr->max_dest_rd_atomic = 4366 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4367 qp_attr->min_rnr_timer = 4368 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4369 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4370 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4371 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4372 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4373 4374 out: 4375 kfree(outb); 4376 return err; 4377 } 4378 4379 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4380 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4381 { 4382 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4383 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4384 int err = 0; 4385 u8 raw_packet_qp_state; 4386 4387 if (ibqp->rwq_ind_tbl) 4388 return -ENOSYS; 4389 4390 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4391 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4392 qp_init_attr); 4393 4394 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4395 /* 4396 * Wait for any outstanding page faults, in case the user frees memory 4397 * based upon this query's result. 4398 */ 4399 flush_workqueue(mlx5_ib_page_fault_wq); 4400 #endif 4401 4402 mutex_lock(&qp->mutex); 4403 4404 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4405 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4406 if (err) 4407 goto out; 4408 qp->state = raw_packet_qp_state; 4409 qp_attr->port_num = 1; 4410 } else { 4411 err = query_qp_attr(dev, qp, qp_attr); 4412 if (err) 4413 goto out; 4414 } 4415 4416 qp_attr->qp_state = qp->state; 4417 qp_attr->cur_qp_state = qp_attr->qp_state; 4418 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4419 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4420 4421 if (!ibqp->uobject) { 4422 qp_attr->cap.max_send_wr = qp->sq.max_post; 4423 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4424 qp_init_attr->qp_context = ibqp->qp_context; 4425 } else { 4426 qp_attr->cap.max_send_wr = 0; 4427 qp_attr->cap.max_send_sge = 0; 4428 } 4429 4430 qp_init_attr->qp_type = ibqp->qp_type; 4431 qp_init_attr->recv_cq = ibqp->recv_cq; 4432 qp_init_attr->send_cq = ibqp->send_cq; 4433 qp_init_attr->srq = ibqp->srq; 4434 qp_attr->cap.max_inline_data = qp->max_inline_data; 4435 4436 qp_init_attr->cap = qp_attr->cap; 4437 4438 qp_init_attr->create_flags = 0; 4439 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4440 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4441 4442 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4443 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4444 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4445 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4446 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4447 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4448 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4449 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4450 4451 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4452 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4453 4454 out: 4455 mutex_unlock(&qp->mutex); 4456 return err; 4457 } 4458 4459 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4460 struct ib_ucontext *context, 4461 struct ib_udata *udata) 4462 { 4463 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4464 struct mlx5_ib_xrcd *xrcd; 4465 int err; 4466 4467 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4468 return ERR_PTR(-ENOSYS); 4469 4470 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4471 if (!xrcd) 4472 return ERR_PTR(-ENOMEM); 4473 4474 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4475 if (err) { 4476 kfree(xrcd); 4477 return ERR_PTR(-ENOMEM); 4478 } 4479 4480 return &xrcd->ibxrcd; 4481 } 4482 4483 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4484 { 4485 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4486 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4487 int err; 4488 4489 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4490 if (err) { 4491 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4492 return err; 4493 } 4494 4495 kfree(xrcd); 4496 4497 return 0; 4498 } 4499 4500 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4501 struct ib_wq_init_attr *init_attr) 4502 { 4503 struct mlx5_ib_dev *dev; 4504 __be64 *rq_pas0; 4505 void *in; 4506 void *rqc; 4507 void *wq; 4508 int inlen; 4509 int err; 4510 4511 dev = to_mdev(pd->device); 4512 4513 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4514 in = mlx5_vzalloc(inlen); 4515 if (!in) 4516 return -ENOMEM; 4517 4518 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4519 MLX5_SET(rqc, rqc, mem_rq_type, 4520 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4521 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4522 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4523 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4524 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4525 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4526 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4527 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4528 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4529 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4530 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4531 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4532 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4533 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4534 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4535 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4536 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4537 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn); 4538 kvfree(in); 4539 return err; 4540 } 4541 4542 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4543 struct ib_wq_init_attr *wq_init_attr, 4544 struct mlx5_ib_create_wq *ucmd, 4545 struct mlx5_ib_rwq *rwq) 4546 { 4547 /* Sanity check RQ size before proceeding */ 4548 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4549 return -EINVAL; 4550 4551 if (!ucmd->rq_wqe_count) 4552 return -EINVAL; 4553 4554 rwq->wqe_count = ucmd->rq_wqe_count; 4555 rwq->wqe_shift = ucmd->rq_wqe_shift; 4556 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4557 rwq->log_rq_stride = rwq->wqe_shift; 4558 rwq->log_rq_size = ilog2(rwq->wqe_count); 4559 return 0; 4560 } 4561 4562 static int prepare_user_rq(struct ib_pd *pd, 4563 struct ib_wq_init_attr *init_attr, 4564 struct ib_udata *udata, 4565 struct mlx5_ib_rwq *rwq) 4566 { 4567 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4568 struct mlx5_ib_create_wq ucmd = {}; 4569 int err; 4570 size_t required_cmd_sz; 4571 4572 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4573 if (udata->inlen < required_cmd_sz) { 4574 mlx5_ib_dbg(dev, "invalid inlen\n"); 4575 return -EINVAL; 4576 } 4577 4578 if (udata->inlen > sizeof(ucmd) && 4579 !ib_is_udata_cleared(udata, sizeof(ucmd), 4580 udata->inlen - sizeof(ucmd))) { 4581 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4582 return -EOPNOTSUPP; 4583 } 4584 4585 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4586 mlx5_ib_dbg(dev, "copy failed\n"); 4587 return -EFAULT; 4588 } 4589 4590 if (ucmd.comp_mask) { 4591 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4592 return -EOPNOTSUPP; 4593 } 4594 4595 if (ucmd.reserved) { 4596 mlx5_ib_dbg(dev, "invalid reserved\n"); 4597 return -EOPNOTSUPP; 4598 } 4599 4600 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4601 if (err) { 4602 mlx5_ib_dbg(dev, "err %d\n", err); 4603 return err; 4604 } 4605 4606 err = create_user_rq(dev, pd, rwq, &ucmd); 4607 if (err) { 4608 mlx5_ib_dbg(dev, "err %d\n", err); 4609 if (err) 4610 return err; 4611 } 4612 4613 rwq->user_index = ucmd.user_index; 4614 return 0; 4615 } 4616 4617 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4618 struct ib_wq_init_attr *init_attr, 4619 struct ib_udata *udata) 4620 { 4621 struct mlx5_ib_dev *dev; 4622 struct mlx5_ib_rwq *rwq; 4623 struct mlx5_ib_create_wq_resp resp = {}; 4624 size_t min_resp_len; 4625 int err; 4626 4627 if (!udata) 4628 return ERR_PTR(-ENOSYS); 4629 4630 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4631 if (udata->outlen && udata->outlen < min_resp_len) 4632 return ERR_PTR(-EINVAL); 4633 4634 dev = to_mdev(pd->device); 4635 switch (init_attr->wq_type) { 4636 case IB_WQT_RQ: 4637 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4638 if (!rwq) 4639 return ERR_PTR(-ENOMEM); 4640 err = prepare_user_rq(pd, init_attr, udata, rwq); 4641 if (err) 4642 goto err; 4643 err = create_rq(rwq, pd, init_attr); 4644 if (err) 4645 goto err_user_rq; 4646 break; 4647 default: 4648 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4649 init_attr->wq_type); 4650 return ERR_PTR(-EINVAL); 4651 } 4652 4653 rwq->ibwq.wq_num = rwq->rqn; 4654 rwq->ibwq.state = IB_WQS_RESET; 4655 if (udata->outlen) { 4656 resp.response_length = offsetof(typeof(resp), response_length) + 4657 sizeof(resp.response_length); 4658 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4659 if (err) 4660 goto err_copy; 4661 } 4662 4663 return &rwq->ibwq; 4664 4665 err_copy: 4666 mlx5_core_destroy_rq(dev->mdev, rwq->rqn); 4667 err_user_rq: 4668 destroy_user_rq(pd, rwq); 4669 err: 4670 kfree(rwq); 4671 return ERR_PTR(err); 4672 } 4673 4674 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4675 { 4676 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4677 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4678 4679 mlx5_core_destroy_rq(dev->mdev, rwq->rqn); 4680 destroy_user_rq(wq->pd, rwq); 4681 kfree(rwq); 4682 4683 return 0; 4684 } 4685 4686 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4687 struct ib_rwq_ind_table_init_attr *init_attr, 4688 struct ib_udata *udata) 4689 { 4690 struct mlx5_ib_dev *dev = to_mdev(device); 4691 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4692 int sz = 1 << init_attr->log_ind_tbl_size; 4693 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4694 size_t min_resp_len; 4695 int inlen; 4696 int err; 4697 int i; 4698 u32 *in; 4699 void *rqtc; 4700 4701 if (udata->inlen > 0 && 4702 !ib_is_udata_cleared(udata, 0, 4703 udata->inlen)) 4704 return ERR_PTR(-EOPNOTSUPP); 4705 4706 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4707 if (udata->outlen && udata->outlen < min_resp_len) 4708 return ERR_PTR(-EINVAL); 4709 4710 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4711 if (!rwq_ind_tbl) 4712 return ERR_PTR(-ENOMEM); 4713 4714 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4715 in = mlx5_vzalloc(inlen); 4716 if (!in) { 4717 err = -ENOMEM; 4718 goto err; 4719 } 4720 4721 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4722 4723 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4724 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4725 4726 for (i = 0; i < sz; i++) 4727 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4728 4729 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4730 kvfree(in); 4731 4732 if (err) 4733 goto err; 4734 4735 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4736 if (udata->outlen) { 4737 resp.response_length = offsetof(typeof(resp), response_length) + 4738 sizeof(resp.response_length); 4739 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4740 if (err) 4741 goto err_copy; 4742 } 4743 4744 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4745 4746 err_copy: 4747 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4748 err: 4749 kfree(rwq_ind_tbl); 4750 return ERR_PTR(err); 4751 } 4752 4753 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4754 { 4755 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4756 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4757 4758 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4759 4760 kfree(rwq_ind_tbl); 4761 return 0; 4762 } 4763 4764 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4765 u32 wq_attr_mask, struct ib_udata *udata) 4766 { 4767 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4768 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4769 struct mlx5_ib_modify_wq ucmd = {}; 4770 size_t required_cmd_sz; 4771 int curr_wq_state; 4772 int wq_state; 4773 int inlen; 4774 int err; 4775 void *rqc; 4776 void *in; 4777 4778 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4779 if (udata->inlen < required_cmd_sz) 4780 return -EINVAL; 4781 4782 if (udata->inlen > sizeof(ucmd) && 4783 !ib_is_udata_cleared(udata, sizeof(ucmd), 4784 udata->inlen - sizeof(ucmd))) 4785 return -EOPNOTSUPP; 4786 4787 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4788 return -EFAULT; 4789 4790 if (ucmd.comp_mask || ucmd.reserved) 4791 return -EOPNOTSUPP; 4792 4793 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4794 in = mlx5_vzalloc(inlen); 4795 if (!in) 4796 return -ENOMEM; 4797 4798 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4799 4800 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 4801 wq_attr->curr_wq_state : wq->state; 4802 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 4803 wq_attr->wq_state : curr_wq_state; 4804 if (curr_wq_state == IB_WQS_ERR) 4805 curr_wq_state = MLX5_RQC_STATE_ERR; 4806 if (wq_state == IB_WQS_ERR) 4807 wq_state = MLX5_RQC_STATE_ERR; 4808 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 4809 MLX5_SET(rqc, rqc, state, wq_state); 4810 4811 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen); 4812 kvfree(in); 4813 if (!err) 4814 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 4815 4816 return err; 4817 } 4818