1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/etherdevice.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "umr.h" 44 #include "qp.h" 45 #include "wr.h" 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum raw_qp_set_mask_map { 59 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 60 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 61 }; 62 63 enum { 64 MLX5_QP_RM_GO_BACK_N = 0x1, 65 }; 66 67 struct mlx5_modify_raw_qp_param { 68 u16 operation; 69 70 u32 set_mask; /* raw_qp_set_mask_map */ 71 72 struct mlx5_rate_limit rl; 73 74 u8 rq_q_ctr_id; 75 u32 port; 76 }; 77 78 struct mlx5_ib_qp_event_work { 79 struct work_struct work; 80 struct mlx5_core_qp *qp; 81 int type; 82 }; 83 84 static struct workqueue_struct *mlx5_ib_qp_event_wq; 85 86 static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90 static int is_qp0(enum ib_qp_type qp_type) 91 { 92 return qp_type == IB_QPT_SMI; 93 } 94 95 static int is_sqp(enum ib_qp_type qp_type) 96 { 97 return is_qp0(qp_type) || is_qp1(qp_type); 98 } 99 100 /** 101 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 102 * to kernel buffer 103 * 104 * @umem: User space memory where the WQ is 105 * @buffer: buffer to copy to 106 * @buflen: buffer length 107 * @wqe_index: index of WQE to copy from 108 * @wq_offset: offset to start of WQ 109 * @wq_wqe_cnt: number of WQEs in WQ 110 * @wq_wqe_shift: log2 of WQE size 111 * @bcnt: number of bytes to copy 112 * @bytes_copied: number of bytes to copy (return value) 113 * 114 * Copies from start of WQE bcnt or less bytes. 115 * Does not gurantee to copy the entire WQE. 116 * 117 * Return: zero on success, or an error code. 118 */ 119 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 120 size_t buflen, int wqe_index, 121 int wq_offset, int wq_wqe_cnt, 122 int wq_wqe_shift, int bcnt, 123 size_t *bytes_copied) 124 { 125 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 126 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 127 size_t copy_length; 128 int ret; 129 130 /* don't copy more than requested, more than buffer length or 131 * beyond WQ end 132 */ 133 copy_length = min_t(u32, buflen, wq_end - offset); 134 copy_length = min_t(u32, copy_length, bcnt); 135 136 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 137 if (ret) 138 return ret; 139 140 if (!ret && bytes_copied) 141 *bytes_copied = copy_length; 142 143 return 0; 144 } 145 146 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 147 void *buffer, size_t buflen, size_t *bc) 148 { 149 struct mlx5_wqe_ctrl_seg *ctrl; 150 size_t bytes_copied = 0; 151 size_t wqe_length; 152 void *p; 153 int ds; 154 155 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 156 157 /* read the control segment first */ 158 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 159 ctrl = p; 160 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 161 wqe_length = ds * MLX5_WQE_DS_UNITS; 162 163 /* read rest of WQE if it spreads over more than one stride */ 164 while (bytes_copied < wqe_length) { 165 size_t copy_length = 166 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 167 168 if (!copy_length) 169 break; 170 171 memcpy(buffer + bytes_copied, p, copy_length); 172 bytes_copied += copy_length; 173 174 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 175 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 176 } 177 *bc = bytes_copied; 178 return 0; 179 } 180 181 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 182 void *buffer, size_t buflen, size_t *bc) 183 { 184 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 185 struct ib_umem *umem = base->ubuffer.umem; 186 struct mlx5_ib_wq *wq = &qp->sq; 187 struct mlx5_wqe_ctrl_seg *ctrl; 188 size_t bytes_copied; 189 size_t bytes_copied2; 190 size_t wqe_length; 191 int ret; 192 int ds; 193 194 /* at first read as much as possible */ 195 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 196 wq->offset, wq->wqe_cnt, 197 wq->wqe_shift, buflen, 198 &bytes_copied); 199 if (ret) 200 return ret; 201 202 /* we need at least control segment size to proceed */ 203 if (bytes_copied < sizeof(*ctrl)) 204 return -EINVAL; 205 206 ctrl = buffer; 207 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 208 wqe_length = ds * MLX5_WQE_DS_UNITS; 209 210 /* if we copied enough then we are done */ 211 if (bytes_copied >= wqe_length) { 212 *bc = bytes_copied; 213 return 0; 214 } 215 216 /* otherwise this a wrapped around wqe 217 * so read the remaining bytes starting 218 * from wqe_index 0 219 */ 220 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 221 buflen - bytes_copied, 0, wq->offset, 222 wq->wqe_cnt, wq->wqe_shift, 223 wqe_length - bytes_copied, 224 &bytes_copied2); 225 226 if (ret) 227 return ret; 228 *bc = bytes_copied + bytes_copied2; 229 return 0; 230 } 231 232 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 233 size_t buflen, size_t *bc) 234 { 235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 236 struct ib_umem *umem = base->ubuffer.umem; 237 238 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 239 return -EINVAL; 240 241 if (!umem) 242 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 243 buflen, bc); 244 245 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 246 } 247 248 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 249 void *buffer, size_t buflen, size_t *bc) 250 { 251 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 252 struct ib_umem *umem = base->ubuffer.umem; 253 struct mlx5_ib_wq *wq = &qp->rq; 254 size_t bytes_copied; 255 int ret; 256 257 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 258 wq->offset, wq->wqe_cnt, 259 wq->wqe_shift, buflen, 260 &bytes_copied); 261 262 if (ret) 263 return ret; 264 *bc = bytes_copied; 265 return 0; 266 } 267 268 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 269 size_t buflen, size_t *bc) 270 { 271 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 272 struct ib_umem *umem = base->ubuffer.umem; 273 struct mlx5_ib_wq *wq = &qp->rq; 274 size_t wqe_size = 1 << wq->wqe_shift; 275 276 if (buflen < wqe_size) 277 return -EINVAL; 278 279 if (!umem) 280 return -EOPNOTSUPP; 281 282 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 283 } 284 285 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 286 void *buffer, size_t buflen, size_t *bc) 287 { 288 struct ib_umem *umem = srq->umem; 289 size_t bytes_copied; 290 int ret; 291 292 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 293 srq->msrq.max, srq->msrq.wqe_shift, 294 buflen, &bytes_copied); 295 296 if (ret) 297 return ret; 298 *bc = bytes_copied; 299 return 0; 300 } 301 302 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 303 size_t buflen, size_t *bc) 304 { 305 struct ib_umem *umem = srq->umem; 306 size_t wqe_size = 1 << srq->msrq.wqe_shift; 307 308 if (buflen < wqe_size) 309 return -EINVAL; 310 311 if (!umem) 312 return -EOPNOTSUPP; 313 314 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 315 } 316 317 static void mlx5_ib_qp_err_syndrome(struct ib_qp *ibqp) 318 { 319 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 320 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 321 struct mlx5_ib_qp *qp = to_mqp(ibqp); 322 void *pas_ext_union, *err_syn; 323 u32 *outb; 324 int err; 325 326 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || 327 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) 328 return; 329 330 outb = kzalloc(outlen, GFP_KERNEL); 331 if (!outb) 332 return; 333 334 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 335 true); 336 if (err) 337 goto out; 338 339 pas_ext_union = 340 MLX5_ADDR_OF(query_qp_out, outb, qp_pas_or_qpc_ext_and_pas); 341 err_syn = MLX5_ADDR_OF(qpc_extension_and_pas_list_in, pas_ext_union, 342 qpc_data_extension.error_syndrome); 343 344 pr_err("%s/%d: QP %d error: %s (0x%x 0x%x 0x%x)\n", 345 ibqp->device->name, ibqp->port, ibqp->qp_num, 346 ib_wc_status_msg( 347 MLX5_GET(cqe_error_syndrome, err_syn, syndrome)), 348 MLX5_GET(cqe_error_syndrome, err_syn, vendor_error_syndrome), 349 MLX5_GET(cqe_error_syndrome, err_syn, hw_syndrome_type), 350 MLX5_GET(cqe_error_syndrome, err_syn, hw_error_syndrome)); 351 out: 352 kfree(outb); 353 } 354 355 static void mlx5_ib_handle_qp_event(struct work_struct *_work) 356 { 357 struct mlx5_ib_qp_event_work *qpe_work = 358 container_of(_work, struct mlx5_ib_qp_event_work, work); 359 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 360 struct ib_event event = {}; 361 362 event.device = ibqp->device; 363 event.element.qp = ibqp; 364 switch (qpe_work->type) { 365 case MLX5_EVENT_TYPE_PATH_MIG: 366 event.event = IB_EVENT_PATH_MIG; 367 break; 368 case MLX5_EVENT_TYPE_COMM_EST: 369 event.event = IB_EVENT_COMM_EST; 370 break; 371 case MLX5_EVENT_TYPE_SQ_DRAINED: 372 event.event = IB_EVENT_SQ_DRAINED; 373 break; 374 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 375 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 376 break; 377 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 378 event.event = IB_EVENT_QP_FATAL; 379 break; 380 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 381 event.event = IB_EVENT_PATH_MIG_ERR; 382 break; 383 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 384 event.event = IB_EVENT_QP_REQ_ERR; 385 break; 386 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 387 event.event = IB_EVENT_QP_ACCESS_ERR; 388 break; 389 default: 390 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", 391 qpe_work->type, qpe_work->qp->qpn); 392 goto out; 393 } 394 395 if ((event.event == IB_EVENT_QP_FATAL) || 396 (event.event == IB_EVENT_QP_ACCESS_ERR)) 397 mlx5_ib_qp_err_syndrome(ibqp); 398 399 ibqp->event_handler(&event, ibqp->qp_context); 400 401 out: 402 mlx5_core_res_put(&qpe_work->qp->common); 403 kfree(qpe_work); 404 } 405 406 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 407 { 408 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 409 struct mlx5_ib_qp_event_work *qpe_work; 410 411 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 412 /* This event is only valid for trans_qps */ 413 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 414 } 415 416 if (!ibqp->event_handler) 417 goto out_no_handler; 418 419 qpe_work = kzalloc(sizeof(*qpe_work), GFP_ATOMIC); 420 if (!qpe_work) 421 goto out_no_handler; 422 423 qpe_work->qp = qp; 424 qpe_work->type = type; 425 INIT_WORK(&qpe_work->work, mlx5_ib_handle_qp_event); 426 queue_work(mlx5_ib_qp_event_wq, &qpe_work->work); 427 return; 428 429 out_no_handler: 430 mlx5_core_res_put(&qp->common); 431 } 432 433 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 434 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 435 { 436 int wqe_size; 437 int wq_size; 438 439 /* Sanity check RQ size before proceeding */ 440 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 441 return -EINVAL; 442 443 if (!has_rq) { 444 qp->rq.max_gs = 0; 445 qp->rq.wqe_cnt = 0; 446 qp->rq.wqe_shift = 0; 447 cap->max_recv_wr = 0; 448 cap->max_recv_sge = 0; 449 } else { 450 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 451 452 if (ucmd) { 453 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 454 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 455 return -EINVAL; 456 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 457 if ((1 << qp->rq.wqe_shift) / 458 sizeof(struct mlx5_wqe_data_seg) < 459 wq_sig) 460 return -EINVAL; 461 qp->rq.max_gs = 462 (1 << qp->rq.wqe_shift) / 463 sizeof(struct mlx5_wqe_data_seg) - 464 wq_sig; 465 qp->rq.max_post = qp->rq.wqe_cnt; 466 } else { 467 wqe_size = 468 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 469 0; 470 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 471 wqe_size = roundup_pow_of_two(wqe_size); 472 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 473 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 474 qp->rq.wqe_cnt = wq_size / wqe_size; 475 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 476 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 477 wqe_size, 478 MLX5_CAP_GEN(dev->mdev, 479 max_wqe_sz_rq)); 480 return -EINVAL; 481 } 482 qp->rq.wqe_shift = ilog2(wqe_size); 483 qp->rq.max_gs = 484 (1 << qp->rq.wqe_shift) / 485 sizeof(struct mlx5_wqe_data_seg) - 486 wq_sig; 487 qp->rq.max_post = qp->rq.wqe_cnt; 488 } 489 } 490 491 return 0; 492 } 493 494 static int sq_overhead(struct ib_qp_init_attr *attr) 495 { 496 int size = 0; 497 498 switch (attr->qp_type) { 499 case IB_QPT_XRC_INI: 500 size += sizeof(struct mlx5_wqe_xrc_seg); 501 fallthrough; 502 case IB_QPT_RC: 503 size += sizeof(struct mlx5_wqe_ctrl_seg) + 504 max(sizeof(struct mlx5_wqe_atomic_seg) + 505 sizeof(struct mlx5_wqe_raddr_seg), 506 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 507 sizeof(struct mlx5_mkey_seg) + 508 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 509 MLX5_IB_UMR_OCTOWORD); 510 break; 511 512 case IB_QPT_XRC_TGT: 513 return 0; 514 515 case IB_QPT_UC: 516 size += sizeof(struct mlx5_wqe_ctrl_seg) + 517 max(sizeof(struct mlx5_wqe_raddr_seg), 518 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 519 sizeof(struct mlx5_mkey_seg)); 520 break; 521 522 case IB_QPT_UD: 523 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 524 size += sizeof(struct mlx5_wqe_eth_pad) + 525 sizeof(struct mlx5_wqe_eth_seg); 526 fallthrough; 527 case IB_QPT_SMI: 528 case MLX5_IB_QPT_HW_GSI: 529 size += sizeof(struct mlx5_wqe_ctrl_seg) + 530 sizeof(struct mlx5_wqe_datagram_seg); 531 break; 532 533 case MLX5_IB_QPT_REG_UMR: 534 size += sizeof(struct mlx5_wqe_ctrl_seg) + 535 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 536 sizeof(struct mlx5_mkey_seg); 537 break; 538 539 default: 540 return -EINVAL; 541 } 542 543 return size; 544 } 545 546 static int calc_send_wqe(struct ib_qp_init_attr *attr) 547 { 548 int inl_size = 0; 549 int size; 550 551 size = sq_overhead(attr); 552 if (size < 0) 553 return size; 554 555 if (attr->cap.max_inline_data) { 556 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 557 attr->cap.max_inline_data; 558 } 559 560 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 561 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 562 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 563 return MLX5_SIG_WQE_SIZE; 564 else 565 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 566 } 567 568 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 569 { 570 int max_sge; 571 572 if (attr->qp_type == IB_QPT_RC) 573 max_sge = (min_t(int, wqe_size, 512) - 574 sizeof(struct mlx5_wqe_ctrl_seg) - 575 sizeof(struct mlx5_wqe_raddr_seg)) / 576 sizeof(struct mlx5_wqe_data_seg); 577 else if (attr->qp_type == IB_QPT_XRC_INI) 578 max_sge = (min_t(int, wqe_size, 512) - 579 sizeof(struct mlx5_wqe_ctrl_seg) - 580 sizeof(struct mlx5_wqe_xrc_seg) - 581 sizeof(struct mlx5_wqe_raddr_seg)) / 582 sizeof(struct mlx5_wqe_data_seg); 583 else 584 max_sge = (wqe_size - sq_overhead(attr)) / 585 sizeof(struct mlx5_wqe_data_seg); 586 587 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 588 sizeof(struct mlx5_wqe_data_seg)); 589 } 590 591 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 592 struct mlx5_ib_qp *qp) 593 { 594 int wqe_size; 595 int wq_size; 596 597 if (!attr->cap.max_send_wr) 598 return 0; 599 600 wqe_size = calc_send_wqe(attr); 601 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 602 if (wqe_size < 0) 603 return wqe_size; 604 605 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 606 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 607 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 608 return -EINVAL; 609 } 610 611 qp->max_inline_data = wqe_size - sq_overhead(attr) - 612 sizeof(struct mlx5_wqe_inline_seg); 613 attr->cap.max_inline_data = qp->max_inline_data; 614 615 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 616 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 617 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 618 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 619 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 620 qp->sq.wqe_cnt, 621 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 622 return -ENOMEM; 623 } 624 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 625 qp->sq.max_gs = get_send_sge(attr, wqe_size); 626 if (qp->sq.max_gs < attr->cap.max_send_sge) 627 return -ENOMEM; 628 629 attr->cap.max_send_sge = qp->sq.max_gs; 630 qp->sq.max_post = wq_size / wqe_size; 631 attr->cap.max_send_wr = qp->sq.max_post; 632 633 return wq_size; 634 } 635 636 static int set_user_buf_size(struct mlx5_ib_dev *dev, 637 struct mlx5_ib_qp *qp, 638 struct mlx5_ib_create_qp *ucmd, 639 struct mlx5_ib_qp_base *base, 640 struct ib_qp_init_attr *attr) 641 { 642 int desc_sz = 1 << qp->sq.wqe_shift; 643 644 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 645 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 646 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 647 return -EINVAL; 648 } 649 650 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 651 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 652 ucmd->sq_wqe_count); 653 return -EINVAL; 654 } 655 656 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 657 658 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 659 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 660 qp->sq.wqe_cnt, 661 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 662 return -EINVAL; 663 } 664 665 if (attr->qp_type == IB_QPT_RAW_PACKET || 666 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 667 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 668 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 669 } else { 670 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 671 (qp->sq.wqe_cnt << 6); 672 } 673 674 return 0; 675 } 676 677 static int qp_has_rq(struct ib_qp_init_attr *attr) 678 { 679 if (attr->qp_type == IB_QPT_XRC_INI || 680 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 681 attr->qp_type == MLX5_IB_QPT_REG_UMR || 682 !attr->cap.max_recv_wr) 683 return 0; 684 685 return 1; 686 } 687 688 enum { 689 /* this is the first blue flame register in the array of bfregs assigned 690 * to a processes. Since we do not use it for blue flame but rather 691 * regular 64 bit doorbells, we do not need a lock for maintaiing 692 * "odd/even" order 693 */ 694 NUM_NON_BLUE_FLAME_BFREGS = 1, 695 }; 696 697 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 698 { 699 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 700 bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR; 701 } 702 703 static int num_med_bfreg(struct mlx5_ib_dev *dev, 704 struct mlx5_bfreg_info *bfregi) 705 { 706 int n; 707 708 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 709 NUM_NON_BLUE_FLAME_BFREGS; 710 711 return n >= 0 ? n : 0; 712 } 713 714 static int first_med_bfreg(struct mlx5_ib_dev *dev, 715 struct mlx5_bfreg_info *bfregi) 716 { 717 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 718 } 719 720 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 721 struct mlx5_bfreg_info *bfregi) 722 { 723 int med; 724 725 med = num_med_bfreg(dev, bfregi); 726 return ++med; 727 } 728 729 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 730 struct mlx5_bfreg_info *bfregi) 731 { 732 int i; 733 734 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 735 if (!bfregi->count[i]) { 736 bfregi->count[i]++; 737 return i; 738 } 739 } 740 741 return -ENOMEM; 742 } 743 744 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 745 struct mlx5_bfreg_info *bfregi) 746 { 747 int minidx = first_med_bfreg(dev, bfregi); 748 int i; 749 750 if (minidx < 0) 751 return minidx; 752 753 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 754 if (bfregi->count[i] < bfregi->count[minidx]) 755 minidx = i; 756 if (!bfregi->count[minidx]) 757 break; 758 } 759 760 bfregi->count[minidx]++; 761 return minidx; 762 } 763 764 static int alloc_bfreg(struct mlx5_ib_dev *dev, 765 struct mlx5_bfreg_info *bfregi) 766 { 767 int bfregn = -ENOMEM; 768 769 if (bfregi->lib_uar_dyn) 770 return -EINVAL; 771 772 mutex_lock(&bfregi->lock); 773 if (bfregi->ver >= 2) { 774 bfregn = alloc_high_class_bfreg(dev, bfregi); 775 if (bfregn < 0) 776 bfregn = alloc_med_class_bfreg(dev, bfregi); 777 } 778 779 if (bfregn < 0) { 780 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 781 bfregn = 0; 782 bfregi->count[bfregn]++; 783 } 784 mutex_unlock(&bfregi->lock); 785 786 return bfregn; 787 } 788 789 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 790 { 791 mutex_lock(&bfregi->lock); 792 bfregi->count[bfregn]--; 793 mutex_unlock(&bfregi->lock); 794 } 795 796 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 797 { 798 switch (state) { 799 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 800 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 801 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 802 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 803 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 804 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 805 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 806 default: return -1; 807 } 808 } 809 810 static int to_mlx5_st(enum ib_qp_type type) 811 { 812 switch (type) { 813 case IB_QPT_RC: return MLX5_QP_ST_RC; 814 case IB_QPT_UC: return MLX5_QP_ST_UC; 815 case IB_QPT_UD: return MLX5_QP_ST_UD; 816 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 817 case IB_QPT_XRC_INI: 818 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 819 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 820 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 821 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 822 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 823 default: return -EINVAL; 824 } 825 } 826 827 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 828 struct mlx5_ib_cq *recv_cq); 829 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 830 struct mlx5_ib_cq *recv_cq); 831 832 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 833 struct mlx5_bfreg_info *bfregi, u32 bfregn, 834 bool dyn_bfreg) 835 { 836 unsigned int bfregs_per_sys_page; 837 u32 index_of_sys_page; 838 u32 offset; 839 840 if (bfregi->lib_uar_dyn) 841 return -EINVAL; 842 843 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 844 MLX5_NON_FP_BFREGS_PER_UAR; 845 index_of_sys_page = bfregn / bfregs_per_sys_page; 846 847 if (dyn_bfreg) { 848 index_of_sys_page += bfregi->num_static_sys_pages; 849 850 if (index_of_sys_page >= bfregi->num_sys_pages) 851 return -EINVAL; 852 853 if (bfregn > bfregi->num_dyn_bfregs || 854 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 855 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 856 return -EINVAL; 857 } 858 } 859 860 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 861 return bfregi->sys_pages[index_of_sys_page] + offset; 862 } 863 864 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 865 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 866 { 867 struct mlx5_ib_ucontext *context = 868 rdma_udata_to_drv_context( 869 udata, 870 struct mlx5_ib_ucontext, 871 ibucontext); 872 873 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 874 atomic_dec(&dev->delay_drop.rqs_cnt); 875 876 mlx5_ib_db_unmap_user(context, &rwq->db); 877 ib_umem_release(rwq->umem); 878 } 879 880 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 881 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 882 struct mlx5_ib_create_wq *ucmd) 883 { 884 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 885 udata, struct mlx5_ib_ucontext, ibucontext); 886 unsigned long page_size = 0; 887 u32 offset = 0; 888 int err; 889 890 if (!ucmd->buf_addr) 891 return -EINVAL; 892 893 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 894 if (IS_ERR(rwq->umem)) { 895 mlx5_ib_dbg(dev, "umem_get failed\n"); 896 err = PTR_ERR(rwq->umem); 897 return err; 898 } 899 900 page_size = mlx5_umem_find_best_quantized_pgoff( 901 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 902 page_offset, 64, &rwq->rq_page_offset); 903 if (!page_size) { 904 mlx5_ib_warn(dev, "bad offset\n"); 905 err = -EINVAL; 906 goto err_umem; 907 } 908 909 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 910 rwq->page_shift = order_base_2(page_size); 911 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 912 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 913 914 mlx5_ib_dbg( 915 dev, 916 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 917 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 918 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 919 offset); 920 921 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 922 if (err) { 923 mlx5_ib_dbg(dev, "map failed\n"); 924 goto err_umem; 925 } 926 927 return 0; 928 929 err_umem: 930 ib_umem_release(rwq->umem); 931 return err; 932 } 933 934 static int adjust_bfregn(struct mlx5_ib_dev *dev, 935 struct mlx5_bfreg_info *bfregi, int bfregn) 936 { 937 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 938 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 939 } 940 941 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 942 struct mlx5_ib_qp *qp, struct ib_udata *udata, 943 struct ib_qp_init_attr *attr, u32 **in, 944 struct mlx5_ib_create_qp_resp *resp, int *inlen, 945 struct mlx5_ib_qp_base *base, 946 struct mlx5_ib_create_qp *ucmd) 947 { 948 struct mlx5_ib_ucontext *context; 949 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 950 unsigned int page_offset_quantized = 0; 951 unsigned long page_size = 0; 952 int uar_index = 0; 953 int bfregn; 954 int ncont = 0; 955 __be64 *pas; 956 void *qpc; 957 int err; 958 u16 uid; 959 u32 uar_flags; 960 961 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 962 ibucontext); 963 uar_flags = qp->flags_en & 964 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 965 switch (uar_flags) { 966 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 967 uar_index = ucmd->bfreg_index; 968 bfregn = MLX5_IB_INVALID_BFREG; 969 break; 970 case MLX5_QP_FLAG_BFREG_INDEX: 971 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 972 ucmd->bfreg_index, true); 973 if (uar_index < 0) 974 return uar_index; 975 bfregn = MLX5_IB_INVALID_BFREG; 976 break; 977 case 0: 978 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 979 return -EINVAL; 980 bfregn = alloc_bfreg(dev, &context->bfregi); 981 if (bfregn < 0) 982 return bfregn; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 989 if (bfregn != MLX5_IB_INVALID_BFREG) 990 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 991 false); 992 993 qp->rq.offset = 0; 994 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 995 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 996 997 err = set_user_buf_size(dev, qp, ucmd, base, attr); 998 if (err) 999 goto err_bfreg; 1000 1001 if (ucmd->buf_addr && ubuffer->buf_size) { 1002 ubuffer->buf_addr = ucmd->buf_addr; 1003 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1004 ubuffer->buf_size, 0); 1005 if (IS_ERR(ubuffer->umem)) { 1006 err = PTR_ERR(ubuffer->umem); 1007 goto err_bfreg; 1008 } 1009 page_size = mlx5_umem_find_best_quantized_pgoff( 1010 ubuffer->umem, qpc, log_page_size, 1011 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1012 &page_offset_quantized); 1013 if (!page_size) { 1014 err = -EINVAL; 1015 goto err_umem; 1016 } 1017 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 1018 } else { 1019 ubuffer->umem = NULL; 1020 } 1021 1022 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1023 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 1024 *in = kvzalloc(*inlen, GFP_KERNEL); 1025 if (!*in) { 1026 err = -ENOMEM; 1027 goto err_umem; 1028 } 1029 1030 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 1031 MLX5_SET(create_qp_in, *in, uid, uid); 1032 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1033 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1034 if (ubuffer->umem) { 1035 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 1036 MLX5_SET(qpc, qpc, log_page_size, 1037 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1038 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 1039 } 1040 MLX5_SET(qpc, qpc, uar_page, uar_index); 1041 if (bfregn != MLX5_IB_INVALID_BFREG) 1042 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1043 else 1044 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1045 qp->bfregn = bfregn; 1046 1047 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 1048 if (err) { 1049 mlx5_ib_dbg(dev, "map failed\n"); 1050 goto err_free; 1051 } 1052 1053 return 0; 1054 1055 err_free: 1056 kvfree(*in); 1057 1058 err_umem: 1059 ib_umem_release(ubuffer->umem); 1060 1061 err_bfreg: 1062 if (bfregn != MLX5_IB_INVALID_BFREG) 1063 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1064 return err; 1065 } 1066 1067 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1068 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1069 { 1070 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1071 udata, struct mlx5_ib_ucontext, ibucontext); 1072 1073 if (udata) { 1074 /* User QP */ 1075 mlx5_ib_db_unmap_user(context, &qp->db); 1076 ib_umem_release(base->ubuffer.umem); 1077 1078 /* 1079 * Free only the BFREGs which are handled by the kernel. 1080 * BFREGs of UARs allocated dynamically are handled by user. 1081 */ 1082 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1083 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1084 return; 1085 } 1086 1087 /* Kernel QP */ 1088 kvfree(qp->sq.wqe_head); 1089 kvfree(qp->sq.w_list); 1090 kvfree(qp->sq.wrid); 1091 kvfree(qp->sq.wr_data); 1092 kvfree(qp->rq.wrid); 1093 if (qp->db.db) 1094 mlx5_db_free(dev->mdev, &qp->db); 1095 if (qp->buf.frags) 1096 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1097 } 1098 1099 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1100 struct ib_qp_init_attr *init_attr, 1101 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1102 struct mlx5_ib_qp_base *base) 1103 { 1104 int uar_index; 1105 void *qpc; 1106 int err; 1107 1108 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1109 qp->bf.bfreg = &dev->fp_bfreg; 1110 else 1111 qp->bf.bfreg = &dev->bfreg; 1112 1113 /* We need to divide by two since each register is comprised of 1114 * two buffers of identical size, namely odd and even 1115 */ 1116 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1117 uar_index = qp->bf.bfreg->index; 1118 1119 err = calc_sq_size(dev, init_attr, qp); 1120 if (err < 0) { 1121 mlx5_ib_dbg(dev, "err %d\n", err); 1122 return err; 1123 } 1124 1125 qp->rq.offset = 0; 1126 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1127 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1128 1129 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1130 &qp->buf, dev->mdev->priv.numa_node); 1131 if (err) { 1132 mlx5_ib_dbg(dev, "err %d\n", err); 1133 return err; 1134 } 1135 1136 if (qp->rq.wqe_cnt) 1137 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1138 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1139 1140 if (qp->sq.wqe_cnt) { 1141 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1142 MLX5_SEND_WQE_BB; 1143 mlx5_init_fbc_offset(qp->buf.frags + 1144 (qp->sq.offset / PAGE_SIZE), 1145 ilog2(MLX5_SEND_WQE_BB), 1146 ilog2(qp->sq.wqe_cnt), 1147 sq_strides_offset, &qp->sq.fbc); 1148 1149 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1150 } 1151 1152 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1153 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1154 *in = kvzalloc(*inlen, GFP_KERNEL); 1155 if (!*in) { 1156 err = -ENOMEM; 1157 goto err_buf; 1158 } 1159 1160 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1161 MLX5_SET(qpc, qpc, uar_page, uar_index); 1162 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1163 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1164 1165 /* Set "fast registration enabled" for all kernel QPs */ 1166 MLX5_SET(qpc, qpc, fre, 1); 1167 MLX5_SET(qpc, qpc, rlky, 1); 1168 1169 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1170 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1171 1172 mlx5_fill_page_frag_array(&qp->buf, 1173 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1174 *in, pas)); 1175 1176 err = mlx5_db_alloc(dev->mdev, &qp->db); 1177 if (err) { 1178 mlx5_ib_dbg(dev, "err %d\n", err); 1179 goto err_free; 1180 } 1181 1182 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1183 sizeof(*qp->sq.wrid), GFP_KERNEL); 1184 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1185 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1186 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1187 sizeof(*qp->rq.wrid), GFP_KERNEL); 1188 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1189 sizeof(*qp->sq.w_list), GFP_KERNEL); 1190 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1191 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1192 1193 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1194 !qp->sq.w_list || !qp->sq.wqe_head) { 1195 err = -ENOMEM; 1196 goto err_wrid; 1197 } 1198 1199 return 0; 1200 1201 err_wrid: 1202 kvfree(qp->sq.wqe_head); 1203 kvfree(qp->sq.w_list); 1204 kvfree(qp->sq.wrid); 1205 kvfree(qp->sq.wr_data); 1206 kvfree(qp->rq.wrid); 1207 mlx5_db_free(dev->mdev, &qp->db); 1208 1209 err_free: 1210 kvfree(*in); 1211 1212 err_buf: 1213 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1214 return err; 1215 } 1216 1217 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1218 { 1219 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1220 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1221 return MLX5_SRQ_RQ; 1222 else if (!qp->has_rq) 1223 return MLX5_ZERO_LEN_RQ; 1224 1225 return MLX5_NON_ZERO_RQ; 1226 } 1227 1228 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1229 struct mlx5_ib_qp *qp, 1230 struct mlx5_ib_sq *sq, u32 tdn, 1231 struct ib_pd *pd) 1232 { 1233 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1234 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1235 1236 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1237 MLX5_SET(tisc, tisc, transport_domain, tdn); 1238 if (!mlx5_ib_lag_should_assign_affinity(dev) && 1239 mlx5_lag_is_lacp_owner(dev->mdev)) 1240 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 1241 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1242 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1243 1244 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1245 } 1246 1247 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1248 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1249 { 1250 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1251 } 1252 1253 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1254 { 1255 if (sq->flow_rule) 1256 mlx5_del_flow_rules(sq->flow_rule); 1257 sq->flow_rule = NULL; 1258 } 1259 1260 static bool fr_supported(int ts_cap) 1261 { 1262 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1263 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1264 } 1265 1266 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1267 bool fr_sup, bool rt_sup) 1268 { 1269 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1270 if (!rt_sup) { 1271 mlx5_ib_dbg(dev, 1272 "Real time TS format is not supported\n"); 1273 return -EOPNOTSUPP; 1274 } 1275 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1276 } 1277 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION) { 1278 if (!fr_sup) { 1279 mlx5_ib_dbg(dev, 1280 "Free running TS format is not supported\n"); 1281 return -EOPNOTSUPP; 1282 } 1283 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1284 } 1285 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1286 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1287 } 1288 1289 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1290 { 1291 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1292 1293 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1294 rt_supported(ts_cap)); 1295 } 1296 1297 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1298 { 1299 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1300 1301 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1302 rt_supported(ts_cap)); 1303 } 1304 1305 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1306 struct mlx5_ib_cq *recv_cq) 1307 { 1308 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1309 bool fr_sup = fr_supported(ts_cap); 1310 bool rt_sup = rt_supported(ts_cap); 1311 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1312 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1313 int send_ts_format = 1314 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1315 default_ts; 1316 int recv_ts_format = 1317 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1318 default_ts; 1319 1320 if (send_ts_format < 0 || recv_ts_format < 0) 1321 return -EOPNOTSUPP; 1322 1323 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1324 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1325 send_ts_format != recv_ts_format) { 1326 mlx5_ib_dbg( 1327 dev, 1328 "The send ts_format does not match the receive ts_format\n"); 1329 return -EOPNOTSUPP; 1330 } 1331 1332 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1333 } 1334 1335 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1336 struct ib_udata *udata, 1337 struct mlx5_ib_sq *sq, void *qpin, 1338 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1339 { 1340 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1341 __be64 *pas; 1342 void *in; 1343 void *sqc; 1344 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1345 void *wq; 1346 int inlen; 1347 int err; 1348 unsigned int page_offset_quantized; 1349 unsigned long page_size; 1350 int ts_format; 1351 1352 ts_format = get_sq_ts_format(dev, cq); 1353 if (ts_format < 0) 1354 return ts_format; 1355 1356 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1357 ubuffer->buf_size, 0); 1358 if (IS_ERR(sq->ubuffer.umem)) 1359 return PTR_ERR(sq->ubuffer.umem); 1360 page_size = mlx5_umem_find_best_quantized_pgoff( 1361 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1362 page_offset, 64, &page_offset_quantized); 1363 if (!page_size) { 1364 err = -EINVAL; 1365 goto err_umem; 1366 } 1367 1368 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1369 sizeof(u64) * 1370 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1371 in = kvzalloc(inlen, GFP_KERNEL); 1372 if (!in) { 1373 err = -ENOMEM; 1374 goto err_umem; 1375 } 1376 1377 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1378 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1379 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1380 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1381 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1382 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1383 MLX5_SET(sqc, sqc, ts_format, ts_format); 1384 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1385 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1386 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1387 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1388 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1389 MLX5_CAP_ETH(dev->mdev, swp)) 1390 MLX5_SET(sqc, sqc, allow_swp, 1); 1391 1392 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1393 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1394 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1395 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1396 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1397 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1398 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1399 MLX5_SET(wq, wq, log_wq_pg_sz, 1400 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1401 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1402 1403 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1404 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1405 1406 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1407 1408 kvfree(in); 1409 1410 if (err) 1411 goto err_umem; 1412 1413 return 0; 1414 1415 err_umem: 1416 ib_umem_release(sq->ubuffer.umem); 1417 sq->ubuffer.umem = NULL; 1418 1419 return err; 1420 } 1421 1422 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1423 struct mlx5_ib_sq *sq) 1424 { 1425 destroy_flow_rule_vport_sq(sq); 1426 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1427 ib_umem_release(sq->ubuffer.umem); 1428 } 1429 1430 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1431 struct mlx5_ib_rq *rq, void *qpin, 1432 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1433 { 1434 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1435 __be64 *pas; 1436 void *in; 1437 void *rqc; 1438 void *wq; 1439 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1440 struct ib_umem *umem = rq->base.ubuffer.umem; 1441 unsigned int page_offset_quantized; 1442 unsigned long page_size = 0; 1443 int ts_format; 1444 size_t inlen; 1445 int err; 1446 1447 ts_format = get_rq_ts_format(dev, cq); 1448 if (ts_format < 0) 1449 return ts_format; 1450 1451 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1452 MLX5_ADAPTER_PAGE_SHIFT, 1453 page_offset, 64, 1454 &page_offset_quantized); 1455 if (!page_size) 1456 return -EINVAL; 1457 1458 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1459 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1460 in = kvzalloc(inlen, GFP_KERNEL); 1461 if (!in) 1462 return -ENOMEM; 1463 1464 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1465 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1466 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1467 MLX5_SET(rqc, rqc, vsd, 1); 1468 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1469 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1470 MLX5_SET(rqc, rqc, ts_format, ts_format); 1471 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1472 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1473 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1474 1475 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1476 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1477 1478 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1479 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1480 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1481 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1482 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1483 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1484 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1485 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1486 MLX5_SET(wq, wq, log_wq_pg_sz, 1487 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1488 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1489 1490 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1491 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1492 1493 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1494 1495 kvfree(in); 1496 1497 return err; 1498 } 1499 1500 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1501 struct mlx5_ib_rq *rq) 1502 { 1503 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1504 } 1505 1506 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1507 struct mlx5_ib_rq *rq, 1508 u32 qp_flags_en, 1509 struct ib_pd *pd) 1510 { 1511 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1512 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1513 mlx5_ib_disable_lb(dev, false, true); 1514 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1515 } 1516 1517 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1518 struct mlx5_ib_rq *rq, u32 tdn, 1519 u32 *qp_flags_en, struct ib_pd *pd, 1520 u32 *out) 1521 { 1522 u8 lb_flag = 0; 1523 u32 *in; 1524 void *tirc; 1525 int inlen; 1526 int err; 1527 1528 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1529 in = kvzalloc(inlen, GFP_KERNEL); 1530 if (!in) 1531 return -ENOMEM; 1532 1533 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1534 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1535 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1536 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1537 MLX5_SET(tirc, tirc, transport_domain, tdn); 1538 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1539 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1540 1541 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1542 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1543 1544 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1545 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1546 1547 if (dev->is_rep) { 1548 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1549 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1550 } 1551 1552 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1553 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1554 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1555 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1556 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1557 err = mlx5_ib_enable_lb(dev, false, true); 1558 1559 if (err) 1560 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1561 } 1562 kvfree(in); 1563 1564 return err; 1565 } 1566 1567 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1568 u32 *in, size_t inlen, struct ib_pd *pd, 1569 struct ib_udata *udata, 1570 struct mlx5_ib_create_qp_resp *resp, 1571 struct ib_qp_init_attr *init_attr) 1572 { 1573 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1574 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1575 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1576 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1577 udata, struct mlx5_ib_ucontext, ibucontext); 1578 int err; 1579 u32 tdn = mucontext->tdn; 1580 u16 uid = to_mpd(pd)->uid; 1581 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1582 1583 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1584 return -EINVAL; 1585 if (qp->sq.wqe_cnt) { 1586 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1587 if (err) 1588 return err; 1589 1590 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1591 to_mcq(init_attr->send_cq)); 1592 if (err) 1593 goto err_destroy_tis; 1594 1595 if (uid) { 1596 resp->tisn = sq->tisn; 1597 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1598 resp->sqn = sq->base.mqp.qpn; 1599 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1600 } 1601 1602 sq->base.container_mibqp = qp; 1603 sq->base.mqp.event = mlx5_ib_qp_event; 1604 } 1605 1606 if (qp->rq.wqe_cnt) { 1607 rq->base.container_mibqp = qp; 1608 1609 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1610 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1611 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1612 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1613 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1614 to_mcq(init_attr->recv_cq)); 1615 if (err) 1616 goto err_destroy_sq; 1617 1618 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1619 out); 1620 if (err) 1621 goto err_destroy_rq; 1622 1623 if (uid) { 1624 resp->rqn = rq->base.mqp.qpn; 1625 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1626 resp->tirn = rq->tirn; 1627 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1628 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1629 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1630 resp->tir_icm_addr = MLX5_GET( 1631 create_tir_out, out, icm_address_31_0); 1632 resp->tir_icm_addr |= 1633 (u64)MLX5_GET(create_tir_out, out, 1634 icm_address_39_32) 1635 << 32; 1636 resp->tir_icm_addr |= 1637 (u64)MLX5_GET(create_tir_out, out, 1638 icm_address_63_40) 1639 << 40; 1640 resp->comp_mask |= 1641 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1642 } 1643 } 1644 } 1645 1646 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1647 rq->base.mqp.qpn; 1648 return 0; 1649 1650 err_destroy_rq: 1651 destroy_raw_packet_qp_rq(dev, rq); 1652 err_destroy_sq: 1653 if (!qp->sq.wqe_cnt) 1654 return err; 1655 destroy_raw_packet_qp_sq(dev, sq); 1656 err_destroy_tis: 1657 destroy_raw_packet_qp_tis(dev, sq, pd); 1658 1659 return err; 1660 } 1661 1662 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1663 struct mlx5_ib_qp *qp) 1664 { 1665 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1666 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1667 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1668 1669 if (qp->rq.wqe_cnt) { 1670 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1671 destroy_raw_packet_qp_rq(dev, rq); 1672 } 1673 1674 if (qp->sq.wqe_cnt) { 1675 destroy_raw_packet_qp_sq(dev, sq); 1676 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1677 } 1678 } 1679 1680 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1681 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1682 { 1683 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1684 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1685 1686 sq->sq = &qp->sq; 1687 rq->rq = &qp->rq; 1688 sq->doorbell = &qp->db; 1689 rq->doorbell = &qp->db; 1690 } 1691 1692 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1693 { 1694 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1695 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1696 mlx5_ib_disable_lb(dev, false, true); 1697 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1698 to_mpd(qp->ibqp.pd)->uid); 1699 } 1700 1701 struct mlx5_create_qp_params { 1702 struct ib_udata *udata; 1703 size_t inlen; 1704 size_t outlen; 1705 size_t ucmd_size; 1706 void *ucmd; 1707 u8 is_rss_raw : 1; 1708 struct ib_qp_init_attr *attr; 1709 u32 uidx; 1710 struct mlx5_ib_create_qp_resp resp; 1711 }; 1712 1713 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1714 struct mlx5_ib_qp *qp, 1715 struct mlx5_create_qp_params *params) 1716 { 1717 struct ib_qp_init_attr *init_attr = params->attr; 1718 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1719 struct ib_udata *udata = params->udata; 1720 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1721 udata, struct mlx5_ib_ucontext, ibucontext); 1722 int inlen; 1723 int outlen; 1724 int err; 1725 u32 *in; 1726 u32 *out; 1727 void *tirc; 1728 void *hfso; 1729 u32 selected_fields = 0; 1730 u32 outer_l4; 1731 u32 tdn = mucontext->tdn; 1732 u8 lb_flag = 0; 1733 1734 if (ucmd->comp_mask) { 1735 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1736 return -EOPNOTSUPP; 1737 } 1738 1739 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1740 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1741 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1742 return -EOPNOTSUPP; 1743 } 1744 1745 if (dev->is_rep) 1746 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1747 1748 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1749 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1750 1751 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1752 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1753 1754 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1755 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1756 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1757 if (!in) 1758 return -ENOMEM; 1759 1760 out = in + MLX5_ST_SZ_DW(create_tir_in); 1761 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1762 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1763 MLX5_SET(tirc, tirc, disp_type, 1764 MLX5_TIRC_DISP_TYPE_INDIRECT); 1765 MLX5_SET(tirc, tirc, indirect_table, 1766 init_attr->rwq_ind_tbl->ind_tbl_num); 1767 MLX5_SET(tirc, tirc, transport_domain, tdn); 1768 1769 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1770 1771 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1772 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1773 1774 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1775 1776 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1777 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1778 else 1779 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1780 1781 switch (ucmd->rx_hash_function) { 1782 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1783 { 1784 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1785 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1786 1787 if (len != ucmd->rx_key_len) { 1788 err = -EINVAL; 1789 goto err; 1790 } 1791 1792 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1793 memcpy(rss_key, ucmd->rx_hash_key, len); 1794 break; 1795 } 1796 default: 1797 err = -EOPNOTSUPP; 1798 goto err; 1799 } 1800 1801 if (!ucmd->rx_hash_fields_mask) { 1802 /* special case when this TIR serves as steering entry without hashing */ 1803 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1804 goto create_tir; 1805 err = -EINVAL; 1806 goto err; 1807 } 1808 1809 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1810 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1811 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1812 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1813 err = -EINVAL; 1814 goto err; 1815 } 1816 1817 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1818 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1819 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1820 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1821 MLX5_L3_PROT_TYPE_IPV4); 1822 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1823 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1824 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1825 MLX5_L3_PROT_TYPE_IPV6); 1826 1827 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1828 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1829 << 0 | 1830 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1831 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1832 << 1 | 1833 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1834 1835 /* Check that only one l4 protocol is set */ 1836 if (outer_l4 & (outer_l4 - 1)) { 1837 err = -EINVAL; 1838 goto err; 1839 } 1840 1841 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1842 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1843 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1844 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1845 MLX5_L4_PROT_TYPE_TCP); 1846 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1847 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1848 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1849 MLX5_L4_PROT_TYPE_UDP); 1850 1851 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1852 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1853 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1854 1855 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1856 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1857 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1858 1859 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1860 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1861 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1862 1863 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1864 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1865 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1866 1867 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1868 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1869 1870 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1871 1872 create_tir: 1873 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1874 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1875 1876 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1877 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1878 err = mlx5_ib_enable_lb(dev, false, true); 1879 1880 if (err) 1881 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1882 to_mpd(pd)->uid); 1883 } 1884 1885 if (err) 1886 goto err; 1887 1888 if (mucontext->devx_uid) { 1889 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1890 params->resp.tirn = qp->rss_qp.tirn; 1891 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1892 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1893 params->resp.tir_icm_addr = 1894 MLX5_GET(create_tir_out, out, icm_address_31_0); 1895 params->resp.tir_icm_addr |= 1896 (u64)MLX5_GET(create_tir_out, out, 1897 icm_address_39_32) 1898 << 32; 1899 params->resp.tir_icm_addr |= 1900 (u64)MLX5_GET(create_tir_out, out, 1901 icm_address_63_40) 1902 << 40; 1903 params->resp.comp_mask |= 1904 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1905 } 1906 } 1907 1908 kvfree(in); 1909 /* qpn is reserved for that QP */ 1910 qp->trans_qp.base.mqp.qpn = 0; 1911 qp->is_rss = true; 1912 return 0; 1913 1914 err: 1915 kvfree(in); 1916 return err; 1917 } 1918 1919 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1920 struct mlx5_ib_qp *qp, 1921 struct ib_qp_init_attr *init_attr, 1922 void *qpc) 1923 { 1924 int scqe_sz; 1925 bool allow_scat_cqe = false; 1926 1927 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1928 1929 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1930 return; 1931 1932 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1933 if (scqe_sz == 128) { 1934 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1935 return; 1936 } 1937 1938 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1939 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1940 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1941 } 1942 1943 static int atomic_size_to_mode(int size_mask) 1944 { 1945 /* driver does not support atomic_size > 256B 1946 * and does not know how to translate bigger sizes 1947 */ 1948 int supported_size_mask = size_mask & 0x1ff; 1949 int log_max_size; 1950 1951 if (!supported_size_mask) 1952 return -EOPNOTSUPP; 1953 1954 log_max_size = __fls(supported_size_mask); 1955 1956 if (log_max_size > 3) 1957 return log_max_size; 1958 1959 return MLX5_ATOMIC_MODE_8B; 1960 } 1961 1962 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1963 enum ib_qp_type qp_type) 1964 { 1965 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1966 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1967 int atomic_mode = -EOPNOTSUPP; 1968 int atomic_size_mask; 1969 1970 if (!atomic) 1971 return -EOPNOTSUPP; 1972 1973 if (qp_type == MLX5_IB_QPT_DCT) 1974 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1975 else 1976 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1977 1978 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1979 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1980 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1981 1982 if (atomic_mode <= 0 && 1983 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1984 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1985 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1986 1987 return atomic_mode; 1988 } 1989 1990 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1991 struct mlx5_create_qp_params *params) 1992 { 1993 struct ib_qp_init_attr *attr = params->attr; 1994 u32 uidx = params->uidx; 1995 struct mlx5_ib_resources *devr = &dev->devr; 1996 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1997 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1998 struct mlx5_core_dev *mdev = dev->mdev; 1999 struct mlx5_ib_qp_base *base; 2000 unsigned long flags; 2001 void *qpc; 2002 u32 *in; 2003 int err; 2004 2005 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2006 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2007 2008 in = kvzalloc(inlen, GFP_KERNEL); 2009 if (!in) 2010 return -ENOMEM; 2011 2012 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2013 2014 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 2015 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2016 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 2017 2018 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2019 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2020 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2021 MLX5_SET(qpc, qpc, cd_master, 1); 2022 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2023 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2024 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2025 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2026 2027 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 2028 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 2029 MLX5_SET(qpc, qpc, no_sq, 1); 2030 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2031 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2032 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2033 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 2034 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2035 2036 /* 0xffffff means we ask to work with cqe version 0 */ 2037 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2038 MLX5_SET(qpc, qpc, user_index, uidx); 2039 2040 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2041 MLX5_SET(qpc, qpc, end_padding_mode, 2042 MLX5_WQ_END_PAD_MODE_ALIGN); 2043 /* Special case to clean flag */ 2044 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2045 } 2046 2047 base = &qp->trans_qp.base; 2048 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2049 kvfree(in); 2050 if (err) 2051 return err; 2052 2053 base->container_mibqp = qp; 2054 base->mqp.event = mlx5_ib_qp_event; 2055 if (MLX5_CAP_GEN(mdev, ece_support)) 2056 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2057 2058 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2059 list_add_tail(&qp->qps_list, &dev->qp_list); 2060 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2061 2062 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 2063 return 0; 2064 } 2065 2066 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2067 struct mlx5_ib_qp *qp, 2068 struct mlx5_create_qp_params *params) 2069 { 2070 struct ib_qp_init_attr *init_attr = params->attr; 2071 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2072 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2073 struct ib_udata *udata = params->udata; 2074 u32 uidx = params->uidx; 2075 struct mlx5_ib_resources *devr = &dev->devr; 2076 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2077 struct mlx5_core_dev *mdev = dev->mdev; 2078 struct mlx5_ib_cq *send_cq; 2079 struct mlx5_ib_cq *recv_cq; 2080 unsigned long flags; 2081 struct mlx5_ib_qp_base *base; 2082 int ts_format; 2083 int mlx5_st; 2084 void *qpc; 2085 u32 *in; 2086 int err; 2087 2088 spin_lock_init(&qp->sq.lock); 2089 spin_lock_init(&qp->rq.lock); 2090 2091 mlx5_st = to_mlx5_st(qp->type); 2092 if (mlx5_st < 0) 2093 return -EINVAL; 2094 2095 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2096 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2097 2098 base = &qp->trans_qp.base; 2099 2100 qp->has_rq = qp_has_rq(init_attr); 2101 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2102 if (err) { 2103 mlx5_ib_dbg(dev, "err %d\n", err); 2104 return err; 2105 } 2106 2107 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2108 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2109 return -EINVAL; 2110 2111 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2112 return -EINVAL; 2113 2114 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2115 to_mcq(init_attr->recv_cq)); 2116 2117 if (ts_format < 0) 2118 return ts_format; 2119 2120 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2121 &inlen, base, ucmd); 2122 if (err) 2123 return err; 2124 2125 if (MLX5_CAP_GEN(mdev, ece_support)) 2126 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2127 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2128 2129 MLX5_SET(qpc, qpc, st, mlx5_st); 2130 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2131 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2132 2133 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2134 MLX5_SET(qpc, qpc, wq_signature, 1); 2135 2136 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2137 MLX5_SET(qpc, qpc, cd_master, 1); 2138 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2139 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2140 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2141 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2142 2143 if (qp->rq.wqe_cnt) { 2144 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2145 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2146 } 2147 2148 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2149 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2150 ucmd->dci_streams.log_num_concurent); 2151 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2152 ucmd->dci_streams.log_num_errored); 2153 } 2154 2155 MLX5_SET(qpc, qpc, ts_format, ts_format); 2156 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2157 2158 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2159 2160 /* Set default resources */ 2161 if (init_attr->srq) { 2162 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2163 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2164 to_msrq(init_attr->srq)->msrq.srqn); 2165 } else { 2166 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2167 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2168 to_msrq(devr->s1)->msrq.srqn); 2169 } 2170 2171 if (init_attr->send_cq) 2172 MLX5_SET(qpc, qpc, cqn_snd, 2173 to_mcq(init_attr->send_cq)->mcq.cqn); 2174 2175 if (init_attr->recv_cq) 2176 MLX5_SET(qpc, qpc, cqn_rcv, 2177 to_mcq(init_attr->recv_cq)->mcq.cqn); 2178 2179 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2180 2181 /* 0xffffff means we ask to work with cqe version 0 */ 2182 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2183 MLX5_SET(qpc, qpc, user_index, uidx); 2184 2185 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2186 MLX5_SET(qpc, qpc, end_padding_mode, 2187 MLX5_WQ_END_PAD_MODE_ALIGN); 2188 /* Special case to clean flag */ 2189 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2190 } 2191 2192 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2193 2194 kvfree(in); 2195 if (err) 2196 goto err_create; 2197 2198 base->container_mibqp = qp; 2199 base->mqp.event = mlx5_ib_qp_event; 2200 if (MLX5_CAP_GEN(mdev, ece_support)) 2201 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2202 2203 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2204 &send_cq, &recv_cq); 2205 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2206 mlx5_ib_lock_cqs(send_cq, recv_cq); 2207 /* Maintain device to QPs access, needed for further handling via reset 2208 * flow 2209 */ 2210 list_add_tail(&qp->qps_list, &dev->qp_list); 2211 /* Maintain CQ to QPs access, needed for further handling via reset flow 2212 */ 2213 if (send_cq) 2214 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2215 if (recv_cq) 2216 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2217 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2218 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2219 2220 return 0; 2221 2222 err_create: 2223 destroy_qp(dev, qp, base, udata); 2224 return err; 2225 } 2226 2227 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2228 struct mlx5_ib_qp *qp, 2229 struct mlx5_create_qp_params *params) 2230 { 2231 struct ib_qp_init_attr *init_attr = params->attr; 2232 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2233 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2234 struct ib_udata *udata = params->udata; 2235 u32 uidx = params->uidx; 2236 struct mlx5_ib_resources *devr = &dev->devr; 2237 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2238 struct mlx5_core_dev *mdev = dev->mdev; 2239 struct mlx5_ib_cq *send_cq; 2240 struct mlx5_ib_cq *recv_cq; 2241 unsigned long flags; 2242 struct mlx5_ib_qp_base *base; 2243 int ts_format; 2244 int mlx5_st; 2245 void *qpc; 2246 u32 *in; 2247 int err; 2248 2249 spin_lock_init(&qp->sq.lock); 2250 spin_lock_init(&qp->rq.lock); 2251 2252 mlx5_st = to_mlx5_st(qp->type); 2253 if (mlx5_st < 0) 2254 return -EINVAL; 2255 2256 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2257 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2258 2259 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2260 qp->underlay_qpn = init_attr->source_qpn; 2261 2262 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2263 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2264 &qp->raw_packet_qp.rq.base : 2265 &qp->trans_qp.base; 2266 2267 qp->has_rq = qp_has_rq(init_attr); 2268 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2269 if (err) { 2270 mlx5_ib_dbg(dev, "err %d\n", err); 2271 return err; 2272 } 2273 2274 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2275 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2276 return -EINVAL; 2277 2278 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2279 return -EINVAL; 2280 2281 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2282 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2283 to_mcq(init_attr->recv_cq)); 2284 if (ts_format < 0) 2285 return ts_format; 2286 } 2287 2288 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2289 &inlen, base, ucmd); 2290 if (err) 2291 return err; 2292 2293 if (is_sqp(init_attr->qp_type)) 2294 qp->port = init_attr->port_num; 2295 2296 if (MLX5_CAP_GEN(mdev, ece_support)) 2297 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2298 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2299 2300 MLX5_SET(qpc, qpc, st, mlx5_st); 2301 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2302 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2303 2304 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2305 MLX5_SET(qpc, qpc, wq_signature, 1); 2306 2307 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2308 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2309 2310 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2311 MLX5_SET(qpc, qpc, cd_master, 1); 2312 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2313 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2314 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2315 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2316 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2317 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2318 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2319 (init_attr->qp_type == IB_QPT_RC || 2320 init_attr->qp_type == IB_QPT_UC)) { 2321 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2322 2323 MLX5_SET(qpc, qpc, cs_res, 2324 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2325 MLX5_RES_SCAT_DATA32_CQE); 2326 } 2327 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2328 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2329 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2330 2331 if (qp->rq.wqe_cnt) { 2332 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2333 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2334 } 2335 2336 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2337 MLX5_SET(qpc, qpc, ts_format, ts_format); 2338 2339 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2340 2341 if (qp->sq.wqe_cnt) { 2342 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2343 } else { 2344 MLX5_SET(qpc, qpc, no_sq, 1); 2345 if (init_attr->srq && 2346 init_attr->srq->srq_type == IB_SRQT_TM) 2347 MLX5_SET(qpc, qpc, offload_type, 2348 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2349 } 2350 2351 /* Set default resources */ 2352 switch (init_attr->qp_type) { 2353 case IB_QPT_XRC_INI: 2354 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2355 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2356 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2357 break; 2358 default: 2359 if (init_attr->srq) { 2360 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2361 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2362 } else { 2363 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2364 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2365 } 2366 } 2367 2368 if (init_attr->send_cq) 2369 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2370 2371 if (init_attr->recv_cq) 2372 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2373 2374 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2375 2376 /* 0xffffff means we ask to work with cqe version 0 */ 2377 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2378 MLX5_SET(qpc, qpc, user_index, uidx); 2379 2380 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2381 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2382 MLX5_SET(qpc, qpc, end_padding_mode, 2383 MLX5_WQ_END_PAD_MODE_ALIGN); 2384 /* Special case to clean flag */ 2385 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2386 } 2387 2388 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2389 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2390 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2391 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2392 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2393 ¶ms->resp, init_attr); 2394 } else 2395 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2396 2397 kvfree(in); 2398 if (err) 2399 goto err_create; 2400 2401 base->container_mibqp = qp; 2402 base->mqp.event = mlx5_ib_qp_event; 2403 if (MLX5_CAP_GEN(mdev, ece_support)) 2404 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2405 2406 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2407 &send_cq, &recv_cq); 2408 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2409 mlx5_ib_lock_cqs(send_cq, recv_cq); 2410 /* Maintain device to QPs access, needed for further handling via reset 2411 * flow 2412 */ 2413 list_add_tail(&qp->qps_list, &dev->qp_list); 2414 /* Maintain CQ to QPs access, needed for further handling via reset flow 2415 */ 2416 if (send_cq) 2417 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2418 if (recv_cq) 2419 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2420 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2421 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2422 2423 return 0; 2424 2425 err_create: 2426 destroy_qp(dev, qp, base, udata); 2427 return err; 2428 } 2429 2430 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2431 struct mlx5_ib_qp *qp, 2432 struct mlx5_create_qp_params *params) 2433 { 2434 struct ib_qp_init_attr *attr = params->attr; 2435 u32 uidx = params->uidx; 2436 struct mlx5_ib_resources *devr = &dev->devr; 2437 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2438 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2439 struct mlx5_core_dev *mdev = dev->mdev; 2440 struct mlx5_ib_cq *send_cq; 2441 struct mlx5_ib_cq *recv_cq; 2442 unsigned long flags; 2443 struct mlx5_ib_qp_base *base; 2444 int mlx5_st; 2445 void *qpc; 2446 u32 *in; 2447 int err; 2448 2449 spin_lock_init(&qp->sq.lock); 2450 spin_lock_init(&qp->rq.lock); 2451 2452 mlx5_st = to_mlx5_st(qp->type); 2453 if (mlx5_st < 0) 2454 return -EINVAL; 2455 2456 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2457 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2458 2459 base = &qp->trans_qp.base; 2460 2461 qp->has_rq = qp_has_rq(attr); 2462 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2463 if (err) { 2464 mlx5_ib_dbg(dev, "err %d\n", err); 2465 return err; 2466 } 2467 2468 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2469 if (err) 2470 return err; 2471 2472 if (is_sqp(attr->qp_type)) 2473 qp->port = attr->port_num; 2474 2475 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2476 2477 MLX5_SET(qpc, qpc, st, mlx5_st); 2478 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2479 2480 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2481 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2482 else 2483 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2484 2485 2486 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2487 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2488 2489 if (qp->rq.wqe_cnt) { 2490 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2491 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2492 } 2493 2494 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2495 2496 if (qp->sq.wqe_cnt) 2497 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2498 else 2499 MLX5_SET(qpc, qpc, no_sq, 1); 2500 2501 if (attr->srq) { 2502 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2503 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2504 to_msrq(attr->srq)->msrq.srqn); 2505 } else { 2506 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2507 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2508 to_msrq(devr->s1)->msrq.srqn); 2509 } 2510 2511 if (attr->send_cq) 2512 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2513 2514 if (attr->recv_cq) 2515 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2516 2517 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2518 2519 /* 0xffffff means we ask to work with cqe version 0 */ 2520 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2521 MLX5_SET(qpc, qpc, user_index, uidx); 2522 2523 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2524 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2525 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2526 2527 if (qp->flags & IB_QP_CREATE_INTEGRITY_EN && 2528 MLX5_CAP_GEN(mdev, go_back_n)) 2529 MLX5_SET(qpc, qpc, retry_mode, MLX5_QP_RM_GO_BACK_N); 2530 2531 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2532 kvfree(in); 2533 if (err) 2534 goto err_create; 2535 2536 base->container_mibqp = qp; 2537 base->mqp.event = mlx5_ib_qp_event; 2538 2539 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2540 &send_cq, &recv_cq); 2541 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2542 mlx5_ib_lock_cqs(send_cq, recv_cq); 2543 /* Maintain device to QPs access, needed for further handling via reset 2544 * flow 2545 */ 2546 list_add_tail(&qp->qps_list, &dev->qp_list); 2547 /* Maintain CQ to QPs access, needed for further handling via reset flow 2548 */ 2549 if (send_cq) 2550 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2551 if (recv_cq) 2552 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2553 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2554 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2555 2556 return 0; 2557 2558 err_create: 2559 destroy_qp(dev, qp, base, NULL); 2560 return err; 2561 } 2562 2563 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2564 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2565 { 2566 if (send_cq) { 2567 if (recv_cq) { 2568 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2569 spin_lock(&send_cq->lock); 2570 spin_lock_nested(&recv_cq->lock, 2571 SINGLE_DEPTH_NESTING); 2572 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2573 spin_lock(&send_cq->lock); 2574 __acquire(&recv_cq->lock); 2575 } else { 2576 spin_lock(&recv_cq->lock); 2577 spin_lock_nested(&send_cq->lock, 2578 SINGLE_DEPTH_NESTING); 2579 } 2580 } else { 2581 spin_lock(&send_cq->lock); 2582 __acquire(&recv_cq->lock); 2583 } 2584 } else if (recv_cq) { 2585 spin_lock(&recv_cq->lock); 2586 __acquire(&send_cq->lock); 2587 } else { 2588 __acquire(&send_cq->lock); 2589 __acquire(&recv_cq->lock); 2590 } 2591 } 2592 2593 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2594 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2595 { 2596 if (send_cq) { 2597 if (recv_cq) { 2598 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2599 spin_unlock(&recv_cq->lock); 2600 spin_unlock(&send_cq->lock); 2601 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2602 __release(&recv_cq->lock); 2603 spin_unlock(&send_cq->lock); 2604 } else { 2605 spin_unlock(&send_cq->lock); 2606 spin_unlock(&recv_cq->lock); 2607 } 2608 } else { 2609 __release(&recv_cq->lock); 2610 spin_unlock(&send_cq->lock); 2611 } 2612 } else if (recv_cq) { 2613 __release(&send_cq->lock); 2614 spin_unlock(&recv_cq->lock); 2615 } else { 2616 __release(&recv_cq->lock); 2617 __release(&send_cq->lock); 2618 } 2619 } 2620 2621 static void get_cqs(enum ib_qp_type qp_type, 2622 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2623 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2624 { 2625 switch (qp_type) { 2626 case IB_QPT_XRC_TGT: 2627 *send_cq = NULL; 2628 *recv_cq = NULL; 2629 break; 2630 case MLX5_IB_QPT_REG_UMR: 2631 case IB_QPT_XRC_INI: 2632 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2633 *recv_cq = NULL; 2634 break; 2635 2636 case IB_QPT_SMI: 2637 case MLX5_IB_QPT_HW_GSI: 2638 case IB_QPT_RC: 2639 case IB_QPT_UC: 2640 case IB_QPT_UD: 2641 case IB_QPT_RAW_PACKET: 2642 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2643 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2644 break; 2645 default: 2646 *send_cq = NULL; 2647 *recv_cq = NULL; 2648 break; 2649 } 2650 } 2651 2652 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2653 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2654 u8 lag_tx_affinity); 2655 2656 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2657 struct ib_udata *udata) 2658 { 2659 struct mlx5_ib_cq *send_cq, *recv_cq; 2660 struct mlx5_ib_qp_base *base; 2661 unsigned long flags; 2662 int err; 2663 2664 if (qp->is_rss) { 2665 destroy_rss_raw_qp_tir(dev, qp); 2666 return; 2667 } 2668 2669 base = (qp->type == IB_QPT_RAW_PACKET || 2670 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2671 &qp->raw_packet_qp.rq.base : 2672 &qp->trans_qp.base; 2673 2674 if (qp->state != IB_QPS_RESET) { 2675 if (qp->type != IB_QPT_RAW_PACKET && 2676 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2677 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2678 NULL, &base->mqp, NULL); 2679 } else { 2680 struct mlx5_modify_raw_qp_param raw_qp_param = { 2681 .operation = MLX5_CMD_OP_2RST_QP 2682 }; 2683 2684 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2685 } 2686 if (err) 2687 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2688 base->mqp.qpn); 2689 } 2690 2691 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2692 &recv_cq); 2693 2694 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2695 mlx5_ib_lock_cqs(send_cq, recv_cq); 2696 /* del from lists under both locks above to protect reset flow paths */ 2697 list_del(&qp->qps_list); 2698 if (send_cq) 2699 list_del(&qp->cq_send_list); 2700 2701 if (recv_cq) 2702 list_del(&qp->cq_recv_list); 2703 2704 if (!udata) { 2705 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2706 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2707 if (send_cq != recv_cq) 2708 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2709 NULL); 2710 } 2711 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2712 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2713 2714 if (qp->type == IB_QPT_RAW_PACKET || 2715 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2716 destroy_raw_packet_qp(dev, qp); 2717 } else { 2718 err = mlx5_core_destroy_qp(dev, &base->mqp); 2719 if (err) 2720 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2721 base->mqp.qpn); 2722 } 2723 2724 destroy_qp(dev, qp, base, udata); 2725 } 2726 2727 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2728 struct mlx5_ib_qp *qp, 2729 struct mlx5_create_qp_params *params) 2730 { 2731 struct ib_qp_init_attr *attr = params->attr; 2732 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2733 u32 uidx = params->uidx; 2734 void *dctc; 2735 2736 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2737 return -EOPNOTSUPP; 2738 2739 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2740 if (!qp->dct.in) 2741 return -ENOMEM; 2742 2743 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2744 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2745 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2746 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2747 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2748 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2749 MLX5_SET(dctc, dctc, user_index, uidx); 2750 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2751 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2752 2753 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2754 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2755 2756 if (rcqe_sz == 128) 2757 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2758 } 2759 2760 qp->state = IB_QPS_RESET; 2761 return 0; 2762 } 2763 2764 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2765 enum ib_qp_type *type) 2766 { 2767 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2768 goto out; 2769 2770 switch (attr->qp_type) { 2771 case IB_QPT_XRC_TGT: 2772 case IB_QPT_XRC_INI: 2773 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2774 goto out; 2775 fallthrough; 2776 case IB_QPT_RC: 2777 case IB_QPT_UC: 2778 case IB_QPT_SMI: 2779 case MLX5_IB_QPT_HW_GSI: 2780 case IB_QPT_DRIVER: 2781 case IB_QPT_GSI: 2782 case IB_QPT_RAW_PACKET: 2783 case IB_QPT_UD: 2784 case MLX5_IB_QPT_REG_UMR: 2785 break; 2786 default: 2787 goto out; 2788 } 2789 2790 *type = attr->qp_type; 2791 return 0; 2792 2793 out: 2794 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2795 return -EOPNOTSUPP; 2796 } 2797 2798 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2799 struct ib_qp_init_attr *attr, 2800 struct ib_udata *udata) 2801 { 2802 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2803 udata, struct mlx5_ib_ucontext, ibucontext); 2804 2805 if (!udata) { 2806 /* Kernel create_qp callers */ 2807 if (attr->rwq_ind_tbl) 2808 return -EOPNOTSUPP; 2809 2810 switch (attr->qp_type) { 2811 case IB_QPT_RAW_PACKET: 2812 case IB_QPT_DRIVER: 2813 return -EOPNOTSUPP; 2814 default: 2815 return 0; 2816 } 2817 } 2818 2819 /* Userspace create_qp callers */ 2820 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2821 mlx5_ib_dbg(dev, 2822 "Raw Packet QP is only supported for CQE version > 0\n"); 2823 return -EINVAL; 2824 } 2825 2826 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2827 mlx5_ib_dbg(dev, 2828 "Wrong QP type %d for the RWQ indirect table\n", 2829 attr->qp_type); 2830 return -EINVAL; 2831 } 2832 2833 /* 2834 * We don't need to see this warning, it means that kernel code 2835 * missing ib_pd. Placed here to catch developer's mistakes. 2836 */ 2837 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2838 "There is a missing PD pointer assignment\n"); 2839 return 0; 2840 } 2841 2842 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2843 bool cond, struct mlx5_ib_qp *qp) 2844 { 2845 if (!(*flags & flag)) 2846 return; 2847 2848 if (cond) { 2849 qp->flags_en |= flag; 2850 *flags &= ~flag; 2851 return; 2852 } 2853 2854 switch (flag) { 2855 case MLX5_QP_FLAG_SCATTER_CQE: 2856 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2857 /* 2858 * We don't return error if these flags were provided, 2859 * and mlx5 doesn't have right capability. 2860 */ 2861 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2862 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2863 return; 2864 default: 2865 break; 2866 } 2867 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2868 } 2869 2870 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2871 void *ucmd, struct ib_qp_init_attr *attr) 2872 { 2873 struct mlx5_core_dev *mdev = dev->mdev; 2874 bool cond; 2875 int flags; 2876 2877 if (attr->rwq_ind_tbl) 2878 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2879 else 2880 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2881 2882 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2883 case MLX5_QP_FLAG_TYPE_DCI: 2884 qp->type = MLX5_IB_QPT_DCI; 2885 break; 2886 case MLX5_QP_FLAG_TYPE_DCT: 2887 qp->type = MLX5_IB_QPT_DCT; 2888 break; 2889 default: 2890 if (qp->type != IB_QPT_DRIVER) 2891 break; 2892 /* 2893 * It is IB_QPT_DRIVER and or no subtype or 2894 * wrong subtype were provided. 2895 */ 2896 return -EINVAL; 2897 } 2898 2899 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2900 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2901 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2902 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2903 qp); 2904 2905 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2906 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2907 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2908 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2909 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2910 2911 if (qp->type == IB_QPT_RAW_PACKET) { 2912 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2913 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2914 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2915 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2916 cond, qp); 2917 process_vendor_flag(dev, &flags, 2918 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2919 qp); 2920 process_vendor_flag(dev, &flags, 2921 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2922 qp); 2923 } 2924 2925 if (qp->type == IB_QPT_RC) 2926 process_vendor_flag(dev, &flags, 2927 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2928 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2929 2930 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2931 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2932 2933 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2934 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2935 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2936 if (attr->rwq_ind_tbl && cond) { 2937 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2938 cond); 2939 return -EINVAL; 2940 } 2941 2942 if (flags) 2943 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2944 2945 return (flags) ? -EINVAL : 0; 2946 } 2947 2948 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2949 bool cond, struct mlx5_ib_qp *qp) 2950 { 2951 if (!(*flags & flag)) 2952 return; 2953 2954 if (cond) { 2955 qp->flags |= flag; 2956 *flags &= ~flag; 2957 return; 2958 } 2959 2960 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2961 } 2962 2963 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2964 struct ib_qp_init_attr *attr) 2965 { 2966 enum ib_qp_type qp_type = qp->type; 2967 struct mlx5_core_dev *mdev = dev->mdev; 2968 int create_flags = attr->create_flags; 2969 bool cond; 2970 2971 if (qp_type == MLX5_IB_QPT_DCT) 2972 return (create_flags) ? -EINVAL : 0; 2973 2974 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2975 return (create_flags) ? -EINVAL : 0; 2976 2977 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2978 mlx5_get_flow_namespace(dev->mdev, 2979 MLX5_FLOW_NAMESPACE_BYPASS), 2980 qp); 2981 process_create_flag(dev, &create_flags, 2982 IB_QP_CREATE_INTEGRITY_EN, 2983 MLX5_CAP_GEN(mdev, sho), qp); 2984 process_create_flag(dev, &create_flags, 2985 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2986 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2987 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2988 MLX5_CAP_GEN(mdev, cd), qp); 2989 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2990 MLX5_CAP_GEN(mdev, cd), qp); 2991 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2992 MLX5_CAP_GEN(mdev, cd), qp); 2993 2994 if (qp_type == IB_QPT_UD) { 2995 process_create_flag(dev, &create_flags, 2996 IB_QP_CREATE_IPOIB_UD_LSO, 2997 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2998 qp); 2999 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 3000 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 3001 cond, qp); 3002 } 3003 3004 if (qp_type == IB_QPT_RAW_PACKET) { 3005 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3006 MLX5_CAP_ETH(mdev, scatter_fcs); 3007 process_create_flag(dev, &create_flags, 3008 IB_QP_CREATE_SCATTER_FCS, cond, qp); 3009 3010 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3011 MLX5_CAP_ETH(mdev, vlan_cap); 3012 process_create_flag(dev, &create_flags, 3013 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 3014 } 3015 3016 process_create_flag(dev, &create_flags, 3017 IB_QP_CREATE_PCI_WRITE_END_PADDING, 3018 MLX5_CAP_GEN(mdev, end_pad), qp); 3019 3020 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 3021 true, qp); 3022 3023 if (create_flags) { 3024 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 3025 create_flags); 3026 return -EOPNOTSUPP; 3027 } 3028 return 0; 3029 } 3030 3031 static int process_udata_size(struct mlx5_ib_dev *dev, 3032 struct mlx5_create_qp_params *params) 3033 { 3034 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 3035 struct ib_udata *udata = params->udata; 3036 size_t outlen = udata->outlen; 3037 size_t inlen = udata->inlen; 3038 3039 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 3040 params->ucmd_size = ucmd; 3041 if (!params->is_rss_raw) { 3042 /* User has old rdma-core, which doesn't support ECE */ 3043 size_t min_inlen = 3044 offsetof(struct mlx5_ib_create_qp, ece_options); 3045 3046 /* 3047 * We will check in check_ucmd_data() that user 3048 * cleared everything after inlen. 3049 */ 3050 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 3051 goto out; 3052 } 3053 3054 /* RSS RAW QP */ 3055 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 3056 return -EINVAL; 3057 3058 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 3059 return -EINVAL; 3060 3061 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 3062 params->ucmd_size = ucmd; 3063 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 3064 return -EINVAL; 3065 3066 params->inlen = min(ucmd, inlen); 3067 out: 3068 if (!params->inlen) 3069 mlx5_ib_dbg(dev, "udata is too small\n"); 3070 3071 return (params->inlen) ? 0 : -EINVAL; 3072 } 3073 3074 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 3075 struct mlx5_ib_qp *qp, 3076 struct mlx5_create_qp_params *params) 3077 { 3078 int err; 3079 3080 if (params->is_rss_raw) { 3081 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3082 goto out; 3083 } 3084 3085 switch (qp->type) { 3086 case MLX5_IB_QPT_DCT: 3087 err = create_dct(dev, pd, qp, params); 3088 break; 3089 case MLX5_IB_QPT_DCI: 3090 err = create_dci(dev, pd, qp, params); 3091 break; 3092 case IB_QPT_XRC_TGT: 3093 err = create_xrc_tgt_qp(dev, qp, params); 3094 break; 3095 case IB_QPT_GSI: 3096 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3097 break; 3098 case MLX5_IB_QPT_HW_GSI: 3099 rdma_restrack_no_track(&qp->ibqp.res); 3100 fallthrough; 3101 case MLX5_IB_QPT_REG_UMR: 3102 default: 3103 if (params->udata) 3104 err = create_user_qp(dev, pd, qp, params); 3105 else 3106 err = create_kernel_qp(dev, pd, qp, params); 3107 } 3108 3109 out: 3110 if (err) { 3111 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3112 return err; 3113 } 3114 3115 if (is_qp0(qp->type)) 3116 qp->ibqp.qp_num = 0; 3117 else if (is_qp1(qp->type)) 3118 qp->ibqp.qp_num = 1; 3119 else 3120 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3121 3122 mlx5_ib_dbg(dev, 3123 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3124 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3125 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3126 -1, 3127 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3128 -1, 3129 params->resp.ece_options); 3130 3131 return 0; 3132 } 3133 3134 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3135 struct ib_qp_init_attr *attr) 3136 { 3137 int ret = 0; 3138 3139 switch (qp->type) { 3140 case MLX5_IB_QPT_DCT: 3141 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3142 break; 3143 case MLX5_IB_QPT_DCI: 3144 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3145 -EINVAL : 3146 0; 3147 break; 3148 case IB_QPT_RAW_PACKET: 3149 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3150 break; 3151 default: 3152 break; 3153 } 3154 3155 if (ret) 3156 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3157 3158 return ret; 3159 } 3160 3161 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3162 struct mlx5_create_qp_params *params) 3163 { 3164 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3165 struct ib_udata *udata = params->udata; 3166 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3167 udata, struct mlx5_ib_ucontext, ibucontext); 3168 3169 if (params->is_rss_raw) 3170 return 0; 3171 3172 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3173 } 3174 3175 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3176 { 3177 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3178 3179 if (mqp->state == IB_QPS_RTR) { 3180 int err; 3181 3182 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3183 if (err) { 3184 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3185 return err; 3186 } 3187 } 3188 3189 kfree(mqp->dct.in); 3190 return 0; 3191 } 3192 3193 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3194 struct mlx5_create_qp_params *params) 3195 { 3196 struct ib_udata *udata = params->udata; 3197 size_t size, last; 3198 int ret; 3199 3200 if (params->is_rss_raw) 3201 /* 3202 * These QPs don't have "reserved" field in their 3203 * create_qp input struct, so their data is always valid. 3204 */ 3205 last = sizeof(struct mlx5_ib_create_qp_rss); 3206 else 3207 last = offsetof(struct mlx5_ib_create_qp, reserved); 3208 3209 if (udata->inlen <= last) 3210 return 0; 3211 3212 /* 3213 * User provides different create_qp structures based on the 3214 * flow and we need to know if he cleared memory after our 3215 * struct create_qp ends. 3216 */ 3217 size = udata->inlen - last; 3218 ret = ib_is_udata_cleared(params->udata, last, size); 3219 if (!ret) 3220 mlx5_ib_dbg( 3221 dev, 3222 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3223 udata->inlen, params->ucmd_size, last, size); 3224 return ret ? 0 : -EINVAL; 3225 } 3226 3227 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3228 struct ib_udata *udata) 3229 { 3230 struct mlx5_create_qp_params params = {}; 3231 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3232 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3233 struct ib_pd *pd = ibqp->pd; 3234 enum ib_qp_type type; 3235 int err; 3236 3237 err = check_qp_type(dev, attr, &type); 3238 if (err) 3239 return err; 3240 3241 err = check_valid_flow(dev, pd, attr, udata); 3242 if (err) 3243 return err; 3244 3245 params.udata = udata; 3246 params.uidx = MLX5_IB_DEFAULT_UIDX; 3247 params.attr = attr; 3248 params.is_rss_raw = !!attr->rwq_ind_tbl; 3249 3250 if (udata) { 3251 err = process_udata_size(dev, ¶ms); 3252 if (err) 3253 return err; 3254 3255 err = check_ucmd_data(dev, ¶ms); 3256 if (err) 3257 return err; 3258 3259 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3260 if (!params.ucmd) 3261 return -ENOMEM; 3262 3263 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3264 if (err) 3265 goto free_ucmd; 3266 } 3267 3268 mutex_init(&qp->mutex); 3269 qp->type = type; 3270 if (udata) { 3271 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3272 if (err) 3273 goto free_ucmd; 3274 3275 err = get_qp_uidx(qp, ¶ms); 3276 if (err) 3277 goto free_ucmd; 3278 } 3279 err = process_create_flags(dev, qp, attr); 3280 if (err) 3281 goto free_ucmd; 3282 3283 err = check_qp_attr(dev, qp, attr); 3284 if (err) 3285 goto free_ucmd; 3286 3287 err = create_qp(dev, pd, qp, ¶ms); 3288 if (err) 3289 goto free_ucmd; 3290 3291 kfree(params.ucmd); 3292 params.ucmd = NULL; 3293 3294 if (udata) 3295 /* 3296 * It is safe to copy response for all user create QP flows, 3297 * including MLX5_IB_QPT_DCT, which doesn't need it. 3298 * In that case, resp will be filled with zeros. 3299 */ 3300 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3301 if (err) 3302 goto destroy_qp; 3303 3304 return 0; 3305 3306 destroy_qp: 3307 switch (qp->type) { 3308 case MLX5_IB_QPT_DCT: 3309 mlx5_ib_destroy_dct(qp); 3310 break; 3311 case IB_QPT_GSI: 3312 mlx5_ib_destroy_gsi(qp); 3313 break; 3314 default: 3315 destroy_qp_common(dev, qp, udata); 3316 } 3317 3318 free_ucmd: 3319 kfree(params.ucmd); 3320 return err; 3321 } 3322 3323 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3324 { 3325 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3326 struct mlx5_ib_qp *mqp = to_mqp(qp); 3327 3328 if (mqp->type == IB_QPT_GSI) 3329 return mlx5_ib_destroy_gsi(mqp); 3330 3331 if (mqp->type == MLX5_IB_QPT_DCT) 3332 return mlx5_ib_destroy_dct(mqp); 3333 3334 destroy_qp_common(dev, mqp, udata); 3335 return 0; 3336 } 3337 3338 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3339 const struct ib_qp_attr *attr, int attr_mask, 3340 void *qpc) 3341 { 3342 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3343 u8 dest_rd_atomic; 3344 u32 access_flags; 3345 3346 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3347 dest_rd_atomic = attr->max_dest_rd_atomic; 3348 else 3349 dest_rd_atomic = qp->trans_qp.resp_depth; 3350 3351 if (attr_mask & IB_QP_ACCESS_FLAGS) 3352 access_flags = attr->qp_access_flags; 3353 else 3354 access_flags = qp->trans_qp.atomic_rd_en; 3355 3356 if (!dest_rd_atomic) 3357 access_flags &= IB_ACCESS_REMOTE_WRITE; 3358 3359 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3360 3361 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3362 int atomic_mode; 3363 3364 atomic_mode = get_atomic_mode(dev, qp->type); 3365 if (atomic_mode < 0) 3366 return -EOPNOTSUPP; 3367 3368 MLX5_SET(qpc, qpc, rae, 1); 3369 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3370 } 3371 3372 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3373 return 0; 3374 } 3375 3376 enum { 3377 MLX5_PATH_FLAG_FL = 1 << 0, 3378 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3379 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3380 }; 3381 3382 static int mlx5_to_ib_rate_map(u8 rate) 3383 { 3384 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3385 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3386 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3387 IB_RATE_400_GBPS }; 3388 3389 if (rate < ARRAY_SIZE(rates)) 3390 return rates[rate]; 3391 3392 return rate - MLX5_STAT_RATE_OFFSET; 3393 } 3394 3395 static int ib_to_mlx5_rate_map(u8 rate) 3396 { 3397 switch (rate) { 3398 case IB_RATE_PORT_CURRENT: 3399 return 0; 3400 case IB_RATE_56_GBPS: 3401 return 1; 3402 case IB_RATE_25_GBPS: 3403 return 2; 3404 case IB_RATE_100_GBPS: 3405 return 3; 3406 case IB_RATE_200_GBPS: 3407 return 4; 3408 case IB_RATE_50_GBPS: 3409 return 5; 3410 case IB_RATE_400_GBPS: 3411 return 6; 3412 default: 3413 return rate + MLX5_STAT_RATE_OFFSET; 3414 } 3415 3416 return 0; 3417 } 3418 3419 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3420 { 3421 u32 stat_rate_support; 3422 3423 if (rate == IB_RATE_PORT_CURRENT) 3424 return 0; 3425 3426 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_800_GBPS) 3427 return -EINVAL; 3428 3429 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3430 while (rate != IB_RATE_PORT_CURRENT && 3431 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3432 --rate; 3433 3434 return ib_to_mlx5_rate_map(rate); 3435 } 3436 3437 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3438 struct mlx5_ib_sq *sq, u8 sl, 3439 struct ib_pd *pd) 3440 { 3441 void *in; 3442 void *tisc; 3443 int inlen; 3444 int err; 3445 3446 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3447 in = kvzalloc(inlen, GFP_KERNEL); 3448 if (!in) 3449 return -ENOMEM; 3450 3451 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3452 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3453 3454 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3455 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3456 3457 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3458 3459 kvfree(in); 3460 3461 return err; 3462 } 3463 3464 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3465 struct mlx5_ib_sq *sq, u8 tx_affinity, 3466 struct ib_pd *pd) 3467 { 3468 void *in; 3469 void *tisc; 3470 int inlen; 3471 int err; 3472 3473 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3474 in = kvzalloc(inlen, GFP_KERNEL); 3475 if (!in) 3476 return -ENOMEM; 3477 3478 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3479 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3480 3481 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3482 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3483 3484 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3485 3486 kvfree(in); 3487 3488 return err; 3489 } 3490 3491 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3492 u32 lqpn, u32 rqpn) 3493 3494 { 3495 u32 fl = ah->grh.flow_label; 3496 3497 if (!fl) 3498 fl = rdma_calc_flow_label(lqpn, rqpn); 3499 3500 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3501 } 3502 3503 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3504 const struct rdma_ah_attr *ah, void *path, u8 port, 3505 int attr_mask, u32 path_flags, 3506 const struct ib_qp_attr *attr, bool alt) 3507 { 3508 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3509 int err; 3510 enum ib_gid_type gid_type; 3511 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3512 u8 sl = rdma_ah_get_sl(ah); 3513 3514 if (attr_mask & IB_QP_PKEY_INDEX) 3515 MLX5_SET(ads, path, pkey_index, 3516 alt ? attr->alt_pkey_index : attr->pkey_index); 3517 3518 if (ah_flags & IB_AH_GRH) { 3519 const struct ib_port_immutable *immutable; 3520 3521 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3522 if (grh->sgid_index >= immutable->gid_tbl_len) { 3523 pr_err("sgid_index (%u) too large. max is %d\n", 3524 grh->sgid_index, 3525 immutable->gid_tbl_len); 3526 return -EINVAL; 3527 } 3528 } 3529 3530 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3531 if (!(ah_flags & IB_AH_GRH)) 3532 return -EINVAL; 3533 3534 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3535 ah->roce.dmac); 3536 if ((qp->type == IB_QPT_RC || 3537 qp->type == IB_QPT_UC || 3538 qp->type == IB_QPT_XRC_INI || 3539 qp->type == IB_QPT_XRC_TGT) && 3540 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3541 (attr_mask & IB_QP_DEST_QPN)) 3542 mlx5_set_path_udp_sport(path, ah, 3543 qp->ibqp.qp_num, 3544 attr->dest_qp_num); 3545 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3546 gid_type = ah->grh.sgid_attr->gid_type; 3547 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3548 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3549 } else { 3550 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3551 MLX5_SET(ads, path, free_ar, 3552 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3553 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3554 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3555 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3556 MLX5_SET(ads, path, sl, sl); 3557 } 3558 3559 if (ah_flags & IB_AH_GRH) { 3560 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3561 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3562 MLX5_SET(ads, path, tclass, grh->traffic_class); 3563 MLX5_SET(ads, path, flow_label, grh->flow_label); 3564 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3565 sizeof(grh->dgid.raw)); 3566 } 3567 3568 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3569 if (err < 0) 3570 return err; 3571 MLX5_SET(ads, path, stat_rate, err); 3572 MLX5_SET(ads, path, vhca_port_num, port); 3573 3574 if (attr_mask & IB_QP_TIMEOUT) 3575 MLX5_SET(ads, path, ack_timeout, 3576 alt ? attr->alt_timeout : attr->timeout); 3577 3578 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3579 return modify_raw_packet_eth_prio(dev->mdev, 3580 &qp->raw_packet_qp.sq, 3581 sl & 0xf, qp->ibqp.pd); 3582 3583 return 0; 3584 } 3585 3586 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3587 [MLX5_QP_STATE_INIT] = { 3588 [MLX5_QP_STATE_INIT] = { 3589 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3590 MLX5_QP_OPTPAR_RAE | 3591 MLX5_QP_OPTPAR_RWE | 3592 MLX5_QP_OPTPAR_PKEY_INDEX | 3593 MLX5_QP_OPTPAR_PRI_PORT | 3594 MLX5_QP_OPTPAR_LAG_TX_AFF, 3595 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3596 MLX5_QP_OPTPAR_PKEY_INDEX | 3597 MLX5_QP_OPTPAR_PRI_PORT | 3598 MLX5_QP_OPTPAR_LAG_TX_AFF, 3599 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3600 MLX5_QP_OPTPAR_Q_KEY | 3601 MLX5_QP_OPTPAR_PRI_PORT, 3602 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3603 MLX5_QP_OPTPAR_RAE | 3604 MLX5_QP_OPTPAR_RWE | 3605 MLX5_QP_OPTPAR_PKEY_INDEX | 3606 MLX5_QP_OPTPAR_PRI_PORT | 3607 MLX5_QP_OPTPAR_LAG_TX_AFF, 3608 }, 3609 [MLX5_QP_STATE_RTR] = { 3610 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3611 MLX5_QP_OPTPAR_RRE | 3612 MLX5_QP_OPTPAR_RAE | 3613 MLX5_QP_OPTPAR_RWE | 3614 MLX5_QP_OPTPAR_PKEY_INDEX | 3615 MLX5_QP_OPTPAR_LAG_TX_AFF, 3616 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3617 MLX5_QP_OPTPAR_RWE | 3618 MLX5_QP_OPTPAR_PKEY_INDEX | 3619 MLX5_QP_OPTPAR_LAG_TX_AFF, 3620 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3621 MLX5_QP_OPTPAR_Q_KEY, 3622 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3623 MLX5_QP_OPTPAR_Q_KEY, 3624 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3625 MLX5_QP_OPTPAR_RRE | 3626 MLX5_QP_OPTPAR_RAE | 3627 MLX5_QP_OPTPAR_RWE | 3628 MLX5_QP_OPTPAR_PKEY_INDEX | 3629 MLX5_QP_OPTPAR_LAG_TX_AFF, 3630 }, 3631 }, 3632 [MLX5_QP_STATE_RTR] = { 3633 [MLX5_QP_STATE_RTS] = { 3634 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3635 MLX5_QP_OPTPAR_RRE | 3636 MLX5_QP_OPTPAR_RAE | 3637 MLX5_QP_OPTPAR_RWE | 3638 MLX5_QP_OPTPAR_PM_STATE | 3639 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3640 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3641 MLX5_QP_OPTPAR_RWE | 3642 MLX5_QP_OPTPAR_PM_STATE, 3643 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3644 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3645 MLX5_QP_OPTPAR_RRE | 3646 MLX5_QP_OPTPAR_RAE | 3647 MLX5_QP_OPTPAR_RWE | 3648 MLX5_QP_OPTPAR_PM_STATE | 3649 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3650 }, 3651 }, 3652 [MLX5_QP_STATE_RTS] = { 3653 [MLX5_QP_STATE_RTS] = { 3654 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3655 MLX5_QP_OPTPAR_RAE | 3656 MLX5_QP_OPTPAR_RWE | 3657 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3658 MLX5_QP_OPTPAR_PM_STATE | 3659 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3660 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3661 MLX5_QP_OPTPAR_PM_STATE | 3662 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3663 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3664 MLX5_QP_OPTPAR_SRQN | 3665 MLX5_QP_OPTPAR_CQN_RCV, 3666 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3667 MLX5_QP_OPTPAR_RAE | 3668 MLX5_QP_OPTPAR_RWE | 3669 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3670 MLX5_QP_OPTPAR_PM_STATE | 3671 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3672 }, 3673 }, 3674 [MLX5_QP_STATE_SQER] = { 3675 [MLX5_QP_STATE_RTS] = { 3676 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3677 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3678 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3679 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3680 MLX5_QP_OPTPAR_RWE | 3681 MLX5_QP_OPTPAR_RAE | 3682 MLX5_QP_OPTPAR_RRE, 3683 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3684 MLX5_QP_OPTPAR_RWE | 3685 MLX5_QP_OPTPAR_RAE | 3686 MLX5_QP_OPTPAR_RRE, 3687 }, 3688 }, 3689 [MLX5_QP_STATE_SQD] = { 3690 [MLX5_QP_STATE_RTS] = { 3691 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3692 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3693 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3694 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3695 MLX5_QP_OPTPAR_RWE | 3696 MLX5_QP_OPTPAR_RAE | 3697 MLX5_QP_OPTPAR_RRE, 3698 }, 3699 }, 3700 }; 3701 3702 static int ib_nr_to_mlx5_nr(int ib_mask) 3703 { 3704 switch (ib_mask) { 3705 case IB_QP_STATE: 3706 return 0; 3707 case IB_QP_CUR_STATE: 3708 return 0; 3709 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3710 return 0; 3711 case IB_QP_ACCESS_FLAGS: 3712 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3713 MLX5_QP_OPTPAR_RAE; 3714 case IB_QP_PKEY_INDEX: 3715 return MLX5_QP_OPTPAR_PKEY_INDEX; 3716 case IB_QP_PORT: 3717 return MLX5_QP_OPTPAR_PRI_PORT; 3718 case IB_QP_QKEY: 3719 return MLX5_QP_OPTPAR_Q_KEY; 3720 case IB_QP_AV: 3721 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3722 MLX5_QP_OPTPAR_PRI_PORT; 3723 case IB_QP_PATH_MTU: 3724 return 0; 3725 case IB_QP_TIMEOUT: 3726 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3727 case IB_QP_RETRY_CNT: 3728 return MLX5_QP_OPTPAR_RETRY_COUNT; 3729 case IB_QP_RNR_RETRY: 3730 return MLX5_QP_OPTPAR_RNR_RETRY; 3731 case IB_QP_RQ_PSN: 3732 return 0; 3733 case IB_QP_MAX_QP_RD_ATOMIC: 3734 return MLX5_QP_OPTPAR_SRA_MAX; 3735 case IB_QP_ALT_PATH: 3736 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3737 case IB_QP_MIN_RNR_TIMER: 3738 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3739 case IB_QP_SQ_PSN: 3740 return 0; 3741 case IB_QP_MAX_DEST_RD_ATOMIC: 3742 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3743 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3744 case IB_QP_PATH_MIG_STATE: 3745 return MLX5_QP_OPTPAR_PM_STATE; 3746 case IB_QP_CAP: 3747 return 0; 3748 case IB_QP_DEST_QPN: 3749 return 0; 3750 } 3751 return 0; 3752 } 3753 3754 static int ib_mask_to_mlx5_opt(int ib_mask) 3755 { 3756 int result = 0; 3757 int i; 3758 3759 for (i = 0; i < 8 * sizeof(int); i++) { 3760 if ((1 << i) & ib_mask) 3761 result |= ib_nr_to_mlx5_nr(1 << i); 3762 } 3763 3764 return result; 3765 } 3766 3767 static int modify_raw_packet_qp_rq( 3768 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3769 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3770 { 3771 void *in; 3772 void *rqc; 3773 int inlen; 3774 int err; 3775 3776 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3777 in = kvzalloc(inlen, GFP_KERNEL); 3778 if (!in) 3779 return -ENOMEM; 3780 3781 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3782 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3783 3784 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3785 MLX5_SET(rqc, rqc, state, new_state); 3786 3787 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3788 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3789 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3790 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3791 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3792 } else 3793 dev_info_once( 3794 &dev->ib_dev.dev, 3795 "RAW PACKET QP counters are not supported on current FW\n"); 3796 } 3797 3798 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3799 if (err) 3800 goto out; 3801 3802 rq->state = new_state; 3803 3804 out: 3805 kvfree(in); 3806 return err; 3807 } 3808 3809 static int modify_raw_packet_qp_sq( 3810 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3811 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3812 { 3813 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3814 struct mlx5_rate_limit old_rl = ibqp->rl; 3815 struct mlx5_rate_limit new_rl = old_rl; 3816 bool new_rate_added = false; 3817 u16 rl_index = 0; 3818 void *in; 3819 void *sqc; 3820 int inlen; 3821 int err; 3822 3823 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3824 in = kvzalloc(inlen, GFP_KERNEL); 3825 if (!in) 3826 return -ENOMEM; 3827 3828 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3829 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3830 3831 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3832 MLX5_SET(sqc, sqc, state, new_state); 3833 3834 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3835 if (new_state != MLX5_SQC_STATE_RDY) 3836 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3837 __func__); 3838 else 3839 new_rl = raw_qp_param->rl; 3840 } 3841 3842 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3843 if (new_rl.rate) { 3844 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3845 if (err) { 3846 pr_err("Failed configuring rate limit(err %d): \ 3847 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3848 err, new_rl.rate, new_rl.max_burst_sz, 3849 new_rl.typical_pkt_sz); 3850 3851 goto out; 3852 } 3853 new_rate_added = true; 3854 } 3855 3856 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3857 /* index 0 means no limit */ 3858 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3859 } 3860 3861 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3862 if (err) { 3863 /* Remove new rate from table if failed */ 3864 if (new_rate_added) 3865 mlx5_rl_remove_rate(dev, &new_rl); 3866 goto out; 3867 } 3868 3869 /* Only remove the old rate after new rate was set */ 3870 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3871 (new_state != MLX5_SQC_STATE_RDY)) { 3872 mlx5_rl_remove_rate(dev, &old_rl); 3873 if (new_state != MLX5_SQC_STATE_RDY) 3874 memset(&new_rl, 0, sizeof(new_rl)); 3875 } 3876 3877 ibqp->rl = new_rl; 3878 sq->state = new_state; 3879 3880 out: 3881 kvfree(in); 3882 return err; 3883 } 3884 3885 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3886 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3887 u8 tx_affinity) 3888 { 3889 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3890 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3891 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3892 int modify_rq = !!qp->rq.wqe_cnt; 3893 int modify_sq = !!qp->sq.wqe_cnt; 3894 int rq_state; 3895 int sq_state; 3896 int err; 3897 3898 switch (raw_qp_param->operation) { 3899 case MLX5_CMD_OP_RST2INIT_QP: 3900 rq_state = MLX5_RQC_STATE_RDY; 3901 sq_state = MLX5_SQC_STATE_RST; 3902 break; 3903 case MLX5_CMD_OP_2ERR_QP: 3904 rq_state = MLX5_RQC_STATE_ERR; 3905 sq_state = MLX5_SQC_STATE_ERR; 3906 break; 3907 case MLX5_CMD_OP_2RST_QP: 3908 rq_state = MLX5_RQC_STATE_RST; 3909 sq_state = MLX5_SQC_STATE_RST; 3910 break; 3911 case MLX5_CMD_OP_RTR2RTS_QP: 3912 case MLX5_CMD_OP_RTS2RTS_QP: 3913 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3914 return -EINVAL; 3915 3916 modify_rq = 0; 3917 sq_state = MLX5_SQC_STATE_RDY; 3918 break; 3919 case MLX5_CMD_OP_INIT2INIT_QP: 3920 case MLX5_CMD_OP_INIT2RTR_QP: 3921 if (raw_qp_param->set_mask) 3922 return -EINVAL; 3923 else 3924 return 0; 3925 default: 3926 WARN_ON(1); 3927 return -EINVAL; 3928 } 3929 3930 if (modify_rq) { 3931 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3932 qp->ibqp.pd); 3933 if (err) 3934 return err; 3935 } 3936 3937 if (modify_sq) { 3938 struct mlx5_flow_handle *flow_rule; 3939 3940 if (tx_affinity) { 3941 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3942 tx_affinity, 3943 qp->ibqp.pd); 3944 if (err) 3945 return err; 3946 } 3947 3948 flow_rule = create_flow_rule_vport_sq(dev, sq, 3949 raw_qp_param->port); 3950 if (IS_ERR(flow_rule)) 3951 return PTR_ERR(flow_rule); 3952 3953 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3954 raw_qp_param, qp->ibqp.pd); 3955 if (err) { 3956 if (flow_rule) 3957 mlx5_del_flow_rules(flow_rule); 3958 return err; 3959 } 3960 3961 if (flow_rule) { 3962 destroy_flow_rule_vport_sq(sq); 3963 sq->flow_rule = flow_rule; 3964 } 3965 3966 return err; 3967 } 3968 3969 return 0; 3970 } 3971 3972 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3973 struct ib_udata *udata) 3974 { 3975 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3976 udata, struct mlx5_ib_ucontext, ibucontext); 3977 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3978 atomic_t *tx_port_affinity; 3979 3980 if (ucontext) 3981 tx_port_affinity = &ucontext->tx_port_affinity; 3982 else 3983 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3984 3985 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3986 (dev->lag_active ? dev->lag_ports : MLX5_CAP_GEN(dev->mdev, num_lag_ports)) + 1; 3987 } 3988 3989 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3990 { 3991 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3992 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3993 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3994 (qp->type == MLX5_IB_QPT_DCI)) 3995 return true; 3996 return false; 3997 } 3998 3999 static unsigned int get_tx_affinity(struct ib_qp *qp, 4000 const struct ib_qp_attr *attr, 4001 int attr_mask, u8 init, 4002 struct ib_udata *udata) 4003 { 4004 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4005 udata, struct mlx5_ib_ucontext, ibucontext); 4006 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4007 struct mlx5_ib_qp *mqp = to_mqp(qp); 4008 struct mlx5_ib_qp_base *qp_base; 4009 unsigned int tx_affinity; 4010 4011 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 4012 qp_supports_affinity(mqp))) 4013 return 0; 4014 4015 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4016 tx_affinity = mqp->gsi_lag_port; 4017 else if (init) 4018 tx_affinity = get_tx_affinity_rr(dev, udata); 4019 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 4020 tx_affinity = 4021 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 4022 else 4023 return 0; 4024 4025 qp_base = &mqp->trans_qp.base; 4026 if (ucontext) 4027 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 4028 tx_affinity, qp_base->mqp.qpn, ucontext); 4029 else 4030 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 4031 tx_affinity, qp_base->mqp.qpn); 4032 return tx_affinity; 4033 } 4034 4035 static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id, 4036 struct mlx5_core_dev *mdev) 4037 { 4038 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4039 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4040 u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; 4041 void *rqc; 4042 4043 if (!qp->rq.wqe_cnt) 4044 return 0; 4045 4046 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 4047 MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid); 4048 4049 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4050 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 4051 4052 MLX5_SET64(modify_rq_in, in, modify_bitmask, 4053 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 4054 MLX5_SET(rqc, rqc, counter_set_id, set_id); 4055 4056 return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in); 4057 } 4058 4059 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4060 struct rdma_counter *counter) 4061 { 4062 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4063 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 4064 struct mlx5_ib_qp *mqp = to_mqp(qp); 4065 struct mlx5_ib_qp_base *base; 4066 u32 set_id; 4067 u32 *qpc; 4068 4069 if (counter) 4070 set_id = counter->id; 4071 else 4072 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4073 4074 if (mqp->type == IB_QPT_RAW_PACKET) 4075 return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev); 4076 4077 base = &mqp->trans_qp.base; 4078 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 4079 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 4080 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 4081 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 4082 MLX5_QP_OPTPAR_COUNTER_SET_ID); 4083 4084 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 4085 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4086 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 4087 } 4088 4089 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 4090 const struct ib_qp_attr *attr, int attr_mask, 4091 enum ib_qp_state cur_state, 4092 enum ib_qp_state new_state, 4093 const struct mlx5_ib_modify_qp *ucmd, 4094 struct mlx5_ib_modify_qp_resp *resp, 4095 struct ib_udata *udata) 4096 { 4097 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 4098 [MLX5_QP_STATE_RST] = { 4099 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4100 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4101 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 4102 }, 4103 [MLX5_QP_STATE_INIT] = { 4104 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4105 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4106 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4107 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4108 }, 4109 [MLX5_QP_STATE_RTR] = { 4110 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4111 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4112 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4113 }, 4114 [MLX5_QP_STATE_RTS] = { 4115 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4116 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4117 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4118 }, 4119 [MLX5_QP_STATE_SQD] = { 4120 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4121 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4122 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4123 }, 4124 [MLX5_QP_STATE_SQER] = { 4125 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4126 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4127 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4128 }, 4129 [MLX5_QP_STATE_ERR] = { 4130 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4131 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4132 } 4133 }; 4134 4135 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4136 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4137 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4138 struct mlx5_ib_cq *send_cq, *recv_cq; 4139 struct mlx5_ib_pd *pd; 4140 enum mlx5_qp_state mlx5_cur, mlx5_new; 4141 void *qpc, *pri_path, *alt_path; 4142 enum mlx5_qp_optpar optpar = 0; 4143 u32 set_id = 0; 4144 int mlx5_st; 4145 int err; 4146 u16 op; 4147 u8 tx_affinity = 0; 4148 4149 mlx5_st = to_mlx5_st(qp->type); 4150 if (mlx5_st < 0) 4151 return -EINVAL; 4152 4153 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4154 if (!qpc) 4155 return -ENOMEM; 4156 4157 pd = to_mpd(qp->ibqp.pd); 4158 MLX5_SET(qpc, qpc, st, mlx5_st); 4159 4160 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4161 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4162 } else { 4163 switch (attr->path_mig_state) { 4164 case IB_MIG_MIGRATED: 4165 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4166 break; 4167 case IB_MIG_REARM: 4168 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4169 break; 4170 case IB_MIG_ARMED: 4171 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4172 break; 4173 } 4174 } 4175 4176 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4177 cur_state == IB_QPS_RESET && 4178 new_state == IB_QPS_INIT, udata); 4179 4180 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4181 if (tx_affinity && new_state == IB_QPS_RTR && 4182 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4183 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4184 4185 if (is_sqp(qp->type)) { 4186 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4187 MLX5_SET(qpc, qpc, log_msg_max, 8); 4188 } else if ((qp->type == IB_QPT_UD && 4189 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4190 qp->type == MLX5_IB_QPT_REG_UMR) { 4191 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4192 MLX5_SET(qpc, qpc, log_msg_max, 12); 4193 } else if (attr_mask & IB_QP_PATH_MTU) { 4194 if (attr->path_mtu < IB_MTU_256 || 4195 attr->path_mtu > IB_MTU_4096) { 4196 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4197 err = -EINVAL; 4198 goto out; 4199 } 4200 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4201 MLX5_SET(qpc, qpc, log_msg_max, 4202 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4203 } 4204 4205 if (attr_mask & IB_QP_DEST_QPN) 4206 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4207 4208 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4209 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4210 4211 if (attr_mask & IB_QP_PKEY_INDEX) 4212 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4213 4214 /* todo implement counter_index functionality */ 4215 4216 if (is_sqp(qp->type)) 4217 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4218 4219 if (attr_mask & IB_QP_PORT) 4220 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4221 4222 if (attr_mask & IB_QP_AV) { 4223 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4224 attr_mask & IB_QP_PORT ? attr->port_num : 4225 qp->port, 4226 attr_mask, 0, attr, false); 4227 if (err) 4228 goto out; 4229 } 4230 4231 if (attr_mask & IB_QP_TIMEOUT) 4232 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4233 4234 if (attr_mask & IB_QP_ALT_PATH) { 4235 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4236 attr->alt_port_num, 4237 attr_mask | IB_QP_PKEY_INDEX | 4238 IB_QP_TIMEOUT, 4239 0, attr, true); 4240 if (err) 4241 goto out; 4242 } 4243 4244 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4245 &send_cq, &recv_cq); 4246 4247 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4248 if (send_cq) 4249 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4250 if (recv_cq) 4251 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4252 4253 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4254 4255 if (attr_mask & IB_QP_RNR_RETRY) 4256 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4257 4258 if (attr_mask & IB_QP_RETRY_CNT) 4259 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4260 4261 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4262 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 4263 4264 if (attr_mask & IB_QP_SQ_PSN) 4265 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4266 4267 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4268 MLX5_SET(qpc, qpc, log_rra_max, 4269 ilog2(attr->max_dest_rd_atomic)); 4270 4271 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4272 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4273 if (err) 4274 goto out; 4275 } 4276 4277 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4278 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4279 4280 if (attr_mask & IB_QP_RQ_PSN) 4281 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4282 4283 if (attr_mask & IB_QP_QKEY) 4284 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4285 4286 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4287 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4288 4289 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4290 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4291 qp->port) - 1; 4292 4293 /* Underlay port should be used - index 0 function per port */ 4294 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4295 port_num = 0; 4296 4297 if (ibqp->counter) 4298 set_id = ibqp->counter->id; 4299 else 4300 set_id = mlx5_ib_get_counters_id(dev, port_num); 4301 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4302 } 4303 4304 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4305 MLX5_SET(qpc, qpc, rlky, 1); 4306 4307 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4308 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4309 4310 mlx5_cur = to_mlx5_state(cur_state); 4311 mlx5_new = to_mlx5_state(new_state); 4312 4313 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4314 !optab[mlx5_cur][mlx5_new]) { 4315 err = -EINVAL; 4316 goto out; 4317 } 4318 4319 op = optab[mlx5_cur][mlx5_new]; 4320 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4321 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4322 4323 if (qp->type == IB_QPT_RAW_PACKET || 4324 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4325 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4326 4327 raw_qp_param.operation = op; 4328 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4329 raw_qp_param.rq_q_ctr_id = set_id; 4330 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4331 } 4332 4333 if (attr_mask & IB_QP_PORT) 4334 raw_qp_param.port = attr->port_num; 4335 4336 if (attr_mask & IB_QP_RATE_LIMIT) { 4337 raw_qp_param.rl.rate = attr->rate_limit; 4338 4339 if (ucmd->burst_info.max_burst_sz) { 4340 if (attr->rate_limit && 4341 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4342 raw_qp_param.rl.max_burst_sz = 4343 ucmd->burst_info.max_burst_sz; 4344 } else { 4345 err = -EINVAL; 4346 goto out; 4347 } 4348 } 4349 4350 if (ucmd->burst_info.typical_pkt_sz) { 4351 if (attr->rate_limit && 4352 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4353 raw_qp_param.rl.typical_pkt_sz = 4354 ucmd->burst_info.typical_pkt_sz; 4355 } else { 4356 err = -EINVAL; 4357 goto out; 4358 } 4359 } 4360 4361 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4362 } 4363 4364 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4365 } else { 4366 if (udata) { 4367 /* For the kernel flows, the resp will stay zero */ 4368 resp->ece_options = 4369 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4370 ucmd->ece_options : 0; 4371 resp->response_length = sizeof(*resp); 4372 } 4373 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4374 &resp->ece_options); 4375 } 4376 4377 if (err) 4378 goto out; 4379 4380 qp->state = new_state; 4381 4382 if (attr_mask & IB_QP_ACCESS_FLAGS) 4383 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4384 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4385 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4386 if (attr_mask & IB_QP_PORT) 4387 qp->port = attr->port_num; 4388 if (attr_mask & IB_QP_ALT_PATH) 4389 qp->trans_qp.alt_port = attr->alt_port_num; 4390 4391 /* 4392 * If we moved a kernel QP to RESET, clean up all old CQ 4393 * entries and reinitialize the QP. 4394 */ 4395 if (new_state == IB_QPS_RESET && 4396 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4397 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4398 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4399 if (send_cq != recv_cq) 4400 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4401 4402 qp->rq.head = 0; 4403 qp->rq.tail = 0; 4404 qp->sq.head = 0; 4405 qp->sq.tail = 0; 4406 qp->sq.cur_post = 0; 4407 if (qp->sq.wqe_cnt) 4408 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4409 qp->sq.last_poll = 0; 4410 qp->db.db[MLX5_RCV_DBR] = 0; 4411 qp->db.db[MLX5_SND_DBR] = 0; 4412 } 4413 4414 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4415 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4416 if (!err) 4417 qp->counter_pending = 0; 4418 } 4419 4420 out: 4421 kfree(qpc); 4422 return err; 4423 } 4424 4425 static inline bool is_valid_mask(int mask, int req, int opt) 4426 { 4427 if ((mask & req) != req) 4428 return false; 4429 4430 if (mask & ~(req | opt)) 4431 return false; 4432 4433 return true; 4434 } 4435 4436 /* check valid transition for driver QP types 4437 * for now the only QP type that this function supports is DCI 4438 */ 4439 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4440 enum ib_qp_attr_mask attr_mask) 4441 { 4442 int req = IB_QP_STATE; 4443 int opt = 0; 4444 4445 if (new_state == IB_QPS_RESET) { 4446 return is_valid_mask(attr_mask, req, opt); 4447 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4448 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4449 return is_valid_mask(attr_mask, req, opt); 4450 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4451 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4452 return is_valid_mask(attr_mask, req, opt); 4453 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4454 req |= IB_QP_PATH_MTU; 4455 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4456 return is_valid_mask(attr_mask, req, opt); 4457 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4458 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4459 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4460 opt = IB_QP_MIN_RNR_TIMER; 4461 return is_valid_mask(attr_mask, req, opt); 4462 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4463 opt = IB_QP_MIN_RNR_TIMER; 4464 return is_valid_mask(attr_mask, req, opt); 4465 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4466 return is_valid_mask(attr_mask, req, opt); 4467 } 4468 return false; 4469 } 4470 4471 /* mlx5_ib_modify_dct: modify a DCT QP 4472 * valid transitions are: 4473 * RESET to INIT: must set access_flags, pkey_index and port 4474 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4475 * mtu, gid_index and hop_limit 4476 * Other transitions and attributes are illegal 4477 */ 4478 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4479 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4480 struct ib_udata *udata) 4481 { 4482 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4483 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4484 enum ib_qp_state cur_state, new_state; 4485 int required = IB_QP_STATE; 4486 void *dctc; 4487 int err; 4488 4489 if (!(attr_mask & IB_QP_STATE)) 4490 return -EINVAL; 4491 4492 cur_state = qp->state; 4493 new_state = attr->qp_state; 4494 4495 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4496 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4497 /* 4498 * DCT doesn't initialize QP till modify command is executed, 4499 * so we need to overwrite previously set ECE field if user 4500 * provided any value except zero, which means not set/not 4501 * valid. 4502 */ 4503 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4504 4505 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4506 u16 set_id; 4507 4508 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4509 if (!is_valid_mask(attr_mask, required, 0)) 4510 return -EINVAL; 4511 4512 if (attr->port_num == 0 || 4513 attr->port_num > dev->num_ports) { 4514 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4515 attr->port_num, dev->num_ports); 4516 return -EINVAL; 4517 } 4518 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4519 MLX5_SET(dctc, dctc, rre, 1); 4520 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4521 MLX5_SET(dctc, dctc, rwe, 1); 4522 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4523 int atomic_mode; 4524 4525 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4526 if (atomic_mode < 0) 4527 return -EOPNOTSUPP; 4528 4529 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4530 MLX5_SET(dctc, dctc, rae, 1); 4531 } 4532 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4533 if (mlx5_lag_is_active(dev->mdev)) 4534 MLX5_SET(dctc, dctc, port, 4535 get_tx_affinity_rr(dev, udata)); 4536 else 4537 MLX5_SET(dctc, dctc, port, attr->port_num); 4538 4539 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4540 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4541 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4542 struct mlx5_ib_modify_qp_resp resp = {}; 4543 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4544 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4545 4546 if (udata->outlen < min_resp_len) 4547 return -EINVAL; 4548 /* 4549 * If we don't have enough space for the ECE options, 4550 * simply indicate it with resp.response_length. 4551 */ 4552 resp.response_length = (udata->outlen < sizeof(resp)) ? 4553 min_resp_len : 4554 sizeof(resp); 4555 4556 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4557 if (!is_valid_mask(attr_mask, required, 0)) 4558 return -EINVAL; 4559 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4560 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4561 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4562 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4563 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4564 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4565 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) 4566 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7); 4567 4568 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4569 MLX5_ST_SZ_BYTES(create_dct_in), out, 4570 sizeof(out)); 4571 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); 4572 if (err) 4573 return err; 4574 resp.dctn = qp->dct.mdct.mqp.qpn; 4575 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4576 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4577 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4578 if (err) { 4579 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4580 return err; 4581 } 4582 } else { 4583 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4584 return -EINVAL; 4585 } 4586 4587 qp->state = new_state; 4588 return 0; 4589 } 4590 4591 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4592 struct mlx5_ib_qp *qp) 4593 { 4594 if (dev->profile != &raw_eth_profile) 4595 return true; 4596 4597 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4598 return true; 4599 4600 return false; 4601 } 4602 4603 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr, 4604 int attr_mask, enum ib_qp_type qp_type) 4605 { 4606 int log_max_ra_res; 4607 int log_max_ra_req; 4608 4609 if (qp_type == MLX5_IB_QPT_DCI) { 4610 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4611 log_max_ra_res_dc); 4612 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4613 log_max_ra_req_dc); 4614 } else { 4615 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4616 log_max_ra_res_qp); 4617 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4618 log_max_ra_req_qp); 4619 } 4620 4621 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4622 attr->max_rd_atomic > log_max_ra_res) { 4623 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4624 attr->max_rd_atomic); 4625 return false; 4626 } 4627 4628 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4629 attr->max_dest_rd_atomic > log_max_ra_req) { 4630 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4631 attr->max_dest_rd_atomic); 4632 return false; 4633 } 4634 return true; 4635 } 4636 4637 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4638 int attr_mask, struct ib_udata *udata) 4639 { 4640 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4641 struct mlx5_ib_modify_qp_resp resp = {}; 4642 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4643 struct mlx5_ib_modify_qp ucmd = {}; 4644 enum ib_qp_type qp_type; 4645 enum ib_qp_state cur_state, new_state; 4646 int err = -EINVAL; 4647 4648 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4649 return -EOPNOTSUPP; 4650 4651 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4652 return -EOPNOTSUPP; 4653 4654 if (ibqp->rwq_ind_tbl) 4655 return -ENOSYS; 4656 4657 if (udata && udata->inlen) { 4658 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4659 return -EINVAL; 4660 4661 if (udata->inlen > sizeof(ucmd) && 4662 !ib_is_udata_cleared(udata, sizeof(ucmd), 4663 udata->inlen - sizeof(ucmd))) 4664 return -EOPNOTSUPP; 4665 4666 if (ib_copy_from_udata(&ucmd, udata, 4667 min(udata->inlen, sizeof(ucmd)))) 4668 return -EFAULT; 4669 4670 if (ucmd.comp_mask || 4671 memchr_inv(&ucmd.burst_info.reserved, 0, 4672 sizeof(ucmd.burst_info.reserved))) 4673 return -EOPNOTSUPP; 4674 4675 } 4676 4677 if (qp->type == IB_QPT_GSI) 4678 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4679 4680 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4681 4682 if (qp_type == MLX5_IB_QPT_DCT) 4683 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4684 4685 mutex_lock(&qp->mutex); 4686 4687 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4688 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4689 4690 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4691 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4692 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4693 attr_mask); 4694 goto out; 4695 } 4696 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4697 qp_type != MLX5_IB_QPT_DCI && 4698 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4699 attr_mask)) { 4700 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4701 cur_state, new_state, qp->type, attr_mask); 4702 goto out; 4703 } else if (qp_type == MLX5_IB_QPT_DCI && 4704 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4705 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4706 cur_state, new_state, qp_type, attr_mask); 4707 goto out; 4708 } 4709 4710 if ((attr_mask & IB_QP_PORT) && 4711 (attr->port_num == 0 || 4712 attr->port_num > dev->num_ports)) { 4713 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4714 attr->port_num, dev->num_ports); 4715 goto out; 4716 } 4717 4718 if ((attr_mask & IB_QP_PKEY_INDEX) && 4719 attr->pkey_index >= dev->pkey_table_len) { 4720 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4721 goto out; 4722 } 4723 4724 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type)) 4725 goto out; 4726 4727 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4728 err = 0; 4729 goto out; 4730 } 4731 4732 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4733 new_state, &ucmd, &resp, udata); 4734 4735 /* resp.response_length is set in ECE supported flows only */ 4736 if (!err && resp.response_length && 4737 udata->outlen >= resp.response_length) 4738 /* Return -EFAULT to the user and expect him to destroy QP. */ 4739 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4740 4741 out: 4742 mutex_unlock(&qp->mutex); 4743 return err; 4744 } 4745 4746 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4747 { 4748 switch (mlx5_state) { 4749 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4750 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4751 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4752 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4753 case MLX5_QP_STATE_SQ_DRAINING: 4754 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4755 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4756 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4757 default: return -1; 4758 } 4759 } 4760 4761 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4762 { 4763 switch (mlx5_mig_state) { 4764 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4765 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4766 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4767 default: return -1; 4768 } 4769 } 4770 4771 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4772 struct rdma_ah_attr *ah_attr, void *path) 4773 { 4774 int port = MLX5_GET(ads, path, vhca_port_num); 4775 int static_rate; 4776 4777 memset(ah_attr, 0, sizeof(*ah_attr)); 4778 4779 if (!port || port > ibdev->num_ports) 4780 return; 4781 4782 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4783 4784 rdma_ah_set_port_num(ah_attr, port); 4785 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4786 4787 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4788 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4789 4790 static_rate = MLX5_GET(ads, path, stat_rate); 4791 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4792 if (MLX5_GET(ads, path, grh) || 4793 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4794 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4795 MLX5_GET(ads, path, src_addr_index), 4796 MLX5_GET(ads, path, hop_limit), 4797 MLX5_GET(ads, path, tclass)); 4798 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4799 } 4800 } 4801 4802 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4803 struct mlx5_ib_sq *sq, 4804 u8 *sq_state) 4805 { 4806 int err; 4807 4808 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4809 if (err) 4810 goto out; 4811 sq->state = *sq_state; 4812 4813 out: 4814 return err; 4815 } 4816 4817 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4818 struct mlx5_ib_rq *rq, 4819 u8 *rq_state) 4820 { 4821 void *out; 4822 void *rqc; 4823 int inlen; 4824 int err; 4825 4826 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4827 out = kvzalloc(inlen, GFP_KERNEL); 4828 if (!out) 4829 return -ENOMEM; 4830 4831 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4832 if (err) 4833 goto out; 4834 4835 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4836 *rq_state = MLX5_GET(rqc, rqc, state); 4837 rq->state = *rq_state; 4838 4839 out: 4840 kvfree(out); 4841 return err; 4842 } 4843 4844 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4845 struct mlx5_ib_qp *qp, u8 *qp_state) 4846 { 4847 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4848 [MLX5_RQC_STATE_RST] = { 4849 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4850 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4851 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4852 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4853 }, 4854 [MLX5_RQC_STATE_RDY] = { 4855 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4856 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4857 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4858 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4859 }, 4860 [MLX5_RQC_STATE_ERR] = { 4861 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4862 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4863 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4864 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4865 }, 4866 [MLX5_RQ_STATE_NA] = { 4867 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4868 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4869 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4870 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4871 }, 4872 }; 4873 4874 *qp_state = sqrq_trans[rq_state][sq_state]; 4875 4876 if (*qp_state == MLX5_QP_STATE_BAD) { 4877 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4878 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4879 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4880 return -EINVAL; 4881 } 4882 4883 if (*qp_state == MLX5_QP_STATE) 4884 *qp_state = qp->state; 4885 4886 return 0; 4887 } 4888 4889 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4890 struct mlx5_ib_qp *qp, 4891 u8 *raw_packet_qp_state) 4892 { 4893 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4894 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4895 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4896 int err; 4897 u8 sq_state = MLX5_SQ_STATE_NA; 4898 u8 rq_state = MLX5_RQ_STATE_NA; 4899 4900 if (qp->sq.wqe_cnt) { 4901 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4902 if (err) 4903 return err; 4904 } 4905 4906 if (qp->rq.wqe_cnt) { 4907 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4908 if (err) 4909 return err; 4910 } 4911 4912 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4913 raw_packet_qp_state); 4914 } 4915 4916 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4917 struct ib_qp_attr *qp_attr) 4918 { 4919 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4920 void *qpc, *pri_path, *alt_path; 4921 u32 *outb; 4922 int err; 4923 4924 outb = kzalloc(outlen, GFP_KERNEL); 4925 if (!outb) 4926 return -ENOMEM; 4927 4928 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 4929 false); 4930 if (err) 4931 goto out; 4932 4933 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4934 4935 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4936 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4937 qp_attr->sq_draining = 1; 4938 4939 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4940 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4941 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4942 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4943 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4944 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4945 4946 if (MLX5_GET(qpc, qpc, rre)) 4947 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4948 if (MLX5_GET(qpc, qpc, rwe)) 4949 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4950 if (MLX5_GET(qpc, qpc, rae)) 4951 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4952 4953 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4954 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4955 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4956 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4957 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4958 4959 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4960 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4961 4962 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 4963 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 4964 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4965 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4966 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4967 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4968 } 4969 4970 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4971 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4972 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4973 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4974 4975 out: 4976 kfree(outb); 4977 return err; 4978 } 4979 4980 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4981 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4982 struct ib_qp_init_attr *qp_init_attr) 4983 { 4984 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4985 u32 *out; 4986 u32 access_flags = 0; 4987 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4988 void *dctc; 4989 int err; 4990 int supported_mask = IB_QP_STATE | 4991 IB_QP_ACCESS_FLAGS | 4992 IB_QP_PORT | 4993 IB_QP_MIN_RNR_TIMER | 4994 IB_QP_AV | 4995 IB_QP_PATH_MTU | 4996 IB_QP_PKEY_INDEX; 4997 4998 if (qp_attr_mask & ~supported_mask) 4999 return -EINVAL; 5000 if (mqp->state != IB_QPS_RTR) 5001 return -EINVAL; 5002 5003 out = kzalloc(outlen, GFP_KERNEL); 5004 if (!out) 5005 return -ENOMEM; 5006 5007 err = mlx5_core_dct_query(dev, dct, out, outlen); 5008 if (err) 5009 goto out; 5010 5011 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5012 5013 if (qp_attr_mask & IB_QP_STATE) 5014 qp_attr->qp_state = IB_QPS_RTR; 5015 5016 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5017 if (MLX5_GET(dctc, dctc, rre)) 5018 access_flags |= IB_ACCESS_REMOTE_READ; 5019 if (MLX5_GET(dctc, dctc, rwe)) 5020 access_flags |= IB_ACCESS_REMOTE_WRITE; 5021 if (MLX5_GET(dctc, dctc, rae)) 5022 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5023 qp_attr->qp_access_flags = access_flags; 5024 } 5025 5026 if (qp_attr_mask & IB_QP_PORT) 5027 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 5028 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5029 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5030 if (qp_attr_mask & IB_QP_AV) { 5031 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5032 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5033 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5034 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5035 } 5036 if (qp_attr_mask & IB_QP_PATH_MTU) 5037 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5038 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5039 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5040 out: 5041 kfree(out); 5042 return err; 5043 } 5044 5045 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5046 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5047 { 5048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5049 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5050 int err = 0; 5051 u8 raw_packet_qp_state; 5052 5053 if (ibqp->rwq_ind_tbl) 5054 return -ENOSYS; 5055 5056 if (qp->type == IB_QPT_GSI) 5057 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5058 qp_init_attr); 5059 5060 /* Not all of output fields are applicable, make sure to zero them */ 5061 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5062 memset(qp_attr, 0, sizeof(*qp_attr)); 5063 5064 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 5065 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5066 qp_attr_mask, qp_init_attr); 5067 5068 mutex_lock(&qp->mutex); 5069 5070 if (qp->type == IB_QPT_RAW_PACKET || 5071 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 5072 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5073 if (err) 5074 goto out; 5075 qp->state = raw_packet_qp_state; 5076 qp_attr->port_num = 1; 5077 } else { 5078 err = query_qp_attr(dev, qp, qp_attr); 5079 if (err) 5080 goto out; 5081 } 5082 5083 qp_attr->qp_state = qp->state; 5084 qp_attr->cur_qp_state = qp_attr->qp_state; 5085 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5086 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5087 5088 if (!ibqp->uobject) { 5089 qp_attr->cap.max_send_wr = qp->sq.max_post; 5090 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5091 qp_init_attr->qp_context = ibqp->qp_context; 5092 } else { 5093 qp_attr->cap.max_send_wr = 0; 5094 qp_attr->cap.max_send_sge = 0; 5095 } 5096 5097 qp_init_attr->qp_type = qp->type; 5098 qp_init_attr->recv_cq = ibqp->recv_cq; 5099 qp_init_attr->send_cq = ibqp->send_cq; 5100 qp_init_attr->srq = ibqp->srq; 5101 qp_attr->cap.max_inline_data = qp->max_inline_data; 5102 5103 qp_init_attr->cap = qp_attr->cap; 5104 5105 qp_init_attr->create_flags = qp->flags; 5106 5107 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5108 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5109 5110 out: 5111 mutex_unlock(&qp->mutex); 5112 return err; 5113 } 5114 5115 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 5116 { 5117 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 5118 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 5119 5120 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5121 return -EOPNOTSUPP; 5122 5123 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5124 } 5125 5126 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5127 { 5128 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5129 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5130 5131 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5132 } 5133 5134 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5135 { 5136 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5137 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5138 struct ib_event event; 5139 5140 if (rwq->ibwq.event_handler) { 5141 event.device = rwq->ibwq.device; 5142 event.element.wq = &rwq->ibwq; 5143 switch (type) { 5144 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5145 event.event = IB_EVENT_WQ_FATAL; 5146 break; 5147 default: 5148 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5149 return; 5150 } 5151 5152 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5153 } 5154 } 5155 5156 static int set_delay_drop(struct mlx5_ib_dev *dev) 5157 { 5158 int err = 0; 5159 5160 mutex_lock(&dev->delay_drop.lock); 5161 if (dev->delay_drop.activate) 5162 goto out; 5163 5164 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5165 if (err) 5166 goto out; 5167 5168 dev->delay_drop.activate = true; 5169 out: 5170 mutex_unlock(&dev->delay_drop.lock); 5171 5172 if (!err) 5173 atomic_inc(&dev->delay_drop.rqs_cnt); 5174 return err; 5175 } 5176 5177 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5178 struct ib_wq_init_attr *init_attr) 5179 { 5180 struct mlx5_ib_dev *dev; 5181 int has_net_offloads; 5182 __be64 *rq_pas0; 5183 int ts_format; 5184 void *in; 5185 void *rqc; 5186 void *wq; 5187 int inlen; 5188 int err; 5189 5190 dev = to_mdev(pd->device); 5191 5192 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5193 if (ts_format < 0) 5194 return ts_format; 5195 5196 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5197 in = kvzalloc(inlen, GFP_KERNEL); 5198 if (!in) 5199 return -ENOMEM; 5200 5201 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5202 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5203 MLX5_SET(rqc, rqc, mem_rq_type, 5204 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5205 MLX5_SET(rqc, rqc, ts_format, ts_format); 5206 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5207 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5208 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5209 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5210 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5211 MLX5_SET(wq, wq, wq_type, 5212 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5213 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5214 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5215 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5216 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5217 err = -EOPNOTSUPP; 5218 goto out; 5219 } else { 5220 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5221 } 5222 } 5223 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5224 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5225 /* 5226 * In Firmware number of strides in each WQE is: 5227 * "512 * 2^single_wqe_log_num_of_strides" 5228 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5229 * accepted as 0 to 9 5230 */ 5231 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5232 2, 3, 4, 5, 6, 7, 8, 9 }; 5233 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5234 MLX5_SET(wq, wq, log_wqe_stride_size, 5235 rwq->single_stride_log_num_of_bytes - 5236 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5237 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5238 fw_map[rwq->log_num_strides - 5239 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5240 } 5241 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5242 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5243 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5244 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5245 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5246 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5247 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5248 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5249 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5250 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5251 err = -EOPNOTSUPP; 5252 goto out; 5253 } 5254 } else { 5255 MLX5_SET(rqc, rqc, vsd, 1); 5256 } 5257 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5258 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5259 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5260 err = -EOPNOTSUPP; 5261 goto out; 5262 } 5263 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5264 } 5265 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5266 if (!(dev->ib_dev.attrs.raw_packet_caps & 5267 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5268 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5269 err = -EOPNOTSUPP; 5270 goto out; 5271 } 5272 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5273 } 5274 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5275 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5276 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5277 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5278 err = set_delay_drop(dev); 5279 if (err) { 5280 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5281 err); 5282 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5283 } else { 5284 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5285 } 5286 } 5287 out: 5288 kvfree(in); 5289 return err; 5290 } 5291 5292 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5293 struct ib_wq_init_attr *wq_init_attr, 5294 struct mlx5_ib_create_wq *ucmd, 5295 struct mlx5_ib_rwq *rwq) 5296 { 5297 /* Sanity check RQ size before proceeding */ 5298 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5299 return -EINVAL; 5300 5301 if (!ucmd->rq_wqe_count) 5302 return -EINVAL; 5303 5304 rwq->wqe_count = ucmd->rq_wqe_count; 5305 rwq->wqe_shift = ucmd->rq_wqe_shift; 5306 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5307 return -EINVAL; 5308 5309 rwq->log_rq_stride = rwq->wqe_shift; 5310 rwq->log_rq_size = ilog2(rwq->wqe_count); 5311 return 0; 5312 } 5313 5314 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5315 { 5316 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5317 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5318 return false; 5319 5320 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5321 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5322 return false; 5323 5324 return true; 5325 } 5326 5327 static int prepare_user_rq(struct ib_pd *pd, 5328 struct ib_wq_init_attr *init_attr, 5329 struct ib_udata *udata, 5330 struct mlx5_ib_rwq *rwq) 5331 { 5332 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5333 struct mlx5_ib_create_wq ucmd = {}; 5334 int err; 5335 size_t required_cmd_sz; 5336 5337 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 5338 single_stride_log_num_of_bytes); 5339 if (udata->inlen < required_cmd_sz) { 5340 mlx5_ib_dbg(dev, "invalid inlen\n"); 5341 return -EINVAL; 5342 } 5343 5344 if (udata->inlen > sizeof(ucmd) && 5345 !ib_is_udata_cleared(udata, sizeof(ucmd), 5346 udata->inlen - sizeof(ucmd))) { 5347 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5348 return -EOPNOTSUPP; 5349 } 5350 5351 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5352 mlx5_ib_dbg(dev, "copy failed\n"); 5353 return -EFAULT; 5354 } 5355 5356 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5357 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5358 return -EOPNOTSUPP; 5359 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5360 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5361 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5362 return -EOPNOTSUPP; 5363 } 5364 if ((ucmd.single_stride_log_num_of_bytes < 5365 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5366 (ucmd.single_stride_log_num_of_bytes > 5367 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5368 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5369 ucmd.single_stride_log_num_of_bytes, 5370 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5371 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5372 return -EINVAL; 5373 } 5374 if (!log_of_strides_valid(dev, 5375 ucmd.single_wqe_log_num_of_strides)) { 5376 mlx5_ib_dbg( 5377 dev, 5378 "Invalid log num strides (%u. Range is %u - %u)\n", 5379 ucmd.single_wqe_log_num_of_strides, 5380 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5381 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5382 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5383 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5384 return -EINVAL; 5385 } 5386 rwq->single_stride_log_num_of_bytes = 5387 ucmd.single_stride_log_num_of_bytes; 5388 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5389 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5390 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5391 } 5392 5393 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5394 if (err) { 5395 mlx5_ib_dbg(dev, "err %d\n", err); 5396 return err; 5397 } 5398 5399 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5400 if (err) { 5401 mlx5_ib_dbg(dev, "err %d\n", err); 5402 return err; 5403 } 5404 5405 rwq->user_index = ucmd.user_index; 5406 return 0; 5407 } 5408 5409 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5410 struct ib_wq_init_attr *init_attr, 5411 struct ib_udata *udata) 5412 { 5413 struct mlx5_ib_dev *dev; 5414 struct mlx5_ib_rwq *rwq; 5415 struct mlx5_ib_create_wq_resp resp = {}; 5416 size_t min_resp_len; 5417 int err; 5418 5419 if (!udata) 5420 return ERR_PTR(-ENOSYS); 5421 5422 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5423 if (udata->outlen && udata->outlen < min_resp_len) 5424 return ERR_PTR(-EINVAL); 5425 5426 if (!capable(CAP_SYS_RAWIO) && 5427 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5428 return ERR_PTR(-EPERM); 5429 5430 dev = to_mdev(pd->device); 5431 switch (init_attr->wq_type) { 5432 case IB_WQT_RQ: 5433 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5434 if (!rwq) 5435 return ERR_PTR(-ENOMEM); 5436 err = prepare_user_rq(pd, init_attr, udata, rwq); 5437 if (err) 5438 goto err; 5439 err = create_rq(rwq, pd, init_attr); 5440 if (err) 5441 goto err_user_rq; 5442 break; 5443 default: 5444 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5445 init_attr->wq_type); 5446 return ERR_PTR(-EINVAL); 5447 } 5448 5449 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5450 rwq->ibwq.state = IB_WQS_RESET; 5451 if (udata->outlen) { 5452 resp.response_length = offsetofend( 5453 struct mlx5_ib_create_wq_resp, response_length); 5454 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5455 if (err) 5456 goto err_copy; 5457 } 5458 5459 rwq->core_qp.event = mlx5_ib_wq_event; 5460 rwq->ibwq.event_handler = init_attr->event_handler; 5461 return &rwq->ibwq; 5462 5463 err_copy: 5464 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5465 err_user_rq: 5466 destroy_user_rq(dev, pd, rwq, udata); 5467 err: 5468 kfree(rwq); 5469 return ERR_PTR(err); 5470 } 5471 5472 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5473 { 5474 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5475 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5476 int ret; 5477 5478 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5479 if (ret) 5480 return ret; 5481 destroy_user_rq(dev, wq->pd, rwq, udata); 5482 kfree(rwq); 5483 return 0; 5484 } 5485 5486 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5487 struct ib_rwq_ind_table_init_attr *init_attr, 5488 struct ib_udata *udata) 5489 { 5490 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5491 to_mrwq_ind_table(ib_rwq_ind_table); 5492 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5493 int sz = 1 << init_attr->log_ind_tbl_size; 5494 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5495 size_t min_resp_len; 5496 int inlen; 5497 int err; 5498 int i; 5499 u32 *in; 5500 void *rqtc; 5501 5502 if (udata->inlen > 0 && 5503 !ib_is_udata_cleared(udata, 0, 5504 udata->inlen)) 5505 return -EOPNOTSUPP; 5506 5507 if (init_attr->log_ind_tbl_size > 5508 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5509 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5510 init_attr->log_ind_tbl_size, 5511 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5512 return -EINVAL; 5513 } 5514 5515 min_resp_len = 5516 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5517 if (udata->outlen && udata->outlen < min_resp_len) 5518 return -EINVAL; 5519 5520 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5521 in = kvzalloc(inlen, GFP_KERNEL); 5522 if (!in) 5523 return -ENOMEM; 5524 5525 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5526 5527 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5528 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5529 5530 for (i = 0; i < sz; i++) 5531 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5532 5533 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5534 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5535 5536 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5537 kvfree(in); 5538 if (err) 5539 return err; 5540 5541 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5542 if (udata->outlen) { 5543 resp.response_length = 5544 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5545 response_length); 5546 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5547 if (err) 5548 goto err_copy; 5549 } 5550 5551 return 0; 5552 5553 err_copy: 5554 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5555 return err; 5556 } 5557 5558 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5559 { 5560 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5561 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5562 5563 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5564 } 5565 5566 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5567 u32 wq_attr_mask, struct ib_udata *udata) 5568 { 5569 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5570 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5571 struct mlx5_ib_modify_wq ucmd = {}; 5572 size_t required_cmd_sz; 5573 int curr_wq_state; 5574 int wq_state; 5575 int inlen; 5576 int err; 5577 void *rqc; 5578 void *in; 5579 5580 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5581 if (udata->inlen < required_cmd_sz) 5582 return -EINVAL; 5583 5584 if (udata->inlen > sizeof(ucmd) && 5585 !ib_is_udata_cleared(udata, sizeof(ucmd), 5586 udata->inlen - sizeof(ucmd))) 5587 return -EOPNOTSUPP; 5588 5589 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5590 return -EFAULT; 5591 5592 if (ucmd.comp_mask || ucmd.reserved) 5593 return -EOPNOTSUPP; 5594 5595 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5596 in = kvzalloc(inlen, GFP_KERNEL); 5597 if (!in) 5598 return -ENOMEM; 5599 5600 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5601 5602 curr_wq_state = wq_attr->curr_wq_state; 5603 wq_state = wq_attr->wq_state; 5604 if (curr_wq_state == IB_WQS_ERR) 5605 curr_wq_state = MLX5_RQC_STATE_ERR; 5606 if (wq_state == IB_WQS_ERR) 5607 wq_state = MLX5_RQC_STATE_ERR; 5608 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5609 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5610 MLX5_SET(rqc, rqc, state, wq_state); 5611 5612 if (wq_attr_mask & IB_WQ_FLAGS) { 5613 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5614 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5615 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5616 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5617 err = -EOPNOTSUPP; 5618 goto out; 5619 } 5620 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5621 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5622 MLX5_SET(rqc, rqc, vsd, 5623 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5624 } 5625 5626 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5627 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5628 err = -EOPNOTSUPP; 5629 goto out; 5630 } 5631 } 5632 5633 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5634 u16 set_id; 5635 5636 set_id = mlx5_ib_get_counters_id(dev, 0); 5637 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5638 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5639 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5640 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5641 } else 5642 dev_info_once( 5643 &dev->ib_dev.dev, 5644 "Receive WQ counters are not supported on current FW\n"); 5645 } 5646 5647 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5648 if (!err) 5649 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5650 5651 out: 5652 kvfree(in); 5653 return err; 5654 } 5655 5656 struct mlx5_ib_drain_cqe { 5657 struct ib_cqe cqe; 5658 struct completion done; 5659 }; 5660 5661 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5662 { 5663 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5664 struct mlx5_ib_drain_cqe, 5665 cqe); 5666 5667 complete(&cqe->done); 5668 } 5669 5670 /* This function returns only once the drained WR was completed */ 5671 static void handle_drain_completion(struct ib_cq *cq, 5672 struct mlx5_ib_drain_cqe *sdrain, 5673 struct mlx5_ib_dev *dev) 5674 { 5675 struct mlx5_core_dev *mdev = dev->mdev; 5676 5677 if (cq->poll_ctx == IB_POLL_DIRECT) { 5678 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5679 ib_process_cq_direct(cq, -1); 5680 return; 5681 } 5682 5683 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5684 struct mlx5_ib_cq *mcq = to_mcq(cq); 5685 bool triggered = false; 5686 unsigned long flags; 5687 5688 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5689 /* Make sure that the CQ handler won't run if wasn't run yet */ 5690 if (!mcq->mcq.reset_notify_added) 5691 mcq->mcq.reset_notify_added = 1; 5692 else 5693 triggered = true; 5694 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5695 5696 if (triggered) { 5697 /* Wait for any scheduled/running task to be ended */ 5698 switch (cq->poll_ctx) { 5699 case IB_POLL_SOFTIRQ: 5700 irq_poll_disable(&cq->iop); 5701 irq_poll_enable(&cq->iop); 5702 break; 5703 case IB_POLL_WORKQUEUE: 5704 cancel_work_sync(&cq->work); 5705 break; 5706 default: 5707 WARN_ON_ONCE(1); 5708 } 5709 } 5710 5711 /* Run the CQ handler - this makes sure that the drain WR will 5712 * be processed if wasn't processed yet. 5713 */ 5714 mcq->mcq.comp(&mcq->mcq, NULL); 5715 } 5716 5717 wait_for_completion(&sdrain->done); 5718 } 5719 5720 void mlx5_ib_drain_sq(struct ib_qp *qp) 5721 { 5722 struct ib_cq *cq = qp->send_cq; 5723 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5724 struct mlx5_ib_drain_cqe sdrain; 5725 const struct ib_send_wr *bad_swr; 5726 struct ib_rdma_wr swr = { 5727 .wr = { 5728 .next = NULL, 5729 { .wr_cqe = &sdrain.cqe, }, 5730 .opcode = IB_WR_RDMA_WRITE, 5731 }, 5732 }; 5733 int ret; 5734 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5735 struct mlx5_core_dev *mdev = dev->mdev; 5736 5737 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5738 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5739 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5740 return; 5741 } 5742 5743 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5744 init_completion(&sdrain.done); 5745 5746 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5747 if (ret) { 5748 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5749 return; 5750 } 5751 5752 handle_drain_completion(cq, &sdrain, dev); 5753 } 5754 5755 void mlx5_ib_drain_rq(struct ib_qp *qp) 5756 { 5757 struct ib_cq *cq = qp->recv_cq; 5758 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5759 struct mlx5_ib_drain_cqe rdrain; 5760 struct ib_recv_wr rwr = {}; 5761 const struct ib_recv_wr *bad_rwr; 5762 int ret; 5763 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5764 struct mlx5_core_dev *mdev = dev->mdev; 5765 5766 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5767 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5768 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5769 return; 5770 } 5771 5772 rwr.wr_cqe = &rdrain.cqe; 5773 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5774 init_completion(&rdrain.done); 5775 5776 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5777 if (ret) { 5778 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5779 return; 5780 } 5781 5782 handle_drain_completion(cq, &rdrain, dev); 5783 } 5784 5785 /* 5786 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5787 * the default counter 5788 */ 5789 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5790 { 5791 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5792 struct mlx5_ib_qp *mqp = to_mqp(qp); 5793 int err = 0; 5794 5795 mutex_lock(&mqp->mutex); 5796 if (mqp->state == IB_QPS_RESET) { 5797 qp->counter = counter; 5798 goto out; 5799 } 5800 5801 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5802 err = -EOPNOTSUPP; 5803 goto out; 5804 } 5805 5806 if (mqp->state == IB_QPS_RTS) { 5807 err = __mlx5_ib_qp_set_counter(qp, counter); 5808 if (!err) 5809 qp->counter = counter; 5810 5811 goto out; 5812 } 5813 5814 mqp->counter_pending = 1; 5815 qp->counter = counter; 5816 5817 out: 5818 mutex_unlock(&mqp->mutex); 5819 return err; 5820 } 5821 5822 int mlx5_ib_qp_event_init(void) 5823 { 5824 mlx5_ib_qp_event_wq = alloc_ordered_workqueue("mlx5_ib_qp_event_wq", 0); 5825 if (!mlx5_ib_qp_event_wq) 5826 return -ENOMEM; 5827 5828 return 0; 5829 } 5830 5831 void mlx5_ib_qp_event_cleanup(void) 5832 { 5833 destroy_workqueue(mlx5_ib_qp_event_wq); 5834 } 5835