1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 34 #include <linux/kref.h> 35 #include <linux/random.h> 36 #include <linux/debugfs.h> 37 #include <linux/export.h> 38 #include <linux/delay.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_umem_odp.h> 41 #include <rdma/ib_verbs.h> 42 #include "mlx5_ib.h" 43 44 enum { 45 MAX_PENDING_REG_MR = 8, 46 }; 47 48 #define MLX5_UMR_ALIGN 2048 49 50 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 51 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 52 static int mr_cache_max_order(struct mlx5_ib_dev *dev); 53 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 54 static bool umr_can_modify_entity_size(struct mlx5_ib_dev *dev) 55 { 56 return !MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled); 57 } 58 59 static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev) 60 { 61 return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); 62 } 63 64 static bool use_umr(struct mlx5_ib_dev *dev, int order) 65 { 66 return order <= mr_cache_max_order(dev) && 67 umr_can_modify_entity_size(dev); 68 } 69 70 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 71 { 72 int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); 73 74 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 75 /* Wait until all page fault handlers using the mr complete. */ 76 synchronize_srcu(&dev->mr_srcu); 77 #endif 78 79 return err; 80 } 81 82 static int order2idx(struct mlx5_ib_dev *dev, int order) 83 { 84 struct mlx5_mr_cache *cache = &dev->cache; 85 86 if (order < cache->ent[0].order) 87 return 0; 88 else 89 return order - cache->ent[0].order; 90 } 91 92 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) 93 { 94 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= 95 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); 96 } 97 98 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 99 static void update_odp_mr(struct mlx5_ib_mr *mr) 100 { 101 if (mr->umem->is_odp) { 102 /* 103 * This barrier prevents the compiler from moving the 104 * setting of umem->odp_data->private to point to our 105 * MR, before reg_umr finished, to ensure that the MR 106 * initialization have finished before starting to 107 * handle invalidations. 108 */ 109 smp_wmb(); 110 to_ib_umem_odp(mr->umem)->private = mr; 111 /* 112 * Make sure we will see the new 113 * umem->odp_data->private value in the invalidation 114 * routines, before we can get page faults on the 115 * MR. Page faults can happen once we put the MR in 116 * the tree, below this line. Without the barrier, 117 * there can be a fault handling and an invalidation 118 * before umem->odp_data->private == mr is visible to 119 * the invalidation handler. 120 */ 121 smp_wmb(); 122 } 123 } 124 #endif 125 126 static void reg_mr_callback(int status, void *context) 127 { 128 struct mlx5_ib_mr *mr = context; 129 struct mlx5_ib_dev *dev = mr->dev; 130 struct mlx5_mr_cache *cache = &dev->cache; 131 int c = order2idx(dev, mr->order); 132 struct mlx5_cache_ent *ent = &cache->ent[c]; 133 u8 key; 134 unsigned long flags; 135 struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; 136 int err; 137 138 spin_lock_irqsave(&ent->lock, flags); 139 ent->pending--; 140 spin_unlock_irqrestore(&ent->lock, flags); 141 if (status) { 142 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); 143 kfree(mr); 144 dev->fill_delay = 1; 145 mod_timer(&dev->delay_timer, jiffies + HZ); 146 return; 147 } 148 149 mr->mmkey.type = MLX5_MKEY_MR; 150 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); 151 key = dev->mdev->priv.mkey_key++; 152 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); 153 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; 154 155 cache->last_add = jiffies; 156 157 spin_lock_irqsave(&ent->lock, flags); 158 list_add_tail(&mr->list, &ent->head); 159 ent->cur++; 160 ent->size++; 161 spin_unlock_irqrestore(&ent->lock, flags); 162 163 write_lock_irqsave(&table->lock, flags); 164 err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), 165 &mr->mmkey); 166 if (err) 167 pr_err("Error inserting to mkey tree. 0x%x\n", -err); 168 write_unlock_irqrestore(&table->lock, flags); 169 170 if (!completion_done(&ent->compl)) 171 complete(&ent->compl); 172 } 173 174 static int add_keys(struct mlx5_ib_dev *dev, int c, int num) 175 { 176 struct mlx5_mr_cache *cache = &dev->cache; 177 struct mlx5_cache_ent *ent = &cache->ent[c]; 178 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 179 struct mlx5_ib_mr *mr; 180 void *mkc; 181 u32 *in; 182 int err = 0; 183 int i; 184 185 in = kzalloc(inlen, GFP_KERNEL); 186 if (!in) 187 return -ENOMEM; 188 189 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 190 for (i = 0; i < num; i++) { 191 if (ent->pending >= MAX_PENDING_REG_MR) { 192 err = -EAGAIN; 193 break; 194 } 195 196 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 197 if (!mr) { 198 err = -ENOMEM; 199 break; 200 } 201 mr->order = ent->order; 202 mr->allocated_from_cache = 1; 203 mr->dev = dev; 204 205 MLX5_SET(mkc, mkc, free, 1); 206 MLX5_SET(mkc, mkc, umr_en, 1); 207 MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3); 208 MLX5_SET(mkc, mkc, access_mode_4_2, 209 (ent->access_mode >> 2) & 0x7); 210 211 MLX5_SET(mkc, mkc, qpn, 0xffffff); 212 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); 213 MLX5_SET(mkc, mkc, log_page_size, ent->page); 214 215 spin_lock_irq(&ent->lock); 216 ent->pending++; 217 spin_unlock_irq(&ent->lock); 218 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, 219 in, inlen, 220 mr->out, sizeof(mr->out), 221 reg_mr_callback, mr); 222 if (err) { 223 spin_lock_irq(&ent->lock); 224 ent->pending--; 225 spin_unlock_irq(&ent->lock); 226 mlx5_ib_warn(dev, "create mkey failed %d\n", err); 227 kfree(mr); 228 break; 229 } 230 } 231 232 kfree(in); 233 return err; 234 } 235 236 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) 237 { 238 struct mlx5_mr_cache *cache = &dev->cache; 239 struct mlx5_cache_ent *ent = &cache->ent[c]; 240 struct mlx5_ib_mr *tmp_mr; 241 struct mlx5_ib_mr *mr; 242 LIST_HEAD(del_list); 243 int i; 244 245 for (i = 0; i < num; i++) { 246 spin_lock_irq(&ent->lock); 247 if (list_empty(&ent->head)) { 248 spin_unlock_irq(&ent->lock); 249 break; 250 } 251 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); 252 list_move(&mr->list, &del_list); 253 ent->cur--; 254 ent->size--; 255 spin_unlock_irq(&ent->lock); 256 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); 257 } 258 259 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 260 synchronize_srcu(&dev->mr_srcu); 261 #endif 262 263 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) { 264 list_del(&mr->list); 265 kfree(mr); 266 } 267 } 268 269 static ssize_t size_write(struct file *filp, const char __user *buf, 270 size_t count, loff_t *pos) 271 { 272 struct mlx5_cache_ent *ent = filp->private_data; 273 struct mlx5_ib_dev *dev = ent->dev; 274 char lbuf[20] = {0}; 275 u32 var; 276 int err; 277 int c; 278 279 count = min(count, sizeof(lbuf) - 1); 280 if (copy_from_user(lbuf, buf, count)) 281 return -EFAULT; 282 283 c = order2idx(dev, ent->order); 284 285 if (sscanf(lbuf, "%u", &var) != 1) 286 return -EINVAL; 287 288 if (var < ent->limit) 289 return -EINVAL; 290 291 if (var > ent->size) { 292 do { 293 err = add_keys(dev, c, var - ent->size); 294 if (err && err != -EAGAIN) 295 return err; 296 297 usleep_range(3000, 5000); 298 } while (err); 299 } else if (var < ent->size) { 300 remove_keys(dev, c, ent->size - var); 301 } 302 303 return count; 304 } 305 306 static ssize_t size_read(struct file *filp, char __user *buf, size_t count, 307 loff_t *pos) 308 { 309 struct mlx5_cache_ent *ent = filp->private_data; 310 char lbuf[20]; 311 int err; 312 313 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); 314 if (err < 0) 315 return err; 316 317 return simple_read_from_buffer(buf, count, pos, lbuf, err); 318 } 319 320 static const struct file_operations size_fops = { 321 .owner = THIS_MODULE, 322 .open = simple_open, 323 .write = size_write, 324 .read = size_read, 325 }; 326 327 static ssize_t limit_write(struct file *filp, const char __user *buf, 328 size_t count, loff_t *pos) 329 { 330 struct mlx5_cache_ent *ent = filp->private_data; 331 struct mlx5_ib_dev *dev = ent->dev; 332 char lbuf[20] = {0}; 333 u32 var; 334 int err; 335 int c; 336 337 count = min(count, sizeof(lbuf) - 1); 338 if (copy_from_user(lbuf, buf, count)) 339 return -EFAULT; 340 341 c = order2idx(dev, ent->order); 342 343 if (sscanf(lbuf, "%u", &var) != 1) 344 return -EINVAL; 345 346 if (var > ent->size) 347 return -EINVAL; 348 349 ent->limit = var; 350 351 if (ent->cur < ent->limit) { 352 err = add_keys(dev, c, 2 * ent->limit - ent->cur); 353 if (err) 354 return err; 355 } 356 357 return count; 358 } 359 360 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, 361 loff_t *pos) 362 { 363 struct mlx5_cache_ent *ent = filp->private_data; 364 char lbuf[20]; 365 int err; 366 367 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); 368 if (err < 0) 369 return err; 370 371 return simple_read_from_buffer(buf, count, pos, lbuf, err); 372 } 373 374 static const struct file_operations limit_fops = { 375 .owner = THIS_MODULE, 376 .open = simple_open, 377 .write = limit_write, 378 .read = limit_read, 379 }; 380 381 static int someone_adding(struct mlx5_mr_cache *cache) 382 { 383 int i; 384 385 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 386 if (cache->ent[i].cur < cache->ent[i].limit) 387 return 1; 388 } 389 390 return 0; 391 } 392 393 static void __cache_work_func(struct mlx5_cache_ent *ent) 394 { 395 struct mlx5_ib_dev *dev = ent->dev; 396 struct mlx5_mr_cache *cache = &dev->cache; 397 int i = order2idx(dev, ent->order); 398 int err; 399 400 if (cache->stopped) 401 return; 402 403 ent = &dev->cache.ent[i]; 404 if (ent->cur < 2 * ent->limit && !dev->fill_delay) { 405 err = add_keys(dev, i, 1); 406 if (ent->cur < 2 * ent->limit) { 407 if (err == -EAGAIN) { 408 mlx5_ib_dbg(dev, "returned eagain, order %d\n", 409 i + 2); 410 queue_delayed_work(cache->wq, &ent->dwork, 411 msecs_to_jiffies(3)); 412 } else if (err) { 413 mlx5_ib_warn(dev, "command failed order %d, err %d\n", 414 i + 2, err); 415 queue_delayed_work(cache->wq, &ent->dwork, 416 msecs_to_jiffies(1000)); 417 } else { 418 queue_work(cache->wq, &ent->work); 419 } 420 } 421 } else if (ent->cur > 2 * ent->limit) { 422 /* 423 * The remove_keys() logic is performed as garbage collection 424 * task. Such task is intended to be run when no other active 425 * processes are running. 426 * 427 * The need_resched() will return TRUE if there are user tasks 428 * to be activated in near future. 429 * 430 * In such case, we don't execute remove_keys() and postpone 431 * the garbage collection work to try to run in next cycle, 432 * in order to free CPU resources to other tasks. 433 */ 434 if (!need_resched() && !someone_adding(cache) && 435 time_after(jiffies, cache->last_add + 300 * HZ)) { 436 remove_keys(dev, i, 1); 437 if (ent->cur > ent->limit) 438 queue_work(cache->wq, &ent->work); 439 } else { 440 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); 441 } 442 } 443 } 444 445 static void delayed_cache_work_func(struct work_struct *work) 446 { 447 struct mlx5_cache_ent *ent; 448 449 ent = container_of(work, struct mlx5_cache_ent, dwork.work); 450 __cache_work_func(ent); 451 } 452 453 static void cache_work_func(struct work_struct *work) 454 { 455 struct mlx5_cache_ent *ent; 456 457 ent = container_of(work, struct mlx5_cache_ent, work); 458 __cache_work_func(ent); 459 } 460 461 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) 462 { 463 struct mlx5_mr_cache *cache = &dev->cache; 464 struct mlx5_cache_ent *ent; 465 struct mlx5_ib_mr *mr; 466 int err; 467 468 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { 469 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); 470 return NULL; 471 } 472 473 ent = &cache->ent[entry]; 474 while (1) { 475 spin_lock_irq(&ent->lock); 476 if (list_empty(&ent->head)) { 477 spin_unlock_irq(&ent->lock); 478 479 err = add_keys(dev, entry, 1); 480 if (err && err != -EAGAIN) 481 return ERR_PTR(err); 482 483 wait_for_completion(&ent->compl); 484 } else { 485 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, 486 list); 487 list_del(&mr->list); 488 ent->cur--; 489 spin_unlock_irq(&ent->lock); 490 if (ent->cur < ent->limit) 491 queue_work(cache->wq, &ent->work); 492 return mr; 493 } 494 } 495 } 496 497 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) 498 { 499 struct mlx5_mr_cache *cache = &dev->cache; 500 struct mlx5_ib_mr *mr = NULL; 501 struct mlx5_cache_ent *ent; 502 int last_umr_cache_entry; 503 int c; 504 int i; 505 506 c = order2idx(dev, order); 507 last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev)); 508 if (c < 0 || c > last_umr_cache_entry) { 509 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); 510 return NULL; 511 } 512 513 for (i = c; i <= last_umr_cache_entry; i++) { 514 ent = &cache->ent[i]; 515 516 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); 517 518 spin_lock_irq(&ent->lock); 519 if (!list_empty(&ent->head)) { 520 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, 521 list); 522 list_del(&mr->list); 523 ent->cur--; 524 spin_unlock_irq(&ent->lock); 525 if (ent->cur < ent->limit) 526 queue_work(cache->wq, &ent->work); 527 break; 528 } 529 spin_unlock_irq(&ent->lock); 530 531 queue_work(cache->wq, &ent->work); 532 } 533 534 if (!mr) 535 cache->ent[c].miss++; 536 537 return mr; 538 } 539 540 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 541 { 542 struct mlx5_mr_cache *cache = &dev->cache; 543 struct mlx5_cache_ent *ent; 544 int shrink = 0; 545 int c; 546 547 if (!mr->allocated_from_cache) 548 return; 549 550 c = order2idx(dev, mr->order); 551 if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { 552 mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); 553 return; 554 } 555 556 if (unreg_umr(dev, mr)) 557 return; 558 559 ent = &cache->ent[c]; 560 spin_lock_irq(&ent->lock); 561 list_add_tail(&mr->list, &ent->head); 562 ent->cur++; 563 if (ent->cur > 2 * ent->limit) 564 shrink = 1; 565 spin_unlock_irq(&ent->lock); 566 567 if (shrink) 568 queue_work(cache->wq, &ent->work); 569 } 570 571 static void clean_keys(struct mlx5_ib_dev *dev, int c) 572 { 573 struct mlx5_mr_cache *cache = &dev->cache; 574 struct mlx5_cache_ent *ent = &cache->ent[c]; 575 struct mlx5_ib_mr *tmp_mr; 576 struct mlx5_ib_mr *mr; 577 LIST_HEAD(del_list); 578 579 cancel_delayed_work(&ent->dwork); 580 while (1) { 581 spin_lock_irq(&ent->lock); 582 if (list_empty(&ent->head)) { 583 spin_unlock_irq(&ent->lock); 584 break; 585 } 586 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); 587 list_move(&mr->list, &del_list); 588 ent->cur--; 589 ent->size--; 590 spin_unlock_irq(&ent->lock); 591 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); 592 } 593 594 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 595 synchronize_srcu(&dev->mr_srcu); 596 #endif 597 598 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) { 599 list_del(&mr->list); 600 kfree(mr); 601 } 602 } 603 604 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) 605 { 606 if (!mlx5_debugfs_root || dev->rep) 607 return; 608 609 debugfs_remove_recursive(dev->cache.root); 610 dev->cache.root = NULL; 611 } 612 613 static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) 614 { 615 struct mlx5_mr_cache *cache = &dev->cache; 616 struct mlx5_cache_ent *ent; 617 int i; 618 619 if (!mlx5_debugfs_root || dev->rep) 620 return 0; 621 622 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); 623 if (!cache->root) 624 return -ENOMEM; 625 626 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 627 ent = &cache->ent[i]; 628 sprintf(ent->name, "%d", ent->order); 629 ent->dir = debugfs_create_dir(ent->name, cache->root); 630 if (!ent->dir) 631 goto err; 632 633 ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, 634 &size_fops); 635 if (!ent->fsize) 636 goto err; 637 638 ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, 639 &limit_fops); 640 if (!ent->flimit) 641 goto err; 642 643 ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, 644 &ent->cur); 645 if (!ent->fcur) 646 goto err; 647 648 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, 649 &ent->miss); 650 if (!ent->fmiss) 651 goto err; 652 } 653 654 return 0; 655 err: 656 mlx5_mr_cache_debugfs_cleanup(dev); 657 658 return -ENOMEM; 659 } 660 661 static void delay_time_func(struct timer_list *t) 662 { 663 struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer); 664 665 dev->fill_delay = 0; 666 } 667 668 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) 669 { 670 struct mlx5_mr_cache *cache = &dev->cache; 671 struct mlx5_cache_ent *ent; 672 int err; 673 int i; 674 675 mutex_init(&dev->slow_path_mutex); 676 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); 677 if (!cache->wq) { 678 mlx5_ib_warn(dev, "failed to create work queue\n"); 679 return -ENOMEM; 680 } 681 682 timer_setup(&dev->delay_timer, delay_time_func, 0); 683 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 684 ent = &cache->ent[i]; 685 INIT_LIST_HEAD(&ent->head); 686 spin_lock_init(&ent->lock); 687 ent->order = i + 2; 688 ent->dev = dev; 689 ent->limit = 0; 690 691 init_completion(&ent->compl); 692 INIT_WORK(&ent->work, cache_work_func); 693 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); 694 695 if (i > MR_CACHE_LAST_STD_ENTRY) { 696 mlx5_odp_init_mr_cache_entry(ent); 697 continue; 698 } 699 700 if (ent->order > mr_cache_max_order(dev)) 701 continue; 702 703 ent->page = PAGE_SHIFT; 704 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / 705 MLX5_IB_UMR_OCTOWORD; 706 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 707 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && 708 !dev->rep && 709 mlx5_core_is_pf(dev->mdev)) 710 ent->limit = dev->mdev->profile->mr_cache[i].limit; 711 else 712 ent->limit = 0; 713 queue_work(cache->wq, &ent->work); 714 } 715 716 err = mlx5_mr_cache_debugfs_init(dev); 717 if (err) 718 mlx5_ib_warn(dev, "cache debugfs failure\n"); 719 720 /* 721 * We don't want to fail driver if debugfs failed to initialize, 722 * so we are not forwarding error to the user. 723 */ 724 725 return 0; 726 } 727 728 static void wait_for_async_commands(struct mlx5_ib_dev *dev) 729 { 730 struct mlx5_mr_cache *cache = &dev->cache; 731 struct mlx5_cache_ent *ent; 732 int total = 0; 733 int i; 734 int j; 735 736 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 737 ent = &cache->ent[i]; 738 for (j = 0 ; j < 1000; j++) { 739 if (!ent->pending) 740 break; 741 msleep(50); 742 } 743 } 744 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { 745 ent = &cache->ent[i]; 746 total += ent->pending; 747 } 748 749 if (total) 750 mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); 751 else 752 mlx5_ib_warn(dev, "done with all pending requests\n"); 753 } 754 755 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) 756 { 757 int i; 758 759 if (!dev->cache.wq) 760 return 0; 761 762 dev->cache.stopped = 1; 763 flush_workqueue(dev->cache.wq); 764 765 mlx5_mr_cache_debugfs_cleanup(dev); 766 767 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) 768 clean_keys(dev, i); 769 770 destroy_workqueue(dev->cache.wq); 771 wait_for_async_commands(dev); 772 del_timer_sync(&dev->delay_timer); 773 774 return 0; 775 } 776 777 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) 778 { 779 struct mlx5_ib_dev *dev = to_mdev(pd->device); 780 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 781 struct mlx5_core_dev *mdev = dev->mdev; 782 struct mlx5_ib_mr *mr; 783 void *mkc; 784 u32 *in; 785 int err; 786 787 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 788 if (!mr) 789 return ERR_PTR(-ENOMEM); 790 791 in = kzalloc(inlen, GFP_KERNEL); 792 if (!in) { 793 err = -ENOMEM; 794 goto err_free; 795 } 796 797 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 798 799 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 800 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); 801 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); 802 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); 803 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); 804 MLX5_SET(mkc, mkc, lr, 1); 805 806 MLX5_SET(mkc, mkc, length64, 1); 807 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 808 MLX5_SET(mkc, mkc, qpn, 0xffffff); 809 MLX5_SET64(mkc, mkc, start_addr, 0); 810 811 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); 812 if (err) 813 goto err_in; 814 815 kfree(in); 816 mr->mmkey.type = MLX5_MKEY_MR; 817 mr->ibmr.lkey = mr->mmkey.key; 818 mr->ibmr.rkey = mr->mmkey.key; 819 mr->umem = NULL; 820 821 return &mr->ibmr; 822 823 err_in: 824 kfree(in); 825 826 err_free: 827 kfree(mr); 828 829 return ERR_PTR(err); 830 } 831 832 static int get_octo_len(u64 addr, u64 len, int page_shift) 833 { 834 u64 page_size = 1ULL << page_shift; 835 u64 offset; 836 int npages; 837 838 offset = addr & (page_size - 1); 839 npages = ALIGN(len + offset, page_size) >> page_shift; 840 return (npages + 1) / 2; 841 } 842 843 static int mr_cache_max_order(struct mlx5_ib_dev *dev) 844 { 845 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) 846 return MR_CACHE_LAST_STD_ENTRY + 2; 847 return MLX5_MAX_UMR_SHIFT; 848 } 849 850 static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, 851 int access_flags, struct ib_umem **umem, 852 int *npages, int *page_shift, int *ncont, 853 int *order) 854 { 855 struct mlx5_ib_dev *dev = to_mdev(pd->device); 856 struct ib_umem *u; 857 int err; 858 859 *umem = NULL; 860 861 u = ib_umem_get(pd->uobject->context, start, length, access_flags, 0); 862 err = PTR_ERR_OR_ZERO(u); 863 if (err) { 864 mlx5_ib_dbg(dev, "umem get failed (%d)\n", err); 865 return err; 866 } 867 868 mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, 869 page_shift, ncont, order); 870 if (!*npages) { 871 mlx5_ib_warn(dev, "avoid zero region\n"); 872 ib_umem_release(u); 873 return -EINVAL; 874 } 875 876 *umem = u; 877 878 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", 879 *npages, *ncont, *order, *page_shift); 880 881 return 0; 882 } 883 884 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) 885 { 886 struct mlx5_ib_umr_context *context = 887 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); 888 889 context->status = wc->status; 890 complete(&context->done); 891 } 892 893 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) 894 { 895 context->cqe.done = mlx5_ib_umr_done; 896 context->status = -1; 897 init_completion(&context->done); 898 } 899 900 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, 901 struct mlx5_umr_wr *umrwr) 902 { 903 struct umr_common *umrc = &dev->umrc; 904 const struct ib_send_wr *bad; 905 int err; 906 struct mlx5_ib_umr_context umr_context; 907 908 mlx5_ib_init_umr_context(&umr_context); 909 umrwr->wr.wr_cqe = &umr_context.cqe; 910 911 down(&umrc->sem); 912 err = ib_post_send(umrc->qp, &umrwr->wr, &bad); 913 if (err) { 914 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); 915 } else { 916 wait_for_completion(&umr_context.done); 917 if (umr_context.status != IB_WC_SUCCESS) { 918 mlx5_ib_warn(dev, "reg umr failed (%u)\n", 919 umr_context.status); 920 err = -EFAULT; 921 } 922 } 923 up(&umrc->sem); 924 return err; 925 } 926 927 static struct mlx5_ib_mr *alloc_mr_from_cache( 928 struct ib_pd *pd, struct ib_umem *umem, 929 u64 virt_addr, u64 len, int npages, 930 int page_shift, int order, int access_flags) 931 { 932 struct mlx5_ib_dev *dev = to_mdev(pd->device); 933 struct mlx5_ib_mr *mr; 934 int err = 0; 935 int i; 936 937 for (i = 0; i < 1; i++) { 938 mr = alloc_cached_mr(dev, order); 939 if (mr) 940 break; 941 942 err = add_keys(dev, order2idx(dev, order), 1); 943 if (err && err != -EAGAIN) { 944 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); 945 break; 946 } 947 } 948 949 if (!mr) 950 return ERR_PTR(-EAGAIN); 951 952 mr->ibmr.pd = pd; 953 mr->umem = umem; 954 mr->access_flags = access_flags; 955 mr->desc_size = sizeof(struct mlx5_mtt); 956 mr->mmkey.iova = virt_addr; 957 mr->mmkey.size = len; 958 mr->mmkey.pd = to_mpd(pd)->pdn; 959 960 return mr; 961 } 962 963 static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, 964 void *xlt, int page_shift, size_t size, 965 int flags) 966 { 967 struct mlx5_ib_dev *dev = mr->dev; 968 struct ib_umem *umem = mr->umem; 969 970 if (flags & MLX5_IB_UPD_XLT_INDIRECT) { 971 if (!umr_can_use_indirect_mkey(dev)) 972 return -EPERM; 973 mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); 974 return npages; 975 } 976 977 npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); 978 979 if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { 980 __mlx5_ib_populate_pas(dev, umem, page_shift, 981 idx, npages, xlt, 982 MLX5_IB_MTT_PRESENT); 983 /* Clear padding after the pages 984 * brought from the umem. 985 */ 986 memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, 987 size - npages * sizeof(struct mlx5_mtt)); 988 } 989 990 return npages; 991 } 992 993 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ 994 MLX5_UMR_MTT_ALIGNMENT) 995 #define MLX5_SPARE_UMR_CHUNK 0x10000 996 997 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 998 int page_shift, int flags) 999 { 1000 struct mlx5_ib_dev *dev = mr->dev; 1001 struct device *ddev = dev->ib_dev.dev.parent; 1002 int size; 1003 void *xlt; 1004 dma_addr_t dma; 1005 struct mlx5_umr_wr wr; 1006 struct ib_sge sg; 1007 int err = 0; 1008 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) 1009 ? sizeof(struct mlx5_klm) 1010 : sizeof(struct mlx5_mtt); 1011 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; 1012 const int page_mask = page_align - 1; 1013 size_t pages_mapped = 0; 1014 size_t pages_to_map = 0; 1015 size_t pages_iter = 0; 1016 gfp_t gfp; 1017 bool use_emergency_page = false; 1018 1019 if ((flags & MLX5_IB_UPD_XLT_INDIRECT) && 1020 !umr_can_use_indirect_mkey(dev)) 1021 return -EPERM; 1022 1023 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, 1024 * so we need to align the offset and length accordingly 1025 */ 1026 if (idx & page_mask) { 1027 npages += idx & page_mask; 1028 idx &= ~page_mask; 1029 } 1030 1031 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; 1032 gfp |= __GFP_ZERO | __GFP_NOWARN; 1033 1034 pages_to_map = ALIGN(npages, page_align); 1035 size = desc_size * pages_to_map; 1036 size = min_t(int, size, MLX5_MAX_UMR_CHUNK); 1037 1038 xlt = (void *)__get_free_pages(gfp, get_order(size)); 1039 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { 1040 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", 1041 size, get_order(size), MLX5_SPARE_UMR_CHUNK); 1042 1043 size = MLX5_SPARE_UMR_CHUNK; 1044 xlt = (void *)__get_free_pages(gfp, get_order(size)); 1045 } 1046 1047 if (!xlt) { 1048 mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); 1049 xlt = (void *)mlx5_ib_get_xlt_emergency_page(); 1050 size = PAGE_SIZE; 1051 memset(xlt, 0, size); 1052 use_emergency_page = true; 1053 } 1054 pages_iter = size / desc_size; 1055 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); 1056 if (dma_mapping_error(ddev, dma)) { 1057 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); 1058 err = -ENOMEM; 1059 goto free_xlt; 1060 } 1061 1062 sg.addr = dma; 1063 sg.lkey = dev->umrc.pd->local_dma_lkey; 1064 1065 memset(&wr, 0, sizeof(wr)); 1066 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; 1067 if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) 1068 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1069 wr.wr.sg_list = &sg; 1070 wr.wr.num_sge = 1; 1071 wr.wr.opcode = MLX5_IB_WR_UMR; 1072 1073 wr.pd = mr->ibmr.pd; 1074 wr.mkey = mr->mmkey.key; 1075 wr.length = mr->mmkey.size; 1076 wr.virt_addr = mr->mmkey.iova; 1077 wr.access_flags = mr->access_flags; 1078 wr.page_shift = page_shift; 1079 1080 for (pages_mapped = 0; 1081 pages_mapped < pages_to_map && !err; 1082 pages_mapped += pages_iter, idx += pages_iter) { 1083 npages = min_t(int, pages_iter, pages_to_map - pages_mapped); 1084 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); 1085 npages = populate_xlt(mr, idx, npages, xlt, 1086 page_shift, size, flags); 1087 1088 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); 1089 1090 sg.length = ALIGN(npages * desc_size, 1091 MLX5_UMR_MTT_ALIGNMENT); 1092 1093 if (pages_mapped + pages_iter >= pages_to_map) { 1094 if (flags & MLX5_IB_UPD_XLT_ENABLE) 1095 wr.wr.send_flags |= 1096 MLX5_IB_SEND_UMR_ENABLE_MR | 1097 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | 1098 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; 1099 if (flags & MLX5_IB_UPD_XLT_PD || 1100 flags & MLX5_IB_UPD_XLT_ACCESS) 1101 wr.wr.send_flags |= 1102 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; 1103 if (flags & MLX5_IB_UPD_XLT_ADDR) 1104 wr.wr.send_flags |= 1105 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; 1106 } 1107 1108 wr.offset = idx * desc_size; 1109 wr.xlt_size = sg.length; 1110 1111 err = mlx5_ib_post_send_wait(dev, &wr); 1112 } 1113 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); 1114 1115 free_xlt: 1116 if (use_emergency_page) 1117 mlx5_ib_put_xlt_emergency_page(); 1118 else 1119 free_pages((unsigned long)xlt, get_order(size)); 1120 1121 return err; 1122 } 1123 1124 /* 1125 * If ibmr is NULL it will be allocated by reg_create. 1126 * Else, the given ibmr will be used. 1127 */ 1128 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, 1129 u64 virt_addr, u64 length, 1130 struct ib_umem *umem, int npages, 1131 int page_shift, int access_flags, 1132 bool populate) 1133 { 1134 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1135 struct mlx5_ib_mr *mr; 1136 __be64 *pas; 1137 void *mkc; 1138 int inlen; 1139 u32 *in; 1140 int err; 1141 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); 1142 1143 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); 1144 if (!mr) 1145 return ERR_PTR(-ENOMEM); 1146 1147 mr->ibmr.pd = pd; 1148 mr->access_flags = access_flags; 1149 1150 inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1151 if (populate) 1152 inlen += sizeof(*pas) * roundup(npages, 2); 1153 in = kvzalloc(inlen, GFP_KERNEL); 1154 if (!in) { 1155 err = -ENOMEM; 1156 goto err_1; 1157 } 1158 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 1159 if (populate && !(access_flags & IB_ACCESS_ON_DEMAND)) 1160 mlx5_ib_populate_pas(dev, umem, page_shift, pas, 1161 pg_cap ? MLX5_IB_MTT_PRESENT : 0); 1162 1163 /* The pg_access bit allows setting the access flags 1164 * in the page list submitted with the command. */ 1165 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); 1166 1167 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1168 MLX5_SET(mkc, mkc, free, !populate); 1169 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 1170 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 1171 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 1172 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); 1173 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); 1174 MLX5_SET(mkc, mkc, lr, 1); 1175 MLX5_SET(mkc, mkc, umr_en, 1); 1176 1177 MLX5_SET64(mkc, mkc, start_addr, virt_addr); 1178 MLX5_SET64(mkc, mkc, len, length); 1179 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1180 MLX5_SET(mkc, mkc, bsf_octword_size, 0); 1181 MLX5_SET(mkc, mkc, translations_octword_size, 1182 get_octo_len(virt_addr, length, page_shift)); 1183 MLX5_SET(mkc, mkc, log_page_size, page_shift); 1184 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1185 if (populate) { 1186 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 1187 get_octo_len(virt_addr, length, page_shift)); 1188 } 1189 1190 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); 1191 if (err) { 1192 mlx5_ib_warn(dev, "create mkey failed\n"); 1193 goto err_2; 1194 } 1195 mr->mmkey.type = MLX5_MKEY_MR; 1196 mr->desc_size = sizeof(struct mlx5_mtt); 1197 mr->dev = dev; 1198 kvfree(in); 1199 1200 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); 1201 1202 return mr; 1203 1204 err_2: 1205 kvfree(in); 1206 1207 err_1: 1208 if (!ibmr) 1209 kfree(mr); 1210 1211 return ERR_PTR(err); 1212 } 1213 1214 static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, 1215 int npages, u64 length, int access_flags) 1216 { 1217 mr->npages = npages; 1218 atomic_add(npages, &dev->mdev->priv.reg_pages); 1219 mr->ibmr.lkey = mr->mmkey.key; 1220 mr->ibmr.rkey = mr->mmkey.key; 1221 mr->ibmr.length = length; 1222 mr->access_flags = access_flags; 1223 } 1224 1225 static struct ib_mr *mlx5_ib_get_memic_mr(struct ib_pd *pd, u64 memic_addr, 1226 u64 length, int acc) 1227 { 1228 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1229 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1230 struct mlx5_core_dev *mdev = dev->mdev; 1231 struct mlx5_ib_mr *mr; 1232 void *mkc; 1233 u32 *in; 1234 int err; 1235 1236 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1237 if (!mr) 1238 return ERR_PTR(-ENOMEM); 1239 1240 in = kzalloc(inlen, GFP_KERNEL); 1241 if (!in) { 1242 err = -ENOMEM; 1243 goto err_free; 1244 } 1245 1246 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1247 1248 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MEMIC & 0x3); 1249 MLX5_SET(mkc, mkc, access_mode_4_2, 1250 (MLX5_MKC_ACCESS_MODE_MEMIC >> 2) & 0x7); 1251 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); 1252 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); 1253 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); 1254 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); 1255 MLX5_SET(mkc, mkc, lr, 1); 1256 1257 MLX5_SET64(mkc, mkc, len, length); 1258 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1259 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1260 MLX5_SET64(mkc, mkc, start_addr, 1261 memic_addr - pci_resource_start(dev->mdev->pdev, 0)); 1262 1263 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); 1264 if (err) 1265 goto err_in; 1266 1267 kfree(in); 1268 1269 mr->umem = NULL; 1270 set_mr_fields(dev, mr, 0, length, acc); 1271 1272 return &mr->ibmr; 1273 1274 err_in: 1275 kfree(in); 1276 1277 err_free: 1278 kfree(mr); 1279 1280 return ERR_PTR(err); 1281 } 1282 1283 int mlx5_ib_advise_mr(struct ib_pd *pd, 1284 enum ib_uverbs_advise_mr_advice advice, 1285 u32 flags, 1286 struct ib_sge *sg_list, 1287 u32 num_sge, 1288 struct uverbs_attr_bundle *attrs) 1289 { 1290 if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH && 1291 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE) 1292 return -EOPNOTSUPP; 1293 1294 return mlx5_ib_advise_mr_prefetch(pd, advice, flags, 1295 sg_list, num_sge); 1296 } 1297 1298 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1299 struct ib_dm_mr_attr *attr, 1300 struct uverbs_attr_bundle *attrs) 1301 { 1302 struct mlx5_ib_dm *mdm = to_mdm(dm); 1303 u64 memic_addr; 1304 1305 if (attr->access_flags & ~MLX5_IB_DM_ALLOWED_ACCESS) 1306 return ERR_PTR(-EINVAL); 1307 1308 memic_addr = mdm->dev_addr + attr->offset; 1309 1310 return mlx5_ib_get_memic_mr(pd, memic_addr, attr->length, 1311 attr->access_flags); 1312 } 1313 1314 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1315 u64 virt_addr, int access_flags, 1316 struct ib_udata *udata) 1317 { 1318 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1319 struct mlx5_ib_mr *mr = NULL; 1320 bool populate_mtts = false; 1321 struct ib_umem *umem; 1322 int page_shift; 1323 int npages; 1324 int ncont; 1325 int order; 1326 int err; 1327 1328 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM)) 1329 return ERR_PTR(-EOPNOTSUPP); 1330 1331 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", 1332 start, virt_addr, length, access_flags); 1333 1334 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1335 if (!start && length == U64_MAX) { 1336 if (!(access_flags & IB_ACCESS_ON_DEMAND) || 1337 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) 1338 return ERR_PTR(-EINVAL); 1339 1340 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); 1341 if (IS_ERR(mr)) 1342 return ERR_CAST(mr); 1343 return &mr->ibmr; 1344 } 1345 #endif 1346 1347 err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, 1348 &page_shift, &ncont, &order); 1349 1350 if (err < 0) 1351 return ERR_PTR(err); 1352 1353 if (use_umr(dev, order)) { 1354 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, 1355 page_shift, order, access_flags); 1356 if (PTR_ERR(mr) == -EAGAIN) { 1357 mlx5_ib_dbg(dev, "cache empty for order %d\n", order); 1358 mr = NULL; 1359 } 1360 populate_mtts = false; 1361 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { 1362 if (access_flags & IB_ACCESS_ON_DEMAND) { 1363 err = -EINVAL; 1364 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n"); 1365 goto error; 1366 } 1367 populate_mtts = true; 1368 } 1369 1370 if (!mr) { 1371 if (!umr_can_modify_entity_size(dev)) 1372 populate_mtts = true; 1373 mutex_lock(&dev->slow_path_mutex); 1374 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, 1375 page_shift, access_flags, populate_mtts); 1376 mutex_unlock(&dev->slow_path_mutex); 1377 } 1378 1379 if (IS_ERR(mr)) { 1380 err = PTR_ERR(mr); 1381 goto error; 1382 } 1383 1384 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); 1385 1386 mr->umem = umem; 1387 set_mr_fields(dev, mr, npages, length, access_flags); 1388 1389 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1390 update_odp_mr(mr); 1391 #endif 1392 1393 if (!populate_mtts) { 1394 int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE; 1395 1396 if (access_flags & IB_ACCESS_ON_DEMAND) 1397 update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP; 1398 1399 err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift, 1400 update_xlt_flags); 1401 1402 if (err) { 1403 dereg_mr(dev, mr); 1404 return ERR_PTR(err); 1405 } 1406 } 1407 1408 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1409 mr->live = 1; 1410 #endif 1411 return &mr->ibmr; 1412 error: 1413 ib_umem_release(umem); 1414 return ERR_PTR(err); 1415 } 1416 1417 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 1418 { 1419 struct mlx5_core_dev *mdev = dev->mdev; 1420 struct mlx5_umr_wr umrwr = {}; 1421 1422 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 1423 return 0; 1424 1425 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | 1426 MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1427 umrwr.wr.opcode = MLX5_IB_WR_UMR; 1428 umrwr.mkey = mr->mmkey.key; 1429 1430 return mlx5_ib_post_send_wait(dev, &umrwr); 1431 } 1432 1433 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1434 int access_flags, int flags) 1435 { 1436 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1437 struct mlx5_umr_wr umrwr = {}; 1438 int err; 1439 1440 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; 1441 1442 umrwr.wr.opcode = MLX5_IB_WR_UMR; 1443 umrwr.mkey = mr->mmkey.key; 1444 1445 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { 1446 umrwr.pd = pd; 1447 umrwr.access_flags = access_flags; 1448 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; 1449 } 1450 1451 err = mlx5_ib_post_send_wait(dev, &umrwr); 1452 1453 return err; 1454 } 1455 1456 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1457 u64 length, u64 virt_addr, int new_access_flags, 1458 struct ib_pd *new_pd, struct ib_udata *udata) 1459 { 1460 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); 1461 struct mlx5_ib_mr *mr = to_mmr(ib_mr); 1462 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; 1463 int access_flags = flags & IB_MR_REREG_ACCESS ? 1464 new_access_flags : 1465 mr->access_flags; 1466 int page_shift = 0; 1467 int upd_flags = 0; 1468 int npages = 0; 1469 int ncont = 0; 1470 int order = 0; 1471 u64 addr, len; 1472 int err; 1473 1474 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", 1475 start, virt_addr, length, access_flags); 1476 1477 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); 1478 1479 if (!mr->umem) 1480 return -EINVAL; 1481 1482 if (flags & IB_MR_REREG_TRANS) { 1483 addr = virt_addr; 1484 len = length; 1485 } else { 1486 addr = mr->umem->address; 1487 len = mr->umem->length; 1488 } 1489 1490 if (flags != IB_MR_REREG_PD) { 1491 /* 1492 * Replace umem. This needs to be done whether or not UMR is 1493 * used. 1494 */ 1495 flags |= IB_MR_REREG_TRANS; 1496 ib_umem_release(mr->umem); 1497 mr->umem = NULL; 1498 err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, 1499 &npages, &page_shift, &ncont, &order); 1500 if (err) 1501 goto err; 1502 } 1503 1504 if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { 1505 /* 1506 * UMR can't be used - MKey needs to be replaced. 1507 */ 1508 if (mr->allocated_from_cache) 1509 err = unreg_umr(dev, mr); 1510 else 1511 err = destroy_mkey(dev, mr); 1512 if (err) 1513 goto err; 1514 1515 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, 1516 page_shift, access_flags, true); 1517 1518 if (IS_ERR(mr)) { 1519 err = PTR_ERR(mr); 1520 mr = to_mmr(ib_mr); 1521 goto err; 1522 } 1523 1524 mr->allocated_from_cache = 0; 1525 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1526 mr->live = 1; 1527 #endif 1528 } else { 1529 /* 1530 * Send a UMR WQE 1531 */ 1532 mr->ibmr.pd = pd; 1533 mr->access_flags = access_flags; 1534 mr->mmkey.iova = addr; 1535 mr->mmkey.size = len; 1536 mr->mmkey.pd = to_mpd(pd)->pdn; 1537 1538 if (flags & IB_MR_REREG_TRANS) { 1539 upd_flags = MLX5_IB_UPD_XLT_ADDR; 1540 if (flags & IB_MR_REREG_PD) 1541 upd_flags |= MLX5_IB_UPD_XLT_PD; 1542 if (flags & IB_MR_REREG_ACCESS) 1543 upd_flags |= MLX5_IB_UPD_XLT_ACCESS; 1544 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, 1545 upd_flags); 1546 } else { 1547 err = rereg_umr(pd, mr, access_flags, flags); 1548 } 1549 1550 if (err) 1551 goto err; 1552 } 1553 1554 set_mr_fields(dev, mr, npages, len, access_flags); 1555 1556 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1557 update_odp_mr(mr); 1558 #endif 1559 return 0; 1560 1561 err: 1562 if (mr->umem) { 1563 ib_umem_release(mr->umem); 1564 mr->umem = NULL; 1565 } 1566 clean_mr(dev, mr); 1567 return err; 1568 } 1569 1570 static int 1571 mlx5_alloc_priv_descs(struct ib_device *device, 1572 struct mlx5_ib_mr *mr, 1573 int ndescs, 1574 int desc_size) 1575 { 1576 int size = ndescs * desc_size; 1577 int add_size; 1578 int ret; 1579 1580 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); 1581 1582 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); 1583 if (!mr->descs_alloc) 1584 return -ENOMEM; 1585 1586 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); 1587 1588 mr->desc_map = dma_map_single(device->dev.parent, mr->descs, 1589 size, DMA_TO_DEVICE); 1590 if (dma_mapping_error(device->dev.parent, mr->desc_map)) { 1591 ret = -ENOMEM; 1592 goto err; 1593 } 1594 1595 return 0; 1596 err: 1597 kfree(mr->descs_alloc); 1598 1599 return ret; 1600 } 1601 1602 static void 1603 mlx5_free_priv_descs(struct mlx5_ib_mr *mr) 1604 { 1605 if (mr->descs) { 1606 struct ib_device *device = mr->ibmr.device; 1607 int size = mr->max_descs * mr->desc_size; 1608 1609 dma_unmap_single(device->dev.parent, mr->desc_map, 1610 size, DMA_TO_DEVICE); 1611 kfree(mr->descs_alloc); 1612 mr->descs = NULL; 1613 } 1614 } 1615 1616 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 1617 { 1618 int allocated_from_cache = mr->allocated_from_cache; 1619 1620 if (mr->sig) { 1621 if (mlx5_core_destroy_psv(dev->mdev, 1622 mr->sig->psv_memory.psv_idx)) 1623 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1624 mr->sig->psv_memory.psv_idx); 1625 if (mlx5_core_destroy_psv(dev->mdev, 1626 mr->sig->psv_wire.psv_idx)) 1627 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1628 mr->sig->psv_wire.psv_idx); 1629 kfree(mr->sig); 1630 mr->sig = NULL; 1631 } 1632 1633 mlx5_free_priv_descs(mr); 1634 1635 if (!allocated_from_cache) 1636 destroy_mkey(dev, mr); 1637 } 1638 1639 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 1640 { 1641 int npages = mr->npages; 1642 struct ib_umem *umem = mr->umem; 1643 1644 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1645 if (umem && umem->is_odp) { 1646 struct ib_umem_odp *umem_odp = to_ib_umem_odp(umem); 1647 1648 /* Prevent new page faults from succeeding */ 1649 mr->live = 0; 1650 /* Wait for all running page-fault handlers to finish. */ 1651 synchronize_srcu(&dev->mr_srcu); 1652 /* Destroy all page mappings */ 1653 if (umem_odp->page_list) 1654 mlx5_ib_invalidate_range(umem_odp, ib_umem_start(umem), 1655 ib_umem_end(umem)); 1656 else 1657 mlx5_ib_free_implicit_mr(mr); 1658 /* 1659 * We kill the umem before the MR for ODP, 1660 * so that there will not be any invalidations in 1661 * flight, looking at the *mr struct. 1662 */ 1663 ib_umem_release(umem); 1664 atomic_sub(npages, &dev->mdev->priv.reg_pages); 1665 1666 /* Avoid double-freeing the umem. */ 1667 umem = NULL; 1668 } 1669 #endif 1670 clean_mr(dev, mr); 1671 1672 /* 1673 * We should unregister the DMA address from the HCA before 1674 * remove the DMA mapping. 1675 */ 1676 mlx5_mr_cache_free(dev, mr); 1677 if (umem) { 1678 ib_umem_release(umem); 1679 atomic_sub(npages, &dev->mdev->priv.reg_pages); 1680 } 1681 if (!mr->allocated_from_cache) 1682 kfree(mr); 1683 } 1684 1685 int mlx5_ib_dereg_mr(struct ib_mr *ibmr) 1686 { 1687 dereg_mr(to_mdev(ibmr->device), to_mmr(ibmr)); 1688 return 0; 1689 } 1690 1691 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1692 enum ib_mr_type mr_type, 1693 u32 max_num_sg) 1694 { 1695 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1696 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1697 int ndescs = ALIGN(max_num_sg, 4); 1698 struct mlx5_ib_mr *mr; 1699 void *mkc; 1700 u32 *in; 1701 int err; 1702 1703 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1704 if (!mr) 1705 return ERR_PTR(-ENOMEM); 1706 1707 in = kzalloc(inlen, GFP_KERNEL); 1708 if (!in) { 1709 err = -ENOMEM; 1710 goto err_free; 1711 } 1712 1713 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1714 MLX5_SET(mkc, mkc, free, 1); 1715 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1716 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1717 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1718 1719 if (mr_type == IB_MR_TYPE_MEM_REG) { 1720 mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; 1721 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); 1722 err = mlx5_alloc_priv_descs(pd->device, mr, 1723 ndescs, sizeof(struct mlx5_mtt)); 1724 if (err) 1725 goto err_free_in; 1726 1727 mr->desc_size = sizeof(struct mlx5_mtt); 1728 mr->max_descs = ndescs; 1729 } else if (mr_type == IB_MR_TYPE_SG_GAPS) { 1730 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; 1731 1732 err = mlx5_alloc_priv_descs(pd->device, mr, 1733 ndescs, sizeof(struct mlx5_klm)); 1734 if (err) 1735 goto err_free_in; 1736 mr->desc_size = sizeof(struct mlx5_klm); 1737 mr->max_descs = ndescs; 1738 } else if (mr_type == IB_MR_TYPE_SIGNATURE) { 1739 u32 psv_index[2]; 1740 1741 MLX5_SET(mkc, mkc, bsf_en, 1); 1742 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); 1743 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); 1744 if (!mr->sig) { 1745 err = -ENOMEM; 1746 goto err_free_in; 1747 } 1748 1749 /* create mem & wire PSVs */ 1750 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 1751 2, psv_index); 1752 if (err) 1753 goto err_free_sig; 1754 1755 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; 1756 mr->sig->psv_memory.psv_idx = psv_index[0]; 1757 mr->sig->psv_wire.psv_idx = psv_index[1]; 1758 1759 mr->sig->sig_status_checked = true; 1760 mr->sig->sig_err_exists = false; 1761 /* Next UMR, Arm SIGERR */ 1762 ++mr->sig->sigerr_count; 1763 } else { 1764 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); 1765 err = -EINVAL; 1766 goto err_free_in; 1767 } 1768 1769 MLX5_SET(mkc, mkc, access_mode_1_0, mr->access_mode & 0x3); 1770 MLX5_SET(mkc, mkc, access_mode_4_2, (mr->access_mode >> 2) & 0x7); 1771 MLX5_SET(mkc, mkc, umr_en, 1); 1772 1773 mr->ibmr.device = pd->device; 1774 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); 1775 if (err) 1776 goto err_destroy_psv; 1777 1778 mr->mmkey.type = MLX5_MKEY_MR; 1779 mr->ibmr.lkey = mr->mmkey.key; 1780 mr->ibmr.rkey = mr->mmkey.key; 1781 mr->umem = NULL; 1782 kfree(in); 1783 1784 return &mr->ibmr; 1785 1786 err_destroy_psv: 1787 if (mr->sig) { 1788 if (mlx5_core_destroy_psv(dev->mdev, 1789 mr->sig->psv_memory.psv_idx)) 1790 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1791 mr->sig->psv_memory.psv_idx); 1792 if (mlx5_core_destroy_psv(dev->mdev, 1793 mr->sig->psv_wire.psv_idx)) 1794 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1795 mr->sig->psv_wire.psv_idx); 1796 } 1797 mlx5_free_priv_descs(mr); 1798 err_free_sig: 1799 kfree(mr->sig); 1800 err_free_in: 1801 kfree(in); 1802 err_free: 1803 kfree(mr); 1804 return ERR_PTR(err); 1805 } 1806 1807 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1808 struct ib_udata *udata) 1809 { 1810 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1811 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1812 struct mlx5_ib_mw *mw = NULL; 1813 u32 *in = NULL; 1814 void *mkc; 1815 int ndescs; 1816 int err; 1817 struct mlx5_ib_alloc_mw req = {}; 1818 struct { 1819 __u32 comp_mask; 1820 __u32 response_length; 1821 } resp = {}; 1822 1823 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1824 if (err) 1825 return ERR_PTR(err); 1826 1827 if (req.comp_mask || req.reserved1 || req.reserved2) 1828 return ERR_PTR(-EOPNOTSUPP); 1829 1830 if (udata->inlen > sizeof(req) && 1831 !ib_is_udata_cleared(udata, sizeof(req), 1832 udata->inlen - sizeof(req))) 1833 return ERR_PTR(-EOPNOTSUPP); 1834 1835 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); 1836 1837 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 1838 in = kzalloc(inlen, GFP_KERNEL); 1839 if (!mw || !in) { 1840 err = -ENOMEM; 1841 goto free; 1842 } 1843 1844 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1845 1846 MLX5_SET(mkc, mkc, free, 1); 1847 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1848 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 1849 MLX5_SET(mkc, mkc, umr_en, 1); 1850 MLX5_SET(mkc, mkc, lr, 1); 1851 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); 1852 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); 1853 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1854 1855 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); 1856 if (err) 1857 goto free; 1858 1859 mw->mmkey.type = MLX5_MKEY_MW; 1860 mw->ibmw.rkey = mw->mmkey.key; 1861 mw->ndescs = ndescs; 1862 1863 resp.response_length = min(offsetof(typeof(resp), response_length) + 1864 sizeof(resp.response_length), udata->outlen); 1865 if (resp.response_length) { 1866 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1867 if (err) { 1868 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); 1869 goto free; 1870 } 1871 } 1872 1873 kfree(in); 1874 return &mw->ibmw; 1875 1876 free: 1877 kfree(mw); 1878 kfree(in); 1879 return ERR_PTR(err); 1880 } 1881 1882 int mlx5_ib_dealloc_mw(struct ib_mw *mw) 1883 { 1884 struct mlx5_ib_mw *mmw = to_mmw(mw); 1885 int err; 1886 1887 err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, 1888 &mmw->mmkey); 1889 if (!err) 1890 kfree(mmw); 1891 return err; 1892 } 1893 1894 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1895 struct ib_mr_status *mr_status) 1896 { 1897 struct mlx5_ib_mr *mmr = to_mmr(ibmr); 1898 int ret = 0; 1899 1900 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { 1901 pr_err("Invalid status check mask\n"); 1902 ret = -EINVAL; 1903 goto done; 1904 } 1905 1906 mr_status->fail_status = 0; 1907 if (check_mask & IB_MR_CHECK_SIG_STATUS) { 1908 if (!mmr->sig) { 1909 ret = -EINVAL; 1910 pr_err("signature status check requested on a non-signature enabled MR\n"); 1911 goto done; 1912 } 1913 1914 mmr->sig->sig_status_checked = true; 1915 if (!mmr->sig->sig_err_exists) 1916 goto done; 1917 1918 if (ibmr->lkey == mmr->sig->err_item.key) 1919 memcpy(&mr_status->sig_err, &mmr->sig->err_item, 1920 sizeof(mr_status->sig_err)); 1921 else { 1922 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; 1923 mr_status->sig_err.sig_err_offset = 0; 1924 mr_status->sig_err.key = mmr->sig->err_item.key; 1925 } 1926 1927 mmr->sig->sig_err_exists = false; 1928 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; 1929 } 1930 1931 done: 1932 return ret; 1933 } 1934 1935 static int 1936 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, 1937 struct scatterlist *sgl, 1938 unsigned short sg_nents, 1939 unsigned int *sg_offset_p) 1940 { 1941 struct scatterlist *sg = sgl; 1942 struct mlx5_klm *klms = mr->descs; 1943 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; 1944 u32 lkey = mr->ibmr.pd->local_dma_lkey; 1945 int i; 1946 1947 mr->ibmr.iova = sg_dma_address(sg) + sg_offset; 1948 mr->ibmr.length = 0; 1949 1950 for_each_sg(sgl, sg, sg_nents, i) { 1951 if (unlikely(i >= mr->max_descs)) 1952 break; 1953 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); 1954 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); 1955 klms[i].key = cpu_to_be32(lkey); 1956 mr->ibmr.length += sg_dma_len(sg) - sg_offset; 1957 1958 sg_offset = 0; 1959 } 1960 mr->ndescs = i; 1961 1962 if (sg_offset_p) 1963 *sg_offset_p = sg_offset; 1964 1965 return i; 1966 } 1967 1968 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) 1969 { 1970 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1971 __be64 *descs; 1972 1973 if (unlikely(mr->ndescs == mr->max_descs)) 1974 return -ENOMEM; 1975 1976 descs = mr->descs; 1977 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); 1978 1979 return 0; 1980 } 1981 1982 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1983 unsigned int *sg_offset) 1984 { 1985 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1986 int n; 1987 1988 mr->ndescs = 0; 1989 1990 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, 1991 mr->desc_size * mr->max_descs, 1992 DMA_TO_DEVICE); 1993 1994 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 1995 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); 1996 else 1997 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, 1998 mlx5_set_page); 1999 2000 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, 2001 mr->desc_size * mr->max_descs, 2002 DMA_TO_DEVICE); 2003 2004 return n; 2005 } 2006