1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2020, Intel Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/bitfield.h> 35 #include <linux/kref.h> 36 #include <linux/random.h> 37 #include <linux/debugfs.h> 38 #include <linux/export.h> 39 #include <linux/delay.h> 40 #include <linux/dma-buf.h> 41 #include <linux/dma-resv.h> 42 #include <rdma/frmr_pools.h> 43 #include <rdma/ib_umem_odp.h> 44 #include "dm.h" 45 #include "mlx5_ib.h" 46 #include "umr.h" 47 #include "data_direct.h" 48 #include "dmah.h" 49 50 static int mkey_max_umr_order(struct mlx5_ib_dev *dev) 51 { 52 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) 53 return MLX5_MAX_UMR_EXTENDED_SHIFT; 54 return MLX5_MAX_UMR_SHIFT; 55 } 56 57 static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, struct ib_umem *umem, 58 u64 iova, int access_flags, 59 unsigned long page_size, bool populate, 60 int access_mode, u16 st_index, u8 ph); 61 static int __mlx5_ib_dereg_mr(struct ib_mr *ibmr); 62 63 static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr, 64 struct ib_pd *pd) 65 { 66 struct mlx5_ib_dev *dev = to_mdev(pd->device); 67 68 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); 69 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); 70 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); 71 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); 72 MLX5_SET(mkc, mkc, lr, 1); 73 74 if (acc & IB_ACCESS_RELAXED_ORDERING) { 75 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) 76 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 77 78 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || 79 (MLX5_CAP_GEN(dev->mdev, 80 relaxed_ordering_read_pci_enabled) && 81 pcie_relaxed_ordering_enabled(dev->mdev->pdev))) 82 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 83 } 84 85 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); 86 MLX5_SET(mkc, mkc, qpn, 0xffffff); 87 MLX5_SET64(mkc, mkc, start_addr, start_addr); 88 } 89 90 static void assign_mkey_variant(struct mlx5_ib_dev *dev, u32 *mkey, u32 *in) 91 { 92 u8 key = atomic_inc_return(&dev->mkey_var); 93 void *mkc; 94 95 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 96 MLX5_SET(mkc, mkc, mkey_7_0, key); 97 *mkey = key; 98 } 99 100 static int mlx5_ib_create_mkey(struct mlx5_ib_dev *dev, 101 struct mlx5_ib_mkey *mkey, u32 *in, int inlen) 102 { 103 int ret; 104 105 assign_mkey_variant(dev, &mkey->key, in); 106 ret = mlx5_core_create_mkey(dev->mdev, &mkey->key, in, inlen); 107 if (!ret) 108 init_waitqueue_head(&mkey->wait); 109 110 return ret; 111 } 112 113 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) 114 { 115 WARN_ON(xa_load(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key))); 116 117 return mlx5_core_destroy_mkey(dev->mdev, mr->mmkey.key); 118 } 119 120 static int get_mkc_octo_size(unsigned int access_mode, unsigned int ndescs) 121 { 122 int ret = 0; 123 124 switch (access_mode) { 125 case MLX5_MKC_ACCESS_MODE_MTT: 126 ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD / 127 sizeof(struct mlx5_mtt)); 128 break; 129 case MLX5_MKC_ACCESS_MODE_KSM: 130 ret = DIV_ROUND_UP(ndescs, MLX5_IB_UMR_OCTOWORD / 131 sizeof(struct mlx5_klm)); 132 break; 133 default: 134 WARN_ON(1); 135 } 136 return ret; 137 } 138 139 static int get_unchangeable_access_flags(struct mlx5_ib_dev *dev, 140 int access_flags) 141 { 142 int ret = 0; 143 144 if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) && 145 MLX5_CAP_GEN(dev->mdev, atomic) && 146 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 147 ret |= IB_ACCESS_REMOTE_ATOMIC; 148 149 if ((access_flags & IB_ACCESS_RELAXED_ORDERING) && 150 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 151 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 152 ret |= IB_ACCESS_RELAXED_ORDERING; 153 154 if ((access_flags & IB_ACCESS_RELAXED_ORDERING) && 155 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || 156 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) && 157 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 158 ret |= IB_ACCESS_RELAXED_ORDERING; 159 160 return ret; 161 } 162 163 #define MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK 1ULL 164 #define MLX5_FRMR_POOLS_KEY_VENDOR_KEY_SUPPORTED \ 165 MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK 166 167 #define MLX5_FRMR_POOLS_KERNEL_KEY_PH_MASK GENMASK_ULL(23, 16) 168 #define MLX5_FRMR_POOLS_KERNEL_KEY_ST_INDEX_MASK GENMASK_ULL(15, 0) 169 170 static struct mlx5_ib_mr * 171 _mlx5_frmr_pool_alloc(struct mlx5_ib_dev *dev, struct ib_umem *umem, 172 int access_flags, int access_mode, 173 unsigned long page_size, u16 st_index, u8 ph) 174 { 175 struct mlx5_ib_mr *mr; 176 int err; 177 178 mr = kzalloc_obj(*mr); 179 if (!mr) 180 return ERR_PTR(-ENOMEM); 181 182 mr->ibmr.frmr.key.ats = mlx5_umem_needs_ats(dev, umem, access_flags); 183 mr->ibmr.frmr.key.access_flags = 184 get_unchangeable_access_flags(dev, access_flags); 185 mr->ibmr.frmr.key.num_dma_blocks = 186 ib_umem_num_dma_blocks(umem, page_size); 187 mr->ibmr.frmr.key.vendor_key = 188 access_mode == MLX5_MKC_ACCESS_MODE_KSM ? 189 MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK : 190 0; 191 192 /* Normalize ph: swap 0 and MLX5_IB_NO_PH */ 193 if (ph == MLX5_IB_NO_PH || ph == 0) 194 ph ^= MLX5_IB_NO_PH; 195 196 mr->ibmr.frmr.key.kernel_vendor_key = 197 FIELD_PREP(MLX5_FRMR_POOLS_KERNEL_KEY_ST_INDEX_MASK, st_index) | 198 FIELD_PREP(MLX5_FRMR_POOLS_KERNEL_KEY_PH_MASK, ph); 199 err = ib_frmr_pool_pop(&dev->ib_dev, &mr->ibmr); 200 if (err) { 201 kfree(mr); 202 return ERR_PTR(err); 203 } 204 mr->mmkey.key = mr->ibmr.frmr.handle; 205 init_waitqueue_head(&mr->mmkey.wait); 206 207 return mr; 208 } 209 210 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 211 int access_flags, int access_mode, 212 int ndescs) 213 { 214 struct ib_frmr_key key = { 215 .access_flags = 216 get_unchangeable_access_flags(dev, access_flags), 217 .vendor_key = access_mode == MLX5_MKC_ACCESS_MODE_MTT ? 218 0 : 219 MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK, 220 .num_dma_blocks = ndescs, 221 .kernel_vendor_key = 0, /* no PH and no ST index */ 222 }; 223 struct mlx5_ib_mr *mr; 224 int ret; 225 226 mr = kzalloc_obj(*mr); 227 if (!mr) 228 return ERR_PTR(-ENOMEM); 229 230 init_waitqueue_head(&mr->mmkey.wait); 231 232 mr->ibmr.frmr.key = key; 233 ret = ib_frmr_pool_pop(&dev->ib_dev, &mr->ibmr); 234 if (ret) { 235 kfree(mr); 236 return ERR_PTR(ret); 237 } 238 mr->mmkey.key = mr->ibmr.frmr.handle; 239 mr->mmkey.type = MLX5_MKEY_MR; 240 241 return mr; 242 } 243 244 static int mlx5r_create_mkeys(struct ib_device *device, struct ib_frmr_key *key, 245 u32 *handles, unsigned int count) 246 { 247 int access_mode = 248 key->vendor_key & MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK ? 249 MLX5_MKC_ACCESS_MODE_KSM : 250 MLX5_MKC_ACCESS_MODE_MTT; 251 252 struct mlx5_ib_dev *dev = to_mdev(device); 253 size_t inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 254 u16 st_index; 255 void *mkc; 256 u32 *in; 257 int err, i; 258 u8 ph; 259 260 in = kzalloc(inlen, GFP_KERNEL); 261 if (!in) 262 return -ENOMEM; 263 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 264 265 set_mkc_access_pd_addr_fields(mkc, key->access_flags, 0, dev->umrc.pd); 266 MLX5_SET(mkc, mkc, free, 1); 267 MLX5_SET(mkc, mkc, umr_en, 1); 268 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3); 269 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7); 270 MLX5_SET(mkc, mkc, ma_translation_mode, !!key->ats); 271 MLX5_SET(mkc, mkc, translations_octword_size, 272 get_mkc_octo_size(access_mode, key->num_dma_blocks)); 273 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); 274 275 st_index = FIELD_GET(MLX5_FRMR_POOLS_KERNEL_KEY_ST_INDEX_MASK, 276 key->kernel_vendor_key); 277 ph = FIELD_GET(MLX5_FRMR_POOLS_KERNEL_KEY_PH_MASK, 278 key->kernel_vendor_key); 279 if (ph) { 280 /* Normalize ph: swap MLX5_IB_NO_PH for 0 */ 281 if (ph == MLX5_IB_NO_PH) 282 ph = 0; 283 MLX5_SET(mkc, mkc, pcie_tph_en, 1); 284 MLX5_SET(mkc, mkc, pcie_tph_ph, ph); 285 if (st_index != MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX) 286 MLX5_SET(mkc, mkc, pcie_tph_steering_tag_index, 287 st_index); 288 } 289 290 for (i = 0; i < count; i++) { 291 assign_mkey_variant(dev, handles + i, in); 292 err = mlx5_core_create_mkey(dev->mdev, handles + i, in, inlen); 293 if (err) 294 goto free_in; 295 } 296 free_in: 297 kfree(in); 298 if (err) 299 for (i--; i >= 0; i--) 300 mlx5_core_destroy_mkey(dev->mdev, handles[i]); 301 return err; 302 } 303 304 static void mlx5r_destroy_mkeys(struct ib_device *device, u32 *handles, 305 unsigned int count) 306 { 307 struct mlx5_ib_dev *dev = to_mdev(device); 308 int i, err; 309 310 for (i = 0; i < count; i++) { 311 err = mlx5_core_destroy_mkey(dev->mdev, handles[i]); 312 if (err) 313 pr_warn_ratelimited( 314 "mlx5_ib: failed to destroy mkey %d: %d", 315 handles[i], err); 316 } 317 } 318 319 static int mlx5r_build_frmr_key(struct ib_device *device, 320 const struct ib_frmr_key *in, 321 struct ib_frmr_key *out) 322 { 323 struct mlx5_ib_dev *dev = to_mdev(device); 324 325 /* check HW capabilities of users requested frmr key */ 326 if ((in->ats && !MLX5_CAP_GEN(dev->mdev, ats)) || 327 ilog2(in->num_dma_blocks) > mkey_max_umr_order(dev)) 328 return -EOPNOTSUPP; 329 330 if (in->vendor_key & ~MLX5_FRMR_POOLS_KEY_VENDOR_KEY_SUPPORTED) 331 return -EOPNOTSUPP; 332 333 out->ats = in->ats; 334 out->access_flags = 335 get_unchangeable_access_flags(dev, in->access_flags); 336 out->vendor_key = in->vendor_key; 337 out->num_dma_blocks = in->num_dma_blocks; 338 339 return 0; 340 } 341 342 static const struct ib_frmr_pool_ops mlx5r_frmr_pool_ops = { 343 .create_frmrs = mlx5r_create_mkeys, 344 .destroy_frmrs = mlx5r_destroy_mkeys, 345 .build_key = mlx5r_build_frmr_key, 346 }; 347 348 int mlx5r_frmr_pools_init(struct ib_device *device) 349 { 350 struct mlx5_ib_dev *dev = to_mdev(device); 351 352 mutex_init(&dev->slow_path_mutex); 353 return ib_frmr_pools_init(device, &mlx5r_frmr_pool_ops); 354 } 355 356 void mlx5r_frmr_pools_cleanup(struct ib_device *device) 357 { 358 ib_frmr_pools_cleanup(device); 359 } 360 361 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) 362 { 363 struct mlx5_ib_dev *dev = to_mdev(pd->device); 364 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 365 struct mlx5_ib_mr *mr; 366 void *mkc; 367 u32 *in; 368 int err; 369 370 mr = kzalloc_obj(*mr); 371 if (!mr) 372 return ERR_PTR(-ENOMEM); 373 374 in = kzalloc(inlen, GFP_KERNEL); 375 if (!in) { 376 err = -ENOMEM; 377 goto err_free; 378 } 379 380 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 381 382 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 383 MLX5_SET(mkc, mkc, length64, 1); 384 set_mkc_access_pd_addr_fields(mkc, acc | IB_ACCESS_RELAXED_ORDERING, 0, 385 pd); 386 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); 387 388 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); 389 if (err) 390 goto err_in; 391 392 kfree(in); 393 mr->mmkey.type = MLX5_MKEY_MR; 394 mr->ibmr.lkey = mr->mmkey.key; 395 mr->ibmr.rkey = mr->mmkey.key; 396 mr->umem = NULL; 397 398 return &mr->ibmr; 399 400 err_in: 401 kfree(in); 402 403 err_free: 404 kfree(mr); 405 406 return ERR_PTR(err); 407 } 408 409 static int get_octo_len(u64 addr, u64 len, int page_shift) 410 { 411 u64 page_size = 1ULL << page_shift; 412 u64 offset; 413 int npages; 414 415 offset = addr & (page_size - 1); 416 npages = ALIGN(len + offset, page_size) >> page_shift; 417 return (npages + 1) / 2; 418 } 419 420 static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, 421 u64 length, int access_flags, u64 iova) 422 { 423 mr->ibmr.lkey = mr->mmkey.key; 424 mr->ibmr.rkey = mr->mmkey.key; 425 mr->ibmr.length = length; 426 mr->ibmr.device = &dev->ib_dev; 427 mr->ibmr.iova = iova; 428 mr->access_flags = access_flags; 429 } 430 431 static unsigned int mlx5_umem_dmabuf_default_pgsz(struct ib_umem *umem, 432 u64 iova) 433 { 434 /* 435 * The alignment of iova has already been checked upon entering 436 * UVERBS_METHOD_REG_DMABUF_MR 437 */ 438 umem->iova = iova; 439 return PAGE_SIZE; 440 } 441 442 static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd, 443 struct ib_umem *umem, u64 iova, 444 int access_flags, int access_mode, 445 u16 st_index, u8 ph) 446 { 447 struct mlx5_ib_dev *dev = to_mdev(pd->device); 448 struct mlx5_ib_mr *mr; 449 unsigned long page_size; 450 451 if (umem->is_dmabuf) 452 page_size = mlx5_umem_dmabuf_default_pgsz(umem, iova); 453 else 454 page_size = mlx5_umem_mkc_find_best_pgsz(dev, umem, iova, 455 access_mode); 456 if (WARN_ON(!page_size)) 457 return ERR_PTR(-EINVAL); 458 459 mr = _mlx5_frmr_pool_alloc(dev, umem, access_flags, access_mode, 460 page_size, st_index, ph); 461 if (IS_ERR(mr)) 462 return mr; 463 464 mr->mmkey.type = MLX5_MKEY_MR; 465 mr->ibmr.pd = pd; 466 mr->umem = umem; 467 mr->page_shift = order_base_2(page_size); 468 set_mr_fields(dev, mr, umem->length, access_flags, iova); 469 470 return mr; 471 } 472 473 static struct ib_mr * 474 reg_create_crossing_vhca_mr(struct ib_pd *pd, u64 iova, u64 length, int access_flags, 475 u32 crossed_lkey) 476 { 477 struct mlx5_ib_dev *dev = to_mdev(pd->device); 478 int access_mode = MLX5_MKC_ACCESS_MODE_CROSSING; 479 struct mlx5_ib_mr *mr; 480 void *mkc; 481 int inlen; 482 u32 *in; 483 int err; 484 485 if (!MLX5_CAP_GEN(dev->mdev, crossing_vhca_mkey)) 486 return ERR_PTR(-EOPNOTSUPP); 487 488 mr = kzalloc_obj(*mr); 489 if (!mr) 490 return ERR_PTR(-ENOMEM); 491 492 inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 493 in = kvzalloc(inlen, GFP_KERNEL); 494 if (!in) { 495 err = -ENOMEM; 496 goto err_1; 497 } 498 499 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 500 MLX5_SET(mkc, mkc, crossing_target_vhca_id, 501 MLX5_CAP_GEN(dev->mdev, vhca_id)); 502 MLX5_SET(mkc, mkc, translations_octword_size, crossed_lkey); 503 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3); 504 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7); 505 506 /* for this crossing mkey IOVA should be 0 and len should be IOVA + len */ 507 set_mkc_access_pd_addr_fields(mkc, access_flags, 0, pd); 508 MLX5_SET64(mkc, mkc, len, iova + length); 509 510 MLX5_SET(mkc, mkc, free, 0); 511 MLX5_SET(mkc, mkc, umr_en, 0); 512 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); 513 if (err) 514 goto err_2; 515 516 mr->mmkey.type = MLX5_MKEY_MR; 517 set_mr_fields(dev, mr, length, access_flags, iova); 518 mr->ibmr.pd = pd; 519 kvfree(in); 520 mlx5_ib_dbg(dev, "crossing mkey = 0x%x\n", mr->mmkey.key); 521 522 return &mr->ibmr; 523 err_2: 524 kvfree(in); 525 err_1: 526 kfree(mr); 527 return ERR_PTR(err); 528 } 529 530 /* 531 * If ibmr is NULL it will be allocated by reg_create. 532 * Else, the given ibmr will be used. 533 */ 534 static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, struct ib_umem *umem, 535 u64 iova, int access_flags, 536 unsigned long page_size, bool populate, 537 int access_mode, u16 st_index, u8 ph) 538 { 539 struct mlx5_ib_dev *dev = to_mdev(pd->device); 540 struct mlx5_ib_mr *mr; 541 __be64 *pas; 542 void *mkc; 543 int inlen; 544 u32 *in; 545 int err; 546 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)) && 547 (access_mode == MLX5_MKC_ACCESS_MODE_MTT) && 548 (ph == MLX5_IB_NO_PH); 549 bool ksm_mode = (access_mode == MLX5_MKC_ACCESS_MODE_KSM); 550 551 if (!page_size) 552 return ERR_PTR(-EINVAL); 553 mr = kzalloc_obj(*mr); 554 if (!mr) 555 return ERR_PTR(-ENOMEM); 556 557 mr->ibmr.pd = pd; 558 mr->access_flags = access_flags; 559 mr->page_shift = order_base_2(page_size); 560 561 inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 562 if (populate) 563 inlen += sizeof(*pas) * 564 roundup(ib_umem_num_dma_blocks(umem, page_size), 2); 565 in = kvzalloc(inlen, GFP_KERNEL); 566 if (!in) { 567 err = -ENOMEM; 568 goto err_1; 569 } 570 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 571 if (populate) { 572 if (WARN_ON(access_flags & IB_ACCESS_ON_DEMAND || ksm_mode)) { 573 err = -EINVAL; 574 goto err_2; 575 } 576 mlx5_ib_populate_pas(umem, 1UL << mr->page_shift, pas, 577 pg_cap ? MLX5_IB_MTT_PRESENT : 0); 578 } 579 580 /* The pg_access bit allows setting the access flags 581 * in the page list submitted with the command. 582 */ 583 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); 584 585 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 586 set_mkc_access_pd_addr_fields(mkc, access_flags, iova, 587 populate ? pd : dev->umrc.pd); 588 /* In case a data direct flow, overwrite the pdn field by its internal kernel PD */ 589 if (umem->is_dmabuf && ksm_mode) 590 MLX5_SET(mkc, mkc, pd, dev->ddr.pdn); 591 592 MLX5_SET(mkc, mkc, free, !populate); 593 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode); 594 MLX5_SET(mkc, mkc, umr_en, 1); 595 596 MLX5_SET64(mkc, mkc, len, umem->length); 597 MLX5_SET(mkc, mkc, bsf_octword_size, 0); 598 if (ksm_mode) 599 MLX5_SET(mkc, mkc, translations_octword_size, 600 get_octo_len(iova, umem->length, mr->page_shift) * 2); 601 else 602 MLX5_SET(mkc, mkc, translations_octword_size, 603 get_octo_len(iova, umem->length, mr->page_shift)); 604 MLX5_SET(mkc, mkc, log_page_size, mr->page_shift); 605 if (mlx5_umem_needs_ats(dev, umem, access_flags)) 606 MLX5_SET(mkc, mkc, ma_translation_mode, 1); 607 if (populate) { 608 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 609 get_octo_len(iova, umem->length, mr->page_shift)); 610 } 611 612 if (ph != MLX5_IB_NO_PH) { 613 MLX5_SET(mkc, mkc, pcie_tph_en, 1); 614 MLX5_SET(mkc, mkc, pcie_tph_ph, ph); 615 if (st_index != MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX) 616 MLX5_SET(mkc, mkc, pcie_tph_steering_tag_index, st_index); 617 } 618 619 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); 620 if (err) { 621 mlx5_ib_warn(dev, "create mkey failed\n"); 622 goto err_2; 623 } 624 mr->mmkey.type = MLX5_MKEY_MR; 625 mr->mmkey.ndescs = get_octo_len(iova, umem->length, mr->page_shift); 626 mr->umem = umem; 627 set_mr_fields(dev, mr, umem->length, access_flags, iova); 628 kvfree(in); 629 630 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); 631 632 return mr; 633 634 err_2: 635 kvfree(in); 636 err_1: 637 kfree(mr); 638 return ERR_PTR(err); 639 } 640 641 static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr, 642 u64 length, int acc, int mode) 643 { 644 struct mlx5_ib_dev *dev = to_mdev(pd->device); 645 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 646 struct mlx5_ib_mr *mr; 647 void *mkc; 648 u32 *in; 649 int err; 650 651 mr = kzalloc_obj(*mr); 652 if (!mr) 653 return ERR_PTR(-ENOMEM); 654 655 in = kzalloc(inlen, GFP_KERNEL); 656 if (!in) { 657 err = -ENOMEM; 658 goto err_free; 659 } 660 661 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 662 663 MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3); 664 MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7); 665 MLX5_SET64(mkc, mkc, len, length); 666 set_mkc_access_pd_addr_fields(mkc, acc, start_addr, pd); 667 668 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); 669 if (err) 670 goto err_in; 671 672 kfree(in); 673 674 set_mr_fields(dev, mr, length, acc, start_addr); 675 676 return &mr->ibmr; 677 678 err_in: 679 kfree(in); 680 681 err_free: 682 kfree(mr); 683 684 return ERR_PTR(err); 685 } 686 687 int mlx5_ib_advise_mr(struct ib_pd *pd, 688 enum ib_uverbs_advise_mr_advice advice, 689 u32 flags, 690 struct ib_sge *sg_list, 691 u32 num_sge, 692 struct uverbs_attr_bundle *attrs) 693 { 694 if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH && 695 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE && 696 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT) 697 return -EOPNOTSUPP; 698 699 return mlx5_ib_advise_mr_prefetch(pd, advice, flags, 700 sg_list, num_sge); 701 } 702 703 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 704 struct ib_dm_mr_attr *attr, 705 struct uverbs_attr_bundle *attrs) 706 { 707 struct mlx5_ib_dm *mdm = to_mdm(dm); 708 struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev; 709 u64 start_addr = mdm->dev_addr + attr->offset; 710 int mode; 711 712 switch (mdm->type) { 713 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 714 if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS) 715 return ERR_PTR(-EINVAL); 716 717 mode = MLX5_MKC_ACCESS_MODE_MEMIC; 718 start_addr -= pci_resource_start(dev->pdev, 0); 719 break; 720 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 721 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 722 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM: 723 case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM: 724 if (attr->access_flags & ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS) 725 return ERR_PTR(-EINVAL); 726 727 mode = MLX5_MKC_ACCESS_MODE_SW_ICM; 728 break; 729 default: 730 return ERR_PTR(-EINVAL); 731 } 732 733 return mlx5_ib_get_dm_mr(pd, start_addr, attr->length, 734 attr->access_flags, mode); 735 } 736 737 static struct ib_mr *create_real_mr(struct ib_pd *pd, struct ib_umem *umem, 738 u64 iova, int access_flags, 739 struct ib_dmah *dmah) 740 { 741 struct mlx5_ib_dev *dev = to_mdev(pd->device); 742 struct mlx5_ib_mr *mr = NULL; 743 bool xlt_with_umr; 744 u16 st_index = MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX; 745 u8 ph = MLX5_IB_NO_PH; 746 int err; 747 748 if (dmah) { 749 struct mlx5_ib_dmah *mdmah = to_mdmah(dmah); 750 751 ph = dmah->ph; 752 if (dmah->valid_fields & BIT(IB_DMAH_CPU_ID_EXISTS)) 753 st_index = mdmah->st_index; 754 } 755 756 xlt_with_umr = mlx5r_umr_can_load_pas(dev, umem->length); 757 if (xlt_with_umr) { 758 mr = alloc_cacheable_mr(pd, umem, iova, access_flags, 759 MLX5_MKC_ACCESS_MODE_MTT, 760 st_index, ph); 761 } else { 762 unsigned long page_size = mlx5_umem_mkc_find_best_pgsz( 763 dev, umem, iova, MLX5_MKC_ACCESS_MODE_MTT); 764 765 mutex_lock(&dev->slow_path_mutex); 766 mr = reg_create(pd, umem, iova, access_flags, page_size, 767 true, MLX5_MKC_ACCESS_MODE_MTT, 768 st_index, ph); 769 mutex_unlock(&dev->slow_path_mutex); 770 } 771 if (IS_ERR(mr)) { 772 ib_umem_release(umem); 773 return ERR_CAST(mr); 774 } 775 776 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); 777 778 atomic_add(ib_umem_num_pages(umem), &dev->mdev->priv.reg_pages); 779 780 if (xlt_with_umr) { 781 /* 782 * If the MR was created with reg_create then it will be 783 * configured properly but left disabled. It is safe to go ahead 784 * and configure it again via UMR while enabling it. 785 */ 786 err = mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ENABLE, 787 to_mpd(pd)->pdn); 788 if (err) { 789 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 790 return ERR_PTR(err); 791 } 792 } 793 return &mr->ibmr; 794 } 795 796 static struct ib_mr *create_user_odp_mr(struct ib_pd *pd, u64 start, u64 length, 797 u64 iova, int access_flags, 798 struct ib_udata *udata) 799 { 800 struct mlx5_ib_dev *dev = to_mdev(pd->device); 801 struct ib_umem_odp *odp; 802 struct mlx5_ib_mr *mr; 803 int err; 804 805 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) 806 return ERR_PTR(-EOPNOTSUPP); 807 808 err = mlx5r_odp_create_eq(dev, &dev->odp_pf_eq); 809 if (err) 810 return ERR_PTR(err); 811 if (!start && length == U64_MAX) { 812 if (iova != 0) 813 return ERR_PTR(-EINVAL); 814 if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) 815 return ERR_PTR(-EINVAL); 816 817 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); 818 if (IS_ERR(mr)) 819 return ERR_CAST(mr); 820 return &mr->ibmr; 821 } 822 823 /* ODP requires xlt update via umr to work. */ 824 if (!mlx5r_umr_can_load_pas(dev, length)) 825 return ERR_PTR(-EINVAL); 826 827 odp = ib_umem_odp_get(&dev->ib_dev, start, length, access_flags, 828 &mlx5_mn_ops); 829 if (IS_ERR(odp)) 830 return ERR_CAST(odp); 831 832 mr = alloc_cacheable_mr(pd, &odp->umem, iova, access_flags, 833 MLX5_MKC_ACCESS_MODE_MTT, 834 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX, 835 MLX5_IB_NO_PH); 836 if (IS_ERR(mr)) { 837 ib_umem_release(&odp->umem); 838 return ERR_CAST(mr); 839 } 840 xa_init(&mr->implicit_children); 841 842 odp->private = mr; 843 err = mlx5r_store_odp_mkey(dev, &mr->mmkey); 844 if (err) 845 goto err_dereg_mr; 846 847 err = mlx5_ib_init_odp_mr(mr, pd); 848 if (err) 849 goto err_dereg_mr; 850 return &mr->ibmr; 851 852 err_dereg_mr: 853 mlx5_ib_dereg_mr(&mr->ibmr, NULL); 854 return ERR_PTR(err); 855 } 856 857 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 858 u64 iova, int access_flags, 859 struct ib_dmah *dmah, 860 struct ib_udata *udata) 861 { 862 struct mlx5_ib_dev *dev = to_mdev(pd->device); 863 struct ib_umem *umem; 864 int err; 865 866 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM) || 867 ((access_flags & IB_ACCESS_ON_DEMAND) && dmah)) 868 return ERR_PTR(-EOPNOTSUPP); 869 870 mlx5_ib_dbg(dev, "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n", 871 start, iova, length, access_flags); 872 873 err = mlx5r_umr_resource_init(dev); 874 if (err) 875 return ERR_PTR(err); 876 877 if (access_flags & IB_ACCESS_ON_DEMAND) 878 return create_user_odp_mr(pd, start, length, iova, access_flags, 879 udata); 880 umem = ib_umem_get_va(&dev->ib_dev, start, length, access_flags); 881 if (IS_ERR(umem)) 882 return ERR_CAST(umem); 883 return create_real_mr(pd, umem, iova, access_flags, dmah); 884 } 885 886 static void mlx5_ib_dmabuf_invalidate_cb(struct dma_buf_attachment *attach) 887 { 888 struct ib_umem_dmabuf *umem_dmabuf = attach->importer_priv; 889 struct mlx5_ib_mr *mr = umem_dmabuf->private; 890 891 dma_resv_assert_held(umem_dmabuf->attach->dmabuf->resv); 892 893 if (!umem_dmabuf->sgt || !mr) 894 return; 895 896 /* MLX5_IB_UPD_XLT_ZAP does not change the pdn */ 897 mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ZAP, 0); 898 ib_umem_dmabuf_unmap_pages(umem_dmabuf); 899 } 900 901 static const struct dma_buf_attach_ops mlx5_ib_dmabuf_attach_ops = { 902 .allow_peer2peer = true, 903 .invalidate_mappings = mlx5_ib_dmabuf_invalidate_cb, 904 }; 905 906 static struct ib_mr * 907 reg_user_mr_dmabuf(struct ib_pd *pd, struct device *dma_device, 908 u64 offset, u64 length, u64 virt_addr, 909 int fd, int access_flags, int access_mode, 910 struct ib_dmah *dmah) 911 { 912 bool pinned_mode = (access_mode == MLX5_MKC_ACCESS_MODE_KSM); 913 struct mlx5_ib_dev *dev = to_mdev(pd->device); 914 struct mlx5_ib_mr *mr = NULL; 915 struct ib_umem_dmabuf *umem_dmabuf; 916 u16 st_index = MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX; 917 u8 ph = MLX5_IB_NO_PH; 918 int err; 919 920 err = mlx5r_umr_resource_init(dev); 921 if (err) 922 return ERR_PTR(err); 923 924 if (!pinned_mode) 925 umem_dmabuf = ib_umem_dmabuf_get(&dev->ib_dev, 926 offset, length, fd, 927 access_flags, 928 &mlx5_ib_dmabuf_attach_ops); 929 else if (dma_device) 930 umem_dmabuf = ib_umem_dmabuf_get_pinned_with_dma_device(&dev->ib_dev, 931 dma_device, offset, length, 932 fd, access_flags); 933 else 934 umem_dmabuf = ib_umem_dmabuf_get_pinned( 935 &dev->ib_dev, offset, length, fd, access_flags); 936 937 if (IS_ERR(umem_dmabuf)) { 938 mlx5_ib_dbg(dev, "umem_dmabuf get failed (%pe)\n", umem_dmabuf); 939 return ERR_CAST(umem_dmabuf); 940 } 941 942 if (dmah) { 943 struct mlx5_ib_dmah *mdmah = to_mdmah(dmah); 944 945 ph = dmah->ph; 946 if (dmah->valid_fields & BIT(IB_DMAH_CPU_ID_EXISTS)) 947 st_index = mdmah->st_index; 948 } 949 950 mr = alloc_cacheable_mr(pd, &umem_dmabuf->umem, virt_addr, 951 access_flags, access_mode, 952 st_index, ph); 953 if (IS_ERR(mr)) { 954 ib_umem_release(&umem_dmabuf->umem); 955 return ERR_CAST(mr); 956 } 957 958 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); 959 960 atomic_add(ib_umem_num_pages(mr->umem), &dev->mdev->priv.reg_pages); 961 umem_dmabuf->private = mr; 962 if (!pinned_mode) { 963 err = mlx5r_odp_create_eq(dev, &dev->odp_pf_eq); 964 if (err) 965 goto err_dereg_mr; 966 967 err = mlx5r_store_odp_mkey(dev, &mr->mmkey); 968 if (err) 969 goto err_dereg_mr; 970 } else { 971 mr->data_direct = true; 972 } 973 974 err = mlx5_ib_init_dmabuf_mr(mr, pd); 975 if (err) 976 goto err_dereg_mr; 977 return &mr->ibmr; 978 979 err_dereg_mr: 980 __mlx5_ib_dereg_mr(&mr->ibmr); 981 return ERR_PTR(err); 982 } 983 984 static struct ib_mr * 985 reg_user_mr_dmabuf_by_data_direct(struct ib_pd *pd, u64 offset, 986 u64 length, u64 virt_addr, 987 int fd, int access_flags) 988 { 989 struct mlx5_ib_dev *dev = to_mdev(pd->device); 990 struct mlx5_data_direct_dev *data_direct_dev; 991 struct ib_mr *crossing_mr; 992 struct ib_mr *crossed_mr; 993 int ret = 0; 994 995 /* As of HW behaviour the IOVA must be page aligned in KSM mode */ 996 if (!PAGE_ALIGNED(virt_addr) || (access_flags & IB_ACCESS_ON_DEMAND)) 997 return ERR_PTR(-EOPNOTSUPP); 998 999 mutex_lock(&dev->data_direct_lock); 1000 data_direct_dev = dev->data_direct_dev; 1001 if (!data_direct_dev) { 1002 ret = -EINVAL; 1003 goto end; 1004 } 1005 1006 /* If no device's 'data direct mkey' with RO flags exists 1007 * mask it out accordingly. 1008 */ 1009 if (!dev->ddr.mkey_ro_valid) 1010 access_flags &= ~IB_ACCESS_RELAXED_ORDERING; 1011 crossed_mr = reg_user_mr_dmabuf(pd, &data_direct_dev->pdev->dev, 1012 offset, length, virt_addr, fd, 1013 access_flags, MLX5_MKC_ACCESS_MODE_KSM, 1014 NULL); 1015 if (IS_ERR(crossed_mr)) { 1016 ret = PTR_ERR(crossed_mr); 1017 goto end; 1018 } 1019 1020 mutex_lock(&dev->slow_path_mutex); 1021 crossing_mr = reg_create_crossing_vhca_mr(pd, virt_addr, length, access_flags, 1022 crossed_mr->lkey); 1023 mutex_unlock(&dev->slow_path_mutex); 1024 if (IS_ERR(crossing_mr)) { 1025 __mlx5_ib_dereg_mr(crossed_mr); 1026 ret = PTR_ERR(crossing_mr); 1027 goto end; 1028 } 1029 1030 list_add_tail(&to_mmr(crossed_mr)->dd_node, &dev->data_direct_mr_list); 1031 to_mmr(crossing_mr)->dd_crossed_mr = to_mmr(crossed_mr); 1032 to_mmr(crossing_mr)->data_direct = true; 1033 end: 1034 mutex_unlock(&dev->data_direct_lock); 1035 return ret ? ERR_PTR(ret) : crossing_mr; 1036 } 1037 1038 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 offset, 1039 u64 length, u64 virt_addr, 1040 int fd, int access_flags, 1041 struct ib_dmah *dmah, 1042 struct uverbs_attr_bundle *attrs) 1043 { 1044 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1045 int mlx5_access_flags = 0; 1046 int err; 1047 1048 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM) || 1049 !IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) 1050 return ERR_PTR(-EOPNOTSUPP); 1051 1052 if (uverbs_attr_is_valid(attrs, MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS)) { 1053 err = uverbs_get_flags32(&mlx5_access_flags, attrs, 1054 MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 1055 MLX5_IB_UAPI_REG_DMABUF_ACCESS_DATA_DIRECT); 1056 if (err) 1057 return ERR_PTR(err); 1058 } 1059 1060 mlx5_ib_dbg(dev, 1061 "offset 0x%llx, virt_addr 0x%llx, length 0x%llx, fd %d, access_flags 0x%x, mlx5_access_flags 0x%x\n", 1062 offset, virt_addr, length, fd, access_flags, mlx5_access_flags); 1063 1064 /* dmabuf requires xlt update via umr to work. */ 1065 if (!mlx5r_umr_can_load_pas(dev, length)) 1066 return ERR_PTR(-EINVAL); 1067 1068 if (mlx5_access_flags & MLX5_IB_UAPI_REG_DMABUF_ACCESS_DATA_DIRECT) 1069 return reg_user_mr_dmabuf_by_data_direct(pd, offset, length, virt_addr, 1070 fd, access_flags); 1071 1072 return reg_user_mr_dmabuf(pd, NULL, offset, length, virt_addr, fd, 1073 access_flags, MLX5_MKC_ACCESS_MODE_MTT, dmah); 1074 } 1075 1076 /* 1077 * True if the change in access flags can be done via UMR, only some access 1078 * flags can be updated. 1079 */ 1080 static bool can_use_umr_rereg_access(struct mlx5_ib_dev *dev, 1081 unsigned int current_access_flags, 1082 unsigned int target_access_flags) 1083 { 1084 unsigned int diffs = current_access_flags ^ target_access_flags; 1085 1086 if (diffs & ~(IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | 1087 IB_ACCESS_REMOTE_READ | IB_ACCESS_RELAXED_ORDERING | 1088 IB_ACCESS_REMOTE_ATOMIC)) 1089 return false; 1090 return mlx5r_umr_can_reconfig(dev, current_access_flags, 1091 target_access_flags); 1092 } 1093 1094 static bool can_use_umr_rereg_pas(struct mlx5_ib_mr *mr, 1095 struct ib_umem *new_umem, 1096 int new_access_flags, u64 iova, 1097 unsigned long *page_size) 1098 { 1099 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 1100 u8 access_mode; 1101 1102 /* We only track the allocated sizes of MRs from the frmr pools */ 1103 if (!mr->ibmr.frmr.pool) 1104 return false; 1105 if (!mlx5r_umr_can_load_pas(dev, new_umem->length)) 1106 return false; 1107 1108 access_mode = mr->ibmr.frmr.key.vendor_key & 1109 MLX5_FRMR_POOLS_KEY_ACCESS_MODE_KSM_MASK ? 1110 MLX5_MKC_ACCESS_MODE_KSM : 1111 MLX5_MKC_ACCESS_MODE_MTT; 1112 1113 *page_size = 1114 mlx5_umem_mkc_find_best_pgsz(dev, new_umem, iova, access_mode); 1115 if (WARN_ON(!*page_size)) 1116 return false; 1117 return (mr->ibmr.frmr.key.num_dma_blocks) >= 1118 ib_umem_num_dma_blocks(new_umem, *page_size); 1119 } 1120 1121 static int umr_rereg_pas(struct mlx5_ib_mr *mr, struct ib_pd *pd, 1122 int access_flags, int flags, struct ib_umem *new_umem, 1123 u64 iova, unsigned long page_size) 1124 { 1125 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 1126 int upd_flags = MLX5_IB_UPD_XLT_ADDR | MLX5_IB_UPD_XLT_ENABLE; 1127 struct ib_umem *old_umem = mr->umem; 1128 int err; 1129 1130 /* 1131 * To keep everything simple the MR is revoked before we start to mess 1132 * with it. This ensure the change is atomic relative to any use of the 1133 * MR. 1134 */ 1135 err = mlx5r_umr_revoke_mr(mr); 1136 if (err) 1137 return err; 1138 1139 if (flags & IB_MR_REREG_PD) 1140 upd_flags |= MLX5_IB_UPD_XLT_PD; 1141 if (flags & IB_MR_REREG_ACCESS) { 1142 mr->access_flags = access_flags; 1143 upd_flags |= MLX5_IB_UPD_XLT_ACCESS; 1144 } 1145 1146 mr->ibmr.iova = iova; 1147 mr->ibmr.length = new_umem->length; 1148 mr->page_shift = order_base_2(page_size); 1149 mr->umem = new_umem; 1150 err = mlx5r_umr_update_mr_pas(mr, upd_flags, to_mpd(pd)->pdn); 1151 if (err) { 1152 /* 1153 * The MR is revoked at this point so there is no issue to free 1154 * new_umem. 1155 */ 1156 mr->umem = old_umem; 1157 return err; 1158 } 1159 1160 atomic_sub(ib_umem_num_pages(old_umem), &dev->mdev->priv.reg_pages); 1161 ib_umem_release(old_umem); 1162 atomic_add(ib_umem_num_pages(new_umem), &dev->mdev->priv.reg_pages); 1163 return 0; 1164 } 1165 1166 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1167 u64 length, u64 iova, int new_access_flags, 1168 struct ib_pd *new_pd, 1169 struct ib_udata *udata) 1170 { 1171 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); 1172 struct mlx5_ib_mr *mr = to_mmr(ib_mr); 1173 int err; 1174 1175 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM) || mr->data_direct || 1176 (mr->ibmr.frmr.key.kernel_vendor_key & 1177 MLX5_FRMR_POOLS_KERNEL_KEY_PH_MASK) != 0) 1178 return ERR_PTR(-EOPNOTSUPP); 1179 1180 mlx5_ib_dbg( 1181 dev, 1182 "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n", 1183 start, iova, length, new_access_flags); 1184 1185 if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS)) 1186 return ERR_PTR(-EOPNOTSUPP); 1187 1188 err = ib_umem_check_rereg(mr->umem, flags, new_access_flags); 1189 if (err) 1190 return ERR_PTR(err); 1191 1192 if (!(flags & IB_MR_REREG_ACCESS)) 1193 new_access_flags = mr->access_flags; 1194 if (!(flags & IB_MR_REREG_PD)) 1195 new_pd = ib_mr->pd; 1196 1197 if (mr->is_odp_implicit && !(flags & IB_MR_REREG_TRANS)) { 1198 if (!(new_access_flags & IB_ACCESS_ON_DEMAND)) 1199 return ERR_PTR(-EOPNOTSUPP); 1200 1201 /* 1202 * Due to all the child mkeys we cannot actually change an 1203 * implicit MR in place. If the user did not specify a new 1204 * translation then force the fixed implicit MR values. 1205 */ 1206 start = 0; 1207 iova = 0; 1208 length = U64_MAX; 1209 flags |= IB_MR_REREG_TRANS; 1210 } 1211 1212 if (!(flags & IB_MR_REREG_TRANS)) { 1213 struct ib_umem *umem; 1214 1215 /* Fast path for PD/access change */ 1216 if (can_use_umr_rereg_access(dev, mr->access_flags, 1217 new_access_flags)) { 1218 err = mlx5r_umr_rereg_pd_access(mr, new_pd, 1219 new_access_flags); 1220 if (err) 1221 return ERR_PTR(err); 1222 return NULL; 1223 } 1224 /* DM or ODP MR's don't have a normal umem so we can't re-use it */ 1225 if (!mr->umem || is_odp_mr(mr) || is_dmabuf_mr(mr)) 1226 return ERR_PTR(-EOPNOTSUPP); 1227 1228 /* 1229 * Only one active MR can refer to a umem at one time, revoke 1230 * the old MR before assigning the umem to the new one. 1231 */ 1232 err = mlx5r_umr_revoke_mr(mr); 1233 if (err) 1234 return ERR_PTR(err); 1235 umem = mr->umem; 1236 mr->umem = NULL; 1237 atomic_sub(ib_umem_num_pages(umem), &dev->mdev->priv.reg_pages); 1238 1239 return create_real_mr(new_pd, umem, mr->ibmr.iova, 1240 new_access_flags, NULL); 1241 } 1242 1243 /* 1244 * DM doesn't have a PAS list so we can't re-use it, odp/dmabuf does 1245 * but the logic around releasing the umem is different 1246 */ 1247 if (!mr->umem || is_odp_mr(mr) || is_dmabuf_mr(mr)) 1248 goto recreate; 1249 1250 if (!(new_access_flags & IB_ACCESS_ON_DEMAND) && 1251 can_use_umr_rereg_access(dev, mr->access_flags, new_access_flags)) { 1252 struct ib_umem *new_umem; 1253 unsigned long page_size; 1254 1255 new_umem = ib_umem_get_va(&dev->ib_dev, start, length, 1256 new_access_flags); 1257 if (IS_ERR(new_umem)) 1258 return ERR_CAST(new_umem); 1259 1260 /* Fast path for PAS change */ 1261 if (can_use_umr_rereg_pas(mr, new_umem, new_access_flags, iova, 1262 &page_size)) { 1263 err = umr_rereg_pas(mr, new_pd, new_access_flags, flags, 1264 new_umem, iova, page_size); 1265 if (err) { 1266 ib_umem_release(new_umem); 1267 return ERR_PTR(err); 1268 } 1269 return NULL; 1270 } 1271 return create_real_mr(new_pd, new_umem, iova, new_access_flags, NULL); 1272 } 1273 1274 /* 1275 * Everything else has no state we can preserve, just create a new MR 1276 * from scratch 1277 */ 1278 recreate: 1279 return mlx5_ib_reg_user_mr(new_pd, start, length, iova, 1280 new_access_flags, NULL, udata); 1281 } 1282 1283 static int 1284 mlx5_alloc_priv_descs(struct ib_device *device, 1285 struct mlx5_ib_mr *mr, 1286 int ndescs, 1287 int desc_size) 1288 { 1289 struct mlx5_ib_dev *dev = to_mdev(device); 1290 struct device *ddev = &dev->mdev->pdev->dev; 1291 int size = ndescs * desc_size; 1292 int add_size; 1293 int ret; 1294 1295 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); 1296 if (is_power_of_2(MLX5_UMR_ALIGN) && add_size) { 1297 int end = max_t(int, MLX5_UMR_ALIGN, roundup_pow_of_two(size)); 1298 1299 add_size = min_t(int, end - size, add_size); 1300 } 1301 1302 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); 1303 if (!mr->descs_alloc) 1304 return -ENOMEM; 1305 1306 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); 1307 1308 mr->desc_map = dma_map_single(ddev, mr->descs, size, DMA_TO_DEVICE); 1309 if (dma_mapping_error(ddev, mr->desc_map)) { 1310 ret = -ENOMEM; 1311 goto err; 1312 } 1313 1314 return 0; 1315 err: 1316 kfree(mr->descs_alloc); 1317 1318 return ret; 1319 } 1320 1321 static void 1322 mlx5_free_priv_descs(struct mlx5_ib_mr *mr) 1323 { 1324 if (!mr->umem && !mr->data_direct && 1325 mr->ibmr.type != IB_MR_TYPE_DM && mr->descs) { 1326 struct ib_device *device = mr->ibmr.device; 1327 int size = mr->max_descs * mr->desc_size; 1328 struct mlx5_ib_dev *dev = to_mdev(device); 1329 1330 dma_unmap_single(&dev->mdev->pdev->dev, mr->desc_map, size, 1331 DMA_TO_DEVICE); 1332 kfree(mr->descs_alloc); 1333 mr->descs = NULL; 1334 } 1335 } 1336 1337 static int mlx5_ib_revoke_data_direct_mr(struct mlx5_ib_mr *mr) 1338 { 1339 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 1340 struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem); 1341 int err; 1342 1343 lockdep_assert_held(&dev->data_direct_lock); 1344 mr->revoked = true; 1345 err = mlx5r_umr_revoke_mr(mr); 1346 if (WARN_ON(err)) 1347 return err; 1348 1349 ib_umem_dmabuf_revoke(umem_dmabuf); 1350 return 0; 1351 } 1352 1353 void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev) 1354 { 1355 struct mlx5_ib_mr *mr, *next; 1356 1357 lockdep_assert_held(&dev->data_direct_lock); 1358 1359 list_for_each_entry_safe(mr, next, &dev->data_direct_mr_list, dd_node) { 1360 list_del(&mr->dd_node); 1361 mlx5_ib_revoke_data_direct_mr(mr); 1362 } 1363 } 1364 1365 static int mlx5_umr_revoke_mr_with_lock(struct mlx5_ib_mr *mr) 1366 { 1367 bool is_odp_dma_buf = is_dmabuf_mr(mr) && 1368 !to_ib_umem_dmabuf(mr->umem)->pinned; 1369 bool is_odp = is_odp_mr(mr); 1370 int ret; 1371 1372 if (is_odp) 1373 mutex_lock(&to_ib_umem_odp(mr->umem)->umem_mutex); 1374 1375 if (is_odp_dma_buf) 1376 dma_resv_lock(to_ib_umem_dmabuf(mr->umem)->attach->dmabuf->resv, 1377 NULL); 1378 1379 ret = mlx5r_umr_revoke_mr(mr); 1380 1381 if (is_odp) { 1382 if (!ret) 1383 to_ib_umem_odp(mr->umem)->private = NULL; 1384 mutex_unlock(&to_ib_umem_odp(mr->umem)->umem_mutex); 1385 } 1386 1387 if (is_odp_dma_buf) { 1388 if (!ret) 1389 to_ib_umem_dmabuf(mr->umem)->private = NULL; 1390 dma_resv_unlock( 1391 to_ib_umem_dmabuf(mr->umem)->attach->dmabuf->resv); 1392 } 1393 1394 return ret; 1395 } 1396 1397 static int mlx5r_handle_mkey_cleanup(struct mlx5_ib_mr *mr) 1398 { 1399 bool is_odp_dma_buf = is_dmabuf_mr(mr) && 1400 !to_ib_umem_dmabuf(mr->umem)->pinned; 1401 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 1402 bool is_odp = is_odp_mr(mr); 1403 int ret; 1404 1405 if (mr->ibmr.frmr.pool) { 1406 if (!mlx5_umr_revoke_mr_with_lock(mr)) { 1407 ib_frmr_pool_push(mr->ibmr.device, &mr->ibmr); 1408 return 0; 1409 } 1410 } 1411 1412 if (is_odp) 1413 mutex_lock(&to_ib_umem_odp(mr->umem)->umem_mutex); 1414 1415 if (is_odp_dma_buf) 1416 dma_resv_lock(to_ib_umem_dmabuf(mr->umem)->attach->dmabuf->resv, 1417 NULL); 1418 ret = destroy_mkey(dev, mr); 1419 if (is_odp) { 1420 if (!ret) 1421 to_ib_umem_odp(mr->umem)->private = NULL; 1422 mutex_unlock(&to_ib_umem_odp(mr->umem)->umem_mutex); 1423 } 1424 1425 if (is_odp_dma_buf) { 1426 if (!ret) 1427 to_ib_umem_dmabuf(mr->umem)->private = NULL; 1428 dma_resv_unlock( 1429 to_ib_umem_dmabuf(mr->umem)->attach->dmabuf->resv); 1430 } 1431 1432 if (mr->ibmr.frmr.pool && !ret) 1433 ib_frmr_pool_drop(&mr->ibmr); 1434 1435 return ret; 1436 } 1437 1438 static int __mlx5_ib_dereg_mr(struct ib_mr *ibmr) 1439 { 1440 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1441 struct mlx5_ib_dev *dev = to_mdev(ibmr->device); 1442 int rc; 1443 1444 /* 1445 * Any async use of the mr must hold the refcount, once the refcount 1446 * goes to zero no other thread, such as ODP page faults, prefetch, any 1447 * UMR activity, etc can touch the mkey. Thus it is safe to destroy it. 1448 */ 1449 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && 1450 refcount_read(&mr->mmkey.usecount) != 0 && 1451 xa_erase(&mr_to_mdev(mr)->odp_mkeys, mlx5_base_mkey(mr->mmkey.key))) 1452 mlx5r_deref_wait_odp_mkey(&mr->mmkey); 1453 1454 if (ibmr->type == IB_MR_TYPE_INTEGRITY) { 1455 xa_cmpxchg(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key), 1456 mr->sig, NULL, GFP_KERNEL); 1457 1458 if (mr->mtt_mr) { 1459 rc = mlx5_ib_dereg_mr(&mr->mtt_mr->ibmr, NULL); 1460 if (rc) 1461 return rc; 1462 mr->mtt_mr = NULL; 1463 } 1464 if (mr->klm_mr) { 1465 rc = mlx5_ib_dereg_mr(&mr->klm_mr->ibmr, NULL); 1466 if (rc) 1467 return rc; 1468 mr->klm_mr = NULL; 1469 } 1470 1471 if (mlx5_core_destroy_psv(dev->mdev, 1472 mr->sig->psv_memory.psv_idx)) 1473 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1474 mr->sig->psv_memory.psv_idx); 1475 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx)) 1476 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1477 mr->sig->psv_wire.psv_idx); 1478 kfree(mr->sig); 1479 mr->sig = NULL; 1480 } 1481 1482 /* Stop DMA */ 1483 rc = mlx5r_handle_mkey_cleanup(mr); 1484 if (rc) 1485 return rc; 1486 1487 if (mr->umem) { 1488 bool is_odp = is_odp_mr(mr); 1489 1490 if (!is_odp) 1491 atomic_sub(ib_umem_num_pages(mr->umem), 1492 &dev->mdev->priv.reg_pages); 1493 ib_umem_release(mr->umem); 1494 if (is_odp) 1495 mlx5_ib_free_odp_mr(mr); 1496 } 1497 1498 if (!mr->ibmr.frmr.pool) 1499 mlx5_free_priv_descs(mr); 1500 1501 kfree(mr); 1502 return 0; 1503 } 1504 1505 static int dereg_crossing_data_direct_mr(struct mlx5_ib_dev *dev, 1506 struct mlx5_ib_mr *mr) 1507 { 1508 struct mlx5_ib_mr *dd_crossed_mr = mr->dd_crossed_mr; 1509 int ret; 1510 1511 ret = __mlx5_ib_dereg_mr(&mr->ibmr); 1512 if (ret) 1513 return ret; 1514 1515 mutex_lock(&dev->data_direct_lock); 1516 if (!dd_crossed_mr->revoked) 1517 list_del(&dd_crossed_mr->dd_node); 1518 1519 ret = __mlx5_ib_dereg_mr(&dd_crossed_mr->ibmr); 1520 mutex_unlock(&dev->data_direct_lock); 1521 return ret; 1522 } 1523 1524 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) 1525 { 1526 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1527 struct mlx5_ib_dev *dev = to_mdev(ibmr->device); 1528 1529 if (mr->data_direct) 1530 return dereg_crossing_data_direct_mr(dev, mr); 1531 1532 return __mlx5_ib_dereg_mr(ibmr); 1533 } 1534 1535 static void mlx5_set_umr_free_mkey(struct ib_pd *pd, u32 *in, int ndescs, 1536 int access_mode, int page_shift) 1537 { 1538 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1539 void *mkc; 1540 1541 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1542 1543 /* This is only used from the kernel, so setting the PD is OK. */ 1544 set_mkc_access_pd_addr_fields(mkc, IB_ACCESS_RELAXED_ORDERING, 0, pd); 1545 MLX5_SET(mkc, mkc, free, 1); 1546 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1547 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3); 1548 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7); 1549 MLX5_SET(mkc, mkc, umr_en, 1); 1550 MLX5_SET(mkc, mkc, log_page_size, page_shift); 1551 if (access_mode == MLX5_MKC_ACCESS_MODE_PA || 1552 access_mode == MLX5_MKC_ACCESS_MODE_MTT) 1553 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); 1554 } 1555 1556 static int _mlx5_alloc_mkey_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1557 int ndescs, int desc_size, int page_shift, 1558 int access_mode, u32 *in, int inlen) 1559 { 1560 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1561 int err; 1562 1563 mr->access_mode = access_mode; 1564 mr->desc_size = desc_size; 1565 mr->max_descs = ndescs; 1566 1567 err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size); 1568 if (err) 1569 return err; 1570 1571 mlx5_set_umr_free_mkey(pd, in, ndescs, access_mode, page_shift); 1572 1573 err = mlx5_ib_create_mkey(dev, &mr->mmkey, in, inlen); 1574 if (err) 1575 goto err_free_descs; 1576 1577 mr->mmkey.type = MLX5_MKEY_MR; 1578 mr->ibmr.lkey = mr->mmkey.key; 1579 mr->ibmr.rkey = mr->mmkey.key; 1580 1581 return 0; 1582 1583 err_free_descs: 1584 mlx5_free_priv_descs(mr); 1585 return err; 1586 } 1587 1588 static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd, 1589 u32 max_num_sg, u32 max_num_meta_sg, 1590 int desc_size, int access_mode) 1591 { 1592 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1593 int ndescs = ALIGN(max_num_sg + max_num_meta_sg, 4); 1594 int page_shift = 0; 1595 struct mlx5_ib_mr *mr; 1596 u32 *in; 1597 int err; 1598 1599 mr = kzalloc_obj(*mr); 1600 if (!mr) 1601 return ERR_PTR(-ENOMEM); 1602 1603 mr->ibmr.pd = pd; 1604 mr->ibmr.device = pd->device; 1605 1606 in = kzalloc(inlen, GFP_KERNEL); 1607 if (!in) { 1608 err = -ENOMEM; 1609 goto err_free; 1610 } 1611 1612 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT) 1613 page_shift = PAGE_SHIFT; 1614 1615 err = _mlx5_alloc_mkey_descs(pd, mr, ndescs, desc_size, page_shift, 1616 access_mode, in, inlen); 1617 if (err) 1618 goto err_free_in; 1619 1620 mr->umem = NULL; 1621 kfree(in); 1622 1623 return mr; 1624 1625 err_free_in: 1626 kfree(in); 1627 err_free: 1628 kfree(mr); 1629 return ERR_PTR(err); 1630 } 1631 1632 static int mlx5_alloc_mem_reg_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1633 int ndescs, u32 *in, int inlen) 1634 { 1635 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_mtt), 1636 PAGE_SHIFT, MLX5_MKC_ACCESS_MODE_MTT, in, 1637 inlen); 1638 } 1639 1640 static int mlx5_alloc_sg_gaps_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1641 int ndescs, u32 *in, int inlen) 1642 { 1643 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_klm), 1644 0, MLX5_MKC_ACCESS_MODE_KLMS, in, inlen); 1645 } 1646 1647 static int mlx5_alloc_integrity_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr, 1648 int max_num_sg, int max_num_meta_sg, 1649 u32 *in, int inlen) 1650 { 1651 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1652 u32 psv_index[2]; 1653 void *mkc; 1654 int err; 1655 1656 mr->sig = kzalloc_obj(*mr->sig); 1657 if (!mr->sig) 1658 return -ENOMEM; 1659 1660 /* create mem & wire PSVs */ 1661 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 2, psv_index); 1662 if (err) 1663 goto err_free_sig; 1664 1665 mr->sig->psv_memory.psv_idx = psv_index[0]; 1666 mr->sig->psv_wire.psv_idx = psv_index[1]; 1667 1668 mr->sig->sig_status_checked = true; 1669 mr->sig->sig_err_exists = false; 1670 /* Next UMR, Arm SIGERR */ 1671 ++mr->sig->sigerr_count; 1672 mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg, 1673 sizeof(struct mlx5_klm), 1674 MLX5_MKC_ACCESS_MODE_KLMS); 1675 if (IS_ERR(mr->klm_mr)) { 1676 err = PTR_ERR(mr->klm_mr); 1677 goto err_destroy_psv; 1678 } 1679 mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg, 1680 sizeof(struct mlx5_mtt), 1681 MLX5_MKC_ACCESS_MODE_MTT); 1682 if (IS_ERR(mr->mtt_mr)) { 1683 err = PTR_ERR(mr->mtt_mr); 1684 goto err_free_klm_mr; 1685 } 1686 1687 /* Set bsf descriptors for mkey */ 1688 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1689 MLX5_SET(mkc, mkc, bsf_en, 1); 1690 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); 1691 1692 err = _mlx5_alloc_mkey_descs(pd, mr, 4, sizeof(struct mlx5_klm), 0, 1693 MLX5_MKC_ACCESS_MODE_KLMS, in, inlen); 1694 if (err) 1695 goto err_free_mtt_mr; 1696 1697 err = xa_err(xa_store(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key), 1698 mr->sig, GFP_KERNEL)); 1699 if (err) 1700 goto err_free_descs; 1701 return 0; 1702 1703 err_free_descs: 1704 destroy_mkey(dev, mr); 1705 mlx5_free_priv_descs(mr); 1706 err_free_mtt_mr: 1707 mlx5_ib_dereg_mr(&mr->mtt_mr->ibmr, NULL); 1708 mr->mtt_mr = NULL; 1709 err_free_klm_mr: 1710 mlx5_ib_dereg_mr(&mr->klm_mr->ibmr, NULL); 1711 mr->klm_mr = NULL; 1712 err_destroy_psv: 1713 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_memory.psv_idx)) 1714 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", 1715 mr->sig->psv_memory.psv_idx); 1716 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx)) 1717 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", 1718 mr->sig->psv_wire.psv_idx); 1719 err_free_sig: 1720 kfree(mr->sig); 1721 1722 return err; 1723 } 1724 1725 static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd, 1726 enum ib_mr_type mr_type, u32 max_num_sg, 1727 u32 max_num_meta_sg) 1728 { 1729 struct mlx5_ib_dev *dev = to_mdev(pd->device); 1730 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1731 int ndescs = ALIGN(max_num_sg, 4); 1732 struct mlx5_ib_mr *mr; 1733 u32 *in; 1734 int err; 1735 1736 mr = kzalloc_obj(*mr); 1737 if (!mr) 1738 return ERR_PTR(-ENOMEM); 1739 1740 in = kzalloc(inlen, GFP_KERNEL); 1741 if (!in) { 1742 err = -ENOMEM; 1743 goto err_free; 1744 } 1745 1746 mr->ibmr.device = pd->device; 1747 mr->umem = NULL; 1748 1749 switch (mr_type) { 1750 case IB_MR_TYPE_MEM_REG: 1751 err = mlx5_alloc_mem_reg_descs(pd, mr, ndescs, in, inlen); 1752 break; 1753 case IB_MR_TYPE_SG_GAPS: 1754 err = mlx5_alloc_sg_gaps_descs(pd, mr, ndescs, in, inlen); 1755 break; 1756 case IB_MR_TYPE_INTEGRITY: 1757 err = mlx5_alloc_integrity_descs(pd, mr, max_num_sg, 1758 max_num_meta_sg, in, inlen); 1759 break; 1760 default: 1761 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); 1762 err = -EINVAL; 1763 } 1764 1765 if (err) 1766 goto err_free_in; 1767 1768 kfree(in); 1769 1770 return &mr->ibmr; 1771 1772 err_free_in: 1773 kfree(in); 1774 err_free: 1775 kfree(mr); 1776 return ERR_PTR(err); 1777 } 1778 1779 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1780 u32 max_num_sg) 1781 { 1782 return __mlx5_ib_alloc_mr(pd, mr_type, max_num_sg, 0); 1783 } 1784 1785 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1786 u32 max_num_sg, u32 max_num_meta_sg) 1787 { 1788 return __mlx5_ib_alloc_mr(pd, IB_MR_TYPE_INTEGRITY, max_num_sg, 1789 max_num_meta_sg); 1790 } 1791 1792 int mlx5_ib_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata) 1793 { 1794 struct mlx5_ib_dev *dev = to_mdev(ibmw->device); 1795 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 1796 struct mlx5_ib_mw *mw = to_mmw(ibmw); 1797 unsigned int ndescs; 1798 u32 *in = NULL; 1799 void *mkc; 1800 int err; 1801 struct mlx5_ib_alloc_mw req = {}; 1802 struct { 1803 __u32 comp_mask; 1804 __u32 response_length; 1805 } resp = {}; 1806 1807 if (udata->inlen) { 1808 err = ib_copy_validate_udata_in_cm(udata, req, reserved2, 0); 1809 if (err) 1810 return err; 1811 } 1812 1813 if (req.reserved1 || req.reserved2) 1814 return -EOPNOTSUPP; 1815 1816 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); 1817 1818 in = kzalloc(inlen, GFP_KERNEL); 1819 if (!in) 1820 return -ENOMEM; 1821 1822 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1823 1824 MLX5_SET(mkc, mkc, free, 1); 1825 MLX5_SET(mkc, mkc, translations_octword_size, ndescs); 1826 MLX5_SET(mkc, mkc, pd, to_mpd(ibmw->pd)->pdn); 1827 MLX5_SET(mkc, mkc, umr_en, 1); 1828 MLX5_SET(mkc, mkc, lr, 1); 1829 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); 1830 MLX5_SET(mkc, mkc, en_rinval, !!((ibmw->type == IB_MW_TYPE_2))); 1831 MLX5_SET(mkc, mkc, qpn, 0xffffff); 1832 1833 err = mlx5_ib_create_mkey(dev, &mw->mmkey, in, inlen); 1834 if (err) 1835 goto free; 1836 1837 mw->mmkey.type = MLX5_MKEY_MW; 1838 ibmw->rkey = mw->mmkey.key; 1839 mw->mmkey.ndescs = ndescs; 1840 1841 resp.response_length = 1842 min(offsetofend(typeof(resp), response_length), udata->outlen); 1843 if (resp.response_length) { 1844 err = ib_respond_udata(udata, resp); 1845 if (err) 1846 goto free_mkey; 1847 } 1848 1849 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1850 err = mlx5r_store_odp_mkey(dev, &mw->mmkey); 1851 if (err) 1852 goto free_mkey; 1853 } 1854 1855 kfree(in); 1856 return 0; 1857 1858 free_mkey: 1859 mlx5_core_destroy_mkey(dev->mdev, mw->mmkey.key); 1860 free: 1861 kfree(in); 1862 return err; 1863 } 1864 1865 int mlx5_ib_dealloc_mw(struct ib_mw *mw) 1866 { 1867 struct mlx5_ib_dev *dev = to_mdev(mw->device); 1868 struct mlx5_ib_mw *mmw = to_mmw(mw); 1869 1870 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && 1871 xa_erase(&dev->odp_mkeys, mlx5_base_mkey(mmw->mmkey.key))) 1872 /* 1873 * pagefault_single_data_segment() may be accessing mmw 1874 * if the user bound an ODP MR to this MW. 1875 */ 1876 mlx5r_deref_wait_odp_mkey(&mmw->mmkey); 1877 1878 return mlx5_core_destroy_mkey(dev->mdev, mmw->mmkey.key); 1879 } 1880 1881 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1882 struct ib_mr_status *mr_status) 1883 { 1884 struct mlx5_ib_mr *mmr = to_mmr(ibmr); 1885 int ret = 0; 1886 1887 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { 1888 pr_err("Invalid status check mask\n"); 1889 ret = -EINVAL; 1890 goto done; 1891 } 1892 1893 mr_status->fail_status = 0; 1894 if (check_mask & IB_MR_CHECK_SIG_STATUS) { 1895 if (!mmr->sig) { 1896 ret = -EINVAL; 1897 pr_err("signature status check requested on a non-signature enabled MR\n"); 1898 goto done; 1899 } 1900 1901 mmr->sig->sig_status_checked = true; 1902 if (!mmr->sig->sig_err_exists) 1903 goto done; 1904 1905 if (ibmr->lkey == mmr->sig->err_item.key) 1906 memcpy(&mr_status->sig_err, &mmr->sig->err_item, 1907 sizeof(mr_status->sig_err)); 1908 else { 1909 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; 1910 mr_status->sig_err.sig_err_offset = 0; 1911 mr_status->sig_err.key = mmr->sig->err_item.key; 1912 } 1913 1914 mmr->sig->sig_err_exists = false; 1915 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; 1916 } 1917 1918 done: 1919 return ret; 1920 } 1921 1922 static int 1923 mlx5_ib_map_pa_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1924 int data_sg_nents, unsigned int *data_sg_offset, 1925 struct scatterlist *meta_sg, int meta_sg_nents, 1926 unsigned int *meta_sg_offset) 1927 { 1928 struct mlx5_ib_mr *mr = to_mmr(ibmr); 1929 unsigned int sg_offset = 0; 1930 int n = 0; 1931 1932 mr->meta_length = 0; 1933 if (data_sg_nents == 1) { 1934 n++; 1935 mr->mmkey.ndescs = 1; 1936 if (data_sg_offset) 1937 sg_offset = *data_sg_offset; 1938 mr->data_length = sg_dma_len(data_sg) - sg_offset; 1939 mr->data_iova = sg_dma_address(data_sg) + sg_offset; 1940 if (meta_sg_nents == 1) { 1941 n++; 1942 mr->meta_ndescs = 1; 1943 if (meta_sg_offset) 1944 sg_offset = *meta_sg_offset; 1945 else 1946 sg_offset = 0; 1947 mr->meta_length = sg_dma_len(meta_sg) - sg_offset; 1948 mr->pi_iova = sg_dma_address(meta_sg) + sg_offset; 1949 } 1950 ibmr->length = mr->data_length + mr->meta_length; 1951 } 1952 1953 return n; 1954 } 1955 1956 static int 1957 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, 1958 struct scatterlist *sgl, 1959 unsigned short sg_nents, 1960 unsigned int *sg_offset_p, 1961 struct scatterlist *meta_sgl, 1962 unsigned short meta_sg_nents, 1963 unsigned int *meta_sg_offset_p) 1964 { 1965 struct scatterlist *sg = sgl; 1966 struct mlx5_klm *klms = mr->descs; 1967 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; 1968 u32 lkey = mr->ibmr.pd->local_dma_lkey; 1969 int i, j = 0; 1970 1971 mr->ibmr.iova = sg_dma_address(sg) + sg_offset; 1972 mr->ibmr.length = 0; 1973 1974 for_each_sg(sgl, sg, sg_nents, i) { 1975 if (unlikely(i >= mr->max_descs)) 1976 break; 1977 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); 1978 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); 1979 klms[i].key = cpu_to_be32(lkey); 1980 mr->ibmr.length += sg_dma_len(sg) - sg_offset; 1981 1982 sg_offset = 0; 1983 } 1984 1985 if (sg_offset_p) 1986 *sg_offset_p = sg_offset; 1987 1988 mr->mmkey.ndescs = i; 1989 mr->data_length = mr->ibmr.length; 1990 1991 if (meta_sg_nents) { 1992 sg = meta_sgl; 1993 sg_offset = meta_sg_offset_p ? *meta_sg_offset_p : 0; 1994 for_each_sg(meta_sgl, sg, meta_sg_nents, j) { 1995 if (unlikely(i + j >= mr->max_descs)) 1996 break; 1997 klms[i + j].va = cpu_to_be64(sg_dma_address(sg) + 1998 sg_offset); 1999 klms[i + j].bcount = cpu_to_be32(sg_dma_len(sg) - 2000 sg_offset); 2001 klms[i + j].key = cpu_to_be32(lkey); 2002 mr->ibmr.length += sg_dma_len(sg) - sg_offset; 2003 2004 sg_offset = 0; 2005 } 2006 if (meta_sg_offset_p) 2007 *meta_sg_offset_p = sg_offset; 2008 2009 mr->meta_ndescs = j; 2010 mr->meta_length = mr->ibmr.length - mr->data_length; 2011 } 2012 2013 return i + j; 2014 } 2015 2016 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) 2017 { 2018 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2019 __be64 *descs; 2020 2021 if (unlikely(mr->mmkey.ndescs == mr->max_descs)) 2022 return -ENOMEM; 2023 2024 descs = mr->descs; 2025 descs[mr->mmkey.ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); 2026 2027 return 0; 2028 } 2029 2030 static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr) 2031 { 2032 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2033 __be64 *descs; 2034 2035 if (unlikely(mr->mmkey.ndescs + mr->meta_ndescs == mr->max_descs)) 2036 return -ENOMEM; 2037 2038 descs = mr->descs; 2039 descs[mr->mmkey.ndescs + mr->meta_ndescs++] = 2040 cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); 2041 2042 return 0; 2043 } 2044 2045 static int 2046 mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 2047 int data_sg_nents, unsigned int *data_sg_offset, 2048 struct scatterlist *meta_sg, int meta_sg_nents, 2049 unsigned int *meta_sg_offset) 2050 { 2051 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2052 struct mlx5_ib_mr *pi_mr = mr->mtt_mr; 2053 int n; 2054 2055 pi_mr->mmkey.ndescs = 0; 2056 pi_mr->meta_ndescs = 0; 2057 pi_mr->meta_length = 0; 2058 2059 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map, 2060 pi_mr->desc_size * pi_mr->max_descs, 2061 DMA_TO_DEVICE); 2062 2063 pi_mr->ibmr.page_size = ibmr->page_size; 2064 n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset, 2065 mlx5_set_page); 2066 if (n != data_sg_nents) 2067 return n; 2068 2069 pi_mr->data_iova = pi_mr->ibmr.iova; 2070 pi_mr->data_length = pi_mr->ibmr.length; 2071 pi_mr->ibmr.length = pi_mr->data_length; 2072 ibmr->length = pi_mr->data_length; 2073 2074 if (meta_sg_nents) { 2075 u64 page_mask = ~((u64)ibmr->page_size - 1); 2076 u64 iova = pi_mr->data_iova; 2077 2078 n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents, 2079 meta_sg_offset, mlx5_set_page_pi); 2080 2081 pi_mr->meta_length = pi_mr->ibmr.length; 2082 /* 2083 * PI address for the HW is the offset of the metadata address 2084 * relative to the first data page address. 2085 * It equals to first data page address + size of data pages + 2086 * metadata offset at the first metadata page 2087 */ 2088 pi_mr->pi_iova = (iova & page_mask) + 2089 pi_mr->mmkey.ndescs * ibmr->page_size + 2090 (pi_mr->ibmr.iova & ~page_mask); 2091 /* 2092 * In order to use one MTT MR for data and metadata, we register 2093 * also the gaps between the end of the data and the start of 2094 * the metadata (the sig MR will verify that the HW will access 2095 * to right addresses). This mapping is safe because we use 2096 * internal mkey for the registration. 2097 */ 2098 pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova; 2099 pi_mr->ibmr.iova = iova; 2100 ibmr->length += pi_mr->meta_length; 2101 } 2102 2103 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map, 2104 pi_mr->desc_size * pi_mr->max_descs, 2105 DMA_TO_DEVICE); 2106 2107 return n; 2108 } 2109 2110 static int 2111 mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 2112 int data_sg_nents, unsigned int *data_sg_offset, 2113 struct scatterlist *meta_sg, int meta_sg_nents, 2114 unsigned int *meta_sg_offset) 2115 { 2116 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2117 struct mlx5_ib_mr *pi_mr = mr->klm_mr; 2118 int n; 2119 2120 pi_mr->mmkey.ndescs = 0; 2121 pi_mr->meta_ndescs = 0; 2122 pi_mr->meta_length = 0; 2123 2124 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map, 2125 pi_mr->desc_size * pi_mr->max_descs, 2126 DMA_TO_DEVICE); 2127 2128 n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset, 2129 meta_sg, meta_sg_nents, meta_sg_offset); 2130 2131 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map, 2132 pi_mr->desc_size * pi_mr->max_descs, 2133 DMA_TO_DEVICE); 2134 2135 /* This is zero-based memory region */ 2136 pi_mr->data_iova = 0; 2137 pi_mr->ibmr.iova = 0; 2138 pi_mr->pi_iova = pi_mr->data_length; 2139 ibmr->length = pi_mr->ibmr.length; 2140 2141 return n; 2142 } 2143 2144 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 2145 int data_sg_nents, unsigned int *data_sg_offset, 2146 struct scatterlist *meta_sg, int meta_sg_nents, 2147 unsigned int *meta_sg_offset) 2148 { 2149 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2150 struct mlx5_ib_mr *pi_mr = NULL; 2151 int n; 2152 2153 WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY); 2154 2155 mr->mmkey.ndescs = 0; 2156 mr->data_length = 0; 2157 mr->data_iova = 0; 2158 mr->meta_ndescs = 0; 2159 mr->pi_iova = 0; 2160 /* 2161 * As a performance optimization, if possible, there is no need to 2162 * perform UMR operation to register the data/metadata buffers. 2163 * First try to map the sg lists to PA descriptors with local_dma_lkey. 2164 * Fallback to UMR only in case of a failure. 2165 */ 2166 n = mlx5_ib_map_pa_mr_sg_pi(ibmr, data_sg, data_sg_nents, 2167 data_sg_offset, meta_sg, meta_sg_nents, 2168 meta_sg_offset); 2169 if (n == data_sg_nents + meta_sg_nents) 2170 goto out; 2171 /* 2172 * As a performance optimization, if possible, there is no need to map 2173 * the sg lists to KLM descriptors. First try to map the sg lists to MTT 2174 * descriptors and fallback to KLM only in case of a failure. 2175 * It's more efficient for the HW to work with MTT descriptors 2176 * (especially in high load). 2177 * Use KLM (indirect access) only if it's mandatory. 2178 */ 2179 pi_mr = mr->mtt_mr; 2180 n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents, 2181 data_sg_offset, meta_sg, meta_sg_nents, 2182 meta_sg_offset); 2183 if (n == data_sg_nents + meta_sg_nents) 2184 goto out; 2185 2186 pi_mr = mr->klm_mr; 2187 n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents, 2188 data_sg_offset, meta_sg, meta_sg_nents, 2189 meta_sg_offset); 2190 if (unlikely(n != data_sg_nents + meta_sg_nents)) 2191 return -ENOMEM; 2192 2193 out: 2194 /* This is zero-based memory region */ 2195 ibmr->iova = 0; 2196 mr->pi_mr = pi_mr; 2197 if (pi_mr) 2198 ibmr->sig_attrs->meta_length = pi_mr->meta_length; 2199 else 2200 ibmr->sig_attrs->meta_length = mr->meta_length; 2201 2202 return 0; 2203 } 2204 2205 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 2206 unsigned int *sg_offset) 2207 { 2208 struct mlx5_ib_mr *mr = to_mmr(ibmr); 2209 int n; 2210 2211 mr->mmkey.ndescs = 0; 2212 2213 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, 2214 mr->desc_size * mr->max_descs, 2215 DMA_TO_DEVICE); 2216 2217 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 2218 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset, NULL, 0, 2219 NULL); 2220 else 2221 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, 2222 mlx5_set_page); 2223 2224 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, 2225 mr->desc_size * mr->max_descs, 2226 DMA_TO_DEVICE); 2227 2228 return n; 2229 } 2230