1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 #include "qp.h" 29 #include "macsec.h" 30 31 #define mlx5_ib_dbg(_dev, format, arg...) \ 32 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 33 __LINE__, current->pid, ##arg) 34 35 #define mlx5_ib_err(_dev, format, arg...) \ 36 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 37 __LINE__, current->pid, ##arg) 38 39 #define mlx5_ib_warn(_dev, format, arg...) \ 40 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 41 __LINE__, current->pid, ##arg) 42 43 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 44 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 45 __func__, __LINE__, current->pid, ##arg) 46 47 #define MLX5_IB_DEFAULT_UIDX 0xffffff 48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 49 50 static __always_inline unsigned long 51 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 52 unsigned int pgsz_shift) 53 { 54 unsigned int largest_pg_shift = 55 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 56 BITS_PER_LONG - 1); 57 58 /* 59 * Despite a command allowing it, the device does not support lower than 60 * 4k page size. 61 */ 62 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 63 return GENMASK(largest_pg_shift, pgsz_shift); 64 } 65 66 static __always_inline unsigned long 67 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 68 unsigned int offset_shift) 69 { 70 unsigned int largest_offset_shift = 71 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 72 BITS_PER_LONG - 1); 73 74 return GENMASK(largest_offset_shift, offset_shift); 75 } 76 77 /* 78 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 79 * page_offset_quantized * (page_size/scale) = page_offset 80 * Which restricts allowed page sizes to ones that satisify the above. 81 */ 82 unsigned long __mlx5_umem_find_best_quantized_pgoff( 83 struct ib_umem *umem, unsigned long pgsz_bitmap, 84 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 85 unsigned int *page_offset_quantized); 86 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 87 pgsz_shift, page_offset_fld, \ 88 scale, page_offset_quantized) \ 89 __mlx5_umem_find_best_quantized_pgoff( \ 90 umem, \ 91 __mlx5_log_page_size_to_bitmap( \ 92 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 93 __mlx5_bit_sz(typ, page_offset_fld), \ 94 GENMASK(31, order_base_2(scale)), scale, \ 95 page_offset_quantized) 96 97 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 98 pgsz_shift, page_offset_fld, \ 99 scale, page_offset_quantized) \ 100 __mlx5_umem_find_best_quantized_pgoff( \ 101 umem, \ 102 __mlx5_log_page_size_to_bitmap( \ 103 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 104 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 105 page_offset_quantized) 106 107 static inline unsigned long 108 mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf) 109 { 110 /* 111 * mkeys used for dmabuf are fixed at PAGE_SIZE because we must be able 112 * to hold any sgl after a move operation. Ideally the mkc page size 113 * could be changed at runtime to be optimal, but right now the driver 114 * cannot do that. 115 */ 116 return ib_umem_find_best_pgsz(&umem_dmabuf->umem, PAGE_SIZE, 117 umem_dmabuf->umem.iova); 118 } 119 120 enum { 121 MLX5_IB_MMAP_OFFSET_START = 9, 122 MLX5_IB_MMAP_OFFSET_END = 255, 123 }; 124 125 enum { 126 MLX5_IB_MMAP_CMD_SHIFT = 8, 127 MLX5_IB_MMAP_CMD_MASK = 0xff, 128 }; 129 130 enum { 131 MLX5_RES_SCAT_DATA32_CQE = 0x1, 132 MLX5_RES_SCAT_DATA64_CQE = 0x2, 133 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 134 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 135 }; 136 137 enum mlx5_ib_mad_ifc_flags { 138 MLX5_MAD_IFC_IGNORE_MKEY = 1, 139 MLX5_MAD_IFC_IGNORE_BKEY = 2, 140 MLX5_MAD_IFC_NET_VIEW = 4, 141 }; 142 143 enum { 144 MLX5_CROSS_CHANNEL_BFREG = 0, 145 }; 146 147 enum { 148 MLX5_CQE_VERSION_V0, 149 MLX5_CQE_VERSION_V1, 150 }; 151 152 enum { 153 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 154 MLX5_TM_MAX_SGE = 1, 155 }; 156 157 enum { 158 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 159 MLX5_IB_INVALID_BFREG = BIT(31), 160 }; 161 162 enum { 163 MLX5_MAX_MEMIC_PAGES = 0x100, 164 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 165 }; 166 167 enum { 168 MLX5_MEMIC_BASE_ALIGN = 6, 169 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 170 }; 171 172 enum mlx5_ib_mmap_type { 173 MLX5_IB_MMAP_TYPE_MEMIC = 1, 174 MLX5_IB_MMAP_TYPE_VAR = 2, 175 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 176 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 177 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 178 }; 179 180 struct mlx5_bfreg_info { 181 u32 *sys_pages; 182 int num_low_latency_bfregs; 183 unsigned int *count; 184 185 /* 186 * protect bfreg allocation data structs 187 */ 188 struct mutex lock; 189 u32 ver; 190 u8 lib_uar_4k : 1; 191 u8 lib_uar_dyn : 1; 192 u32 num_sys_pages; 193 u32 num_static_sys_pages; 194 u32 total_num_bfregs; 195 u32 num_dyn_bfregs; 196 }; 197 198 struct mlx5_ib_ucontext { 199 struct ib_ucontext ibucontext; 200 struct list_head db_page_list; 201 202 /* protect doorbell record alloc/free 203 */ 204 struct mutex db_page_mutex; 205 struct mlx5_bfreg_info bfregi; 206 u8 cqe_version; 207 /* Transport Domain number */ 208 u32 tdn; 209 210 u64 lib_caps; 211 u16 devx_uid; 212 /* For RoCE LAG TX affinity */ 213 atomic_t tx_port_affinity; 214 }; 215 216 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 217 { 218 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 219 } 220 221 struct mlx5_ib_pd { 222 struct ib_pd ibpd; 223 u32 pdn; 224 u16 uid; 225 }; 226 227 enum { 228 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 229 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 230 MLX5_IB_FLOW_ACTION_DECAP, 231 }; 232 233 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 234 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 235 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 236 #error "Invalid number of bypass priorities" 237 #endif 238 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 239 240 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 241 #define MLX5_IB_NUM_SNIFFER_FTS 2 242 #define MLX5_IB_NUM_EGRESS_FTS 1 243 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 244 245 struct mlx5_ib_anchor { 246 struct mlx5_flow_table *ft; 247 struct mlx5_flow_group *fg_goto_table; 248 struct mlx5_flow_group *fg_drop; 249 struct mlx5_flow_handle *rule_goto_table; 250 struct mlx5_flow_handle *rule_drop; 251 unsigned int rule_goto_table_ref; 252 }; 253 254 struct mlx5_ib_flow_prio { 255 struct mlx5_flow_table *flow_table; 256 struct mlx5_ib_anchor anchor; 257 unsigned int refcount; 258 }; 259 260 struct mlx5_ib_flow_handler { 261 struct list_head list; 262 struct ib_flow ibflow; 263 struct mlx5_ib_flow_prio *prio; 264 struct mlx5_flow_handle *rule; 265 struct ib_counters *ibcounters; 266 struct mlx5_ib_dev *dev; 267 struct mlx5_ib_flow_matcher *flow_matcher; 268 }; 269 270 struct mlx5_ib_flow_matcher { 271 struct mlx5_ib_match_params matcher_mask; 272 int mask_len; 273 enum mlx5_ib_flow_type flow_type; 274 enum mlx5_flow_namespace_type ns_type; 275 u16 priority; 276 struct mlx5_core_dev *mdev; 277 atomic_t usecnt; 278 u8 match_criteria_enable; 279 }; 280 281 struct mlx5_ib_steering_anchor { 282 struct mlx5_ib_flow_prio *ft_prio; 283 struct mlx5_ib_dev *dev; 284 atomic_t usecnt; 285 }; 286 287 struct mlx5_ib_pp { 288 u16 index; 289 struct mlx5_core_dev *mdev; 290 }; 291 292 enum mlx5_ib_optional_counter_type { 293 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 294 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 295 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 296 297 MLX5_IB_OPCOUNTER_MAX, 298 }; 299 300 struct mlx5_ib_flow_db { 301 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 302 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 303 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 304 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 305 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 306 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 307 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 308 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 309 struct mlx5_flow_table *lag_demux_ft; 310 /* Protect flow steering bypass flow tables 311 * when add/del flow rules. 312 * only single add/removal of flow steering rule could be done 313 * simultaneously. 314 */ 315 struct mutex lock; 316 }; 317 318 /* Use macros here so that don't have to duplicate 319 * enum ib_qp_type for low-level driver 320 */ 321 322 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 323 /* 324 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 325 * creates the actual hardware QP. 326 */ 327 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 328 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 329 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 330 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 331 332 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 333 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 334 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 335 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 336 #define MLX5_IB_UPD_XLT_PD BIT(4) 337 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 338 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 339 340 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 341 * 342 * These flags are intended for internal use by the mlx5_ib driver, and they 343 * rely on the range reserved for that use in the ib_qp_create_flags enum. 344 */ 345 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 346 347 struct wr_list { 348 u16 opcode; 349 u16 next; 350 }; 351 352 enum mlx5_ib_rq_flags { 353 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 354 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 355 }; 356 357 struct mlx5_ib_wq { 358 struct mlx5_frag_buf_ctrl fbc; 359 u64 *wrid; 360 u32 *wr_data; 361 struct wr_list *w_list; 362 unsigned *wqe_head; 363 u16 unsig_count; 364 365 /* serialize post to the work queue 366 */ 367 spinlock_t lock; 368 int wqe_cnt; 369 int max_post; 370 int max_gs; 371 int offset; 372 int wqe_shift; 373 unsigned head; 374 unsigned tail; 375 u16 cur_post; 376 u16 last_poll; 377 void *cur_edge; 378 }; 379 380 enum mlx5_ib_wq_flags { 381 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 382 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 383 }; 384 385 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 386 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 387 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 388 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 389 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 390 391 struct mlx5_ib_rwq { 392 struct ib_wq ibwq; 393 struct mlx5_core_qp core_qp; 394 u32 rq_num_pas; 395 u32 log_rq_stride; 396 u32 log_rq_size; 397 u32 rq_page_offset; 398 u32 log_page_size; 399 u32 log_num_strides; 400 u32 two_byte_shift_en; 401 u32 single_stride_log_num_of_bytes; 402 struct ib_umem *umem; 403 size_t buf_size; 404 unsigned int page_shift; 405 struct mlx5_db db; 406 u32 user_index; 407 u32 wqe_count; 408 u32 wqe_shift; 409 int wq_sig; 410 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 411 }; 412 413 struct mlx5_ib_rwq_ind_table { 414 struct ib_rwq_ind_table ib_rwq_ind_tbl; 415 u32 rqtn; 416 u16 uid; 417 }; 418 419 struct mlx5_ib_ubuffer { 420 struct ib_umem *umem; 421 int buf_size; 422 u64 buf_addr; 423 }; 424 425 struct mlx5_ib_qp_base { 426 struct mlx5_ib_qp *container_mibqp; 427 struct mlx5_core_qp mqp; 428 struct mlx5_ib_ubuffer ubuffer; 429 }; 430 431 struct mlx5_ib_qp_trans { 432 struct mlx5_ib_qp_base base; 433 u16 xrcdn; 434 u32 alt_port; 435 u8 atomic_rd_en; 436 u8 resp_depth; 437 }; 438 439 struct mlx5_ib_rss_qp { 440 u32 tirn; 441 }; 442 443 struct mlx5_ib_rq { 444 struct mlx5_ib_qp_base base; 445 struct mlx5_ib_wq *rq; 446 struct mlx5_ib_ubuffer ubuffer; 447 struct mlx5_db *doorbell; 448 u32 tirn; 449 u8 state; 450 u32 flags; 451 }; 452 453 struct mlx5_ib_sq { 454 struct mlx5_ib_qp_base base; 455 struct mlx5_ib_wq *sq; 456 struct mlx5_ib_ubuffer ubuffer; 457 struct mlx5_db *doorbell; 458 struct mlx5_flow_handle *flow_rule; 459 u32 tisn; 460 u8 state; 461 }; 462 463 struct mlx5_ib_raw_packet_qp { 464 struct mlx5_ib_sq sq; 465 struct mlx5_ib_rq rq; 466 }; 467 468 struct mlx5_bf { 469 int buf_size; 470 unsigned long offset; 471 struct mlx5_sq_bfreg *bfreg; 472 }; 473 474 struct mlx5_ib_dct { 475 struct mlx5_core_dct mdct; 476 u32 *in; 477 }; 478 479 struct mlx5_ib_gsi_qp { 480 struct ib_qp *rx_qp; 481 u32 port_num; 482 struct ib_qp_cap cap; 483 struct ib_cq *cq; 484 struct mlx5_ib_gsi_wr *outstanding_wrs; 485 u32 outstanding_pi, outstanding_ci; 486 int num_qps; 487 /* Protects access to the tx_qps. Post send operations synchronize 488 * with tx_qp creation in setup_qp(). Also protects the 489 * outstanding_wrs array and indices. 490 */ 491 spinlock_t lock; 492 struct ib_qp **tx_qps; 493 }; 494 495 struct mlx5_ib_qp { 496 struct ib_qp ibqp; 497 union { 498 struct mlx5_ib_qp_trans trans_qp; 499 struct mlx5_ib_raw_packet_qp raw_packet_qp; 500 struct mlx5_ib_rss_qp rss_qp; 501 struct mlx5_ib_dct dct; 502 struct mlx5_ib_gsi_qp gsi; 503 }; 504 struct mlx5_frag_buf buf; 505 506 struct mlx5_db db; 507 struct mlx5_ib_wq rq; 508 509 u8 sq_signal_bits; 510 u8 next_fence; 511 struct mlx5_ib_wq sq; 512 513 /* serialize qp state modifications 514 */ 515 struct mutex mutex; 516 /* cached variant of create_flags from struct ib_qp_init_attr */ 517 u32 flags; 518 u32 port; 519 u8 state; 520 int max_inline_data; 521 struct mlx5_bf bf; 522 u8 has_rq:1; 523 u8 is_rss:1; 524 u8 is_ooo_rq:1; 525 526 /* only for user space QPs. For kernel 527 * we have it from the bf object 528 */ 529 int bfregn; 530 531 struct list_head qps_list; 532 struct list_head cq_recv_list; 533 struct list_head cq_send_list; 534 struct mlx5_rate_limit rl; 535 u32 underlay_qpn; 536 u32 flags_en; 537 /* 538 * IB/core doesn't store low-level QP types, so 539 * store both MLX and IBTA types in the field below. 540 */ 541 enum ib_qp_type type; 542 /* A flag to indicate if there's a new counter is configured 543 * but not take effective 544 */ 545 u32 counter_pending; 546 u16 gsi_lag_port; 547 }; 548 549 struct mlx5_ib_cq_buf { 550 struct mlx5_frag_buf_ctrl fbc; 551 struct mlx5_frag_buf frag_buf; 552 struct ib_umem *umem; 553 int cqe_size; 554 int nent; 555 }; 556 557 enum mlx5_ib_cq_pr_flags { 558 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 559 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 560 }; 561 562 struct mlx5_ib_cq { 563 struct ib_cq ibcq; 564 struct mlx5_core_cq mcq; 565 struct mlx5_ib_cq_buf buf; 566 struct mlx5_db db; 567 568 /* serialize access to the CQ 569 */ 570 spinlock_t lock; 571 572 /* protect resize cq 573 */ 574 struct mutex resize_mutex; 575 struct mlx5_ib_cq_buf *resize_buf; 576 struct ib_umem *resize_umem; 577 int cqe_size; 578 struct list_head list_send_qp; 579 struct list_head list_recv_qp; 580 u32 create_flags; 581 struct list_head wc_list; 582 enum ib_cq_notify_flags notify_flags; 583 struct work_struct notify_work; 584 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 585 }; 586 587 struct mlx5_ib_wc { 588 struct ib_wc wc; 589 struct list_head list; 590 }; 591 592 struct mlx5_ib_srq { 593 struct ib_srq ibsrq; 594 struct mlx5_core_srq msrq; 595 struct mlx5_frag_buf buf; 596 struct mlx5_db db; 597 struct mlx5_frag_buf_ctrl fbc; 598 u64 *wrid; 599 /* protect SRQ hanlding 600 */ 601 spinlock_t lock; 602 int head; 603 int tail; 604 u16 wqe_ctr; 605 struct ib_umem *umem; 606 /* serialize arming a SRQ 607 */ 608 struct mutex mutex; 609 int wq_sig; 610 }; 611 612 struct mlx5_ib_xrcd { 613 struct ib_xrcd ibxrcd; 614 u32 xrcdn; 615 }; 616 617 enum mlx5_ib_mtt_access_flags { 618 MLX5_IB_MTT_READ = (1 << 0), 619 MLX5_IB_MTT_WRITE = (1 << 1), 620 }; 621 622 struct mlx5_user_mmap_entry { 623 struct rdma_user_mmap_entry rdma_entry; 624 u8 mmap_flag; 625 u64 address; 626 u32 page_idx; 627 }; 628 629 enum mlx5_mkey_type { 630 MLX5_MKEY_MR = 1, 631 MLX5_MKEY_MW, 632 MLX5_MKEY_INDIRECT_DEVX, 633 MLX5_MKEY_NULL, 634 MLX5_MKEY_IMPLICIT_CHILD, 635 }; 636 637 struct mlx5r_cache_rb_key { 638 u8 ats:1; 639 unsigned int access_mode; 640 unsigned int access_flags; 641 unsigned int ndescs; 642 }; 643 644 struct mlx5_ib_mkey { 645 u32 key; 646 enum mlx5_mkey_type type; 647 unsigned int ndescs; 648 struct wait_queue_head wait; 649 refcount_t usecount; 650 /* Cacheable user Mkey must hold either a rb_key or a cache_ent. */ 651 struct mlx5r_cache_rb_key rb_key; 652 struct mlx5_cache_ent *cache_ent; 653 u8 cacheable : 1; 654 }; 655 656 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 657 658 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 659 IB_ACCESS_REMOTE_WRITE |\ 660 IB_ACCESS_REMOTE_READ |\ 661 IB_ACCESS_REMOTE_ATOMIC |\ 662 IB_ZERO_BASED) 663 664 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 665 IB_ACCESS_REMOTE_WRITE |\ 666 IB_ACCESS_REMOTE_READ |\ 667 IB_ZERO_BASED) 668 669 #define mlx5_update_odp_stats(mr, counter_name, value) \ 670 atomic64_add(value, &((mr)->odp_stats.counter_name)) 671 672 #define mlx5_update_odp_stats_with_handled(mr, counter_name, value) \ 673 do { \ 674 mlx5_update_odp_stats(mr, counter_name, value); \ 675 atomic64_add(1, &((mr)->odp_stats.counter_name##_handled)); \ 676 } while (0) 677 678 struct mlx5_ib_mr { 679 struct ib_mr ibmr; 680 struct mlx5_ib_mkey mmkey; 681 682 struct ib_umem *umem; 683 /* The mr is data direct related */ 684 u8 data_direct :1; 685 686 union { 687 /* Used only by kernel MRs (umem == NULL) */ 688 struct { 689 void *descs; 690 void *descs_alloc; 691 dma_addr_t desc_map; 692 int max_descs; 693 int desc_size; 694 int access_mode; 695 696 /* For Kernel IB_MR_TYPE_INTEGRITY */ 697 struct mlx5_core_sig_ctx *sig; 698 struct mlx5_ib_mr *pi_mr; 699 struct mlx5_ib_mr *klm_mr; 700 struct mlx5_ib_mr *mtt_mr; 701 u64 data_iova; 702 u64 pi_iova; 703 int meta_ndescs; 704 int meta_length; 705 int data_length; 706 }; 707 708 /* Used only by User MRs (umem != NULL) */ 709 struct { 710 unsigned int page_shift; 711 /* Current access_flags */ 712 int access_flags; 713 714 /* For User ODP */ 715 struct mlx5_ib_mr *parent; 716 struct xarray implicit_children; 717 union { 718 struct work_struct work; 719 } odp_destroy; 720 struct ib_odp_counters odp_stats; 721 bool is_odp_implicit; 722 /* The affilated data direct crossed mr */ 723 struct mlx5_ib_mr *dd_crossed_mr; 724 struct list_head dd_node; 725 u8 revoked :1; 726 struct mlx5_ib_mkey null_mmkey; 727 }; 728 }; 729 }; 730 731 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 732 { 733 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 734 mr->umem->is_odp; 735 } 736 737 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 738 { 739 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 740 mr->umem->is_dmabuf; 741 } 742 743 struct mlx5_ib_mw { 744 struct ib_mw ibmw; 745 struct mlx5_ib_mkey mmkey; 746 }; 747 748 struct mlx5_ib_umr_context { 749 struct ib_cqe cqe; 750 enum ib_wc_status status; 751 struct completion done; 752 }; 753 754 enum { 755 MLX5_UMR_STATE_UNINIT, 756 MLX5_UMR_STATE_ACTIVE, 757 MLX5_UMR_STATE_RECOVER, 758 MLX5_UMR_STATE_ERR, 759 }; 760 761 struct umr_common { 762 struct ib_pd *pd; 763 struct ib_cq *cq; 764 struct ib_qp *qp; 765 /* Protects from UMR QP overflow 766 */ 767 struct semaphore sem; 768 /* Protects from using UMR while the UMR is not active 769 */ 770 struct mutex lock; 771 unsigned int state; 772 /* Protects from repeat UMR QP creation */ 773 struct mutex init_lock; 774 }; 775 776 #define NUM_MKEYS_PER_PAGE \ 777 ((PAGE_SIZE - sizeof(struct list_head)) / sizeof(u32)) 778 779 struct mlx5_mkeys_page { 780 u32 mkeys[NUM_MKEYS_PER_PAGE]; 781 struct list_head list; 782 }; 783 static_assert(sizeof(struct mlx5_mkeys_page) == PAGE_SIZE); 784 785 struct mlx5_mkeys_queue { 786 struct list_head pages_list; 787 u32 num_pages; 788 unsigned long ci; 789 spinlock_t lock; /* sync list ops */ 790 }; 791 792 struct mlx5_cache_ent { 793 struct mlx5_mkeys_queue mkeys_queue; 794 u32 pending; 795 796 char name[4]; 797 798 struct rb_node node; 799 struct mlx5r_cache_rb_key rb_key; 800 801 u8 is_tmp:1; 802 u8 disabled:1; 803 u8 fill_to_high_water:1; 804 u8 tmp_cleanup_scheduled:1; 805 806 /* 807 * - limit is the low water mark for stored mkeys, 2* limit is the 808 * upper water mark. 809 */ 810 u32 in_use; 811 u32 limit; 812 813 /* Statistics */ 814 u32 miss; 815 816 struct mlx5_ib_dev *dev; 817 struct delayed_work dwork; 818 }; 819 820 struct mlx5r_async_create_mkey { 821 union { 822 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 823 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 824 }; 825 struct mlx5_async_work cb_work; 826 struct mlx5_cache_ent *ent; 827 u32 mkey; 828 }; 829 830 struct mlx5_mkey_cache { 831 struct workqueue_struct *wq; 832 struct rb_root rb_root; 833 struct mutex rb_lock; 834 struct dentry *fs_root; 835 unsigned long last_add; 836 }; 837 838 struct mlx5_ib_port_resources { 839 struct mlx5_ib_gsi_qp *gsi; 840 struct work_struct pkey_change_work; 841 }; 842 843 struct mlx5_data_direct_resources { 844 u32 pdn; 845 u32 mkey; 846 }; 847 848 struct mlx5_ib_resources { 849 struct ib_cq *c0; 850 struct mutex cq_lock; 851 u32 xrcdn0; 852 u32 xrcdn1; 853 struct ib_pd *p0; 854 struct ib_srq *s0; 855 struct ib_srq *s1; 856 struct mutex srq_lock; 857 struct mlx5_ib_port_resources ports[2]; 858 }; 859 860 #define MAX_OPFC_RULES 2 861 862 struct mlx5_ib_op_fc { 863 struct mlx5_fc *fc; 864 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 865 }; 866 867 struct mlx5_ib_counters { 868 struct rdma_stat_desc *descs; 869 size_t *offsets; 870 u32 num_q_counters; 871 u32 num_cong_counters; 872 u32 num_ext_ppcnt_counters; 873 u32 num_op_counters; 874 u16 set_id; 875 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 876 }; 877 878 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 879 struct mlx5_ib_op_fc *opfc, 880 enum mlx5_ib_optional_counter_type type); 881 882 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 883 struct mlx5_ib_op_fc *opfc, 884 enum mlx5_ib_optional_counter_type type); 885 886 struct mlx5_ib_multiport_info; 887 888 struct mlx5_ib_multiport { 889 struct mlx5_ib_multiport_info *mpi; 890 /* To be held when accessing the multiport info */ 891 spinlock_t mpi_lock; 892 }; 893 894 struct mlx5_roce { 895 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 896 * netdev pointer 897 */ 898 struct notifier_block nb; 899 struct netdev_net_notifier nn; 900 struct notifier_block mdev_nb; 901 struct net_device *tracking_netdev; 902 atomic_t tx_port_affinity; 903 enum ib_port_state last_port_state; 904 struct mlx5_ib_dev *dev; 905 u32 native_port_num; 906 }; 907 908 struct mlx5_ib_port { 909 struct mlx5_ib_counters cnts; 910 struct mlx5_ib_multiport mp; 911 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 912 struct mlx5_roce roce; 913 struct mlx5_eswitch_rep *rep; 914 #ifdef CONFIG_MLX5_MACSEC 915 struct mlx5_reserved_gids *reserved_gids; 916 #endif 917 }; 918 919 struct mlx5_ib_dbg_param { 920 int offset; 921 struct mlx5_ib_dev *dev; 922 struct dentry *dentry; 923 u32 port_num; 924 }; 925 926 enum mlx5_ib_dbg_cc_types { 927 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 928 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 929 MLX5_IB_DBG_CC_RP_TIME_RESET, 930 MLX5_IB_DBG_CC_RP_BYTE_RESET, 931 MLX5_IB_DBG_CC_RP_THRESHOLD, 932 MLX5_IB_DBG_CC_RP_AI_RATE, 933 MLX5_IB_DBG_CC_RP_MAX_RATE, 934 MLX5_IB_DBG_CC_RP_HAI_RATE, 935 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 936 MLX5_IB_DBG_CC_RP_MIN_RATE, 937 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 938 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 939 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 940 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 941 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 942 MLX5_IB_DBG_CC_RP_GD, 943 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 944 MLX5_IB_DBG_CC_NP_CNP_DSCP, 945 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 946 MLX5_IB_DBG_CC_NP_CNP_PRIO, 947 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 948 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 949 MLX5_IB_DBG_CC_MAX, 950 }; 951 952 struct mlx5_ib_dbg_cc_params { 953 struct dentry *root; 954 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 955 }; 956 957 enum { 958 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 959 }; 960 961 struct mlx5_ib_delay_drop { 962 struct mlx5_ib_dev *dev; 963 struct work_struct delay_drop_work; 964 /* serialize setting of delay drop */ 965 struct mutex lock; 966 u32 timeout; 967 bool activate; 968 atomic_t events_cnt; 969 atomic_t rqs_cnt; 970 struct dentry *dir_debugfs; 971 }; 972 973 enum mlx5_ib_stages { 974 MLX5_IB_STAGE_INIT, 975 MLX5_IB_STAGE_FS, 976 MLX5_IB_STAGE_CAPS, 977 MLX5_IB_STAGE_NON_DEFAULT_CB, 978 MLX5_IB_STAGE_ROCE, 979 MLX5_IB_STAGE_QP, 980 MLX5_IB_STAGE_SRQ, 981 MLX5_IB_STAGE_DEVICE_RESOURCES, 982 MLX5_IB_STAGE_ODP, 983 MLX5_IB_STAGE_COUNTERS, 984 MLX5_IB_STAGE_CONG_DEBUGFS, 985 MLX5_IB_STAGE_UAR, 986 MLX5_IB_STAGE_BFREG, 987 MLX5_IB_STAGE_PRE_IB_REG_UMR, 988 MLX5_IB_STAGE_WHITELIST_UID, 989 MLX5_IB_STAGE_IB_REG, 990 MLX5_IB_STAGE_DEVICE_NOTIFIER, 991 MLX5_IB_STAGE_POST_IB_REG_UMR, 992 MLX5_IB_STAGE_DELAY_DROP, 993 MLX5_IB_STAGE_RESTRACK, 994 MLX5_IB_STAGE_MAX, 995 }; 996 997 struct mlx5_ib_stage { 998 int (*init)(struct mlx5_ib_dev *dev); 999 void (*cleanup)(struct mlx5_ib_dev *dev); 1000 }; 1001 1002 #define STAGE_CREATE(_stage, _init, _cleanup) \ 1003 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 1004 1005 struct mlx5_ib_profile { 1006 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 1007 }; 1008 1009 struct mlx5_ib_multiport_info { 1010 struct list_head list; 1011 struct mlx5_ib_dev *ibdev; 1012 struct mlx5_core_dev *mdev; 1013 struct notifier_block mdev_events; 1014 struct completion unref_comp; 1015 u64 sys_image_guid; 1016 u32 mdev_refcnt; 1017 bool is_master; 1018 bool unaffiliate; 1019 }; 1020 1021 struct mlx5_ib_flow_action { 1022 struct ib_flow_action ib_action; 1023 union { 1024 struct { 1025 u64 ib_flags; 1026 struct mlx5_accel_esp_xfrm *ctx; 1027 } esp_aes_gcm; 1028 struct { 1029 struct mlx5_ib_dev *dev; 1030 u32 sub_type; 1031 union { 1032 struct mlx5_modify_hdr *modify_hdr; 1033 struct mlx5_pkt_reformat *pkt_reformat; 1034 }; 1035 } flow_action_raw; 1036 }; 1037 }; 1038 1039 struct mlx5_dm { 1040 struct mlx5_core_dev *dev; 1041 /* This lock is used to protect the access to the shared 1042 * allocation map when concurrent requests by different 1043 * processes are handled. 1044 */ 1045 spinlock_t lock; 1046 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 1047 }; 1048 1049 struct mlx5_read_counters_attr { 1050 struct mlx5_fc *hw_cntrs_hndl; 1051 u64 *out; 1052 u32 flags; 1053 }; 1054 1055 enum mlx5_ib_counters_type { 1056 MLX5_IB_COUNTERS_FLOW, 1057 }; 1058 1059 struct mlx5_ib_mcounters { 1060 struct ib_counters ibcntrs; 1061 enum mlx5_ib_counters_type type; 1062 /* number of counters supported for this counters type */ 1063 u32 counters_num; 1064 struct mlx5_fc *hw_cntrs_hndl; 1065 /* read function for this counters type */ 1066 int (*read_counters)(struct ib_device *ibdev, 1067 struct mlx5_read_counters_attr *read_attr); 1068 /* max index set as part of create_flow */ 1069 u32 cntrs_max_index; 1070 /* number of counters data entries (<description,index> pair) */ 1071 u32 ncounters; 1072 /* counters data array for descriptions and indexes */ 1073 struct mlx5_ib_flow_counters_desc *counters_data; 1074 /* protects access to mcounters internal data */ 1075 struct mutex mcntrs_mutex; 1076 }; 1077 1078 static inline struct mlx5_ib_mcounters * 1079 to_mcounters(struct ib_counters *ibcntrs) 1080 { 1081 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1082 } 1083 1084 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1085 bool is_egress, 1086 struct mlx5_flow_act *action); 1087 struct mlx5_ib_lb_state { 1088 /* protect the user_td */ 1089 struct mutex mutex; 1090 u32 user_td; 1091 int qps; 1092 bool enabled; 1093 }; 1094 1095 struct mlx5_ib_pf_eq { 1096 struct notifier_block irq_nb; 1097 struct mlx5_ib_dev *dev; 1098 struct mlx5_eq *core; 1099 struct work_struct work; 1100 spinlock_t lock; /* Pagefaults spinlock */ 1101 struct workqueue_struct *wq; 1102 mempool_t *pool; 1103 }; 1104 1105 struct mlx5_devx_event_table { 1106 struct mlx5_nb devx_nb; 1107 /* serialize updating the event_xa */ 1108 struct mutex event_xa_lock; 1109 struct xarray event_xa; 1110 }; 1111 1112 struct mlx5_var_table { 1113 /* serialize updating the bitmap */ 1114 struct mutex bitmap_lock; 1115 unsigned long *bitmap; 1116 u64 hw_start_addr; 1117 u32 stride_size; 1118 u64 num_var_hw_entries; 1119 }; 1120 1121 struct mlx5_port_caps { 1122 bool has_smi; 1123 u8 ext_port_cap; 1124 }; 1125 1126 1127 struct mlx5_special_mkeys { 1128 u32 dump_fill_mkey; 1129 __be32 null_mkey; 1130 __be32 terminate_scatter_list_mkey; 1131 }; 1132 1133 struct mlx5_macsec { 1134 struct mutex lock; /* Protects mlx5_macsec internal contexts */ 1135 struct list_head macsec_devices_list; 1136 struct notifier_block blocking_events_nb; 1137 }; 1138 1139 struct mlx5_ib_dev { 1140 struct ib_device ib_dev; 1141 struct mlx5_core_dev *mdev; 1142 struct mlx5_data_direct_dev *data_direct_dev; 1143 /* protect accessing data_direct_dev */ 1144 struct mutex data_direct_lock; 1145 struct notifier_block mdev_events; 1146 struct notifier_block lag_events; 1147 int num_ports; 1148 /* serialize update of capability mask 1149 */ 1150 struct mutex cap_mask_mutex; 1151 u8 ib_active:1; 1152 u8 is_rep:1; 1153 u8 lag_active:1; 1154 u8 fill_delay; 1155 struct umr_common umrc; 1156 /* sync used page count stats 1157 */ 1158 struct mlx5_ib_resources devr; 1159 1160 atomic_t mkey_var; 1161 struct mlx5_mkey_cache cache; 1162 struct timer_list delay_timer; 1163 /* Prevents soft lock on massive reg MRs */ 1164 struct mutex slow_path_mutex; 1165 struct ib_odp_caps odp_caps; 1166 u64 odp_max_size; 1167 struct mutex odp_eq_mutex; 1168 struct mlx5_ib_pf_eq odp_pf_eq; 1169 1170 struct xarray odp_mkeys; 1171 1172 struct mlx5_ib_flow_db *flow_db; 1173 /* protect resources needed as part of reset flow */ 1174 spinlock_t reset_flow_resource_lock; 1175 struct list_head qp_list; 1176 struct list_head data_direct_mr_list; 1177 /* Array with num_ports elements */ 1178 struct mlx5_ib_port *port; 1179 struct mlx5_sq_bfreg bfreg; 1180 struct mlx5_sq_bfreg fp_bfreg; 1181 struct mlx5_ib_delay_drop delay_drop; 1182 const struct mlx5_ib_profile *profile; 1183 1184 struct mlx5_ib_lb_state lb; 1185 u8 umr_fence; 1186 struct list_head ib_dev_list; 1187 u64 sys_image_guid; 1188 struct mlx5_dm dm; 1189 u16 devx_whitelist_uid; 1190 struct mlx5_srq_table srq_table; 1191 struct mlx5_qp_table qp_table; 1192 struct mlx5_async_ctx async_ctx; 1193 struct mlx5_devx_event_table devx_event_table; 1194 struct mlx5_var_table var_table; 1195 1196 struct xarray sig_mrs; 1197 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1198 u16 pkey_table_len; 1199 u8 lag_ports; 1200 struct mlx5_special_mkeys mkeys; 1201 struct mlx5_data_direct_resources ddr; 1202 1203 #ifdef CONFIG_MLX5_MACSEC 1204 struct mlx5_macsec macsec; 1205 #endif 1206 1207 u8 num_plane; 1208 struct mlx5_ib_dev *smi_dev; 1209 const char *sub_dev_name; 1210 }; 1211 1212 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1213 { 1214 return container_of(mcq, struct mlx5_ib_cq, mcq); 1215 } 1216 1217 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1218 { 1219 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1220 } 1221 1222 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1223 { 1224 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1225 } 1226 1227 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1228 { 1229 return to_mdev(mr->ibmr.device); 1230 } 1231 1232 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1233 { 1234 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1235 udata, struct mlx5_ib_ucontext, ibucontext); 1236 1237 return to_mdev(context->ibucontext.device); 1238 } 1239 1240 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1241 { 1242 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1243 } 1244 1245 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1246 { 1247 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1248 } 1249 1250 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1251 { 1252 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1253 } 1254 1255 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1256 { 1257 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1258 } 1259 1260 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1261 { 1262 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1263 } 1264 1265 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1266 { 1267 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1268 } 1269 1270 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1271 { 1272 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1273 } 1274 1275 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1276 { 1277 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1278 } 1279 1280 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1281 { 1282 return container_of(msrq, struct mlx5_ib_srq, msrq); 1283 } 1284 1285 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1286 { 1287 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1288 } 1289 1290 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1291 { 1292 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1293 } 1294 1295 static inline struct mlx5_ib_flow_action * 1296 to_mflow_act(struct ib_flow_action *ibact) 1297 { 1298 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1299 } 1300 1301 static inline struct mlx5_user_mmap_entry * 1302 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1303 { 1304 return container_of(rdma_entry, 1305 struct mlx5_user_mmap_entry, rdma_entry); 1306 } 1307 1308 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev); 1309 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev); 1310 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1311 struct mlx5_db *db); 1312 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1313 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1314 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1315 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1316 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1317 struct ib_udata *udata); 1318 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1319 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1320 { 1321 return 0; 1322 } 1323 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1324 struct ib_udata *udata); 1325 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1326 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1327 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1328 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1329 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1330 const struct ib_recv_wr **bad_wr); 1331 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1332 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1333 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1334 struct ib_udata *udata); 1335 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1336 int attr_mask, struct ib_udata *udata); 1337 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1338 struct ib_qp_init_attr *qp_init_attr); 1339 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1340 void mlx5_ib_drain_sq(struct ib_qp *qp); 1341 void mlx5_ib_drain_rq(struct ib_qp *qp); 1342 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1343 size_t buflen, size_t *bc); 1344 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1345 size_t buflen, size_t *bc); 1346 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1347 size_t buflen, size_t *bc); 1348 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1349 struct uverbs_attr_bundle *attrs); 1350 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1351 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1352 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1353 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1354 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1355 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1356 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1357 u64 virt_addr, int access_flags, 1358 struct ib_udata *udata); 1359 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1360 u64 length, u64 virt_addr, 1361 int fd, int access_flags, 1362 struct uverbs_attr_bundle *attrs); 1363 int mlx5_ib_advise_mr(struct ib_pd *pd, 1364 enum ib_uverbs_advise_mr_advice advice, 1365 u32 flags, 1366 struct ib_sge *sg_list, 1367 u32 num_sge, 1368 struct uverbs_attr_bundle *attrs); 1369 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1370 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1371 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1372 int access_flags); 1373 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1374 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1375 u64 length, u64 virt_addr, int access_flags, 1376 struct ib_pd *pd, struct ib_udata *udata); 1377 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1378 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1379 u32 max_num_sg); 1380 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1381 u32 max_num_sg, 1382 u32 max_num_meta_sg); 1383 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1384 unsigned int *sg_offset); 1385 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1386 int data_sg_nents, unsigned int *data_sg_offset, 1387 struct scatterlist *meta_sg, int meta_sg_nents, 1388 unsigned int *meta_sg_offset); 1389 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1390 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1391 const struct ib_mad *in, struct ib_mad *out, 1392 size_t *out_mad_size, u16 *out_mad_pkey_index); 1393 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1394 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1395 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1396 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1397 __be64 *sys_image_guid); 1398 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1399 u16 *max_pkeys); 1400 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1401 u32 *vendor_id); 1402 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1403 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1404 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1405 u16 *pkey); 1406 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1407 union ib_gid *gid); 1408 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1409 struct ib_port_attr *props); 1410 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1411 struct ib_port_attr *props); 1412 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1413 u64 access_flags); 1414 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1415 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1416 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1417 struct mlx5_cache_ent * 1418 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 1419 struct mlx5r_cache_rb_key rb_key, 1420 bool persistent_entry); 1421 1422 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1423 int access_flags, int access_mode, 1424 int ndescs); 1425 1426 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1427 struct ib_mr_status *mr_status); 1428 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1429 struct ib_wq_init_attr *init_attr, 1430 struct ib_udata *udata); 1431 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1432 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1433 u32 wq_attr_mask, struct ib_udata *udata); 1434 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1435 struct ib_rwq_ind_table_init_attr *init_attr, 1436 struct ib_udata *udata); 1437 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1438 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1439 struct ib_dm_mr_attr *attr, 1440 struct uverbs_attr_bundle *attrs); 1441 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 1442 struct mlx5_data_direct_dev *dev); 1443 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev); 1444 void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev); 1445 1446 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1447 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1448 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1449 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1450 int __init mlx5_ib_odp_init(void); 1451 void mlx5_ib_odp_cleanup(void); 1452 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1453 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1454 struct mlx5_ib_mr *mr, int flags); 1455 1456 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1457 enum ib_uverbs_advise_mr_advice advice, 1458 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1459 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1460 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1461 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1462 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1463 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1464 struct mlx5_ib_pf_eq *eq) 1465 { 1466 return 0; 1467 } 1468 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1469 static inline int mlx5_ib_odp_init(void) { return 0; } 1470 static inline void mlx5_ib_odp_cleanup(void) {} 1471 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1472 { 1473 return 0; 1474 } 1475 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1476 struct mlx5_ib_mr *mr, int flags) {} 1477 1478 static inline int 1479 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1480 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1481 struct ib_sge *sg_list, u32 num_sge) 1482 { 1483 return -EOPNOTSUPP; 1484 } 1485 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1486 { 1487 return -EOPNOTSUPP; 1488 } 1489 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1490 { 1491 return -EOPNOTSUPP; 1492 } 1493 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1494 1495 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1496 1497 /* Needed for rep profile */ 1498 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1499 const struct mlx5_ib_profile *profile, 1500 int stage); 1501 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1502 const struct mlx5_ib_profile *profile); 1503 1504 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1505 u32 port, struct ifla_vf_info *info); 1506 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1507 u32 port, int state); 1508 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1509 u32 port, struct ifla_vf_stats *stats); 1510 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1511 struct ifla_vf_guid *node_guid, 1512 struct ifla_vf_guid *port_guid); 1513 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1514 u64 guid, int type); 1515 1516 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1517 const struct ib_gid_attr *attr); 1518 1519 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1520 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1521 1522 /* GSI QP helper functions */ 1523 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1524 struct ib_qp_init_attr *attr); 1525 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1526 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1527 int attr_mask); 1528 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1529 int qp_attr_mask, 1530 struct ib_qp_init_attr *qp_init_attr); 1531 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1532 const struct ib_send_wr **bad_wr); 1533 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1534 const struct ib_recv_wr **bad_wr); 1535 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1536 1537 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1538 1539 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1540 int bfregn); 1541 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1542 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1543 u32 ib_port_num, 1544 u32 *native_port_num); 1545 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1546 u32 port_num); 1547 1548 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1549 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1550 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1551 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1552 extern const struct uapi_definition mlx5_ib_create_cq_defs[]; 1553 1554 static inline int is_qp1(enum ib_qp_type qp_type) 1555 { 1556 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1557 } 1558 1559 static inline u32 check_cq_create_flags(u32 flags) 1560 { 1561 /* 1562 * It returns non-zero value for unsupported CQ 1563 * create flags, otherwise it returns zero. 1564 */ 1565 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1566 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1567 } 1568 1569 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1570 u32 *user_index) 1571 { 1572 if (cqe_version) { 1573 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1574 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1575 return -EINVAL; 1576 *user_index = cmd_uidx; 1577 } else { 1578 *user_index = MLX5_IB_DEFAULT_UIDX; 1579 } 1580 1581 return 0; 1582 } 1583 1584 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1585 struct mlx5_ib_create_qp *ucmd, 1586 int inlen, 1587 u32 *user_index) 1588 { 1589 u8 cqe_version = ucontext->cqe_version; 1590 1591 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1592 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1593 return 0; 1594 1595 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1596 return -EINVAL; 1597 1598 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1599 } 1600 1601 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1602 struct mlx5_ib_create_srq *ucmd, 1603 int inlen, 1604 u32 *user_index) 1605 { 1606 u8 cqe_version = ucontext->cqe_version; 1607 1608 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1609 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1610 return 0; 1611 1612 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1613 return -EINVAL; 1614 1615 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1616 } 1617 1618 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1619 { 1620 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1621 MLX5_UARS_IN_PAGE : 1; 1622 } 1623 1624 extern void *xlt_emergency_page; 1625 1626 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1627 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1628 bool dyn_bfreg); 1629 1630 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1631 struct mlx5_ib_mkey *mmkey) 1632 { 1633 refcount_set(&mmkey->usecount, 1); 1634 1635 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1636 mmkey, GFP_KERNEL)); 1637 } 1638 1639 /* deref an mkey that can participate in ODP flow */ 1640 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1641 { 1642 if (refcount_dec_and_test(&mmkey->usecount)) 1643 wake_up(&mmkey->wait); 1644 } 1645 1646 /* deref an mkey that can participate in ODP flow and wait for relese */ 1647 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1648 { 1649 mlx5r_deref_odp_mkey(mmkey); 1650 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1651 } 1652 1653 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1654 { 1655 /* 1656 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1657 * is supported, it means that the driver no longer needs to assign the port 1658 * affinity by default. If a user wants to set the port affinity explicitly, 1659 * the user has a dedicated API to do that, so there is no need to assign 1660 * the port affinity by default. 1661 */ 1662 if (dev->lag_active && 1663 mlx5_lag_mode_is_hash(dev->mdev) && 1664 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1665 return 0; 1666 1667 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1668 return 0; 1669 1670 return dev->lag_active || 1671 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1672 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1673 } 1674 1675 static inline bool rt_supported(int ts_cap) 1676 { 1677 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1678 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1679 } 1680 1681 /* 1682 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1683 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1684 * root complexes. However if a switch is present in the path, then things get 1685 * really ugly depending on how the switch is setup. This table assumes that the 1686 * root complex is strict and is validating that all req/reps are matches 1687 * perfectly - so any scenario where it sees only half the transaction is a 1688 * failure. 1689 * 1690 * CR/RR/DT ATS RO P2P 1691 * 00X X X OK 1692 * 010 X X fails (request is routed to root but root never sees comp) 1693 * 011 0 X fails (request is routed to root but root never sees comp) 1694 * 011 1 X OK 1695 * 10X X 1 OK 1696 * 101 X 0 fails (completion is routed to root but root didn't see req) 1697 * 110 X 0 SLOW 1698 * 111 0 0 SLOW 1699 * 111 1 0 fails (completion is routed to root but root didn't see req) 1700 * 111 1 1 OK 1701 * 1702 * Unfortunately we cannot reliably know if a switch is present or what the 1703 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1704 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1705 * 1706 * For now assume if the umem is a dma_buf then it is P2P. 1707 */ 1708 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1709 struct ib_umem *umem, int access_flags) 1710 { 1711 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1712 return false; 1713 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1714 } 1715 1716 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 1717 unsigned int index, const union ib_gid *gid, 1718 const struct ib_gid_attr *attr); 1719 1720 static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) 1721 { 1722 return (port - 1) / dev->num_ports + 1; 1723 } 1724 1725 /* 1726 * For mkc users, instead of a page_offset the command has a start_iova which 1727 * specifies both the page_offset and the on-the-wire IOVA 1728 */ 1729 static __always_inline unsigned long 1730 mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1731 u64 iova) 1732 { 1733 int page_size_bits = 1734 MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5) ? 6 : 5; 1735 unsigned long bitmap = 1736 __mlx5_log_page_size_to_bitmap(page_size_bits, 0); 1737 1738 return ib_umem_find_best_pgsz(umem, bitmap, iova); 1739 } 1740 1741 #endif /* MLX5_IB_H */ 1742