1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 #include "qp.h" 29 #include "macsec.h" 30 31 #define mlx5_ib_dbg(_dev, format, arg...) \ 32 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 33 __LINE__, current->pid, ##arg) 34 35 #define mlx5_ib_err(_dev, format, arg...) \ 36 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 37 __LINE__, current->pid, ##arg) 38 39 #define mlx5_ib_warn(_dev, format, arg...) \ 40 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 41 __LINE__, current->pid, ##arg) 42 43 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 44 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 45 __func__, __LINE__, current->pid, ##arg) 46 47 #define MLX5_IB_DEFAULT_UIDX 0xffffff 48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 49 50 static __always_inline unsigned long 51 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 52 unsigned int pgsz_shift) 53 { 54 unsigned int largest_pg_shift = 55 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 56 BITS_PER_LONG - 1); 57 58 /* 59 * Despite a command allowing it, the device does not support lower than 60 * 4k page size. 61 */ 62 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 63 return GENMASK(largest_pg_shift, pgsz_shift); 64 } 65 66 static __always_inline unsigned long 67 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 68 unsigned int offset_shift) 69 { 70 unsigned int largest_offset_shift = 71 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 72 BITS_PER_LONG - 1); 73 74 return GENMASK(largest_offset_shift, offset_shift); 75 } 76 77 /* 78 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 79 * page_offset_quantized * (page_size/scale) = page_offset 80 * Which restricts allowed page sizes to ones that satisify the above. 81 */ 82 unsigned long __mlx5_umem_find_best_quantized_pgoff( 83 struct ib_umem *umem, unsigned long pgsz_bitmap, 84 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 85 unsigned int *page_offset_quantized); 86 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 87 pgsz_shift, page_offset_fld, \ 88 scale, page_offset_quantized) \ 89 __mlx5_umem_find_best_quantized_pgoff( \ 90 umem, \ 91 __mlx5_log_page_size_to_bitmap( \ 92 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 93 __mlx5_bit_sz(typ, page_offset_fld), \ 94 GENMASK(31, order_base_2(scale)), scale, \ 95 page_offset_quantized) 96 97 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 98 pgsz_shift, page_offset_fld, \ 99 scale, page_offset_quantized) \ 100 __mlx5_umem_find_best_quantized_pgoff( \ 101 umem, \ 102 __mlx5_log_page_size_to_bitmap( \ 103 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 104 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 105 page_offset_quantized) 106 107 enum { 108 MLX5_IB_MMAP_OFFSET_START = 9, 109 MLX5_IB_MMAP_OFFSET_END = 255, 110 }; 111 112 enum { 113 MLX5_IB_MMAP_CMD_SHIFT = 8, 114 MLX5_IB_MMAP_CMD_MASK = 0xff, 115 }; 116 117 enum { 118 MLX5_RES_SCAT_DATA32_CQE = 0x1, 119 MLX5_RES_SCAT_DATA64_CQE = 0x2, 120 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 121 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 122 }; 123 124 enum mlx5_ib_mad_ifc_flags { 125 MLX5_MAD_IFC_IGNORE_MKEY = 1, 126 MLX5_MAD_IFC_IGNORE_BKEY = 2, 127 MLX5_MAD_IFC_NET_VIEW = 4, 128 }; 129 130 enum { 131 MLX5_CROSS_CHANNEL_BFREG = 0, 132 }; 133 134 enum { 135 MLX5_CQE_VERSION_V0, 136 MLX5_CQE_VERSION_V1, 137 }; 138 139 enum { 140 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 141 MLX5_TM_MAX_SGE = 1, 142 }; 143 144 enum { 145 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 146 MLX5_IB_INVALID_BFREG = BIT(31), 147 }; 148 149 enum { 150 MLX5_MAX_MEMIC_PAGES = 0x100, 151 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 152 }; 153 154 enum { 155 MLX5_MEMIC_BASE_ALIGN = 6, 156 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 157 }; 158 159 enum mlx5_ib_mmap_type { 160 MLX5_IB_MMAP_TYPE_MEMIC = 1, 161 MLX5_IB_MMAP_TYPE_VAR = 2, 162 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 163 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 164 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 165 MLX5_IB_MMAP_TYPE_TLP_VAR = 6, 166 }; 167 168 struct mlx5_bfreg_info { 169 u32 *sys_pages; 170 int num_low_latency_bfregs; 171 unsigned int *count; 172 173 /* 174 * protect bfreg allocation data structs 175 */ 176 struct mutex lock; 177 u32 ver; 178 u8 lib_uar_4k : 1; 179 u8 lib_uar_dyn : 1; 180 u32 num_sys_pages; 181 u32 num_static_sys_pages; 182 u32 total_num_bfregs; 183 u32 num_dyn_bfregs; 184 }; 185 186 struct mlx5_ib_ucontext { 187 struct ib_ucontext ibucontext; 188 struct list_head db_page_list; 189 190 /* protect doorbell record alloc/free 191 */ 192 struct mutex db_page_mutex; 193 struct mlx5_bfreg_info bfregi; 194 u8 cqe_version; 195 /* Transport Domain number */ 196 u32 tdn; 197 198 u64 lib_caps; 199 u16 devx_uid; 200 /* For RoCE LAG TX affinity */ 201 atomic_t tx_port_affinity; 202 }; 203 204 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 205 { 206 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 207 } 208 209 struct mlx5_ib_pd { 210 struct ib_pd ibpd; 211 u32 pdn; 212 u16 uid; 213 }; 214 215 enum { 216 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 217 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 218 MLX5_IB_FLOW_ACTION_DECAP, 219 }; 220 221 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 222 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 223 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 224 #error "Invalid number of bypass priorities" 225 #endif 226 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 227 228 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 229 #define MLX5_IB_NUM_SNIFFER_FTS 2 230 #define MLX5_IB_NUM_EGRESS_FTS 1 231 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 232 233 struct mlx5_ib_anchor { 234 struct mlx5_flow_table *ft; 235 struct mlx5_flow_group *fg_goto_table; 236 struct mlx5_flow_group *fg_drop; 237 struct mlx5_flow_handle *rule_goto_table; 238 struct mlx5_flow_handle *rule_drop; 239 unsigned int rule_goto_table_ref; 240 }; 241 242 struct mlx5_ib_flow_prio { 243 struct mlx5_flow_table *flow_table; 244 struct mlx5_ib_anchor anchor; 245 unsigned int refcount; 246 }; 247 248 struct mlx5_ib_flow_handler { 249 struct list_head list; 250 struct ib_flow ibflow; 251 struct mlx5_ib_flow_prio *prio; 252 struct mlx5_flow_handle *rule; 253 struct ib_counters *ibcounters; 254 struct mlx5_ib_dev *dev; 255 struct mlx5_ib_flow_matcher *flow_matcher; 256 }; 257 258 struct mlx5_ib_flow_matcher { 259 struct mlx5_ib_match_params matcher_mask; 260 int mask_len; 261 enum mlx5_ib_flow_type flow_type; 262 enum mlx5_flow_namespace_type ns_type; 263 u16 priority; 264 struct mlx5_core_dev *mdev; 265 atomic_t usecnt; 266 u8 match_criteria_enable; 267 u32 ib_port; 268 }; 269 270 struct mlx5_ib_steering_anchor { 271 struct mlx5_ib_flow_prio *ft_prio; 272 struct mlx5_ib_dev *dev; 273 atomic_t usecnt; 274 }; 275 276 struct mlx5_ib_pp { 277 u16 index; 278 struct mlx5_core_dev *mdev; 279 }; 280 281 enum mlx5_ib_optional_counter_type { 282 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 283 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 284 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 285 MLX5_IB_OPCOUNTER_RDMA_TX_PACKETS, 286 MLX5_IB_OPCOUNTER_RDMA_TX_BYTES, 287 MLX5_IB_OPCOUNTER_RDMA_RX_PACKETS, 288 MLX5_IB_OPCOUNTER_RDMA_RX_BYTES, 289 290 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS_PER_QP, 291 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS_PER_QP, 292 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS_PER_QP, 293 MLX5_IB_OPCOUNTER_RDMA_TX_PACKETS_PER_QP, 294 MLX5_IB_OPCOUNTER_RDMA_TX_BYTES_PER_QP, 295 MLX5_IB_OPCOUNTER_RDMA_RX_PACKETS_PER_QP, 296 MLX5_IB_OPCOUNTER_RDMA_RX_BYTES_PER_QP, 297 298 MLX5_IB_OPCOUNTER_MAX, 299 }; 300 301 struct mlx5_ib_flow_db { 302 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 303 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 304 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 305 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 306 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 307 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 308 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 309 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 310 struct mlx5_ib_flow_prio *rdma_transport_rx[MLX5_RDMA_TRANSPORT_BYPASS_PRIO]; 311 struct mlx5_ib_flow_prio *rdma_transport_tx[MLX5_RDMA_TRANSPORT_BYPASS_PRIO]; 312 /* Protect flow steering bypass flow tables 313 * when add/del flow rules. 314 * only single add/removal of flow steering rule could be done 315 * simultaneously. 316 */ 317 struct mutex lock; 318 }; 319 320 /* Use macros here so that don't have to duplicate 321 * enum ib_qp_type for low-level driver 322 */ 323 324 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 325 /* 326 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 327 * creates the actual hardware QP. 328 */ 329 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 330 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 331 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 332 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 333 334 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 335 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 336 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 337 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 338 #define MLX5_IB_UPD_XLT_PD BIT(4) 339 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 340 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 341 #define MLX5_IB_UPD_XLT_DOWNGRADE BIT(7) 342 #define MLX5_IB_UPD_XLT_KEEP_PGSZ BIT(8) 343 344 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 345 * 346 * These flags are intended for internal use by the mlx5_ib driver, and they 347 * rely on the range reserved for that use in the ib_qp_create_flags enum. 348 */ 349 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 350 351 struct wr_list { 352 u16 opcode; 353 u16 next; 354 }; 355 356 enum mlx5_ib_rq_flags { 357 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 358 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 359 }; 360 361 struct mlx5_ib_wq { 362 struct mlx5_frag_buf_ctrl fbc; 363 u64 *wrid; 364 u32 *wr_data; 365 struct wr_list *w_list; 366 unsigned *wqe_head; 367 u16 unsig_count; 368 369 /* serialize post to the work queue 370 */ 371 spinlock_t lock; 372 int wqe_cnt; 373 int max_post; 374 int max_gs; 375 int offset; 376 int wqe_shift; 377 unsigned head; 378 unsigned tail; 379 u16 cur_post; 380 u16 last_poll; 381 void *cur_edge; 382 }; 383 384 enum mlx5_ib_wq_flags { 385 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 386 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 387 }; 388 389 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 390 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 391 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 392 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 393 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 394 395 struct mlx5_ib_rwq { 396 struct ib_wq ibwq; 397 struct mlx5_core_qp core_qp; 398 u32 rq_num_pas; 399 u32 log_rq_stride; 400 u32 log_rq_size; 401 u32 rq_page_offset; 402 u32 log_page_size; 403 u32 log_num_strides; 404 u32 two_byte_shift_en; 405 u32 single_stride_log_num_of_bytes; 406 struct ib_umem *umem; 407 size_t buf_size; 408 unsigned int page_shift; 409 struct mlx5_db db; 410 u32 user_index; 411 u32 wqe_count; 412 u32 wqe_shift; 413 int wq_sig; 414 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 415 }; 416 417 struct mlx5_ib_rwq_ind_table { 418 struct ib_rwq_ind_table ib_rwq_ind_tbl; 419 u32 rqtn; 420 u16 uid; 421 }; 422 423 struct mlx5_ib_ubuffer { 424 struct ib_umem *umem; 425 int buf_size; 426 u64 buf_addr; 427 }; 428 429 struct mlx5_ib_qp_base { 430 struct mlx5_ib_qp *container_mibqp; 431 struct mlx5_core_qp mqp; 432 struct mlx5_ib_ubuffer ubuffer; 433 }; 434 435 struct mlx5_ib_qp_trans { 436 struct mlx5_ib_qp_base base; 437 u16 xrcdn; 438 u32 alt_port; 439 u8 atomic_rd_en; 440 u8 resp_depth; 441 }; 442 443 struct mlx5_ib_rss_qp { 444 u32 tirn; 445 }; 446 447 struct mlx5_ib_rq { 448 struct mlx5_ib_qp_base base; 449 struct mlx5_ib_wq *rq; 450 struct mlx5_ib_ubuffer ubuffer; 451 struct mlx5_db *doorbell; 452 u32 tirn; 453 u8 state; 454 u32 flags; 455 }; 456 457 struct mlx5_ib_sq { 458 struct mlx5_ib_qp_base base; 459 struct mlx5_ib_wq *sq; 460 struct mlx5_ib_ubuffer ubuffer; 461 struct mlx5_db *doorbell; 462 struct mlx5_flow_handle *flow_rule; 463 u32 tisn; 464 u8 state; 465 }; 466 467 struct mlx5_ib_raw_packet_qp { 468 struct mlx5_ib_sq sq; 469 struct mlx5_ib_rq rq; 470 }; 471 472 struct mlx5_bf { 473 int buf_size; 474 unsigned long offset; 475 struct mlx5_sq_bfreg *bfreg; 476 }; 477 478 struct mlx5_ib_dct { 479 struct mlx5_core_dct mdct; 480 u32 *in; 481 }; 482 483 struct mlx5_ib_gsi_qp { 484 struct ib_qp *rx_qp; 485 u32 port_num; 486 struct ib_qp_cap cap; 487 struct ib_cq *cq; 488 struct mlx5_ib_gsi_wr *outstanding_wrs; 489 u32 outstanding_pi, outstanding_ci; 490 int num_qps; 491 /* Protects access to the tx_qps. Post send operations synchronize 492 * with tx_qp creation in setup_qp(). Also protects the 493 * outstanding_wrs array and indices. 494 */ 495 spinlock_t lock; 496 struct ib_qp **tx_qps; 497 }; 498 499 struct mlx5_ib_qp { 500 struct ib_qp ibqp; 501 union { 502 struct mlx5_ib_qp_trans trans_qp; 503 struct mlx5_ib_raw_packet_qp raw_packet_qp; 504 struct mlx5_ib_rss_qp rss_qp; 505 struct mlx5_ib_dct dct; 506 struct mlx5_ib_gsi_qp gsi; 507 }; 508 struct mlx5_frag_buf buf; 509 510 struct mlx5_db db; 511 struct mlx5_ib_wq rq; 512 513 u8 sq_signal_bits; 514 u8 next_fence; 515 struct mlx5_ib_wq sq; 516 517 /* serialize qp state modifications 518 */ 519 struct mutex mutex; 520 /* cached variant of create_flags from struct ib_qp_init_attr */ 521 u32 flags; 522 u32 port; 523 u8 state; 524 int max_inline_data; 525 struct mlx5_bf bf; 526 u8 has_rq:1; 527 u8 is_rss:1; 528 u8 is_ooo_rq:1; 529 530 /* only for user space QPs. For kernel 531 * we have it from the bf object 532 */ 533 int bfregn; 534 535 struct list_head qps_list; 536 struct list_head cq_recv_list; 537 struct list_head cq_send_list; 538 struct mlx5_rate_limit rl; 539 u32 underlay_qpn; 540 u32 flags_en; 541 /* 542 * IB/core doesn't store low-level QP types, so 543 * store both MLX and IBTA types in the field below. 544 */ 545 enum ib_qp_type type; 546 /* A flag to indicate if there's a new counter is configured 547 * but not take effective 548 */ 549 u32 counter_pending; 550 u16 gsi_lag_port; 551 }; 552 553 struct mlx5_ib_cq_buf { 554 struct mlx5_frag_buf_ctrl fbc; 555 struct mlx5_frag_buf frag_buf; 556 struct ib_umem *umem; 557 int cqe_size; 558 int nent; 559 }; 560 561 enum mlx5_ib_cq_pr_flags { 562 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 563 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 564 MLX5_IB_CQ_PR_TIMESTAMP_COMPLETION = 1 << 2, 565 }; 566 567 struct mlx5_ib_cq { 568 struct ib_cq ibcq; 569 struct mlx5_core_cq mcq; 570 struct mlx5_ib_cq_buf buf; 571 struct mlx5_db db; 572 573 /* serialize access to the CQ 574 */ 575 spinlock_t lock; 576 577 /* protect resize cq 578 */ 579 struct mutex resize_mutex; 580 struct mlx5_ib_cq_buf *resize_buf; 581 struct ib_umem *resize_umem; 582 int cqe_size; 583 struct list_head list_send_qp; 584 struct list_head list_recv_qp; 585 struct list_head wc_list; 586 enum ib_cq_notify_flags notify_flags; 587 struct work_struct notify_work; 588 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 589 }; 590 591 struct mlx5_ib_wc { 592 struct ib_wc wc; 593 struct list_head list; 594 }; 595 596 struct mlx5_ib_srq { 597 struct ib_srq ibsrq; 598 struct mlx5_core_srq msrq; 599 struct mlx5_frag_buf buf; 600 struct mlx5_db db; 601 struct mlx5_frag_buf_ctrl fbc; 602 u64 *wrid; 603 /* protect SRQ hanlding 604 */ 605 spinlock_t lock; 606 int head; 607 int tail; 608 u16 wqe_ctr; 609 struct ib_umem *umem; 610 /* serialize arming a SRQ 611 */ 612 struct mutex mutex; 613 int wq_sig; 614 }; 615 616 struct mlx5_ib_xrcd { 617 struct ib_xrcd ibxrcd; 618 u32 xrcdn; 619 }; 620 621 enum mlx5_ib_mtt_access_flags { 622 MLX5_IB_MTT_READ = (1 << 0), 623 MLX5_IB_MTT_WRITE = (1 << 1), 624 }; 625 626 struct mlx5_user_mmap_entry { 627 struct rdma_user_mmap_entry rdma_entry; 628 u8 mmap_flag; 629 u64 address; 630 u32 page_idx; 631 }; 632 633 enum mlx5_mkey_type { 634 MLX5_MKEY_MR = 1, 635 MLX5_MKEY_MW, 636 MLX5_MKEY_INDIRECT_DEVX, 637 MLX5_MKEY_NULL, 638 MLX5_MKEY_IMPLICIT_CHILD, 639 }; 640 641 /* Used for non-existent ph value */ 642 #define MLX5_IB_NO_PH 0xff 643 644 struct mlx5_ib_mkey { 645 u32 key; 646 enum mlx5_mkey_type type; 647 unsigned int ndescs; 648 struct wait_queue_head wait; 649 refcount_t usecount; 650 }; 651 652 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 653 654 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 655 IB_ACCESS_REMOTE_WRITE |\ 656 IB_ACCESS_REMOTE_READ |\ 657 IB_ACCESS_REMOTE_ATOMIC |\ 658 IB_ZERO_BASED) 659 660 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 661 IB_ACCESS_REMOTE_WRITE |\ 662 IB_ACCESS_REMOTE_READ |\ 663 IB_ZERO_BASED) 664 665 #define mlx5_update_odp_stats(mr, counter_name, value) \ 666 atomic64_add(value, &((mr)->odp_stats.counter_name)) 667 668 #define mlx5_update_odp_stats_with_handled(mr, counter_name, value) \ 669 do { \ 670 mlx5_update_odp_stats(mr, counter_name, value); \ 671 atomic64_add(1, &((mr)->odp_stats.counter_name##_handled)); \ 672 } while (0) 673 674 struct mlx5_ib_mr { 675 struct ib_mr ibmr; 676 struct mlx5_ib_mkey mmkey; 677 678 struct ib_umem *umem; 679 /* The mr is data direct related */ 680 u8 data_direct :1; 681 682 union { 683 /* Used only by kernel MRs (umem == NULL) */ 684 struct { 685 void *descs; 686 void *descs_alloc; 687 dma_addr_t desc_map; 688 int max_descs; 689 int desc_size; 690 int access_mode; 691 692 /* For Kernel IB_MR_TYPE_INTEGRITY */ 693 struct mlx5_core_sig_ctx *sig; 694 struct mlx5_ib_mr *pi_mr; 695 struct mlx5_ib_mr *klm_mr; 696 struct mlx5_ib_mr *mtt_mr; 697 u64 data_iova; 698 u64 pi_iova; 699 int meta_ndescs; 700 int meta_length; 701 int data_length; 702 }; 703 704 /* Used only by User MRs (umem != NULL) */ 705 struct { 706 unsigned int page_shift; 707 /* Current access_flags */ 708 int access_flags; 709 710 /* For User ODP */ 711 struct mlx5_ib_mr *parent; 712 struct xarray implicit_children; 713 union { 714 struct work_struct work; 715 } odp_destroy; 716 struct ib_odp_counters odp_stats; 717 bool is_odp_implicit; 718 /* The affilated data direct crossed mr */ 719 struct mlx5_ib_mr *dd_crossed_mr; 720 struct list_head dd_node; 721 u8 revoked :1; 722 /* Indicates previous dmabuf page fault occurred */ 723 u8 dmabuf_faulted:1; 724 struct mlx5_ib_mkey null_mmkey; 725 }; 726 }; 727 }; 728 729 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 730 { 731 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 732 mr->umem->is_odp; 733 } 734 735 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 736 { 737 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 738 mr->umem->is_dmabuf; 739 } 740 741 struct mlx5_ib_mw { 742 struct ib_mw ibmw; 743 struct mlx5_ib_mkey mmkey; 744 }; 745 746 struct mlx5_ib_umr_context { 747 struct ib_cqe cqe; 748 enum ib_wc_status status; 749 struct completion done; 750 }; 751 752 enum { 753 MLX5_UMR_STATE_UNINIT, 754 MLX5_UMR_STATE_ACTIVE, 755 MLX5_UMR_STATE_RECOVER, 756 MLX5_UMR_STATE_ERR, 757 }; 758 759 struct umr_common { 760 struct ib_pd *pd; 761 struct ib_cq *cq; 762 struct ib_qp *qp; 763 /* Protects from UMR QP overflow 764 */ 765 struct semaphore sem; 766 /* Protects from using UMR while the UMR is not active 767 */ 768 struct mutex lock; 769 unsigned int state; 770 /* Protects from repeat UMR QP creation */ 771 struct mutex init_lock; 772 }; 773 774 struct mlx5_ib_port_resources { 775 struct mlx5_ib_gsi_qp *gsi; 776 struct work_struct pkey_change_work; 777 }; 778 779 struct mlx5_data_direct_resources { 780 u32 pdn; 781 u32 mkey; 782 u32 mkey_ro; 783 u8 mkey_ro_valid :1; 784 }; 785 786 struct mlx5_ib_resources { 787 struct ib_cq *c0; 788 struct mutex cq_lock; 789 u32 xrcdn0; 790 u32 xrcdn1; 791 struct ib_pd *p0; 792 struct ib_srq *s0; 793 struct ib_srq *s1; 794 struct mutex srq_lock; 795 struct mlx5_ib_port_resources ports[2]; 796 }; 797 798 #define MAX_OPFC_RULES 2 799 800 struct mlx5_ib_op_fc { 801 struct mlx5_fc *fc; 802 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 803 }; 804 805 struct mlx5_ib_counters { 806 struct rdma_stat_desc *descs; 807 size_t *offsets; 808 u32 num_q_counters; 809 u32 num_cong_counters; 810 u32 num_ext_ppcnt_counters; 811 u32 num_op_counters; 812 u16 set_id; 813 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 814 }; 815 816 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 817 struct mlx5_ib_op_fc *opfc, 818 enum mlx5_ib_optional_counter_type type); 819 820 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 821 struct mlx5_ib_op_fc *opfc, 822 enum mlx5_ib_optional_counter_type type); 823 824 int mlx5r_fs_bind_op_fc(struct ib_qp *qp, 825 struct mlx5_fc *fc_arr[MLX5_IB_OPCOUNTER_MAX], 826 struct xarray *qpn_opfc_xa, u32 port); 827 828 void mlx5r_fs_unbind_op_fc(struct ib_qp *qp, struct xarray *qpn_opfc_xa); 829 830 void mlx5r_fs_destroy_fcs(struct mlx5_ib_dev *dev, 831 struct mlx5_fc *fc_arr[MLX5_IB_OPCOUNTER_MAX]); 832 833 struct mlx5_ib_multiport_info; 834 835 struct mlx5_ib_multiport { 836 struct mlx5_ib_multiport_info *mpi; 837 /* To be held when accessing the multiport info */ 838 spinlock_t mpi_lock; 839 }; 840 841 struct mlx5_roce { 842 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 843 * netdev pointer 844 */ 845 struct notifier_block nb; 846 struct netdev_net_notifier nn; 847 struct notifier_block mdev_nb; 848 struct net_device *tracking_netdev; 849 atomic_t tx_port_affinity; 850 enum ib_port_state last_port_state; 851 struct mlx5_ib_dev *dev; 852 u32 native_port_num; 853 }; 854 855 struct mlx5_ib_port { 856 struct mlx5_ib_counters cnts; 857 struct mlx5_ib_multiport mp; 858 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 859 struct mlx5_roce roce; 860 struct mlx5_eswitch_rep *rep; 861 #ifdef CONFIG_MLX5_MACSEC 862 struct mlx5_reserved_gids *reserved_gids; 863 #endif 864 }; 865 866 struct mlx5_ib_dbg_param { 867 int offset; 868 struct mlx5_ib_dev *dev; 869 struct dentry *dentry; 870 u32 port_num; 871 }; 872 873 enum mlx5_ib_dbg_cc_types { 874 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 875 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 876 MLX5_IB_DBG_CC_RP_TIME_RESET, 877 MLX5_IB_DBG_CC_RP_BYTE_RESET, 878 MLX5_IB_DBG_CC_RP_THRESHOLD, 879 MLX5_IB_DBG_CC_RP_AI_RATE, 880 MLX5_IB_DBG_CC_RP_MAX_RATE, 881 MLX5_IB_DBG_CC_RP_HAI_RATE, 882 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 883 MLX5_IB_DBG_CC_RP_MIN_RATE, 884 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 885 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 886 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 887 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 888 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 889 MLX5_IB_DBG_CC_RP_GD, 890 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 891 MLX5_IB_DBG_CC_NP_CNP_DSCP, 892 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 893 MLX5_IB_DBG_CC_NP_CNP_PRIO, 894 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 895 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 896 MLX5_IB_DBG_CC_MAX, 897 }; 898 899 struct mlx5_ib_dbg_cc_params { 900 struct dentry *root; 901 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 902 }; 903 904 enum { 905 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 906 }; 907 908 struct mlx5_ib_delay_drop { 909 struct mlx5_ib_dev *dev; 910 struct work_struct delay_drop_work; 911 /* serialize setting of delay drop */ 912 struct mutex lock; 913 u32 timeout; 914 bool activate; 915 atomic_t events_cnt; 916 atomic_t rqs_cnt; 917 struct dentry *dir_debugfs; 918 }; 919 920 enum mlx5_ib_stages { 921 MLX5_IB_STAGE_INIT, 922 MLX5_IB_STAGE_FS, 923 MLX5_IB_STAGE_CAPS, 924 MLX5_IB_STAGE_NON_DEFAULT_CB, 925 MLX5_IB_STAGE_ROCE, 926 MLX5_IB_STAGE_QP, 927 MLX5_IB_STAGE_SRQ, 928 MLX5_IB_STAGE_DEVICE_RESOURCES, 929 MLX5_IB_STAGE_ODP, 930 MLX5_IB_STAGE_COUNTERS, 931 MLX5_IB_STAGE_CONG_DEBUGFS, 932 MLX5_IB_STAGE_BFREG, 933 MLX5_IB_STAGE_PRE_IB_REG_UMR, 934 MLX5_IB_STAGE_WHITELIST_UID, 935 MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 936 MLX5_IB_STAGE_IB_REG, 937 MLX5_IB_STAGE_DEVICE_NOTIFIER, 938 MLX5_IB_STAGE_POST_IB_REG_UMR, 939 MLX5_IB_STAGE_DELAY_DROP, 940 MLX5_IB_STAGE_RESTRACK, 941 MLX5_IB_STAGE_MAX, 942 }; 943 944 struct mlx5_ib_stage { 945 int (*init)(struct mlx5_ib_dev *dev); 946 void (*cleanup)(struct mlx5_ib_dev *dev); 947 }; 948 949 #define STAGE_CREATE(_stage, _init, _cleanup) \ 950 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 951 952 struct mlx5_ib_profile { 953 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 954 }; 955 956 struct mlx5_ib_multiport_info { 957 struct list_head list; 958 struct mlx5_ib_dev *ibdev; 959 struct mlx5_core_dev *mdev; 960 struct notifier_block mdev_events; 961 struct completion unref_comp; 962 u64 sys_image_guid; 963 u32 mdev_refcnt; 964 bool is_master; 965 bool unaffiliate; 966 }; 967 968 struct mlx5_ib_flow_action { 969 struct ib_flow_action ib_action; 970 union { 971 struct { 972 u64 ib_flags; 973 struct mlx5_accel_esp_xfrm *ctx; 974 } esp_aes_gcm; 975 struct { 976 struct mlx5_ib_dev *dev; 977 u32 sub_type; 978 union { 979 struct mlx5_modify_hdr *modify_hdr; 980 struct mlx5_pkt_reformat *pkt_reformat; 981 }; 982 } flow_action_raw; 983 }; 984 }; 985 986 struct mlx5_dm { 987 struct mlx5_core_dev *dev; 988 /* This lock is used to protect the access to the shared 989 * allocation map when concurrent requests by different 990 * processes are handled. 991 */ 992 spinlock_t lock; 993 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 994 }; 995 996 struct mlx5_read_counters_attr { 997 struct mlx5_fc *hw_cntrs_hndl; 998 u64 *out; 999 u32 flags; 1000 }; 1001 1002 enum mlx5_ib_counters_type { 1003 MLX5_IB_COUNTERS_FLOW, 1004 }; 1005 1006 struct mlx5_ib_mcounters { 1007 struct ib_counters ibcntrs; 1008 enum mlx5_ib_counters_type type; 1009 /* number of counters supported for this counters type */ 1010 u32 counters_num; 1011 struct mlx5_fc *hw_cntrs_hndl; 1012 /* read function for this counters type */ 1013 int (*read_counters)(struct ib_device *ibdev, 1014 struct mlx5_read_counters_attr *read_attr); 1015 /* max index set as part of create_flow */ 1016 u32 cntrs_max_index; 1017 /* number of counters data entries (<description,index> pair) */ 1018 u32 ncounters; 1019 /* counters data array for descriptions and indexes */ 1020 struct mlx5_ib_flow_counters_desc *counters_data; 1021 /* protects access to mcounters internal data */ 1022 struct mutex mcntrs_mutex; 1023 }; 1024 1025 static inline struct mlx5_ib_mcounters * 1026 to_mcounters(struct ib_counters *ibcntrs) 1027 { 1028 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1029 } 1030 1031 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1032 bool is_egress, 1033 struct mlx5_flow_act *action); 1034 struct mlx5_ib_lb_state { 1035 /* protect the user_td */ 1036 struct mutex mutex; 1037 u32 user_td; 1038 int qps; 1039 bool enabled; 1040 bool force_enable; 1041 }; 1042 1043 struct mlx5_ib_pf_eq { 1044 struct notifier_block irq_nb; 1045 struct mlx5_ib_dev *dev; 1046 struct mlx5_eq *core; 1047 struct work_struct work; 1048 spinlock_t lock; /* Pagefaults spinlock */ 1049 struct workqueue_struct *wq; 1050 mempool_t *pool; 1051 }; 1052 1053 struct mlx5_devx_event_table { 1054 struct mlx5_nb devx_nb; 1055 /* serialize updating the event_xa */ 1056 struct mutex event_xa_lock; 1057 struct xarray event_xa; 1058 }; 1059 1060 struct mlx5_var_region { 1061 /* serialize updating the bitmap */ 1062 struct mutex bitmap_lock; 1063 unsigned long *bitmap; 1064 u64 hw_start_addr; 1065 u32 stride_size; 1066 u64 num_var_hw_entries; 1067 }; 1068 1069 struct mlx5_var_table { 1070 struct mlx5_var_region var_region; 1071 struct mlx5_var_region tlp_var_region; 1072 }; 1073 1074 struct mlx5_port_caps { 1075 bool has_smi; 1076 u8 ext_port_cap; 1077 }; 1078 1079 1080 struct mlx5_special_mkeys { 1081 u32 dump_fill_mkey; 1082 __be32 null_mkey; 1083 __be32 terminate_scatter_list_mkey; 1084 }; 1085 1086 struct mlx5_macsec { 1087 struct mutex lock; /* Protects mlx5_macsec internal contexts */ 1088 struct list_head macsec_devices_list; 1089 struct notifier_block blocking_events_nb; 1090 }; 1091 1092 struct mlx5_ib_dev { 1093 struct ib_device ib_dev; 1094 struct mlx5_core_dev *mdev; 1095 struct mlx5_data_direct_dev *data_direct_dev; 1096 /* protect accessing data_direct_dev */ 1097 struct mutex data_direct_lock; 1098 struct notifier_block mdev_events; 1099 struct notifier_block sys_error_events; 1100 struct notifier_block lag_events; 1101 int num_ports; 1102 /* serialize update of capability mask 1103 */ 1104 struct mutex cap_mask_mutex; 1105 u8 ib_active:1; 1106 u8 is_rep:1; 1107 u8 lag_active:1; 1108 u8 fill_delay; 1109 struct umr_common umrc; 1110 /* sync used page count stats 1111 */ 1112 struct mlx5_ib_resources devr; 1113 1114 atomic_t mkey_var; 1115 /* Prevents soft lock on massive reg MRs */ 1116 struct mutex slow_path_mutex; 1117 struct ib_odp_caps odp_caps; 1118 u64 odp_max_size; 1119 struct mutex odp_eq_mutex; 1120 struct mlx5_ib_pf_eq odp_pf_eq; 1121 1122 struct xarray odp_mkeys; 1123 1124 struct mlx5_ib_flow_db *flow_db; 1125 /* protect resources needed as part of reset flow */ 1126 spinlock_t reset_flow_resource_lock; 1127 struct list_head qp_list; 1128 struct list_head data_direct_mr_list; 1129 /* Array with num_ports elements */ 1130 struct mlx5_ib_port *port; 1131 struct mlx5_sq_bfreg bfreg; 1132 struct mlx5_sq_bfreg fp_bfreg; 1133 struct mlx5_ib_delay_drop delay_drop; 1134 const struct mlx5_ib_profile *profile; 1135 1136 struct mlx5_ib_lb_state lb; 1137 u8 umr_fence; 1138 struct list_head ib_dev_list; 1139 u64 sys_image_guid; 1140 struct mlx5_dm dm; 1141 u16 devx_whitelist_uid; 1142 struct mlx5_srq_table srq_table; 1143 struct mlx5_qp_table qp_table; 1144 struct mlx5_async_ctx async_ctx; 1145 struct mlx5_devx_event_table devx_event_table; 1146 struct mlx5_var_table var_table; 1147 1148 struct xarray sig_mrs; 1149 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1150 u16 pkey_table_len; 1151 u8 lag_ports; 1152 struct mlx5_special_mkeys mkeys; 1153 struct mlx5_data_direct_resources ddr; 1154 1155 #ifdef CONFIG_MLX5_MACSEC 1156 struct mlx5_macsec macsec; 1157 #endif 1158 1159 u8 num_plane; 1160 struct mlx5_ib_dev *smi_dev; 1161 const char *sub_dev_name; 1162 }; 1163 1164 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1165 { 1166 return container_of(mcq, struct mlx5_ib_cq, mcq); 1167 } 1168 1169 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1170 { 1171 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1172 } 1173 1174 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1175 { 1176 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1177 } 1178 1179 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1180 { 1181 return to_mdev(mr->ibmr.device); 1182 } 1183 1184 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1185 { 1186 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1187 udata, struct mlx5_ib_ucontext, ibucontext); 1188 1189 return to_mdev(context->ibucontext.device); 1190 } 1191 1192 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1193 { 1194 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1195 } 1196 1197 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1198 { 1199 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1200 } 1201 1202 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1203 { 1204 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1205 } 1206 1207 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1208 { 1209 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1210 } 1211 1212 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1213 { 1214 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1215 } 1216 1217 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1218 { 1219 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1220 } 1221 1222 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1223 { 1224 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1225 } 1226 1227 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1228 { 1229 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1230 } 1231 1232 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1233 { 1234 return container_of(msrq, struct mlx5_ib_srq, msrq); 1235 } 1236 1237 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1238 { 1239 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1240 } 1241 1242 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1243 { 1244 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1245 } 1246 1247 static inline struct mlx5_ib_flow_action * 1248 to_mflow_act(struct ib_flow_action *ibact) 1249 { 1250 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1251 } 1252 1253 static inline struct mlx5_user_mmap_entry * 1254 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1255 { 1256 return container_of(rdma_entry, 1257 struct mlx5_user_mmap_entry, rdma_entry); 1258 } 1259 1260 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev); 1261 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev); 1262 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1263 struct mlx5_db *db); 1264 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1265 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1266 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1267 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1268 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1269 struct ib_udata *udata); 1270 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1271 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1272 { 1273 return 0; 1274 } 1275 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1276 struct ib_udata *udata); 1277 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1278 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1279 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1280 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1281 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1282 const struct ib_recv_wr **bad_wr); 1283 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1284 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1285 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1286 struct ib_udata *udata); 1287 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1288 int attr_mask, struct ib_udata *udata); 1289 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1290 struct ib_qp_init_attr *qp_init_attr); 1291 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1292 void mlx5_ib_drain_sq(struct ib_qp *qp); 1293 void mlx5_ib_drain_rq(struct ib_qp *qp); 1294 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1295 size_t buflen, size_t *bc); 1296 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1297 size_t buflen, size_t *bc); 1298 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1299 size_t buflen, size_t *bc); 1300 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1301 struct uverbs_attr_bundle *attrs); 1302 int mlx5_ib_create_user_cq(struct ib_cq *ibcq, 1303 const struct ib_cq_init_attr *attr, 1304 struct uverbs_attr_bundle *attrs); 1305 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1306 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1307 int mlx5_ib_pre_destroy_cq(struct ib_cq *cq); 1308 void mlx5_ib_post_destroy_cq(struct ib_cq *cq); 1309 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1310 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1311 int mlx5_ib_resize_cq(struct ib_cq *ibcq, unsigned int entries, 1312 struct ib_udata *udata); 1313 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1314 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1315 u64 virt_addr, int access_flags, 1316 struct ib_dmah *dmah, 1317 struct ib_udata *udata); 1318 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1319 u64 length, u64 virt_addr, 1320 int fd, int access_flags, 1321 struct ib_dmah *dmah, 1322 struct uverbs_attr_bundle *attrs); 1323 int mlx5_ib_advise_mr(struct ib_pd *pd, 1324 enum ib_uverbs_advise_mr_advice advice, 1325 u32 flags, 1326 struct ib_sge *sg_list, 1327 u32 num_sge, 1328 struct uverbs_attr_bundle *attrs); 1329 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1330 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1331 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1332 int access_flags); 1333 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1334 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1335 u64 length, u64 virt_addr, int access_flags, 1336 struct ib_pd *pd, struct ib_udata *udata); 1337 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1338 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1339 u32 max_num_sg); 1340 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1341 u32 max_num_sg, 1342 u32 max_num_meta_sg); 1343 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1344 unsigned int *sg_offset); 1345 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1346 int data_sg_nents, unsigned int *data_sg_offset, 1347 struct scatterlist *meta_sg, int meta_sg_nents, 1348 unsigned int *meta_sg_offset); 1349 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1350 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1351 const struct ib_mad *in, struct ib_mad *out, 1352 size_t *out_mad_size, u16 *out_mad_pkey_index); 1353 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1354 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1355 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1356 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1357 __be64 *sys_image_guid); 1358 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1359 u16 *max_pkeys); 1360 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1361 u32 *vendor_id); 1362 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1363 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1364 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1365 u16 *pkey); 1366 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1367 union ib_gid *gid); 1368 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1369 struct ib_port_attr *props); 1370 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1371 struct ib_port_attr *props); 1372 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, 1373 u64 *speed); 1374 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1375 u64 access_flags); 1376 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1377 int mlx5r_frmr_pools_init(struct ib_device *device); 1378 void mlx5r_frmr_pools_cleanup(struct ib_device *device); 1379 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1380 int access_flags, int access_mode, 1381 int ndescs); 1382 1383 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1384 struct ib_mr_status *mr_status); 1385 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1386 struct ib_wq_init_attr *init_attr, 1387 struct ib_udata *udata); 1388 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1389 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1390 u32 wq_attr_mask, struct ib_udata *udata); 1391 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1392 struct ib_rwq_ind_table_init_attr *init_attr, 1393 struct ib_udata *udata); 1394 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1395 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1396 struct ib_dm_mr_attr *attr, 1397 struct uverbs_attr_bundle *attrs); 1398 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 1399 struct mlx5_data_direct_dev *dev); 1400 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev); 1401 void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev); 1402 1403 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1404 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1405 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1406 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1407 int __init mlx5_ib_odp_init(void); 1408 void mlx5_ib_odp_cleanup(void); 1409 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1410 int mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1411 struct mlx5_ib_mr *mr, int flags); 1412 1413 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1414 enum ib_uverbs_advise_mr_advice advice, 1415 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1416 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1417 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1418 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1419 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1420 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1421 struct mlx5_ib_pf_eq *eq) 1422 { 1423 return 0; 1424 } 1425 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1426 static inline int mlx5_ib_odp_init(void) { return 0; } 1427 static inline void mlx5_ib_odp_cleanup(void) {} 1428 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1429 { 1430 return 0; 1431 } 1432 static inline int mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1433 struct mlx5_ib_mr *mr, int flags) 1434 { 1435 return -EOPNOTSUPP; 1436 } 1437 1438 static inline int 1439 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1440 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1441 struct ib_sge *sg_list, u32 num_sge) 1442 { 1443 return -EOPNOTSUPP; 1444 } 1445 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1446 { 1447 return -EOPNOTSUPP; 1448 } 1449 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1450 { 1451 return -EOPNOTSUPP; 1452 } 1453 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1454 1455 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1456 1457 /* Needed for rep profile */ 1458 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1459 const struct mlx5_ib_profile *profile, 1460 int stage); 1461 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1462 const struct mlx5_ib_profile *profile); 1463 1464 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1465 u32 port, struct ifla_vf_info *info); 1466 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1467 u32 port, int state); 1468 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1469 u32 port, struct ifla_vf_stats *stats); 1470 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1471 struct ifla_vf_guid *node_guid, 1472 struct ifla_vf_guid *port_guid); 1473 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1474 u64 guid, int type); 1475 1476 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1477 const struct ib_gid_attr *attr); 1478 1479 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1480 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1481 1482 /* GSI QP helper functions */ 1483 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1484 struct ib_qp_init_attr *attr); 1485 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1486 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1487 int attr_mask); 1488 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1489 int qp_attr_mask, 1490 struct ib_qp_init_attr *qp_init_attr); 1491 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1492 const struct ib_send_wr **bad_wr); 1493 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1494 const struct ib_recv_wr **bad_wr); 1495 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1496 1497 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1498 1499 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1500 int bfregn); 1501 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1502 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1503 u32 ib_port_num, 1504 u32 *native_port_num); 1505 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1506 u32 port_num); 1507 1508 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1509 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1510 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1511 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1512 extern const struct uapi_definition mlx5_ib_create_cq_defs[]; 1513 1514 static inline int is_qp1(enum ib_qp_type qp_type) 1515 { 1516 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1517 } 1518 1519 static inline u32 check_cq_create_flags(u32 flags) 1520 { 1521 /* 1522 * It returns non-zero value for unsupported CQ 1523 * create flags, otherwise it returns zero. 1524 */ 1525 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1526 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1527 } 1528 1529 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1530 u32 *user_index) 1531 { 1532 if (cqe_version) { 1533 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1534 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1535 return -EINVAL; 1536 *user_index = cmd_uidx; 1537 } else { 1538 *user_index = MLX5_IB_DEFAULT_UIDX; 1539 } 1540 1541 return 0; 1542 } 1543 1544 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1545 struct mlx5_ib_create_qp *ucmd, 1546 int inlen, 1547 u32 *user_index) 1548 { 1549 u8 cqe_version = ucontext->cqe_version; 1550 1551 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1552 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1553 return 0; 1554 1555 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1556 return -EINVAL; 1557 1558 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1559 } 1560 1561 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1562 struct mlx5_ib_create_srq *ucmd, 1563 int inlen, 1564 u32 *user_index) 1565 { 1566 u8 cqe_version = ucontext->cqe_version; 1567 1568 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1569 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1570 return 0; 1571 1572 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1573 return -EINVAL; 1574 1575 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1576 } 1577 1578 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1579 { 1580 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1581 MLX5_UARS_IN_PAGE : 1; 1582 } 1583 1584 extern void *xlt_emergency_page; 1585 1586 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1587 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1588 bool dyn_bfreg); 1589 1590 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1591 struct mlx5_ib_mkey *mmkey) 1592 { 1593 refcount_set(&mmkey->usecount, 1); 1594 1595 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1596 mmkey, GFP_KERNEL)); 1597 } 1598 1599 /* deref an mkey that can participate in ODP flow */ 1600 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1601 { 1602 if (refcount_dec_and_test(&mmkey->usecount)) 1603 wake_up(&mmkey->wait); 1604 } 1605 1606 /* deref an mkey that can participate in ODP flow and wait for relese */ 1607 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1608 { 1609 mlx5r_deref_odp_mkey(mmkey); 1610 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1611 } 1612 1613 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1614 { 1615 /* 1616 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1617 * is supported, it means that the driver no longer needs to assign the port 1618 * affinity by default. If a user wants to set the port affinity explicitly, 1619 * the user has a dedicated API to do that, so there is no need to assign 1620 * the port affinity by default. 1621 */ 1622 if (dev->lag_active && 1623 mlx5_lag_mode_is_hash(dev->mdev) && 1624 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1625 return 0; 1626 1627 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1628 return 0; 1629 1630 return dev->lag_active || 1631 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1632 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1633 } 1634 1635 static inline bool rt_supported(int ts_cap) 1636 { 1637 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1638 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1639 } 1640 1641 /* 1642 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1643 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1644 * root complexes. However if a switch is present in the path, then things get 1645 * really ugly depending on how the switch is setup. This table assumes that the 1646 * root complex is strict and is validating that all req/reps are matches 1647 * perfectly - so any scenario where it sees only half the transaction is a 1648 * failure. 1649 * 1650 * CR/RR/DT ATS RO P2P 1651 * 00X X X OK 1652 * 010 X X fails (request is routed to root but root never sees comp) 1653 * 011 0 X fails (request is routed to root but root never sees comp) 1654 * 011 1 X OK 1655 * 10X X 1 OK 1656 * 101 X 0 fails (completion is routed to root but root didn't see req) 1657 * 110 X 0 SLOW 1658 * 111 0 0 SLOW 1659 * 111 1 0 fails (completion is routed to root but root didn't see req) 1660 * 111 1 1 OK 1661 * 1662 * Unfortunately we cannot reliably know if a switch is present or what the 1663 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1664 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1665 * 1666 * For now assume if the umem is a dma_buf then it is P2P. 1667 */ 1668 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1669 struct ib_umem *umem, int access_flags) 1670 { 1671 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1672 return false; 1673 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1674 } 1675 1676 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 1677 unsigned int index, const union ib_gid *gid, 1678 const struct ib_gid_attr *attr); 1679 1680 static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) 1681 { 1682 return (port - 1) / dev->num_ports + 1; 1683 } 1684 1685 static inline unsigned int get_max_log_entity_size_cap(struct mlx5_ib_dev *dev, 1686 int access_mode) 1687 { 1688 int max_log_size = 0; 1689 1690 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT) 1691 max_log_size = 1692 MLX5_CAP_GEN_2(dev->mdev, max_mkey_log_entity_size_mtt); 1693 else if (access_mode == MLX5_MKC_ACCESS_MODE_KSM) 1694 max_log_size = MLX5_CAP_GEN_2( 1695 dev->mdev, max_mkey_log_entity_size_fixed_buffer); 1696 1697 if (!max_log_size || 1698 (max_log_size > 31 && 1699 !MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5))) 1700 max_log_size = 31; 1701 1702 return max_log_size; 1703 } 1704 1705 static inline unsigned int get_min_log_entity_size_cap(struct mlx5_ib_dev *dev, 1706 int access_mode) 1707 { 1708 int min_log_size = 0; 1709 1710 if (access_mode == MLX5_MKC_ACCESS_MODE_KSM && 1711 MLX5_CAP_GEN_2(dev->mdev, 1712 min_mkey_log_entity_size_fixed_buffer_valid)) 1713 min_log_size = MLX5_CAP_GEN_2( 1714 dev->mdev, min_mkey_log_entity_size_fixed_buffer); 1715 else 1716 min_log_size = 1717 MLX5_CAP_GEN_2(dev->mdev, log_min_mkey_entity_size); 1718 1719 min_log_size = max(min_log_size, MLX5_ADAPTER_PAGE_SHIFT); 1720 return min_log_size; 1721 } 1722 1723 /* 1724 * For mkc users, instead of a page_offset the command has a start_iova which 1725 * specifies both the page_offset and the on-the-wire IOVA 1726 */ 1727 static __always_inline unsigned long 1728 mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1729 u64 iova, int access_mode) 1730 { 1731 unsigned int max_log_entity_size_cap, min_log_entity_size_cap; 1732 unsigned long bitmap; 1733 1734 max_log_entity_size_cap = get_max_log_entity_size_cap(dev, access_mode); 1735 min_log_entity_size_cap = get_min_log_entity_size_cap(dev, access_mode); 1736 1737 bitmap = GENMASK_ULL(max_log_entity_size_cap, min_log_entity_size_cap); 1738 1739 /* In KSM mode HW requires IOVA and mkey's page size to be aligned */ 1740 if (access_mode == MLX5_MKC_ACCESS_MODE_KSM && iova) 1741 bitmap &= GENMASK_ULL(__ffs64(iova), 0); 1742 1743 return ib_umem_find_best_pgsz(umem, bitmap, iova); 1744 } 1745 1746 static inline unsigned long 1747 mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf, 1748 int access_mode) 1749 { 1750 return mlx5_umem_mkc_find_best_pgsz(to_mdev(umem_dmabuf->umem.ibdev), 1751 &umem_dmabuf->umem, 1752 umem_dmabuf->umem.iova, 1753 access_mode); 1754 } 1755 1756 #endif /* MLX5_IB_H */ 1757