1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 29 #define mlx5_ib_dbg(_dev, format, arg...) \ 30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 31 __LINE__, current->pid, ##arg) 32 33 #define mlx5_ib_err(_dev, format, arg...) \ 34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 35 __LINE__, current->pid, ##arg) 36 37 #define mlx5_ib_warn(_dev, format, arg...) \ 38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 39 __LINE__, current->pid, ##arg) 40 41 #define MLX5_IB_DEFAULT_UIDX 0xffffff 42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 43 44 static __always_inline unsigned long 45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 46 unsigned int pgsz_shift) 47 { 48 unsigned int largest_pg_shift = 49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 50 BITS_PER_LONG - 1); 51 52 /* 53 * Despite a command allowing it, the device does not support lower than 54 * 4k page size. 55 */ 56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 57 return GENMASK(largest_pg_shift, pgsz_shift); 58 } 59 60 /* 61 * For mkc users, instead of a page_offset the command has a start_iova which 62 * specifies both the page_offset and the on-the-wire IOVA 63 */ 64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 65 ib_umem_find_best_pgsz(umem, \ 66 __mlx5_log_page_size_to_bitmap( \ 67 __mlx5_bit_sz(typ, log_pgsz_fld), \ 68 pgsz_shift), \ 69 iova) 70 71 static __always_inline unsigned long 72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 73 unsigned int offset_shift) 74 { 75 unsigned int largest_offset_shift = 76 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 77 BITS_PER_LONG - 1); 78 79 return GENMASK(largest_offset_shift, offset_shift); 80 } 81 82 /* 83 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 84 * page_offset_quantized * (page_size/scale) = page_offset 85 * Which restricts allowed page sizes to ones that satisify the above. 86 */ 87 unsigned long __mlx5_umem_find_best_quantized_pgoff( 88 struct ib_umem *umem, unsigned long pgsz_bitmap, 89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 90 unsigned int *page_offset_quantized); 91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 92 pgsz_shift, page_offset_fld, \ 93 scale, page_offset_quantized) \ 94 __mlx5_umem_find_best_quantized_pgoff( \ 95 umem, \ 96 __mlx5_log_page_size_to_bitmap( \ 97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 98 __mlx5_bit_sz(typ, page_offset_fld), \ 99 GENMASK(31, order_base_2(scale)), scale, \ 100 page_offset_quantized) 101 102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 103 pgsz_shift, page_offset_fld, \ 104 scale, page_offset_quantized) \ 105 __mlx5_umem_find_best_quantized_pgoff( \ 106 umem, \ 107 __mlx5_log_page_size_to_bitmap( \ 108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 110 page_offset_quantized) 111 112 enum { 113 MLX5_IB_MMAP_OFFSET_START = 9, 114 MLX5_IB_MMAP_OFFSET_END = 255, 115 }; 116 117 enum { 118 MLX5_IB_MMAP_CMD_SHIFT = 8, 119 MLX5_IB_MMAP_CMD_MASK = 0xff, 120 }; 121 122 enum { 123 MLX5_RES_SCAT_DATA32_CQE = 0x1, 124 MLX5_RES_SCAT_DATA64_CQE = 0x2, 125 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 126 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 127 }; 128 129 enum mlx5_ib_mad_ifc_flags { 130 MLX5_MAD_IFC_IGNORE_MKEY = 1, 131 MLX5_MAD_IFC_IGNORE_BKEY = 2, 132 MLX5_MAD_IFC_NET_VIEW = 4, 133 }; 134 135 enum { 136 MLX5_CROSS_CHANNEL_BFREG = 0, 137 }; 138 139 enum { 140 MLX5_CQE_VERSION_V0, 141 MLX5_CQE_VERSION_V1, 142 }; 143 144 enum { 145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 146 MLX5_TM_MAX_SGE = 1, 147 }; 148 149 enum { 150 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 151 MLX5_IB_INVALID_BFREG = BIT(31), 152 }; 153 154 enum { 155 MLX5_MAX_MEMIC_PAGES = 0x100, 156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 157 }; 158 159 enum { 160 MLX5_MEMIC_BASE_ALIGN = 6, 161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 162 }; 163 164 enum mlx5_ib_mmap_type { 165 MLX5_IB_MMAP_TYPE_MEMIC = 1, 166 MLX5_IB_MMAP_TYPE_VAR = 2, 167 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 168 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 169 }; 170 171 struct mlx5_bfreg_info { 172 u32 *sys_pages; 173 int num_low_latency_bfregs; 174 unsigned int *count; 175 176 /* 177 * protect bfreg allocation data structs 178 */ 179 struct mutex lock; 180 u32 ver; 181 u8 lib_uar_4k : 1; 182 u8 lib_uar_dyn : 1; 183 u32 num_sys_pages; 184 u32 num_static_sys_pages; 185 u32 total_num_bfregs; 186 u32 num_dyn_bfregs; 187 }; 188 189 struct mlx5_ib_ucontext { 190 struct ib_ucontext ibucontext; 191 struct list_head db_page_list; 192 193 /* protect doorbell record alloc/free 194 */ 195 struct mutex db_page_mutex; 196 struct mlx5_bfreg_info bfregi; 197 u8 cqe_version; 198 /* Transport Domain number */ 199 u32 tdn; 200 201 u64 lib_caps; 202 u16 devx_uid; 203 /* For RoCE LAG TX affinity */ 204 atomic_t tx_port_affinity; 205 }; 206 207 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 208 { 209 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 210 } 211 212 struct mlx5_ib_pd { 213 struct ib_pd ibpd; 214 u32 pdn; 215 u16 uid; 216 }; 217 218 enum { 219 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 220 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 221 MLX5_IB_FLOW_ACTION_DECAP, 222 }; 223 224 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 225 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 226 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 227 #error "Invalid number of bypass priorities" 228 #endif 229 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 230 231 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 232 #define MLX5_IB_NUM_SNIFFER_FTS 2 233 #define MLX5_IB_NUM_EGRESS_FTS 1 234 struct mlx5_ib_flow_prio { 235 struct mlx5_flow_table *flow_table; 236 unsigned int refcount; 237 }; 238 239 struct mlx5_ib_flow_handler { 240 struct list_head list; 241 struct ib_flow ibflow; 242 struct mlx5_ib_flow_prio *prio; 243 struct mlx5_flow_handle *rule; 244 struct ib_counters *ibcounters; 245 struct mlx5_ib_dev *dev; 246 struct mlx5_ib_flow_matcher *flow_matcher; 247 }; 248 249 struct mlx5_ib_flow_matcher { 250 struct mlx5_ib_match_params matcher_mask; 251 int mask_len; 252 enum mlx5_ib_flow_type flow_type; 253 enum mlx5_flow_namespace_type ns_type; 254 u16 priority; 255 struct mlx5_core_dev *mdev; 256 atomic_t usecnt; 257 u8 match_criteria_enable; 258 }; 259 260 struct mlx5_ib_pp { 261 u16 index; 262 struct mlx5_core_dev *mdev; 263 }; 264 265 struct mlx5_ib_flow_db { 266 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 267 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 268 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 269 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 270 struct mlx5_ib_flow_prio fdb; 271 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 272 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 273 struct mlx5_flow_table *lag_demux_ft; 274 /* Protect flow steering bypass flow tables 275 * when add/del flow rules. 276 * only single add/removal of flow steering rule could be done 277 * simultaneously. 278 */ 279 struct mutex lock; 280 }; 281 282 /* Use macros here so that don't have to duplicate 283 * enum ib_send_flags and enum ib_qp_type for low-level driver 284 */ 285 286 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 287 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 288 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 289 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 290 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 291 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 292 293 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 294 /* 295 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 296 * creates the actual hardware QP. 297 */ 298 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 299 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 300 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 301 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 302 303 #define MLX5_IB_UMR_OCTOWORD 16 304 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 305 306 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 307 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 308 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 309 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 310 #define MLX5_IB_UPD_XLT_PD BIT(4) 311 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 312 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 313 314 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 315 * 316 * These flags are intended for internal use by the mlx5_ib driver, and they 317 * rely on the range reserved for that use in the ib_qp_create_flags enum. 318 */ 319 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 320 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 321 322 struct wr_list { 323 u16 opcode; 324 u16 next; 325 }; 326 327 enum mlx5_ib_rq_flags { 328 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 329 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 330 }; 331 332 struct mlx5_ib_wq { 333 struct mlx5_frag_buf_ctrl fbc; 334 u64 *wrid; 335 u32 *wr_data; 336 struct wr_list *w_list; 337 unsigned *wqe_head; 338 u16 unsig_count; 339 340 /* serialize post to the work queue 341 */ 342 spinlock_t lock; 343 int wqe_cnt; 344 int max_post; 345 int max_gs; 346 int offset; 347 int wqe_shift; 348 unsigned head; 349 unsigned tail; 350 u16 cur_post; 351 u16 last_poll; 352 void *cur_edge; 353 }; 354 355 enum mlx5_ib_wq_flags { 356 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 357 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 358 }; 359 360 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 361 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 362 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 363 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 364 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 365 366 struct mlx5_ib_rwq { 367 struct ib_wq ibwq; 368 struct mlx5_core_qp core_qp; 369 u32 rq_num_pas; 370 u32 log_rq_stride; 371 u32 log_rq_size; 372 u32 rq_page_offset; 373 u32 log_page_size; 374 u32 log_num_strides; 375 u32 two_byte_shift_en; 376 u32 single_stride_log_num_of_bytes; 377 struct ib_umem *umem; 378 size_t buf_size; 379 unsigned int page_shift; 380 struct mlx5_db db; 381 u32 user_index; 382 u32 wqe_count; 383 u32 wqe_shift; 384 int wq_sig; 385 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 386 }; 387 388 struct mlx5_ib_rwq_ind_table { 389 struct ib_rwq_ind_table ib_rwq_ind_tbl; 390 u32 rqtn; 391 u16 uid; 392 }; 393 394 struct mlx5_ib_ubuffer { 395 struct ib_umem *umem; 396 int buf_size; 397 u64 buf_addr; 398 }; 399 400 struct mlx5_ib_qp_base { 401 struct mlx5_ib_qp *container_mibqp; 402 struct mlx5_core_qp mqp; 403 struct mlx5_ib_ubuffer ubuffer; 404 }; 405 406 struct mlx5_ib_qp_trans { 407 struct mlx5_ib_qp_base base; 408 u16 xrcdn; 409 u8 alt_port; 410 u8 atomic_rd_en; 411 u8 resp_depth; 412 }; 413 414 struct mlx5_ib_rss_qp { 415 u32 tirn; 416 }; 417 418 struct mlx5_ib_rq { 419 struct mlx5_ib_qp_base base; 420 struct mlx5_ib_wq *rq; 421 struct mlx5_ib_ubuffer ubuffer; 422 struct mlx5_db *doorbell; 423 u32 tirn; 424 u8 state; 425 u32 flags; 426 }; 427 428 struct mlx5_ib_sq { 429 struct mlx5_ib_qp_base base; 430 struct mlx5_ib_wq *sq; 431 struct mlx5_ib_ubuffer ubuffer; 432 struct mlx5_db *doorbell; 433 struct mlx5_flow_handle *flow_rule; 434 u32 tisn; 435 u8 state; 436 }; 437 438 struct mlx5_ib_raw_packet_qp { 439 struct mlx5_ib_sq sq; 440 struct mlx5_ib_rq rq; 441 }; 442 443 struct mlx5_bf { 444 int buf_size; 445 unsigned long offset; 446 struct mlx5_sq_bfreg *bfreg; 447 }; 448 449 struct mlx5_ib_dct { 450 struct mlx5_core_dct mdct; 451 u32 *in; 452 }; 453 454 struct mlx5_ib_gsi_qp { 455 struct ib_qp *rx_qp; 456 u8 port_num; 457 struct ib_qp_cap cap; 458 struct ib_cq *cq; 459 struct mlx5_ib_gsi_wr *outstanding_wrs; 460 u32 outstanding_pi, outstanding_ci; 461 int num_qps; 462 /* Protects access to the tx_qps. Post send operations synchronize 463 * with tx_qp creation in setup_qp(). Also protects the 464 * outstanding_wrs array and indices. 465 */ 466 spinlock_t lock; 467 struct ib_qp **tx_qps; 468 }; 469 470 struct mlx5_ib_qp { 471 struct ib_qp ibqp; 472 union { 473 struct mlx5_ib_qp_trans trans_qp; 474 struct mlx5_ib_raw_packet_qp raw_packet_qp; 475 struct mlx5_ib_rss_qp rss_qp; 476 struct mlx5_ib_dct dct; 477 struct mlx5_ib_gsi_qp gsi; 478 }; 479 struct mlx5_frag_buf buf; 480 481 struct mlx5_db db; 482 struct mlx5_ib_wq rq; 483 484 u8 sq_signal_bits; 485 u8 next_fence; 486 struct mlx5_ib_wq sq; 487 488 /* serialize qp state modifications 489 */ 490 struct mutex mutex; 491 /* cached variant of create_flags from struct ib_qp_init_attr */ 492 u32 flags; 493 u8 port; 494 u8 state; 495 int max_inline_data; 496 struct mlx5_bf bf; 497 u8 has_rq:1; 498 u8 is_rss:1; 499 500 /* only for user space QPs. For kernel 501 * we have it from the bf object 502 */ 503 int bfregn; 504 505 struct list_head qps_list; 506 struct list_head cq_recv_list; 507 struct list_head cq_send_list; 508 struct mlx5_rate_limit rl; 509 u32 underlay_qpn; 510 u32 flags_en; 511 /* 512 * IB/core doesn't store low-level QP types, so 513 * store both MLX and IBTA types in the field below. 514 * IB_QPT_DRIVER will be break to DCI/DCT subtypes. 515 */ 516 enum ib_qp_type type; 517 /* A flag to indicate if there's a new counter is configured 518 * but not take effective 519 */ 520 u32 counter_pending; 521 u16 gsi_lag_port; 522 }; 523 524 struct mlx5_ib_cq_buf { 525 struct mlx5_frag_buf_ctrl fbc; 526 struct mlx5_frag_buf frag_buf; 527 struct ib_umem *umem; 528 int cqe_size; 529 int nent; 530 }; 531 532 struct mlx5_umr_wr { 533 struct ib_send_wr wr; 534 u64 virt_addr; 535 u64 offset; 536 struct ib_pd *pd; 537 unsigned int page_shift; 538 unsigned int xlt_size; 539 u64 length; 540 int access_flags; 541 u32 mkey; 542 u8 ignore_free_state:1; 543 }; 544 545 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 546 { 547 return container_of(wr, struct mlx5_umr_wr, wr); 548 } 549 550 struct mlx5_shared_mr_info { 551 int mr_id; 552 struct ib_umem *umem; 553 }; 554 555 enum mlx5_ib_cq_pr_flags { 556 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 557 }; 558 559 struct mlx5_ib_cq { 560 struct ib_cq ibcq; 561 struct mlx5_core_cq mcq; 562 struct mlx5_ib_cq_buf buf; 563 struct mlx5_db db; 564 565 /* serialize access to the CQ 566 */ 567 spinlock_t lock; 568 569 /* protect resize cq 570 */ 571 struct mutex resize_mutex; 572 struct mlx5_ib_cq_buf *resize_buf; 573 struct ib_umem *resize_umem; 574 int cqe_size; 575 struct list_head list_send_qp; 576 struct list_head list_recv_qp; 577 u32 create_flags; 578 struct list_head wc_list; 579 enum ib_cq_notify_flags notify_flags; 580 struct work_struct notify_work; 581 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 582 }; 583 584 struct mlx5_ib_wc { 585 struct ib_wc wc; 586 struct list_head list; 587 }; 588 589 struct mlx5_ib_srq { 590 struct ib_srq ibsrq; 591 struct mlx5_core_srq msrq; 592 struct mlx5_frag_buf buf; 593 struct mlx5_db db; 594 struct mlx5_frag_buf_ctrl fbc; 595 u64 *wrid; 596 /* protect SRQ hanlding 597 */ 598 spinlock_t lock; 599 int head; 600 int tail; 601 u16 wqe_ctr; 602 struct ib_umem *umem; 603 /* serialize arming a SRQ 604 */ 605 struct mutex mutex; 606 int wq_sig; 607 }; 608 609 struct mlx5_ib_xrcd { 610 struct ib_xrcd ibxrcd; 611 u32 xrcdn; 612 }; 613 614 enum mlx5_ib_mtt_access_flags { 615 MLX5_IB_MTT_READ = (1 << 0), 616 MLX5_IB_MTT_WRITE = (1 << 1), 617 }; 618 619 struct mlx5_user_mmap_entry { 620 struct rdma_user_mmap_entry rdma_entry; 621 u8 mmap_flag; 622 u64 address; 623 u32 page_idx; 624 }; 625 626 struct mlx5_ib_dm { 627 struct ib_dm ibdm; 628 phys_addr_t dev_addr; 629 u32 type; 630 size_t size; 631 union { 632 struct { 633 u32 obj_id; 634 } icm_dm; 635 /* other dm types specific params should be added here */ 636 }; 637 struct mlx5_user_mmap_entry mentry; 638 }; 639 640 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 641 642 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 643 IB_ACCESS_REMOTE_WRITE |\ 644 IB_ACCESS_REMOTE_READ |\ 645 IB_ACCESS_REMOTE_ATOMIC |\ 646 IB_ZERO_BASED) 647 648 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 649 IB_ACCESS_REMOTE_WRITE |\ 650 IB_ACCESS_REMOTE_READ |\ 651 IB_ZERO_BASED) 652 653 #define mlx5_update_odp_stats(mr, counter_name, value) \ 654 atomic64_add(value, &((mr)->odp_stats.counter_name)) 655 656 struct mlx5_ib_mr { 657 struct ib_mr ibmr; 658 void *descs; 659 dma_addr_t desc_map; 660 int ndescs; 661 int data_length; 662 int meta_ndescs; 663 int meta_length; 664 int max_descs; 665 int desc_size; 666 int access_mode; 667 unsigned int page_shift; 668 struct mlx5_core_mkey mmkey; 669 struct ib_umem *umem; 670 struct mlx5_shared_mr_info *smr_info; 671 struct list_head list; 672 struct mlx5_cache_ent *cache_ent; 673 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 674 struct mlx5_core_sig_ctx *sig; 675 void *descs_alloc; 676 int access_flags; /* Needed for rereg MR */ 677 678 struct mlx5_ib_mr *parent; 679 /* Needed for IB_MR_TYPE_INTEGRITY */ 680 struct mlx5_ib_mr *pi_mr; 681 struct mlx5_ib_mr *klm_mr; 682 struct mlx5_ib_mr *mtt_mr; 683 u64 data_iova; 684 u64 pi_iova; 685 686 /* For ODP and implicit */ 687 struct xarray implicit_children; 688 union { 689 struct list_head elm; 690 struct work_struct work; 691 } odp_destroy; 692 struct ib_odp_counters odp_stats; 693 bool is_odp_implicit; 694 695 struct mlx5_async_work cb_work; 696 }; 697 698 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 699 { 700 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 701 mr->umem->is_odp; 702 } 703 704 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 705 { 706 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 707 mr->umem->is_dmabuf; 708 } 709 710 struct mlx5_ib_mw { 711 struct ib_mw ibmw; 712 struct mlx5_core_mkey mmkey; 713 int ndescs; 714 }; 715 716 struct mlx5_ib_devx_mr { 717 struct mlx5_core_mkey mmkey; 718 int ndescs; 719 }; 720 721 struct mlx5_ib_umr_context { 722 struct ib_cqe cqe; 723 enum ib_wc_status status; 724 struct completion done; 725 }; 726 727 struct umr_common { 728 struct ib_pd *pd; 729 struct ib_cq *cq; 730 struct ib_qp *qp; 731 /* control access to UMR QP 732 */ 733 struct semaphore sem; 734 }; 735 736 struct mlx5_cache_ent { 737 struct list_head head; 738 /* sync access to the cahce entry 739 */ 740 spinlock_t lock; 741 742 743 char name[4]; 744 u32 order; 745 u32 xlt; 746 u32 access_mode; 747 u32 page; 748 749 u8 disabled:1; 750 u8 fill_to_high_water:1; 751 752 /* 753 * - available_mrs is the length of list head, ie the number of MRs 754 * available for immediate allocation. 755 * - total_mrs is available_mrs plus all in use MRs that could be 756 * returned to the cache. 757 * - limit is the low water mark for available_mrs, 2* limit is the 758 * upper water mark. 759 * - pending is the number of MRs currently being created 760 */ 761 u32 total_mrs; 762 u32 available_mrs; 763 u32 limit; 764 u32 pending; 765 766 /* Statistics */ 767 u32 miss; 768 769 struct mlx5_ib_dev *dev; 770 struct work_struct work; 771 struct delayed_work dwork; 772 }; 773 774 struct mlx5_mr_cache { 775 struct workqueue_struct *wq; 776 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 777 struct dentry *root; 778 unsigned long last_add; 779 }; 780 781 struct mlx5_ib_port_resources { 782 struct mlx5_ib_gsi_qp *gsi; 783 struct work_struct pkey_change_work; 784 }; 785 786 struct mlx5_ib_resources { 787 struct ib_cq *c0; 788 u32 xrcdn0; 789 u32 xrcdn1; 790 struct ib_pd *p0; 791 struct ib_srq *s0; 792 struct ib_srq *s1; 793 struct mlx5_ib_port_resources ports[2]; 794 /* Protects changes to the port resources */ 795 struct mutex mutex; 796 }; 797 798 struct mlx5_ib_counters { 799 const char **names; 800 size_t *offsets; 801 u32 num_q_counters; 802 u32 num_cong_counters; 803 u32 num_ext_ppcnt_counters; 804 u16 set_id; 805 }; 806 807 struct mlx5_ib_multiport_info; 808 809 struct mlx5_ib_multiport { 810 struct mlx5_ib_multiport_info *mpi; 811 /* To be held when accessing the multiport info */ 812 spinlock_t mpi_lock; 813 }; 814 815 struct mlx5_roce { 816 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 817 * netdev pointer 818 */ 819 rwlock_t netdev_lock; 820 struct net_device *netdev; 821 struct notifier_block nb; 822 atomic_t tx_port_affinity; 823 enum ib_port_state last_port_state; 824 struct mlx5_ib_dev *dev; 825 u8 native_port_num; 826 }; 827 828 struct mlx5_ib_port { 829 struct mlx5_ib_counters cnts; 830 struct mlx5_ib_multiport mp; 831 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 832 struct mlx5_roce roce; 833 struct mlx5_eswitch_rep *rep; 834 }; 835 836 struct mlx5_ib_dbg_param { 837 int offset; 838 struct mlx5_ib_dev *dev; 839 struct dentry *dentry; 840 u8 port_num; 841 }; 842 843 enum mlx5_ib_dbg_cc_types { 844 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 845 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 846 MLX5_IB_DBG_CC_RP_TIME_RESET, 847 MLX5_IB_DBG_CC_RP_BYTE_RESET, 848 MLX5_IB_DBG_CC_RP_THRESHOLD, 849 MLX5_IB_DBG_CC_RP_AI_RATE, 850 MLX5_IB_DBG_CC_RP_MAX_RATE, 851 MLX5_IB_DBG_CC_RP_HAI_RATE, 852 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 853 MLX5_IB_DBG_CC_RP_MIN_RATE, 854 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 855 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 856 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 857 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 858 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 859 MLX5_IB_DBG_CC_RP_GD, 860 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 861 MLX5_IB_DBG_CC_NP_CNP_DSCP, 862 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 863 MLX5_IB_DBG_CC_NP_CNP_PRIO, 864 MLX5_IB_DBG_CC_MAX, 865 }; 866 867 struct mlx5_ib_dbg_cc_params { 868 struct dentry *root; 869 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 870 }; 871 872 enum { 873 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 874 }; 875 876 struct mlx5_ib_delay_drop { 877 struct mlx5_ib_dev *dev; 878 struct work_struct delay_drop_work; 879 /* serialize setting of delay drop */ 880 struct mutex lock; 881 u32 timeout; 882 bool activate; 883 atomic_t events_cnt; 884 atomic_t rqs_cnt; 885 struct dentry *dir_debugfs; 886 }; 887 888 enum mlx5_ib_stages { 889 MLX5_IB_STAGE_INIT, 890 MLX5_IB_STAGE_FS, 891 MLX5_IB_STAGE_CAPS, 892 MLX5_IB_STAGE_NON_DEFAULT_CB, 893 MLX5_IB_STAGE_ROCE, 894 MLX5_IB_STAGE_QP, 895 MLX5_IB_STAGE_SRQ, 896 MLX5_IB_STAGE_DEVICE_RESOURCES, 897 MLX5_IB_STAGE_DEVICE_NOTIFIER, 898 MLX5_IB_STAGE_ODP, 899 MLX5_IB_STAGE_COUNTERS, 900 MLX5_IB_STAGE_CONG_DEBUGFS, 901 MLX5_IB_STAGE_UAR, 902 MLX5_IB_STAGE_BFREG, 903 MLX5_IB_STAGE_PRE_IB_REG_UMR, 904 MLX5_IB_STAGE_WHITELIST_UID, 905 MLX5_IB_STAGE_IB_REG, 906 MLX5_IB_STAGE_POST_IB_REG_UMR, 907 MLX5_IB_STAGE_DELAY_DROP, 908 MLX5_IB_STAGE_RESTRACK, 909 MLX5_IB_STAGE_MAX, 910 }; 911 912 struct mlx5_ib_stage { 913 int (*init)(struct mlx5_ib_dev *dev); 914 void (*cleanup)(struct mlx5_ib_dev *dev); 915 }; 916 917 #define STAGE_CREATE(_stage, _init, _cleanup) \ 918 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 919 920 struct mlx5_ib_profile { 921 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 922 }; 923 924 struct mlx5_ib_multiport_info { 925 struct list_head list; 926 struct mlx5_ib_dev *ibdev; 927 struct mlx5_core_dev *mdev; 928 struct notifier_block mdev_events; 929 struct completion unref_comp; 930 u64 sys_image_guid; 931 u32 mdev_refcnt; 932 bool is_master; 933 bool unaffiliate; 934 }; 935 936 struct mlx5_ib_flow_action { 937 struct ib_flow_action ib_action; 938 union { 939 struct { 940 u64 ib_flags; 941 struct mlx5_accel_esp_xfrm *ctx; 942 } esp_aes_gcm; 943 struct { 944 struct mlx5_ib_dev *dev; 945 u32 sub_type; 946 union { 947 struct mlx5_modify_hdr *modify_hdr; 948 struct mlx5_pkt_reformat *pkt_reformat; 949 }; 950 } flow_action_raw; 951 }; 952 }; 953 954 struct mlx5_dm { 955 struct mlx5_core_dev *dev; 956 /* This lock is used to protect the access to the shared 957 * allocation map when concurrent requests by different 958 * processes are handled. 959 */ 960 spinlock_t lock; 961 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 962 }; 963 964 struct mlx5_read_counters_attr { 965 struct mlx5_fc *hw_cntrs_hndl; 966 u64 *out; 967 u32 flags; 968 }; 969 970 enum mlx5_ib_counters_type { 971 MLX5_IB_COUNTERS_FLOW, 972 }; 973 974 struct mlx5_ib_mcounters { 975 struct ib_counters ibcntrs; 976 enum mlx5_ib_counters_type type; 977 /* number of counters supported for this counters type */ 978 u32 counters_num; 979 struct mlx5_fc *hw_cntrs_hndl; 980 /* read function for this counters type */ 981 int (*read_counters)(struct ib_device *ibdev, 982 struct mlx5_read_counters_attr *read_attr); 983 /* max index set as part of create_flow */ 984 u32 cntrs_max_index; 985 /* number of counters data entries (<description,index> pair) */ 986 u32 ncounters; 987 /* counters data array for descriptions and indexes */ 988 struct mlx5_ib_flow_counters_desc *counters_data; 989 /* protects access to mcounters internal data */ 990 struct mutex mcntrs_mutex; 991 }; 992 993 static inline struct mlx5_ib_mcounters * 994 to_mcounters(struct ib_counters *ibcntrs) 995 { 996 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 997 } 998 999 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1000 bool is_egress, 1001 struct mlx5_flow_act *action); 1002 struct mlx5_ib_lb_state { 1003 /* protect the user_td */ 1004 struct mutex mutex; 1005 u32 user_td; 1006 int qps; 1007 bool enabled; 1008 }; 1009 1010 struct mlx5_ib_pf_eq { 1011 struct notifier_block irq_nb; 1012 struct mlx5_ib_dev *dev; 1013 struct mlx5_eq *core; 1014 struct work_struct work; 1015 spinlock_t lock; /* Pagefaults spinlock */ 1016 struct workqueue_struct *wq; 1017 mempool_t *pool; 1018 }; 1019 1020 struct mlx5_devx_event_table { 1021 struct mlx5_nb devx_nb; 1022 /* serialize updating the event_xa */ 1023 struct mutex event_xa_lock; 1024 struct xarray event_xa; 1025 }; 1026 1027 struct mlx5_var_table { 1028 /* serialize updating the bitmap */ 1029 struct mutex bitmap_lock; 1030 unsigned long *bitmap; 1031 u64 hw_start_addr; 1032 u32 stride_size; 1033 u64 num_var_hw_entries; 1034 }; 1035 1036 struct mlx5_port_caps { 1037 bool has_smi; 1038 u8 ext_port_cap; 1039 }; 1040 1041 struct mlx5_ib_dev { 1042 struct ib_device ib_dev; 1043 struct mlx5_core_dev *mdev; 1044 struct notifier_block mdev_events; 1045 int num_ports; 1046 /* serialize update of capability mask 1047 */ 1048 struct mutex cap_mask_mutex; 1049 u8 ib_active:1; 1050 u8 is_rep:1; 1051 u8 lag_active:1; 1052 u8 wc_support:1; 1053 u8 fill_delay; 1054 struct umr_common umrc; 1055 /* sync used page count stats 1056 */ 1057 struct mlx5_ib_resources devr; 1058 1059 atomic_t mkey_var; 1060 struct mlx5_mr_cache cache; 1061 struct timer_list delay_timer; 1062 /* Prevents soft lock on massive reg MRs */ 1063 struct mutex slow_path_mutex; 1064 struct ib_odp_caps odp_caps; 1065 u64 odp_max_size; 1066 struct mlx5_ib_pf_eq odp_pf_eq; 1067 1068 struct xarray odp_mkeys; 1069 1070 u32 null_mkey; 1071 struct mlx5_ib_flow_db *flow_db; 1072 /* protect resources needed as part of reset flow */ 1073 spinlock_t reset_flow_resource_lock; 1074 struct list_head qp_list; 1075 /* Array with num_ports elements */ 1076 struct mlx5_ib_port *port; 1077 struct mlx5_sq_bfreg bfreg; 1078 struct mlx5_sq_bfreg wc_bfreg; 1079 struct mlx5_sq_bfreg fp_bfreg; 1080 struct mlx5_ib_delay_drop delay_drop; 1081 const struct mlx5_ib_profile *profile; 1082 1083 struct mlx5_ib_lb_state lb; 1084 u8 umr_fence; 1085 struct list_head ib_dev_list; 1086 u64 sys_image_guid; 1087 struct mlx5_dm dm; 1088 u16 devx_whitelist_uid; 1089 struct mlx5_srq_table srq_table; 1090 struct mlx5_qp_table qp_table; 1091 struct mlx5_async_ctx async_ctx; 1092 struct mlx5_devx_event_table devx_event_table; 1093 struct mlx5_var_table var_table; 1094 1095 struct xarray sig_mrs; 1096 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1097 u16 pkey_table_len; 1098 }; 1099 1100 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1101 { 1102 return container_of(mcq, struct mlx5_ib_cq, mcq); 1103 } 1104 1105 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1106 { 1107 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1108 } 1109 1110 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1111 { 1112 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1113 } 1114 1115 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1116 { 1117 return to_mdev(mr->ibmr.device); 1118 } 1119 1120 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1121 { 1122 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1123 udata, struct mlx5_ib_ucontext, ibucontext); 1124 1125 return to_mdev(context->ibucontext.device); 1126 } 1127 1128 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1129 { 1130 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1131 } 1132 1133 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1134 { 1135 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1136 } 1137 1138 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1139 { 1140 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1141 } 1142 1143 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1144 { 1145 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1146 } 1147 1148 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1149 { 1150 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1151 } 1152 1153 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1154 { 1155 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1156 } 1157 1158 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1159 { 1160 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1161 } 1162 1163 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1164 { 1165 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1166 } 1167 1168 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1169 { 1170 return container_of(msrq, struct mlx5_ib_srq, msrq); 1171 } 1172 1173 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1174 { 1175 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1176 } 1177 1178 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1179 { 1180 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1181 } 1182 1183 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1184 { 1185 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1186 } 1187 1188 static inline struct mlx5_ib_flow_action * 1189 to_mflow_act(struct ib_flow_action *ibact) 1190 { 1191 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1192 } 1193 1194 static inline struct mlx5_user_mmap_entry * 1195 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1196 { 1197 return container_of(rdma_entry, 1198 struct mlx5_user_mmap_entry, rdma_entry); 1199 } 1200 1201 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1202 struct ib_udata *udata, unsigned long virt, 1203 struct mlx5_db *db); 1204 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1205 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1206 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1207 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1208 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1209 struct ib_udata *udata); 1210 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1211 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1212 { 1213 return 0; 1214 } 1215 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1216 struct ib_udata *udata); 1217 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1218 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1219 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1220 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1221 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1222 const struct ib_recv_wr **bad_wr); 1223 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1224 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1225 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1226 struct ib_qp_init_attr *init_attr, 1227 struct ib_udata *udata); 1228 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1229 int attr_mask, struct ib_udata *udata); 1230 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1231 struct ib_qp_init_attr *qp_init_attr); 1232 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1233 void mlx5_ib_drain_sq(struct ib_qp *qp); 1234 void mlx5_ib_drain_rq(struct ib_qp *qp); 1235 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1236 size_t buflen, size_t *bc); 1237 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1238 size_t buflen, size_t *bc); 1239 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1240 size_t buflen, size_t *bc); 1241 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1242 struct ib_udata *udata); 1243 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1244 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1245 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1246 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1247 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1248 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1249 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1250 u64 virt_addr, int access_flags, 1251 struct ib_udata *udata); 1252 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1253 u64 length, u64 virt_addr, 1254 int fd, int access_flags, 1255 struct ib_udata *udata); 1256 int mlx5_ib_advise_mr(struct ib_pd *pd, 1257 enum ib_uverbs_advise_mr_advice advice, 1258 u32 flags, 1259 struct ib_sge *sg_list, 1260 u32 num_sge, 1261 struct uverbs_attr_bundle *attrs); 1262 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1263 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1264 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1265 int page_shift, int flags); 1266 int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags); 1267 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1268 struct ib_udata *udata, 1269 int access_flags); 1270 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1271 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1272 void mlx5_ib_fence_dmabuf_mr(struct mlx5_ib_mr *mr); 1273 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1274 u64 length, u64 virt_addr, int access_flags, 1275 struct ib_pd *pd, struct ib_udata *udata); 1276 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1277 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1278 u32 max_num_sg); 1279 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1280 u32 max_num_sg, 1281 u32 max_num_meta_sg); 1282 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1283 unsigned int *sg_offset); 1284 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1285 int data_sg_nents, unsigned int *data_sg_offset, 1286 struct scatterlist *meta_sg, int meta_sg_nents, 1287 unsigned int *meta_sg_offset); 1288 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1289 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1290 const struct ib_mad *in, struct ib_mad *out, 1291 size_t *out_mad_size, u16 *out_mad_pkey_index); 1292 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1293 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1294 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1295 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1296 __be64 *sys_image_guid); 1297 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1298 u16 *max_pkeys); 1299 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1300 u32 *vendor_id); 1301 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1302 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1303 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1304 u16 *pkey); 1305 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1306 union ib_gid *gid); 1307 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1308 struct ib_port_attr *props); 1309 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1310 struct ib_port_attr *props); 1311 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1312 u64 access_flags); 1313 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1314 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1315 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1316 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1317 1318 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1319 unsigned int entry, int access_flags); 1320 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1321 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1322 1323 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1324 struct ib_mr_status *mr_status); 1325 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1326 struct ib_wq_init_attr *init_attr, 1327 struct ib_udata *udata); 1328 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1329 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1330 u32 wq_attr_mask, struct ib_udata *udata); 1331 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1332 struct ib_rwq_ind_table_init_attr *init_attr, 1333 struct ib_udata *udata); 1334 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1335 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1336 struct ib_ucontext *context, 1337 struct ib_dm_alloc_attr *attr, 1338 struct uverbs_attr_bundle *attrs); 1339 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1340 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1341 struct ib_dm_mr_attr *attr, 1342 struct uverbs_attr_bundle *attrs); 1343 1344 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1345 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1346 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1347 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1348 int __init mlx5_ib_odp_init(void); 1349 void mlx5_ib_odp_cleanup(void); 1350 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1351 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1352 struct mlx5_ib_mr *mr, int flags); 1353 1354 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1355 enum ib_uverbs_advise_mr_advice advice, 1356 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1357 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1358 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1359 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1360 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1361 { 1362 return; 1363 } 1364 1365 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1366 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1367 static inline int mlx5_ib_odp_init(void) { return 0; } 1368 static inline void mlx5_ib_odp_cleanup(void) {} 1369 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1370 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1371 struct mlx5_ib_mr *mr, int flags) {} 1372 1373 static inline int 1374 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1375 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1376 struct ib_sge *sg_list, u32 num_sge) 1377 { 1378 return -EOPNOTSUPP; 1379 } 1380 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1381 { 1382 return -EOPNOTSUPP; 1383 } 1384 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1385 { 1386 return -EOPNOTSUPP; 1387 } 1388 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1389 1390 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1391 1392 /* Needed for rep profile */ 1393 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1394 const struct mlx5_ib_profile *profile, 1395 int stage); 1396 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1397 const struct mlx5_ib_profile *profile); 1398 1399 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1400 u8 port, struct ifla_vf_info *info); 1401 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1402 u8 port, int state); 1403 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1404 u8 port, struct ifla_vf_stats *stats); 1405 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1406 struct ifla_vf_guid *node_guid, 1407 struct ifla_vf_guid *port_guid); 1408 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1409 u64 guid, int type); 1410 1411 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1412 const struct ib_gid_attr *attr); 1413 1414 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1415 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1416 1417 /* GSI QP helper functions */ 1418 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1419 struct ib_qp_init_attr *attr); 1420 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1421 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1422 int attr_mask); 1423 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1424 int qp_attr_mask, 1425 struct ib_qp_init_attr *qp_init_attr); 1426 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1427 const struct ib_send_wr **bad_wr); 1428 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1429 const struct ib_recv_wr **bad_wr); 1430 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1431 1432 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1433 1434 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1435 int bfregn); 1436 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1437 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1438 u8 ib_port_num, 1439 u8 *native_port_num); 1440 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1441 u8 port_num); 1442 1443 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1444 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1445 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1446 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1447 1448 static inline void init_query_mad(struct ib_smp *mad) 1449 { 1450 mad->base_version = 1; 1451 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1452 mad->class_version = 1; 1453 mad->method = IB_MGMT_METHOD_GET; 1454 } 1455 1456 static inline int is_qp1(enum ib_qp_type qp_type) 1457 { 1458 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1459 } 1460 1461 #define MLX5_MAX_UMR_SHIFT 16 1462 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1463 1464 static inline u32 check_cq_create_flags(u32 flags) 1465 { 1466 /* 1467 * It returns non-zero value for unsupported CQ 1468 * create flags, otherwise it returns zero. 1469 */ 1470 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1471 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1472 } 1473 1474 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1475 u32 *user_index) 1476 { 1477 if (cqe_version) { 1478 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1479 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1480 return -EINVAL; 1481 *user_index = cmd_uidx; 1482 } else { 1483 *user_index = MLX5_IB_DEFAULT_UIDX; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1490 struct mlx5_ib_create_qp *ucmd, 1491 int inlen, 1492 u32 *user_index) 1493 { 1494 u8 cqe_version = ucontext->cqe_version; 1495 1496 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1497 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1498 return 0; 1499 1500 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1501 return -EINVAL; 1502 1503 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1504 } 1505 1506 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1507 struct mlx5_ib_create_srq *ucmd, 1508 int inlen, 1509 u32 *user_index) 1510 { 1511 u8 cqe_version = ucontext->cqe_version; 1512 1513 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1514 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1515 return 0; 1516 1517 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1518 return -EINVAL; 1519 1520 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1521 } 1522 1523 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1524 { 1525 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1526 MLX5_UARS_IN_PAGE : 1; 1527 } 1528 1529 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1530 struct mlx5_bfreg_info *bfregi) 1531 { 1532 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1533 } 1534 1535 extern void *xlt_emergency_page; 1536 1537 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1538 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1539 bool dyn_bfreg); 1540 1541 static inline bool mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev *dev, 1542 size_t length) 1543 { 1544 /* 1545 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is 1546 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka 1547 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey 1548 * can never be enabled without this capability. Simplify this weird 1549 * quirky hardware by just saying it can't use PAS lists with UMR at 1550 * all. 1551 */ 1552 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1553 return false; 1554 1555 /* 1556 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is 1557 * used. 1558 */ 1559 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 1560 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE) 1561 return false; 1562 return true; 1563 } 1564 1565 /* 1566 * true if an existing MR can be reconfigured to new access_flags using UMR. 1567 * Older HW cannot use UMR to update certain elements of the MKC. See 1568 * umr_check_mkey_mask(), get_umr_update_access_mask() and umr_check_mkey_mask() 1569 */ 1570 static inline bool mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev *dev, 1571 unsigned int current_access_flags, 1572 unsigned int target_access_flags) 1573 { 1574 unsigned int diffs = current_access_flags ^ target_access_flags; 1575 1576 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) && 1577 MLX5_CAP_GEN(dev->mdev, atomic) && 1578 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1579 return false; 1580 1581 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1582 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 1583 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 1584 return false; 1585 1586 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1587 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) && 1588 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 1589 return false; 1590 1591 return true; 1592 } 1593 1594 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1595 struct mlx5_core_mkey *mmkey) 1596 { 1597 refcount_set(&mmkey->usecount, 1); 1598 1599 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1600 mmkey, GFP_KERNEL)); 1601 } 1602 1603 /* deref an mkey that can participate in ODP flow */ 1604 static inline void mlx5r_deref_odp_mkey(struct mlx5_core_mkey *mmkey) 1605 { 1606 if (refcount_dec_and_test(&mmkey->usecount)) 1607 wake_up(&mmkey->wait); 1608 } 1609 1610 /* deref an mkey that can participate in ODP flow and wait for relese */ 1611 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_core_mkey *mmkey) 1612 { 1613 mlx5r_deref_odp_mkey(mmkey); 1614 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1615 } 1616 1617 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1618 1619 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1620 { 1621 return dev->lag_active || 1622 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1623 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1624 } 1625 #endif /* MLX5_IB_H */ 1626