1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 48 #define mlx5_ib_dbg(dev, format, arg...) \ 49 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 50 __LINE__, current->pid, ##arg) 51 52 #define mlx5_ib_err(dev, format, arg...) \ 53 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 54 __LINE__, current->pid, ##arg) 55 56 #define mlx5_ib_warn(dev, format, arg...) \ 57 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 58 __LINE__, current->pid, ##arg) 59 60 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 61 sizeof(((type *)0)->fld) <= (sz)) 62 #define MLX5_IB_DEFAULT_UIDX 0xffffff 63 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 64 65 enum { 66 MLX5_IB_MMAP_CMD_SHIFT = 8, 67 MLX5_IB_MMAP_CMD_MASK = 0xff, 68 }; 69 70 enum mlx5_ib_mmap_cmd { 71 MLX5_IB_MMAP_REGULAR_PAGE = 0, 72 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 73 MLX5_IB_MMAP_WC_PAGE = 2, 74 MLX5_IB_MMAP_NC_PAGE = 3, 75 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 76 MLX5_IB_MMAP_CORE_CLOCK = 5, 77 }; 78 79 enum { 80 MLX5_RES_SCAT_DATA32_CQE = 0x1, 81 MLX5_RES_SCAT_DATA64_CQE = 0x2, 82 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 83 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 84 }; 85 86 enum mlx5_ib_latency_class { 87 MLX5_IB_LATENCY_CLASS_LOW, 88 MLX5_IB_LATENCY_CLASS_MEDIUM, 89 MLX5_IB_LATENCY_CLASS_HIGH, 90 MLX5_IB_LATENCY_CLASS_FAST_PATH 91 }; 92 93 enum mlx5_ib_mad_ifc_flags { 94 MLX5_MAD_IFC_IGNORE_MKEY = 1, 95 MLX5_MAD_IFC_IGNORE_BKEY = 2, 96 MLX5_MAD_IFC_NET_VIEW = 4, 97 }; 98 99 enum { 100 MLX5_CROSS_CHANNEL_UUAR = 0, 101 }; 102 103 enum { 104 MLX5_CQE_VERSION_V0, 105 MLX5_CQE_VERSION_V1, 106 }; 107 108 struct mlx5_ib_vma_private_data { 109 struct list_head list; 110 struct vm_area_struct *vma; 111 }; 112 113 struct mlx5_ib_ucontext { 114 struct ib_ucontext ibucontext; 115 struct list_head db_page_list; 116 117 /* protect doorbell record alloc/free 118 */ 119 struct mutex db_page_mutex; 120 struct mlx5_uuar_info uuari; 121 u8 cqe_version; 122 /* Transport Domain number */ 123 u32 tdn; 124 struct list_head vma_private_list; 125 }; 126 127 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 128 { 129 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 130 } 131 132 struct mlx5_ib_pd { 133 struct ib_pd ibpd; 134 u32 pdn; 135 }; 136 137 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 138 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 139 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 140 #error "Invalid number of bypass priorities" 141 #endif 142 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 143 144 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 145 struct mlx5_ib_flow_prio { 146 struct mlx5_flow_table *flow_table; 147 unsigned int refcount; 148 }; 149 150 struct mlx5_ib_flow_handler { 151 struct list_head list; 152 struct ib_flow ibflow; 153 unsigned int prio; 154 struct mlx5_flow_rule *rule; 155 }; 156 157 struct mlx5_ib_flow_db { 158 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 159 /* Protect flow steering bypass flow tables 160 * when add/del flow rules. 161 * only single add/removal of flow steering rule could be done 162 * simultaneously. 163 */ 164 struct mutex lock; 165 }; 166 167 /* Use macros here so that don't have to duplicate 168 * enum ib_send_flags and enum ib_qp_type for low-level driver 169 */ 170 171 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 172 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 173 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 174 175 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 176 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 177 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 178 179 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 180 /* 181 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 182 * creates the actual hardware QP. 183 */ 184 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 185 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 186 187 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 188 * 189 * These flags are intended for internal use by the mlx5_ib driver, and they 190 * rely on the range reserved for that use in the ib_qp_create_flags enum. 191 */ 192 193 /* Create a UD QP whose source QP number is 1 */ 194 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 195 { 196 return IB_QP_CREATE_RESERVED_START; 197 } 198 199 struct wr_list { 200 u16 opcode; 201 u16 next; 202 }; 203 204 struct mlx5_ib_wq { 205 u64 *wrid; 206 u32 *wr_data; 207 struct wr_list *w_list; 208 unsigned *wqe_head; 209 u16 unsig_count; 210 211 /* serialize post to the work queue 212 */ 213 spinlock_t lock; 214 int wqe_cnt; 215 int max_post; 216 int max_gs; 217 int offset; 218 int wqe_shift; 219 unsigned head; 220 unsigned tail; 221 u16 cur_post; 222 u16 last_poll; 223 void *qend; 224 }; 225 226 struct mlx5_ib_rwq { 227 struct ib_wq ibwq; 228 u32 rqn; 229 u32 rq_num_pas; 230 u32 log_rq_stride; 231 u32 log_rq_size; 232 u32 rq_page_offset; 233 u32 log_page_size; 234 struct ib_umem *umem; 235 size_t buf_size; 236 unsigned int page_shift; 237 int create_type; 238 struct mlx5_db db; 239 u32 user_index; 240 u32 wqe_count; 241 u32 wqe_shift; 242 int wq_sig; 243 }; 244 245 enum { 246 MLX5_QP_USER, 247 MLX5_QP_KERNEL, 248 MLX5_QP_EMPTY 249 }; 250 251 enum { 252 MLX5_WQ_USER, 253 MLX5_WQ_KERNEL 254 }; 255 256 struct mlx5_ib_rwq_ind_table { 257 struct ib_rwq_ind_table ib_rwq_ind_tbl; 258 u32 rqtn; 259 }; 260 261 /* 262 * Connect-IB can trigger up to four concurrent pagefaults 263 * per-QP. 264 */ 265 enum mlx5_ib_pagefault_context { 266 MLX5_IB_PAGEFAULT_RESPONDER_READ, 267 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 268 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 269 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 270 MLX5_IB_PAGEFAULT_CONTEXTS 271 }; 272 273 static inline enum mlx5_ib_pagefault_context 274 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 275 { 276 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 277 } 278 279 struct mlx5_ib_pfault { 280 struct work_struct work; 281 struct mlx5_pagefault mpfault; 282 }; 283 284 struct mlx5_ib_ubuffer { 285 struct ib_umem *umem; 286 int buf_size; 287 u64 buf_addr; 288 }; 289 290 struct mlx5_ib_qp_base { 291 struct mlx5_ib_qp *container_mibqp; 292 struct mlx5_core_qp mqp; 293 struct mlx5_ib_ubuffer ubuffer; 294 }; 295 296 struct mlx5_ib_qp_trans { 297 struct mlx5_ib_qp_base base; 298 u16 xrcdn; 299 u8 alt_port; 300 u8 atomic_rd_en; 301 u8 resp_depth; 302 }; 303 304 struct mlx5_ib_rss_qp { 305 u32 tirn; 306 }; 307 308 struct mlx5_ib_rq { 309 struct mlx5_ib_qp_base base; 310 struct mlx5_ib_wq *rq; 311 struct mlx5_ib_ubuffer ubuffer; 312 struct mlx5_db *doorbell; 313 u32 tirn; 314 u8 state; 315 }; 316 317 struct mlx5_ib_sq { 318 struct mlx5_ib_qp_base base; 319 struct mlx5_ib_wq *sq; 320 struct mlx5_ib_ubuffer ubuffer; 321 struct mlx5_db *doorbell; 322 u32 tisn; 323 u8 state; 324 }; 325 326 struct mlx5_ib_raw_packet_qp { 327 struct mlx5_ib_sq sq; 328 struct mlx5_ib_rq rq; 329 }; 330 331 struct mlx5_ib_qp { 332 struct ib_qp ibqp; 333 union { 334 struct mlx5_ib_qp_trans trans_qp; 335 struct mlx5_ib_raw_packet_qp raw_packet_qp; 336 struct mlx5_ib_rss_qp rss_qp; 337 }; 338 struct mlx5_buf buf; 339 340 struct mlx5_db db; 341 struct mlx5_ib_wq rq; 342 343 u8 sq_signal_bits; 344 u8 fm_cache; 345 struct mlx5_ib_wq sq; 346 347 /* serialize qp state modifications 348 */ 349 struct mutex mutex; 350 u32 flags; 351 u8 port; 352 u8 state; 353 int wq_sig; 354 int scat_cqe; 355 int max_inline_data; 356 struct mlx5_bf *bf; 357 int has_rq; 358 359 /* only for user space QPs. For kernel 360 * we have it from the bf object 361 */ 362 int uuarn; 363 364 int create_type; 365 366 /* Store signature errors */ 367 bool signature_en; 368 369 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 370 /* 371 * A flag that is true for QP's that are in a state that doesn't 372 * allow page faults, and shouldn't schedule any more faults. 373 */ 374 int disable_page_faults; 375 /* 376 * The disable_page_faults_lock protects a QP's disable_page_faults 377 * field, allowing for a thread to atomically check whether the QP 378 * allows page faults, and if so schedule a page fault. 379 */ 380 spinlock_t disable_page_faults_lock; 381 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 382 #endif 383 struct list_head qps_list; 384 struct list_head cq_recv_list; 385 struct list_head cq_send_list; 386 }; 387 388 struct mlx5_ib_cq_buf { 389 struct mlx5_buf buf; 390 struct ib_umem *umem; 391 int cqe_size; 392 int nent; 393 }; 394 395 enum mlx5_ib_qp_flags { 396 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 397 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 398 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 399 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 400 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 401 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 402 /* QP uses 1 as its source QP number */ 403 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 404 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 405 }; 406 407 struct mlx5_umr_wr { 408 struct ib_send_wr wr; 409 union { 410 u64 virt_addr; 411 u64 offset; 412 } target; 413 struct ib_pd *pd; 414 unsigned int page_shift; 415 unsigned int npages; 416 u32 length; 417 int access_flags; 418 u32 mkey; 419 }; 420 421 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 422 { 423 return container_of(wr, struct mlx5_umr_wr, wr); 424 } 425 426 struct mlx5_shared_mr_info { 427 int mr_id; 428 struct ib_umem *umem; 429 }; 430 431 struct mlx5_ib_cq { 432 struct ib_cq ibcq; 433 struct mlx5_core_cq mcq; 434 struct mlx5_ib_cq_buf buf; 435 struct mlx5_db db; 436 437 /* serialize access to the CQ 438 */ 439 spinlock_t lock; 440 441 /* protect resize cq 442 */ 443 struct mutex resize_mutex; 444 struct mlx5_ib_cq_buf *resize_buf; 445 struct ib_umem *resize_umem; 446 int cqe_size; 447 struct list_head list_send_qp; 448 struct list_head list_recv_qp; 449 u32 create_flags; 450 struct list_head wc_list; 451 enum ib_cq_notify_flags notify_flags; 452 struct work_struct notify_work; 453 }; 454 455 struct mlx5_ib_wc { 456 struct ib_wc wc; 457 struct list_head list; 458 }; 459 460 struct mlx5_ib_srq { 461 struct ib_srq ibsrq; 462 struct mlx5_core_srq msrq; 463 struct mlx5_buf buf; 464 struct mlx5_db db; 465 u64 *wrid; 466 /* protect SRQ hanlding 467 */ 468 spinlock_t lock; 469 int head; 470 int tail; 471 u16 wqe_ctr; 472 struct ib_umem *umem; 473 /* serialize arming a SRQ 474 */ 475 struct mutex mutex; 476 int wq_sig; 477 }; 478 479 struct mlx5_ib_xrcd { 480 struct ib_xrcd ibxrcd; 481 u32 xrcdn; 482 }; 483 484 enum mlx5_ib_mtt_access_flags { 485 MLX5_IB_MTT_READ = (1 << 0), 486 MLX5_IB_MTT_WRITE = (1 << 1), 487 }; 488 489 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 490 491 struct mlx5_ib_mr { 492 struct ib_mr ibmr; 493 void *descs; 494 dma_addr_t desc_map; 495 int ndescs; 496 int max_descs; 497 int desc_size; 498 int access_mode; 499 struct mlx5_core_mkey mmkey; 500 struct ib_umem *umem; 501 struct mlx5_shared_mr_info *smr_info; 502 struct list_head list; 503 int order; 504 int umred; 505 int npages; 506 struct mlx5_ib_dev *dev; 507 struct mlx5_create_mkey_mbox_out out; 508 struct mlx5_core_sig_ctx *sig; 509 int live; 510 void *descs_alloc; 511 int access_flags; /* Needed for rereg MR */ 512 }; 513 514 struct mlx5_ib_mw { 515 struct ib_mw ibmw; 516 struct mlx5_core_mkey mmkey; 517 }; 518 519 struct mlx5_ib_umr_context { 520 struct ib_cqe cqe; 521 enum ib_wc_status status; 522 struct completion done; 523 }; 524 525 struct umr_common { 526 struct ib_pd *pd; 527 struct ib_cq *cq; 528 struct ib_qp *qp; 529 /* control access to UMR QP 530 */ 531 struct semaphore sem; 532 }; 533 534 enum { 535 MLX5_FMR_INVALID, 536 MLX5_FMR_VALID, 537 MLX5_FMR_BUSY, 538 }; 539 540 struct mlx5_cache_ent { 541 struct list_head head; 542 /* sync access to the cahce entry 543 */ 544 spinlock_t lock; 545 546 547 struct dentry *dir; 548 char name[4]; 549 u32 order; 550 u32 size; 551 u32 cur; 552 u32 miss; 553 u32 limit; 554 555 struct dentry *fsize; 556 struct dentry *fcur; 557 struct dentry *fmiss; 558 struct dentry *flimit; 559 560 struct mlx5_ib_dev *dev; 561 struct work_struct work; 562 struct delayed_work dwork; 563 int pending; 564 }; 565 566 struct mlx5_mr_cache { 567 struct workqueue_struct *wq; 568 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 569 int stopped; 570 struct dentry *root; 571 unsigned long last_add; 572 }; 573 574 struct mlx5_ib_gsi_qp; 575 576 struct mlx5_ib_port_resources { 577 struct mlx5_ib_resources *devr; 578 struct mlx5_ib_gsi_qp *gsi; 579 struct work_struct pkey_change_work; 580 }; 581 582 struct mlx5_ib_resources { 583 struct ib_cq *c0; 584 struct ib_xrcd *x0; 585 struct ib_xrcd *x1; 586 struct ib_pd *p0; 587 struct ib_srq *s0; 588 struct ib_srq *s1; 589 struct mlx5_ib_port_resources ports[2]; 590 /* Protects changes to the port resources */ 591 struct mutex mutex; 592 }; 593 594 struct mlx5_ib_port { 595 u16 q_cnt_id; 596 }; 597 598 struct mlx5_roce { 599 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 600 * netdev pointer 601 */ 602 rwlock_t netdev_lock; 603 struct net_device *netdev; 604 struct notifier_block nb; 605 }; 606 607 struct mlx5_ib_dev { 608 struct ib_device ib_dev; 609 struct mlx5_core_dev *mdev; 610 struct mlx5_roce roce; 611 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 612 int num_ports; 613 /* serialize update of capability mask 614 */ 615 struct mutex cap_mask_mutex; 616 bool ib_active; 617 struct umr_common umrc; 618 /* sync used page count stats 619 */ 620 struct mlx5_ib_resources devr; 621 struct mlx5_mr_cache cache; 622 struct timer_list delay_timer; 623 int fill_delay; 624 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 625 struct ib_odp_caps odp_caps; 626 /* 627 * Sleepable RCU that prevents destruction of MRs while they are still 628 * being used by a page fault handler. 629 */ 630 struct srcu_struct mr_srcu; 631 #endif 632 struct mlx5_ib_flow_db flow_db; 633 /* protect resources needed as part of reset flow */ 634 spinlock_t reset_flow_resource_lock; 635 struct list_head qp_list; 636 /* Array with num_ports elements */ 637 struct mlx5_ib_port *port; 638 }; 639 640 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 641 { 642 return container_of(mcq, struct mlx5_ib_cq, mcq); 643 } 644 645 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 646 { 647 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 648 } 649 650 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 651 { 652 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 653 } 654 655 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 656 { 657 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 658 } 659 660 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 661 { 662 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 663 } 664 665 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 666 { 667 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 668 } 669 670 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 671 { 672 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 673 } 674 675 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 676 { 677 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 678 } 679 680 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 681 { 682 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 683 } 684 685 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 686 { 687 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 688 } 689 690 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 691 { 692 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 693 } 694 695 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 696 { 697 return container_of(msrq, struct mlx5_ib_srq, msrq); 698 } 699 700 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 701 { 702 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 703 } 704 705 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 706 { 707 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 708 } 709 710 struct mlx5_ib_ah { 711 struct ib_ah ibah; 712 struct mlx5_av av; 713 }; 714 715 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 716 { 717 return container_of(ibah, struct mlx5_ib_ah, ibah); 718 } 719 720 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 721 struct mlx5_db *db); 722 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 723 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 724 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 725 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 726 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 727 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 728 const void *in_mad, void *response_mad); 729 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 730 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 731 int mlx5_ib_destroy_ah(struct ib_ah *ah); 732 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 733 struct ib_srq_init_attr *init_attr, 734 struct ib_udata *udata); 735 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 736 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 737 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 738 int mlx5_ib_destroy_srq(struct ib_srq *srq); 739 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 740 struct ib_recv_wr **bad_wr); 741 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 742 struct ib_qp_init_attr *init_attr, 743 struct ib_udata *udata); 744 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 745 int attr_mask, struct ib_udata *udata); 746 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 747 struct ib_qp_init_attr *qp_init_attr); 748 int mlx5_ib_destroy_qp(struct ib_qp *qp); 749 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 750 struct ib_send_wr **bad_wr); 751 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 752 struct ib_recv_wr **bad_wr); 753 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 754 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 755 void *buffer, u32 length, 756 struct mlx5_ib_qp_base *base); 757 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 758 const struct ib_cq_init_attr *attr, 759 struct ib_ucontext *context, 760 struct ib_udata *udata); 761 int mlx5_ib_destroy_cq(struct ib_cq *cq); 762 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 763 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 764 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 765 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 766 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 767 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 768 u64 virt_addr, int access_flags, 769 struct ib_udata *udata); 770 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 771 struct ib_udata *udata); 772 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 773 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 774 int npages, int zap); 775 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 776 u64 length, u64 virt_addr, int access_flags, 777 struct ib_pd *pd, struct ib_udata *udata); 778 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 779 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 780 enum ib_mr_type mr_type, 781 u32 max_num_sg); 782 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 783 unsigned int *sg_offset); 784 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 785 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 786 const struct ib_mad_hdr *in, size_t in_mad_size, 787 struct ib_mad_hdr *out, size_t *out_mad_size, 788 u16 *out_mad_pkey_index); 789 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 790 struct ib_ucontext *context, 791 struct ib_udata *udata); 792 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 793 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 794 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 795 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 796 struct ib_smp *out_mad); 797 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 798 __be64 *sys_image_guid); 799 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 800 u16 *max_pkeys); 801 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 802 u32 *vendor_id); 803 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 804 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 805 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 806 u16 *pkey); 807 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 808 union ib_gid *gid); 809 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 810 struct ib_port_attr *props); 811 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 812 struct ib_port_attr *props); 813 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 814 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 815 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 816 int *ncont, int *order); 817 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 818 int page_shift, size_t offset, size_t num_pages, 819 __be64 *pas, int access_flags); 820 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 821 int page_shift, __be64 *pas, int access_flags); 822 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 823 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 824 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 825 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 826 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 827 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 828 struct ib_mr_status *mr_status); 829 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 830 struct ib_wq_init_attr *init_attr, 831 struct ib_udata *udata); 832 int mlx5_ib_destroy_wq(struct ib_wq *wq); 833 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 834 u32 wq_attr_mask, struct ib_udata *udata); 835 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 836 struct ib_rwq_ind_table_init_attr *init_attr, 837 struct ib_udata *udata); 838 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 839 840 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 841 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 842 843 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 844 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 845 struct mlx5_ib_pfault *pfault); 846 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 847 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 848 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 849 int __init mlx5_ib_odp_init(void); 850 void mlx5_ib_odp_cleanup(void); 851 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 852 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 853 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 854 unsigned long end); 855 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 856 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 857 { 858 return; 859 } 860 861 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 862 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 863 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 864 static inline int mlx5_ib_odp_init(void) { return 0; } 865 static inline void mlx5_ib_odp_cleanup(void) {} 866 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 867 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 868 869 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 870 871 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 872 u8 port, struct ifla_vf_info *info); 873 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 874 u8 port, int state); 875 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 876 u8 port, struct ifla_vf_stats *stats); 877 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 878 u64 guid, int type); 879 880 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 881 int index); 882 883 /* GSI QP helper functions */ 884 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 885 struct ib_qp_init_attr *init_attr); 886 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 887 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 888 int attr_mask); 889 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 890 int qp_attr_mask, 891 struct ib_qp_init_attr *qp_init_attr); 892 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 893 struct ib_send_wr **bad_wr); 894 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 895 struct ib_recv_wr **bad_wr); 896 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 897 898 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 899 900 static inline void init_query_mad(struct ib_smp *mad) 901 { 902 mad->base_version = 1; 903 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 904 mad->class_version = 1; 905 mad->method = IB_MGMT_METHOD_GET; 906 } 907 908 static inline u8 convert_access(int acc) 909 { 910 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 911 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 912 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 913 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 914 MLX5_PERM_LOCAL_READ; 915 } 916 917 static inline int is_qp1(enum ib_qp_type qp_type) 918 { 919 return qp_type == MLX5_IB_QPT_HW_GSI; 920 } 921 922 #define MLX5_MAX_UMR_SHIFT 16 923 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 924 925 static inline u32 check_cq_create_flags(u32 flags) 926 { 927 /* 928 * It returns non-zero value for unsupported CQ 929 * create flags, otherwise it returns zero. 930 */ 931 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 932 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 933 } 934 935 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 936 u32 *user_index) 937 { 938 if (cqe_version) { 939 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 940 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 941 return -EINVAL; 942 *user_index = cmd_uidx; 943 } else { 944 *user_index = MLX5_IB_DEFAULT_UIDX; 945 } 946 947 return 0; 948 } 949 #endif /* MLX5_IB_H */ 950