1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include "srq.h" 64 #include <linux/mlx5/fs_helpers.h> 65 #include <linux/mlx5/accel.h> 66 #include <rdma/uverbs_std_types.h> 67 #include <rdma/mlx5_user_ioctl_verbs.h> 68 #include <rdma/mlx5_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME mlx5_ib 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #define DRIVER_NAME "mlx5_ib" 74 #define DRIVER_VERSION "5.0-0" 75 76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 78 MODULE_LICENSE("Dual BSD/GPL"); 79 80 static char mlx5_version[] = 81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 82 DRIVER_VERSION "\n"; 83 84 struct mlx5_ib_event_work { 85 struct work_struct work; 86 union { 87 struct mlx5_ib_dev *dev; 88 struct mlx5_ib_multiport_info *mpi; 89 }; 90 bool is_slave; 91 unsigned int event; 92 void *param; 93 }; 94 95 enum { 96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 97 }; 98 99 static struct workqueue_struct *mlx5_ib_event_wq; 100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 101 static LIST_HEAD(mlx5_ib_dev_list); 102 /* 103 * This mutex should be held when accessing either of the above lists 104 */ 105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 106 107 /* We can't use an array for xlt_emergency_page because dma_map_single 108 * doesn't work on kernel modules memory 109 */ 110 static unsigned long xlt_emergency_page; 111 static struct mutex xlt_emergency_page_mutex; 112 113 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 114 { 115 struct mlx5_ib_dev *dev; 116 117 mutex_lock(&mlx5_ib_multiport_mutex); 118 dev = mpi->ibdev; 119 mutex_unlock(&mlx5_ib_multiport_mutex); 120 return dev; 121 } 122 123 static enum rdma_link_layer 124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 125 { 126 switch (port_type_cap) { 127 case MLX5_CAP_PORT_TYPE_IB: 128 return IB_LINK_LAYER_INFINIBAND; 129 case MLX5_CAP_PORT_TYPE_ETH: 130 return IB_LINK_LAYER_ETHERNET; 131 default: 132 return IB_LINK_LAYER_UNSPECIFIED; 133 } 134 } 135 136 static enum rdma_link_layer 137 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 141 142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 143 } 144 145 static int get_port_state(struct ib_device *ibdev, 146 u8 port_num, 147 enum ib_port_state *state) 148 { 149 struct ib_port_attr attr; 150 int ret; 151 152 memset(&attr, 0, sizeof(attr)); 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 154 if (!ret) 155 *state = attr.state; 156 return ret; 157 } 158 159 static int mlx5_netdev_event(struct notifier_block *this, 160 unsigned long event, void *ptr) 161 { 162 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 163 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 164 u8 port_num = roce->native_port_num; 165 struct mlx5_core_dev *mdev; 166 struct mlx5_ib_dev *ibdev; 167 168 ibdev = roce->dev; 169 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 170 if (!mdev) 171 return NOTIFY_DONE; 172 173 switch (event) { 174 case NETDEV_REGISTER: 175 write_lock(&roce->netdev_lock); 176 if (ibdev->rep) { 177 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 178 struct net_device *rep_ndev; 179 180 rep_ndev = mlx5_ib_get_rep_netdev(esw, 181 ibdev->rep->vport); 182 if (rep_ndev == ndev) 183 roce->netdev = ndev; 184 } else if (ndev->dev.parent == &mdev->pdev->dev) { 185 roce->netdev = ndev; 186 } 187 write_unlock(&roce->netdev_lock); 188 break; 189 190 case NETDEV_UNREGISTER: 191 write_lock(&roce->netdev_lock); 192 if (roce->netdev == ndev) 193 roce->netdev = NULL; 194 write_unlock(&roce->netdev_lock); 195 break; 196 197 case NETDEV_CHANGE: 198 case NETDEV_UP: 199 case NETDEV_DOWN: { 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 201 struct net_device *upper = NULL; 202 203 if (lag_ndev) { 204 upper = netdev_master_upper_dev_get(lag_ndev); 205 dev_put(lag_ndev); 206 } 207 208 if ((upper == ndev || (!upper && ndev == roce->netdev)) 209 && ibdev->ib_active) { 210 struct ib_event ibev = { }; 211 enum ib_port_state port_state; 212 213 if (get_port_state(&ibdev->ib_dev, port_num, 214 &port_state)) 215 goto done; 216 217 if (roce->last_port_state == port_state) 218 goto done; 219 220 roce->last_port_state = port_state; 221 ibev.device = &ibdev->ib_dev; 222 if (port_state == IB_PORT_DOWN) 223 ibev.event = IB_EVENT_PORT_ERR; 224 else if (port_state == IB_PORT_ACTIVE) 225 ibev.event = IB_EVENT_PORT_ACTIVE; 226 else 227 goto done; 228 229 ibev.element.port_num = port_num; 230 ib_dispatch_event(&ibev); 231 } 232 break; 233 } 234 235 default: 236 break; 237 } 238 done: 239 mlx5_ib_put_native_port_mdev(ibdev, port_num); 240 return NOTIFY_DONE; 241 } 242 243 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 244 u8 port_num) 245 { 246 struct mlx5_ib_dev *ibdev = to_mdev(device); 247 struct net_device *ndev; 248 struct mlx5_core_dev *mdev; 249 250 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 251 if (!mdev) 252 return NULL; 253 254 ndev = mlx5_lag_get_roce_netdev(mdev); 255 if (ndev) 256 goto out; 257 258 /* Ensure ndev does not disappear before we invoke dev_hold() 259 */ 260 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 261 ndev = ibdev->roce[port_num - 1].netdev; 262 if (ndev) 263 dev_hold(ndev); 264 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 265 266 out: 267 mlx5_ib_put_native_port_mdev(ibdev, port_num); 268 return ndev; 269 } 270 271 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 272 u8 ib_port_num, 273 u8 *native_port_num) 274 { 275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 276 ib_port_num); 277 struct mlx5_core_dev *mdev = NULL; 278 struct mlx5_ib_multiport_info *mpi; 279 struct mlx5_ib_port *port; 280 281 if (!mlx5_core_mp_enabled(ibdev->mdev) || 282 ll != IB_LINK_LAYER_ETHERNET) { 283 if (native_port_num) 284 *native_port_num = ib_port_num; 285 return ibdev->mdev; 286 } 287 288 if (native_port_num) 289 *native_port_num = 1; 290 291 port = &ibdev->port[ib_port_num - 1]; 292 if (!port) 293 return NULL; 294 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 297 if (mpi && !mpi->unaffiliate) { 298 mdev = mpi->mdev; 299 /* If it's the master no need to refcount, it'll exist 300 * as long as the ib_dev exists. 301 */ 302 if (!mpi->is_master) 303 mpi->mdev_refcnt++; 304 } 305 spin_unlock(&port->mp.mpi_lock); 306 307 return mdev; 308 } 309 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 311 { 312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 313 port_num); 314 struct mlx5_ib_multiport_info *mpi; 315 struct mlx5_ib_port *port; 316 317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 318 return; 319 320 port = &ibdev->port[port_num - 1]; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[port_num - 1].mp.mpi; 324 if (mpi->is_master) 325 goto out; 326 327 mpi->mdev_refcnt--; 328 if (mpi->unaffiliate) 329 complete(&mpi->unref_comp); 330 out: 331 spin_unlock(&port->mp.mpi_lock); 332 } 333 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed, 335 u8 *active_width) 336 { 337 switch (eth_proto_oper) { 338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_SDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 352 *active_width = IB_WIDTH_1X; 353 *active_speed = IB_SPEED_QDR; 354 break; 355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 358 *active_width = IB_WIDTH_1X; 359 *active_speed = IB_SPEED_EDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_QDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_HDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_FDR; 377 break; 378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 382 *active_width = IB_WIDTH_4X; 383 *active_speed = IB_SPEED_EDR; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 393 u8 *active_width) 394 { 395 switch (eth_proto_oper) { 396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_SDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_DDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 406 *active_width = IB_WIDTH_1X; 407 *active_speed = IB_SPEED_QDR; 408 break; 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_EDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 418 *active_width = IB_WIDTH_2X; 419 *active_speed = IB_SPEED_EDR; 420 break; 421 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 422 *active_width = IB_WIDTH_1X; 423 *active_speed = IB_SPEED_HDR; 424 break; 425 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 430 *active_width = IB_WIDTH_2X; 431 *active_speed = IB_SPEED_HDR; 432 break; 433 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 434 *active_width = IB_WIDTH_4X; 435 *active_speed = IB_SPEED_HDR; 436 break; 437 default: 438 return -EINVAL; 439 } 440 441 return 0; 442 } 443 444 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 445 u8 *active_width, bool ext) 446 { 447 return ext ? 448 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 449 active_width) : 450 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 451 active_width); 452 } 453 454 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 455 struct ib_port_attr *props) 456 { 457 struct mlx5_ib_dev *dev = to_mdev(device); 458 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 459 struct mlx5_core_dev *mdev; 460 struct net_device *ndev, *upper; 461 enum ib_mtu ndev_ib_mtu; 462 bool put_mdev = true; 463 u16 qkey_viol_cntr; 464 u32 eth_prot_oper; 465 u8 mdev_port_num; 466 bool ext; 467 int err; 468 469 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 470 if (!mdev) { 471 /* This means the port isn't affiliated yet. Get the 472 * info for the master port instead. 473 */ 474 put_mdev = false; 475 mdev = dev->mdev; 476 mdev_port_num = 1; 477 port_num = 1; 478 } 479 480 /* Possible bad flows are checked before filling out props so in case 481 * of an error it will still be zeroed out. 482 */ 483 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 484 mdev_port_num); 485 if (err) 486 goto out; 487 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 488 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 489 490 props->active_width = IB_WIDTH_4X; 491 props->active_speed = IB_SPEED_QDR; 492 493 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 494 &props->active_width, ext); 495 496 props->port_cap_flags |= IB_PORT_CM_SUP; 497 props->ip_gids = true; 498 499 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 500 roce_address_table_size); 501 props->max_mtu = IB_MTU_4096; 502 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 503 props->pkey_tbl_len = 1; 504 props->state = IB_PORT_DOWN; 505 props->phys_state = 3; 506 507 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 508 props->qkey_viol_cntr = qkey_viol_cntr; 509 510 /* If this is a stub query for an unaffiliated port stop here */ 511 if (!put_mdev) 512 goto out; 513 514 ndev = mlx5_ib_get_netdev(device, port_num); 515 if (!ndev) 516 goto out; 517 518 if (dev->lag_active) { 519 rcu_read_lock(); 520 upper = netdev_master_upper_dev_get_rcu(ndev); 521 if (upper) { 522 dev_put(ndev); 523 ndev = upper; 524 dev_hold(ndev); 525 } 526 rcu_read_unlock(); 527 } 528 529 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 530 props->state = IB_PORT_ACTIVE; 531 props->phys_state = 5; 532 } 533 534 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 535 536 dev_put(ndev); 537 538 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 539 out: 540 if (put_mdev) 541 mlx5_ib_put_native_port_mdev(dev, port_num); 542 return err; 543 } 544 545 struct mlx5_ib_vlan_info { 546 u16 vlan_id; 547 bool vlan; 548 }; 549 550 static int get_lower_dev_vlan(struct net_device *lower_dev, void *data) 551 { 552 struct mlx5_ib_vlan_info *vlan_info = data; 553 554 if (is_vlan_dev(lower_dev)) { 555 vlan_info->vlan = true; 556 vlan_info->vlan_id = vlan_dev_vlan_id(lower_dev); 557 } 558 /* We are interested only in first level vlan device, so 559 * always return 1 to stop iterating over next level devices. 560 */ 561 return 1; 562 } 563 564 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 565 unsigned int index, const union ib_gid *gid, 566 const struct ib_gid_attr *attr) 567 { 568 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 569 struct mlx5_ib_vlan_info vlan_info = { }; 570 u8 roce_version = 0; 571 u8 roce_l3_type = 0; 572 u8 mac[ETH_ALEN]; 573 574 if (gid) { 575 gid_type = attr->gid_type; 576 ether_addr_copy(mac, attr->ndev->dev_addr); 577 578 if (is_vlan_dev(attr->ndev)) { 579 vlan_info.vlan = true; 580 vlan_info.vlan_id = vlan_dev_vlan_id(attr->ndev); 581 } else { 582 /* If the netdev is upper device and if it's lower 583 * lower device is vlan device, consider vlan id of 584 * the lower vlan device for this gid entry. 585 */ 586 rcu_read_lock(); 587 netdev_walk_all_lower_dev_rcu(attr->ndev, 588 get_lower_dev_vlan, &vlan_info); 589 rcu_read_unlock(); 590 } 591 } 592 593 switch (gid_type) { 594 case IB_GID_TYPE_IB: 595 roce_version = MLX5_ROCE_VERSION_1; 596 break; 597 case IB_GID_TYPE_ROCE_UDP_ENCAP: 598 roce_version = MLX5_ROCE_VERSION_2; 599 if (ipv6_addr_v4mapped((void *)gid)) 600 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 601 else 602 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 603 break; 604 605 default: 606 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 607 } 608 609 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 610 roce_l3_type, gid->raw, mac, 611 vlan_info.vlan, vlan_info.vlan_id, 612 port_num); 613 } 614 615 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 616 __always_unused void **context) 617 { 618 return set_roce_addr(to_mdev(attr->device), attr->port_num, 619 attr->index, &attr->gid, attr); 620 } 621 622 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 623 __always_unused void **context) 624 { 625 return set_roce_addr(to_mdev(attr->device), attr->port_num, 626 attr->index, NULL, NULL); 627 } 628 629 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 630 const struct ib_gid_attr *attr) 631 { 632 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 633 return 0; 634 635 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 636 } 637 638 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 639 { 640 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 641 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 642 return 0; 643 } 644 645 enum { 646 MLX5_VPORT_ACCESS_METHOD_MAD, 647 MLX5_VPORT_ACCESS_METHOD_HCA, 648 MLX5_VPORT_ACCESS_METHOD_NIC, 649 }; 650 651 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 652 { 653 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 654 return MLX5_VPORT_ACCESS_METHOD_MAD; 655 656 if (mlx5_ib_port_link_layer(ibdev, 1) == 657 IB_LINK_LAYER_ETHERNET) 658 return MLX5_VPORT_ACCESS_METHOD_NIC; 659 660 return MLX5_VPORT_ACCESS_METHOD_HCA; 661 } 662 663 static void get_atomic_caps(struct mlx5_ib_dev *dev, 664 u8 atomic_size_qp, 665 struct ib_device_attr *props) 666 { 667 u8 tmp; 668 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 669 u8 atomic_req_8B_endianness_mode = 670 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 671 672 /* Check if HW supports 8 bytes standard atomic operations and capable 673 * of host endianness respond 674 */ 675 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 676 if (((atomic_operations & tmp) == tmp) && 677 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 678 (atomic_req_8B_endianness_mode)) { 679 props->atomic_cap = IB_ATOMIC_HCA; 680 } else { 681 props->atomic_cap = IB_ATOMIC_NONE; 682 } 683 } 684 685 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 686 struct ib_device_attr *props) 687 { 688 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 689 690 get_atomic_caps(dev, atomic_size_qp, props); 691 } 692 693 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 694 struct ib_device_attr *props) 695 { 696 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 697 698 get_atomic_caps(dev, atomic_size_qp, props); 699 } 700 701 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 702 { 703 struct ib_device_attr props = {}; 704 705 get_atomic_caps_dc(dev, &props); 706 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 707 } 708 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 709 __be64 *sys_image_guid) 710 { 711 struct mlx5_ib_dev *dev = to_mdev(ibdev); 712 struct mlx5_core_dev *mdev = dev->mdev; 713 u64 tmp; 714 int err; 715 716 switch (mlx5_get_vport_access_method(ibdev)) { 717 case MLX5_VPORT_ACCESS_METHOD_MAD: 718 return mlx5_query_mad_ifc_system_image_guid(ibdev, 719 sys_image_guid); 720 721 case MLX5_VPORT_ACCESS_METHOD_HCA: 722 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 723 break; 724 725 case MLX5_VPORT_ACCESS_METHOD_NIC: 726 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 727 break; 728 729 default: 730 return -EINVAL; 731 } 732 733 if (!err) 734 *sys_image_guid = cpu_to_be64(tmp); 735 736 return err; 737 738 } 739 740 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 741 u16 *max_pkeys) 742 { 743 struct mlx5_ib_dev *dev = to_mdev(ibdev); 744 struct mlx5_core_dev *mdev = dev->mdev; 745 746 switch (mlx5_get_vport_access_method(ibdev)) { 747 case MLX5_VPORT_ACCESS_METHOD_MAD: 748 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 749 750 case MLX5_VPORT_ACCESS_METHOD_HCA: 751 case MLX5_VPORT_ACCESS_METHOD_NIC: 752 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 753 pkey_table_size)); 754 return 0; 755 756 default: 757 return -EINVAL; 758 } 759 } 760 761 static int mlx5_query_vendor_id(struct ib_device *ibdev, 762 u32 *vendor_id) 763 { 764 struct mlx5_ib_dev *dev = to_mdev(ibdev); 765 766 switch (mlx5_get_vport_access_method(ibdev)) { 767 case MLX5_VPORT_ACCESS_METHOD_MAD: 768 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 769 770 case MLX5_VPORT_ACCESS_METHOD_HCA: 771 case MLX5_VPORT_ACCESS_METHOD_NIC: 772 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 773 774 default: 775 return -EINVAL; 776 } 777 } 778 779 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 780 __be64 *node_guid) 781 { 782 u64 tmp; 783 int err; 784 785 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 786 case MLX5_VPORT_ACCESS_METHOD_MAD: 787 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 788 789 case MLX5_VPORT_ACCESS_METHOD_HCA: 790 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 791 break; 792 793 case MLX5_VPORT_ACCESS_METHOD_NIC: 794 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 795 break; 796 797 default: 798 return -EINVAL; 799 } 800 801 if (!err) 802 *node_guid = cpu_to_be64(tmp); 803 804 return err; 805 } 806 807 struct mlx5_reg_node_desc { 808 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 809 }; 810 811 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 812 { 813 struct mlx5_reg_node_desc in; 814 815 if (mlx5_use_mad_ifc(dev)) 816 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 817 818 memset(&in, 0, sizeof(in)); 819 820 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 821 sizeof(struct mlx5_reg_node_desc), 822 MLX5_REG_NODE_DESC, 0, 0); 823 } 824 825 static int mlx5_ib_query_device(struct ib_device *ibdev, 826 struct ib_device_attr *props, 827 struct ib_udata *uhw) 828 { 829 struct mlx5_ib_dev *dev = to_mdev(ibdev); 830 struct mlx5_core_dev *mdev = dev->mdev; 831 int err = -ENOMEM; 832 int max_sq_desc; 833 int max_rq_sg; 834 int max_sq_sg; 835 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 836 bool raw_support = !mlx5_core_mp_enabled(mdev); 837 struct mlx5_ib_query_device_resp resp = {}; 838 size_t resp_len; 839 u64 max_tso; 840 841 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 842 if (uhw->outlen && uhw->outlen < resp_len) 843 return -EINVAL; 844 else 845 resp.response_length = resp_len; 846 847 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 848 return -EINVAL; 849 850 memset(props, 0, sizeof(*props)); 851 err = mlx5_query_system_image_guid(ibdev, 852 &props->sys_image_guid); 853 if (err) 854 return err; 855 856 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 857 if (err) 858 return err; 859 860 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 861 if (err) 862 return err; 863 864 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 865 (fw_rev_min(dev->mdev) << 16) | 866 fw_rev_sub(dev->mdev); 867 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 868 IB_DEVICE_PORT_ACTIVE_EVENT | 869 IB_DEVICE_SYS_IMAGE_GUID | 870 IB_DEVICE_RC_RNR_NAK_GEN; 871 872 if (MLX5_CAP_GEN(mdev, pkv)) 873 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 874 if (MLX5_CAP_GEN(mdev, qkv)) 875 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 876 if (MLX5_CAP_GEN(mdev, apm)) 877 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 878 if (MLX5_CAP_GEN(mdev, xrc)) 879 props->device_cap_flags |= IB_DEVICE_XRC; 880 if (MLX5_CAP_GEN(mdev, imaicl)) { 881 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 882 IB_DEVICE_MEM_WINDOW_TYPE_2B; 883 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 884 /* We support 'Gappy' memory registration too */ 885 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 886 } 887 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 888 if (MLX5_CAP_GEN(mdev, sho)) { 889 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 890 /* At this stage no support for signature handover */ 891 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 892 IB_PROT_T10DIF_TYPE_2 | 893 IB_PROT_T10DIF_TYPE_3; 894 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 895 IB_GUARD_T10DIF_CSUM; 896 } 897 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 898 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 899 900 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 901 if (MLX5_CAP_ETH(mdev, csum_cap)) { 902 /* Legacy bit to support old userspace libraries */ 903 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 904 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 905 } 906 907 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 908 props->raw_packet_caps |= 909 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 910 911 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 912 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 913 if (max_tso) { 914 resp.tso_caps.max_tso = 1 << max_tso; 915 resp.tso_caps.supported_qpts |= 916 1 << IB_QPT_RAW_PACKET; 917 resp.response_length += sizeof(resp.tso_caps); 918 } 919 } 920 921 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 922 resp.rss_caps.rx_hash_function = 923 MLX5_RX_HASH_FUNC_TOEPLITZ; 924 resp.rss_caps.rx_hash_fields_mask = 925 MLX5_RX_HASH_SRC_IPV4 | 926 MLX5_RX_HASH_DST_IPV4 | 927 MLX5_RX_HASH_SRC_IPV6 | 928 MLX5_RX_HASH_DST_IPV6 | 929 MLX5_RX_HASH_SRC_PORT_TCP | 930 MLX5_RX_HASH_DST_PORT_TCP | 931 MLX5_RX_HASH_SRC_PORT_UDP | 932 MLX5_RX_HASH_DST_PORT_UDP | 933 MLX5_RX_HASH_INNER; 934 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 935 MLX5_ACCEL_IPSEC_CAP_DEVICE) 936 resp.rss_caps.rx_hash_fields_mask |= 937 MLX5_RX_HASH_IPSEC_SPI; 938 resp.response_length += sizeof(resp.rss_caps); 939 } 940 } else { 941 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 942 resp.response_length += sizeof(resp.tso_caps); 943 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 944 resp.response_length += sizeof(resp.rss_caps); 945 } 946 947 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 948 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 949 props->device_cap_flags |= IB_DEVICE_UD_TSO; 950 } 951 952 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 953 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 954 raw_support) 955 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 956 957 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 958 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 959 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 960 961 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 962 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 963 raw_support) { 964 /* Legacy bit to support old userspace libraries */ 965 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 966 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 967 } 968 969 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 970 props->max_dm_size = 971 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 972 } 973 974 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 975 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 976 977 if (MLX5_CAP_GEN(mdev, end_pad)) 978 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 979 980 props->vendor_part_id = mdev->pdev->device; 981 props->hw_ver = mdev->pdev->revision; 982 983 props->max_mr_size = ~0ull; 984 props->page_size_cap = ~(min_page_size - 1); 985 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 986 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 987 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 988 sizeof(struct mlx5_wqe_data_seg); 989 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 990 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 991 sizeof(struct mlx5_wqe_raddr_seg)) / 992 sizeof(struct mlx5_wqe_data_seg); 993 props->max_send_sge = max_sq_sg; 994 props->max_recv_sge = max_rq_sg; 995 props->max_sge_rd = MLX5_MAX_SGE_RD; 996 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 997 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 998 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 999 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1000 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1001 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1002 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1003 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1004 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1005 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1006 props->max_srq_sge = max_rq_sg - 1; 1007 props->max_fast_reg_page_list_len = 1008 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1009 get_atomic_caps_qp(dev, props); 1010 props->masked_atomic_cap = IB_ATOMIC_NONE; 1011 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1012 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1013 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1014 props->max_mcast_grp; 1015 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 1016 props->max_ah = INT_MAX; 1017 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1018 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1019 1020 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1021 if (MLX5_CAP_GEN(mdev, pg)) 1022 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1023 props->odp_caps = dev->odp_caps; 1024 } 1025 1026 if (MLX5_CAP_GEN(mdev, cd)) 1027 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1028 1029 if (!mlx5_core_is_pf(mdev)) 1030 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1031 1032 if (mlx5_ib_port_link_layer(ibdev, 1) == 1033 IB_LINK_LAYER_ETHERNET && raw_support) { 1034 props->rss_caps.max_rwq_indirection_tables = 1035 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1036 props->rss_caps.max_rwq_indirection_table_size = 1037 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1038 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1039 props->max_wq_type_rq = 1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1041 } 1042 1043 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1044 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1045 props->tm_caps.max_num_tags = 1046 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1047 props->tm_caps.flags = IB_TM_CAP_RC; 1048 props->tm_caps.max_ops = 1049 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1050 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1051 } 1052 1053 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1054 props->cq_caps.max_cq_moderation_count = 1055 MLX5_MAX_CQ_COUNT; 1056 props->cq_caps.max_cq_moderation_period = 1057 MLX5_MAX_CQ_PERIOD; 1058 } 1059 1060 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 1061 resp.response_length += sizeof(resp.cqe_comp_caps); 1062 1063 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1064 resp.cqe_comp_caps.max_num = 1065 MLX5_CAP_GEN(dev->mdev, 1066 cqe_compression_max_num); 1067 1068 resp.cqe_comp_caps.supported_format = 1069 MLX5_IB_CQE_RES_FORMAT_HASH | 1070 MLX5_IB_CQE_RES_FORMAT_CSUM; 1071 1072 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1073 resp.cqe_comp_caps.supported_format |= 1074 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1075 } 1076 } 1077 1078 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 1079 raw_support) { 1080 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1081 MLX5_CAP_GEN(mdev, qos)) { 1082 resp.packet_pacing_caps.qp_rate_limit_max = 1083 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1084 resp.packet_pacing_caps.qp_rate_limit_min = 1085 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1086 resp.packet_pacing_caps.supported_qpts |= 1087 1 << IB_QPT_RAW_PACKET; 1088 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1089 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1090 resp.packet_pacing_caps.cap_flags |= 1091 MLX5_IB_PP_SUPPORT_BURST; 1092 } 1093 resp.response_length += sizeof(resp.packet_pacing_caps); 1094 } 1095 1096 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 1097 uhw->outlen)) { 1098 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1099 resp.mlx5_ib_support_multi_pkt_send_wqes = 1100 MLX5_IB_ALLOW_MPW; 1101 1102 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1103 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1104 MLX5_IB_SUPPORT_EMPW; 1105 1106 resp.response_length += 1107 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1108 } 1109 1110 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1111 resp.response_length += sizeof(resp.flags); 1112 1113 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1114 resp.flags |= 1115 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1116 1117 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1118 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1119 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1120 resp.flags |= 1121 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1122 1123 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1124 } 1125 1126 if (field_avail(typeof(resp), sw_parsing_caps, 1127 uhw->outlen)) { 1128 resp.response_length += sizeof(resp.sw_parsing_caps); 1129 if (MLX5_CAP_ETH(mdev, swp)) { 1130 resp.sw_parsing_caps.sw_parsing_offloads |= 1131 MLX5_IB_SW_PARSING; 1132 1133 if (MLX5_CAP_ETH(mdev, swp_csum)) 1134 resp.sw_parsing_caps.sw_parsing_offloads |= 1135 MLX5_IB_SW_PARSING_CSUM; 1136 1137 if (MLX5_CAP_ETH(mdev, swp_lso)) 1138 resp.sw_parsing_caps.sw_parsing_offloads |= 1139 MLX5_IB_SW_PARSING_LSO; 1140 1141 if (resp.sw_parsing_caps.sw_parsing_offloads) 1142 resp.sw_parsing_caps.supported_qpts = 1143 BIT(IB_QPT_RAW_PACKET); 1144 } 1145 } 1146 1147 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1148 raw_support) { 1149 resp.response_length += sizeof(resp.striding_rq_caps); 1150 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1151 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1152 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1153 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1154 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1155 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1156 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1157 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1158 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1159 resp.striding_rq_caps.supported_qpts = 1160 BIT(IB_QPT_RAW_PACKET); 1161 } 1162 } 1163 1164 if (field_avail(typeof(resp), tunnel_offloads_caps, 1165 uhw->outlen)) { 1166 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1167 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1168 resp.tunnel_offloads_caps |= 1169 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1171 resp.tunnel_offloads_caps |= 1172 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1173 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1174 resp.tunnel_offloads_caps |= 1175 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1176 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1177 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1178 resp.tunnel_offloads_caps |= 1179 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1180 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1181 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1182 resp.tunnel_offloads_caps |= 1183 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1184 } 1185 1186 if (uhw->outlen) { 1187 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1188 1189 if (err) 1190 return err; 1191 } 1192 1193 return 0; 1194 } 1195 1196 enum mlx5_ib_width { 1197 MLX5_IB_WIDTH_1X = 1 << 0, 1198 MLX5_IB_WIDTH_2X = 1 << 1, 1199 MLX5_IB_WIDTH_4X = 1 << 2, 1200 MLX5_IB_WIDTH_8X = 1 << 3, 1201 MLX5_IB_WIDTH_12X = 1 << 4 1202 }; 1203 1204 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1205 u8 *ib_width) 1206 { 1207 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1208 1209 if (active_width & MLX5_IB_WIDTH_1X) 1210 *ib_width = IB_WIDTH_1X; 1211 else if (active_width & MLX5_IB_WIDTH_2X) 1212 *ib_width = IB_WIDTH_2X; 1213 else if (active_width & MLX5_IB_WIDTH_4X) 1214 *ib_width = IB_WIDTH_4X; 1215 else if (active_width & MLX5_IB_WIDTH_8X) 1216 *ib_width = IB_WIDTH_8X; 1217 else if (active_width & MLX5_IB_WIDTH_12X) 1218 *ib_width = IB_WIDTH_12X; 1219 else { 1220 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1221 (int)active_width); 1222 *ib_width = IB_WIDTH_4X; 1223 } 1224 1225 return; 1226 } 1227 1228 static int mlx5_mtu_to_ib_mtu(int mtu) 1229 { 1230 switch (mtu) { 1231 case 256: return 1; 1232 case 512: return 2; 1233 case 1024: return 3; 1234 case 2048: return 4; 1235 case 4096: return 5; 1236 default: 1237 pr_warn("invalid mtu\n"); 1238 return -1; 1239 } 1240 } 1241 1242 enum ib_max_vl_num { 1243 __IB_MAX_VL_0 = 1, 1244 __IB_MAX_VL_0_1 = 2, 1245 __IB_MAX_VL_0_3 = 3, 1246 __IB_MAX_VL_0_7 = 4, 1247 __IB_MAX_VL_0_14 = 5, 1248 }; 1249 1250 enum mlx5_vl_hw_cap { 1251 MLX5_VL_HW_0 = 1, 1252 MLX5_VL_HW_0_1 = 2, 1253 MLX5_VL_HW_0_2 = 3, 1254 MLX5_VL_HW_0_3 = 4, 1255 MLX5_VL_HW_0_4 = 5, 1256 MLX5_VL_HW_0_5 = 6, 1257 MLX5_VL_HW_0_6 = 7, 1258 MLX5_VL_HW_0_7 = 8, 1259 MLX5_VL_HW_0_14 = 15 1260 }; 1261 1262 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1263 u8 *max_vl_num) 1264 { 1265 switch (vl_hw_cap) { 1266 case MLX5_VL_HW_0: 1267 *max_vl_num = __IB_MAX_VL_0; 1268 break; 1269 case MLX5_VL_HW_0_1: 1270 *max_vl_num = __IB_MAX_VL_0_1; 1271 break; 1272 case MLX5_VL_HW_0_3: 1273 *max_vl_num = __IB_MAX_VL_0_3; 1274 break; 1275 case MLX5_VL_HW_0_7: 1276 *max_vl_num = __IB_MAX_VL_0_7; 1277 break; 1278 case MLX5_VL_HW_0_14: 1279 *max_vl_num = __IB_MAX_VL_0_14; 1280 break; 1281 1282 default: 1283 return -EINVAL; 1284 } 1285 1286 return 0; 1287 } 1288 1289 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1290 struct ib_port_attr *props) 1291 { 1292 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1293 struct mlx5_core_dev *mdev = dev->mdev; 1294 struct mlx5_hca_vport_context *rep; 1295 u16 max_mtu; 1296 u16 oper_mtu; 1297 int err; 1298 u8 ib_link_width_oper; 1299 u8 vl_hw_cap; 1300 1301 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1302 if (!rep) { 1303 err = -ENOMEM; 1304 goto out; 1305 } 1306 1307 /* props being zeroed by the caller, avoid zeroing it here */ 1308 1309 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1310 if (err) 1311 goto out; 1312 1313 props->lid = rep->lid; 1314 props->lmc = rep->lmc; 1315 props->sm_lid = rep->sm_lid; 1316 props->sm_sl = rep->sm_sl; 1317 props->state = rep->vport_state; 1318 props->phys_state = rep->port_physical_state; 1319 props->port_cap_flags = rep->cap_mask1; 1320 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1321 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1322 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1323 props->bad_pkey_cntr = rep->pkey_violation_counter; 1324 props->qkey_viol_cntr = rep->qkey_violation_counter; 1325 props->subnet_timeout = rep->subnet_timeout; 1326 props->init_type_reply = rep->init_type_reply; 1327 1328 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1329 props->port_cap_flags2 = rep->cap_mask2; 1330 1331 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1332 if (err) 1333 goto out; 1334 1335 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1336 1337 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1338 if (err) 1339 goto out; 1340 1341 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1342 1343 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1344 1345 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1346 1347 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1348 1349 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1350 if (err) 1351 goto out; 1352 1353 err = translate_max_vl_num(ibdev, vl_hw_cap, 1354 &props->max_vl_num); 1355 out: 1356 kfree(rep); 1357 return err; 1358 } 1359 1360 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1361 struct ib_port_attr *props) 1362 { 1363 unsigned int count; 1364 int ret; 1365 1366 switch (mlx5_get_vport_access_method(ibdev)) { 1367 case MLX5_VPORT_ACCESS_METHOD_MAD: 1368 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1369 break; 1370 1371 case MLX5_VPORT_ACCESS_METHOD_HCA: 1372 ret = mlx5_query_hca_port(ibdev, port, props); 1373 break; 1374 1375 case MLX5_VPORT_ACCESS_METHOD_NIC: 1376 ret = mlx5_query_port_roce(ibdev, port, props); 1377 break; 1378 1379 default: 1380 ret = -EINVAL; 1381 } 1382 1383 if (!ret && props) { 1384 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1385 struct mlx5_core_dev *mdev; 1386 bool put_mdev = true; 1387 1388 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1389 if (!mdev) { 1390 /* If the port isn't affiliated yet query the master. 1391 * The master and slave will have the same values. 1392 */ 1393 mdev = dev->mdev; 1394 port = 1; 1395 put_mdev = false; 1396 } 1397 count = mlx5_core_reserved_gids_count(mdev); 1398 if (put_mdev) 1399 mlx5_ib_put_native_port_mdev(dev, port); 1400 props->gid_tbl_len -= count; 1401 } 1402 return ret; 1403 } 1404 1405 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1406 struct ib_port_attr *props) 1407 { 1408 int ret; 1409 1410 /* Only link layer == ethernet is valid for representors */ 1411 ret = mlx5_query_port_roce(ibdev, port, props); 1412 if (ret || !props) 1413 return ret; 1414 1415 /* We don't support GIDS */ 1416 props->gid_tbl_len = 0; 1417 1418 return ret; 1419 } 1420 1421 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1422 union ib_gid *gid) 1423 { 1424 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1425 struct mlx5_core_dev *mdev = dev->mdev; 1426 1427 switch (mlx5_get_vport_access_method(ibdev)) { 1428 case MLX5_VPORT_ACCESS_METHOD_MAD: 1429 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1430 1431 case MLX5_VPORT_ACCESS_METHOD_HCA: 1432 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1433 1434 default: 1435 return -EINVAL; 1436 } 1437 1438 } 1439 1440 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1441 u16 index, u16 *pkey) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct mlx5_core_dev *mdev; 1445 bool put_mdev = true; 1446 u8 mdev_port_num; 1447 int err; 1448 1449 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1450 if (!mdev) { 1451 /* The port isn't affiliated yet, get the PKey from the master 1452 * port. For RoCE the PKey tables will be the same. 1453 */ 1454 put_mdev = false; 1455 mdev = dev->mdev; 1456 mdev_port_num = 1; 1457 } 1458 1459 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1460 index, pkey); 1461 if (put_mdev) 1462 mlx5_ib_put_native_port_mdev(dev, port); 1463 1464 return err; 1465 } 1466 1467 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1468 u16 *pkey) 1469 { 1470 switch (mlx5_get_vport_access_method(ibdev)) { 1471 case MLX5_VPORT_ACCESS_METHOD_MAD: 1472 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1473 1474 case MLX5_VPORT_ACCESS_METHOD_HCA: 1475 case MLX5_VPORT_ACCESS_METHOD_NIC: 1476 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1477 default: 1478 return -EINVAL; 1479 } 1480 } 1481 1482 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1483 struct ib_device_modify *props) 1484 { 1485 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1486 struct mlx5_reg_node_desc in; 1487 struct mlx5_reg_node_desc out; 1488 int err; 1489 1490 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1491 return -EOPNOTSUPP; 1492 1493 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1494 return 0; 1495 1496 /* 1497 * If possible, pass node desc to FW, so it can generate 1498 * a 144 trap. If cmd fails, just ignore. 1499 */ 1500 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1501 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1502 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1503 if (err) 1504 return err; 1505 1506 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1507 1508 return err; 1509 } 1510 1511 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1512 u32 value) 1513 { 1514 struct mlx5_hca_vport_context ctx = {}; 1515 struct mlx5_core_dev *mdev; 1516 u8 mdev_port_num; 1517 int err; 1518 1519 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1520 if (!mdev) 1521 return -ENODEV; 1522 1523 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1524 if (err) 1525 goto out; 1526 1527 if (~ctx.cap_mask1_perm & mask) { 1528 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1529 mask, ctx.cap_mask1_perm); 1530 err = -EINVAL; 1531 goto out; 1532 } 1533 1534 ctx.cap_mask1 = value; 1535 ctx.cap_mask1_perm = mask; 1536 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1537 0, &ctx); 1538 1539 out: 1540 mlx5_ib_put_native_port_mdev(dev, port_num); 1541 1542 return err; 1543 } 1544 1545 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1546 struct ib_port_modify *props) 1547 { 1548 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1549 struct ib_port_attr attr; 1550 u32 tmp; 1551 int err; 1552 u32 change_mask; 1553 u32 value; 1554 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1555 IB_LINK_LAYER_INFINIBAND); 1556 1557 /* CM layer calls ib_modify_port() regardless of the link layer. For 1558 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1559 */ 1560 if (!is_ib) 1561 return 0; 1562 1563 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1564 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1565 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1566 return set_port_caps_atomic(dev, port, change_mask, value); 1567 } 1568 1569 mutex_lock(&dev->cap_mask_mutex); 1570 1571 err = ib_query_port(ibdev, port, &attr); 1572 if (err) 1573 goto out; 1574 1575 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1576 ~props->clr_port_cap_mask; 1577 1578 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1579 1580 out: 1581 mutex_unlock(&dev->cap_mask_mutex); 1582 return err; 1583 } 1584 1585 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1586 { 1587 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1588 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1589 } 1590 1591 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1592 { 1593 /* Large page with non 4k uar support might limit the dynamic size */ 1594 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1595 return MLX5_MIN_DYN_BFREGS; 1596 1597 return MLX5_MAX_DYN_BFREGS; 1598 } 1599 1600 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1601 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1602 struct mlx5_bfreg_info *bfregi) 1603 { 1604 int uars_per_sys_page; 1605 int bfregs_per_sys_page; 1606 int ref_bfregs = req->total_num_bfregs; 1607 1608 if (req->total_num_bfregs == 0) 1609 return -EINVAL; 1610 1611 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1612 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1613 1614 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1615 return -ENOMEM; 1616 1617 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1618 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1619 /* This holds the required static allocation asked by the user */ 1620 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1621 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1622 return -EINVAL; 1623 1624 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1625 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1626 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1627 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1628 1629 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1630 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1631 lib_uar_4k ? "yes" : "no", ref_bfregs, 1632 req->total_num_bfregs, bfregi->total_num_bfregs, 1633 bfregi->num_sys_pages); 1634 1635 return 0; 1636 } 1637 1638 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1639 { 1640 struct mlx5_bfreg_info *bfregi; 1641 int err; 1642 int i; 1643 1644 bfregi = &context->bfregi; 1645 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1646 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1647 if (err) 1648 goto error; 1649 1650 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1651 } 1652 1653 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1654 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1655 1656 return 0; 1657 1658 error: 1659 for (--i; i >= 0; i--) 1660 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1661 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1662 1663 return err; 1664 } 1665 1666 static void deallocate_uars(struct mlx5_ib_dev *dev, 1667 struct mlx5_ib_ucontext *context) 1668 { 1669 struct mlx5_bfreg_info *bfregi; 1670 int i; 1671 1672 bfregi = &context->bfregi; 1673 for (i = 0; i < bfregi->num_sys_pages; i++) 1674 if (i < bfregi->num_static_sys_pages || 1675 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1676 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1677 } 1678 1679 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1680 { 1681 int err = 0; 1682 1683 mutex_lock(&dev->lb.mutex); 1684 if (td) 1685 dev->lb.user_td++; 1686 if (qp) 1687 dev->lb.qps++; 1688 1689 if (dev->lb.user_td == 2 || 1690 dev->lb.qps == 1) { 1691 if (!dev->lb.enabled) { 1692 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1693 dev->lb.enabled = true; 1694 } 1695 } 1696 1697 mutex_unlock(&dev->lb.mutex); 1698 1699 return err; 1700 } 1701 1702 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1703 { 1704 mutex_lock(&dev->lb.mutex); 1705 if (td) 1706 dev->lb.user_td--; 1707 if (qp) 1708 dev->lb.qps--; 1709 1710 if (dev->lb.user_td == 1 && 1711 dev->lb.qps == 0) { 1712 if (dev->lb.enabled) { 1713 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1714 dev->lb.enabled = false; 1715 } 1716 } 1717 1718 mutex_unlock(&dev->lb.mutex); 1719 } 1720 1721 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1722 u16 uid) 1723 { 1724 int err; 1725 1726 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1727 return 0; 1728 1729 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1730 if (err) 1731 return err; 1732 1733 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1734 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1735 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1736 return err; 1737 1738 return mlx5_ib_enable_lb(dev, true, false); 1739 } 1740 1741 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1742 u16 uid) 1743 { 1744 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1745 return; 1746 1747 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1748 1749 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1750 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1751 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1752 return; 1753 1754 mlx5_ib_disable_lb(dev, true, false); 1755 } 1756 1757 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1758 struct ib_udata *udata) 1759 { 1760 struct ib_device *ibdev = uctx->device; 1761 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1762 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1763 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1764 struct mlx5_core_dev *mdev = dev->mdev; 1765 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1766 struct mlx5_bfreg_info *bfregi; 1767 int ver; 1768 int err; 1769 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1770 max_cqe_version); 1771 u32 dump_fill_mkey; 1772 bool lib_uar_4k; 1773 1774 if (!dev->ib_active) 1775 return -EAGAIN; 1776 1777 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1778 ver = 0; 1779 else if (udata->inlen >= min_req_v2) 1780 ver = 2; 1781 else 1782 return -EINVAL; 1783 1784 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1785 if (err) 1786 return err; 1787 1788 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1789 return -EOPNOTSUPP; 1790 1791 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1792 return -EOPNOTSUPP; 1793 1794 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1795 MLX5_NON_FP_BFREGS_PER_UAR); 1796 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1797 return -EINVAL; 1798 1799 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1800 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1801 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1802 resp.cache_line_size = cache_line_size(); 1803 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1804 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1805 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1806 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1807 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1808 resp.cqe_version = min_t(__u8, 1809 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1810 req.max_cqe_version); 1811 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1812 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1813 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1814 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1815 resp.response_length = min(offsetof(typeof(resp), response_length) + 1816 sizeof(resp.response_length), udata->outlen); 1817 1818 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1819 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1820 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1821 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1822 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1823 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1824 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1825 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1826 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1827 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1828 } 1829 1830 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1831 bfregi = &context->bfregi; 1832 1833 /* updates req->total_num_bfregs */ 1834 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1835 if (err) 1836 goto out_ctx; 1837 1838 mutex_init(&bfregi->lock); 1839 bfregi->lib_uar_4k = lib_uar_4k; 1840 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1841 GFP_KERNEL); 1842 if (!bfregi->count) { 1843 err = -ENOMEM; 1844 goto out_ctx; 1845 } 1846 1847 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1848 sizeof(*bfregi->sys_pages), 1849 GFP_KERNEL); 1850 if (!bfregi->sys_pages) { 1851 err = -ENOMEM; 1852 goto out_count; 1853 } 1854 1855 err = allocate_uars(dev, context); 1856 if (err) 1857 goto out_sys_pages; 1858 1859 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING) 1860 context->ibucontext.invalidate_range = 1861 &mlx5_ib_invalidate_range; 1862 1863 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1864 err = mlx5_ib_devx_create(dev, true); 1865 if (err < 0) 1866 goto out_uars; 1867 context->devx_uid = err; 1868 } 1869 1870 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1871 context->devx_uid); 1872 if (err) 1873 goto out_devx; 1874 1875 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1876 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1877 if (err) 1878 goto out_mdev; 1879 } 1880 1881 INIT_LIST_HEAD(&context->db_page_list); 1882 mutex_init(&context->db_page_mutex); 1883 1884 resp.tot_bfregs = req.total_num_bfregs; 1885 resp.num_ports = dev->num_ports; 1886 1887 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1888 resp.response_length += sizeof(resp.cqe_version); 1889 1890 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1891 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1892 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1893 resp.response_length += sizeof(resp.cmds_supp_uhw); 1894 } 1895 1896 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1897 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1898 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1899 resp.eth_min_inline++; 1900 } 1901 resp.response_length += sizeof(resp.eth_min_inline); 1902 } 1903 1904 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1905 if (mdev->clock_info) 1906 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1907 resp.response_length += sizeof(resp.clock_info_versions); 1908 } 1909 1910 /* 1911 * We don't want to expose information from the PCI bar that is located 1912 * after 4096 bytes, so if the arch only supports larger pages, let's 1913 * pretend we don't support reading the HCA's core clock. This is also 1914 * forced by mmap function. 1915 */ 1916 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1917 if (PAGE_SIZE <= 4096) { 1918 resp.comp_mask |= 1919 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1920 resp.hca_core_clock_offset = 1921 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1922 } 1923 resp.response_length += sizeof(resp.hca_core_clock_offset); 1924 } 1925 1926 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1927 resp.response_length += sizeof(resp.log_uar_size); 1928 1929 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1930 resp.response_length += sizeof(resp.num_uars_per_page); 1931 1932 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1933 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1934 resp.response_length += sizeof(resp.num_dyn_bfregs); 1935 } 1936 1937 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1938 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1939 resp.dump_fill_mkey = dump_fill_mkey; 1940 resp.comp_mask |= 1941 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1942 } 1943 resp.response_length += sizeof(resp.dump_fill_mkey); 1944 } 1945 1946 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1947 if (err) 1948 goto out_mdev; 1949 1950 bfregi->ver = ver; 1951 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1952 context->cqe_version = resp.cqe_version; 1953 context->lib_caps = req.lib_caps; 1954 print_lib_caps(dev, context->lib_caps); 1955 1956 if (dev->lag_active) { 1957 u8 port = mlx5_core_native_port_num(dev->mdev); 1958 1959 atomic_set(&context->tx_port_affinity, 1960 atomic_add_return( 1961 1, &dev->roce[port].tx_port_affinity)); 1962 } 1963 1964 return 0; 1965 1966 out_mdev: 1967 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1968 out_devx: 1969 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1970 mlx5_ib_devx_destroy(dev, context->devx_uid); 1971 1972 out_uars: 1973 deallocate_uars(dev, context); 1974 1975 out_sys_pages: 1976 kfree(bfregi->sys_pages); 1977 1978 out_count: 1979 kfree(bfregi->count); 1980 1981 out_ctx: 1982 return err; 1983 } 1984 1985 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1986 { 1987 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1988 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1989 struct mlx5_bfreg_info *bfregi; 1990 1991 /* All umem's must be destroyed before destroying the ucontext. */ 1992 mutex_lock(&ibcontext->per_mm_list_lock); 1993 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1994 mutex_unlock(&ibcontext->per_mm_list_lock); 1995 1996 bfregi = &context->bfregi; 1997 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1998 1999 if (context->devx_uid) 2000 mlx5_ib_devx_destroy(dev, context->devx_uid); 2001 2002 deallocate_uars(dev, context); 2003 kfree(bfregi->sys_pages); 2004 kfree(bfregi->count); 2005 } 2006 2007 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2008 int uar_idx) 2009 { 2010 int fw_uars_per_page; 2011 2012 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2013 2014 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2015 } 2016 2017 static int get_command(unsigned long offset) 2018 { 2019 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2020 } 2021 2022 static int get_arg(unsigned long offset) 2023 { 2024 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2025 } 2026 2027 static int get_index(unsigned long offset) 2028 { 2029 return get_arg(offset); 2030 } 2031 2032 /* Index resides in an extra byte to enable larger values than 255 */ 2033 static int get_extended_index(unsigned long offset) 2034 { 2035 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2036 } 2037 2038 2039 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2040 { 2041 } 2042 2043 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2044 { 2045 switch (cmd) { 2046 case MLX5_IB_MMAP_WC_PAGE: 2047 return "WC"; 2048 case MLX5_IB_MMAP_REGULAR_PAGE: 2049 return "best effort WC"; 2050 case MLX5_IB_MMAP_NC_PAGE: 2051 return "NC"; 2052 case MLX5_IB_MMAP_DEVICE_MEM: 2053 return "Device Memory"; 2054 default: 2055 return NULL; 2056 } 2057 } 2058 2059 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2060 struct vm_area_struct *vma, 2061 struct mlx5_ib_ucontext *context) 2062 { 2063 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2064 return -EINVAL; 2065 2066 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2067 return -EOPNOTSUPP; 2068 2069 if (vma->vm_flags & VM_WRITE) 2070 return -EPERM; 2071 vma->vm_flags &= ~VM_MAYWRITE; 2072 2073 if (!dev->mdev->clock_info_page) 2074 return -EOPNOTSUPP; 2075 2076 return rdma_user_mmap_page(&context->ibucontext, vma, 2077 dev->mdev->clock_info_page, PAGE_SIZE); 2078 } 2079 2080 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2081 struct vm_area_struct *vma, 2082 struct mlx5_ib_ucontext *context) 2083 { 2084 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2085 int err; 2086 unsigned long idx; 2087 phys_addr_t pfn; 2088 pgprot_t prot; 2089 u32 bfreg_dyn_idx = 0; 2090 u32 uar_index; 2091 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2092 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2093 bfregi->num_static_sys_pages; 2094 2095 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2096 return -EINVAL; 2097 2098 if (dyn_uar) 2099 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2100 else 2101 idx = get_index(vma->vm_pgoff); 2102 2103 if (idx >= max_valid_idx) { 2104 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2105 idx, max_valid_idx); 2106 return -EINVAL; 2107 } 2108 2109 switch (cmd) { 2110 case MLX5_IB_MMAP_WC_PAGE: 2111 case MLX5_IB_MMAP_ALLOC_WC: 2112 /* Some architectures don't support WC memory */ 2113 #if defined(CONFIG_X86) 2114 if (!pat_enabled()) 2115 return -EPERM; 2116 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2117 return -EPERM; 2118 #endif 2119 /* fall through */ 2120 case MLX5_IB_MMAP_REGULAR_PAGE: 2121 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2122 prot = pgprot_writecombine(vma->vm_page_prot); 2123 break; 2124 case MLX5_IB_MMAP_NC_PAGE: 2125 prot = pgprot_noncached(vma->vm_page_prot); 2126 break; 2127 default: 2128 return -EINVAL; 2129 } 2130 2131 if (dyn_uar) { 2132 int uars_per_page; 2133 2134 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2135 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2136 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2137 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2138 bfreg_dyn_idx, bfregi->total_num_bfregs); 2139 return -EINVAL; 2140 } 2141 2142 mutex_lock(&bfregi->lock); 2143 /* Fail if uar already allocated, first bfreg index of each 2144 * page holds its count. 2145 */ 2146 if (bfregi->count[bfreg_dyn_idx]) { 2147 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2148 mutex_unlock(&bfregi->lock); 2149 return -EINVAL; 2150 } 2151 2152 bfregi->count[bfreg_dyn_idx]++; 2153 mutex_unlock(&bfregi->lock); 2154 2155 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2156 if (err) { 2157 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2158 goto free_bfreg; 2159 } 2160 } else { 2161 uar_index = bfregi->sys_pages[idx]; 2162 } 2163 2164 pfn = uar_index2pfn(dev, uar_index); 2165 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2166 2167 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2168 prot); 2169 if (err) { 2170 mlx5_ib_err(dev, 2171 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2172 err, mmap_cmd2str(cmd)); 2173 goto err; 2174 } 2175 2176 if (dyn_uar) 2177 bfregi->sys_pages[idx] = uar_index; 2178 return 0; 2179 2180 err: 2181 if (!dyn_uar) 2182 return err; 2183 2184 mlx5_cmd_free_uar(dev->mdev, idx); 2185 2186 free_bfreg: 2187 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2188 2189 return err; 2190 } 2191 2192 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2193 { 2194 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2195 struct mlx5_ib_dev *dev = to_mdev(context->device); 2196 u16 page_idx = get_extended_index(vma->vm_pgoff); 2197 size_t map_size = vma->vm_end - vma->vm_start; 2198 u32 npages = map_size >> PAGE_SHIFT; 2199 phys_addr_t pfn; 2200 2201 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2202 page_idx + npages) 2203 return -EINVAL; 2204 2205 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2206 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2207 PAGE_SHIFT) + 2208 page_idx; 2209 return rdma_user_mmap_io(context, vma, pfn, map_size, 2210 pgprot_writecombine(vma->vm_page_prot)); 2211 } 2212 2213 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2214 { 2215 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2216 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2217 unsigned long command; 2218 phys_addr_t pfn; 2219 2220 command = get_command(vma->vm_pgoff); 2221 switch (command) { 2222 case MLX5_IB_MMAP_WC_PAGE: 2223 case MLX5_IB_MMAP_NC_PAGE: 2224 case MLX5_IB_MMAP_REGULAR_PAGE: 2225 case MLX5_IB_MMAP_ALLOC_WC: 2226 return uar_mmap(dev, command, vma, context); 2227 2228 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2229 return -ENOSYS; 2230 2231 case MLX5_IB_MMAP_CORE_CLOCK: 2232 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2233 return -EINVAL; 2234 2235 if (vma->vm_flags & VM_WRITE) 2236 return -EPERM; 2237 vma->vm_flags &= ~VM_MAYWRITE; 2238 2239 /* Don't expose to user-space information it shouldn't have */ 2240 if (PAGE_SIZE > 4096) 2241 return -EOPNOTSUPP; 2242 2243 pfn = (dev->mdev->iseg_base + 2244 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2245 PAGE_SHIFT; 2246 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2247 PAGE_SIZE, 2248 pgprot_noncached(vma->vm_page_prot)); 2249 case MLX5_IB_MMAP_CLOCK_INFO: 2250 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2251 2252 case MLX5_IB_MMAP_DEVICE_MEM: 2253 return dm_mmap(ibcontext, vma); 2254 2255 default: 2256 return -EINVAL; 2257 } 2258 2259 return 0; 2260 } 2261 2262 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2263 struct ib_ucontext *context, 2264 struct ib_dm_alloc_attr *attr, 2265 struct uverbs_attr_bundle *attrs) 2266 { 2267 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2268 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2269 phys_addr_t memic_addr; 2270 struct mlx5_ib_dm *dm; 2271 u64 start_offset; 2272 u32 page_idx; 2273 int err; 2274 2275 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2276 if (!dm) 2277 return ERR_PTR(-ENOMEM); 2278 2279 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2280 attr->length, act_size, attr->alignment); 2281 2282 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2283 act_size, attr->alignment); 2284 if (err) 2285 goto err_free; 2286 2287 start_offset = memic_addr & ~PAGE_MASK; 2288 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2289 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2290 PAGE_SHIFT; 2291 2292 err = uverbs_copy_to(attrs, 2293 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2294 &start_offset, sizeof(start_offset)); 2295 if (err) 2296 goto err_dealloc; 2297 2298 err = uverbs_copy_to(attrs, 2299 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2300 &page_idx, sizeof(page_idx)); 2301 if (err) 2302 goto err_dealloc; 2303 2304 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2305 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2306 2307 dm->dev_addr = memic_addr; 2308 2309 return &dm->ibdm; 2310 2311 err_dealloc: 2312 mlx5_cmd_dealloc_memic(memic, memic_addr, 2313 act_size); 2314 err_free: 2315 kfree(dm); 2316 return ERR_PTR(err); 2317 } 2318 2319 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2320 { 2321 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2322 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2323 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2324 u32 page_idx; 2325 int ret; 2326 2327 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2328 if (ret) 2329 return ret; 2330 2331 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2332 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2333 PAGE_SHIFT; 2334 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2335 page_idx, 2336 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2337 2338 kfree(dm); 2339 2340 return 0; 2341 } 2342 2343 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_ucontext *context, 2344 struct ib_udata *udata) 2345 { 2346 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2347 struct ib_device *ibdev = ibpd->device; 2348 struct mlx5_ib_alloc_pd_resp resp; 2349 int err; 2350 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2351 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2352 u16 uid = 0; 2353 2354 uid = context ? to_mucontext(context)->devx_uid : 0; 2355 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2356 MLX5_SET(alloc_pd_in, in, uid, uid); 2357 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in), 2358 out, sizeof(out)); 2359 if (err) 2360 return err; 2361 2362 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2363 pd->uid = uid; 2364 if (context) { 2365 resp.pdn = pd->pdn; 2366 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2367 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2368 return -EFAULT; 2369 } 2370 } 2371 2372 return 0; 2373 } 2374 2375 static void mlx5_ib_dealloc_pd(struct ib_pd *pd) 2376 { 2377 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2378 struct mlx5_ib_pd *mpd = to_mpd(pd); 2379 2380 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2381 } 2382 2383 enum { 2384 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2385 MATCH_CRITERIA_ENABLE_MISC_BIT, 2386 MATCH_CRITERIA_ENABLE_INNER_BIT, 2387 MATCH_CRITERIA_ENABLE_MISC2_BIT 2388 }; 2389 2390 #define HEADER_IS_ZERO(match_criteria, headers) \ 2391 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2392 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2393 2394 static u8 get_match_criteria_enable(u32 *match_criteria) 2395 { 2396 u8 match_criteria_enable; 2397 2398 match_criteria_enable = 2399 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2400 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2401 match_criteria_enable |= 2402 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2403 MATCH_CRITERIA_ENABLE_MISC_BIT; 2404 match_criteria_enable |= 2405 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2406 MATCH_CRITERIA_ENABLE_INNER_BIT; 2407 match_criteria_enable |= 2408 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2409 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2410 2411 return match_criteria_enable; 2412 } 2413 2414 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2415 { 2416 u8 entry_mask; 2417 u8 entry_val; 2418 int err = 0; 2419 2420 if (!mask) 2421 goto out; 2422 2423 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c, 2424 ip_protocol); 2425 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v, 2426 ip_protocol); 2427 if (!entry_mask) { 2428 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2429 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2430 goto out; 2431 } 2432 /* Don't override existing ip protocol */ 2433 if (mask != entry_mask || val != entry_val) 2434 err = -EINVAL; 2435 out: 2436 return err; 2437 } 2438 2439 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2440 bool inner) 2441 { 2442 if (inner) { 2443 MLX5_SET(fte_match_set_misc, 2444 misc_c, inner_ipv6_flow_label, mask); 2445 MLX5_SET(fte_match_set_misc, 2446 misc_v, inner_ipv6_flow_label, val); 2447 } else { 2448 MLX5_SET(fte_match_set_misc, 2449 misc_c, outer_ipv6_flow_label, mask); 2450 MLX5_SET(fte_match_set_misc, 2451 misc_v, outer_ipv6_flow_label, val); 2452 } 2453 } 2454 2455 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2456 { 2457 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2458 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2459 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2460 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2461 } 2462 2463 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2464 { 2465 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2466 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2467 return -EOPNOTSUPP; 2468 2469 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2470 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2471 return -EOPNOTSUPP; 2472 2473 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2474 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2475 return -EOPNOTSUPP; 2476 2477 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2478 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2479 return -EOPNOTSUPP; 2480 2481 return 0; 2482 } 2483 2484 #define LAST_ETH_FIELD vlan_tag 2485 #define LAST_IB_FIELD sl 2486 #define LAST_IPV4_FIELD tos 2487 #define LAST_IPV6_FIELD traffic_class 2488 #define LAST_TCP_UDP_FIELD src_port 2489 #define LAST_TUNNEL_FIELD tunnel_id 2490 #define LAST_FLOW_TAG_FIELD tag_id 2491 #define LAST_DROP_FIELD size 2492 #define LAST_COUNTERS_FIELD counters 2493 2494 /* Field is the last supported field */ 2495 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2496 memchr_inv((void *)&filter.field +\ 2497 sizeof(filter.field), 0,\ 2498 sizeof(filter) -\ 2499 offsetof(typeof(filter), field) -\ 2500 sizeof(filter.field)) 2501 2502 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2503 bool is_egress, 2504 struct mlx5_flow_act *action) 2505 { 2506 2507 switch (maction->ib_action.type) { 2508 case IB_FLOW_ACTION_ESP: 2509 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2510 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2511 return -EINVAL; 2512 /* Currently only AES_GCM keymat is supported by the driver */ 2513 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2514 action->action |= is_egress ? 2515 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2516 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2517 return 0; 2518 case IB_FLOW_ACTION_UNSPECIFIED: 2519 if (maction->flow_action_raw.sub_type == 2520 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2521 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2522 return -EINVAL; 2523 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2524 action->modify_id = maction->flow_action_raw.action_id; 2525 return 0; 2526 } 2527 if (maction->flow_action_raw.sub_type == 2528 MLX5_IB_FLOW_ACTION_DECAP) { 2529 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2530 return -EINVAL; 2531 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2532 return 0; 2533 } 2534 if (maction->flow_action_raw.sub_type == 2535 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2536 if (action->action & 2537 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2538 return -EINVAL; 2539 action->action |= 2540 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2541 action->reformat_id = 2542 maction->flow_action_raw.action_id; 2543 return 0; 2544 } 2545 /* fall through */ 2546 default: 2547 return -EOPNOTSUPP; 2548 } 2549 } 2550 2551 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2552 u32 *match_v, const union ib_flow_spec *ib_spec, 2553 const struct ib_flow_attr *flow_attr, 2554 struct mlx5_flow_act *action, u32 prev_type) 2555 { 2556 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2557 misc_parameters); 2558 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2559 misc_parameters); 2560 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2561 misc_parameters_2); 2562 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2563 misc_parameters_2); 2564 void *headers_c; 2565 void *headers_v; 2566 int match_ipv; 2567 int ret; 2568 2569 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2570 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2571 inner_headers); 2572 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2573 inner_headers); 2574 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2575 ft_field_support.inner_ip_version); 2576 } else { 2577 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2578 outer_headers); 2579 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2580 outer_headers); 2581 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2582 ft_field_support.outer_ip_version); 2583 } 2584 2585 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2586 case IB_FLOW_SPEC_ETH: 2587 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2588 return -EOPNOTSUPP; 2589 2590 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2591 dmac_47_16), 2592 ib_spec->eth.mask.dst_mac); 2593 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2594 dmac_47_16), 2595 ib_spec->eth.val.dst_mac); 2596 2597 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2598 smac_47_16), 2599 ib_spec->eth.mask.src_mac); 2600 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2601 smac_47_16), 2602 ib_spec->eth.val.src_mac); 2603 2604 if (ib_spec->eth.mask.vlan_tag) { 2605 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2606 cvlan_tag, 1); 2607 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2608 cvlan_tag, 1); 2609 2610 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2611 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2612 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2613 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2614 2615 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2616 first_cfi, 2617 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2618 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2619 first_cfi, 2620 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2621 2622 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2623 first_prio, 2624 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2626 first_prio, 2627 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2628 } 2629 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2630 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2632 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2633 break; 2634 case IB_FLOW_SPEC_IPV4: 2635 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2636 return -EOPNOTSUPP; 2637 2638 if (match_ipv) { 2639 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2640 ip_version, 0xf); 2641 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2642 ip_version, MLX5_FS_IPV4_VERSION); 2643 } else { 2644 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2645 ethertype, 0xffff); 2646 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2647 ethertype, ETH_P_IP); 2648 } 2649 2650 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2651 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2652 &ib_spec->ipv4.mask.src_ip, 2653 sizeof(ib_spec->ipv4.mask.src_ip)); 2654 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2655 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2656 &ib_spec->ipv4.val.src_ip, 2657 sizeof(ib_spec->ipv4.val.src_ip)); 2658 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2659 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2660 &ib_spec->ipv4.mask.dst_ip, 2661 sizeof(ib_spec->ipv4.mask.dst_ip)); 2662 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2663 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2664 &ib_spec->ipv4.val.dst_ip, 2665 sizeof(ib_spec->ipv4.val.dst_ip)); 2666 2667 set_tos(headers_c, headers_v, 2668 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2669 2670 if (set_proto(headers_c, headers_v, 2671 ib_spec->ipv4.mask.proto, 2672 ib_spec->ipv4.val.proto)) 2673 return -EINVAL; 2674 break; 2675 case IB_FLOW_SPEC_IPV6: 2676 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2677 return -EOPNOTSUPP; 2678 2679 if (match_ipv) { 2680 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2681 ip_version, 0xf); 2682 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2683 ip_version, MLX5_FS_IPV6_VERSION); 2684 } else { 2685 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2686 ethertype, 0xffff); 2687 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2688 ethertype, ETH_P_IPV6); 2689 } 2690 2691 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2692 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2693 &ib_spec->ipv6.mask.src_ip, 2694 sizeof(ib_spec->ipv6.mask.src_ip)); 2695 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2696 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2697 &ib_spec->ipv6.val.src_ip, 2698 sizeof(ib_spec->ipv6.val.src_ip)); 2699 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2700 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2701 &ib_spec->ipv6.mask.dst_ip, 2702 sizeof(ib_spec->ipv6.mask.dst_ip)); 2703 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2704 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2705 &ib_spec->ipv6.val.dst_ip, 2706 sizeof(ib_spec->ipv6.val.dst_ip)); 2707 2708 set_tos(headers_c, headers_v, 2709 ib_spec->ipv6.mask.traffic_class, 2710 ib_spec->ipv6.val.traffic_class); 2711 2712 if (set_proto(headers_c, headers_v, 2713 ib_spec->ipv6.mask.next_hdr, 2714 ib_spec->ipv6.val.next_hdr)) 2715 return -EINVAL; 2716 2717 set_flow_label(misc_params_c, misc_params_v, 2718 ntohl(ib_spec->ipv6.mask.flow_label), 2719 ntohl(ib_spec->ipv6.val.flow_label), 2720 ib_spec->type & IB_FLOW_SPEC_INNER); 2721 break; 2722 case IB_FLOW_SPEC_ESP: 2723 if (ib_spec->esp.mask.seq) 2724 return -EOPNOTSUPP; 2725 2726 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2727 ntohl(ib_spec->esp.mask.spi)); 2728 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2729 ntohl(ib_spec->esp.val.spi)); 2730 break; 2731 case IB_FLOW_SPEC_TCP: 2732 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2733 LAST_TCP_UDP_FIELD)) 2734 return -EOPNOTSUPP; 2735 2736 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP)) 2737 return -EINVAL; 2738 2739 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2740 ntohs(ib_spec->tcp_udp.mask.src_port)); 2741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2742 ntohs(ib_spec->tcp_udp.val.src_port)); 2743 2744 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2745 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2747 ntohs(ib_spec->tcp_udp.val.dst_port)); 2748 break; 2749 case IB_FLOW_SPEC_UDP: 2750 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2751 LAST_TCP_UDP_FIELD)) 2752 return -EOPNOTSUPP; 2753 2754 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP)) 2755 return -EINVAL; 2756 2757 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2758 ntohs(ib_spec->tcp_udp.mask.src_port)); 2759 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2760 ntohs(ib_spec->tcp_udp.val.src_port)); 2761 2762 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2763 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2764 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2765 ntohs(ib_spec->tcp_udp.val.dst_port)); 2766 break; 2767 case IB_FLOW_SPEC_GRE: 2768 if (ib_spec->gre.mask.c_ks_res0_ver) 2769 return -EOPNOTSUPP; 2770 2771 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE)) 2772 return -EINVAL; 2773 2774 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2775 0xff); 2776 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2777 IPPROTO_GRE); 2778 2779 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2780 ntohs(ib_spec->gre.mask.protocol)); 2781 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2782 ntohs(ib_spec->gre.val.protocol)); 2783 2784 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2785 gre_key.nvgre.hi), 2786 &ib_spec->gre.mask.key, 2787 sizeof(ib_spec->gre.mask.key)); 2788 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2789 gre_key.nvgre.hi), 2790 &ib_spec->gre.val.key, 2791 sizeof(ib_spec->gre.val.key)); 2792 break; 2793 case IB_FLOW_SPEC_MPLS: 2794 switch (prev_type) { 2795 case IB_FLOW_SPEC_UDP: 2796 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2797 ft_field_support.outer_first_mpls_over_udp), 2798 &ib_spec->mpls.mask.tag)) 2799 return -EOPNOTSUPP; 2800 2801 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2802 outer_first_mpls_over_udp), 2803 &ib_spec->mpls.val.tag, 2804 sizeof(ib_spec->mpls.val.tag)); 2805 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2806 outer_first_mpls_over_udp), 2807 &ib_spec->mpls.mask.tag, 2808 sizeof(ib_spec->mpls.mask.tag)); 2809 break; 2810 case IB_FLOW_SPEC_GRE: 2811 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2812 ft_field_support.outer_first_mpls_over_gre), 2813 &ib_spec->mpls.mask.tag)) 2814 return -EOPNOTSUPP; 2815 2816 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2817 outer_first_mpls_over_gre), 2818 &ib_spec->mpls.val.tag, 2819 sizeof(ib_spec->mpls.val.tag)); 2820 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2821 outer_first_mpls_over_gre), 2822 &ib_spec->mpls.mask.tag, 2823 sizeof(ib_spec->mpls.mask.tag)); 2824 break; 2825 default: 2826 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2827 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2828 ft_field_support.inner_first_mpls), 2829 &ib_spec->mpls.mask.tag)) 2830 return -EOPNOTSUPP; 2831 2832 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2833 inner_first_mpls), 2834 &ib_spec->mpls.val.tag, 2835 sizeof(ib_spec->mpls.val.tag)); 2836 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2837 inner_first_mpls), 2838 &ib_spec->mpls.mask.tag, 2839 sizeof(ib_spec->mpls.mask.tag)); 2840 } else { 2841 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2842 ft_field_support.outer_first_mpls), 2843 &ib_spec->mpls.mask.tag)) 2844 return -EOPNOTSUPP; 2845 2846 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2847 outer_first_mpls), 2848 &ib_spec->mpls.val.tag, 2849 sizeof(ib_spec->mpls.val.tag)); 2850 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2851 outer_first_mpls), 2852 &ib_spec->mpls.mask.tag, 2853 sizeof(ib_spec->mpls.mask.tag)); 2854 } 2855 } 2856 break; 2857 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2858 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2859 LAST_TUNNEL_FIELD)) 2860 return -EOPNOTSUPP; 2861 2862 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2863 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2864 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2865 ntohl(ib_spec->tunnel.val.tunnel_id)); 2866 break; 2867 case IB_FLOW_SPEC_ACTION_TAG: 2868 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2869 LAST_FLOW_TAG_FIELD)) 2870 return -EOPNOTSUPP; 2871 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2872 return -EINVAL; 2873 2874 action->flow_tag = ib_spec->flow_tag.tag_id; 2875 action->flags |= FLOW_ACT_HAS_TAG; 2876 break; 2877 case IB_FLOW_SPEC_ACTION_DROP: 2878 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2879 LAST_DROP_FIELD)) 2880 return -EOPNOTSUPP; 2881 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2882 break; 2883 case IB_FLOW_SPEC_ACTION_HANDLE: 2884 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 2885 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 2886 if (ret) 2887 return ret; 2888 break; 2889 case IB_FLOW_SPEC_ACTION_COUNT: 2890 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2891 LAST_COUNTERS_FIELD)) 2892 return -EOPNOTSUPP; 2893 2894 /* for now support only one counters spec per flow */ 2895 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2896 return -EINVAL; 2897 2898 action->counters = ib_spec->flow_count.counters; 2899 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2900 break; 2901 default: 2902 return -EINVAL; 2903 } 2904 2905 return 0; 2906 } 2907 2908 /* If a flow could catch both multicast and unicast packets, 2909 * it won't fall into the multicast flow steering table and this rule 2910 * could steal other multicast packets. 2911 */ 2912 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2913 { 2914 union ib_flow_spec *flow_spec; 2915 2916 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2917 ib_attr->num_of_specs < 1) 2918 return false; 2919 2920 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2921 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2922 struct ib_flow_spec_ipv4 *ipv4_spec; 2923 2924 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2925 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2926 return true; 2927 2928 return false; 2929 } 2930 2931 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2932 struct ib_flow_spec_eth *eth_spec; 2933 2934 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2935 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2936 is_multicast_ether_addr(eth_spec->val.dst_mac); 2937 } 2938 2939 return false; 2940 } 2941 2942 enum valid_spec { 2943 VALID_SPEC_INVALID, 2944 VALID_SPEC_VALID, 2945 VALID_SPEC_NA, 2946 }; 2947 2948 static enum valid_spec 2949 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2950 const struct mlx5_flow_spec *spec, 2951 const struct mlx5_flow_act *flow_act, 2952 bool egress) 2953 { 2954 const u32 *match_c = spec->match_criteria; 2955 bool is_crypto = 2956 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2957 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2958 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2959 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2960 2961 /* 2962 * Currently only crypto is supported in egress, when regular egress 2963 * rules would be supported, always return VALID_SPEC_NA. 2964 */ 2965 if (!is_crypto) 2966 return VALID_SPEC_NA; 2967 2968 return is_crypto && is_ipsec && 2969 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ? 2970 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2971 } 2972 2973 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2974 const struct mlx5_flow_spec *spec, 2975 const struct mlx5_flow_act *flow_act, 2976 bool egress) 2977 { 2978 /* We curretly only support ipsec egress flow */ 2979 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2980 } 2981 2982 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2983 const struct ib_flow_attr *flow_attr, 2984 bool check_inner) 2985 { 2986 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2987 int match_ipv = check_inner ? 2988 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2989 ft_field_support.inner_ip_version) : 2990 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2991 ft_field_support.outer_ip_version); 2992 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2993 bool ipv4_spec_valid, ipv6_spec_valid; 2994 unsigned int ip_spec_type = 0; 2995 bool has_ethertype = false; 2996 unsigned int spec_index; 2997 bool mask_valid = true; 2998 u16 eth_type = 0; 2999 bool type_valid; 3000 3001 /* Validate that ethertype is correct */ 3002 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3003 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 3004 ib_spec->eth.mask.ether_type) { 3005 mask_valid = (ib_spec->eth.mask.ether_type == 3006 htons(0xffff)); 3007 has_ethertype = true; 3008 eth_type = ntohs(ib_spec->eth.val.ether_type); 3009 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 3010 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 3011 ip_spec_type = ib_spec->type; 3012 } 3013 ib_spec = (void *)ib_spec + ib_spec->size; 3014 } 3015 3016 type_valid = (!has_ethertype) || (!ip_spec_type); 3017 if (!type_valid && mask_valid) { 3018 ipv4_spec_valid = (eth_type == ETH_P_IP) && 3019 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 3020 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 3021 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 3022 3023 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 3024 (((eth_type == ETH_P_MPLS_UC) || 3025 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 3026 } 3027 3028 return type_valid; 3029 } 3030 3031 static bool is_valid_attr(struct mlx5_core_dev *mdev, 3032 const struct ib_flow_attr *flow_attr) 3033 { 3034 return is_valid_ethertype(mdev, flow_attr, false) && 3035 is_valid_ethertype(mdev, flow_attr, true); 3036 } 3037 3038 static void put_flow_table(struct mlx5_ib_dev *dev, 3039 struct mlx5_ib_flow_prio *prio, bool ft_added) 3040 { 3041 prio->refcount -= !!ft_added; 3042 if (!prio->refcount) { 3043 mlx5_destroy_flow_table(prio->flow_table); 3044 prio->flow_table = NULL; 3045 } 3046 } 3047 3048 static void counters_clear_description(struct ib_counters *counters) 3049 { 3050 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3051 3052 mutex_lock(&mcounters->mcntrs_mutex); 3053 kfree(mcounters->counters_data); 3054 mcounters->counters_data = NULL; 3055 mcounters->cntrs_max_index = 0; 3056 mutex_unlock(&mcounters->mcntrs_mutex); 3057 } 3058 3059 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 3060 { 3061 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 3062 struct mlx5_ib_flow_handler, 3063 ibflow); 3064 struct mlx5_ib_flow_handler *iter, *tmp; 3065 struct mlx5_ib_dev *dev = handler->dev; 3066 3067 mutex_lock(&dev->flow_db->lock); 3068 3069 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 3070 mlx5_del_flow_rules(iter->rule); 3071 put_flow_table(dev, iter->prio, true); 3072 list_del(&iter->list); 3073 kfree(iter); 3074 } 3075 3076 mlx5_del_flow_rules(handler->rule); 3077 put_flow_table(dev, handler->prio, true); 3078 if (handler->ibcounters && 3079 atomic_read(&handler->ibcounters->usecnt) == 1) 3080 counters_clear_description(handler->ibcounters); 3081 3082 mutex_unlock(&dev->flow_db->lock); 3083 if (handler->flow_matcher) 3084 atomic_dec(&handler->flow_matcher->usecnt); 3085 kfree(handler); 3086 3087 return 0; 3088 } 3089 3090 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 3091 { 3092 priority *= 2; 3093 if (!dont_trap) 3094 priority++; 3095 return priority; 3096 } 3097 3098 enum flow_table_type { 3099 MLX5_IB_FT_RX, 3100 MLX5_IB_FT_TX 3101 }; 3102 3103 #define MLX5_FS_MAX_TYPES 6 3104 #define MLX5_FS_MAX_ENTRIES BIT(16) 3105 3106 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3107 struct mlx5_ib_flow_prio *prio, 3108 int priority, 3109 int num_entries, int num_groups, 3110 u32 flags) 3111 { 3112 struct mlx5_flow_table *ft; 3113 3114 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3115 num_entries, 3116 num_groups, 3117 0, flags); 3118 if (IS_ERR(ft)) 3119 return ERR_CAST(ft); 3120 3121 prio->flow_table = ft; 3122 prio->refcount = 0; 3123 return prio; 3124 } 3125 3126 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3127 struct ib_flow_attr *flow_attr, 3128 enum flow_table_type ft_type) 3129 { 3130 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3131 struct mlx5_flow_namespace *ns = NULL; 3132 struct mlx5_ib_flow_prio *prio; 3133 struct mlx5_flow_table *ft; 3134 int max_table_size; 3135 int num_entries; 3136 int num_groups; 3137 u32 flags = 0; 3138 int priority; 3139 3140 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3141 log_max_ft_size)); 3142 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3143 enum mlx5_flow_namespace_type fn_type; 3144 3145 if (flow_is_multicast_only(flow_attr) && 3146 !dont_trap) 3147 priority = MLX5_IB_FLOW_MCAST_PRIO; 3148 else 3149 priority = ib_prio_to_core_prio(flow_attr->priority, 3150 dont_trap); 3151 if (ft_type == MLX5_IB_FT_RX) { 3152 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3153 prio = &dev->flow_db->prios[priority]; 3154 if (!dev->rep && 3155 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3156 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3157 if (!dev->rep && 3158 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3159 reformat_l3_tunnel_to_l2)) 3160 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3161 } else { 3162 max_table_size = 3163 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3164 log_max_ft_size)); 3165 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3166 prio = &dev->flow_db->egress_prios[priority]; 3167 if (!dev->rep && 3168 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3169 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3170 } 3171 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3172 num_entries = MLX5_FS_MAX_ENTRIES; 3173 num_groups = MLX5_FS_MAX_TYPES; 3174 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3175 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3176 ns = mlx5_get_flow_namespace(dev->mdev, 3177 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3178 build_leftovers_ft_param(&priority, 3179 &num_entries, 3180 &num_groups); 3181 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3182 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3183 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3184 allow_sniffer_and_nic_rx_shared_tir)) 3185 return ERR_PTR(-ENOTSUPP); 3186 3187 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3188 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3189 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3190 3191 prio = &dev->flow_db->sniffer[ft_type]; 3192 priority = 0; 3193 num_entries = 1; 3194 num_groups = 1; 3195 } 3196 3197 if (!ns) 3198 return ERR_PTR(-ENOTSUPP); 3199 3200 if (num_entries > max_table_size) 3201 return ERR_PTR(-ENOMEM); 3202 3203 ft = prio->flow_table; 3204 if (!ft) 3205 return _get_prio(ns, prio, priority, num_entries, num_groups, 3206 flags); 3207 3208 return prio; 3209 } 3210 3211 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3212 struct mlx5_flow_spec *spec, 3213 u32 underlay_qpn) 3214 { 3215 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3216 spec->match_criteria, 3217 misc_parameters); 3218 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3219 misc_parameters); 3220 3221 if (underlay_qpn && 3222 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3223 ft_field_support.bth_dst_qp)) { 3224 MLX5_SET(fte_match_set_misc, 3225 misc_params_v, bth_dst_qp, underlay_qpn); 3226 MLX5_SET(fte_match_set_misc, 3227 misc_params_c, bth_dst_qp, 0xffffff); 3228 } 3229 } 3230 3231 static int read_flow_counters(struct ib_device *ibdev, 3232 struct mlx5_read_counters_attr *read_attr) 3233 { 3234 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3235 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3236 3237 return mlx5_fc_query(dev->mdev, fc, 3238 &read_attr->out[IB_COUNTER_PACKETS], 3239 &read_attr->out[IB_COUNTER_BYTES]); 3240 } 3241 3242 /* flow counters currently expose two counters packets and bytes */ 3243 #define FLOW_COUNTERS_NUM 2 3244 static int counters_set_description(struct ib_counters *counters, 3245 enum mlx5_ib_counters_type counters_type, 3246 struct mlx5_ib_flow_counters_desc *desc_data, 3247 u32 ncounters) 3248 { 3249 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3250 u32 cntrs_max_index = 0; 3251 int i; 3252 3253 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3254 return -EINVAL; 3255 3256 /* init the fields for the object */ 3257 mcounters->type = counters_type; 3258 mcounters->read_counters = read_flow_counters; 3259 mcounters->counters_num = FLOW_COUNTERS_NUM; 3260 mcounters->ncounters = ncounters; 3261 /* each counter entry have both description and index pair */ 3262 for (i = 0; i < ncounters; i++) { 3263 if (desc_data[i].description > IB_COUNTER_BYTES) 3264 return -EINVAL; 3265 3266 if (cntrs_max_index <= desc_data[i].index) 3267 cntrs_max_index = desc_data[i].index + 1; 3268 } 3269 3270 mutex_lock(&mcounters->mcntrs_mutex); 3271 mcounters->counters_data = desc_data; 3272 mcounters->cntrs_max_index = cntrs_max_index; 3273 mutex_unlock(&mcounters->mcntrs_mutex); 3274 3275 return 0; 3276 } 3277 3278 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3279 static int flow_counters_set_data(struct ib_counters *ibcounters, 3280 struct mlx5_ib_create_flow *ucmd) 3281 { 3282 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3283 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3284 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3285 bool hw_hndl = false; 3286 int ret = 0; 3287 3288 if (ucmd && ucmd->ncounters_data != 0) { 3289 cntrs_data = ucmd->data; 3290 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3291 return -EINVAL; 3292 3293 desc_data = kcalloc(cntrs_data->ncounters, 3294 sizeof(*desc_data), 3295 GFP_KERNEL); 3296 if (!desc_data) 3297 return -ENOMEM; 3298 3299 if (copy_from_user(desc_data, 3300 u64_to_user_ptr(cntrs_data->counters_data), 3301 sizeof(*desc_data) * cntrs_data->ncounters)) { 3302 ret = -EFAULT; 3303 goto free; 3304 } 3305 } 3306 3307 if (!mcounters->hw_cntrs_hndl) { 3308 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3309 to_mdev(ibcounters->device)->mdev, false); 3310 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3311 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3312 goto free; 3313 } 3314 hw_hndl = true; 3315 } 3316 3317 if (desc_data) { 3318 /* counters already bound to at least one flow */ 3319 if (mcounters->cntrs_max_index) { 3320 ret = -EINVAL; 3321 goto free_hndl; 3322 } 3323 3324 ret = counters_set_description(ibcounters, 3325 MLX5_IB_COUNTERS_FLOW, 3326 desc_data, 3327 cntrs_data->ncounters); 3328 if (ret) 3329 goto free_hndl; 3330 3331 } else if (!mcounters->cntrs_max_index) { 3332 /* counters not bound yet, must have udata passed */ 3333 ret = -EINVAL; 3334 goto free_hndl; 3335 } 3336 3337 return 0; 3338 3339 free_hndl: 3340 if (hw_hndl) { 3341 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3342 mcounters->hw_cntrs_hndl); 3343 mcounters->hw_cntrs_hndl = NULL; 3344 } 3345 free: 3346 kfree(desc_data); 3347 return ret; 3348 } 3349 3350 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3351 struct mlx5_ib_flow_prio *ft_prio, 3352 const struct ib_flow_attr *flow_attr, 3353 struct mlx5_flow_destination *dst, 3354 u32 underlay_qpn, 3355 struct mlx5_ib_create_flow *ucmd) 3356 { 3357 struct mlx5_flow_table *ft = ft_prio->flow_table; 3358 struct mlx5_ib_flow_handler *handler; 3359 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3360 struct mlx5_flow_spec *spec; 3361 struct mlx5_flow_destination dest_arr[2] = {}; 3362 struct mlx5_flow_destination *rule_dst = dest_arr; 3363 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3364 unsigned int spec_index; 3365 u32 prev_type = 0; 3366 int err = 0; 3367 int dest_num = 0; 3368 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3369 3370 if (!is_valid_attr(dev->mdev, flow_attr)) 3371 return ERR_PTR(-EINVAL); 3372 3373 if (dev->rep && is_egress) 3374 return ERR_PTR(-EINVAL); 3375 3376 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3377 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3378 if (!handler || !spec) { 3379 err = -ENOMEM; 3380 goto free; 3381 } 3382 3383 INIT_LIST_HEAD(&handler->list); 3384 if (dst) { 3385 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3386 dest_num++; 3387 } 3388 3389 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3390 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3391 spec->match_value, 3392 ib_flow, flow_attr, &flow_act, 3393 prev_type); 3394 if (err < 0) 3395 goto free; 3396 3397 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3398 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3399 } 3400 3401 if (!flow_is_multicast_only(flow_attr)) 3402 set_underlay_qp(dev, spec, underlay_qpn); 3403 3404 if (dev->rep) { 3405 void *misc; 3406 3407 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3408 misc_parameters); 3409 MLX5_SET(fte_match_set_misc, misc, source_port, 3410 dev->rep->vport); 3411 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3412 misc_parameters); 3413 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3414 } 3415 3416 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3417 3418 if (is_egress && 3419 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3420 err = -EINVAL; 3421 goto free; 3422 } 3423 3424 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3425 struct mlx5_ib_mcounters *mcounters; 3426 3427 err = flow_counters_set_data(flow_act.counters, ucmd); 3428 if (err) 3429 goto free; 3430 3431 mcounters = to_mcounters(flow_act.counters); 3432 handler->ibcounters = flow_act.counters; 3433 dest_arr[dest_num].type = 3434 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3435 dest_arr[dest_num].counter_id = 3436 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3437 dest_num++; 3438 } 3439 3440 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3441 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3442 rule_dst = NULL; 3443 dest_num = 0; 3444 } 3445 } else { 3446 if (is_egress) 3447 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3448 else 3449 flow_act.action |= 3450 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3451 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3452 } 3453 3454 if ((flow_act.flags & FLOW_ACT_HAS_TAG) && 3455 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3456 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3457 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3458 flow_act.flow_tag, flow_attr->type); 3459 err = -EINVAL; 3460 goto free; 3461 } 3462 handler->rule = mlx5_add_flow_rules(ft, spec, 3463 &flow_act, 3464 rule_dst, dest_num); 3465 3466 if (IS_ERR(handler->rule)) { 3467 err = PTR_ERR(handler->rule); 3468 goto free; 3469 } 3470 3471 ft_prio->refcount++; 3472 handler->prio = ft_prio; 3473 handler->dev = dev; 3474 3475 ft_prio->flow_table = ft; 3476 free: 3477 if (err && handler) { 3478 if (handler->ibcounters && 3479 atomic_read(&handler->ibcounters->usecnt) == 1) 3480 counters_clear_description(handler->ibcounters); 3481 kfree(handler); 3482 } 3483 kvfree(spec); 3484 return err ? ERR_PTR(err) : handler; 3485 } 3486 3487 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3488 struct mlx5_ib_flow_prio *ft_prio, 3489 const struct ib_flow_attr *flow_attr, 3490 struct mlx5_flow_destination *dst) 3491 { 3492 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3493 } 3494 3495 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3496 struct mlx5_ib_flow_prio *ft_prio, 3497 struct ib_flow_attr *flow_attr, 3498 struct mlx5_flow_destination *dst) 3499 { 3500 struct mlx5_ib_flow_handler *handler_dst = NULL; 3501 struct mlx5_ib_flow_handler *handler = NULL; 3502 3503 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3504 if (!IS_ERR(handler)) { 3505 handler_dst = create_flow_rule(dev, ft_prio, 3506 flow_attr, dst); 3507 if (IS_ERR(handler_dst)) { 3508 mlx5_del_flow_rules(handler->rule); 3509 ft_prio->refcount--; 3510 kfree(handler); 3511 handler = handler_dst; 3512 } else { 3513 list_add(&handler_dst->list, &handler->list); 3514 } 3515 } 3516 3517 return handler; 3518 } 3519 enum { 3520 LEFTOVERS_MC, 3521 LEFTOVERS_UC, 3522 }; 3523 3524 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3525 struct mlx5_ib_flow_prio *ft_prio, 3526 struct ib_flow_attr *flow_attr, 3527 struct mlx5_flow_destination *dst) 3528 { 3529 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3530 struct mlx5_ib_flow_handler *handler = NULL; 3531 3532 static struct { 3533 struct ib_flow_attr flow_attr; 3534 struct ib_flow_spec_eth eth_flow; 3535 } leftovers_specs[] = { 3536 [LEFTOVERS_MC] = { 3537 .flow_attr = { 3538 .num_of_specs = 1, 3539 .size = sizeof(leftovers_specs[0]) 3540 }, 3541 .eth_flow = { 3542 .type = IB_FLOW_SPEC_ETH, 3543 .size = sizeof(struct ib_flow_spec_eth), 3544 .mask = {.dst_mac = {0x1} }, 3545 .val = {.dst_mac = {0x1} } 3546 } 3547 }, 3548 [LEFTOVERS_UC] = { 3549 .flow_attr = { 3550 .num_of_specs = 1, 3551 .size = sizeof(leftovers_specs[0]) 3552 }, 3553 .eth_flow = { 3554 .type = IB_FLOW_SPEC_ETH, 3555 .size = sizeof(struct ib_flow_spec_eth), 3556 .mask = {.dst_mac = {0x1} }, 3557 .val = {.dst_mac = {} } 3558 } 3559 } 3560 }; 3561 3562 handler = create_flow_rule(dev, ft_prio, 3563 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3564 dst); 3565 if (!IS_ERR(handler) && 3566 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3567 handler_ucast = create_flow_rule(dev, ft_prio, 3568 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3569 dst); 3570 if (IS_ERR(handler_ucast)) { 3571 mlx5_del_flow_rules(handler->rule); 3572 ft_prio->refcount--; 3573 kfree(handler); 3574 handler = handler_ucast; 3575 } else { 3576 list_add(&handler_ucast->list, &handler->list); 3577 } 3578 } 3579 3580 return handler; 3581 } 3582 3583 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3584 struct mlx5_ib_flow_prio *ft_rx, 3585 struct mlx5_ib_flow_prio *ft_tx, 3586 struct mlx5_flow_destination *dst) 3587 { 3588 struct mlx5_ib_flow_handler *handler_rx; 3589 struct mlx5_ib_flow_handler *handler_tx; 3590 int err; 3591 static const struct ib_flow_attr flow_attr = { 3592 .num_of_specs = 0, 3593 .size = sizeof(flow_attr) 3594 }; 3595 3596 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3597 if (IS_ERR(handler_rx)) { 3598 err = PTR_ERR(handler_rx); 3599 goto err; 3600 } 3601 3602 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3603 if (IS_ERR(handler_tx)) { 3604 err = PTR_ERR(handler_tx); 3605 goto err_tx; 3606 } 3607 3608 list_add(&handler_tx->list, &handler_rx->list); 3609 3610 return handler_rx; 3611 3612 err_tx: 3613 mlx5_del_flow_rules(handler_rx->rule); 3614 ft_rx->refcount--; 3615 kfree(handler_rx); 3616 err: 3617 return ERR_PTR(err); 3618 } 3619 3620 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3621 struct ib_flow_attr *flow_attr, 3622 int domain, 3623 struct ib_udata *udata) 3624 { 3625 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3626 struct mlx5_ib_qp *mqp = to_mqp(qp); 3627 struct mlx5_ib_flow_handler *handler = NULL; 3628 struct mlx5_flow_destination *dst = NULL; 3629 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3630 struct mlx5_ib_flow_prio *ft_prio; 3631 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3632 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3633 size_t min_ucmd_sz, required_ucmd_sz; 3634 int err; 3635 int underlay_qpn; 3636 3637 if (udata && udata->inlen) { 3638 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3639 sizeof(ucmd_hdr.reserved); 3640 if (udata->inlen < min_ucmd_sz) 3641 return ERR_PTR(-EOPNOTSUPP); 3642 3643 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3644 if (err) 3645 return ERR_PTR(err); 3646 3647 /* currently supports only one counters data */ 3648 if (ucmd_hdr.ncounters_data > 1) 3649 return ERR_PTR(-EINVAL); 3650 3651 required_ucmd_sz = min_ucmd_sz + 3652 sizeof(struct mlx5_ib_flow_counters_data) * 3653 ucmd_hdr.ncounters_data; 3654 if (udata->inlen > required_ucmd_sz && 3655 !ib_is_udata_cleared(udata, required_ucmd_sz, 3656 udata->inlen - required_ucmd_sz)) 3657 return ERR_PTR(-EOPNOTSUPP); 3658 3659 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3660 if (!ucmd) 3661 return ERR_PTR(-ENOMEM); 3662 3663 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3664 if (err) 3665 goto free_ucmd; 3666 } 3667 3668 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3669 err = -ENOMEM; 3670 goto free_ucmd; 3671 } 3672 3673 if (domain != IB_FLOW_DOMAIN_USER || 3674 flow_attr->port > dev->num_ports || 3675 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3676 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3677 err = -EINVAL; 3678 goto free_ucmd; 3679 } 3680 3681 if (is_egress && 3682 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3683 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3684 err = -EINVAL; 3685 goto free_ucmd; 3686 } 3687 3688 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3689 if (!dst) { 3690 err = -ENOMEM; 3691 goto free_ucmd; 3692 } 3693 3694 mutex_lock(&dev->flow_db->lock); 3695 3696 ft_prio = get_flow_table(dev, flow_attr, 3697 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3698 if (IS_ERR(ft_prio)) { 3699 err = PTR_ERR(ft_prio); 3700 goto unlock; 3701 } 3702 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3703 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3704 if (IS_ERR(ft_prio_tx)) { 3705 err = PTR_ERR(ft_prio_tx); 3706 ft_prio_tx = NULL; 3707 goto destroy_ft; 3708 } 3709 } 3710 3711 if (is_egress) { 3712 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3713 } else { 3714 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3715 if (mqp->flags & MLX5_IB_QP_RSS) 3716 dst->tir_num = mqp->rss_qp.tirn; 3717 else 3718 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3719 } 3720 3721 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3722 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3723 handler = create_dont_trap_rule(dev, ft_prio, 3724 flow_attr, dst); 3725 } else { 3726 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3727 mqp->underlay_qpn : 0; 3728 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3729 dst, underlay_qpn, ucmd); 3730 } 3731 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3732 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3733 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3734 dst); 3735 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3736 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3737 } else { 3738 err = -EINVAL; 3739 goto destroy_ft; 3740 } 3741 3742 if (IS_ERR(handler)) { 3743 err = PTR_ERR(handler); 3744 handler = NULL; 3745 goto destroy_ft; 3746 } 3747 3748 mutex_unlock(&dev->flow_db->lock); 3749 kfree(dst); 3750 kfree(ucmd); 3751 3752 return &handler->ibflow; 3753 3754 destroy_ft: 3755 put_flow_table(dev, ft_prio, false); 3756 if (ft_prio_tx) 3757 put_flow_table(dev, ft_prio_tx, false); 3758 unlock: 3759 mutex_unlock(&dev->flow_db->lock); 3760 kfree(dst); 3761 free_ucmd: 3762 kfree(ucmd); 3763 return ERR_PTR(err); 3764 } 3765 3766 static struct mlx5_ib_flow_prio * 3767 _get_flow_table(struct mlx5_ib_dev *dev, 3768 struct mlx5_ib_flow_matcher *fs_matcher, 3769 bool mcast) 3770 { 3771 struct mlx5_flow_namespace *ns = NULL; 3772 struct mlx5_ib_flow_prio *prio; 3773 int max_table_size; 3774 u32 flags = 0; 3775 int priority; 3776 3777 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3778 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3779 log_max_ft_size)); 3780 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3781 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3782 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3783 reformat_l3_tunnel_to_l2)) 3784 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3785 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */ 3786 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3787 log_max_ft_size)); 3788 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3789 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3790 } 3791 3792 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3793 return ERR_PTR(-ENOMEM); 3794 3795 if (mcast) 3796 priority = MLX5_IB_FLOW_MCAST_PRIO; 3797 else 3798 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3799 3800 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3801 if (!ns) 3802 return ERR_PTR(-ENOTSUPP); 3803 3804 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3805 prio = &dev->flow_db->prios[priority]; 3806 else 3807 prio = &dev->flow_db->egress_prios[priority]; 3808 3809 if (prio->flow_table) 3810 return prio; 3811 3812 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3813 MLX5_FS_MAX_TYPES, flags); 3814 } 3815 3816 static struct mlx5_ib_flow_handler * 3817 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3818 struct mlx5_ib_flow_prio *ft_prio, 3819 struct mlx5_flow_destination *dst, 3820 struct mlx5_ib_flow_matcher *fs_matcher, 3821 struct mlx5_flow_act *flow_act, 3822 void *cmd_in, int inlen, 3823 int dst_num) 3824 { 3825 struct mlx5_ib_flow_handler *handler; 3826 struct mlx5_flow_spec *spec; 3827 struct mlx5_flow_table *ft = ft_prio->flow_table; 3828 int err = 0; 3829 3830 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3831 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3832 if (!handler || !spec) { 3833 err = -ENOMEM; 3834 goto free; 3835 } 3836 3837 INIT_LIST_HEAD(&handler->list); 3838 3839 memcpy(spec->match_value, cmd_in, inlen); 3840 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3841 fs_matcher->mask_len); 3842 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3843 3844 handler->rule = mlx5_add_flow_rules(ft, spec, 3845 flow_act, dst, dst_num); 3846 3847 if (IS_ERR(handler->rule)) { 3848 err = PTR_ERR(handler->rule); 3849 goto free; 3850 } 3851 3852 ft_prio->refcount++; 3853 handler->prio = ft_prio; 3854 handler->dev = dev; 3855 ft_prio->flow_table = ft; 3856 3857 free: 3858 if (err) 3859 kfree(handler); 3860 kvfree(spec); 3861 return err ? ERR_PTR(err) : handler; 3862 } 3863 3864 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3865 void *match_v) 3866 { 3867 void *match_c; 3868 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3869 void *dmac, *dmac_mask; 3870 void *ipv4, *ipv4_mask; 3871 3872 if (!(fs_matcher->match_criteria_enable & 3873 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3874 return false; 3875 3876 match_c = fs_matcher->matcher_mask.match_params; 3877 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3878 outer_headers); 3879 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3880 outer_headers); 3881 3882 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3883 dmac_47_16); 3884 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3885 dmac_47_16); 3886 3887 if (is_multicast_ether_addr(dmac) && 3888 is_multicast_ether_addr(dmac_mask)) 3889 return true; 3890 3891 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3892 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3893 3894 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3895 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3896 3897 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3898 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3899 return true; 3900 3901 return false; 3902 } 3903 3904 struct mlx5_ib_flow_handler * 3905 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3906 struct mlx5_ib_flow_matcher *fs_matcher, 3907 struct mlx5_flow_act *flow_act, 3908 u32 counter_id, 3909 void *cmd_in, int inlen, int dest_id, 3910 int dest_type) 3911 { 3912 struct mlx5_flow_destination *dst; 3913 struct mlx5_ib_flow_prio *ft_prio; 3914 struct mlx5_ib_flow_handler *handler; 3915 int dst_num = 0; 3916 bool mcast; 3917 int err; 3918 3919 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3920 return ERR_PTR(-EOPNOTSUPP); 3921 3922 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3923 return ERR_PTR(-ENOMEM); 3924 3925 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL); 3926 if (!dst) 3927 return ERR_PTR(-ENOMEM); 3928 3929 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3930 mutex_lock(&dev->flow_db->lock); 3931 3932 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 3933 if (IS_ERR(ft_prio)) { 3934 err = PTR_ERR(ft_prio); 3935 goto unlock; 3936 } 3937 3938 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3939 dst[dst_num].type = dest_type; 3940 dst[dst_num].tir_num = dest_id; 3941 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3942 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 3943 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3944 dst[dst_num].ft_num = dest_id; 3945 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3946 } else { 3947 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3948 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3949 } 3950 3951 dst_num++; 3952 3953 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3954 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3955 dst[dst_num].counter_id = counter_id; 3956 dst_num++; 3957 } 3958 3959 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 3960 cmd_in, inlen, dst_num); 3961 3962 if (IS_ERR(handler)) { 3963 err = PTR_ERR(handler); 3964 goto destroy_ft; 3965 } 3966 3967 mutex_unlock(&dev->flow_db->lock); 3968 atomic_inc(&fs_matcher->usecnt); 3969 handler->flow_matcher = fs_matcher; 3970 3971 kfree(dst); 3972 3973 return handler; 3974 3975 destroy_ft: 3976 put_flow_table(dev, ft_prio, false); 3977 unlock: 3978 mutex_unlock(&dev->flow_db->lock); 3979 kfree(dst); 3980 3981 return ERR_PTR(err); 3982 } 3983 3984 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3985 { 3986 u32 flags = 0; 3987 3988 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3989 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3990 3991 return flags; 3992 } 3993 3994 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3995 static struct ib_flow_action * 3996 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3997 const struct ib_flow_action_attrs_esp *attr, 3998 struct uverbs_attr_bundle *attrs) 3999 { 4000 struct mlx5_ib_dev *mdev = to_mdev(device); 4001 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 4002 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 4003 struct mlx5_ib_flow_action *action; 4004 u64 action_flags; 4005 u64 flags; 4006 int err = 0; 4007 4008 err = uverbs_get_flags64( 4009 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 4010 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 4011 if (err) 4012 return ERR_PTR(err); 4013 4014 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 4015 4016 /* We current only support a subset of the standard features. Only a 4017 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 4018 * (with overlap). Full offload mode isn't supported. 4019 */ 4020 if (!attr->keymat || attr->replay || attr->encap || 4021 attr->spi || attr->seq || attr->tfc_pad || 4022 attr->hard_limit_pkts || 4023 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4024 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 4025 return ERR_PTR(-EOPNOTSUPP); 4026 4027 if (attr->keymat->protocol != 4028 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 4029 return ERR_PTR(-EOPNOTSUPP); 4030 4031 aes_gcm = &attr->keymat->keymat.aes_gcm; 4032 4033 if (aes_gcm->icv_len != 16 || 4034 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 4035 return ERR_PTR(-EOPNOTSUPP); 4036 4037 action = kmalloc(sizeof(*action), GFP_KERNEL); 4038 if (!action) 4039 return ERR_PTR(-ENOMEM); 4040 4041 action->esp_aes_gcm.ib_flags = attr->flags; 4042 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 4043 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 4044 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 4045 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 4046 sizeof(accel_attrs.keymat.aes_gcm.salt)); 4047 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 4048 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 4049 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 4050 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 4051 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 4052 4053 accel_attrs.esn = attr->esn; 4054 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 4055 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 4056 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4057 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4058 4059 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 4060 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 4061 4062 action->esp_aes_gcm.ctx = 4063 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 4064 if (IS_ERR(action->esp_aes_gcm.ctx)) { 4065 err = PTR_ERR(action->esp_aes_gcm.ctx); 4066 goto err_parse; 4067 } 4068 4069 action->esp_aes_gcm.ib_flags = attr->flags; 4070 4071 return &action->ib_action; 4072 4073 err_parse: 4074 kfree(action); 4075 return ERR_PTR(err); 4076 } 4077 4078 static int 4079 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 4080 const struct ib_flow_action_attrs_esp *attr, 4081 struct uverbs_attr_bundle *attrs) 4082 { 4083 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4084 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 4085 int err = 0; 4086 4087 if (attr->keymat || attr->replay || attr->encap || 4088 attr->spi || attr->seq || attr->tfc_pad || 4089 attr->hard_limit_pkts || 4090 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4091 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 4092 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 4093 return -EOPNOTSUPP; 4094 4095 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 4096 * be modified. 4097 */ 4098 if (!(maction->esp_aes_gcm.ib_flags & 4099 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 4100 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4101 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 4102 return -EINVAL; 4103 4104 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 4105 sizeof(accel_attrs)); 4106 4107 accel_attrs.esn = attr->esn; 4108 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4109 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4110 else 4111 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4112 4113 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 4114 &accel_attrs); 4115 if (err) 4116 return err; 4117 4118 maction->esp_aes_gcm.ib_flags &= 4119 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4120 maction->esp_aes_gcm.ib_flags |= 4121 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4122 4123 return 0; 4124 } 4125 4126 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4127 { 4128 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4129 4130 switch (action->type) { 4131 case IB_FLOW_ACTION_ESP: 4132 /* 4133 * We only support aes_gcm by now, so we implicitly know this is 4134 * the underline crypto. 4135 */ 4136 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4137 break; 4138 case IB_FLOW_ACTION_UNSPECIFIED: 4139 mlx5_ib_destroy_flow_action_raw(maction); 4140 break; 4141 default: 4142 WARN_ON(true); 4143 break; 4144 } 4145 4146 kfree(maction); 4147 return 0; 4148 } 4149 4150 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4151 { 4152 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4153 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4154 int err; 4155 u16 uid; 4156 4157 uid = ibqp->pd ? 4158 to_mpd(ibqp->pd)->uid : 0; 4159 4160 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4161 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4162 return -EOPNOTSUPP; 4163 } 4164 4165 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4166 if (err) 4167 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4168 ibqp->qp_num, gid->raw); 4169 4170 return err; 4171 } 4172 4173 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4174 { 4175 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4176 int err; 4177 u16 uid; 4178 4179 uid = ibqp->pd ? 4180 to_mpd(ibqp->pd)->uid : 0; 4181 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4182 if (err) 4183 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4184 ibqp->qp_num, gid->raw); 4185 4186 return err; 4187 } 4188 4189 static int init_node_data(struct mlx5_ib_dev *dev) 4190 { 4191 int err; 4192 4193 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4194 if (err) 4195 return err; 4196 4197 dev->mdev->rev_id = dev->mdev->pdev->revision; 4198 4199 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4200 } 4201 4202 static ssize_t fw_pages_show(struct device *device, 4203 struct device_attribute *attr, char *buf) 4204 { 4205 struct mlx5_ib_dev *dev = 4206 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4207 4208 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4209 } 4210 static DEVICE_ATTR_RO(fw_pages); 4211 4212 static ssize_t reg_pages_show(struct device *device, 4213 struct device_attribute *attr, char *buf) 4214 { 4215 struct mlx5_ib_dev *dev = 4216 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4217 4218 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4219 } 4220 static DEVICE_ATTR_RO(reg_pages); 4221 4222 static ssize_t hca_type_show(struct device *device, 4223 struct device_attribute *attr, char *buf) 4224 { 4225 struct mlx5_ib_dev *dev = 4226 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4227 4228 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4229 } 4230 static DEVICE_ATTR_RO(hca_type); 4231 4232 static ssize_t hw_rev_show(struct device *device, 4233 struct device_attribute *attr, char *buf) 4234 { 4235 struct mlx5_ib_dev *dev = 4236 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4237 4238 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4239 } 4240 static DEVICE_ATTR_RO(hw_rev); 4241 4242 static ssize_t board_id_show(struct device *device, 4243 struct device_attribute *attr, char *buf) 4244 { 4245 struct mlx5_ib_dev *dev = 4246 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4247 4248 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4249 dev->mdev->board_id); 4250 } 4251 static DEVICE_ATTR_RO(board_id); 4252 4253 static struct attribute *mlx5_class_attributes[] = { 4254 &dev_attr_hw_rev.attr, 4255 &dev_attr_hca_type.attr, 4256 &dev_attr_board_id.attr, 4257 &dev_attr_fw_pages.attr, 4258 &dev_attr_reg_pages.attr, 4259 NULL, 4260 }; 4261 4262 static const struct attribute_group mlx5_attr_group = { 4263 .attrs = mlx5_class_attributes, 4264 }; 4265 4266 static void pkey_change_handler(struct work_struct *work) 4267 { 4268 struct mlx5_ib_port_resources *ports = 4269 container_of(work, struct mlx5_ib_port_resources, 4270 pkey_change_work); 4271 4272 mutex_lock(&ports->devr->mutex); 4273 mlx5_ib_gsi_pkey_change(ports->gsi); 4274 mutex_unlock(&ports->devr->mutex); 4275 } 4276 4277 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4278 { 4279 struct mlx5_ib_qp *mqp; 4280 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4281 struct mlx5_core_cq *mcq; 4282 struct list_head cq_armed_list; 4283 unsigned long flags_qp; 4284 unsigned long flags_cq; 4285 unsigned long flags; 4286 4287 INIT_LIST_HEAD(&cq_armed_list); 4288 4289 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4290 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4291 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4292 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4293 if (mqp->sq.tail != mqp->sq.head) { 4294 send_mcq = to_mcq(mqp->ibqp.send_cq); 4295 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4296 if (send_mcq->mcq.comp && 4297 mqp->ibqp.send_cq->comp_handler) { 4298 if (!send_mcq->mcq.reset_notify_added) { 4299 send_mcq->mcq.reset_notify_added = 1; 4300 list_add_tail(&send_mcq->mcq.reset_notify, 4301 &cq_armed_list); 4302 } 4303 } 4304 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4305 } 4306 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4307 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4308 /* no handling is needed for SRQ */ 4309 if (!mqp->ibqp.srq) { 4310 if (mqp->rq.tail != mqp->rq.head) { 4311 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4312 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4313 if (recv_mcq->mcq.comp && 4314 mqp->ibqp.recv_cq->comp_handler) { 4315 if (!recv_mcq->mcq.reset_notify_added) { 4316 recv_mcq->mcq.reset_notify_added = 1; 4317 list_add_tail(&recv_mcq->mcq.reset_notify, 4318 &cq_armed_list); 4319 } 4320 } 4321 spin_unlock_irqrestore(&recv_mcq->lock, 4322 flags_cq); 4323 } 4324 } 4325 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4326 } 4327 /*At that point all inflight post send were put to be executed as of we 4328 * lock/unlock above locks Now need to arm all involved CQs. 4329 */ 4330 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4331 mcq->comp(mcq); 4332 } 4333 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4334 } 4335 4336 static void delay_drop_handler(struct work_struct *work) 4337 { 4338 int err; 4339 struct mlx5_ib_delay_drop *delay_drop = 4340 container_of(work, struct mlx5_ib_delay_drop, 4341 delay_drop_work); 4342 4343 atomic_inc(&delay_drop->events_cnt); 4344 4345 mutex_lock(&delay_drop->lock); 4346 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4347 delay_drop->timeout); 4348 if (err) { 4349 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4350 delay_drop->timeout); 4351 delay_drop->activate = false; 4352 } 4353 mutex_unlock(&delay_drop->lock); 4354 } 4355 4356 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4357 struct ib_event *ibev) 4358 { 4359 switch (eqe->sub_type) { 4360 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 4361 schedule_work(&ibdev->delay_drop.delay_drop_work); 4362 break; 4363 default: /* do nothing */ 4364 return; 4365 } 4366 } 4367 4368 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4369 struct ib_event *ibev) 4370 { 4371 u8 port = (eqe->data.port.port >> 4) & 0xf; 4372 4373 ibev->element.port_num = port; 4374 4375 switch (eqe->sub_type) { 4376 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 4377 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 4378 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 4379 /* In RoCE, port up/down events are handled in 4380 * mlx5_netdev_event(). 4381 */ 4382 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4383 IB_LINK_LAYER_ETHERNET) 4384 return -EINVAL; 4385 4386 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 4387 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4388 break; 4389 4390 case MLX5_PORT_CHANGE_SUBTYPE_LID: 4391 ibev->event = IB_EVENT_LID_CHANGE; 4392 break; 4393 4394 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 4395 ibev->event = IB_EVENT_PKEY_CHANGE; 4396 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4397 break; 4398 4399 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 4400 ibev->event = IB_EVENT_GID_CHANGE; 4401 break; 4402 4403 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 4404 ibev->event = IB_EVENT_CLIENT_REREGISTER; 4405 break; 4406 default: 4407 return -EINVAL; 4408 } 4409 4410 return 0; 4411 } 4412 4413 static void mlx5_ib_handle_event(struct work_struct *_work) 4414 { 4415 struct mlx5_ib_event_work *work = 4416 container_of(_work, struct mlx5_ib_event_work, work); 4417 struct mlx5_ib_dev *ibdev; 4418 struct ib_event ibev; 4419 bool fatal = false; 4420 4421 if (work->is_slave) { 4422 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 4423 if (!ibdev) 4424 goto out; 4425 } else { 4426 ibdev = work->dev; 4427 } 4428 4429 switch (work->event) { 4430 case MLX5_DEV_EVENT_SYS_ERROR: 4431 ibev.event = IB_EVENT_DEVICE_FATAL; 4432 mlx5_ib_handle_internal_error(ibdev); 4433 ibev.element.port_num = (u8)(unsigned long)work->param; 4434 fatal = true; 4435 break; 4436 case MLX5_EVENT_TYPE_PORT_CHANGE: 4437 if (handle_port_change(ibdev, work->param, &ibev)) 4438 goto out; 4439 break; 4440 case MLX5_EVENT_TYPE_GENERAL_EVENT: 4441 handle_general_event(ibdev, work->param, &ibev); 4442 /* fall through */ 4443 default: 4444 goto out; 4445 } 4446 4447 ibev.device = &ibdev->ib_dev; 4448 4449 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 4450 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 4451 goto out; 4452 } 4453 4454 if (ibdev->ib_active) 4455 ib_dispatch_event(&ibev); 4456 4457 if (fatal) 4458 ibdev->ib_active = false; 4459 out: 4460 kfree(work); 4461 } 4462 4463 static int mlx5_ib_event(struct notifier_block *nb, 4464 unsigned long event, void *param) 4465 { 4466 struct mlx5_ib_event_work *work; 4467 4468 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4469 if (!work) 4470 return NOTIFY_DONE; 4471 4472 INIT_WORK(&work->work, mlx5_ib_handle_event); 4473 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 4474 work->is_slave = false; 4475 work->param = param; 4476 work->event = event; 4477 4478 queue_work(mlx5_ib_event_wq, &work->work); 4479 4480 return NOTIFY_OK; 4481 } 4482 4483 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 4484 unsigned long event, void *param) 4485 { 4486 struct mlx5_ib_event_work *work; 4487 4488 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4489 if (!work) 4490 return NOTIFY_DONE; 4491 4492 INIT_WORK(&work->work, mlx5_ib_handle_event); 4493 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 4494 work->is_slave = true; 4495 work->param = param; 4496 work->event = event; 4497 queue_work(mlx5_ib_event_wq, &work->work); 4498 4499 return NOTIFY_OK; 4500 } 4501 4502 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4503 { 4504 struct mlx5_hca_vport_context vport_ctx; 4505 int err; 4506 int port; 4507 4508 for (port = 1; port <= dev->num_ports; port++) { 4509 dev->mdev->port_caps[port - 1].has_smi = false; 4510 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4511 MLX5_CAP_PORT_TYPE_IB) { 4512 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4513 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4514 port, 0, 4515 &vport_ctx); 4516 if (err) { 4517 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4518 port, err); 4519 return err; 4520 } 4521 dev->mdev->port_caps[port - 1].has_smi = 4522 vport_ctx.has_smi; 4523 } else { 4524 dev->mdev->port_caps[port - 1].has_smi = true; 4525 } 4526 } 4527 } 4528 return 0; 4529 } 4530 4531 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4532 { 4533 int port; 4534 4535 for (port = 1; port <= dev->num_ports; port++) 4536 mlx5_query_ext_port_caps(dev, port); 4537 } 4538 4539 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4540 { 4541 struct ib_device_attr *dprops = NULL; 4542 struct ib_port_attr *pprops = NULL; 4543 int err = -ENOMEM; 4544 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4545 4546 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4547 if (!pprops) 4548 goto out; 4549 4550 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4551 if (!dprops) 4552 goto out; 4553 4554 err = set_has_smi_cap(dev); 4555 if (err) 4556 goto out; 4557 4558 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4559 if (err) { 4560 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4561 goto out; 4562 } 4563 4564 memset(pprops, 0, sizeof(*pprops)); 4565 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4566 if (err) { 4567 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4568 port, err); 4569 goto out; 4570 } 4571 4572 dev->mdev->port_caps[port - 1].pkey_table_len = 4573 dprops->max_pkeys; 4574 dev->mdev->port_caps[port - 1].gid_table_len = 4575 pprops->gid_tbl_len; 4576 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4577 port, dprops->max_pkeys, pprops->gid_tbl_len); 4578 4579 out: 4580 kfree(pprops); 4581 kfree(dprops); 4582 4583 return err; 4584 } 4585 4586 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4587 { 4588 int err; 4589 4590 err = mlx5_mr_cache_cleanup(dev); 4591 if (err) 4592 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4593 4594 if (dev->umrc.qp) 4595 mlx5_ib_destroy_qp(dev->umrc.qp); 4596 if (dev->umrc.cq) 4597 ib_free_cq(dev->umrc.cq); 4598 if (dev->umrc.pd) 4599 ib_dealloc_pd(dev->umrc.pd); 4600 } 4601 4602 enum { 4603 MAX_UMR_WR = 128, 4604 }; 4605 4606 static int create_umr_res(struct mlx5_ib_dev *dev) 4607 { 4608 struct ib_qp_init_attr *init_attr = NULL; 4609 struct ib_qp_attr *attr = NULL; 4610 struct ib_pd *pd; 4611 struct ib_cq *cq; 4612 struct ib_qp *qp; 4613 int ret; 4614 4615 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4616 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4617 if (!attr || !init_attr) { 4618 ret = -ENOMEM; 4619 goto error_0; 4620 } 4621 4622 pd = ib_alloc_pd(&dev->ib_dev, 0); 4623 if (IS_ERR(pd)) { 4624 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4625 ret = PTR_ERR(pd); 4626 goto error_0; 4627 } 4628 4629 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4630 if (IS_ERR(cq)) { 4631 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4632 ret = PTR_ERR(cq); 4633 goto error_2; 4634 } 4635 4636 init_attr->send_cq = cq; 4637 init_attr->recv_cq = cq; 4638 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4639 init_attr->cap.max_send_wr = MAX_UMR_WR; 4640 init_attr->cap.max_send_sge = 1; 4641 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4642 init_attr->port_num = 1; 4643 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4644 if (IS_ERR(qp)) { 4645 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4646 ret = PTR_ERR(qp); 4647 goto error_3; 4648 } 4649 qp->device = &dev->ib_dev; 4650 qp->real_qp = qp; 4651 qp->uobject = NULL; 4652 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4653 qp->send_cq = init_attr->send_cq; 4654 qp->recv_cq = init_attr->recv_cq; 4655 4656 attr->qp_state = IB_QPS_INIT; 4657 attr->port_num = 1; 4658 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4659 IB_QP_PORT, NULL); 4660 if (ret) { 4661 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4662 goto error_4; 4663 } 4664 4665 memset(attr, 0, sizeof(*attr)); 4666 attr->qp_state = IB_QPS_RTR; 4667 attr->path_mtu = IB_MTU_256; 4668 4669 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4670 if (ret) { 4671 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4672 goto error_4; 4673 } 4674 4675 memset(attr, 0, sizeof(*attr)); 4676 attr->qp_state = IB_QPS_RTS; 4677 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4678 if (ret) { 4679 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4680 goto error_4; 4681 } 4682 4683 dev->umrc.qp = qp; 4684 dev->umrc.cq = cq; 4685 dev->umrc.pd = pd; 4686 4687 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4688 ret = mlx5_mr_cache_init(dev); 4689 if (ret) { 4690 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4691 goto error_4; 4692 } 4693 4694 kfree(attr); 4695 kfree(init_attr); 4696 4697 return 0; 4698 4699 error_4: 4700 mlx5_ib_destroy_qp(qp); 4701 dev->umrc.qp = NULL; 4702 4703 error_3: 4704 ib_free_cq(cq); 4705 dev->umrc.cq = NULL; 4706 4707 error_2: 4708 ib_dealloc_pd(pd); 4709 dev->umrc.pd = NULL; 4710 4711 error_0: 4712 kfree(attr); 4713 kfree(init_attr); 4714 return ret; 4715 } 4716 4717 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4718 { 4719 switch (umr_fence_cap) { 4720 case MLX5_CAP_UMR_FENCE_NONE: 4721 return MLX5_FENCE_MODE_NONE; 4722 case MLX5_CAP_UMR_FENCE_SMALL: 4723 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4724 default: 4725 return MLX5_FENCE_MODE_STRONG_ORDERING; 4726 } 4727 } 4728 4729 static int create_dev_resources(struct mlx5_ib_resources *devr) 4730 { 4731 struct ib_srq_init_attr attr; 4732 struct mlx5_ib_dev *dev; 4733 struct ib_device *ibdev; 4734 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4735 int port; 4736 int ret = 0; 4737 4738 dev = container_of(devr, struct mlx5_ib_dev, devr); 4739 ibdev = &dev->ib_dev; 4740 4741 mutex_init(&devr->mutex); 4742 4743 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 4744 if (!devr->p0) 4745 return -ENOMEM; 4746 4747 devr->p0->device = ibdev; 4748 devr->p0->uobject = NULL; 4749 atomic_set(&devr->p0->usecnt, 0); 4750 4751 ret = mlx5_ib_alloc_pd(devr->p0, NULL, NULL); 4752 if (ret) 4753 goto error0; 4754 4755 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4756 if (IS_ERR(devr->c0)) { 4757 ret = PTR_ERR(devr->c0); 4758 goto error1; 4759 } 4760 devr->c0->device = &dev->ib_dev; 4761 devr->c0->uobject = NULL; 4762 devr->c0->comp_handler = NULL; 4763 devr->c0->event_handler = NULL; 4764 devr->c0->cq_context = NULL; 4765 atomic_set(&devr->c0->usecnt, 0); 4766 4767 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4768 if (IS_ERR(devr->x0)) { 4769 ret = PTR_ERR(devr->x0); 4770 goto error2; 4771 } 4772 devr->x0->device = &dev->ib_dev; 4773 devr->x0->inode = NULL; 4774 atomic_set(&devr->x0->usecnt, 0); 4775 mutex_init(&devr->x0->tgt_qp_mutex); 4776 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4777 4778 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4779 if (IS_ERR(devr->x1)) { 4780 ret = PTR_ERR(devr->x1); 4781 goto error3; 4782 } 4783 devr->x1->device = &dev->ib_dev; 4784 devr->x1->inode = NULL; 4785 atomic_set(&devr->x1->usecnt, 0); 4786 mutex_init(&devr->x1->tgt_qp_mutex); 4787 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4788 4789 memset(&attr, 0, sizeof(attr)); 4790 attr.attr.max_sge = 1; 4791 attr.attr.max_wr = 1; 4792 attr.srq_type = IB_SRQT_XRC; 4793 attr.ext.cq = devr->c0; 4794 attr.ext.xrc.xrcd = devr->x0; 4795 4796 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4797 if (IS_ERR(devr->s0)) { 4798 ret = PTR_ERR(devr->s0); 4799 goto error4; 4800 } 4801 devr->s0->device = &dev->ib_dev; 4802 devr->s0->pd = devr->p0; 4803 devr->s0->uobject = NULL; 4804 devr->s0->event_handler = NULL; 4805 devr->s0->srq_context = NULL; 4806 devr->s0->srq_type = IB_SRQT_XRC; 4807 devr->s0->ext.xrc.xrcd = devr->x0; 4808 devr->s0->ext.cq = devr->c0; 4809 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4810 atomic_inc(&devr->s0->ext.cq->usecnt); 4811 atomic_inc(&devr->p0->usecnt); 4812 atomic_set(&devr->s0->usecnt, 0); 4813 4814 memset(&attr, 0, sizeof(attr)); 4815 attr.attr.max_sge = 1; 4816 attr.attr.max_wr = 1; 4817 attr.srq_type = IB_SRQT_BASIC; 4818 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4819 if (IS_ERR(devr->s1)) { 4820 ret = PTR_ERR(devr->s1); 4821 goto error5; 4822 } 4823 devr->s1->device = &dev->ib_dev; 4824 devr->s1->pd = devr->p0; 4825 devr->s1->uobject = NULL; 4826 devr->s1->event_handler = NULL; 4827 devr->s1->srq_context = NULL; 4828 devr->s1->srq_type = IB_SRQT_BASIC; 4829 devr->s1->ext.cq = devr->c0; 4830 atomic_inc(&devr->p0->usecnt); 4831 atomic_set(&devr->s1->usecnt, 0); 4832 4833 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4834 INIT_WORK(&devr->ports[port].pkey_change_work, 4835 pkey_change_handler); 4836 devr->ports[port].devr = devr; 4837 } 4838 4839 return 0; 4840 4841 error5: 4842 mlx5_ib_destroy_srq(devr->s0); 4843 error4: 4844 mlx5_ib_dealloc_xrcd(devr->x1); 4845 error3: 4846 mlx5_ib_dealloc_xrcd(devr->x0); 4847 error2: 4848 mlx5_ib_destroy_cq(devr->c0); 4849 error1: 4850 mlx5_ib_dealloc_pd(devr->p0); 4851 error0: 4852 kfree(devr->p0); 4853 return ret; 4854 } 4855 4856 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4857 { 4858 struct mlx5_ib_dev *dev = 4859 container_of(devr, struct mlx5_ib_dev, devr); 4860 int port; 4861 4862 mlx5_ib_destroy_srq(devr->s1); 4863 mlx5_ib_destroy_srq(devr->s0); 4864 mlx5_ib_dealloc_xrcd(devr->x0); 4865 mlx5_ib_dealloc_xrcd(devr->x1); 4866 mlx5_ib_destroy_cq(devr->c0); 4867 mlx5_ib_dealloc_pd(devr->p0); 4868 kfree(devr->p0); 4869 4870 /* Make sure no change P_Key work items are still executing */ 4871 for (port = 0; port < dev->num_ports; ++port) 4872 cancel_work_sync(&devr->ports[port].pkey_change_work); 4873 } 4874 4875 static u32 get_core_cap_flags(struct ib_device *ibdev, 4876 struct mlx5_hca_vport_context *rep) 4877 { 4878 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4879 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4880 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4881 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4882 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4883 u32 ret = 0; 4884 4885 if (rep->grh_required) 4886 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4887 4888 if (ll == IB_LINK_LAYER_INFINIBAND) 4889 return ret | RDMA_CORE_PORT_IBA_IB; 4890 4891 if (raw_support) 4892 ret |= RDMA_CORE_PORT_RAW_PACKET; 4893 4894 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4895 return ret; 4896 4897 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4898 return ret; 4899 4900 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4901 ret |= RDMA_CORE_PORT_IBA_ROCE; 4902 4903 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4904 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4905 4906 return ret; 4907 } 4908 4909 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4910 struct ib_port_immutable *immutable) 4911 { 4912 struct ib_port_attr attr; 4913 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4914 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4915 struct mlx5_hca_vport_context rep = {0}; 4916 int err; 4917 4918 err = ib_query_port(ibdev, port_num, &attr); 4919 if (err) 4920 return err; 4921 4922 if (ll == IB_LINK_LAYER_INFINIBAND) { 4923 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4924 &rep); 4925 if (err) 4926 return err; 4927 } 4928 4929 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4930 immutable->gid_tbl_len = attr.gid_tbl_len; 4931 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4932 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4933 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4934 4935 return 0; 4936 } 4937 4938 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4939 struct ib_port_immutable *immutable) 4940 { 4941 struct ib_port_attr attr; 4942 int err; 4943 4944 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4945 4946 err = ib_query_port(ibdev, port_num, &attr); 4947 if (err) 4948 return err; 4949 4950 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4951 immutable->gid_tbl_len = attr.gid_tbl_len; 4952 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4953 4954 return 0; 4955 } 4956 4957 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4958 { 4959 struct mlx5_ib_dev *dev = 4960 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4961 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4962 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4963 fw_rev_sub(dev->mdev)); 4964 } 4965 4966 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4967 { 4968 struct mlx5_core_dev *mdev = dev->mdev; 4969 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4970 MLX5_FLOW_NAMESPACE_LAG); 4971 struct mlx5_flow_table *ft; 4972 int err; 4973 4974 if (!ns || !mlx5_lag_is_roce(mdev)) 4975 return 0; 4976 4977 err = mlx5_cmd_create_vport_lag(mdev); 4978 if (err) 4979 return err; 4980 4981 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4982 if (IS_ERR(ft)) { 4983 err = PTR_ERR(ft); 4984 goto err_destroy_vport_lag; 4985 } 4986 4987 dev->flow_db->lag_demux_ft = ft; 4988 dev->lag_active = true; 4989 return 0; 4990 4991 err_destroy_vport_lag: 4992 mlx5_cmd_destroy_vport_lag(mdev); 4993 return err; 4994 } 4995 4996 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4997 { 4998 struct mlx5_core_dev *mdev = dev->mdev; 4999 5000 if (dev->lag_active) { 5001 dev->lag_active = false; 5002 5003 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 5004 dev->flow_db->lag_demux_ft = NULL; 5005 5006 mlx5_cmd_destroy_vport_lag(mdev); 5007 } 5008 } 5009 5010 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5011 { 5012 int err; 5013 5014 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 5015 err = register_netdevice_notifier(&dev->roce[port_num].nb); 5016 if (err) { 5017 dev->roce[port_num].nb.notifier_call = NULL; 5018 return err; 5019 } 5020 5021 return 0; 5022 } 5023 5024 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5025 { 5026 if (dev->roce[port_num].nb.notifier_call) { 5027 unregister_netdevice_notifier(&dev->roce[port_num].nb); 5028 dev->roce[port_num].nb.notifier_call = NULL; 5029 } 5030 } 5031 5032 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 5033 { 5034 int err; 5035 5036 if (MLX5_CAP_GEN(dev->mdev, roce)) { 5037 err = mlx5_nic_vport_enable_roce(dev->mdev); 5038 if (err) 5039 return err; 5040 } 5041 5042 err = mlx5_eth_lag_init(dev); 5043 if (err) 5044 goto err_disable_roce; 5045 5046 return 0; 5047 5048 err_disable_roce: 5049 if (MLX5_CAP_GEN(dev->mdev, roce)) 5050 mlx5_nic_vport_disable_roce(dev->mdev); 5051 5052 return err; 5053 } 5054 5055 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 5056 { 5057 mlx5_eth_lag_cleanup(dev); 5058 if (MLX5_CAP_GEN(dev->mdev, roce)) 5059 mlx5_nic_vport_disable_roce(dev->mdev); 5060 } 5061 5062 struct mlx5_ib_counter { 5063 const char *name; 5064 size_t offset; 5065 }; 5066 5067 #define INIT_Q_COUNTER(_name) \ 5068 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 5069 5070 static const struct mlx5_ib_counter basic_q_cnts[] = { 5071 INIT_Q_COUNTER(rx_write_requests), 5072 INIT_Q_COUNTER(rx_read_requests), 5073 INIT_Q_COUNTER(rx_atomic_requests), 5074 INIT_Q_COUNTER(out_of_buffer), 5075 }; 5076 5077 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 5078 INIT_Q_COUNTER(out_of_sequence), 5079 }; 5080 5081 static const struct mlx5_ib_counter retrans_q_cnts[] = { 5082 INIT_Q_COUNTER(duplicate_request), 5083 INIT_Q_COUNTER(rnr_nak_retry_err), 5084 INIT_Q_COUNTER(packet_seq_err), 5085 INIT_Q_COUNTER(implied_nak_seq_err), 5086 INIT_Q_COUNTER(local_ack_timeout_err), 5087 }; 5088 5089 #define INIT_CONG_COUNTER(_name) \ 5090 { .name = #_name, .offset = \ 5091 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 5092 5093 static const struct mlx5_ib_counter cong_cnts[] = { 5094 INIT_CONG_COUNTER(rp_cnp_ignored), 5095 INIT_CONG_COUNTER(rp_cnp_handled), 5096 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 5097 INIT_CONG_COUNTER(np_cnp_sent), 5098 }; 5099 5100 static const struct mlx5_ib_counter extended_err_cnts[] = { 5101 INIT_Q_COUNTER(resp_local_length_error), 5102 INIT_Q_COUNTER(resp_cqe_error), 5103 INIT_Q_COUNTER(req_cqe_error), 5104 INIT_Q_COUNTER(req_remote_invalid_request), 5105 INIT_Q_COUNTER(req_remote_access_errors), 5106 INIT_Q_COUNTER(resp_remote_access_errors), 5107 INIT_Q_COUNTER(resp_cqe_flush_error), 5108 INIT_Q_COUNTER(req_cqe_flush_error), 5109 }; 5110 5111 #define INIT_EXT_PPCNT_COUNTER(_name) \ 5112 { .name = #_name, .offset = \ 5113 MLX5_BYTE_OFF(ppcnt_reg, \ 5114 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 5115 5116 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 5117 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 5118 }; 5119 5120 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 5121 { 5122 int i; 5123 5124 for (i = 0; i < dev->num_ports; i++) { 5125 if (dev->port[i].cnts.set_id_valid) 5126 mlx5_core_dealloc_q_counter(dev->mdev, 5127 dev->port[i].cnts.set_id); 5128 kfree(dev->port[i].cnts.names); 5129 kfree(dev->port[i].cnts.offsets); 5130 } 5131 } 5132 5133 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 5134 struct mlx5_ib_counters *cnts) 5135 { 5136 u32 num_counters; 5137 5138 num_counters = ARRAY_SIZE(basic_q_cnts); 5139 5140 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 5141 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 5142 5143 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 5144 num_counters += ARRAY_SIZE(retrans_q_cnts); 5145 5146 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 5147 num_counters += ARRAY_SIZE(extended_err_cnts); 5148 5149 cnts->num_q_counters = num_counters; 5150 5151 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5152 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 5153 num_counters += ARRAY_SIZE(cong_cnts); 5154 } 5155 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5156 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 5157 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 5158 } 5159 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 5160 if (!cnts->names) 5161 return -ENOMEM; 5162 5163 cnts->offsets = kcalloc(num_counters, 5164 sizeof(cnts->offsets), GFP_KERNEL); 5165 if (!cnts->offsets) 5166 goto err_names; 5167 5168 return 0; 5169 5170 err_names: 5171 kfree(cnts->names); 5172 cnts->names = NULL; 5173 return -ENOMEM; 5174 } 5175 5176 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 5177 const char **names, 5178 size_t *offsets) 5179 { 5180 int i; 5181 int j = 0; 5182 5183 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5184 names[j] = basic_q_cnts[i].name; 5185 offsets[j] = basic_q_cnts[i].offset; 5186 } 5187 5188 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5189 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5190 names[j] = out_of_seq_q_cnts[i].name; 5191 offsets[j] = out_of_seq_q_cnts[i].offset; 5192 } 5193 } 5194 5195 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5196 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5197 names[j] = retrans_q_cnts[i].name; 5198 offsets[j] = retrans_q_cnts[i].offset; 5199 } 5200 } 5201 5202 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5203 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5204 names[j] = extended_err_cnts[i].name; 5205 offsets[j] = extended_err_cnts[i].offset; 5206 } 5207 } 5208 5209 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5210 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5211 names[j] = cong_cnts[i].name; 5212 offsets[j] = cong_cnts[i].offset; 5213 } 5214 } 5215 5216 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5217 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5218 names[j] = ext_ppcnt_cnts[i].name; 5219 offsets[j] = ext_ppcnt_cnts[i].offset; 5220 } 5221 } 5222 } 5223 5224 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5225 { 5226 int err = 0; 5227 int i; 5228 bool is_shared; 5229 5230 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0; 5231 5232 for (i = 0; i < dev->num_ports; i++) { 5233 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5234 if (err) 5235 goto err_alloc; 5236 5237 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5238 dev->port[i].cnts.offsets); 5239 5240 err = mlx5_cmd_alloc_q_counter(dev->mdev, 5241 &dev->port[i].cnts.set_id, 5242 is_shared ? 5243 MLX5_SHARED_RESOURCE_UID : 0); 5244 if (err) { 5245 mlx5_ib_warn(dev, 5246 "couldn't allocate queue counter for port %d, err %d\n", 5247 i + 1, err); 5248 goto err_alloc; 5249 } 5250 dev->port[i].cnts.set_id_valid = true; 5251 } 5252 5253 return 0; 5254 5255 err_alloc: 5256 mlx5_ib_dealloc_counters(dev); 5257 return err; 5258 } 5259 5260 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5261 u8 port_num) 5262 { 5263 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5264 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5265 5266 /* We support only per port stats */ 5267 if (port_num == 0) 5268 return NULL; 5269 5270 return rdma_alloc_hw_stats_struct(port->cnts.names, 5271 port->cnts.num_q_counters + 5272 port->cnts.num_cong_counters + 5273 port->cnts.num_ext_ppcnt_counters, 5274 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5275 } 5276 5277 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5278 struct mlx5_ib_port *port, 5279 struct rdma_hw_stats *stats) 5280 { 5281 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5282 void *out; 5283 __be32 val; 5284 int ret, i; 5285 5286 out = kvzalloc(outlen, GFP_KERNEL); 5287 if (!out) 5288 return -ENOMEM; 5289 5290 ret = mlx5_core_query_q_counter(mdev, 5291 port->cnts.set_id, 0, 5292 out, outlen); 5293 if (ret) 5294 goto free; 5295 5296 for (i = 0; i < port->cnts.num_q_counters; i++) { 5297 val = *(__be32 *)(out + port->cnts.offsets[i]); 5298 stats->value[i] = (u64)be32_to_cpu(val); 5299 } 5300 5301 free: 5302 kvfree(out); 5303 return ret; 5304 } 5305 5306 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5307 struct mlx5_ib_port *port, 5308 struct rdma_hw_stats *stats) 5309 { 5310 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5311 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5312 int ret, i; 5313 void *out; 5314 5315 out = kvzalloc(sz, GFP_KERNEL); 5316 if (!out) 5317 return -ENOMEM; 5318 5319 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5320 if (ret) 5321 goto free; 5322 5323 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5324 stats->value[i + offset] = 5325 be64_to_cpup((__be64 *)(out + 5326 port->cnts.offsets[i + offset])); 5327 } 5328 5329 free: 5330 kvfree(out); 5331 return ret; 5332 } 5333 5334 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5335 struct rdma_hw_stats *stats, 5336 u8 port_num, int index) 5337 { 5338 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5339 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5340 struct mlx5_core_dev *mdev; 5341 int ret, num_counters; 5342 u8 mdev_port_num; 5343 5344 if (!stats) 5345 return -EINVAL; 5346 5347 num_counters = port->cnts.num_q_counters + 5348 port->cnts.num_cong_counters + 5349 port->cnts.num_ext_ppcnt_counters; 5350 5351 /* q_counters are per IB device, query the master mdev */ 5352 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5353 if (ret) 5354 return ret; 5355 5356 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5357 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5358 if (ret) 5359 return ret; 5360 } 5361 5362 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5363 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5364 &mdev_port_num); 5365 if (!mdev) { 5366 /* If port is not affiliated yet, its in down state 5367 * which doesn't have any counters yet, so it would be 5368 * zero. So no need to read from the HCA. 5369 */ 5370 goto done; 5371 } 5372 ret = mlx5_lag_query_cong_counters(dev->mdev, 5373 stats->value + 5374 port->cnts.num_q_counters, 5375 port->cnts.num_cong_counters, 5376 port->cnts.offsets + 5377 port->cnts.num_q_counters); 5378 5379 mlx5_ib_put_native_port_mdev(dev, port_num); 5380 if (ret) 5381 return ret; 5382 } 5383 5384 done: 5385 return num_counters; 5386 } 5387 5388 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5389 enum rdma_netdev_t type, 5390 struct rdma_netdev_alloc_params *params) 5391 { 5392 if (type != RDMA_NETDEV_IPOIB) 5393 return -EOPNOTSUPP; 5394 5395 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5396 } 5397 5398 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5399 { 5400 if (!dev->delay_drop.dbg) 5401 return; 5402 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5403 kfree(dev->delay_drop.dbg); 5404 dev->delay_drop.dbg = NULL; 5405 } 5406 5407 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5408 { 5409 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5410 return; 5411 5412 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5413 delay_drop_debugfs_cleanup(dev); 5414 } 5415 5416 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5417 size_t count, loff_t *pos) 5418 { 5419 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5420 char lbuf[20]; 5421 int len; 5422 5423 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5424 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5425 } 5426 5427 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5428 size_t count, loff_t *pos) 5429 { 5430 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5431 u32 timeout; 5432 u32 var; 5433 5434 if (kstrtouint_from_user(buf, count, 0, &var)) 5435 return -EFAULT; 5436 5437 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5438 1000); 5439 if (timeout != var) 5440 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5441 timeout); 5442 5443 delay_drop->timeout = timeout; 5444 5445 return count; 5446 } 5447 5448 static const struct file_operations fops_delay_drop_timeout = { 5449 .owner = THIS_MODULE, 5450 .open = simple_open, 5451 .write = delay_drop_timeout_write, 5452 .read = delay_drop_timeout_read, 5453 }; 5454 5455 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5456 { 5457 struct mlx5_ib_dbg_delay_drop *dbg; 5458 5459 if (!mlx5_debugfs_root) 5460 return 0; 5461 5462 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5463 if (!dbg) 5464 return -ENOMEM; 5465 5466 dev->delay_drop.dbg = dbg; 5467 5468 dbg->dir_debugfs = 5469 debugfs_create_dir("delay_drop", 5470 dev->mdev->priv.dbg_root); 5471 if (!dbg->dir_debugfs) 5472 goto out_debugfs; 5473 5474 dbg->events_cnt_debugfs = 5475 debugfs_create_atomic_t("num_timeout_events", 0400, 5476 dbg->dir_debugfs, 5477 &dev->delay_drop.events_cnt); 5478 if (!dbg->events_cnt_debugfs) 5479 goto out_debugfs; 5480 5481 dbg->rqs_cnt_debugfs = 5482 debugfs_create_atomic_t("num_rqs", 0400, 5483 dbg->dir_debugfs, 5484 &dev->delay_drop.rqs_cnt); 5485 if (!dbg->rqs_cnt_debugfs) 5486 goto out_debugfs; 5487 5488 dbg->timeout_debugfs = 5489 debugfs_create_file("timeout", 0600, 5490 dbg->dir_debugfs, 5491 &dev->delay_drop, 5492 &fops_delay_drop_timeout); 5493 if (!dbg->timeout_debugfs) 5494 goto out_debugfs; 5495 5496 return 0; 5497 5498 out_debugfs: 5499 delay_drop_debugfs_cleanup(dev); 5500 return -ENOMEM; 5501 } 5502 5503 static void init_delay_drop(struct mlx5_ib_dev *dev) 5504 { 5505 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5506 return; 5507 5508 mutex_init(&dev->delay_drop.lock); 5509 dev->delay_drop.dev = dev; 5510 dev->delay_drop.activate = false; 5511 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5512 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5513 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5514 atomic_set(&dev->delay_drop.events_cnt, 0); 5515 5516 if (delay_drop_debugfs_init(dev)) 5517 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5518 } 5519 5520 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5521 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5522 struct mlx5_ib_multiport_info *mpi) 5523 { 5524 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5525 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5526 int comps; 5527 int err; 5528 int i; 5529 5530 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5531 5532 spin_lock(&port->mp.mpi_lock); 5533 if (!mpi->ibdev) { 5534 spin_unlock(&port->mp.mpi_lock); 5535 return; 5536 } 5537 5538 if (mpi->mdev_events.notifier_call) 5539 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 5540 mpi->mdev_events.notifier_call = NULL; 5541 5542 mpi->ibdev = NULL; 5543 5544 spin_unlock(&port->mp.mpi_lock); 5545 mlx5_remove_netdev_notifier(ibdev, port_num); 5546 spin_lock(&port->mp.mpi_lock); 5547 5548 comps = mpi->mdev_refcnt; 5549 if (comps) { 5550 mpi->unaffiliate = true; 5551 init_completion(&mpi->unref_comp); 5552 spin_unlock(&port->mp.mpi_lock); 5553 5554 for (i = 0; i < comps; i++) 5555 wait_for_completion(&mpi->unref_comp); 5556 5557 spin_lock(&port->mp.mpi_lock); 5558 mpi->unaffiliate = false; 5559 } 5560 5561 port->mp.mpi = NULL; 5562 5563 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5564 5565 spin_unlock(&port->mp.mpi_lock); 5566 5567 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5568 5569 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5570 /* Log an error, still needed to cleanup the pointers and add 5571 * it back to the list. 5572 */ 5573 if (err) 5574 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5575 port_num + 1); 5576 5577 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5578 } 5579 5580 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5581 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5582 struct mlx5_ib_multiport_info *mpi) 5583 { 5584 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5585 int err; 5586 5587 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5588 if (ibdev->port[port_num].mp.mpi) { 5589 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5590 port_num + 1); 5591 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5592 return false; 5593 } 5594 5595 ibdev->port[port_num].mp.mpi = mpi; 5596 mpi->ibdev = ibdev; 5597 mpi->mdev_events.notifier_call = NULL; 5598 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5599 5600 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5601 if (err) 5602 goto unbind; 5603 5604 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5605 if (err) 5606 goto unbind; 5607 5608 err = mlx5_add_netdev_notifier(ibdev, port_num); 5609 if (err) { 5610 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5611 port_num + 1); 5612 goto unbind; 5613 } 5614 5615 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 5616 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 5617 5618 mlx5_ib_init_cong_debugfs(ibdev, port_num); 5619 5620 return true; 5621 5622 unbind: 5623 mlx5_ib_unbind_slave_port(ibdev, mpi); 5624 return false; 5625 } 5626 5627 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5628 { 5629 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5630 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5631 port_num + 1); 5632 struct mlx5_ib_multiport_info *mpi; 5633 int err; 5634 int i; 5635 5636 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5637 return 0; 5638 5639 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5640 &dev->sys_image_guid); 5641 if (err) 5642 return err; 5643 5644 err = mlx5_nic_vport_enable_roce(dev->mdev); 5645 if (err) 5646 return err; 5647 5648 mutex_lock(&mlx5_ib_multiport_mutex); 5649 for (i = 0; i < dev->num_ports; i++) { 5650 bool bound = false; 5651 5652 /* build a stub multiport info struct for the native port. */ 5653 if (i == port_num) { 5654 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5655 if (!mpi) { 5656 mutex_unlock(&mlx5_ib_multiport_mutex); 5657 mlx5_nic_vport_disable_roce(dev->mdev); 5658 return -ENOMEM; 5659 } 5660 5661 mpi->is_master = true; 5662 mpi->mdev = dev->mdev; 5663 mpi->sys_image_guid = dev->sys_image_guid; 5664 dev->port[i].mp.mpi = mpi; 5665 mpi->ibdev = dev; 5666 mpi = NULL; 5667 continue; 5668 } 5669 5670 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5671 list) { 5672 if (dev->sys_image_guid == mpi->sys_image_guid && 5673 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5674 bound = mlx5_ib_bind_slave_port(dev, mpi); 5675 } 5676 5677 if (bound) { 5678 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5679 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5680 list_del(&mpi->list); 5681 break; 5682 } 5683 } 5684 if (!bound) { 5685 get_port_caps(dev, i + 1); 5686 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5687 i + 1); 5688 } 5689 } 5690 5691 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5692 mutex_unlock(&mlx5_ib_multiport_mutex); 5693 return err; 5694 } 5695 5696 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5697 { 5698 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5699 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5700 port_num + 1); 5701 int i; 5702 5703 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5704 return; 5705 5706 mutex_lock(&mlx5_ib_multiport_mutex); 5707 for (i = 0; i < dev->num_ports; i++) { 5708 if (dev->port[i].mp.mpi) { 5709 /* Destroy the native port stub */ 5710 if (i == port_num) { 5711 kfree(dev->port[i].mp.mpi); 5712 dev->port[i].mp.mpi = NULL; 5713 } else { 5714 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5715 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5716 } 5717 } 5718 } 5719 5720 mlx5_ib_dbg(dev, "removing from devlist\n"); 5721 list_del(&dev->ib_dev_list); 5722 mutex_unlock(&mlx5_ib_multiport_mutex); 5723 5724 mlx5_nic_vport_disable_roce(dev->mdev); 5725 } 5726 5727 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5728 mlx5_ib_dm, 5729 UVERBS_OBJECT_DM, 5730 UVERBS_METHOD_DM_ALLOC, 5731 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5732 UVERBS_ATTR_TYPE(u64), 5733 UA_MANDATORY), 5734 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5735 UVERBS_ATTR_TYPE(u16), 5736 UA_MANDATORY)); 5737 5738 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5739 mlx5_ib_flow_action, 5740 UVERBS_OBJECT_FLOW_ACTION, 5741 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5742 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5743 enum mlx5_ib_uapi_flow_action_flags)); 5744 5745 static const struct uapi_definition mlx5_ib_defs[] = { 5746 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 5747 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 5748 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 5749 #endif 5750 5751 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 5752 &mlx5_ib_flow_action), 5753 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 5754 {} 5755 }; 5756 5757 static int mlx5_ib_read_counters(struct ib_counters *counters, 5758 struct ib_counters_read_attr *read_attr, 5759 struct uverbs_attr_bundle *attrs) 5760 { 5761 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5762 struct mlx5_read_counters_attr mread_attr = {}; 5763 struct mlx5_ib_flow_counters_desc *desc; 5764 int ret, i; 5765 5766 mutex_lock(&mcounters->mcntrs_mutex); 5767 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5768 ret = -EINVAL; 5769 goto err_bound; 5770 } 5771 5772 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5773 GFP_KERNEL); 5774 if (!mread_attr.out) { 5775 ret = -ENOMEM; 5776 goto err_bound; 5777 } 5778 5779 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5780 mread_attr.flags = read_attr->flags; 5781 ret = mcounters->read_counters(counters->device, &mread_attr); 5782 if (ret) 5783 goto err_read; 5784 5785 /* do the pass over the counters data array to assign according to the 5786 * descriptions and indexing pairs 5787 */ 5788 desc = mcounters->counters_data; 5789 for (i = 0; i < mcounters->ncounters; i++) 5790 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5791 5792 err_read: 5793 kfree(mread_attr.out); 5794 err_bound: 5795 mutex_unlock(&mcounters->mcntrs_mutex); 5796 return ret; 5797 } 5798 5799 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5800 { 5801 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5802 5803 counters_clear_description(counters); 5804 if (mcounters->hw_cntrs_hndl) 5805 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5806 mcounters->hw_cntrs_hndl); 5807 5808 kfree(mcounters); 5809 5810 return 0; 5811 } 5812 5813 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5814 struct uverbs_attr_bundle *attrs) 5815 { 5816 struct mlx5_ib_mcounters *mcounters; 5817 5818 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5819 if (!mcounters) 5820 return ERR_PTR(-ENOMEM); 5821 5822 mutex_init(&mcounters->mcntrs_mutex); 5823 5824 return &mcounters->ibcntrs; 5825 } 5826 5827 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5828 { 5829 mlx5_ib_cleanup_multiport_master(dev); 5830 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 5831 srcu_barrier(&dev->mr_srcu); 5832 cleanup_srcu_struct(&dev->mr_srcu); 5833 } 5834 kfree(dev->port); 5835 } 5836 5837 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5838 { 5839 struct mlx5_core_dev *mdev = dev->mdev; 5840 int err; 5841 int i; 5842 5843 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5844 GFP_KERNEL); 5845 if (!dev->port) 5846 return -ENOMEM; 5847 5848 for (i = 0; i < dev->num_ports; i++) { 5849 spin_lock_init(&dev->port[i].mp.mpi_lock); 5850 rwlock_init(&dev->roce[i].netdev_lock); 5851 } 5852 5853 err = mlx5_ib_init_multiport_master(dev); 5854 if (err) 5855 goto err_free_port; 5856 5857 if (!mlx5_core_mp_enabled(mdev)) { 5858 for (i = 1; i <= dev->num_ports; i++) { 5859 err = get_port_caps(dev, i); 5860 if (err) 5861 break; 5862 } 5863 } else { 5864 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5865 } 5866 if (err) 5867 goto err_mp; 5868 5869 if (mlx5_use_mad_ifc(dev)) 5870 get_ext_port_caps(dev); 5871 5872 dev->ib_dev.owner = THIS_MODULE; 5873 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5874 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5875 dev->ib_dev.phys_port_cnt = dev->num_ports; 5876 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 5877 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5878 5879 mutex_init(&dev->cap_mask_mutex); 5880 INIT_LIST_HEAD(&dev->qp_list); 5881 spin_lock_init(&dev->reset_flow_resource_lock); 5882 5883 spin_lock_init(&dev->memic.memic_lock); 5884 dev->memic.dev = mdev; 5885 5886 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 5887 err = init_srcu_struct(&dev->mr_srcu); 5888 if (err) 5889 goto err_mp; 5890 } 5891 5892 return 0; 5893 err_mp: 5894 mlx5_ib_cleanup_multiport_master(dev); 5895 5896 err_free_port: 5897 kfree(dev->port); 5898 5899 return -ENOMEM; 5900 } 5901 5902 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5903 { 5904 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5905 5906 if (!dev->flow_db) 5907 return -ENOMEM; 5908 5909 mutex_init(&dev->flow_db->lock); 5910 5911 return 0; 5912 } 5913 5914 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5915 { 5916 struct mlx5_ib_dev *nic_dev; 5917 5918 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5919 5920 if (!nic_dev) 5921 return -EINVAL; 5922 5923 dev->flow_db = nic_dev->flow_db; 5924 5925 return 0; 5926 } 5927 5928 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5929 { 5930 kfree(dev->flow_db); 5931 } 5932 5933 static const struct ib_device_ops mlx5_ib_dev_ops = { 5934 .add_gid = mlx5_ib_add_gid, 5935 .alloc_mr = mlx5_ib_alloc_mr, 5936 .alloc_pd = mlx5_ib_alloc_pd, 5937 .alloc_ucontext = mlx5_ib_alloc_ucontext, 5938 .attach_mcast = mlx5_ib_mcg_attach, 5939 .check_mr_status = mlx5_ib_check_mr_status, 5940 .create_ah = mlx5_ib_create_ah, 5941 .create_counters = mlx5_ib_create_counters, 5942 .create_cq = mlx5_ib_create_cq, 5943 .create_flow = mlx5_ib_create_flow, 5944 .create_qp = mlx5_ib_create_qp, 5945 .create_srq = mlx5_ib_create_srq, 5946 .dealloc_pd = mlx5_ib_dealloc_pd, 5947 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 5948 .del_gid = mlx5_ib_del_gid, 5949 .dereg_mr = mlx5_ib_dereg_mr, 5950 .destroy_ah = mlx5_ib_destroy_ah, 5951 .destroy_counters = mlx5_ib_destroy_counters, 5952 .destroy_cq = mlx5_ib_destroy_cq, 5953 .destroy_flow = mlx5_ib_destroy_flow, 5954 .destroy_flow_action = mlx5_ib_destroy_flow_action, 5955 .destroy_qp = mlx5_ib_destroy_qp, 5956 .destroy_srq = mlx5_ib_destroy_srq, 5957 .detach_mcast = mlx5_ib_mcg_detach, 5958 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 5959 .drain_rq = mlx5_ib_drain_rq, 5960 .drain_sq = mlx5_ib_drain_sq, 5961 .get_dev_fw_str = get_dev_fw_str, 5962 .get_dma_mr = mlx5_ib_get_dma_mr, 5963 .get_link_layer = mlx5_ib_port_link_layer, 5964 .map_mr_sg = mlx5_ib_map_mr_sg, 5965 .mmap = mlx5_ib_mmap, 5966 .modify_cq = mlx5_ib_modify_cq, 5967 .modify_device = mlx5_ib_modify_device, 5968 .modify_port = mlx5_ib_modify_port, 5969 .modify_qp = mlx5_ib_modify_qp, 5970 .modify_srq = mlx5_ib_modify_srq, 5971 .poll_cq = mlx5_ib_poll_cq, 5972 .post_recv = mlx5_ib_post_recv, 5973 .post_send = mlx5_ib_post_send, 5974 .post_srq_recv = mlx5_ib_post_srq_recv, 5975 .process_mad = mlx5_ib_process_mad, 5976 .query_ah = mlx5_ib_query_ah, 5977 .query_device = mlx5_ib_query_device, 5978 .query_gid = mlx5_ib_query_gid, 5979 .query_pkey = mlx5_ib_query_pkey, 5980 .query_qp = mlx5_ib_query_qp, 5981 .query_srq = mlx5_ib_query_srq, 5982 .read_counters = mlx5_ib_read_counters, 5983 .reg_user_mr = mlx5_ib_reg_user_mr, 5984 .req_notify_cq = mlx5_ib_arm_cq, 5985 .rereg_user_mr = mlx5_ib_rereg_user_mr, 5986 .resize_cq = mlx5_ib_resize_cq, 5987 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 5988 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 5989 }; 5990 5991 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = { 5992 .create_flow_action_esp = mlx5_ib_create_flow_action_esp, 5993 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp, 5994 }; 5995 5996 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 5997 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 5998 }; 5999 6000 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 6001 .get_vf_config = mlx5_ib_get_vf_config, 6002 .get_vf_stats = mlx5_ib_get_vf_stats, 6003 .set_vf_guid = mlx5_ib_set_vf_guid, 6004 .set_vf_link_state = mlx5_ib_set_vf_link_state, 6005 }; 6006 6007 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 6008 .alloc_mw = mlx5_ib_alloc_mw, 6009 .dealloc_mw = mlx5_ib_dealloc_mw, 6010 }; 6011 6012 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 6013 .alloc_xrcd = mlx5_ib_alloc_xrcd, 6014 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 6015 }; 6016 6017 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 6018 .alloc_dm = mlx5_ib_alloc_dm, 6019 .dealloc_dm = mlx5_ib_dealloc_dm, 6020 .reg_dm_mr = mlx5_ib_reg_dm_mr, 6021 }; 6022 6023 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 6024 { 6025 struct mlx5_core_dev *mdev = dev->mdev; 6026 int err; 6027 6028 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 6029 dev->ib_dev.uverbs_cmd_mask = 6030 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 6031 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 6032 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 6033 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 6034 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 6035 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 6036 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 6037 (1ull << IB_USER_VERBS_CMD_REG_MR) | 6038 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 6039 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 6040 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 6041 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 6042 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 6043 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 6044 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 6045 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 6046 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 6047 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 6048 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 6049 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 6050 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 6051 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 6052 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 6053 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 6054 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 6055 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 6056 dev->ib_dev.uverbs_ex_cmd_mask = 6057 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 6058 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 6059 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 6060 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 6061 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 6062 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 6063 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 6064 6065 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 6066 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 6067 ib_set_device_ops(&dev->ib_dev, 6068 &mlx5_ib_dev_ipoib_enhanced_ops); 6069 6070 if (mlx5_core_is_pf(mdev)) 6071 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 6072 6073 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 6074 6075 if (MLX5_CAP_GEN(mdev, imaicl)) { 6076 dev->ib_dev.uverbs_cmd_mask |= 6077 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 6078 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 6079 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 6080 } 6081 6082 if (MLX5_CAP_GEN(mdev, xrc)) { 6083 dev->ib_dev.uverbs_cmd_mask |= 6084 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 6085 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 6086 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 6087 } 6088 6089 if (MLX5_CAP_DEV_MEM(mdev, memic)) 6090 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 6091 6092 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 6093 MLX5_ACCEL_IPSEC_CAP_DEVICE) 6094 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops); 6095 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 6096 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 6097 6098 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 6099 dev->ib_dev.driver_def = mlx5_ib_defs; 6100 6101 err = init_node_data(dev); 6102 if (err) 6103 return err; 6104 6105 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 6106 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 6107 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 6108 mutex_init(&dev->lb.mutex); 6109 6110 return 0; 6111 } 6112 6113 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 6114 .get_port_immutable = mlx5_port_immutable, 6115 .query_port = mlx5_ib_query_port, 6116 }; 6117 6118 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 6119 { 6120 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 6121 return 0; 6122 } 6123 6124 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 6125 .get_port_immutable = mlx5_port_rep_immutable, 6126 .query_port = mlx5_ib_rep_query_port, 6127 }; 6128 6129 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 6130 { 6131 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 6132 return 0; 6133 } 6134 6135 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 6136 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 6137 .create_wq = mlx5_ib_create_wq, 6138 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 6139 .destroy_wq = mlx5_ib_destroy_wq, 6140 .get_netdev = mlx5_ib_get_netdev, 6141 .modify_wq = mlx5_ib_modify_wq, 6142 }; 6143 6144 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 6145 { 6146 u8 port_num; 6147 int i; 6148 6149 for (i = 0; i < dev->num_ports; i++) { 6150 dev->roce[i].dev = dev; 6151 dev->roce[i].native_port_num = i + 1; 6152 dev->roce[i].last_port_state = IB_PORT_DOWN; 6153 } 6154 6155 dev->ib_dev.uverbs_ex_cmd_mask |= 6156 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 6157 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 6158 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 6159 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 6160 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 6161 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 6162 6163 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6164 6165 return mlx5_add_netdev_notifier(dev, port_num); 6166 } 6167 6168 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 6169 { 6170 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6171 6172 mlx5_remove_netdev_notifier(dev, port_num); 6173 } 6174 6175 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 6176 { 6177 struct mlx5_core_dev *mdev = dev->mdev; 6178 enum rdma_link_layer ll; 6179 int port_type_cap; 6180 int err = 0; 6181 6182 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6183 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6184 6185 if (ll == IB_LINK_LAYER_ETHERNET) 6186 err = mlx5_ib_stage_common_roce_init(dev); 6187 6188 return err; 6189 } 6190 6191 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 6192 { 6193 mlx5_ib_stage_common_roce_cleanup(dev); 6194 } 6195 6196 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 6197 { 6198 struct mlx5_core_dev *mdev = dev->mdev; 6199 enum rdma_link_layer ll; 6200 int port_type_cap; 6201 int err; 6202 6203 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6204 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6205 6206 if (ll == IB_LINK_LAYER_ETHERNET) { 6207 err = mlx5_ib_stage_common_roce_init(dev); 6208 if (err) 6209 return err; 6210 6211 err = mlx5_enable_eth(dev); 6212 if (err) 6213 goto cleanup; 6214 } 6215 6216 return 0; 6217 cleanup: 6218 mlx5_ib_stage_common_roce_cleanup(dev); 6219 6220 return err; 6221 } 6222 6223 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6224 { 6225 struct mlx5_core_dev *mdev = dev->mdev; 6226 enum rdma_link_layer ll; 6227 int port_type_cap; 6228 6229 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6230 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6231 6232 if (ll == IB_LINK_LAYER_ETHERNET) { 6233 mlx5_disable_eth(dev); 6234 mlx5_ib_stage_common_roce_cleanup(dev); 6235 } 6236 } 6237 6238 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6239 { 6240 return create_dev_resources(&dev->devr); 6241 } 6242 6243 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6244 { 6245 destroy_dev_resources(&dev->devr); 6246 } 6247 6248 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6249 { 6250 mlx5_ib_internal_fill_odp_caps(dev); 6251 6252 return mlx5_ib_odp_init_one(dev); 6253 } 6254 6255 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 6256 { 6257 mlx5_ib_odp_cleanup_one(dev); 6258 } 6259 6260 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = { 6261 .alloc_hw_stats = mlx5_ib_alloc_hw_stats, 6262 .get_hw_stats = mlx5_ib_get_hw_stats, 6263 }; 6264 6265 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6266 { 6267 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6268 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops); 6269 6270 return mlx5_ib_alloc_counters(dev); 6271 } 6272 6273 return 0; 6274 } 6275 6276 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6277 { 6278 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6279 mlx5_ib_dealloc_counters(dev); 6280 } 6281 6282 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6283 { 6284 mlx5_ib_init_cong_debugfs(dev, 6285 mlx5_core_native_port_num(dev->mdev) - 1); 6286 return 0; 6287 } 6288 6289 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6290 { 6291 mlx5_ib_cleanup_cong_debugfs(dev, 6292 mlx5_core_native_port_num(dev->mdev) - 1); 6293 } 6294 6295 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6296 { 6297 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6298 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6299 } 6300 6301 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6302 { 6303 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6304 } 6305 6306 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6307 { 6308 int err; 6309 6310 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6311 if (err) 6312 return err; 6313 6314 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6315 if (err) 6316 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6317 6318 return err; 6319 } 6320 6321 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6322 { 6323 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6324 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6325 } 6326 6327 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6328 { 6329 const char *name; 6330 6331 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 6332 if (!mlx5_lag_is_roce(dev->mdev)) 6333 name = "mlx5_%d"; 6334 else 6335 name = "mlx5_bond_%d"; 6336 return ib_register_device(&dev->ib_dev, name); 6337 } 6338 6339 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6340 { 6341 destroy_umrc_res(dev); 6342 } 6343 6344 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6345 { 6346 ib_unregister_device(&dev->ib_dev); 6347 } 6348 6349 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6350 { 6351 return create_umr_res(dev); 6352 } 6353 6354 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6355 { 6356 init_delay_drop(dev); 6357 6358 return 0; 6359 } 6360 6361 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6362 { 6363 cancel_delay_drop(dev); 6364 } 6365 6366 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 6367 { 6368 dev->mdev_events.notifier_call = mlx5_ib_event; 6369 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 6370 return 0; 6371 } 6372 6373 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 6374 { 6375 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 6376 } 6377 6378 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev) 6379 { 6380 int uid; 6381 6382 uid = mlx5_ib_devx_create(dev, false); 6383 if (uid > 0) 6384 dev->devx_whitelist_uid = uid; 6385 6386 return 0; 6387 } 6388 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev) 6389 { 6390 if (dev->devx_whitelist_uid) 6391 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 6392 } 6393 6394 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6395 const struct mlx5_ib_profile *profile, 6396 int stage) 6397 { 6398 /* Number of stages to cleanup */ 6399 while (stage) { 6400 stage--; 6401 if (profile->stage[stage].cleanup) 6402 profile->stage[stage].cleanup(dev); 6403 } 6404 } 6405 6406 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6407 const struct mlx5_ib_profile *profile) 6408 { 6409 int err; 6410 int i; 6411 6412 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6413 if (profile->stage[i].init) { 6414 err = profile->stage[i].init(dev); 6415 if (err) 6416 goto err_out; 6417 } 6418 } 6419 6420 dev->profile = profile; 6421 dev->ib_active = true; 6422 6423 return dev; 6424 6425 err_out: 6426 __mlx5_ib_remove(dev, profile, i); 6427 6428 return NULL; 6429 } 6430 6431 static const struct mlx5_ib_profile pf_profile = { 6432 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6433 mlx5_ib_stage_init_init, 6434 mlx5_ib_stage_init_cleanup), 6435 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6436 mlx5_ib_stage_flow_db_init, 6437 mlx5_ib_stage_flow_db_cleanup), 6438 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6439 mlx5_ib_stage_caps_init, 6440 NULL), 6441 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6442 mlx5_ib_stage_non_default_cb, 6443 NULL), 6444 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6445 mlx5_ib_stage_roce_init, 6446 mlx5_ib_stage_roce_cleanup), 6447 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6448 mlx5_init_srq_table, 6449 mlx5_cleanup_srq_table), 6450 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6451 mlx5_ib_stage_dev_res_init, 6452 mlx5_ib_stage_dev_res_cleanup), 6453 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6454 mlx5_ib_stage_dev_notifier_init, 6455 mlx5_ib_stage_dev_notifier_cleanup), 6456 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6457 mlx5_ib_stage_odp_init, 6458 mlx5_ib_stage_odp_cleanup), 6459 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6460 mlx5_ib_stage_counters_init, 6461 mlx5_ib_stage_counters_cleanup), 6462 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6463 mlx5_ib_stage_cong_debugfs_init, 6464 mlx5_ib_stage_cong_debugfs_cleanup), 6465 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6466 mlx5_ib_stage_uar_init, 6467 mlx5_ib_stage_uar_cleanup), 6468 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6469 mlx5_ib_stage_bfrag_init, 6470 mlx5_ib_stage_bfrag_cleanup), 6471 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6472 NULL, 6473 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6474 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 6475 mlx5_ib_stage_devx_init, 6476 mlx5_ib_stage_devx_cleanup), 6477 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6478 mlx5_ib_stage_ib_reg_init, 6479 mlx5_ib_stage_ib_reg_cleanup), 6480 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6481 mlx5_ib_stage_post_ib_reg_umr_init, 6482 NULL), 6483 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6484 mlx5_ib_stage_delay_drop_init, 6485 mlx5_ib_stage_delay_drop_cleanup), 6486 }; 6487 6488 const struct mlx5_ib_profile uplink_rep_profile = { 6489 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6490 mlx5_ib_stage_init_init, 6491 mlx5_ib_stage_init_cleanup), 6492 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6493 mlx5_ib_stage_flow_db_init, 6494 mlx5_ib_stage_flow_db_cleanup), 6495 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6496 mlx5_ib_stage_caps_init, 6497 NULL), 6498 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6499 mlx5_ib_stage_rep_non_default_cb, 6500 NULL), 6501 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6502 mlx5_ib_stage_rep_roce_init, 6503 mlx5_ib_stage_rep_roce_cleanup), 6504 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6505 mlx5_init_srq_table, 6506 mlx5_cleanup_srq_table), 6507 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6508 mlx5_ib_stage_dev_res_init, 6509 mlx5_ib_stage_dev_res_cleanup), 6510 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6511 mlx5_ib_stage_dev_notifier_init, 6512 mlx5_ib_stage_dev_notifier_cleanup), 6513 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6514 mlx5_ib_stage_counters_init, 6515 mlx5_ib_stage_counters_cleanup), 6516 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6517 mlx5_ib_stage_uar_init, 6518 mlx5_ib_stage_uar_cleanup), 6519 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6520 mlx5_ib_stage_bfrag_init, 6521 mlx5_ib_stage_bfrag_cleanup), 6522 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6523 NULL, 6524 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6525 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6526 mlx5_ib_stage_ib_reg_init, 6527 mlx5_ib_stage_ib_reg_cleanup), 6528 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6529 mlx5_ib_stage_post_ib_reg_umr_init, 6530 NULL), 6531 }; 6532 6533 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6534 { 6535 struct mlx5_ib_multiport_info *mpi; 6536 struct mlx5_ib_dev *dev; 6537 bool bound = false; 6538 int err; 6539 6540 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6541 if (!mpi) 6542 return NULL; 6543 6544 mpi->mdev = mdev; 6545 6546 err = mlx5_query_nic_vport_system_image_guid(mdev, 6547 &mpi->sys_image_guid); 6548 if (err) { 6549 kfree(mpi); 6550 return NULL; 6551 } 6552 6553 mutex_lock(&mlx5_ib_multiport_mutex); 6554 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6555 if (dev->sys_image_guid == mpi->sys_image_guid) 6556 bound = mlx5_ib_bind_slave_port(dev, mpi); 6557 6558 if (bound) { 6559 rdma_roce_rescan_device(&dev->ib_dev); 6560 break; 6561 } 6562 } 6563 6564 if (!bound) { 6565 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6566 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6567 } 6568 mutex_unlock(&mlx5_ib_multiport_mutex); 6569 6570 return mpi; 6571 } 6572 6573 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6574 { 6575 enum rdma_link_layer ll; 6576 struct mlx5_ib_dev *dev; 6577 int port_type_cap; 6578 6579 printk_once(KERN_INFO "%s", mlx5_version); 6580 6581 if (MLX5_ESWITCH_MANAGER(mdev) && 6582 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6583 mlx5_ib_register_vport_reps(mdev); 6584 return mdev; 6585 } 6586 6587 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6588 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6589 6590 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6591 return mlx5_ib_add_slave_port(mdev); 6592 6593 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 6594 if (!dev) 6595 return NULL; 6596 6597 dev->mdev = mdev; 6598 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6599 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6600 6601 return __mlx5_ib_add(dev, &pf_profile); 6602 } 6603 6604 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6605 { 6606 struct mlx5_ib_multiport_info *mpi; 6607 struct mlx5_ib_dev *dev; 6608 6609 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 6610 mlx5_ib_unregister_vport_reps(mdev); 6611 return; 6612 } 6613 6614 if (mlx5_core_is_mp_slave(mdev)) { 6615 mpi = context; 6616 mutex_lock(&mlx5_ib_multiport_mutex); 6617 if (mpi->ibdev) 6618 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6619 list_del(&mpi->list); 6620 mutex_unlock(&mlx5_ib_multiport_mutex); 6621 return; 6622 } 6623 6624 dev = context; 6625 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6626 6627 ib_dealloc_device((struct ib_device *)dev); 6628 } 6629 6630 static struct mlx5_interface mlx5_ib_interface = { 6631 .add = mlx5_ib_add, 6632 .remove = mlx5_ib_remove, 6633 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6634 }; 6635 6636 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6637 { 6638 mutex_lock(&xlt_emergency_page_mutex); 6639 return xlt_emergency_page; 6640 } 6641 6642 void mlx5_ib_put_xlt_emergency_page(void) 6643 { 6644 mutex_unlock(&xlt_emergency_page_mutex); 6645 } 6646 6647 static int __init mlx5_ib_init(void) 6648 { 6649 int err; 6650 6651 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6652 if (!xlt_emergency_page) 6653 return -ENOMEM; 6654 6655 mutex_init(&xlt_emergency_page_mutex); 6656 6657 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6658 if (!mlx5_ib_event_wq) { 6659 free_page(xlt_emergency_page); 6660 return -ENOMEM; 6661 } 6662 6663 mlx5_ib_odp_init(); 6664 6665 err = mlx5_register_interface(&mlx5_ib_interface); 6666 6667 return err; 6668 } 6669 6670 static void __exit mlx5_ib_cleanup(void) 6671 { 6672 mlx5_unregister_interface(&mlx5_ib_interface); 6673 destroy_workqueue(mlx5_ib_event_wq); 6674 mutex_destroy(&xlt_emergency_page_mutex); 6675 free_page(xlt_emergency_page); 6676 } 6677 6678 module_init(mlx5_ib_init); 6679 module_exit(mlx5_ib_cleanup); 6680