1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/sched/mm.h> 45 #include <linux/sched/task.h> 46 #include <linux/delay.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_cache.h> 50 #include <linux/mlx5/port.h> 51 #include <linux/mlx5/vport.h> 52 #include <linux/list.h> 53 #include <rdma/ib_smi.h> 54 #include <rdma/ib_umem.h> 55 #include <linux/in.h> 56 #include <linux/etherdevice.h> 57 #include <linux/mlx5/fs.h> 58 #include <linux/mlx5/vport.h> 59 #include "mlx5_ib.h" 60 #include "cmd.h" 61 62 #define DRIVER_NAME "mlx5_ib" 63 #define DRIVER_VERSION "2.2-1" 64 #define DRIVER_RELDATE "Feb 2014" 65 66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 68 MODULE_LICENSE("Dual BSD/GPL"); 69 MODULE_VERSION(DRIVER_VERSION); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 switch (event) { 109 case NETDEV_REGISTER: 110 case NETDEV_UNREGISTER: 111 write_lock(&ibdev->roce.netdev_lock); 112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 114 NULL : ndev; 115 write_unlock(&ibdev->roce.netdev_lock); 116 break; 117 118 case NETDEV_UP: 119 case NETDEV_DOWN: { 120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 121 struct net_device *upper = NULL; 122 123 if (lag_ndev) { 124 upper = netdev_master_upper_dev_get(lag_ndev); 125 dev_put(lag_ndev); 126 } 127 128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 129 && ibdev->ib_active) { 130 struct ib_event ibev = { }; 131 132 ibev.device = &ibdev->ib_dev; 133 ibev.event = (event == NETDEV_UP) ? 134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 135 ibev.element.port_num = 1; 136 ib_dispatch_event(&ibev); 137 } 138 break; 139 } 140 141 default: 142 break; 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 149 u8 port_num) 150 { 151 struct mlx5_ib_dev *ibdev = to_mdev(device); 152 struct net_device *ndev; 153 154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 155 if (ndev) 156 return ndev; 157 158 /* Ensure ndev does not disappear before we invoke dev_hold() 159 */ 160 read_lock(&ibdev->roce.netdev_lock); 161 ndev = ibdev->roce.netdev; 162 if (ndev) 163 dev_hold(ndev); 164 read_unlock(&ibdev->roce.netdev_lock); 165 166 return ndev; 167 } 168 169 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 170 u8 *active_width) 171 { 172 switch (eth_proto_oper) { 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 174 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 175 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 176 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 177 *active_width = IB_WIDTH_1X; 178 *active_speed = IB_SPEED_SDR; 179 break; 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 184 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 185 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 186 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 187 *active_width = IB_WIDTH_1X; 188 *active_speed = IB_SPEED_QDR; 189 break; 190 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 191 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 192 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 193 *active_width = IB_WIDTH_1X; 194 *active_speed = IB_SPEED_EDR; 195 break; 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 197 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 198 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 199 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 200 *active_width = IB_WIDTH_4X; 201 *active_speed = IB_SPEED_QDR; 202 break; 203 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 204 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 205 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 206 *active_width = IB_WIDTH_1X; 207 *active_speed = IB_SPEED_HDR; 208 break; 209 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 210 *active_width = IB_WIDTH_4X; 211 *active_speed = IB_SPEED_FDR; 212 break; 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 214 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 215 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 216 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 217 *active_width = IB_WIDTH_4X; 218 *active_speed = IB_SPEED_EDR; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 return 0; 225 } 226 227 static void mlx5_query_port_roce(struct ib_device *device, u8 port_num, 228 struct ib_port_attr *props) 229 { 230 struct mlx5_ib_dev *dev = to_mdev(device); 231 struct mlx5_core_dev *mdev = dev->mdev; 232 struct net_device *ndev, *upper; 233 enum ib_mtu ndev_ib_mtu; 234 u16 qkey_viol_cntr; 235 u32 eth_prot_oper; 236 237 /* Possible bad flows are checked before filling out props so in case 238 * of an error it will still be zeroed out. 239 */ 240 if (mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num)) 241 return; 242 243 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 244 &props->active_width); 245 246 props->port_cap_flags |= IB_PORT_CM_SUP; 247 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 248 249 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 250 roce_address_table_size); 251 props->max_mtu = IB_MTU_4096; 252 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 253 props->pkey_tbl_len = 1; 254 props->state = IB_PORT_DOWN; 255 props->phys_state = 3; 256 257 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 258 props->qkey_viol_cntr = qkey_viol_cntr; 259 260 ndev = mlx5_ib_get_netdev(device, port_num); 261 if (!ndev) 262 return; 263 264 if (mlx5_lag_is_active(dev->mdev)) { 265 rcu_read_lock(); 266 upper = netdev_master_upper_dev_get_rcu(ndev); 267 if (upper) { 268 dev_put(ndev); 269 ndev = upper; 270 dev_hold(ndev); 271 } 272 rcu_read_unlock(); 273 } 274 275 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 276 props->state = IB_PORT_ACTIVE; 277 props->phys_state = 5; 278 } 279 280 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 281 282 dev_put(ndev); 283 284 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 285 } 286 287 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 288 const struct ib_gid_attr *attr, 289 void *mlx5_addr) 290 { 291 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 292 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 293 source_l3_address); 294 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 295 source_mac_47_32); 296 297 if (!gid) 298 return; 299 300 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 301 302 if (is_vlan_dev(attr->ndev)) { 303 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 304 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 305 } 306 307 switch (attr->gid_type) { 308 case IB_GID_TYPE_IB: 309 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 310 break; 311 case IB_GID_TYPE_ROCE_UDP_ENCAP: 312 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 313 break; 314 315 default: 316 WARN_ON(true); 317 } 318 319 if (attr->gid_type != IB_GID_TYPE_IB) { 320 if (ipv6_addr_v4mapped((void *)gid)) 321 MLX5_SET_RA(mlx5_addr, roce_l3_type, 322 MLX5_ROCE_L3_TYPE_IPV4); 323 else 324 MLX5_SET_RA(mlx5_addr, roce_l3_type, 325 MLX5_ROCE_L3_TYPE_IPV6); 326 } 327 328 if ((attr->gid_type == IB_GID_TYPE_IB) || 329 !ipv6_addr_v4mapped((void *)gid)) 330 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 331 else 332 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 333 } 334 335 static int set_roce_addr(struct ib_device *device, u8 port_num, 336 unsigned int index, 337 const union ib_gid *gid, 338 const struct ib_gid_attr *attr) 339 { 340 struct mlx5_ib_dev *dev = to_mdev(device); 341 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 342 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 343 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 344 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 345 346 if (ll != IB_LINK_LAYER_ETHERNET) 347 return -EINVAL; 348 349 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 350 351 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 352 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 353 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 354 } 355 356 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 357 unsigned int index, const union ib_gid *gid, 358 const struct ib_gid_attr *attr, 359 __always_unused void **context) 360 { 361 return set_roce_addr(device, port_num, index, gid, attr); 362 } 363 364 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 365 unsigned int index, __always_unused void **context) 366 { 367 return set_roce_addr(device, port_num, index, NULL, NULL); 368 } 369 370 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 371 int index) 372 { 373 struct ib_gid_attr attr; 374 union ib_gid gid; 375 376 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 377 return 0; 378 379 if (!attr.ndev) 380 return 0; 381 382 dev_put(attr.ndev); 383 384 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 385 return 0; 386 387 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 388 } 389 390 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 391 int index, enum ib_gid_type *gid_type) 392 { 393 struct ib_gid_attr attr; 394 union ib_gid gid; 395 int ret; 396 397 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 398 if (ret) 399 return ret; 400 401 if (!attr.ndev) 402 return -ENODEV; 403 404 dev_put(attr.ndev); 405 406 *gid_type = attr.gid_type; 407 408 return 0; 409 } 410 411 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 412 { 413 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 414 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 415 return 0; 416 } 417 418 enum { 419 MLX5_VPORT_ACCESS_METHOD_MAD, 420 MLX5_VPORT_ACCESS_METHOD_HCA, 421 MLX5_VPORT_ACCESS_METHOD_NIC, 422 }; 423 424 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 425 { 426 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 427 return MLX5_VPORT_ACCESS_METHOD_MAD; 428 429 if (mlx5_ib_port_link_layer(ibdev, 1) == 430 IB_LINK_LAYER_ETHERNET) 431 return MLX5_VPORT_ACCESS_METHOD_NIC; 432 433 return MLX5_VPORT_ACCESS_METHOD_HCA; 434 } 435 436 static void get_atomic_caps(struct mlx5_ib_dev *dev, 437 struct ib_device_attr *props) 438 { 439 u8 tmp; 440 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 441 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 442 u8 atomic_req_8B_endianness_mode = 443 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 444 445 /* Check if HW supports 8 bytes standard atomic operations and capable 446 * of host endianness respond 447 */ 448 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 449 if (((atomic_operations & tmp) == tmp) && 450 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 451 (atomic_req_8B_endianness_mode)) { 452 props->atomic_cap = IB_ATOMIC_HCA; 453 } else { 454 props->atomic_cap = IB_ATOMIC_NONE; 455 } 456 } 457 458 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 459 __be64 *sys_image_guid) 460 { 461 struct mlx5_ib_dev *dev = to_mdev(ibdev); 462 struct mlx5_core_dev *mdev = dev->mdev; 463 u64 tmp; 464 int err; 465 466 switch (mlx5_get_vport_access_method(ibdev)) { 467 case MLX5_VPORT_ACCESS_METHOD_MAD: 468 return mlx5_query_mad_ifc_system_image_guid(ibdev, 469 sys_image_guid); 470 471 case MLX5_VPORT_ACCESS_METHOD_HCA: 472 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 473 break; 474 475 case MLX5_VPORT_ACCESS_METHOD_NIC: 476 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 default: 480 return -EINVAL; 481 } 482 483 if (!err) 484 *sys_image_guid = cpu_to_be64(tmp); 485 486 return err; 487 488 } 489 490 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 491 u16 *max_pkeys) 492 { 493 struct mlx5_ib_dev *dev = to_mdev(ibdev); 494 struct mlx5_core_dev *mdev = dev->mdev; 495 496 switch (mlx5_get_vport_access_method(ibdev)) { 497 case MLX5_VPORT_ACCESS_METHOD_MAD: 498 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 499 500 case MLX5_VPORT_ACCESS_METHOD_HCA: 501 case MLX5_VPORT_ACCESS_METHOD_NIC: 502 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 503 pkey_table_size)); 504 return 0; 505 506 default: 507 return -EINVAL; 508 } 509 } 510 511 static int mlx5_query_vendor_id(struct ib_device *ibdev, 512 u32 *vendor_id) 513 { 514 struct mlx5_ib_dev *dev = to_mdev(ibdev); 515 516 switch (mlx5_get_vport_access_method(ibdev)) { 517 case MLX5_VPORT_ACCESS_METHOD_MAD: 518 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 519 520 case MLX5_VPORT_ACCESS_METHOD_HCA: 521 case MLX5_VPORT_ACCESS_METHOD_NIC: 522 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 523 524 default: 525 return -EINVAL; 526 } 527 } 528 529 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 530 __be64 *node_guid) 531 { 532 u64 tmp; 533 int err; 534 535 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 536 case MLX5_VPORT_ACCESS_METHOD_MAD: 537 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 538 539 case MLX5_VPORT_ACCESS_METHOD_HCA: 540 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 541 break; 542 543 case MLX5_VPORT_ACCESS_METHOD_NIC: 544 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 default: 548 return -EINVAL; 549 } 550 551 if (!err) 552 *node_guid = cpu_to_be64(tmp); 553 554 return err; 555 } 556 557 struct mlx5_reg_node_desc { 558 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 559 }; 560 561 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 562 { 563 struct mlx5_reg_node_desc in; 564 565 if (mlx5_use_mad_ifc(dev)) 566 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 567 568 memset(&in, 0, sizeof(in)); 569 570 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 571 sizeof(struct mlx5_reg_node_desc), 572 MLX5_REG_NODE_DESC, 0, 0); 573 } 574 575 static int mlx5_ib_query_device(struct ib_device *ibdev, 576 struct ib_device_attr *props, 577 struct ib_udata *uhw) 578 { 579 struct mlx5_ib_dev *dev = to_mdev(ibdev); 580 struct mlx5_core_dev *mdev = dev->mdev; 581 int err = -ENOMEM; 582 int max_sq_desc; 583 int max_rq_sg; 584 int max_sq_sg; 585 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 586 struct mlx5_ib_query_device_resp resp = {}; 587 size_t resp_len; 588 u64 max_tso; 589 590 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 591 if (uhw->outlen && uhw->outlen < resp_len) 592 return -EINVAL; 593 else 594 resp.response_length = resp_len; 595 596 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 597 return -EINVAL; 598 599 memset(props, 0, sizeof(*props)); 600 err = mlx5_query_system_image_guid(ibdev, 601 &props->sys_image_guid); 602 if (err) 603 return err; 604 605 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 606 if (err) 607 return err; 608 609 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 610 if (err) 611 return err; 612 613 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 614 (fw_rev_min(dev->mdev) << 16) | 615 fw_rev_sub(dev->mdev); 616 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 617 IB_DEVICE_PORT_ACTIVE_EVENT | 618 IB_DEVICE_SYS_IMAGE_GUID | 619 IB_DEVICE_RC_RNR_NAK_GEN; 620 621 if (MLX5_CAP_GEN(mdev, pkv)) 622 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 623 if (MLX5_CAP_GEN(mdev, qkv)) 624 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 625 if (MLX5_CAP_GEN(mdev, apm)) 626 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 627 if (MLX5_CAP_GEN(mdev, xrc)) 628 props->device_cap_flags |= IB_DEVICE_XRC; 629 if (MLX5_CAP_GEN(mdev, imaicl)) { 630 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 631 IB_DEVICE_MEM_WINDOW_TYPE_2B; 632 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 633 /* We support 'Gappy' memory registration too */ 634 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 635 } 636 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 637 if (MLX5_CAP_GEN(mdev, sho)) { 638 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 639 /* At this stage no support for signature handover */ 640 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 641 IB_PROT_T10DIF_TYPE_2 | 642 IB_PROT_T10DIF_TYPE_3; 643 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 644 IB_GUARD_T10DIF_CSUM; 645 } 646 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 647 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 648 649 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 650 if (MLX5_CAP_ETH(mdev, csum_cap)) { 651 /* Legacy bit to support old userspace libraries */ 652 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 653 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 654 } 655 656 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 657 props->raw_packet_caps |= 658 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 659 660 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 661 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 662 if (max_tso) { 663 resp.tso_caps.max_tso = 1 << max_tso; 664 resp.tso_caps.supported_qpts |= 665 1 << IB_QPT_RAW_PACKET; 666 resp.response_length += sizeof(resp.tso_caps); 667 } 668 } 669 670 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 671 resp.rss_caps.rx_hash_function = 672 MLX5_RX_HASH_FUNC_TOEPLITZ; 673 resp.rss_caps.rx_hash_fields_mask = 674 MLX5_RX_HASH_SRC_IPV4 | 675 MLX5_RX_HASH_DST_IPV4 | 676 MLX5_RX_HASH_SRC_IPV6 | 677 MLX5_RX_HASH_DST_IPV6 | 678 MLX5_RX_HASH_SRC_PORT_TCP | 679 MLX5_RX_HASH_DST_PORT_TCP | 680 MLX5_RX_HASH_SRC_PORT_UDP | 681 MLX5_RX_HASH_DST_PORT_UDP; 682 resp.response_length += sizeof(resp.rss_caps); 683 } 684 } else { 685 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 686 resp.response_length += sizeof(resp.tso_caps); 687 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 688 resp.response_length += sizeof(resp.rss_caps); 689 } 690 691 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 692 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 693 props->device_cap_flags |= IB_DEVICE_UD_TSO; 694 } 695 696 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 697 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 698 /* Legacy bit to support old userspace libraries */ 699 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 700 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 701 } 702 703 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 704 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 705 706 props->vendor_part_id = mdev->pdev->device; 707 props->hw_ver = mdev->pdev->revision; 708 709 props->max_mr_size = ~0ull; 710 props->page_size_cap = ~(min_page_size - 1); 711 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 712 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 713 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 714 sizeof(struct mlx5_wqe_data_seg); 715 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 716 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 717 sizeof(struct mlx5_wqe_raddr_seg)) / 718 sizeof(struct mlx5_wqe_data_seg); 719 props->max_sge = min(max_rq_sg, max_sq_sg); 720 props->max_sge_rd = MLX5_MAX_SGE_RD; 721 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 722 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 723 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 724 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 725 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 726 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 727 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 728 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 729 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 730 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 731 props->max_srq_sge = max_rq_sg - 1; 732 props->max_fast_reg_page_list_len = 733 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 734 get_atomic_caps(dev, props); 735 props->masked_atomic_cap = IB_ATOMIC_NONE; 736 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 737 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 738 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 739 props->max_mcast_grp; 740 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 741 props->max_ah = INT_MAX; 742 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 743 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 744 745 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 746 if (MLX5_CAP_GEN(mdev, pg)) 747 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 748 props->odp_caps = dev->odp_caps; 749 #endif 750 751 if (MLX5_CAP_GEN(mdev, cd)) 752 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 753 754 if (!mlx5_core_is_pf(mdev)) 755 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 756 757 if (mlx5_ib_port_link_layer(ibdev, 1) == 758 IB_LINK_LAYER_ETHERNET) { 759 props->rss_caps.max_rwq_indirection_tables = 760 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 761 props->rss_caps.max_rwq_indirection_table_size = 762 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 763 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 764 props->max_wq_type_rq = 765 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 766 } 767 768 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 769 resp.cqe_comp_caps.max_num = 770 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 771 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 772 resp.cqe_comp_caps.supported_format = 773 MLX5_IB_CQE_RES_FORMAT_HASH | 774 MLX5_IB_CQE_RES_FORMAT_CSUM; 775 resp.response_length += sizeof(resp.cqe_comp_caps); 776 } 777 778 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 779 if (MLX5_CAP_QOS(mdev, packet_pacing) && 780 MLX5_CAP_GEN(mdev, qos)) { 781 resp.packet_pacing_caps.qp_rate_limit_max = 782 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 783 resp.packet_pacing_caps.qp_rate_limit_min = 784 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 785 resp.packet_pacing_caps.supported_qpts |= 786 1 << IB_QPT_RAW_PACKET; 787 } 788 resp.response_length += sizeof(resp.packet_pacing_caps); 789 } 790 791 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 792 uhw->outlen)) { 793 resp.mlx5_ib_support_multi_pkt_send_wqes = 794 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 795 resp.response_length += 796 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 797 } 798 799 if (field_avail(typeof(resp), reserved, uhw->outlen)) 800 resp.response_length += sizeof(resp.reserved); 801 802 if (uhw->outlen) { 803 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 804 805 if (err) 806 return err; 807 } 808 809 return 0; 810 } 811 812 enum mlx5_ib_width { 813 MLX5_IB_WIDTH_1X = 1 << 0, 814 MLX5_IB_WIDTH_2X = 1 << 1, 815 MLX5_IB_WIDTH_4X = 1 << 2, 816 MLX5_IB_WIDTH_8X = 1 << 3, 817 MLX5_IB_WIDTH_12X = 1 << 4 818 }; 819 820 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 821 u8 *ib_width) 822 { 823 struct mlx5_ib_dev *dev = to_mdev(ibdev); 824 int err = 0; 825 826 if (active_width & MLX5_IB_WIDTH_1X) { 827 *ib_width = IB_WIDTH_1X; 828 } else if (active_width & MLX5_IB_WIDTH_2X) { 829 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 830 (int)active_width); 831 err = -EINVAL; 832 } else if (active_width & MLX5_IB_WIDTH_4X) { 833 *ib_width = IB_WIDTH_4X; 834 } else if (active_width & MLX5_IB_WIDTH_8X) { 835 *ib_width = IB_WIDTH_8X; 836 } else if (active_width & MLX5_IB_WIDTH_12X) { 837 *ib_width = IB_WIDTH_12X; 838 } else { 839 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 840 (int)active_width); 841 err = -EINVAL; 842 } 843 844 return err; 845 } 846 847 static int mlx5_mtu_to_ib_mtu(int mtu) 848 { 849 switch (mtu) { 850 case 256: return 1; 851 case 512: return 2; 852 case 1024: return 3; 853 case 2048: return 4; 854 case 4096: return 5; 855 default: 856 pr_warn("invalid mtu\n"); 857 return -1; 858 } 859 } 860 861 enum ib_max_vl_num { 862 __IB_MAX_VL_0 = 1, 863 __IB_MAX_VL_0_1 = 2, 864 __IB_MAX_VL_0_3 = 3, 865 __IB_MAX_VL_0_7 = 4, 866 __IB_MAX_VL_0_14 = 5, 867 }; 868 869 enum mlx5_vl_hw_cap { 870 MLX5_VL_HW_0 = 1, 871 MLX5_VL_HW_0_1 = 2, 872 MLX5_VL_HW_0_2 = 3, 873 MLX5_VL_HW_0_3 = 4, 874 MLX5_VL_HW_0_4 = 5, 875 MLX5_VL_HW_0_5 = 6, 876 MLX5_VL_HW_0_6 = 7, 877 MLX5_VL_HW_0_7 = 8, 878 MLX5_VL_HW_0_14 = 15 879 }; 880 881 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 882 u8 *max_vl_num) 883 { 884 switch (vl_hw_cap) { 885 case MLX5_VL_HW_0: 886 *max_vl_num = __IB_MAX_VL_0; 887 break; 888 case MLX5_VL_HW_0_1: 889 *max_vl_num = __IB_MAX_VL_0_1; 890 break; 891 case MLX5_VL_HW_0_3: 892 *max_vl_num = __IB_MAX_VL_0_3; 893 break; 894 case MLX5_VL_HW_0_7: 895 *max_vl_num = __IB_MAX_VL_0_7; 896 break; 897 case MLX5_VL_HW_0_14: 898 *max_vl_num = __IB_MAX_VL_0_14; 899 break; 900 901 default: 902 return -EINVAL; 903 } 904 905 return 0; 906 } 907 908 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 909 struct ib_port_attr *props) 910 { 911 struct mlx5_ib_dev *dev = to_mdev(ibdev); 912 struct mlx5_core_dev *mdev = dev->mdev; 913 struct mlx5_hca_vport_context *rep; 914 u16 max_mtu; 915 u16 oper_mtu; 916 int err; 917 u8 ib_link_width_oper; 918 u8 vl_hw_cap; 919 920 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 921 if (!rep) { 922 err = -ENOMEM; 923 goto out; 924 } 925 926 /* props being zeroed by the caller, avoid zeroing it here */ 927 928 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 929 if (err) 930 goto out; 931 932 props->lid = rep->lid; 933 props->lmc = rep->lmc; 934 props->sm_lid = rep->sm_lid; 935 props->sm_sl = rep->sm_sl; 936 props->state = rep->vport_state; 937 props->phys_state = rep->port_physical_state; 938 props->port_cap_flags = rep->cap_mask1; 939 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 940 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 941 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 942 props->bad_pkey_cntr = rep->pkey_violation_counter; 943 props->qkey_viol_cntr = rep->qkey_violation_counter; 944 props->subnet_timeout = rep->subnet_timeout; 945 props->init_type_reply = rep->init_type_reply; 946 props->grh_required = rep->grh_required; 947 948 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 949 if (err) 950 goto out; 951 952 err = translate_active_width(ibdev, ib_link_width_oper, 953 &props->active_width); 954 if (err) 955 goto out; 956 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 957 if (err) 958 goto out; 959 960 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 961 962 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 963 964 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 965 966 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 967 968 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 969 if (err) 970 goto out; 971 972 err = translate_max_vl_num(ibdev, vl_hw_cap, 973 &props->max_vl_num); 974 out: 975 kfree(rep); 976 return err; 977 } 978 979 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 980 struct ib_port_attr *props) 981 { 982 switch (mlx5_get_vport_access_method(ibdev)) { 983 case MLX5_VPORT_ACCESS_METHOD_MAD: 984 return mlx5_query_mad_ifc_port(ibdev, port, props); 985 986 case MLX5_VPORT_ACCESS_METHOD_HCA: 987 return mlx5_query_hca_port(ibdev, port, props); 988 989 case MLX5_VPORT_ACCESS_METHOD_NIC: 990 mlx5_query_port_roce(ibdev, port, props); 991 return 0; 992 993 default: 994 return -EINVAL; 995 } 996 } 997 998 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 999 union ib_gid *gid) 1000 { 1001 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1002 struct mlx5_core_dev *mdev = dev->mdev; 1003 1004 switch (mlx5_get_vport_access_method(ibdev)) { 1005 case MLX5_VPORT_ACCESS_METHOD_MAD: 1006 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1007 1008 case MLX5_VPORT_ACCESS_METHOD_HCA: 1009 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1010 1011 default: 1012 return -EINVAL; 1013 } 1014 1015 } 1016 1017 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1018 u16 *pkey) 1019 { 1020 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1021 struct mlx5_core_dev *mdev = dev->mdev; 1022 1023 switch (mlx5_get_vport_access_method(ibdev)) { 1024 case MLX5_VPORT_ACCESS_METHOD_MAD: 1025 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1026 1027 case MLX5_VPORT_ACCESS_METHOD_HCA: 1028 case MLX5_VPORT_ACCESS_METHOD_NIC: 1029 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1030 pkey); 1031 default: 1032 return -EINVAL; 1033 } 1034 } 1035 1036 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1037 struct ib_device_modify *props) 1038 { 1039 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1040 struct mlx5_reg_node_desc in; 1041 struct mlx5_reg_node_desc out; 1042 int err; 1043 1044 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1045 return -EOPNOTSUPP; 1046 1047 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1048 return 0; 1049 1050 /* 1051 * If possible, pass node desc to FW, so it can generate 1052 * a 144 trap. If cmd fails, just ignore. 1053 */ 1054 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1055 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1056 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1057 if (err) 1058 return err; 1059 1060 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1061 1062 return err; 1063 } 1064 1065 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1066 u32 value) 1067 { 1068 struct mlx5_hca_vport_context ctx = {}; 1069 int err; 1070 1071 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1072 port_num, 0, &ctx); 1073 if (err) 1074 return err; 1075 1076 if (~ctx.cap_mask1_perm & mask) { 1077 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1078 mask, ctx.cap_mask1_perm); 1079 return -EINVAL; 1080 } 1081 1082 ctx.cap_mask1 = value; 1083 ctx.cap_mask1_perm = mask; 1084 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1085 port_num, 0, &ctx); 1086 1087 return err; 1088 } 1089 1090 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1091 struct ib_port_modify *props) 1092 { 1093 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1094 struct ib_port_attr attr; 1095 u32 tmp; 1096 int err; 1097 u32 change_mask; 1098 u32 value; 1099 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1100 IB_LINK_LAYER_INFINIBAND); 1101 1102 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1103 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1104 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1105 return set_port_caps_atomic(dev, port, change_mask, value); 1106 } 1107 1108 mutex_lock(&dev->cap_mask_mutex); 1109 1110 err = ib_query_port(ibdev, port, &attr); 1111 if (err) 1112 goto out; 1113 1114 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1115 ~props->clr_port_cap_mask; 1116 1117 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1118 1119 out: 1120 mutex_unlock(&dev->cap_mask_mutex); 1121 return err; 1122 } 1123 1124 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1125 { 1126 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1127 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1128 } 1129 1130 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1131 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1132 u32 *num_sys_pages) 1133 { 1134 int uars_per_sys_page; 1135 int bfregs_per_sys_page; 1136 int ref_bfregs = req->total_num_bfregs; 1137 1138 if (req->total_num_bfregs == 0) 1139 return -EINVAL; 1140 1141 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1142 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1143 1144 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1145 return -ENOMEM; 1146 1147 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1148 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1149 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1150 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1151 1152 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1153 return -EINVAL; 1154 1155 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n", 1156 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1157 lib_uar_4k ? "yes" : "no", ref_bfregs, 1158 req->total_num_bfregs, *num_sys_pages); 1159 1160 return 0; 1161 } 1162 1163 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1164 { 1165 struct mlx5_bfreg_info *bfregi; 1166 int err; 1167 int i; 1168 1169 bfregi = &context->bfregi; 1170 for (i = 0; i < bfregi->num_sys_pages; i++) { 1171 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1172 if (err) 1173 goto error; 1174 1175 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1176 } 1177 return 0; 1178 1179 error: 1180 for (--i; i >= 0; i--) 1181 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1182 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1183 1184 return err; 1185 } 1186 1187 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1188 { 1189 struct mlx5_bfreg_info *bfregi; 1190 int err; 1191 int i; 1192 1193 bfregi = &context->bfregi; 1194 for (i = 0; i < bfregi->num_sys_pages; i++) { 1195 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1196 if (err) { 1197 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1198 return err; 1199 } 1200 } 1201 return 0; 1202 } 1203 1204 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1205 struct ib_udata *udata) 1206 { 1207 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1208 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1209 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1210 struct mlx5_ib_ucontext *context; 1211 struct mlx5_bfreg_info *bfregi; 1212 int ver; 1213 int err; 1214 size_t reqlen; 1215 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1216 max_cqe_version); 1217 bool lib_uar_4k; 1218 1219 if (!dev->ib_active) 1220 return ERR_PTR(-EAGAIN); 1221 1222 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1223 return ERR_PTR(-EINVAL); 1224 1225 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1226 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1227 ver = 0; 1228 else if (reqlen >= min_req_v2) 1229 ver = 2; 1230 else 1231 return ERR_PTR(-EINVAL); 1232 1233 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1234 if (err) 1235 return ERR_PTR(err); 1236 1237 if (req.flags) 1238 return ERR_PTR(-EINVAL); 1239 1240 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1241 return ERR_PTR(-EOPNOTSUPP); 1242 1243 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1244 MLX5_NON_FP_BFREGS_PER_UAR); 1245 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1246 return ERR_PTR(-EINVAL); 1247 1248 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1249 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1250 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1251 resp.cache_line_size = cache_line_size(); 1252 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1253 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1254 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1255 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1256 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1257 resp.cqe_version = min_t(__u8, 1258 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1259 req.max_cqe_version); 1260 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1261 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1262 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1263 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1264 resp.response_length = min(offsetof(typeof(resp), response_length) + 1265 sizeof(resp.response_length), udata->outlen); 1266 1267 context = kzalloc(sizeof(*context), GFP_KERNEL); 1268 if (!context) 1269 return ERR_PTR(-ENOMEM); 1270 1271 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1272 bfregi = &context->bfregi; 1273 1274 /* updates req->total_num_bfregs */ 1275 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1276 if (err) 1277 goto out_ctx; 1278 1279 mutex_init(&bfregi->lock); 1280 bfregi->lib_uar_4k = lib_uar_4k; 1281 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1282 GFP_KERNEL); 1283 if (!bfregi->count) { 1284 err = -ENOMEM; 1285 goto out_ctx; 1286 } 1287 1288 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1289 sizeof(*bfregi->sys_pages), 1290 GFP_KERNEL); 1291 if (!bfregi->sys_pages) { 1292 err = -ENOMEM; 1293 goto out_count; 1294 } 1295 1296 err = allocate_uars(dev, context); 1297 if (err) 1298 goto out_sys_pages; 1299 1300 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1301 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1302 #endif 1303 1304 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1305 if (!context->upd_xlt_page) { 1306 err = -ENOMEM; 1307 goto out_uars; 1308 } 1309 mutex_init(&context->upd_xlt_page_mutex); 1310 1311 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1312 err = mlx5_core_alloc_transport_domain(dev->mdev, 1313 &context->tdn); 1314 if (err) 1315 goto out_page; 1316 } 1317 1318 INIT_LIST_HEAD(&context->vma_private_list); 1319 INIT_LIST_HEAD(&context->db_page_list); 1320 mutex_init(&context->db_page_mutex); 1321 1322 resp.tot_bfregs = req.total_num_bfregs; 1323 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1324 1325 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1326 resp.response_length += sizeof(resp.cqe_version); 1327 1328 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1329 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1330 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1331 resp.response_length += sizeof(resp.cmds_supp_uhw); 1332 } 1333 1334 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1335 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1336 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1337 resp.eth_min_inline++; 1338 } 1339 resp.response_length += sizeof(resp.eth_min_inline); 1340 } 1341 1342 /* 1343 * We don't want to expose information from the PCI bar that is located 1344 * after 4096 bytes, so if the arch only supports larger pages, let's 1345 * pretend we don't support reading the HCA's core clock. This is also 1346 * forced by mmap function. 1347 */ 1348 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1349 if (PAGE_SIZE <= 4096) { 1350 resp.comp_mask |= 1351 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1352 resp.hca_core_clock_offset = 1353 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1354 } 1355 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1356 sizeof(resp.reserved2); 1357 } 1358 1359 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1360 resp.response_length += sizeof(resp.log_uar_size); 1361 1362 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1363 resp.response_length += sizeof(resp.num_uars_per_page); 1364 1365 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1366 if (err) 1367 goto out_td; 1368 1369 bfregi->ver = ver; 1370 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1371 context->cqe_version = resp.cqe_version; 1372 context->lib_caps = req.lib_caps; 1373 print_lib_caps(dev, context->lib_caps); 1374 1375 return &context->ibucontext; 1376 1377 out_td: 1378 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1379 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1380 1381 out_page: 1382 free_page(context->upd_xlt_page); 1383 1384 out_uars: 1385 deallocate_uars(dev, context); 1386 1387 out_sys_pages: 1388 kfree(bfregi->sys_pages); 1389 1390 out_count: 1391 kfree(bfregi->count); 1392 1393 out_ctx: 1394 kfree(context); 1395 1396 return ERR_PTR(err); 1397 } 1398 1399 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1400 { 1401 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1402 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1403 struct mlx5_bfreg_info *bfregi; 1404 1405 bfregi = &context->bfregi; 1406 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1407 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1408 1409 free_page(context->upd_xlt_page); 1410 deallocate_uars(dev, context); 1411 kfree(bfregi->sys_pages); 1412 kfree(bfregi->count); 1413 kfree(context); 1414 1415 return 0; 1416 } 1417 1418 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1419 struct mlx5_bfreg_info *bfregi, 1420 int idx) 1421 { 1422 int fw_uars_per_page; 1423 1424 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1425 1426 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1427 bfregi->sys_pages[idx] / fw_uars_per_page; 1428 } 1429 1430 static int get_command(unsigned long offset) 1431 { 1432 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1433 } 1434 1435 static int get_arg(unsigned long offset) 1436 { 1437 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1438 } 1439 1440 static int get_index(unsigned long offset) 1441 { 1442 return get_arg(offset); 1443 } 1444 1445 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1446 { 1447 /* vma_open is called when a new VMA is created on top of our VMA. This 1448 * is done through either mremap flow or split_vma (usually due to 1449 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1450 * as this VMA is strongly hardware related. Therefore we set the 1451 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1452 * calling us again and trying to do incorrect actions. We assume that 1453 * the original VMA size is exactly a single page, and therefore all 1454 * "splitting" operation will not happen to it. 1455 */ 1456 area->vm_ops = NULL; 1457 } 1458 1459 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1460 { 1461 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1462 1463 /* It's guaranteed that all VMAs opened on a FD are closed before the 1464 * file itself is closed, therefore no sync is needed with the regular 1465 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1466 * However need a sync with accessing the vma as part of 1467 * mlx5_ib_disassociate_ucontext. 1468 * The close operation is usually called under mm->mmap_sem except when 1469 * process is exiting. 1470 * The exiting case is handled explicitly as part of 1471 * mlx5_ib_disassociate_ucontext. 1472 */ 1473 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1474 1475 /* setting the vma context pointer to null in the mlx5_ib driver's 1476 * private data, to protect a race condition in 1477 * mlx5_ib_disassociate_ucontext(). 1478 */ 1479 mlx5_ib_vma_priv_data->vma = NULL; 1480 list_del(&mlx5_ib_vma_priv_data->list); 1481 kfree(mlx5_ib_vma_priv_data); 1482 } 1483 1484 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1485 .open = mlx5_ib_vma_open, 1486 .close = mlx5_ib_vma_close 1487 }; 1488 1489 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1490 struct mlx5_ib_ucontext *ctx) 1491 { 1492 struct mlx5_ib_vma_private_data *vma_prv; 1493 struct list_head *vma_head = &ctx->vma_private_list; 1494 1495 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1496 if (!vma_prv) 1497 return -ENOMEM; 1498 1499 vma_prv->vma = vma; 1500 vma->vm_private_data = vma_prv; 1501 vma->vm_ops = &mlx5_ib_vm_ops; 1502 1503 list_add(&vma_prv->list, vma_head); 1504 1505 return 0; 1506 } 1507 1508 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1509 { 1510 int ret; 1511 struct vm_area_struct *vma; 1512 struct mlx5_ib_vma_private_data *vma_private, *n; 1513 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1514 struct task_struct *owning_process = NULL; 1515 struct mm_struct *owning_mm = NULL; 1516 1517 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1518 if (!owning_process) 1519 return; 1520 1521 owning_mm = get_task_mm(owning_process); 1522 if (!owning_mm) { 1523 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1524 while (1) { 1525 put_task_struct(owning_process); 1526 usleep_range(1000, 2000); 1527 owning_process = get_pid_task(ibcontext->tgid, 1528 PIDTYPE_PID); 1529 if (!owning_process || 1530 owning_process->state == TASK_DEAD) { 1531 pr_info("disassociate ucontext done, task was terminated\n"); 1532 /* in case task was dead need to release the 1533 * task struct. 1534 */ 1535 if (owning_process) 1536 put_task_struct(owning_process); 1537 return; 1538 } 1539 } 1540 } 1541 1542 /* need to protect from a race on closing the vma as part of 1543 * mlx5_ib_vma_close. 1544 */ 1545 down_write(&owning_mm->mmap_sem); 1546 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1547 list) { 1548 vma = vma_private->vma; 1549 ret = zap_vma_ptes(vma, vma->vm_start, 1550 PAGE_SIZE); 1551 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1552 /* context going to be destroyed, should 1553 * not access ops any more. 1554 */ 1555 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1556 vma->vm_ops = NULL; 1557 list_del(&vma_private->list); 1558 kfree(vma_private); 1559 } 1560 up_write(&owning_mm->mmap_sem); 1561 mmput(owning_mm); 1562 put_task_struct(owning_process); 1563 } 1564 1565 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1566 { 1567 switch (cmd) { 1568 case MLX5_IB_MMAP_WC_PAGE: 1569 return "WC"; 1570 case MLX5_IB_MMAP_REGULAR_PAGE: 1571 return "best effort WC"; 1572 case MLX5_IB_MMAP_NC_PAGE: 1573 return "NC"; 1574 default: 1575 return NULL; 1576 } 1577 } 1578 1579 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1580 struct vm_area_struct *vma, 1581 struct mlx5_ib_ucontext *context) 1582 { 1583 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1584 int err; 1585 unsigned long idx; 1586 phys_addr_t pfn, pa; 1587 pgprot_t prot; 1588 int uars_per_page; 1589 1590 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1591 return -EINVAL; 1592 1593 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1594 idx = get_index(vma->vm_pgoff); 1595 if (idx % uars_per_page || 1596 idx * uars_per_page >= bfregi->num_sys_pages) { 1597 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1598 return -EINVAL; 1599 } 1600 1601 switch (cmd) { 1602 case MLX5_IB_MMAP_WC_PAGE: 1603 /* Some architectures don't support WC memory */ 1604 #if defined(CONFIG_X86) 1605 if (!pat_enabled()) 1606 return -EPERM; 1607 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1608 return -EPERM; 1609 #endif 1610 /* fall through */ 1611 case MLX5_IB_MMAP_REGULAR_PAGE: 1612 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1613 prot = pgprot_writecombine(vma->vm_page_prot); 1614 break; 1615 case MLX5_IB_MMAP_NC_PAGE: 1616 prot = pgprot_noncached(vma->vm_page_prot); 1617 break; 1618 default: 1619 return -EINVAL; 1620 } 1621 1622 pfn = uar_index2pfn(dev, bfregi, idx); 1623 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1624 1625 vma->vm_page_prot = prot; 1626 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1627 PAGE_SIZE, vma->vm_page_prot); 1628 if (err) { 1629 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1630 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1631 return -EAGAIN; 1632 } 1633 1634 pa = pfn << PAGE_SHIFT; 1635 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1636 vma->vm_start, &pa); 1637 1638 return mlx5_ib_set_vma_data(vma, context); 1639 } 1640 1641 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1642 { 1643 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1644 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1645 unsigned long command; 1646 phys_addr_t pfn; 1647 1648 command = get_command(vma->vm_pgoff); 1649 switch (command) { 1650 case MLX5_IB_MMAP_WC_PAGE: 1651 case MLX5_IB_MMAP_NC_PAGE: 1652 case MLX5_IB_MMAP_REGULAR_PAGE: 1653 return uar_mmap(dev, command, vma, context); 1654 1655 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1656 return -ENOSYS; 1657 1658 case MLX5_IB_MMAP_CORE_CLOCK: 1659 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1660 return -EINVAL; 1661 1662 if (vma->vm_flags & VM_WRITE) 1663 return -EPERM; 1664 1665 /* Don't expose to user-space information it shouldn't have */ 1666 if (PAGE_SIZE > 4096) 1667 return -EOPNOTSUPP; 1668 1669 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1670 pfn = (dev->mdev->iseg_base + 1671 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1672 PAGE_SHIFT; 1673 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1674 PAGE_SIZE, vma->vm_page_prot)) 1675 return -EAGAIN; 1676 1677 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1678 vma->vm_start, 1679 (unsigned long long)pfn << PAGE_SHIFT); 1680 break; 1681 1682 default: 1683 return -EINVAL; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1690 struct ib_ucontext *context, 1691 struct ib_udata *udata) 1692 { 1693 struct mlx5_ib_alloc_pd_resp resp; 1694 struct mlx5_ib_pd *pd; 1695 int err; 1696 1697 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1698 if (!pd) 1699 return ERR_PTR(-ENOMEM); 1700 1701 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1702 if (err) { 1703 kfree(pd); 1704 return ERR_PTR(err); 1705 } 1706 1707 if (context) { 1708 resp.pdn = pd->pdn; 1709 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1710 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1711 kfree(pd); 1712 return ERR_PTR(-EFAULT); 1713 } 1714 } 1715 1716 return &pd->ibpd; 1717 } 1718 1719 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1720 { 1721 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1722 struct mlx5_ib_pd *mpd = to_mpd(pd); 1723 1724 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1725 kfree(mpd); 1726 1727 return 0; 1728 } 1729 1730 enum { 1731 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1732 MATCH_CRITERIA_ENABLE_MISC_BIT, 1733 MATCH_CRITERIA_ENABLE_INNER_BIT 1734 }; 1735 1736 #define HEADER_IS_ZERO(match_criteria, headers) \ 1737 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1738 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1739 1740 static u8 get_match_criteria_enable(u32 *match_criteria) 1741 { 1742 u8 match_criteria_enable; 1743 1744 match_criteria_enable = 1745 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1746 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1747 match_criteria_enable |= 1748 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1749 MATCH_CRITERIA_ENABLE_MISC_BIT; 1750 match_criteria_enable |= 1751 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1752 MATCH_CRITERIA_ENABLE_INNER_BIT; 1753 1754 return match_criteria_enable; 1755 } 1756 1757 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1758 { 1759 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1760 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1761 } 1762 1763 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1764 bool inner) 1765 { 1766 if (inner) { 1767 MLX5_SET(fte_match_set_misc, 1768 misc_c, inner_ipv6_flow_label, mask); 1769 MLX5_SET(fte_match_set_misc, 1770 misc_v, inner_ipv6_flow_label, val); 1771 } else { 1772 MLX5_SET(fte_match_set_misc, 1773 misc_c, outer_ipv6_flow_label, mask); 1774 MLX5_SET(fte_match_set_misc, 1775 misc_v, outer_ipv6_flow_label, val); 1776 } 1777 } 1778 1779 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1780 { 1781 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1782 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1783 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1784 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1785 } 1786 1787 #define LAST_ETH_FIELD vlan_tag 1788 #define LAST_IB_FIELD sl 1789 #define LAST_IPV4_FIELD tos 1790 #define LAST_IPV6_FIELD traffic_class 1791 #define LAST_TCP_UDP_FIELD src_port 1792 #define LAST_TUNNEL_FIELD tunnel_id 1793 #define LAST_FLOW_TAG_FIELD tag_id 1794 #define LAST_DROP_FIELD size 1795 1796 /* Field is the last supported field */ 1797 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1798 memchr_inv((void *)&filter.field +\ 1799 sizeof(filter.field), 0,\ 1800 sizeof(filter) -\ 1801 offsetof(typeof(filter), field) -\ 1802 sizeof(filter.field)) 1803 1804 #define IPV4_VERSION 4 1805 #define IPV6_VERSION 6 1806 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1807 u32 *match_v, const union ib_flow_spec *ib_spec, 1808 u32 *tag_id, bool *is_drop) 1809 { 1810 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1811 misc_parameters); 1812 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1813 misc_parameters); 1814 void *headers_c; 1815 void *headers_v; 1816 int match_ipv; 1817 1818 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1819 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1820 inner_headers); 1821 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1822 inner_headers); 1823 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1824 ft_field_support.inner_ip_version); 1825 } else { 1826 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1827 outer_headers); 1828 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1829 outer_headers); 1830 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1831 ft_field_support.outer_ip_version); 1832 } 1833 1834 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1835 case IB_FLOW_SPEC_ETH: 1836 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1837 return -EOPNOTSUPP; 1838 1839 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1840 dmac_47_16), 1841 ib_spec->eth.mask.dst_mac); 1842 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1843 dmac_47_16), 1844 ib_spec->eth.val.dst_mac); 1845 1846 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1847 smac_47_16), 1848 ib_spec->eth.mask.src_mac); 1849 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1850 smac_47_16), 1851 ib_spec->eth.val.src_mac); 1852 1853 if (ib_spec->eth.mask.vlan_tag) { 1854 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1855 cvlan_tag, 1); 1856 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1857 cvlan_tag, 1); 1858 1859 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1860 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1861 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1862 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1863 1864 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1865 first_cfi, 1866 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1867 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1868 first_cfi, 1869 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1870 1871 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1872 first_prio, 1873 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1874 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1875 first_prio, 1876 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1877 } 1878 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1879 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1881 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1882 break; 1883 case IB_FLOW_SPEC_IPV4: 1884 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1885 return -EOPNOTSUPP; 1886 1887 if (match_ipv) { 1888 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1889 ip_version, 0xf); 1890 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1891 ip_version, IPV4_VERSION); 1892 } else { 1893 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1894 ethertype, 0xffff); 1895 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1896 ethertype, ETH_P_IP); 1897 } 1898 1899 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1900 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1901 &ib_spec->ipv4.mask.src_ip, 1902 sizeof(ib_spec->ipv4.mask.src_ip)); 1903 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1904 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1905 &ib_spec->ipv4.val.src_ip, 1906 sizeof(ib_spec->ipv4.val.src_ip)); 1907 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1908 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1909 &ib_spec->ipv4.mask.dst_ip, 1910 sizeof(ib_spec->ipv4.mask.dst_ip)); 1911 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1912 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1913 &ib_spec->ipv4.val.dst_ip, 1914 sizeof(ib_spec->ipv4.val.dst_ip)); 1915 1916 set_tos(headers_c, headers_v, 1917 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1918 1919 set_proto(headers_c, headers_v, 1920 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1921 break; 1922 case IB_FLOW_SPEC_IPV6: 1923 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1924 return -EOPNOTSUPP; 1925 1926 if (match_ipv) { 1927 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1928 ip_version, 0xf); 1929 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1930 ip_version, IPV6_VERSION); 1931 } else { 1932 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1933 ethertype, 0xffff); 1934 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1935 ethertype, ETH_P_IPV6); 1936 } 1937 1938 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1939 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1940 &ib_spec->ipv6.mask.src_ip, 1941 sizeof(ib_spec->ipv6.mask.src_ip)); 1942 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1943 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1944 &ib_spec->ipv6.val.src_ip, 1945 sizeof(ib_spec->ipv6.val.src_ip)); 1946 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1947 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1948 &ib_spec->ipv6.mask.dst_ip, 1949 sizeof(ib_spec->ipv6.mask.dst_ip)); 1950 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1951 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1952 &ib_spec->ipv6.val.dst_ip, 1953 sizeof(ib_spec->ipv6.val.dst_ip)); 1954 1955 set_tos(headers_c, headers_v, 1956 ib_spec->ipv6.mask.traffic_class, 1957 ib_spec->ipv6.val.traffic_class); 1958 1959 set_proto(headers_c, headers_v, 1960 ib_spec->ipv6.mask.next_hdr, 1961 ib_spec->ipv6.val.next_hdr); 1962 1963 set_flow_label(misc_params_c, misc_params_v, 1964 ntohl(ib_spec->ipv6.mask.flow_label), 1965 ntohl(ib_spec->ipv6.val.flow_label), 1966 ib_spec->type & IB_FLOW_SPEC_INNER); 1967 1968 break; 1969 case IB_FLOW_SPEC_TCP: 1970 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1971 LAST_TCP_UDP_FIELD)) 1972 return -EOPNOTSUPP; 1973 1974 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1975 0xff); 1976 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1977 IPPROTO_TCP); 1978 1979 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 1980 ntohs(ib_spec->tcp_udp.mask.src_port)); 1981 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 1982 ntohs(ib_spec->tcp_udp.val.src_port)); 1983 1984 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 1985 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 1987 ntohs(ib_spec->tcp_udp.val.dst_port)); 1988 break; 1989 case IB_FLOW_SPEC_UDP: 1990 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1991 LAST_TCP_UDP_FIELD)) 1992 return -EOPNOTSUPP; 1993 1994 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1995 0xff); 1996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1997 IPPROTO_UDP); 1998 1999 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2000 ntohs(ib_spec->tcp_udp.mask.src_port)); 2001 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2002 ntohs(ib_spec->tcp_udp.val.src_port)); 2003 2004 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2005 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2006 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2007 ntohs(ib_spec->tcp_udp.val.dst_port)); 2008 break; 2009 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2010 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2011 LAST_TUNNEL_FIELD)) 2012 return -EOPNOTSUPP; 2013 2014 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2015 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2016 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2017 ntohl(ib_spec->tunnel.val.tunnel_id)); 2018 break; 2019 case IB_FLOW_SPEC_ACTION_TAG: 2020 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2021 LAST_FLOW_TAG_FIELD)) 2022 return -EOPNOTSUPP; 2023 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2024 return -EINVAL; 2025 2026 *tag_id = ib_spec->flow_tag.tag_id; 2027 break; 2028 case IB_FLOW_SPEC_ACTION_DROP: 2029 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2030 LAST_DROP_FIELD)) 2031 return -EOPNOTSUPP; 2032 *is_drop = true; 2033 break; 2034 default: 2035 return -EINVAL; 2036 } 2037 2038 return 0; 2039 } 2040 2041 /* If a flow could catch both multicast and unicast packets, 2042 * it won't fall into the multicast flow steering table and this rule 2043 * could steal other multicast packets. 2044 */ 2045 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 2046 { 2047 struct ib_flow_spec_eth *eth_spec; 2048 2049 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2050 ib_attr->size < sizeof(struct ib_flow_attr) + 2051 sizeof(struct ib_flow_spec_eth) || 2052 ib_attr->num_of_specs < 1) 2053 return false; 2054 2055 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 2056 if (eth_spec->type != IB_FLOW_SPEC_ETH || 2057 eth_spec->size != sizeof(*eth_spec)) 2058 return false; 2059 2060 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2061 is_multicast_ether_addr(eth_spec->val.dst_mac); 2062 } 2063 2064 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2065 const struct ib_flow_attr *flow_attr, 2066 bool check_inner) 2067 { 2068 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2069 int match_ipv = check_inner ? 2070 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2071 ft_field_support.inner_ip_version) : 2072 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2073 ft_field_support.outer_ip_version); 2074 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2075 bool ipv4_spec_valid, ipv6_spec_valid; 2076 unsigned int ip_spec_type = 0; 2077 bool has_ethertype = false; 2078 unsigned int spec_index; 2079 bool mask_valid = true; 2080 u16 eth_type = 0; 2081 bool type_valid; 2082 2083 /* Validate that ethertype is correct */ 2084 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2085 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2086 ib_spec->eth.mask.ether_type) { 2087 mask_valid = (ib_spec->eth.mask.ether_type == 2088 htons(0xffff)); 2089 has_ethertype = true; 2090 eth_type = ntohs(ib_spec->eth.val.ether_type); 2091 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2092 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2093 ip_spec_type = ib_spec->type; 2094 } 2095 ib_spec = (void *)ib_spec + ib_spec->size; 2096 } 2097 2098 type_valid = (!has_ethertype) || (!ip_spec_type); 2099 if (!type_valid && mask_valid) { 2100 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2101 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2102 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2103 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2104 2105 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2106 (((eth_type == ETH_P_MPLS_UC) || 2107 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2108 } 2109 2110 return type_valid; 2111 } 2112 2113 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2114 const struct ib_flow_attr *flow_attr) 2115 { 2116 return is_valid_ethertype(mdev, flow_attr, false) && 2117 is_valid_ethertype(mdev, flow_attr, true); 2118 } 2119 2120 static void put_flow_table(struct mlx5_ib_dev *dev, 2121 struct mlx5_ib_flow_prio *prio, bool ft_added) 2122 { 2123 prio->refcount -= !!ft_added; 2124 if (!prio->refcount) { 2125 mlx5_destroy_flow_table(prio->flow_table); 2126 prio->flow_table = NULL; 2127 } 2128 } 2129 2130 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2131 { 2132 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2133 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2134 struct mlx5_ib_flow_handler, 2135 ibflow); 2136 struct mlx5_ib_flow_handler *iter, *tmp; 2137 2138 mutex_lock(&dev->flow_db.lock); 2139 2140 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2141 mlx5_del_flow_rules(iter->rule); 2142 put_flow_table(dev, iter->prio, true); 2143 list_del(&iter->list); 2144 kfree(iter); 2145 } 2146 2147 mlx5_del_flow_rules(handler->rule); 2148 put_flow_table(dev, handler->prio, true); 2149 mutex_unlock(&dev->flow_db.lock); 2150 2151 kfree(handler); 2152 2153 return 0; 2154 } 2155 2156 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2157 { 2158 priority *= 2; 2159 if (!dont_trap) 2160 priority++; 2161 return priority; 2162 } 2163 2164 enum flow_table_type { 2165 MLX5_IB_FT_RX, 2166 MLX5_IB_FT_TX 2167 }; 2168 2169 #define MLX5_FS_MAX_TYPES 6 2170 #define MLX5_FS_MAX_ENTRIES BIT(16) 2171 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2172 struct ib_flow_attr *flow_attr, 2173 enum flow_table_type ft_type) 2174 { 2175 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2176 struct mlx5_flow_namespace *ns = NULL; 2177 struct mlx5_ib_flow_prio *prio; 2178 struct mlx5_flow_table *ft; 2179 int max_table_size; 2180 int num_entries; 2181 int num_groups; 2182 int priority; 2183 int err = 0; 2184 2185 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2186 log_max_ft_size)); 2187 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2188 if (flow_is_multicast_only(flow_attr) && 2189 !dont_trap) 2190 priority = MLX5_IB_FLOW_MCAST_PRIO; 2191 else 2192 priority = ib_prio_to_core_prio(flow_attr->priority, 2193 dont_trap); 2194 ns = mlx5_get_flow_namespace(dev->mdev, 2195 MLX5_FLOW_NAMESPACE_BYPASS); 2196 num_entries = MLX5_FS_MAX_ENTRIES; 2197 num_groups = MLX5_FS_MAX_TYPES; 2198 prio = &dev->flow_db.prios[priority]; 2199 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2200 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2201 ns = mlx5_get_flow_namespace(dev->mdev, 2202 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2203 build_leftovers_ft_param(&priority, 2204 &num_entries, 2205 &num_groups); 2206 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2207 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2208 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2209 allow_sniffer_and_nic_rx_shared_tir)) 2210 return ERR_PTR(-ENOTSUPP); 2211 2212 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2213 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2214 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2215 2216 prio = &dev->flow_db.sniffer[ft_type]; 2217 priority = 0; 2218 num_entries = 1; 2219 num_groups = 1; 2220 } 2221 2222 if (!ns) 2223 return ERR_PTR(-ENOTSUPP); 2224 2225 if (num_entries > max_table_size) 2226 return ERR_PTR(-ENOMEM); 2227 2228 ft = prio->flow_table; 2229 if (!ft) { 2230 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2231 num_entries, 2232 num_groups, 2233 0, 0); 2234 2235 if (!IS_ERR(ft)) { 2236 prio->refcount = 0; 2237 prio->flow_table = ft; 2238 } else { 2239 err = PTR_ERR(ft); 2240 } 2241 } 2242 2243 return err ? ERR_PTR(err) : prio; 2244 } 2245 2246 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2247 struct mlx5_ib_flow_prio *ft_prio, 2248 const struct ib_flow_attr *flow_attr, 2249 struct mlx5_flow_destination *dst) 2250 { 2251 struct mlx5_flow_table *ft = ft_prio->flow_table; 2252 struct mlx5_ib_flow_handler *handler; 2253 struct mlx5_flow_act flow_act = {0}; 2254 struct mlx5_flow_spec *spec; 2255 struct mlx5_flow_destination *rule_dst = dst; 2256 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2257 unsigned int spec_index; 2258 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2259 bool is_drop = false; 2260 int err = 0; 2261 int dest_num = 1; 2262 2263 if (!is_valid_attr(dev->mdev, flow_attr)) 2264 return ERR_PTR(-EINVAL); 2265 2266 spec = mlx5_vzalloc(sizeof(*spec)); 2267 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2268 if (!handler || !spec) { 2269 err = -ENOMEM; 2270 goto free; 2271 } 2272 2273 INIT_LIST_HEAD(&handler->list); 2274 2275 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2276 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2277 spec->match_value, 2278 ib_flow, &flow_tag, &is_drop); 2279 if (err < 0) 2280 goto free; 2281 2282 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2283 } 2284 2285 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2286 if (is_drop) { 2287 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2288 rule_dst = NULL; 2289 dest_num = 0; 2290 } else { 2291 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2292 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2293 } 2294 2295 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2296 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2297 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2298 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2299 flow_tag, flow_attr->type); 2300 err = -EINVAL; 2301 goto free; 2302 } 2303 flow_act.flow_tag = flow_tag; 2304 handler->rule = mlx5_add_flow_rules(ft, spec, 2305 &flow_act, 2306 rule_dst, dest_num); 2307 2308 if (IS_ERR(handler->rule)) { 2309 err = PTR_ERR(handler->rule); 2310 goto free; 2311 } 2312 2313 ft_prio->refcount++; 2314 handler->prio = ft_prio; 2315 2316 ft_prio->flow_table = ft; 2317 free: 2318 if (err) 2319 kfree(handler); 2320 kvfree(spec); 2321 return err ? ERR_PTR(err) : handler; 2322 } 2323 2324 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2325 struct mlx5_ib_flow_prio *ft_prio, 2326 struct ib_flow_attr *flow_attr, 2327 struct mlx5_flow_destination *dst) 2328 { 2329 struct mlx5_ib_flow_handler *handler_dst = NULL; 2330 struct mlx5_ib_flow_handler *handler = NULL; 2331 2332 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2333 if (!IS_ERR(handler)) { 2334 handler_dst = create_flow_rule(dev, ft_prio, 2335 flow_attr, dst); 2336 if (IS_ERR(handler_dst)) { 2337 mlx5_del_flow_rules(handler->rule); 2338 ft_prio->refcount--; 2339 kfree(handler); 2340 handler = handler_dst; 2341 } else { 2342 list_add(&handler_dst->list, &handler->list); 2343 } 2344 } 2345 2346 return handler; 2347 } 2348 enum { 2349 LEFTOVERS_MC, 2350 LEFTOVERS_UC, 2351 }; 2352 2353 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2354 struct mlx5_ib_flow_prio *ft_prio, 2355 struct ib_flow_attr *flow_attr, 2356 struct mlx5_flow_destination *dst) 2357 { 2358 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2359 struct mlx5_ib_flow_handler *handler = NULL; 2360 2361 static struct { 2362 struct ib_flow_attr flow_attr; 2363 struct ib_flow_spec_eth eth_flow; 2364 } leftovers_specs[] = { 2365 [LEFTOVERS_MC] = { 2366 .flow_attr = { 2367 .num_of_specs = 1, 2368 .size = sizeof(leftovers_specs[0]) 2369 }, 2370 .eth_flow = { 2371 .type = IB_FLOW_SPEC_ETH, 2372 .size = sizeof(struct ib_flow_spec_eth), 2373 .mask = {.dst_mac = {0x1} }, 2374 .val = {.dst_mac = {0x1} } 2375 } 2376 }, 2377 [LEFTOVERS_UC] = { 2378 .flow_attr = { 2379 .num_of_specs = 1, 2380 .size = sizeof(leftovers_specs[0]) 2381 }, 2382 .eth_flow = { 2383 .type = IB_FLOW_SPEC_ETH, 2384 .size = sizeof(struct ib_flow_spec_eth), 2385 .mask = {.dst_mac = {0x1} }, 2386 .val = {.dst_mac = {} } 2387 } 2388 } 2389 }; 2390 2391 handler = create_flow_rule(dev, ft_prio, 2392 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2393 dst); 2394 if (!IS_ERR(handler) && 2395 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2396 handler_ucast = create_flow_rule(dev, ft_prio, 2397 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2398 dst); 2399 if (IS_ERR(handler_ucast)) { 2400 mlx5_del_flow_rules(handler->rule); 2401 ft_prio->refcount--; 2402 kfree(handler); 2403 handler = handler_ucast; 2404 } else { 2405 list_add(&handler_ucast->list, &handler->list); 2406 } 2407 } 2408 2409 return handler; 2410 } 2411 2412 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2413 struct mlx5_ib_flow_prio *ft_rx, 2414 struct mlx5_ib_flow_prio *ft_tx, 2415 struct mlx5_flow_destination *dst) 2416 { 2417 struct mlx5_ib_flow_handler *handler_rx; 2418 struct mlx5_ib_flow_handler *handler_tx; 2419 int err; 2420 static const struct ib_flow_attr flow_attr = { 2421 .num_of_specs = 0, 2422 .size = sizeof(flow_attr) 2423 }; 2424 2425 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2426 if (IS_ERR(handler_rx)) { 2427 err = PTR_ERR(handler_rx); 2428 goto err; 2429 } 2430 2431 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2432 if (IS_ERR(handler_tx)) { 2433 err = PTR_ERR(handler_tx); 2434 goto err_tx; 2435 } 2436 2437 list_add(&handler_tx->list, &handler_rx->list); 2438 2439 return handler_rx; 2440 2441 err_tx: 2442 mlx5_del_flow_rules(handler_rx->rule); 2443 ft_rx->refcount--; 2444 kfree(handler_rx); 2445 err: 2446 return ERR_PTR(err); 2447 } 2448 2449 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2450 struct ib_flow_attr *flow_attr, 2451 int domain) 2452 { 2453 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2454 struct mlx5_ib_qp *mqp = to_mqp(qp); 2455 struct mlx5_ib_flow_handler *handler = NULL; 2456 struct mlx5_flow_destination *dst = NULL; 2457 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2458 struct mlx5_ib_flow_prio *ft_prio; 2459 int err; 2460 2461 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2462 return ERR_PTR(-ENOMEM); 2463 2464 if (domain != IB_FLOW_DOMAIN_USER || 2465 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2466 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2467 return ERR_PTR(-EINVAL); 2468 2469 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2470 if (!dst) 2471 return ERR_PTR(-ENOMEM); 2472 2473 mutex_lock(&dev->flow_db.lock); 2474 2475 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2476 if (IS_ERR(ft_prio)) { 2477 err = PTR_ERR(ft_prio); 2478 goto unlock; 2479 } 2480 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2481 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2482 if (IS_ERR(ft_prio_tx)) { 2483 err = PTR_ERR(ft_prio_tx); 2484 ft_prio_tx = NULL; 2485 goto destroy_ft; 2486 } 2487 } 2488 2489 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2490 if (mqp->flags & MLX5_IB_QP_RSS) 2491 dst->tir_num = mqp->rss_qp.tirn; 2492 else 2493 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2494 2495 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2496 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2497 handler = create_dont_trap_rule(dev, ft_prio, 2498 flow_attr, dst); 2499 } else { 2500 handler = create_flow_rule(dev, ft_prio, flow_attr, 2501 dst); 2502 } 2503 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2504 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2505 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2506 dst); 2507 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2508 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2509 } else { 2510 err = -EINVAL; 2511 goto destroy_ft; 2512 } 2513 2514 if (IS_ERR(handler)) { 2515 err = PTR_ERR(handler); 2516 handler = NULL; 2517 goto destroy_ft; 2518 } 2519 2520 mutex_unlock(&dev->flow_db.lock); 2521 kfree(dst); 2522 2523 return &handler->ibflow; 2524 2525 destroy_ft: 2526 put_flow_table(dev, ft_prio, false); 2527 if (ft_prio_tx) 2528 put_flow_table(dev, ft_prio_tx, false); 2529 unlock: 2530 mutex_unlock(&dev->flow_db.lock); 2531 kfree(dst); 2532 kfree(handler); 2533 return ERR_PTR(err); 2534 } 2535 2536 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2537 { 2538 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2539 int err; 2540 2541 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2542 if (err) 2543 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2544 ibqp->qp_num, gid->raw); 2545 2546 return err; 2547 } 2548 2549 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2550 { 2551 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2552 int err; 2553 2554 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2555 if (err) 2556 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2557 ibqp->qp_num, gid->raw); 2558 2559 return err; 2560 } 2561 2562 static int init_node_data(struct mlx5_ib_dev *dev) 2563 { 2564 int err; 2565 2566 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2567 if (err) 2568 return err; 2569 2570 dev->mdev->rev_id = dev->mdev->pdev->revision; 2571 2572 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2573 } 2574 2575 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2576 char *buf) 2577 { 2578 struct mlx5_ib_dev *dev = 2579 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2580 2581 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2582 } 2583 2584 static ssize_t show_reg_pages(struct device *device, 2585 struct device_attribute *attr, char *buf) 2586 { 2587 struct mlx5_ib_dev *dev = 2588 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2589 2590 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2591 } 2592 2593 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2594 char *buf) 2595 { 2596 struct mlx5_ib_dev *dev = 2597 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2598 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2599 } 2600 2601 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2602 char *buf) 2603 { 2604 struct mlx5_ib_dev *dev = 2605 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2606 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2607 } 2608 2609 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2610 char *buf) 2611 { 2612 struct mlx5_ib_dev *dev = 2613 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2614 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2615 dev->mdev->board_id); 2616 } 2617 2618 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2619 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2620 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2621 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2622 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2623 2624 static struct device_attribute *mlx5_class_attributes[] = { 2625 &dev_attr_hw_rev, 2626 &dev_attr_hca_type, 2627 &dev_attr_board_id, 2628 &dev_attr_fw_pages, 2629 &dev_attr_reg_pages, 2630 }; 2631 2632 static void pkey_change_handler(struct work_struct *work) 2633 { 2634 struct mlx5_ib_port_resources *ports = 2635 container_of(work, struct mlx5_ib_port_resources, 2636 pkey_change_work); 2637 2638 mutex_lock(&ports->devr->mutex); 2639 mlx5_ib_gsi_pkey_change(ports->gsi); 2640 mutex_unlock(&ports->devr->mutex); 2641 } 2642 2643 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2644 { 2645 struct mlx5_ib_qp *mqp; 2646 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2647 struct mlx5_core_cq *mcq; 2648 struct list_head cq_armed_list; 2649 unsigned long flags_qp; 2650 unsigned long flags_cq; 2651 unsigned long flags; 2652 2653 INIT_LIST_HEAD(&cq_armed_list); 2654 2655 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2656 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2657 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2658 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2659 if (mqp->sq.tail != mqp->sq.head) { 2660 send_mcq = to_mcq(mqp->ibqp.send_cq); 2661 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2662 if (send_mcq->mcq.comp && 2663 mqp->ibqp.send_cq->comp_handler) { 2664 if (!send_mcq->mcq.reset_notify_added) { 2665 send_mcq->mcq.reset_notify_added = 1; 2666 list_add_tail(&send_mcq->mcq.reset_notify, 2667 &cq_armed_list); 2668 } 2669 } 2670 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2671 } 2672 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2673 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2674 /* no handling is needed for SRQ */ 2675 if (!mqp->ibqp.srq) { 2676 if (mqp->rq.tail != mqp->rq.head) { 2677 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2678 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2679 if (recv_mcq->mcq.comp && 2680 mqp->ibqp.recv_cq->comp_handler) { 2681 if (!recv_mcq->mcq.reset_notify_added) { 2682 recv_mcq->mcq.reset_notify_added = 1; 2683 list_add_tail(&recv_mcq->mcq.reset_notify, 2684 &cq_armed_list); 2685 } 2686 } 2687 spin_unlock_irqrestore(&recv_mcq->lock, 2688 flags_cq); 2689 } 2690 } 2691 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2692 } 2693 /*At that point all inflight post send were put to be executed as of we 2694 * lock/unlock above locks Now need to arm all involved CQs. 2695 */ 2696 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2697 mcq->comp(mcq); 2698 } 2699 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2700 } 2701 2702 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2703 enum mlx5_dev_event event, unsigned long param) 2704 { 2705 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2706 struct ib_event ibev; 2707 bool fatal = false; 2708 u8 port = 0; 2709 2710 switch (event) { 2711 case MLX5_DEV_EVENT_SYS_ERROR: 2712 ibev.event = IB_EVENT_DEVICE_FATAL; 2713 mlx5_ib_handle_internal_error(ibdev); 2714 fatal = true; 2715 break; 2716 2717 case MLX5_DEV_EVENT_PORT_UP: 2718 case MLX5_DEV_EVENT_PORT_DOWN: 2719 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2720 port = (u8)param; 2721 2722 /* In RoCE, port up/down events are handled in 2723 * mlx5_netdev_event(). 2724 */ 2725 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2726 IB_LINK_LAYER_ETHERNET) 2727 return; 2728 2729 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2730 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2731 break; 2732 2733 case MLX5_DEV_EVENT_LID_CHANGE: 2734 ibev.event = IB_EVENT_LID_CHANGE; 2735 port = (u8)param; 2736 break; 2737 2738 case MLX5_DEV_EVENT_PKEY_CHANGE: 2739 ibev.event = IB_EVENT_PKEY_CHANGE; 2740 port = (u8)param; 2741 2742 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2743 break; 2744 2745 case MLX5_DEV_EVENT_GUID_CHANGE: 2746 ibev.event = IB_EVENT_GID_CHANGE; 2747 port = (u8)param; 2748 break; 2749 2750 case MLX5_DEV_EVENT_CLIENT_REREG: 2751 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2752 port = (u8)param; 2753 break; 2754 default: 2755 return; 2756 } 2757 2758 ibev.device = &ibdev->ib_dev; 2759 ibev.element.port_num = port; 2760 2761 if (port < 1 || port > ibdev->num_ports) { 2762 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2763 return; 2764 } 2765 2766 if (ibdev->ib_active) 2767 ib_dispatch_event(&ibev); 2768 2769 if (fatal) 2770 ibdev->ib_active = false; 2771 } 2772 2773 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2774 { 2775 struct mlx5_hca_vport_context vport_ctx; 2776 int err; 2777 int port; 2778 2779 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2780 dev->mdev->port_caps[port - 1].has_smi = false; 2781 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2782 MLX5_CAP_PORT_TYPE_IB) { 2783 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2784 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2785 port, 0, 2786 &vport_ctx); 2787 if (err) { 2788 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2789 port, err); 2790 return err; 2791 } 2792 dev->mdev->port_caps[port - 1].has_smi = 2793 vport_ctx.has_smi; 2794 } else { 2795 dev->mdev->port_caps[port - 1].has_smi = true; 2796 } 2797 } 2798 } 2799 return 0; 2800 } 2801 2802 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2803 { 2804 int port; 2805 2806 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2807 mlx5_query_ext_port_caps(dev, port); 2808 } 2809 2810 static int get_port_caps(struct mlx5_ib_dev *dev) 2811 { 2812 struct ib_device_attr *dprops = NULL; 2813 struct ib_port_attr *pprops = NULL; 2814 int err = -ENOMEM; 2815 int port; 2816 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2817 2818 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2819 if (!pprops) 2820 goto out; 2821 2822 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2823 if (!dprops) 2824 goto out; 2825 2826 err = set_has_smi_cap(dev); 2827 if (err) 2828 goto out; 2829 2830 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2831 if (err) { 2832 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2833 goto out; 2834 } 2835 2836 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2837 memset(pprops, 0, sizeof(*pprops)); 2838 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2839 if (err) { 2840 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2841 port, err); 2842 break; 2843 } 2844 dev->mdev->port_caps[port - 1].pkey_table_len = 2845 dprops->max_pkeys; 2846 dev->mdev->port_caps[port - 1].gid_table_len = 2847 pprops->gid_tbl_len; 2848 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2849 dprops->max_pkeys, pprops->gid_tbl_len); 2850 } 2851 2852 out: 2853 kfree(pprops); 2854 kfree(dprops); 2855 2856 return err; 2857 } 2858 2859 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2860 { 2861 int err; 2862 2863 err = mlx5_mr_cache_cleanup(dev); 2864 if (err) 2865 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2866 2867 mlx5_ib_destroy_qp(dev->umrc.qp); 2868 ib_free_cq(dev->umrc.cq); 2869 ib_dealloc_pd(dev->umrc.pd); 2870 } 2871 2872 enum { 2873 MAX_UMR_WR = 128, 2874 }; 2875 2876 static int create_umr_res(struct mlx5_ib_dev *dev) 2877 { 2878 struct ib_qp_init_attr *init_attr = NULL; 2879 struct ib_qp_attr *attr = NULL; 2880 struct ib_pd *pd; 2881 struct ib_cq *cq; 2882 struct ib_qp *qp; 2883 int ret; 2884 2885 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2886 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2887 if (!attr || !init_attr) { 2888 ret = -ENOMEM; 2889 goto error_0; 2890 } 2891 2892 pd = ib_alloc_pd(&dev->ib_dev, 0); 2893 if (IS_ERR(pd)) { 2894 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2895 ret = PTR_ERR(pd); 2896 goto error_0; 2897 } 2898 2899 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2900 if (IS_ERR(cq)) { 2901 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2902 ret = PTR_ERR(cq); 2903 goto error_2; 2904 } 2905 2906 init_attr->send_cq = cq; 2907 init_attr->recv_cq = cq; 2908 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2909 init_attr->cap.max_send_wr = MAX_UMR_WR; 2910 init_attr->cap.max_send_sge = 1; 2911 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2912 init_attr->port_num = 1; 2913 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2914 if (IS_ERR(qp)) { 2915 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2916 ret = PTR_ERR(qp); 2917 goto error_3; 2918 } 2919 qp->device = &dev->ib_dev; 2920 qp->real_qp = qp; 2921 qp->uobject = NULL; 2922 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2923 2924 attr->qp_state = IB_QPS_INIT; 2925 attr->port_num = 1; 2926 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2927 IB_QP_PORT, NULL); 2928 if (ret) { 2929 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2930 goto error_4; 2931 } 2932 2933 memset(attr, 0, sizeof(*attr)); 2934 attr->qp_state = IB_QPS_RTR; 2935 attr->path_mtu = IB_MTU_256; 2936 2937 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2938 if (ret) { 2939 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2940 goto error_4; 2941 } 2942 2943 memset(attr, 0, sizeof(*attr)); 2944 attr->qp_state = IB_QPS_RTS; 2945 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2946 if (ret) { 2947 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2948 goto error_4; 2949 } 2950 2951 dev->umrc.qp = qp; 2952 dev->umrc.cq = cq; 2953 dev->umrc.pd = pd; 2954 2955 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2956 ret = mlx5_mr_cache_init(dev); 2957 if (ret) { 2958 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2959 goto error_4; 2960 } 2961 2962 kfree(attr); 2963 kfree(init_attr); 2964 2965 return 0; 2966 2967 error_4: 2968 mlx5_ib_destroy_qp(qp); 2969 2970 error_3: 2971 ib_free_cq(cq); 2972 2973 error_2: 2974 ib_dealloc_pd(pd); 2975 2976 error_0: 2977 kfree(attr); 2978 kfree(init_attr); 2979 return ret; 2980 } 2981 2982 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2983 { 2984 switch (umr_fence_cap) { 2985 case MLX5_CAP_UMR_FENCE_NONE: 2986 return MLX5_FENCE_MODE_NONE; 2987 case MLX5_CAP_UMR_FENCE_SMALL: 2988 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2989 default: 2990 return MLX5_FENCE_MODE_STRONG_ORDERING; 2991 } 2992 } 2993 2994 static int create_dev_resources(struct mlx5_ib_resources *devr) 2995 { 2996 struct ib_srq_init_attr attr; 2997 struct mlx5_ib_dev *dev; 2998 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2999 int port; 3000 int ret = 0; 3001 3002 dev = container_of(devr, struct mlx5_ib_dev, devr); 3003 3004 mutex_init(&devr->mutex); 3005 3006 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3007 if (IS_ERR(devr->p0)) { 3008 ret = PTR_ERR(devr->p0); 3009 goto error0; 3010 } 3011 devr->p0->device = &dev->ib_dev; 3012 devr->p0->uobject = NULL; 3013 atomic_set(&devr->p0->usecnt, 0); 3014 3015 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3016 if (IS_ERR(devr->c0)) { 3017 ret = PTR_ERR(devr->c0); 3018 goto error1; 3019 } 3020 devr->c0->device = &dev->ib_dev; 3021 devr->c0->uobject = NULL; 3022 devr->c0->comp_handler = NULL; 3023 devr->c0->event_handler = NULL; 3024 devr->c0->cq_context = NULL; 3025 atomic_set(&devr->c0->usecnt, 0); 3026 3027 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3028 if (IS_ERR(devr->x0)) { 3029 ret = PTR_ERR(devr->x0); 3030 goto error2; 3031 } 3032 devr->x0->device = &dev->ib_dev; 3033 devr->x0->inode = NULL; 3034 atomic_set(&devr->x0->usecnt, 0); 3035 mutex_init(&devr->x0->tgt_qp_mutex); 3036 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3037 3038 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3039 if (IS_ERR(devr->x1)) { 3040 ret = PTR_ERR(devr->x1); 3041 goto error3; 3042 } 3043 devr->x1->device = &dev->ib_dev; 3044 devr->x1->inode = NULL; 3045 atomic_set(&devr->x1->usecnt, 0); 3046 mutex_init(&devr->x1->tgt_qp_mutex); 3047 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3048 3049 memset(&attr, 0, sizeof(attr)); 3050 attr.attr.max_sge = 1; 3051 attr.attr.max_wr = 1; 3052 attr.srq_type = IB_SRQT_XRC; 3053 attr.ext.xrc.cq = devr->c0; 3054 attr.ext.xrc.xrcd = devr->x0; 3055 3056 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3057 if (IS_ERR(devr->s0)) { 3058 ret = PTR_ERR(devr->s0); 3059 goto error4; 3060 } 3061 devr->s0->device = &dev->ib_dev; 3062 devr->s0->pd = devr->p0; 3063 devr->s0->uobject = NULL; 3064 devr->s0->event_handler = NULL; 3065 devr->s0->srq_context = NULL; 3066 devr->s0->srq_type = IB_SRQT_XRC; 3067 devr->s0->ext.xrc.xrcd = devr->x0; 3068 devr->s0->ext.xrc.cq = devr->c0; 3069 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3070 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 3071 atomic_inc(&devr->p0->usecnt); 3072 atomic_set(&devr->s0->usecnt, 0); 3073 3074 memset(&attr, 0, sizeof(attr)); 3075 attr.attr.max_sge = 1; 3076 attr.attr.max_wr = 1; 3077 attr.srq_type = IB_SRQT_BASIC; 3078 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3079 if (IS_ERR(devr->s1)) { 3080 ret = PTR_ERR(devr->s1); 3081 goto error5; 3082 } 3083 devr->s1->device = &dev->ib_dev; 3084 devr->s1->pd = devr->p0; 3085 devr->s1->uobject = NULL; 3086 devr->s1->event_handler = NULL; 3087 devr->s1->srq_context = NULL; 3088 devr->s1->srq_type = IB_SRQT_BASIC; 3089 devr->s1->ext.xrc.cq = devr->c0; 3090 atomic_inc(&devr->p0->usecnt); 3091 atomic_set(&devr->s0->usecnt, 0); 3092 3093 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3094 INIT_WORK(&devr->ports[port].pkey_change_work, 3095 pkey_change_handler); 3096 devr->ports[port].devr = devr; 3097 } 3098 3099 return 0; 3100 3101 error5: 3102 mlx5_ib_destroy_srq(devr->s0); 3103 error4: 3104 mlx5_ib_dealloc_xrcd(devr->x1); 3105 error3: 3106 mlx5_ib_dealloc_xrcd(devr->x0); 3107 error2: 3108 mlx5_ib_destroy_cq(devr->c0); 3109 error1: 3110 mlx5_ib_dealloc_pd(devr->p0); 3111 error0: 3112 return ret; 3113 } 3114 3115 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3116 { 3117 struct mlx5_ib_dev *dev = 3118 container_of(devr, struct mlx5_ib_dev, devr); 3119 int port; 3120 3121 mlx5_ib_destroy_srq(devr->s1); 3122 mlx5_ib_destroy_srq(devr->s0); 3123 mlx5_ib_dealloc_xrcd(devr->x0); 3124 mlx5_ib_dealloc_xrcd(devr->x1); 3125 mlx5_ib_destroy_cq(devr->c0); 3126 mlx5_ib_dealloc_pd(devr->p0); 3127 3128 /* Make sure no change P_Key work items are still executing */ 3129 for (port = 0; port < dev->num_ports; ++port) 3130 cancel_work_sync(&devr->ports[port].pkey_change_work); 3131 } 3132 3133 static u32 get_core_cap_flags(struct ib_device *ibdev) 3134 { 3135 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3136 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3137 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3138 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3139 u32 ret = 0; 3140 3141 if (ll == IB_LINK_LAYER_INFINIBAND) 3142 return RDMA_CORE_PORT_IBA_IB; 3143 3144 ret = RDMA_CORE_PORT_RAW_PACKET; 3145 3146 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3147 return ret; 3148 3149 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3150 return ret; 3151 3152 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3153 ret |= RDMA_CORE_PORT_IBA_ROCE; 3154 3155 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3156 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3157 3158 return ret; 3159 } 3160 3161 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3162 struct ib_port_immutable *immutable) 3163 { 3164 struct ib_port_attr attr; 3165 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3166 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3167 int err; 3168 3169 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3170 3171 err = ib_query_port(ibdev, port_num, &attr); 3172 if (err) 3173 return err; 3174 3175 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3176 immutable->gid_tbl_len = attr.gid_tbl_len; 3177 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3178 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3179 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3180 3181 return 0; 3182 } 3183 3184 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3185 size_t str_len) 3186 { 3187 struct mlx5_ib_dev *dev = 3188 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3189 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3190 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3191 } 3192 3193 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3194 { 3195 struct mlx5_core_dev *mdev = dev->mdev; 3196 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3197 MLX5_FLOW_NAMESPACE_LAG); 3198 struct mlx5_flow_table *ft; 3199 int err; 3200 3201 if (!ns || !mlx5_lag_is_active(mdev)) 3202 return 0; 3203 3204 err = mlx5_cmd_create_vport_lag(mdev); 3205 if (err) 3206 return err; 3207 3208 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3209 if (IS_ERR(ft)) { 3210 err = PTR_ERR(ft); 3211 goto err_destroy_vport_lag; 3212 } 3213 3214 dev->flow_db.lag_demux_ft = ft; 3215 return 0; 3216 3217 err_destroy_vport_lag: 3218 mlx5_cmd_destroy_vport_lag(mdev); 3219 return err; 3220 } 3221 3222 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3223 { 3224 struct mlx5_core_dev *mdev = dev->mdev; 3225 3226 if (dev->flow_db.lag_demux_ft) { 3227 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3228 dev->flow_db.lag_demux_ft = NULL; 3229 3230 mlx5_cmd_destroy_vport_lag(mdev); 3231 } 3232 } 3233 3234 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3235 { 3236 int err; 3237 3238 dev->roce.nb.notifier_call = mlx5_netdev_event; 3239 err = register_netdevice_notifier(&dev->roce.nb); 3240 if (err) { 3241 dev->roce.nb.notifier_call = NULL; 3242 return err; 3243 } 3244 3245 return 0; 3246 } 3247 3248 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3249 { 3250 if (dev->roce.nb.notifier_call) { 3251 unregister_netdevice_notifier(&dev->roce.nb); 3252 dev->roce.nb.notifier_call = NULL; 3253 } 3254 } 3255 3256 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3257 { 3258 int err; 3259 3260 err = mlx5_add_netdev_notifier(dev); 3261 if (err) 3262 return err; 3263 3264 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3265 err = mlx5_nic_vport_enable_roce(dev->mdev); 3266 if (err) 3267 goto err_unregister_netdevice_notifier; 3268 } 3269 3270 err = mlx5_eth_lag_init(dev); 3271 if (err) 3272 goto err_disable_roce; 3273 3274 return 0; 3275 3276 err_disable_roce: 3277 if (MLX5_CAP_GEN(dev->mdev, roce)) 3278 mlx5_nic_vport_disable_roce(dev->mdev); 3279 3280 err_unregister_netdevice_notifier: 3281 mlx5_remove_netdev_notifier(dev); 3282 return err; 3283 } 3284 3285 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3286 { 3287 mlx5_eth_lag_cleanup(dev); 3288 if (MLX5_CAP_GEN(dev->mdev, roce)) 3289 mlx5_nic_vport_disable_roce(dev->mdev); 3290 } 3291 3292 struct mlx5_ib_counter { 3293 const char *name; 3294 size_t offset; 3295 }; 3296 3297 #define INIT_Q_COUNTER(_name) \ 3298 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3299 3300 static const struct mlx5_ib_counter basic_q_cnts[] = { 3301 INIT_Q_COUNTER(rx_write_requests), 3302 INIT_Q_COUNTER(rx_read_requests), 3303 INIT_Q_COUNTER(rx_atomic_requests), 3304 INIT_Q_COUNTER(out_of_buffer), 3305 }; 3306 3307 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3308 INIT_Q_COUNTER(out_of_sequence), 3309 }; 3310 3311 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3312 INIT_Q_COUNTER(duplicate_request), 3313 INIT_Q_COUNTER(rnr_nak_retry_err), 3314 INIT_Q_COUNTER(packet_seq_err), 3315 INIT_Q_COUNTER(implied_nak_seq_err), 3316 INIT_Q_COUNTER(local_ack_timeout_err), 3317 }; 3318 3319 #define INIT_CONG_COUNTER(_name) \ 3320 { .name = #_name, .offset = \ 3321 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3322 3323 static const struct mlx5_ib_counter cong_cnts[] = { 3324 INIT_CONG_COUNTER(rp_cnp_ignored), 3325 INIT_CONG_COUNTER(rp_cnp_handled), 3326 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3327 INIT_CONG_COUNTER(np_cnp_sent), 3328 }; 3329 3330 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3331 { 3332 unsigned int i; 3333 3334 for (i = 0; i < dev->num_ports; i++) { 3335 mlx5_core_dealloc_q_counter(dev->mdev, 3336 dev->port[i].cnts.set_id); 3337 kfree(dev->port[i].cnts.names); 3338 kfree(dev->port[i].cnts.offsets); 3339 } 3340 } 3341 3342 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3343 struct mlx5_ib_counters *cnts) 3344 { 3345 u32 num_counters; 3346 3347 num_counters = ARRAY_SIZE(basic_q_cnts); 3348 3349 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3350 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3351 3352 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3353 num_counters += ARRAY_SIZE(retrans_q_cnts); 3354 cnts->num_q_counters = num_counters; 3355 3356 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3357 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3358 num_counters += ARRAY_SIZE(cong_cnts); 3359 } 3360 3361 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3362 if (!cnts->names) 3363 return -ENOMEM; 3364 3365 cnts->offsets = kcalloc(num_counters, 3366 sizeof(cnts->offsets), GFP_KERNEL); 3367 if (!cnts->offsets) 3368 goto err_names; 3369 3370 return 0; 3371 3372 err_names: 3373 kfree(cnts->names); 3374 return -ENOMEM; 3375 } 3376 3377 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3378 const char **names, 3379 size_t *offsets) 3380 { 3381 int i; 3382 int j = 0; 3383 3384 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3385 names[j] = basic_q_cnts[i].name; 3386 offsets[j] = basic_q_cnts[i].offset; 3387 } 3388 3389 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3390 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3391 names[j] = out_of_seq_q_cnts[i].name; 3392 offsets[j] = out_of_seq_q_cnts[i].offset; 3393 } 3394 } 3395 3396 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3397 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3398 names[j] = retrans_q_cnts[i].name; 3399 offsets[j] = retrans_q_cnts[i].offset; 3400 } 3401 } 3402 3403 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3404 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3405 names[j] = cong_cnts[i].name; 3406 offsets[j] = cong_cnts[i].offset; 3407 } 3408 } 3409 } 3410 3411 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3412 { 3413 int i; 3414 int ret; 3415 3416 for (i = 0; i < dev->num_ports; i++) { 3417 struct mlx5_ib_port *port = &dev->port[i]; 3418 3419 ret = mlx5_core_alloc_q_counter(dev->mdev, 3420 &port->cnts.set_id); 3421 if (ret) { 3422 mlx5_ib_warn(dev, 3423 "couldn't allocate queue counter for port %d, err %d\n", 3424 i + 1, ret); 3425 goto dealloc_counters; 3426 } 3427 3428 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3429 if (ret) 3430 goto dealloc_counters; 3431 3432 mlx5_ib_fill_counters(dev, port->cnts.names, 3433 port->cnts.offsets); 3434 } 3435 3436 return 0; 3437 3438 dealloc_counters: 3439 while (--i >= 0) 3440 mlx5_core_dealloc_q_counter(dev->mdev, 3441 dev->port[i].cnts.set_id); 3442 3443 return ret; 3444 } 3445 3446 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3447 u8 port_num) 3448 { 3449 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3450 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3451 3452 /* We support only per port stats */ 3453 if (port_num == 0) 3454 return NULL; 3455 3456 return rdma_alloc_hw_stats_struct(port->cnts.names, 3457 port->cnts.num_q_counters + 3458 port->cnts.num_cong_counters, 3459 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3460 } 3461 3462 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3463 struct mlx5_ib_port *port, 3464 struct rdma_hw_stats *stats) 3465 { 3466 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3467 void *out; 3468 __be32 val; 3469 int ret, i; 3470 3471 out = mlx5_vzalloc(outlen); 3472 if (!out) 3473 return -ENOMEM; 3474 3475 ret = mlx5_core_query_q_counter(dev->mdev, 3476 port->cnts.set_id, 0, 3477 out, outlen); 3478 if (ret) 3479 goto free; 3480 3481 for (i = 0; i < port->cnts.num_q_counters; i++) { 3482 val = *(__be32 *)(out + port->cnts.offsets[i]); 3483 stats->value[i] = (u64)be32_to_cpu(val); 3484 } 3485 3486 free: 3487 kvfree(out); 3488 return ret; 3489 } 3490 3491 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3492 struct mlx5_ib_port *port, 3493 struct rdma_hw_stats *stats) 3494 { 3495 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3496 void *out; 3497 int ret, i; 3498 int offset = port->cnts.num_q_counters; 3499 3500 out = mlx5_vzalloc(outlen); 3501 if (!out) 3502 return -ENOMEM; 3503 3504 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3505 if (ret) 3506 goto free; 3507 3508 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3509 stats->value[i + offset] = 3510 be64_to_cpup((__be64 *)(out + 3511 port->cnts.offsets[i + offset])); 3512 } 3513 3514 free: 3515 kvfree(out); 3516 return ret; 3517 } 3518 3519 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3520 struct rdma_hw_stats *stats, 3521 u8 port_num, int index) 3522 { 3523 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3524 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3525 int ret, num_counters; 3526 3527 if (!stats) 3528 return -EINVAL; 3529 3530 ret = mlx5_ib_query_q_counters(dev, port, stats); 3531 if (ret) 3532 return ret; 3533 num_counters = port->cnts.num_q_counters; 3534 3535 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3536 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3537 if (ret) 3538 return ret; 3539 num_counters += port->cnts.num_cong_counters; 3540 } 3541 3542 return num_counters; 3543 } 3544 3545 static struct net_device* 3546 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3547 u8 port_num, 3548 enum rdma_netdev_t type, 3549 const char *name, 3550 unsigned char name_assign_type, 3551 void (*setup)(struct net_device *)) 3552 { 3553 if (type != RDMA_NETDEV_IPOIB) 3554 return ERR_PTR(-EOPNOTSUPP); 3555 3556 return mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3557 name, setup); 3558 } 3559 3560 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3561 { 3562 return mlx5_rdma_netdev_free(netdev); 3563 } 3564 3565 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3566 { 3567 struct mlx5_ib_dev *dev; 3568 enum rdma_link_layer ll; 3569 int port_type_cap; 3570 const char *name; 3571 int err; 3572 int i; 3573 3574 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3575 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3576 3577 printk_once(KERN_INFO "%s", mlx5_version); 3578 3579 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3580 if (!dev) 3581 return NULL; 3582 3583 dev->mdev = mdev; 3584 3585 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3586 GFP_KERNEL); 3587 if (!dev->port) 3588 goto err_dealloc; 3589 3590 rwlock_init(&dev->roce.netdev_lock); 3591 err = get_port_caps(dev); 3592 if (err) 3593 goto err_free_port; 3594 3595 if (mlx5_use_mad_ifc(dev)) 3596 get_ext_port_caps(dev); 3597 3598 if (!mlx5_lag_is_active(mdev)) 3599 name = "mlx5_%d"; 3600 else 3601 name = "mlx5_bond_%d"; 3602 3603 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3604 dev->ib_dev.owner = THIS_MODULE; 3605 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3606 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3607 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3608 dev->ib_dev.phys_port_cnt = dev->num_ports; 3609 dev->ib_dev.num_comp_vectors = 3610 dev->mdev->priv.eq_table.num_comp_vectors; 3611 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3612 3613 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3614 dev->ib_dev.uverbs_cmd_mask = 3615 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3616 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3617 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3618 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3619 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3620 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3621 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3622 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3623 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3624 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3625 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3626 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3627 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3628 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3629 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3630 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3631 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3632 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3633 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3634 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3635 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3636 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3637 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3638 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3639 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3640 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3641 dev->ib_dev.uverbs_ex_cmd_mask = 3642 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3643 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3644 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3645 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3646 3647 dev->ib_dev.query_device = mlx5_ib_query_device; 3648 dev->ib_dev.query_port = mlx5_ib_query_port; 3649 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3650 if (ll == IB_LINK_LAYER_ETHERNET) 3651 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3652 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3653 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3654 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3655 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3656 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3657 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3658 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3659 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3660 dev->ib_dev.mmap = mlx5_ib_mmap; 3661 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3662 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3663 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3664 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3665 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3666 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3667 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3668 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3669 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3670 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3671 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3672 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3673 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3674 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3675 dev->ib_dev.post_send = mlx5_ib_post_send; 3676 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3677 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3678 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3679 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3680 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3681 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3682 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3683 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3684 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3685 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3686 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3687 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3688 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3689 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3690 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3691 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3692 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3693 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3694 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3695 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 3696 dev->ib_dev.free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3697 if (mlx5_core_is_pf(mdev)) { 3698 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3699 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3700 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3701 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3702 } 3703 3704 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3705 3706 mlx5_ib_internal_fill_odp_caps(dev); 3707 3708 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3709 3710 if (MLX5_CAP_GEN(mdev, imaicl)) { 3711 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3712 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3713 dev->ib_dev.uverbs_cmd_mask |= 3714 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3715 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3716 } 3717 3718 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3719 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3720 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3721 } 3722 3723 if (MLX5_CAP_GEN(mdev, xrc)) { 3724 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3725 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3726 dev->ib_dev.uverbs_cmd_mask |= 3727 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3728 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3729 } 3730 3731 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3732 IB_LINK_LAYER_ETHERNET) { 3733 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3734 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3735 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3736 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3737 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3738 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3739 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3740 dev->ib_dev.uverbs_ex_cmd_mask |= 3741 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3742 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3743 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3744 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3745 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3746 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3747 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3748 } 3749 err = init_node_data(dev); 3750 if (err) 3751 goto err_free_port; 3752 3753 mutex_init(&dev->flow_db.lock); 3754 mutex_init(&dev->cap_mask_mutex); 3755 INIT_LIST_HEAD(&dev->qp_list); 3756 spin_lock_init(&dev->reset_flow_resource_lock); 3757 3758 if (ll == IB_LINK_LAYER_ETHERNET) { 3759 err = mlx5_enable_eth(dev); 3760 if (err) 3761 goto err_free_port; 3762 } 3763 3764 err = create_dev_resources(&dev->devr); 3765 if (err) 3766 goto err_disable_eth; 3767 3768 err = mlx5_ib_odp_init_one(dev); 3769 if (err) 3770 goto err_rsrc; 3771 3772 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3773 err = mlx5_ib_alloc_counters(dev); 3774 if (err) 3775 goto err_odp; 3776 } 3777 3778 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3779 if (!dev->mdev->priv.uar) 3780 goto err_cnt; 3781 3782 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3783 if (err) 3784 goto err_uar_page; 3785 3786 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3787 if (err) 3788 goto err_bfreg; 3789 3790 err = ib_register_device(&dev->ib_dev, NULL); 3791 if (err) 3792 goto err_fp_bfreg; 3793 3794 err = create_umr_res(dev); 3795 if (err) 3796 goto err_dev; 3797 3798 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3799 err = device_create_file(&dev->ib_dev.dev, 3800 mlx5_class_attributes[i]); 3801 if (err) 3802 goto err_umrc; 3803 } 3804 3805 dev->ib_active = true; 3806 3807 return dev; 3808 3809 err_umrc: 3810 destroy_umrc_res(dev); 3811 3812 err_dev: 3813 ib_unregister_device(&dev->ib_dev); 3814 3815 err_fp_bfreg: 3816 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3817 3818 err_bfreg: 3819 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3820 3821 err_uar_page: 3822 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3823 3824 err_cnt: 3825 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3826 mlx5_ib_dealloc_counters(dev); 3827 3828 err_odp: 3829 mlx5_ib_odp_remove_one(dev); 3830 3831 err_rsrc: 3832 destroy_dev_resources(&dev->devr); 3833 3834 err_disable_eth: 3835 if (ll == IB_LINK_LAYER_ETHERNET) { 3836 mlx5_disable_eth(dev); 3837 mlx5_remove_netdev_notifier(dev); 3838 } 3839 3840 err_free_port: 3841 kfree(dev->port); 3842 3843 err_dealloc: 3844 ib_dealloc_device((struct ib_device *)dev); 3845 3846 return NULL; 3847 } 3848 3849 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3850 { 3851 struct mlx5_ib_dev *dev = context; 3852 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3853 3854 mlx5_remove_netdev_notifier(dev); 3855 ib_unregister_device(&dev->ib_dev); 3856 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3857 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3858 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 3859 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3860 mlx5_ib_dealloc_counters(dev); 3861 destroy_umrc_res(dev); 3862 mlx5_ib_odp_remove_one(dev); 3863 destroy_dev_resources(&dev->devr); 3864 if (ll == IB_LINK_LAYER_ETHERNET) 3865 mlx5_disable_eth(dev); 3866 kfree(dev->port); 3867 ib_dealloc_device(&dev->ib_dev); 3868 } 3869 3870 static struct mlx5_interface mlx5_ib_interface = { 3871 .add = mlx5_ib_add, 3872 .remove = mlx5_ib_remove, 3873 .event = mlx5_ib_event, 3874 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3875 .pfault = mlx5_ib_pfault, 3876 #endif 3877 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3878 }; 3879 3880 static int __init mlx5_ib_init(void) 3881 { 3882 int err; 3883 3884 mlx5_ib_odp_init(); 3885 3886 err = mlx5_register_interface(&mlx5_ib_interface); 3887 3888 return err; 3889 } 3890 3891 static void __exit mlx5_ib_cleanup(void) 3892 { 3893 mlx5_unregister_interface(&mlx5_ib_interface); 3894 } 3895 3896 module_init(mlx5_ib_init); 3897 module_exit(mlx5_ib_cleanup); 3898