1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/driver.h> 29 #include <linux/list.h> 30 #include <rdma/ib_smi.h> 31 #include <rdma/ib_umem_odp.h> 32 #include <rdma/lag.h> 33 #include <linux/in.h> 34 #include <linux/etherdevice.h> 35 #include "mlx5_ib.h" 36 #include "ib_rep.h" 37 #include "cmd.h" 38 #include "devx.h" 39 #include "dm.h" 40 #include "fs.h" 41 #include "srq.h" 42 #include "qp.h" 43 #include "wr.h" 44 #include "restrack.h" 45 #include "counters.h" 46 #include "umr.h" 47 #include <rdma/uverbs_std_types.h> 48 #include <rdma/uverbs_ioctl.h> 49 #include <rdma/mlx5_user_ioctl_verbs.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/ib_ucaps.h> 52 #include "macsec.h" 53 #include "data_direct.h" 54 #include "dmah.h" 55 56 #define UVERBS_MODULE_NAME mlx5_ib 57 #include <rdma/uverbs_named_ioctl.h> 58 59 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 60 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 61 MODULE_LICENSE("Dual BSD/GPL"); 62 63 struct mlx5_ib_event_work { 64 struct work_struct work; 65 union { 66 struct mlx5_ib_dev *dev; 67 struct mlx5_ib_multiport_info *mpi; 68 }; 69 bool is_slave; 70 unsigned int event; 71 void *param; 72 }; 73 74 enum { 75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 76 }; 77 78 static struct workqueue_struct *mlx5_ib_event_wq; 79 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 80 static LIST_HEAD(mlx5_ib_dev_list); 81 /* 82 * This mutex should be held when accessing either of the above lists 83 */ 84 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 85 86 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 87 { 88 struct mlx5_ib_dev *dev; 89 90 mutex_lock(&mlx5_ib_multiport_mutex); 91 dev = mpi->ibdev; 92 mutex_unlock(&mlx5_ib_multiport_mutex); 93 return dev; 94 } 95 96 static enum rdma_link_layer 97 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 98 { 99 switch (port_type_cap) { 100 case MLX5_CAP_PORT_TYPE_IB: 101 return IB_LINK_LAYER_INFINIBAND; 102 case MLX5_CAP_PORT_TYPE_ETH: 103 return IB_LINK_LAYER_ETHERNET; 104 default: 105 return IB_LINK_LAYER_UNSPECIFIED; 106 } 107 } 108 109 static enum rdma_link_layer 110 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 111 { 112 struct mlx5_ib_dev *dev = to_mdev(device); 113 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 114 115 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 116 } 117 118 static int get_port_state(struct ib_device *ibdev, 119 u32 port_num, 120 enum ib_port_state *state) 121 { 122 struct ib_port_attr attr; 123 int ret; 124 125 memset(&attr, 0, sizeof(attr)); 126 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 127 if (!ret) 128 *state = attr.state; 129 return ret; 130 } 131 132 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 133 struct net_device *ndev, 134 struct net_device *upper, 135 u32 *port_num) 136 { 137 struct net_device *rep_ndev; 138 struct mlx5_ib_port *port; 139 int i; 140 141 for (i = 0; i < dev->num_ports; i++) { 142 port = &dev->port[i]; 143 if (!port->rep) 144 continue; 145 146 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 147 *port_num = i + 1; 148 return &port->roce; 149 } 150 151 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 152 continue; 153 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 154 if (rep_ndev && rep_ndev == ndev) { 155 dev_put(rep_ndev); 156 *port_num = i + 1; 157 return &port->roce; 158 } 159 160 dev_put(rep_ndev); 161 } 162 163 return NULL; 164 } 165 166 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 167 struct net_device *ndev, 168 struct net_device *upper, 169 struct net_device *ib_ndev) 170 { 171 if (!dev->ib_active) 172 return false; 173 174 /* Event is about our upper device */ 175 if (upper == ndev) 176 return true; 177 178 /* RDMA device is not in lag and not in switchdev */ 179 if (!dev->is_rep && !upper && ndev == ib_ndev) 180 return true; 181 182 /* RDMA devie is in switchdev */ 183 if (dev->is_rep && ndev == ib_ndev) 184 return true; 185 186 return false; 187 } 188 189 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 190 { 191 struct mlx5_ib_port *port; 192 int i; 193 194 for (i = 0; i < ibdev->num_ports; i++) { 195 port = &ibdev->port[i]; 196 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 197 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 198 } 199 } 200 201 return NULL; 202 } 203 204 static int mlx5_netdev_event(struct notifier_block *this, 205 unsigned long event, void *ptr) 206 { 207 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 208 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 209 u32 port_num = roce->native_port_num; 210 struct net_device *ib_ndev = NULL; 211 struct mlx5_core_dev *mdev; 212 struct mlx5_ib_dev *ibdev; 213 214 ibdev = roce->dev; 215 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 216 if (!mdev) 217 return NOTIFY_DONE; 218 219 switch (event) { 220 case NETDEV_REGISTER: 221 /* Should already be registered during the load */ 222 if (ibdev->is_rep) 223 break; 224 225 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 226 /* Exit if already registered */ 227 if (ib_ndev) 228 goto put_ndev; 229 230 if (ndev->dev.parent == mdev->device) 231 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 232 break; 233 234 case NETDEV_UNREGISTER: 235 /* In case of reps, ib device goes away before the netdevs */ 236 if (ibdev->is_rep) 237 break; 238 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 239 if (ib_ndev == ndev) 240 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 241 goto put_ndev; 242 243 case NETDEV_CHANGE: 244 case NETDEV_UP: 245 case NETDEV_DOWN: { 246 struct net_device *upper = NULL; 247 248 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 249 !mlx5_core_mp_enabled(mdev)) 250 return NOTIFY_DONE; 251 252 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 253 struct net_device *lag_ndev; 254 255 if(mlx5_lag_is_roce(mdev)) 256 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 257 else /* sriov lag */ 258 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 259 260 if (lag_ndev) { 261 upper = netdev_master_upper_dev_get(lag_ndev); 262 dev_put(lag_ndev); 263 } else { 264 goto done; 265 } 266 } 267 268 if (ibdev->is_rep) 269 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 270 if (!roce) 271 return NOTIFY_DONE; 272 273 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 274 275 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 276 struct ib_event ibev = { }; 277 enum ib_port_state port_state; 278 279 if (get_port_state(&ibdev->ib_dev, port_num, 280 &port_state)) 281 goto put_ndev; 282 283 if (roce->last_port_state == port_state) 284 goto put_ndev; 285 286 roce->last_port_state = port_state; 287 ibev.device = &ibdev->ib_dev; 288 if (port_state == IB_PORT_DOWN) 289 ibev.event = IB_EVENT_PORT_ERR; 290 else if (port_state == IB_PORT_ACTIVE) 291 ibev.event = IB_EVENT_PORT_ACTIVE; 292 else 293 goto put_ndev; 294 295 ibev.element.port_num = port_num; 296 ib_dispatch_event(&ibev); 297 } 298 break; 299 } 300 301 default: 302 break; 303 } 304 put_ndev: 305 dev_put(ib_ndev); 306 done: 307 mlx5_ib_put_native_port_mdev(ibdev, port_num); 308 return NOTIFY_DONE; 309 } 310 311 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 312 u32 ib_port_num, 313 u32 *native_port_num) 314 { 315 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 316 ib_port_num); 317 struct mlx5_core_dev *mdev = NULL; 318 struct mlx5_ib_multiport_info *mpi; 319 struct mlx5_ib_port *port; 320 321 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 322 if (native_port_num) 323 *native_port_num = smi_to_native_portnum(ibdev, 324 ib_port_num); 325 return ibdev->mdev; 326 327 } 328 329 if (!mlx5_core_mp_enabled(ibdev->mdev) || 330 ll != IB_LINK_LAYER_ETHERNET) { 331 if (native_port_num) 332 *native_port_num = ib_port_num; 333 return ibdev->mdev; 334 } 335 336 if (native_port_num) 337 *native_port_num = 1; 338 339 port = &ibdev->port[ib_port_num - 1]; 340 spin_lock(&port->mp.mpi_lock); 341 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 342 if (mpi && !mpi->unaffiliate) { 343 mdev = mpi->mdev; 344 /* If it's the master no need to refcount, it'll exist 345 * as long as the ib_dev exists. 346 */ 347 if (!mpi->is_master) 348 mpi->mdev_refcnt++; 349 } 350 spin_unlock(&port->mp.mpi_lock); 351 352 return mdev; 353 } 354 355 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 356 { 357 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 358 port_num); 359 struct mlx5_ib_multiport_info *mpi; 360 struct mlx5_ib_port *port; 361 362 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 363 return; 364 365 port = &ibdev->port[port_num - 1]; 366 367 spin_lock(&port->mp.mpi_lock); 368 mpi = ibdev->port[port_num - 1].mp.mpi; 369 if (mpi->is_master) 370 goto out; 371 372 mpi->mdev_refcnt--; 373 if (mpi->unaffiliate) 374 complete(&mpi->unref_comp); 375 out: 376 spin_unlock(&port->mp.mpi_lock); 377 } 378 379 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 380 u16 *active_speed, u8 *active_width) 381 { 382 switch (eth_proto_oper) { 383 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 385 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 386 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 387 *active_width = IB_WIDTH_1X; 388 *active_speed = IB_SPEED_SDR; 389 break; 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 397 *active_width = IB_WIDTH_1X; 398 *active_speed = IB_SPEED_QDR; 399 break; 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_EDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 416 *active_width = IB_WIDTH_1X; 417 *active_speed = IB_SPEED_HDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 420 *active_width = IB_WIDTH_4X; 421 *active_speed = IB_SPEED_FDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 438 u8 *active_width) 439 { 440 switch (eth_proto_oper) { 441 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 442 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 443 *active_width = IB_WIDTH_1X; 444 *active_speed = IB_SPEED_SDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 447 *active_width = IB_WIDTH_1X; 448 *active_speed = IB_SPEED_DDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 451 *active_width = IB_WIDTH_1X; 452 *active_speed = IB_SPEED_QDR; 453 break; 454 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 455 *active_width = IB_WIDTH_4X; 456 *active_speed = IB_SPEED_QDR; 457 break; 458 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 459 *active_width = IB_WIDTH_1X; 460 *active_speed = IB_SPEED_EDR; 461 break; 462 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 463 *active_width = IB_WIDTH_2X; 464 *active_speed = IB_SPEED_EDR; 465 break; 466 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 467 *active_width = IB_WIDTH_1X; 468 *active_speed = IB_SPEED_HDR; 469 break; 470 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 471 *active_width = IB_WIDTH_4X; 472 *active_speed = IB_SPEED_EDR; 473 break; 474 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 475 *active_width = IB_WIDTH_2X; 476 *active_speed = IB_SPEED_HDR; 477 break; 478 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 479 *active_width = IB_WIDTH_1X; 480 *active_speed = IB_SPEED_NDR; 481 break; 482 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 483 *active_width = IB_WIDTH_4X; 484 *active_speed = IB_SPEED_HDR; 485 break; 486 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 487 *active_width = IB_WIDTH_2X; 488 *active_speed = IB_SPEED_NDR; 489 break; 490 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 491 *active_width = IB_WIDTH_1X; 492 *active_speed = IB_SPEED_XDR; 493 break; 494 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 495 *active_width = IB_WIDTH_8X; 496 *active_speed = IB_SPEED_HDR; 497 break; 498 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 499 *active_width = IB_WIDTH_4X; 500 *active_speed = IB_SPEED_NDR; 501 break; 502 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 503 *active_width = IB_WIDTH_2X; 504 *active_speed = IB_SPEED_XDR; 505 break; 506 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 507 *active_width = IB_WIDTH_8X; 508 *active_speed = IB_SPEED_NDR; 509 break; 510 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 511 *active_width = IB_WIDTH_4X; 512 *active_speed = IB_SPEED_XDR; 513 break; 514 case MLX5E_PROT_MASK(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8): 515 *active_width = IB_WIDTH_8X; 516 *active_speed = IB_SPEED_XDR; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 return 0; 523 } 524 525 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 526 u8 *active_width, bool ext) 527 { 528 return ext ? 529 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 530 active_width) : 531 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 532 active_width); 533 } 534 535 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 536 struct ib_port_attr *props) 537 { 538 struct mlx5_ib_dev *dev = to_mdev(device); 539 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 540 struct mlx5_core_dev *mdev; 541 struct net_device *ndev, *upper; 542 enum ib_mtu ndev_ib_mtu; 543 bool put_mdev = true; 544 u32 eth_prot_oper; 545 u32 mdev_port_num; 546 bool ext; 547 int err; 548 549 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 550 if (!mdev) { 551 /* This means the port isn't affiliated yet. Get the 552 * info for the master port instead. 553 */ 554 put_mdev = false; 555 mdev = dev->mdev; 556 mdev_port_num = 1; 557 port_num = 1; 558 } 559 560 /* Possible bad flows are checked before filling out props so in case 561 * of an error it will still be zeroed out. 562 * Use native port in case of reps 563 */ 564 if (dev->is_rep) 565 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 566 1, 0); 567 else 568 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 569 mdev_port_num, 0); 570 if (err) 571 goto out; 572 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 573 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 574 575 props->active_width = IB_WIDTH_4X; 576 props->active_speed = IB_SPEED_QDR; 577 578 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 579 &props->active_width, ext); 580 581 if (!dev->is_rep && dev->mdev->roce.roce_en) { 582 u16 qkey_viol_cntr; 583 584 props->port_cap_flags |= IB_PORT_CM_SUP; 585 props->ip_gids = true; 586 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 587 roce_address_table_size); 588 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 589 props->qkey_viol_cntr = qkey_viol_cntr; 590 } 591 props->max_mtu = IB_MTU_4096; 592 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 593 props->pkey_tbl_len = 1; 594 props->state = IB_PORT_DOWN; 595 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 596 597 /* If this is a stub query for an unaffiliated port stop here */ 598 if (!put_mdev) 599 goto out; 600 601 ndev = ib_device_get_netdev(device, port_num); 602 if (!ndev) 603 goto out; 604 605 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 606 rcu_read_lock(); 607 upper = netdev_master_upper_dev_get_rcu(ndev); 608 if (upper) { 609 dev_put(ndev); 610 ndev = upper; 611 dev_hold(ndev); 612 } 613 rcu_read_unlock(); 614 } 615 616 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 617 props->state = IB_PORT_ACTIVE; 618 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 619 } 620 621 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 622 623 dev_put(ndev); 624 625 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 626 out: 627 if (put_mdev) 628 mlx5_ib_put_native_port_mdev(dev, port_num); 629 return err; 630 } 631 632 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 633 unsigned int index, const union ib_gid *gid, 634 const struct ib_gid_attr *attr) 635 { 636 enum ib_gid_type gid_type; 637 u16 vlan_id = 0xffff; 638 u8 roce_version = 0; 639 u8 roce_l3_type = 0; 640 u8 mac[ETH_ALEN]; 641 int ret; 642 643 gid_type = attr->gid_type; 644 if (gid) { 645 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 646 if (ret) 647 return ret; 648 } 649 650 switch (gid_type) { 651 case IB_GID_TYPE_ROCE: 652 roce_version = MLX5_ROCE_VERSION_1; 653 break; 654 case IB_GID_TYPE_ROCE_UDP_ENCAP: 655 roce_version = MLX5_ROCE_VERSION_2; 656 if (gid && ipv6_addr_v4mapped((void *)gid)) 657 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 658 else 659 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 660 break; 661 662 default: 663 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 664 } 665 666 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 667 roce_l3_type, gid->raw, mac, 668 vlan_id < VLAN_CFI_MASK, vlan_id, 669 port_num); 670 } 671 672 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 673 __always_unused void **context) 674 { 675 int ret; 676 677 ret = mlx5r_add_gid_macsec_operations(attr); 678 if (ret) 679 return ret; 680 681 return set_roce_addr(to_mdev(attr->device), attr->port_num, 682 attr->index, &attr->gid, attr); 683 } 684 685 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 686 __always_unused void **context) 687 { 688 int ret; 689 690 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 691 attr->index, NULL, attr); 692 if (ret) 693 return ret; 694 695 mlx5r_del_gid_macsec_operations(attr); 696 return 0; 697 } 698 699 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 700 const struct ib_gid_attr *attr) 701 { 702 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 703 return 0; 704 705 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 706 } 707 708 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 709 { 710 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 711 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 712 return 0; 713 } 714 715 enum { 716 MLX5_VPORT_ACCESS_METHOD_MAD, 717 MLX5_VPORT_ACCESS_METHOD_HCA, 718 MLX5_VPORT_ACCESS_METHOD_NIC, 719 }; 720 721 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 722 { 723 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 724 return MLX5_VPORT_ACCESS_METHOD_MAD; 725 726 if (mlx5_ib_port_link_layer(ibdev, 1) == 727 IB_LINK_LAYER_ETHERNET) 728 return MLX5_VPORT_ACCESS_METHOD_NIC; 729 730 return MLX5_VPORT_ACCESS_METHOD_HCA; 731 } 732 733 static void get_atomic_caps(struct mlx5_ib_dev *dev, 734 u8 atomic_size_qp, 735 struct ib_device_attr *props) 736 { 737 u8 tmp; 738 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 739 u8 atomic_req_8B_endianness_mode = 740 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 741 742 /* Check if HW supports 8 bytes standard atomic operations and capable 743 * of host endianness respond 744 */ 745 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 746 if (((atomic_operations & tmp) == tmp) && 747 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 748 (atomic_req_8B_endianness_mode)) { 749 props->atomic_cap = IB_ATOMIC_HCA; 750 } else { 751 props->atomic_cap = IB_ATOMIC_NONE; 752 } 753 } 754 755 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 756 struct ib_device_attr *props) 757 { 758 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 759 760 get_atomic_caps(dev, atomic_size_qp, props); 761 } 762 763 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 764 __be64 *sys_image_guid) 765 { 766 struct mlx5_ib_dev *dev = to_mdev(ibdev); 767 struct mlx5_core_dev *mdev = dev->mdev; 768 u64 tmp; 769 int err; 770 771 switch (mlx5_get_vport_access_method(ibdev)) { 772 case MLX5_VPORT_ACCESS_METHOD_MAD: 773 return mlx5_query_mad_ifc_system_image_guid(ibdev, 774 sys_image_guid); 775 776 case MLX5_VPORT_ACCESS_METHOD_HCA: 777 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 778 break; 779 780 case MLX5_VPORT_ACCESS_METHOD_NIC: 781 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 782 break; 783 784 default: 785 return -EINVAL; 786 } 787 788 if (!err) 789 *sys_image_guid = cpu_to_be64(tmp); 790 791 return err; 792 793 } 794 795 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 796 u16 *max_pkeys) 797 { 798 struct mlx5_ib_dev *dev = to_mdev(ibdev); 799 struct mlx5_core_dev *mdev = dev->mdev; 800 801 switch (mlx5_get_vport_access_method(ibdev)) { 802 case MLX5_VPORT_ACCESS_METHOD_MAD: 803 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 804 805 case MLX5_VPORT_ACCESS_METHOD_HCA: 806 case MLX5_VPORT_ACCESS_METHOD_NIC: 807 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 808 pkey_table_size)); 809 return 0; 810 811 default: 812 return -EINVAL; 813 } 814 } 815 816 static int mlx5_query_vendor_id(struct ib_device *ibdev, 817 u32 *vendor_id) 818 { 819 struct mlx5_ib_dev *dev = to_mdev(ibdev); 820 821 switch (mlx5_get_vport_access_method(ibdev)) { 822 case MLX5_VPORT_ACCESS_METHOD_MAD: 823 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 824 825 case MLX5_VPORT_ACCESS_METHOD_HCA: 826 case MLX5_VPORT_ACCESS_METHOD_NIC: 827 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 828 829 default: 830 return -EINVAL; 831 } 832 } 833 834 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 835 __be64 *node_guid) 836 { 837 u64 tmp; 838 int err; 839 840 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 841 case MLX5_VPORT_ACCESS_METHOD_MAD: 842 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 843 844 case MLX5_VPORT_ACCESS_METHOD_HCA: 845 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 846 break; 847 848 case MLX5_VPORT_ACCESS_METHOD_NIC: 849 err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp); 850 break; 851 852 default: 853 return -EINVAL; 854 } 855 856 if (!err) 857 *node_guid = cpu_to_be64(tmp); 858 859 return err; 860 } 861 862 struct mlx5_reg_node_desc { 863 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 864 }; 865 866 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 867 { 868 struct mlx5_reg_node_desc in; 869 870 if (mlx5_use_mad_ifc(dev)) 871 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 872 873 memset(&in, 0, sizeof(in)); 874 875 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 876 sizeof(struct mlx5_reg_node_desc), 877 MLX5_REG_NODE_DESC, 0, 0); 878 } 879 880 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 881 struct mlx5_ib_query_device_resp *resp) 882 { 883 struct mlx5_eswitch *esw = mdev->priv.eswitch; 884 u16 vport = mlx5_eswitch_manager_vport(mdev); 885 886 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 887 vport); 888 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 889 } 890 891 /* 892 * Calculate maximum SQ overhead across all QP types. 893 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 894 * have smaller overhead than the types calculated below, 895 * so they are implicitly included. 896 */ 897 static u32 mlx5_ib_calc_max_sq_overhead(void) 898 { 899 u32 max_overhead_xrc, overhead_ud_lso, a, b; 900 901 /* XRC_INI */ 902 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 903 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 904 a = sizeof(struct mlx5_wqe_atomic_seg) + 905 sizeof(struct mlx5_wqe_raddr_seg); 906 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 907 sizeof(struct mlx5_mkey_seg) + 908 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 909 max_overhead_xrc += max(a, b); 910 911 /* UD with LSO */ 912 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 913 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 914 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 915 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 916 917 return max(max_overhead_xrc, overhead_ud_lso); 918 } 919 920 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 921 { 922 struct mlx5_core_dev *mdev = dev->mdev; 923 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 924 u32 max_wqe_size; 925 /* max QP overhead + 1 SGE, no inline, no special features */ 926 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 927 sizeof(struct mlx5_wqe_data_seg); 928 929 max_wqe_size = roundup_pow_of_two(max_wqe_size); 930 931 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 932 933 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 934 } 935 936 static int mlx5_ib_query_device(struct ib_device *ibdev, 937 struct ib_device_attr *props, 938 struct ib_udata *uhw) 939 { 940 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 941 struct mlx5_ib_dev *dev = to_mdev(ibdev); 942 struct mlx5_core_dev *mdev = dev->mdev; 943 int err = -ENOMEM; 944 int max_sq_desc; 945 int max_rq_sg; 946 int max_sq_sg; 947 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 948 bool raw_support = !mlx5_core_mp_enabled(mdev); 949 struct mlx5_ib_query_device_resp resp = {}; 950 size_t resp_len; 951 u64 max_tso; 952 953 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 954 if (uhw_outlen && uhw_outlen < resp_len) 955 return -EINVAL; 956 957 resp.response_length = resp_len; 958 959 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 960 return -EINVAL; 961 962 memset(props, 0, sizeof(*props)); 963 err = mlx5_query_system_image_guid(ibdev, 964 &props->sys_image_guid); 965 if (err) 966 return err; 967 968 props->max_pkeys = dev->pkey_table_len; 969 970 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 971 if (err) 972 return err; 973 974 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 975 (fw_rev_min(dev->mdev) << 16) | 976 fw_rev_sub(dev->mdev); 977 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 978 IB_DEVICE_PORT_ACTIVE_EVENT | 979 IB_DEVICE_SYS_IMAGE_GUID | 980 IB_DEVICE_RC_RNR_NAK_GEN; 981 982 if (MLX5_CAP_GEN(mdev, pkv)) 983 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 984 if (MLX5_CAP_GEN(mdev, qkv)) 985 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 986 if (MLX5_CAP_GEN(mdev, apm)) 987 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 988 if (MLX5_CAP_GEN(mdev, xrc)) 989 props->device_cap_flags |= IB_DEVICE_XRC; 990 if (MLX5_CAP_GEN(mdev, imaicl)) { 991 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 992 IB_DEVICE_MEM_WINDOW_TYPE_2B; 993 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 994 /* We support 'Gappy' memory registration too */ 995 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 996 } 997 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 998 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 999 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 1000 if (MLX5_CAP_GEN(mdev, sho)) { 1001 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 1002 /* At this stage no support for signature handover */ 1003 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1004 IB_PROT_T10DIF_TYPE_2 | 1005 IB_PROT_T10DIF_TYPE_3; 1006 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1007 IB_GUARD_T10DIF_CSUM; 1008 } 1009 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1010 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1011 1012 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1013 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1014 /* Legacy bit to support old userspace libraries */ 1015 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1016 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1017 } 1018 1019 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1020 props->raw_packet_caps |= 1021 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1022 1023 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1024 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1025 if (max_tso) { 1026 resp.tso_caps.max_tso = 1 << max_tso; 1027 resp.tso_caps.supported_qpts |= 1028 1 << IB_QPT_RAW_PACKET; 1029 resp.response_length += sizeof(resp.tso_caps); 1030 } 1031 } 1032 1033 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1034 resp.rss_caps.rx_hash_function = 1035 MLX5_RX_HASH_FUNC_TOEPLITZ; 1036 resp.rss_caps.rx_hash_fields_mask = 1037 MLX5_RX_HASH_SRC_IPV4 | 1038 MLX5_RX_HASH_DST_IPV4 | 1039 MLX5_RX_HASH_SRC_IPV6 | 1040 MLX5_RX_HASH_DST_IPV6 | 1041 MLX5_RX_HASH_SRC_PORT_TCP | 1042 MLX5_RX_HASH_DST_PORT_TCP | 1043 MLX5_RX_HASH_SRC_PORT_UDP | 1044 MLX5_RX_HASH_DST_PORT_UDP | 1045 MLX5_RX_HASH_INNER; 1046 resp.response_length += sizeof(resp.rss_caps); 1047 } 1048 } else { 1049 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1050 resp.response_length += sizeof(resp.tso_caps); 1051 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1052 resp.response_length += sizeof(resp.rss_caps); 1053 } 1054 1055 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1056 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1057 props->kernel_cap_flags |= IBK_UD_TSO; 1058 } 1059 1060 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1061 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1062 raw_support) 1063 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1064 1065 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1066 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1067 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1068 1069 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1070 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1071 raw_support) { 1072 /* Legacy bit to support old userspace libraries */ 1073 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1074 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1075 } 1076 1077 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1078 props->max_dm_size = 1079 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1080 } 1081 1082 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1083 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1084 1085 if (MLX5_CAP_GEN(mdev, end_pad)) 1086 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1087 1088 props->vendor_part_id = mdev->pdev->device; 1089 props->hw_ver = mdev->pdev->revision; 1090 1091 props->max_mr_size = ~0ull; 1092 props->page_size_cap = ~(min_page_size - 1); 1093 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1094 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1095 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1096 sizeof(struct mlx5_wqe_data_seg); 1097 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1098 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1099 sizeof(struct mlx5_wqe_raddr_seg)) / 1100 sizeof(struct mlx5_wqe_data_seg); 1101 props->max_send_sge = max_sq_sg; 1102 props->max_recv_sge = max_rq_sg; 1103 props->max_sge_rd = MLX5_MAX_SGE_RD; 1104 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1105 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1106 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1107 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1108 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1109 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1110 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1111 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1112 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1113 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1114 props->max_srq_sge = max_rq_sg - 1; 1115 props->max_fast_reg_page_list_len = 1116 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1117 props->max_pi_fast_reg_page_list_len = 1118 props->max_fast_reg_page_list_len / 2; 1119 props->max_sgl_rd = 1120 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1121 get_atomic_caps_qp(dev, props); 1122 props->masked_atomic_cap = IB_ATOMIC_NONE; 1123 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1124 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1125 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1126 props->max_mcast_grp; 1127 props->max_ah = INT_MAX; 1128 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1129 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1130 1131 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1132 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1133 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1134 props->odp_caps = dev->odp_caps; 1135 if (!uhw) { 1136 /* ODP for kernel QPs is not implemented for receive 1137 * WQEs and SRQ WQEs 1138 */ 1139 props->odp_caps.per_transport_caps.rc_odp_caps &= 1140 ~(IB_ODP_SUPPORT_READ | 1141 IB_ODP_SUPPORT_SRQ_RECV); 1142 props->odp_caps.per_transport_caps.uc_odp_caps &= 1143 ~(IB_ODP_SUPPORT_READ | 1144 IB_ODP_SUPPORT_SRQ_RECV); 1145 props->odp_caps.per_transport_caps.ud_odp_caps &= 1146 ~(IB_ODP_SUPPORT_READ | 1147 IB_ODP_SUPPORT_SRQ_RECV); 1148 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1149 ~(IB_ODP_SUPPORT_READ | 1150 IB_ODP_SUPPORT_SRQ_RECV); 1151 } 1152 } 1153 1154 if (mlx5_core_is_vf(mdev)) 1155 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1156 1157 if (mlx5_ib_port_link_layer(ibdev, 1) == 1158 IB_LINK_LAYER_ETHERNET && raw_support) { 1159 props->rss_caps.max_rwq_indirection_tables = 1160 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1161 props->rss_caps.max_rwq_indirection_table_size = 1162 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1163 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1164 props->max_wq_type_rq = 1165 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1166 } 1167 1168 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1169 props->tm_caps.max_num_tags = 1170 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1171 props->tm_caps.max_ops = 1172 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1173 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1174 } 1175 1176 if (MLX5_CAP_GEN(mdev, tag_matching) && 1177 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1178 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1179 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1180 } 1181 1182 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1183 props->cq_caps.max_cq_moderation_count = 1184 MLX5_MAX_CQ_COUNT; 1185 props->cq_caps.max_cq_moderation_period = 1186 MLX5_MAX_CQ_PERIOD; 1187 } 1188 1189 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1190 resp.response_length += sizeof(resp.cqe_comp_caps); 1191 1192 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1193 resp.cqe_comp_caps.max_num = 1194 MLX5_CAP_GEN(dev->mdev, 1195 cqe_compression_max_num); 1196 1197 resp.cqe_comp_caps.supported_format = 1198 MLX5_IB_CQE_RES_FORMAT_HASH | 1199 MLX5_IB_CQE_RES_FORMAT_CSUM; 1200 1201 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1202 resp.cqe_comp_caps.supported_format |= 1203 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1204 } 1205 } 1206 1207 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1208 raw_support) { 1209 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1210 MLX5_CAP_GEN(mdev, qos)) { 1211 resp.packet_pacing_caps.qp_rate_limit_max = 1212 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1213 resp.packet_pacing_caps.qp_rate_limit_min = 1214 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1215 resp.packet_pacing_caps.supported_qpts |= 1216 1 << IB_QPT_RAW_PACKET; 1217 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1218 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1219 resp.packet_pacing_caps.cap_flags |= 1220 MLX5_IB_PP_SUPPORT_BURST; 1221 } 1222 resp.response_length += sizeof(resp.packet_pacing_caps); 1223 } 1224 1225 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1226 uhw_outlen) { 1227 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1228 resp.mlx5_ib_support_multi_pkt_send_wqes = 1229 MLX5_IB_ALLOW_MPW; 1230 1231 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1232 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1233 MLX5_IB_SUPPORT_EMPW; 1234 1235 resp.response_length += 1236 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1237 } 1238 1239 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1240 resp.response_length += sizeof(resp.flags); 1241 1242 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1243 resp.flags |= 1244 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1245 1246 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1247 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1248 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1249 resp.flags |= 1250 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1251 1252 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1253 1254 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1255 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1256 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1257 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1258 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1259 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1260 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1261 } 1262 1263 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1264 resp.response_length += sizeof(resp.sw_parsing_caps); 1265 if (MLX5_CAP_ETH(mdev, swp)) { 1266 resp.sw_parsing_caps.sw_parsing_offloads |= 1267 MLX5_IB_SW_PARSING; 1268 1269 if (MLX5_CAP_ETH(mdev, swp_csum)) 1270 resp.sw_parsing_caps.sw_parsing_offloads |= 1271 MLX5_IB_SW_PARSING_CSUM; 1272 1273 if (MLX5_CAP_ETH(mdev, swp_lso)) 1274 resp.sw_parsing_caps.sw_parsing_offloads |= 1275 MLX5_IB_SW_PARSING_LSO; 1276 1277 if (resp.sw_parsing_caps.sw_parsing_offloads) 1278 resp.sw_parsing_caps.supported_qpts = 1279 BIT(IB_QPT_RAW_PACKET); 1280 } 1281 } 1282 1283 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1284 raw_support) { 1285 resp.response_length += sizeof(resp.striding_rq_caps); 1286 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1287 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1288 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1289 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1290 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1291 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1292 resp.striding_rq_caps 1293 .min_single_wqe_log_num_of_strides = 1294 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1295 else 1296 resp.striding_rq_caps 1297 .min_single_wqe_log_num_of_strides = 1298 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1299 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1300 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1301 resp.striding_rq_caps.supported_qpts = 1302 BIT(IB_QPT_RAW_PACKET); 1303 } 1304 } 1305 1306 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1307 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1308 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1309 resp.tunnel_offloads_caps |= 1310 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1311 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1312 resp.tunnel_offloads_caps |= 1313 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1314 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1315 resp.tunnel_offloads_caps |= 1316 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1317 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1318 resp.tunnel_offloads_caps |= 1319 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1320 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1321 resp.tunnel_offloads_caps |= 1322 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1323 } 1324 1325 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1326 resp.response_length += sizeof(resp.dci_streams_caps); 1327 1328 resp.dci_streams_caps.max_log_num_concurent = 1329 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1330 1331 resp.dci_streams_caps.max_log_num_errored = 1332 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1333 } 1334 1335 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1336 resp.response_length += sizeof(resp.reserved); 1337 1338 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1339 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1340 1341 resp.response_length += sizeof(resp.reg_c0); 1342 1343 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1344 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1345 fill_esw_mgr_reg_c0(mdev, &resp); 1346 } 1347 1348 if (uhw_outlen) { 1349 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1350 1351 if (err) 1352 return err; 1353 } 1354 1355 return 0; 1356 } 1357 1358 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1359 u8 *ib_width) 1360 { 1361 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1362 1363 if (active_width & MLX5_PTYS_WIDTH_1X) 1364 *ib_width = IB_WIDTH_1X; 1365 else if (active_width & MLX5_PTYS_WIDTH_2X) 1366 *ib_width = IB_WIDTH_2X; 1367 else if (active_width & MLX5_PTYS_WIDTH_4X) 1368 *ib_width = IB_WIDTH_4X; 1369 else if (active_width & MLX5_PTYS_WIDTH_8X) 1370 *ib_width = IB_WIDTH_8X; 1371 else if (active_width & MLX5_PTYS_WIDTH_12X) 1372 *ib_width = IB_WIDTH_12X; 1373 else { 1374 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1375 active_width); 1376 *ib_width = IB_WIDTH_4X; 1377 } 1378 1379 return; 1380 } 1381 1382 static int mlx5_mtu_to_ib_mtu(int mtu) 1383 { 1384 switch (mtu) { 1385 case 256: return 1; 1386 case 512: return 2; 1387 case 1024: return 3; 1388 case 2048: return 4; 1389 case 4096: return 5; 1390 default: 1391 pr_warn("invalid mtu\n"); 1392 return -1; 1393 } 1394 } 1395 1396 enum ib_max_vl_num { 1397 __IB_MAX_VL_0 = 1, 1398 __IB_MAX_VL_0_1 = 2, 1399 __IB_MAX_VL_0_3 = 3, 1400 __IB_MAX_VL_0_7 = 4, 1401 __IB_MAX_VL_0_14 = 5, 1402 }; 1403 1404 enum mlx5_vl_hw_cap { 1405 MLX5_VL_HW_0 = 1, 1406 MLX5_VL_HW_0_1 = 2, 1407 MLX5_VL_HW_0_2 = 3, 1408 MLX5_VL_HW_0_3 = 4, 1409 MLX5_VL_HW_0_4 = 5, 1410 MLX5_VL_HW_0_5 = 6, 1411 MLX5_VL_HW_0_6 = 7, 1412 MLX5_VL_HW_0_7 = 8, 1413 MLX5_VL_HW_0_14 = 15 1414 }; 1415 1416 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1417 u8 *max_vl_num) 1418 { 1419 switch (vl_hw_cap) { 1420 case MLX5_VL_HW_0: 1421 *max_vl_num = __IB_MAX_VL_0; 1422 break; 1423 case MLX5_VL_HW_0_1: 1424 *max_vl_num = __IB_MAX_VL_0_1; 1425 break; 1426 case MLX5_VL_HW_0_3: 1427 *max_vl_num = __IB_MAX_VL_0_3; 1428 break; 1429 case MLX5_VL_HW_0_7: 1430 *max_vl_num = __IB_MAX_VL_0_7; 1431 break; 1432 case MLX5_VL_HW_0_14: 1433 *max_vl_num = __IB_MAX_VL_0_14; 1434 break; 1435 1436 default: 1437 return -EINVAL; 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1444 struct ib_port_attr *props) 1445 { 1446 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1447 struct mlx5_core_dev *mdev = dev->mdev; 1448 struct mlx5_hca_vport_context *rep; 1449 u8 vl_hw_cap, plane_index = 0; 1450 u16 max_mtu; 1451 u16 oper_mtu; 1452 int err; 1453 u16 ib_link_width_oper; 1454 1455 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1456 if (!rep) { 1457 err = -ENOMEM; 1458 goto out; 1459 } 1460 1461 /* props being zeroed by the caller, avoid zeroing it here */ 1462 1463 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1464 plane_index = port; 1465 port = smi_to_native_portnum(dev, port); 1466 } 1467 1468 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1469 if (err) 1470 goto out; 1471 1472 props->lid = rep->lid; 1473 props->lmc = rep->lmc; 1474 props->sm_lid = rep->sm_lid; 1475 props->sm_sl = rep->sm_sl; 1476 props->state = rep->vport_state; 1477 props->phys_state = rep->port_physical_state; 1478 1479 props->port_cap_flags = rep->cap_mask1; 1480 if (dev->num_plane) { 1481 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1482 props->port_cap_flags &= ~IB_PORT_SM; 1483 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1484 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1485 1486 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1487 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1488 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1489 props->bad_pkey_cntr = rep->pkey_violation_counter; 1490 props->qkey_viol_cntr = rep->qkey_violation_counter; 1491 props->subnet_timeout = rep->subnet_timeout; 1492 props->init_type_reply = rep->init_type_reply; 1493 1494 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1495 props->port_cap_flags2 = rep->cap_mask2; 1496 1497 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1498 &props->active_speed, port, plane_index); 1499 if (err) 1500 goto out; 1501 1502 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1503 1504 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1505 1506 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1507 1508 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1509 1510 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1511 1512 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1513 if (err) 1514 goto out; 1515 1516 err = translate_max_vl_num(ibdev, vl_hw_cap, 1517 &props->max_vl_num); 1518 out: 1519 kfree(rep); 1520 return err; 1521 } 1522 1523 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1524 struct ib_port_attr *props) 1525 { 1526 unsigned int count; 1527 int ret; 1528 1529 switch (mlx5_get_vport_access_method(ibdev)) { 1530 case MLX5_VPORT_ACCESS_METHOD_MAD: 1531 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1532 break; 1533 1534 case MLX5_VPORT_ACCESS_METHOD_HCA: 1535 ret = mlx5_query_hca_port(ibdev, port, props); 1536 break; 1537 1538 case MLX5_VPORT_ACCESS_METHOD_NIC: 1539 ret = mlx5_query_port_roce(ibdev, port, props); 1540 break; 1541 1542 default: 1543 ret = -EINVAL; 1544 } 1545 1546 if (!ret && props) { 1547 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1548 struct mlx5_core_dev *mdev; 1549 bool put_mdev = true; 1550 1551 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1552 if (!mdev) { 1553 /* If the port isn't affiliated yet query the master. 1554 * The master and slave will have the same values. 1555 */ 1556 mdev = dev->mdev; 1557 port = 1; 1558 put_mdev = false; 1559 } 1560 count = mlx5_core_reserved_gids_count(mdev); 1561 if (put_mdev) 1562 mlx5_ib_put_native_port_mdev(dev, port); 1563 props->gid_tbl_len -= count; 1564 } 1565 return ret; 1566 } 1567 1568 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1569 struct ib_port_attr *props) 1570 { 1571 return mlx5_query_port_roce(ibdev, port, props); 1572 } 1573 1574 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1575 u16 *pkey) 1576 { 1577 /* Default special Pkey for representor device port as per the 1578 * IB specification 1.3 section 10.9.1.2. 1579 */ 1580 *pkey = 0xffff; 1581 return 0; 1582 } 1583 1584 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1585 union ib_gid *gid) 1586 { 1587 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1588 struct mlx5_core_dev *mdev = dev->mdev; 1589 1590 switch (mlx5_get_vport_access_method(ibdev)) { 1591 case MLX5_VPORT_ACCESS_METHOD_MAD: 1592 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1593 1594 case MLX5_VPORT_ACCESS_METHOD_HCA: 1595 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1596 1597 default: 1598 return -EINVAL; 1599 } 1600 1601 } 1602 1603 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1604 u16 index, u16 *pkey) 1605 { 1606 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1607 struct mlx5_core_dev *mdev; 1608 bool put_mdev = true; 1609 u32 mdev_port_num; 1610 int err; 1611 1612 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1613 if (!mdev) { 1614 /* The port isn't affiliated yet, get the PKey from the master 1615 * port. For RoCE the PKey tables will be the same. 1616 */ 1617 put_mdev = false; 1618 mdev = dev->mdev; 1619 mdev_port_num = 1; 1620 } 1621 1622 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1623 index, pkey); 1624 if (put_mdev) 1625 mlx5_ib_put_native_port_mdev(dev, port); 1626 1627 return err; 1628 } 1629 1630 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1631 u16 *pkey) 1632 { 1633 switch (mlx5_get_vport_access_method(ibdev)) { 1634 case MLX5_VPORT_ACCESS_METHOD_MAD: 1635 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1636 1637 case MLX5_VPORT_ACCESS_METHOD_HCA: 1638 case MLX5_VPORT_ACCESS_METHOD_NIC: 1639 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1640 default: 1641 return -EINVAL; 1642 } 1643 } 1644 1645 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1646 struct ib_device_modify *props) 1647 { 1648 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1649 struct mlx5_reg_node_desc in; 1650 struct mlx5_reg_node_desc out; 1651 int err; 1652 1653 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1654 return -EOPNOTSUPP; 1655 1656 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1657 return 0; 1658 1659 /* 1660 * If possible, pass node desc to FW, so it can generate 1661 * a 144 trap. If cmd fails, just ignore. 1662 */ 1663 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1664 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1665 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1666 if (err) 1667 return err; 1668 1669 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1670 1671 return err; 1672 } 1673 1674 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1675 u32 value) 1676 { 1677 struct mlx5_hca_vport_context ctx = {}; 1678 struct mlx5_core_dev *mdev; 1679 u32 mdev_port_num; 1680 int err; 1681 1682 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1683 if (!mdev) 1684 return -ENODEV; 1685 1686 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1687 if (err) 1688 goto out; 1689 1690 if (~ctx.cap_mask1_perm & mask) { 1691 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1692 mask, ctx.cap_mask1_perm); 1693 err = -EINVAL; 1694 goto out; 1695 } 1696 1697 ctx.cap_mask1 = value; 1698 ctx.cap_mask1_perm = mask; 1699 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1700 0, &ctx); 1701 1702 out: 1703 mlx5_ib_put_native_port_mdev(dev, port_num); 1704 1705 return err; 1706 } 1707 1708 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1709 struct ib_port_modify *props) 1710 { 1711 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1712 struct ib_port_attr attr; 1713 u32 tmp; 1714 int err; 1715 u32 change_mask; 1716 u32 value; 1717 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1718 IB_LINK_LAYER_INFINIBAND); 1719 1720 /* CM layer calls ib_modify_port() regardless of the link layer. For 1721 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1722 */ 1723 if (!is_ib) 1724 return 0; 1725 1726 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1727 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1728 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1729 return set_port_caps_atomic(dev, port, change_mask, value); 1730 } 1731 1732 mutex_lock(&dev->cap_mask_mutex); 1733 1734 err = ib_query_port(ibdev, port, &attr); 1735 if (err) 1736 goto out; 1737 1738 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1739 ~props->clr_port_cap_mask; 1740 1741 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1742 1743 out: 1744 mutex_unlock(&dev->cap_mask_mutex); 1745 return err; 1746 } 1747 1748 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1749 { 1750 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1751 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1752 } 1753 1754 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1755 { 1756 /* Large page with non 4k uar support might limit the dynamic size */ 1757 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1758 return MLX5_MIN_DYN_BFREGS; 1759 1760 return MLX5_MAX_DYN_BFREGS; 1761 } 1762 1763 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1764 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1765 struct mlx5_bfreg_info *bfregi) 1766 { 1767 int uars_per_sys_page; 1768 int bfregs_per_sys_page; 1769 int ref_bfregs = req->total_num_bfregs; 1770 1771 if (req->total_num_bfregs == 0) 1772 return -EINVAL; 1773 1774 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1775 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1776 1777 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1778 return -ENOMEM; 1779 1780 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1781 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1782 /* This holds the required static allocation asked by the user */ 1783 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1784 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1785 return -EINVAL; 1786 1787 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1788 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1789 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1790 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1791 1792 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1793 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1794 lib_uar_4k ? "yes" : "no", ref_bfregs, 1795 req->total_num_bfregs, bfregi->total_num_bfregs, 1796 bfregi->num_sys_pages); 1797 1798 return 0; 1799 } 1800 1801 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1802 { 1803 struct mlx5_bfreg_info *bfregi; 1804 int err; 1805 int i; 1806 1807 bfregi = &context->bfregi; 1808 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1809 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1810 context->devx_uid); 1811 if (err) 1812 goto error; 1813 1814 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1815 } 1816 1817 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1818 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1819 1820 return 0; 1821 1822 error: 1823 for (--i; i >= 0; i--) 1824 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1825 context->devx_uid)) 1826 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1827 1828 return err; 1829 } 1830 1831 static void deallocate_uars(struct mlx5_ib_dev *dev, 1832 struct mlx5_ib_ucontext *context) 1833 { 1834 struct mlx5_bfreg_info *bfregi; 1835 int i; 1836 1837 bfregi = &context->bfregi; 1838 for (i = 0; i < bfregi->num_sys_pages; i++) 1839 if (i < bfregi->num_static_sys_pages || 1840 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1841 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1842 context->devx_uid); 1843 } 1844 1845 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1846 struct mlx5_core_dev *slave, 1847 struct mlx5_ib_lb_state *lb_state) 1848 { 1849 int err; 1850 1851 err = mlx5_nic_vport_update_local_lb(master, true); 1852 if (err) 1853 return err; 1854 1855 err = mlx5_nic_vport_update_local_lb(slave, true); 1856 if (err) 1857 goto out; 1858 1859 lb_state->force_enable = true; 1860 return 0; 1861 1862 out: 1863 mlx5_nic_vport_update_local_lb(master, false); 1864 return err; 1865 } 1866 1867 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 1868 struct mlx5_core_dev *slave, 1869 struct mlx5_ib_lb_state *lb_state) 1870 { 1871 mlx5_nic_vport_update_local_lb(slave, false); 1872 mlx5_nic_vport_update_local_lb(master, false); 1873 1874 lb_state->force_enable = false; 1875 } 1876 1877 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1878 { 1879 int err = 0; 1880 1881 if (dev->lb.force_enable) 1882 return 0; 1883 1884 mutex_lock(&dev->lb.mutex); 1885 if (td) 1886 dev->lb.user_td++; 1887 if (qp) 1888 dev->lb.qps++; 1889 1890 if (dev->lb.user_td == 2 || 1891 dev->lb.qps == 1) { 1892 if (!dev->lb.enabled) { 1893 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1894 dev->lb.enabled = true; 1895 } 1896 } 1897 1898 mutex_unlock(&dev->lb.mutex); 1899 1900 return err; 1901 } 1902 1903 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1904 { 1905 if (dev->lb.force_enable) 1906 return; 1907 1908 mutex_lock(&dev->lb.mutex); 1909 if (td) 1910 dev->lb.user_td--; 1911 if (qp) 1912 dev->lb.qps--; 1913 1914 if (dev->lb.user_td == 1 && 1915 dev->lb.qps == 0) { 1916 if (dev->lb.enabled) { 1917 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1918 dev->lb.enabled = false; 1919 } 1920 } 1921 1922 mutex_unlock(&dev->lb.mutex); 1923 } 1924 1925 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1926 u16 uid) 1927 { 1928 int err; 1929 1930 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1931 return 0; 1932 1933 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1934 if (err) 1935 return err; 1936 1937 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1938 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1939 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1940 return err; 1941 1942 return mlx5_ib_enable_lb(dev, true, false); 1943 } 1944 1945 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1946 u16 uid) 1947 { 1948 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1949 return; 1950 1951 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1952 1953 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1954 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1955 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1956 return; 1957 1958 mlx5_ib_disable_lb(dev, true, false); 1959 } 1960 1961 static int set_ucontext_resp(struct ib_ucontext *uctx, 1962 struct mlx5_ib_alloc_ucontext_resp *resp) 1963 { 1964 struct ib_device *ibdev = uctx->device; 1965 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1966 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1967 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1968 1969 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1970 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1971 resp->comp_mask |= 1972 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1973 } 1974 1975 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1976 if (mlx5_wc_support_get(dev->mdev)) 1977 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1978 log_bf_reg_size); 1979 resp->cache_line_size = cache_line_size(); 1980 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1981 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1982 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1983 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1984 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1985 resp->cqe_version = context->cqe_version; 1986 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1987 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1988 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1989 MLX5_CAP_GEN(dev->mdev, 1990 num_of_uars_per_page) : 1; 1991 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1992 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1993 resp->num_ports = dev->num_ports; 1994 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1995 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1996 1997 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1998 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1999 resp->eth_min_inline++; 2000 } 2001 2002 if (dev->mdev->clock_info) 2003 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2004 2005 /* 2006 * We don't want to expose information from the PCI bar that is located 2007 * after 4096 bytes, so if the arch only supports larger pages, let's 2008 * pretend we don't support reading the HCA's core clock. This is also 2009 * forced by mmap function. 2010 */ 2011 if (PAGE_SIZE <= 4096) { 2012 resp->comp_mask |= 2013 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2014 resp->hca_core_clock_offset = 2015 offsetof(struct mlx5_init_seg, 2016 internal_timer_h) % PAGE_SIZE; 2017 } 2018 2019 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2020 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2021 2022 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2023 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2024 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2025 resp->comp_mask |= 2026 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2027 2028 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2029 2030 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2031 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2032 2033 resp->comp_mask |= 2034 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2035 2036 return 0; 2037 } 2038 2039 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2040 { 2041 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2042 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2043 } 2044 2045 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2046 struct ib_udata *udata) 2047 { 2048 struct ib_device *ibdev = uctx->device; 2049 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2050 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 2051 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2052 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2053 struct mlx5_bfreg_info *bfregi; 2054 int ver; 2055 int err; 2056 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2057 max_cqe_version); 2058 bool lib_uar_4k; 2059 bool lib_uar_dyn; 2060 2061 if (!dev->ib_active) 2062 return -EAGAIN; 2063 2064 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2065 ver = 0; 2066 else if (udata->inlen >= min_req_v2) 2067 ver = 2; 2068 else 2069 return -EINVAL; 2070 2071 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2072 if (err) 2073 return err; 2074 2075 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2076 return -EOPNOTSUPP; 2077 2078 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2079 return -EOPNOTSUPP; 2080 2081 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2082 MLX5_NON_FP_BFREGS_PER_UAR); 2083 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2084 return -EINVAL; 2085 2086 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2087 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2088 if (err < 0) 2089 goto out_ctx; 2090 context->devx_uid = err; 2091 2092 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2093 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2094 context->devx_uid); 2095 if (err) 2096 goto out_devx; 2097 } 2098 } 2099 2100 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2101 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2102 bfregi = &context->bfregi; 2103 2104 if (lib_uar_dyn) { 2105 bfregi->lib_uar_dyn = lib_uar_dyn; 2106 goto uar_done; 2107 } 2108 2109 /* updates req->total_num_bfregs */ 2110 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2111 if (err) 2112 goto out_ucap; 2113 2114 mutex_init(&bfregi->lock); 2115 bfregi->lib_uar_4k = lib_uar_4k; 2116 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2117 GFP_KERNEL); 2118 if (!bfregi->count) { 2119 err = -ENOMEM; 2120 goto out_ucap; 2121 } 2122 2123 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2124 sizeof(*bfregi->sys_pages), 2125 GFP_KERNEL); 2126 if (!bfregi->sys_pages) { 2127 err = -ENOMEM; 2128 goto out_count; 2129 } 2130 2131 err = allocate_uars(dev, context); 2132 if (err) 2133 goto out_sys_pages; 2134 2135 uar_done: 2136 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2137 context->devx_uid); 2138 if (err) 2139 goto out_uars; 2140 2141 INIT_LIST_HEAD(&context->db_page_list); 2142 mutex_init(&context->db_page_mutex); 2143 2144 context->cqe_version = min_t(__u8, 2145 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2146 req.max_cqe_version); 2147 2148 err = set_ucontext_resp(uctx, &resp); 2149 if (err) 2150 goto out_mdev; 2151 2152 resp.response_length = min(udata->outlen, sizeof(resp)); 2153 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2154 if (err) 2155 goto out_mdev; 2156 2157 bfregi->ver = ver; 2158 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2159 context->lib_caps = req.lib_caps; 2160 print_lib_caps(dev, context->lib_caps); 2161 2162 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2163 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2164 2165 atomic_set(&context->tx_port_affinity, 2166 atomic_add_return( 2167 1, &dev->port[port].roce.tx_port_affinity)); 2168 } 2169 2170 return 0; 2171 2172 out_mdev: 2173 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2174 2175 out_uars: 2176 deallocate_uars(dev, context); 2177 2178 out_sys_pages: 2179 kfree(bfregi->sys_pages); 2180 2181 out_count: 2182 kfree(bfregi->count); 2183 2184 out_ucap: 2185 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2186 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2187 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2188 2189 out_devx: 2190 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2191 mlx5_ib_devx_destroy(dev, context->devx_uid); 2192 2193 out_ctx: 2194 return err; 2195 } 2196 2197 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2198 struct uverbs_attr_bundle *attrs) 2199 { 2200 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2201 int ret; 2202 2203 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2204 if (ret) 2205 return ret; 2206 2207 uctx_resp.response_length = 2208 min_t(size_t, 2209 uverbs_attr_get_len(attrs, 2210 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2211 sizeof(uctx_resp)); 2212 2213 ret = uverbs_copy_to_struct_or_zero(attrs, 2214 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2215 &uctx_resp, 2216 sizeof(uctx_resp)); 2217 return ret; 2218 } 2219 2220 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2221 { 2222 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2223 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2224 struct mlx5_bfreg_info *bfregi; 2225 2226 bfregi = &context->bfregi; 2227 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2228 2229 deallocate_uars(dev, context); 2230 kfree(bfregi->sys_pages); 2231 kfree(bfregi->count); 2232 2233 if (context->devx_uid) { 2234 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2235 mlx5_cmd_remove_privileged_uid(dev->mdev, 2236 context->devx_uid); 2237 mlx5_ib_devx_destroy(dev, context->devx_uid); 2238 } 2239 } 2240 2241 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2242 int uar_idx) 2243 { 2244 int fw_uars_per_page; 2245 2246 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2247 2248 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2249 } 2250 2251 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2252 int uar_idx) 2253 { 2254 unsigned int fw_uars_per_page; 2255 2256 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2257 MLX5_UARS_IN_PAGE : 1; 2258 2259 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2260 } 2261 2262 static int get_command(unsigned long offset) 2263 { 2264 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2265 } 2266 2267 static int get_arg(unsigned long offset) 2268 { 2269 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2270 } 2271 2272 static int get_index(unsigned long offset) 2273 { 2274 return get_arg(offset); 2275 } 2276 2277 /* Index resides in an extra byte to enable larger values than 255 */ 2278 static int get_extended_index(unsigned long offset) 2279 { 2280 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2281 } 2282 2283 2284 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2285 { 2286 } 2287 2288 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2289 { 2290 switch (cmd) { 2291 case MLX5_IB_MMAP_WC_PAGE: 2292 return "WC"; 2293 case MLX5_IB_MMAP_REGULAR_PAGE: 2294 return "best effort WC"; 2295 case MLX5_IB_MMAP_NC_PAGE: 2296 return "NC"; 2297 case MLX5_IB_MMAP_DEVICE_MEM: 2298 return "Device Memory"; 2299 default: 2300 return "Unknown"; 2301 } 2302 } 2303 2304 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2305 struct vm_area_struct *vma, 2306 struct mlx5_ib_ucontext *context) 2307 { 2308 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2309 !(vma->vm_flags & VM_SHARED)) 2310 return -EINVAL; 2311 2312 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2313 return -EOPNOTSUPP; 2314 2315 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2316 return -EPERM; 2317 vm_flags_clear(vma, VM_MAYWRITE); 2318 2319 if (!dev->mdev->clock_info) 2320 return -EOPNOTSUPP; 2321 2322 return vm_insert_page(vma, vma->vm_start, 2323 virt_to_page(dev->mdev->clock_info)); 2324 } 2325 2326 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2327 { 2328 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2329 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2330 struct mlx5_var_table *var_table = &dev->var_table; 2331 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2332 2333 switch (mentry->mmap_flag) { 2334 case MLX5_IB_MMAP_TYPE_MEMIC: 2335 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2336 mlx5_ib_dm_mmap_free(dev, mentry); 2337 break; 2338 case MLX5_IB_MMAP_TYPE_VAR: 2339 mutex_lock(&var_table->bitmap_lock); 2340 clear_bit(mentry->page_idx, var_table->bitmap); 2341 mutex_unlock(&var_table->bitmap_lock); 2342 kfree(mentry); 2343 break; 2344 case MLX5_IB_MMAP_TYPE_UAR_WC: 2345 case MLX5_IB_MMAP_TYPE_UAR_NC: 2346 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2347 context->devx_uid); 2348 kfree(mentry); 2349 break; 2350 default: 2351 WARN_ON(true); 2352 } 2353 } 2354 2355 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2356 struct vm_area_struct *vma, 2357 struct mlx5_ib_ucontext *context) 2358 { 2359 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2360 int err; 2361 unsigned long idx; 2362 phys_addr_t pfn; 2363 pgprot_t prot; 2364 u32 bfreg_dyn_idx = 0; 2365 u32 uar_index; 2366 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2367 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2368 bfregi->num_static_sys_pages; 2369 2370 if (bfregi->lib_uar_dyn) 2371 return -EINVAL; 2372 2373 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2374 return -EINVAL; 2375 2376 if (dyn_uar) 2377 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2378 else 2379 idx = get_index(vma->vm_pgoff); 2380 2381 if (idx >= max_valid_idx) { 2382 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2383 idx, max_valid_idx); 2384 return -EINVAL; 2385 } 2386 2387 switch (cmd) { 2388 case MLX5_IB_MMAP_WC_PAGE: 2389 case MLX5_IB_MMAP_ALLOC_WC: 2390 case MLX5_IB_MMAP_REGULAR_PAGE: 2391 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2392 prot = pgprot_writecombine(vma->vm_page_prot); 2393 break; 2394 case MLX5_IB_MMAP_NC_PAGE: 2395 prot = pgprot_noncached(vma->vm_page_prot); 2396 break; 2397 default: 2398 return -EINVAL; 2399 } 2400 2401 if (dyn_uar) { 2402 int uars_per_page; 2403 2404 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2405 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2406 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2407 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2408 bfreg_dyn_idx, bfregi->total_num_bfregs); 2409 return -EINVAL; 2410 } 2411 2412 mutex_lock(&bfregi->lock); 2413 /* Fail if uar already allocated, first bfreg index of each 2414 * page holds its count. 2415 */ 2416 if (bfregi->count[bfreg_dyn_idx]) { 2417 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2418 mutex_unlock(&bfregi->lock); 2419 return -EINVAL; 2420 } 2421 2422 bfregi->count[bfreg_dyn_idx]++; 2423 mutex_unlock(&bfregi->lock); 2424 2425 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2426 context->devx_uid); 2427 if (err) { 2428 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2429 goto free_bfreg; 2430 } 2431 } else { 2432 uar_index = bfregi->sys_pages[idx]; 2433 } 2434 2435 pfn = uar_index2pfn(dev, uar_index); 2436 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2437 2438 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2439 prot, NULL); 2440 if (err) { 2441 mlx5_ib_err(dev, 2442 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2443 err, mmap_cmd2str(cmd)); 2444 goto err; 2445 } 2446 2447 if (dyn_uar) 2448 bfregi->sys_pages[idx] = uar_index; 2449 return 0; 2450 2451 err: 2452 if (!dyn_uar) 2453 return err; 2454 2455 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2456 2457 free_bfreg: 2458 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2459 2460 return err; 2461 } 2462 2463 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2464 { 2465 unsigned long idx; 2466 u8 command; 2467 2468 command = get_command(vma->vm_pgoff); 2469 idx = get_extended_index(vma->vm_pgoff); 2470 2471 return (command << 16 | idx); 2472 } 2473 2474 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2475 struct vm_area_struct *vma, 2476 struct ib_ucontext *ucontext) 2477 { 2478 struct mlx5_user_mmap_entry *mentry; 2479 struct rdma_user_mmap_entry *entry; 2480 unsigned long pgoff; 2481 pgprot_t prot; 2482 phys_addr_t pfn; 2483 int ret; 2484 2485 pgoff = mlx5_vma_to_pgoff(vma); 2486 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2487 if (!entry) 2488 return -EINVAL; 2489 2490 mentry = to_mmmap(entry); 2491 pfn = (mentry->address >> PAGE_SHIFT); 2492 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2493 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2494 prot = pgprot_noncached(vma->vm_page_prot); 2495 else 2496 prot = pgprot_writecombine(vma->vm_page_prot); 2497 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2498 entry->npages * PAGE_SIZE, 2499 prot, 2500 entry); 2501 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2502 return ret; 2503 } 2504 2505 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2506 { 2507 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2508 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2509 2510 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2511 (index & 0xFF)) << PAGE_SHIFT; 2512 } 2513 2514 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2515 { 2516 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2517 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2518 unsigned long command; 2519 phys_addr_t pfn; 2520 2521 command = get_command(vma->vm_pgoff); 2522 switch (command) { 2523 case MLX5_IB_MMAP_WC_PAGE: 2524 case MLX5_IB_MMAP_ALLOC_WC: 2525 if (!mlx5_wc_support_get(dev->mdev)) 2526 return -EPERM; 2527 fallthrough; 2528 case MLX5_IB_MMAP_NC_PAGE: 2529 case MLX5_IB_MMAP_REGULAR_PAGE: 2530 return uar_mmap(dev, command, vma, context); 2531 2532 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2533 return -ENOSYS; 2534 2535 case MLX5_IB_MMAP_CORE_CLOCK: 2536 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2537 return -EINVAL; 2538 2539 if (vma->vm_flags & VM_WRITE) 2540 return -EPERM; 2541 vm_flags_clear(vma, VM_MAYWRITE); 2542 2543 /* Don't expose to user-space information it shouldn't have */ 2544 if (PAGE_SIZE > 4096) 2545 return -EOPNOTSUPP; 2546 2547 pfn = (dev->mdev->iseg_base + 2548 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2549 PAGE_SHIFT; 2550 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2551 PAGE_SIZE, 2552 pgprot_noncached(vma->vm_page_prot), 2553 NULL); 2554 case MLX5_IB_MMAP_CLOCK_INFO: 2555 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2556 2557 default: 2558 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2559 } 2560 2561 return 0; 2562 } 2563 2564 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2565 { 2566 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2567 struct ib_device *ibdev = ibpd->device; 2568 struct mlx5_ib_alloc_pd_resp resp; 2569 int err; 2570 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2571 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2572 u16 uid = 0; 2573 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2574 udata, struct mlx5_ib_ucontext, ibucontext); 2575 2576 uid = context ? context->devx_uid : 0; 2577 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2578 MLX5_SET(alloc_pd_in, in, uid, uid); 2579 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2580 if (err) 2581 return err; 2582 2583 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2584 pd->uid = uid; 2585 if (udata) { 2586 resp.pdn = pd->pdn; 2587 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2588 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2589 return -EFAULT; 2590 } 2591 } 2592 2593 return 0; 2594 } 2595 2596 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2597 { 2598 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2599 struct mlx5_ib_pd *mpd = to_mpd(pd); 2600 2601 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2602 } 2603 2604 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2605 { 2606 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2607 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2608 int err; 2609 u16 uid; 2610 2611 uid = ibqp->pd ? 2612 to_mpd(ibqp->pd)->uid : 0; 2613 2614 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2615 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2616 return -EOPNOTSUPP; 2617 } 2618 2619 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2620 if (err) 2621 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2622 ibqp->qp_num, gid->raw); 2623 2624 return err; 2625 } 2626 2627 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2628 { 2629 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2630 int err; 2631 u16 uid; 2632 2633 uid = ibqp->pd ? 2634 to_mpd(ibqp->pd)->uid : 0; 2635 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2636 if (err) 2637 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2638 ibqp->qp_num, gid->raw); 2639 2640 return err; 2641 } 2642 2643 static int init_node_data(struct mlx5_ib_dev *dev) 2644 { 2645 int err; 2646 2647 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2648 if (err) 2649 return err; 2650 2651 dev->mdev->rev_id = dev->mdev->pdev->revision; 2652 2653 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2654 } 2655 2656 static ssize_t fw_pages_show(struct device *device, 2657 struct device_attribute *attr, char *buf) 2658 { 2659 struct mlx5_ib_dev *dev = 2660 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2661 2662 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2663 } 2664 static DEVICE_ATTR_RO(fw_pages); 2665 2666 static ssize_t reg_pages_show(struct device *device, 2667 struct device_attribute *attr, char *buf) 2668 { 2669 struct mlx5_ib_dev *dev = 2670 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2671 2672 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2673 } 2674 static DEVICE_ATTR_RO(reg_pages); 2675 2676 static ssize_t hca_type_show(struct device *device, 2677 struct device_attribute *attr, char *buf) 2678 { 2679 struct mlx5_ib_dev *dev = 2680 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2681 2682 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2683 } 2684 static DEVICE_ATTR_RO(hca_type); 2685 2686 static ssize_t hw_rev_show(struct device *device, 2687 struct device_attribute *attr, char *buf) 2688 { 2689 struct mlx5_ib_dev *dev = 2690 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2691 2692 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2693 } 2694 static DEVICE_ATTR_RO(hw_rev); 2695 2696 static ssize_t board_id_show(struct device *device, 2697 struct device_attribute *attr, char *buf) 2698 { 2699 struct mlx5_ib_dev *dev = 2700 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2701 2702 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2703 dev->mdev->board_id); 2704 } 2705 static DEVICE_ATTR_RO(board_id); 2706 2707 static struct attribute *mlx5_class_attributes[] = { 2708 &dev_attr_hw_rev.attr, 2709 &dev_attr_hca_type.attr, 2710 &dev_attr_board_id.attr, 2711 &dev_attr_fw_pages.attr, 2712 &dev_attr_reg_pages.attr, 2713 NULL, 2714 }; 2715 2716 static const struct attribute_group mlx5_attr_group = { 2717 .attrs = mlx5_class_attributes, 2718 }; 2719 2720 static void pkey_change_handler(struct work_struct *work) 2721 { 2722 struct mlx5_ib_port_resources *ports = 2723 container_of(work, struct mlx5_ib_port_resources, 2724 pkey_change_work); 2725 2726 if (!ports->gsi) 2727 /* 2728 * We got this event before device was fully configured 2729 * and MAD registration code wasn't called/finished yet. 2730 */ 2731 return; 2732 2733 mlx5_ib_gsi_pkey_change(ports->gsi); 2734 } 2735 2736 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2737 { 2738 struct mlx5_ib_qp *mqp; 2739 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2740 struct mlx5_core_cq *mcq; 2741 struct list_head cq_armed_list; 2742 unsigned long flags_qp; 2743 unsigned long flags_cq; 2744 unsigned long flags; 2745 2746 INIT_LIST_HEAD(&cq_armed_list); 2747 2748 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2749 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2750 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2751 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2752 if (mqp->sq.tail != mqp->sq.head) { 2753 send_mcq = to_mcq(mqp->ibqp.send_cq); 2754 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2755 if (send_mcq->mcq.comp && 2756 mqp->ibqp.send_cq->comp_handler) { 2757 if (!send_mcq->mcq.reset_notify_added) { 2758 send_mcq->mcq.reset_notify_added = 1; 2759 list_add_tail(&send_mcq->mcq.reset_notify, 2760 &cq_armed_list); 2761 } 2762 } 2763 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2764 } 2765 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2766 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2767 /* no handling is needed for SRQ */ 2768 if (!mqp->ibqp.srq) { 2769 if (mqp->rq.tail != mqp->rq.head) { 2770 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2771 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2772 if (recv_mcq->mcq.comp && 2773 mqp->ibqp.recv_cq->comp_handler) { 2774 if (!recv_mcq->mcq.reset_notify_added) { 2775 recv_mcq->mcq.reset_notify_added = 1; 2776 list_add_tail(&recv_mcq->mcq.reset_notify, 2777 &cq_armed_list); 2778 } 2779 } 2780 spin_unlock_irqrestore(&recv_mcq->lock, 2781 flags_cq); 2782 } 2783 } 2784 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2785 } 2786 /*At that point all inflight post send were put to be executed as of we 2787 * lock/unlock above locks Now need to arm all involved CQs. 2788 */ 2789 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2790 mcq->comp(mcq, NULL); 2791 } 2792 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2793 } 2794 2795 static void delay_drop_handler(struct work_struct *work) 2796 { 2797 int err; 2798 struct mlx5_ib_delay_drop *delay_drop = 2799 container_of(work, struct mlx5_ib_delay_drop, 2800 delay_drop_work); 2801 2802 atomic_inc(&delay_drop->events_cnt); 2803 2804 mutex_lock(&delay_drop->lock); 2805 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2806 if (err) { 2807 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2808 delay_drop->timeout); 2809 delay_drop->activate = false; 2810 } 2811 mutex_unlock(&delay_drop->lock); 2812 } 2813 2814 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2815 struct ib_event *ibev) 2816 { 2817 u32 port = (eqe->data.port.port >> 4) & 0xf; 2818 2819 switch (eqe->sub_type) { 2820 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2821 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2822 IB_LINK_LAYER_ETHERNET) 2823 schedule_work(&ibdev->delay_drop.delay_drop_work); 2824 break; 2825 default: /* do nothing */ 2826 return; 2827 } 2828 } 2829 2830 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2831 struct ib_event *ibev) 2832 { 2833 u32 port = (eqe->data.port.port >> 4) & 0xf; 2834 2835 ibev->element.port_num = port; 2836 2837 switch (eqe->sub_type) { 2838 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2839 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2840 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2841 /* In RoCE, port up/down events are handled in 2842 * mlx5_netdev_event(). 2843 */ 2844 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2845 IB_LINK_LAYER_ETHERNET) 2846 return -EINVAL; 2847 2848 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2849 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2850 break; 2851 2852 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2853 ibev->event = IB_EVENT_LID_CHANGE; 2854 break; 2855 2856 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2857 ibev->event = IB_EVENT_PKEY_CHANGE; 2858 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2859 break; 2860 2861 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2862 ibev->event = IB_EVENT_GID_CHANGE; 2863 break; 2864 2865 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2866 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2867 break; 2868 default: 2869 return -EINVAL; 2870 } 2871 2872 return 0; 2873 } 2874 2875 static void mlx5_ib_handle_event(struct work_struct *_work) 2876 { 2877 struct mlx5_ib_event_work *work = 2878 container_of(_work, struct mlx5_ib_event_work, work); 2879 struct mlx5_ib_dev *ibdev; 2880 struct ib_event ibev; 2881 bool fatal = false; 2882 2883 if (work->is_slave) { 2884 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2885 if (!ibdev) 2886 goto out; 2887 } else { 2888 ibdev = work->dev; 2889 } 2890 2891 switch (work->event) { 2892 case MLX5_DEV_EVENT_SYS_ERROR: 2893 ibev.event = IB_EVENT_DEVICE_FATAL; 2894 mlx5_ib_handle_internal_error(ibdev); 2895 ibev.element.port_num = (u8)(unsigned long)work->param; 2896 fatal = true; 2897 break; 2898 case MLX5_EVENT_TYPE_PORT_CHANGE: 2899 if (handle_port_change(ibdev, work->param, &ibev)) 2900 goto out; 2901 break; 2902 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2903 handle_general_event(ibdev, work->param, &ibev); 2904 fallthrough; 2905 default: 2906 goto out; 2907 } 2908 2909 ibev.device = &ibdev->ib_dev; 2910 2911 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2912 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2913 goto out; 2914 } 2915 2916 if (ibdev->ib_active) 2917 ib_dispatch_event(&ibev); 2918 2919 if (fatal) 2920 ibdev->ib_active = false; 2921 out: 2922 kfree(work); 2923 } 2924 2925 static int mlx5_ib_event(struct notifier_block *nb, 2926 unsigned long event, void *param) 2927 { 2928 struct mlx5_ib_event_work *work; 2929 2930 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2931 if (!work) 2932 return NOTIFY_DONE; 2933 2934 INIT_WORK(&work->work, mlx5_ib_handle_event); 2935 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2936 work->is_slave = false; 2937 work->param = param; 2938 work->event = event; 2939 2940 queue_work(mlx5_ib_event_wq, &work->work); 2941 2942 return NOTIFY_OK; 2943 } 2944 2945 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2946 unsigned long event, void *param) 2947 { 2948 struct mlx5_ib_event_work *work; 2949 2950 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2951 if (!work) 2952 return NOTIFY_DONE; 2953 2954 INIT_WORK(&work->work, mlx5_ib_handle_event); 2955 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2956 work->is_slave = true; 2957 work->param = param; 2958 work->event = event; 2959 queue_work(mlx5_ib_event_wq, &work->work); 2960 2961 return NOTIFY_OK; 2962 } 2963 2964 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 2965 { 2966 struct mlx5_hca_vport_context vport_ctx; 2967 int err; 2968 2969 *num_plane = 0; 2970 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 2971 return 0; 2972 2973 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 2974 if (err) 2975 return err; 2976 2977 *num_plane = vport_ctx.num_plane; 2978 return 0; 2979 } 2980 2981 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2982 { 2983 struct mlx5_hca_vport_context vport_ctx; 2984 int err; 2985 int port; 2986 2987 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2988 return 0; 2989 2990 for (port = 1; port <= dev->num_ports; port++) { 2991 if (dev->num_plane) { 2992 dev->port_caps[port - 1].has_smi = false; 2993 continue; 2994 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 2995 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 2996 dev->port_caps[port - 1].has_smi = true; 2997 continue; 2998 } 2999 3000 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 3001 &vport_ctx); 3002 if (err) { 3003 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3004 port, err); 3005 return err; 3006 } 3007 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3008 } 3009 3010 return 0; 3011 } 3012 3013 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3014 { 3015 unsigned int port; 3016 3017 rdma_for_each_port (&dev->ib_dev, port) 3018 mlx5_query_ext_port_caps(dev, port); 3019 } 3020 3021 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3022 { 3023 switch (umr_fence_cap) { 3024 case MLX5_CAP_UMR_FENCE_NONE: 3025 return MLX5_FENCE_MODE_NONE; 3026 case MLX5_CAP_UMR_FENCE_SMALL: 3027 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3028 default: 3029 return MLX5_FENCE_MODE_STRONG_ORDERING; 3030 } 3031 } 3032 3033 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3034 { 3035 struct mlx5_ib_resources *devr = &dev->devr; 3036 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3037 struct ib_device *ibdev; 3038 struct ib_pd *pd; 3039 struct ib_cq *cq; 3040 int ret = 0; 3041 3042 3043 /* 3044 * devr->c0 is set once, never changed until device unload. 3045 * Avoid taking the mutex if initialization is already done. 3046 */ 3047 if (devr->c0) 3048 return 0; 3049 3050 mutex_lock(&devr->cq_lock); 3051 if (devr->c0) 3052 goto unlock; 3053 3054 ibdev = &dev->ib_dev; 3055 pd = ib_alloc_pd(ibdev, 0); 3056 if (IS_ERR(pd)) { 3057 ret = PTR_ERR(pd); 3058 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n", 3059 pd); 3060 goto unlock; 3061 } 3062 3063 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3064 if (IS_ERR(cq)) { 3065 ret = PTR_ERR(cq); 3066 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n", 3067 cq); 3068 ib_dealloc_pd(pd); 3069 goto unlock; 3070 } 3071 3072 devr->p0 = pd; 3073 devr->c0 = cq; 3074 3075 unlock: 3076 mutex_unlock(&devr->cq_lock); 3077 return ret; 3078 } 3079 3080 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3081 { 3082 struct mlx5_ib_resources *devr = &dev->devr; 3083 struct ib_srq_init_attr attr; 3084 struct ib_srq *s0, *s1; 3085 int ret = 0; 3086 3087 /* 3088 * devr->s1 is set once, never changed until device unload. 3089 * Avoid taking the mutex if initialization is already done. 3090 */ 3091 if (devr->s1) 3092 return 0; 3093 3094 mutex_lock(&devr->srq_lock); 3095 if (devr->s1) 3096 goto unlock; 3097 3098 ret = mlx5_ib_dev_res_cq_init(dev); 3099 if (ret) 3100 goto unlock; 3101 3102 memset(&attr, 0, sizeof(attr)); 3103 attr.attr.max_sge = 1; 3104 attr.attr.max_wr = 1; 3105 attr.srq_type = IB_SRQT_XRC; 3106 attr.ext.cq = devr->c0; 3107 3108 s0 = ib_create_srq(devr->p0, &attr); 3109 if (IS_ERR(s0)) { 3110 ret = PTR_ERR(s0); 3111 mlx5_ib_err(dev, 3112 "Couldn't create SRQ 0 for res init, err=%pe\n", 3113 s0); 3114 goto unlock; 3115 } 3116 3117 memset(&attr, 0, sizeof(attr)); 3118 attr.attr.max_sge = 1; 3119 attr.attr.max_wr = 1; 3120 attr.srq_type = IB_SRQT_BASIC; 3121 3122 s1 = ib_create_srq(devr->p0, &attr); 3123 if (IS_ERR(s1)) { 3124 ret = PTR_ERR(s1); 3125 mlx5_ib_err(dev, 3126 "Couldn't create SRQ 1 for res init, err=%pe\n", 3127 s1); 3128 ib_destroy_srq(s0); 3129 } 3130 3131 devr->s0 = s0; 3132 devr->s1 = s1; 3133 3134 unlock: 3135 mutex_unlock(&devr->srq_lock); 3136 return ret; 3137 } 3138 3139 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3140 { 3141 struct mlx5_ib_resources *devr = &dev->devr; 3142 int ret; 3143 3144 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3145 return -EOPNOTSUPP; 3146 3147 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3148 if (ret) 3149 return ret; 3150 3151 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3152 if (ret) { 3153 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3154 return ret; 3155 } 3156 3157 mutex_init(&devr->cq_lock); 3158 mutex_init(&devr->srq_lock); 3159 3160 return 0; 3161 } 3162 3163 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3164 { 3165 struct mlx5_ib_resources *devr = &dev->devr; 3166 3167 /* After s0/s1 init, they are not unset during the device lifetime. */ 3168 if (devr->s1) { 3169 ib_destroy_srq(devr->s1); 3170 ib_destroy_srq(devr->s0); 3171 } 3172 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3173 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3174 /* After p0/c0 init, they are not unset during the device lifetime. */ 3175 if (devr->c0) { 3176 ib_destroy_cq(devr->c0); 3177 ib_dealloc_pd(devr->p0); 3178 } 3179 mutex_destroy(&devr->cq_lock); 3180 mutex_destroy(&devr->srq_lock); 3181 } 3182 3183 static int 3184 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3185 { 3186 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3187 struct mlx5_core_dev *mdev = dev->mdev; 3188 bool ro_supp = false; 3189 void *mkc; 3190 u32 mkey; 3191 u32 pdn; 3192 u32 *in; 3193 int err; 3194 3195 err = mlx5_core_alloc_pd(mdev, &pdn); 3196 if (err) 3197 return err; 3198 3199 in = kvzalloc(inlen, GFP_KERNEL); 3200 if (!in) { 3201 err = -ENOMEM; 3202 goto err; 3203 } 3204 3205 MLX5_SET(create_mkey_in, in, data_direct, 1); 3206 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3207 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3208 MLX5_SET(mkc, mkc, lw, 1); 3209 MLX5_SET(mkc, mkc, lr, 1); 3210 MLX5_SET(mkc, mkc, rw, 1); 3211 MLX5_SET(mkc, mkc, rr, 1); 3212 MLX5_SET(mkc, mkc, a, 1); 3213 MLX5_SET(mkc, mkc, pd, pdn); 3214 MLX5_SET(mkc, mkc, length64, 1); 3215 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3216 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3217 if (err) 3218 goto err_mkey; 3219 3220 dev->ddr.mkey = mkey; 3221 dev->ddr.pdn = pdn; 3222 3223 /* create another mkey with RO support */ 3224 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { 3225 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 3226 ro_supp = true; 3227 } 3228 3229 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { 3230 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 3231 ro_supp = true; 3232 } 3233 3234 if (ro_supp) { 3235 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3236 /* RO is defined as best effort */ 3237 if (!err) { 3238 dev->ddr.mkey_ro = mkey; 3239 dev->ddr.mkey_ro_valid = true; 3240 } 3241 } 3242 3243 kvfree(in); 3244 return 0; 3245 3246 err_mkey: 3247 kvfree(in); 3248 err: 3249 mlx5_core_dealloc_pd(mdev, pdn); 3250 return err; 3251 } 3252 3253 static void 3254 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3255 { 3256 3257 if (dev->ddr.mkey_ro_valid) 3258 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro); 3259 3260 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3261 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3262 } 3263 3264 static u32 get_core_cap_flags(struct ib_device *ibdev, 3265 struct mlx5_hca_vport_context *rep) 3266 { 3267 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3269 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3270 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3271 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3272 u32 ret = 0; 3273 3274 if (rep->grh_required) 3275 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3276 3277 if (dev->num_plane) 3278 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3279 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3280 RDMA_CORE_CAP_AF_IB; 3281 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3282 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3283 3284 if (ll == IB_LINK_LAYER_INFINIBAND) 3285 return ret | RDMA_CORE_PORT_IBA_IB; 3286 3287 if (raw_support) 3288 ret |= RDMA_CORE_PORT_RAW_PACKET; 3289 3290 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3291 return ret; 3292 3293 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3294 return ret; 3295 3296 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3297 ret |= RDMA_CORE_PORT_IBA_ROCE; 3298 3299 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3300 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3301 3302 return ret; 3303 } 3304 3305 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3306 struct ib_port_immutable *immutable) 3307 { 3308 struct ib_port_attr attr; 3309 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3310 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3311 struct mlx5_hca_vport_context rep = {0}; 3312 int err; 3313 3314 err = ib_query_port(ibdev, port_num, &attr); 3315 if (err) 3316 return err; 3317 3318 if (ll == IB_LINK_LAYER_INFINIBAND) { 3319 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3320 port_num = smi_to_native_portnum(dev, port_num); 3321 3322 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3323 &rep); 3324 if (err) 3325 return err; 3326 } 3327 3328 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3329 immutable->gid_tbl_len = attr.gid_tbl_len; 3330 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3331 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3332 3333 return 0; 3334 } 3335 3336 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3337 struct ib_port_immutable *immutable) 3338 { 3339 struct ib_port_attr attr; 3340 int err; 3341 3342 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3343 3344 err = ib_query_port(ibdev, port_num, &attr); 3345 if (err) 3346 return err; 3347 3348 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3349 immutable->gid_tbl_len = attr.gid_tbl_len; 3350 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3351 3352 return 0; 3353 } 3354 3355 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3356 { 3357 struct mlx5_ib_dev *dev = 3358 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3359 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3360 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3361 fw_rev_sub(dev->mdev)); 3362 } 3363 3364 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3365 { 3366 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3367 lag_events); 3368 struct mlx5_core_dev *mdev = dev->mdev; 3369 struct ib_device *ibdev = &dev->ib_dev; 3370 struct net_device *old_ndev = NULL; 3371 struct mlx5_ib_port *port; 3372 struct net_device *ndev; 3373 u32 portnum = 0; 3374 int ret = 0; 3375 int i; 3376 3377 switch (event) { 3378 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3379 ndev = data; 3380 if (ndev) { 3381 if (!mlx5_lag_is_roce(mdev)) { 3382 // sriov lag 3383 for (i = 0; i < dev->num_ports; i++) { 3384 port = &dev->port[i]; 3385 if (port->rep && port->rep->vport == 3386 MLX5_VPORT_UPLINK) { 3387 portnum = i; 3388 break; 3389 } 3390 } 3391 } 3392 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3393 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3394 if (ret) 3395 goto out; 3396 3397 if (old_ndev) 3398 roce_del_all_netdev_gids(ibdev, portnum + 1, 3399 old_ndev); 3400 rdma_roce_rescan_port(ibdev, portnum + 1); 3401 } 3402 break; 3403 default: 3404 return NOTIFY_DONE; 3405 } 3406 3407 out: 3408 dev_put(old_ndev); 3409 return notifier_from_errno(ret); 3410 } 3411 3412 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3413 { 3414 dev->lag_events.notifier_call = lag_event; 3415 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3416 &dev->lag_events); 3417 } 3418 3419 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3420 { 3421 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3422 &dev->lag_events); 3423 } 3424 3425 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3426 { 3427 struct mlx5_core_dev *mdev = dev->mdev; 3428 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3429 MLX5_FLOW_NAMESPACE_LAG); 3430 struct mlx5_flow_table *ft; 3431 int err; 3432 3433 if (!ns || !mlx5_lag_is_active(mdev)) 3434 return 0; 3435 3436 err = mlx5_cmd_create_vport_lag(mdev); 3437 if (err) 3438 return err; 3439 3440 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3441 if (IS_ERR(ft)) { 3442 err = PTR_ERR(ft); 3443 goto err_destroy_vport_lag; 3444 } 3445 3446 mlx5e_lag_event_register(dev); 3447 dev->flow_db->lag_demux_ft = ft; 3448 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3449 dev->lag_active = true; 3450 return 0; 3451 3452 err_destroy_vport_lag: 3453 mlx5_cmd_destroy_vport_lag(mdev); 3454 return err; 3455 } 3456 3457 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3458 { 3459 struct mlx5_core_dev *mdev = dev->mdev; 3460 3461 if (dev->lag_active) { 3462 dev->lag_active = false; 3463 3464 mlx5e_lag_event_unregister(dev); 3465 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3466 dev->flow_db->lag_demux_ft = NULL; 3467 3468 mlx5_cmd_destroy_vport_lag(mdev); 3469 } 3470 } 3471 3472 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3473 struct net_device *netdev) 3474 { 3475 int err; 3476 3477 if (roce->tracking_netdev) 3478 return; 3479 roce->tracking_netdev = netdev; 3480 roce->nb.notifier_call = mlx5_netdev_event; 3481 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3482 WARN_ON(err); 3483 } 3484 3485 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3486 { 3487 if (!roce->tracking_netdev) 3488 return; 3489 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3490 &roce->nn); 3491 roce->tracking_netdev = NULL; 3492 } 3493 3494 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3495 unsigned long event, void *data) 3496 { 3497 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3498 struct net_device *netdev = data; 3499 3500 switch (event) { 3501 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3502 if (netdev) 3503 mlx5_netdev_notifier_register(roce, netdev); 3504 else 3505 mlx5_netdev_notifier_unregister(roce); 3506 break; 3507 default: 3508 return NOTIFY_DONE; 3509 } 3510 3511 return NOTIFY_OK; 3512 } 3513 3514 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3515 { 3516 struct mlx5_roce *roce = &dev->port[port_num].roce; 3517 3518 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3519 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3520 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3521 } 3522 3523 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3524 { 3525 struct mlx5_roce *roce = &dev->port[port_num].roce; 3526 3527 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3528 mlx5_netdev_notifier_unregister(roce); 3529 } 3530 3531 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3532 { 3533 int err; 3534 3535 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3536 err = mlx5_nic_vport_enable_roce(dev->mdev); 3537 if (err) 3538 return err; 3539 } 3540 3541 err = mlx5_eth_lag_init(dev); 3542 if (err) 3543 goto err_disable_roce; 3544 3545 return 0; 3546 3547 err_disable_roce: 3548 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3549 mlx5_nic_vport_disable_roce(dev->mdev); 3550 3551 return err; 3552 } 3553 3554 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3555 { 3556 mlx5_eth_lag_cleanup(dev); 3557 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3558 mlx5_nic_vport_disable_roce(dev->mdev); 3559 } 3560 3561 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3562 enum rdma_netdev_t type, 3563 struct rdma_netdev_alloc_params *params) 3564 { 3565 if (type != RDMA_NETDEV_IPOIB) 3566 return -EOPNOTSUPP; 3567 3568 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3569 } 3570 3571 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3572 size_t count, loff_t *pos) 3573 { 3574 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3575 char lbuf[20]; 3576 int len; 3577 3578 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3579 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3580 } 3581 3582 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3583 size_t count, loff_t *pos) 3584 { 3585 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3586 u32 timeout; 3587 u32 var; 3588 3589 if (kstrtouint_from_user(buf, count, 0, &var)) 3590 return -EFAULT; 3591 3592 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3593 1000); 3594 if (timeout != var) 3595 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3596 timeout); 3597 3598 delay_drop->timeout = timeout; 3599 3600 return count; 3601 } 3602 3603 static const struct file_operations fops_delay_drop_timeout = { 3604 .owner = THIS_MODULE, 3605 .open = simple_open, 3606 .write = delay_drop_timeout_write, 3607 .read = delay_drop_timeout_read, 3608 }; 3609 3610 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3611 struct mlx5_ib_multiport_info *mpi) 3612 { 3613 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3614 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3615 int comps; 3616 int err; 3617 int i; 3618 3619 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3620 3621 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3622 3623 mlx5_core_mp_event_replay(ibdev->mdev, 3624 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3625 NULL); 3626 mlx5_core_mp_event_replay(mpi->mdev, 3627 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3628 NULL); 3629 3630 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3631 3632 spin_lock(&port->mp.mpi_lock); 3633 if (!mpi->ibdev) { 3634 spin_unlock(&port->mp.mpi_lock); 3635 return; 3636 } 3637 3638 mpi->ibdev = NULL; 3639 3640 spin_unlock(&port->mp.mpi_lock); 3641 if (mpi->mdev_events.notifier_call) 3642 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3643 mpi->mdev_events.notifier_call = NULL; 3644 mlx5_mdev_netdev_untrack(ibdev, port_num); 3645 spin_lock(&port->mp.mpi_lock); 3646 3647 comps = mpi->mdev_refcnt; 3648 if (comps) { 3649 mpi->unaffiliate = true; 3650 init_completion(&mpi->unref_comp); 3651 spin_unlock(&port->mp.mpi_lock); 3652 3653 for (i = 0; i < comps; i++) 3654 wait_for_completion(&mpi->unref_comp); 3655 3656 spin_lock(&port->mp.mpi_lock); 3657 mpi->unaffiliate = false; 3658 } 3659 3660 port->mp.mpi = NULL; 3661 3662 spin_unlock(&port->mp.mpi_lock); 3663 3664 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3665 3666 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3667 /* Log an error, still needed to cleanup the pointers and add 3668 * it back to the list. 3669 */ 3670 if (err) 3671 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3672 port_num + 1); 3673 3674 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3675 } 3676 3677 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3678 struct mlx5_ib_multiport_info *mpi) 3679 { 3680 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3681 u64 key; 3682 int err; 3683 3684 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3685 3686 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3687 if (ibdev->port[port_num].mp.mpi) { 3688 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3689 port_num + 1); 3690 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3691 return false; 3692 } 3693 3694 ibdev->port[port_num].mp.mpi = mpi; 3695 mpi->ibdev = ibdev; 3696 mpi->mdev_events.notifier_call = NULL; 3697 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3698 3699 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3700 if (err) 3701 goto unbind; 3702 3703 mlx5_mdev_netdev_track(ibdev, port_num); 3704 3705 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3706 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3707 3708 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3709 3710 key = mpi->mdev->priv.adev_idx; 3711 mlx5_core_mp_event_replay(mpi->mdev, 3712 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3713 &key); 3714 mlx5_core_mp_event_replay(ibdev->mdev, 3715 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3716 &key); 3717 3718 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3719 if (err) 3720 goto unbind; 3721 3722 return true; 3723 3724 unbind: 3725 mlx5_ib_unbind_slave_port(ibdev, mpi); 3726 return false; 3727 } 3728 3729 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3730 { 3731 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3732 int ret; 3733 3734 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3735 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3736 return 0; 3737 3738 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3739 if (ret) 3740 return ret; 3741 3742 ret = mlx5_ib_create_data_direct_resources(dev); 3743 if (ret) 3744 return ret; 3745 3746 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3747 ret = mlx5_data_direct_ib_reg(dev, vuid); 3748 if (ret) 3749 mlx5_ib_free_data_direct_resources(dev); 3750 3751 return ret; 3752 } 3753 3754 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3755 { 3756 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3757 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3758 return; 3759 3760 mlx5_data_direct_ib_unreg(dev); 3761 mlx5_ib_free_data_direct_resources(dev); 3762 } 3763 3764 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3765 { 3766 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3767 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3768 port_num + 1); 3769 struct mlx5_ib_multiport_info *mpi; 3770 int err; 3771 u32 i; 3772 3773 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3774 return 0; 3775 3776 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3777 &dev->sys_image_guid); 3778 if (err) 3779 return err; 3780 3781 err = mlx5_nic_vport_enable_roce(dev->mdev); 3782 if (err) 3783 return err; 3784 3785 mutex_lock(&mlx5_ib_multiport_mutex); 3786 for (i = 0; i < dev->num_ports; i++) { 3787 bool bound = false; 3788 3789 /* build a stub multiport info struct for the native port. */ 3790 if (i == port_num) { 3791 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3792 if (!mpi) { 3793 mutex_unlock(&mlx5_ib_multiport_mutex); 3794 mlx5_nic_vport_disable_roce(dev->mdev); 3795 return -ENOMEM; 3796 } 3797 3798 mpi->is_master = true; 3799 mpi->mdev = dev->mdev; 3800 mpi->sys_image_guid = dev->sys_image_guid; 3801 dev->port[i].mp.mpi = mpi; 3802 mpi->ibdev = dev; 3803 mpi = NULL; 3804 continue; 3805 } 3806 3807 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3808 list) { 3809 if (dev->sys_image_guid == mpi->sys_image_guid && 3810 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 3811 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 3812 bound = mlx5_ib_bind_slave_port(dev, mpi); 3813 } 3814 3815 if (bound) { 3816 dev_dbg(mpi->mdev->device, 3817 "removing port from unaffiliated list.\n"); 3818 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3819 list_del(&mpi->list); 3820 break; 3821 } 3822 } 3823 if (!bound) 3824 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3825 i + 1); 3826 } 3827 3828 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3829 mutex_unlock(&mlx5_ib_multiport_mutex); 3830 return err; 3831 } 3832 3833 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3834 { 3835 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3836 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3837 port_num + 1); 3838 u32 i; 3839 3840 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3841 return; 3842 3843 mutex_lock(&mlx5_ib_multiport_mutex); 3844 for (i = 0; i < dev->num_ports; i++) { 3845 if (dev->port[i].mp.mpi) { 3846 /* Destroy the native port stub */ 3847 if (i == port_num) { 3848 kfree(dev->port[i].mp.mpi); 3849 dev->port[i].mp.mpi = NULL; 3850 } else { 3851 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3852 i + 1); 3853 list_add_tail(&dev->port[i].mp.mpi->list, 3854 &mlx5_ib_unaffiliated_port_list); 3855 mlx5_ib_unbind_slave_port(dev, 3856 dev->port[i].mp.mpi); 3857 } 3858 } 3859 } 3860 3861 mlx5_ib_dbg(dev, "removing from devlist\n"); 3862 list_del(&dev->ib_dev_list); 3863 mutex_unlock(&mlx5_ib_multiport_mutex); 3864 3865 mlx5_nic_vport_disable_roce(dev->mdev); 3866 } 3867 3868 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3869 enum rdma_remove_reason why, 3870 struct uverbs_attr_bundle *attrs) 3871 { 3872 struct mlx5_user_mmap_entry *obj = uobject->object; 3873 3874 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3875 return 0; 3876 } 3877 3878 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3879 struct mlx5_user_mmap_entry *entry, 3880 size_t length) 3881 { 3882 return rdma_user_mmap_entry_insert_range( 3883 &c->ibucontext, &entry->rdma_entry, length, 3884 (MLX5_IB_MMAP_OFFSET_START << 16), 3885 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3886 } 3887 3888 static struct mlx5_user_mmap_entry * 3889 alloc_var_entry(struct mlx5_ib_ucontext *c) 3890 { 3891 struct mlx5_user_mmap_entry *entry; 3892 struct mlx5_var_table *var_table; 3893 u32 page_idx; 3894 int err; 3895 3896 var_table = &to_mdev(c->ibucontext.device)->var_table; 3897 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3898 if (!entry) 3899 return ERR_PTR(-ENOMEM); 3900 3901 mutex_lock(&var_table->bitmap_lock); 3902 page_idx = find_first_zero_bit(var_table->bitmap, 3903 var_table->num_var_hw_entries); 3904 if (page_idx >= var_table->num_var_hw_entries) { 3905 err = -ENOSPC; 3906 mutex_unlock(&var_table->bitmap_lock); 3907 goto end; 3908 } 3909 3910 set_bit(page_idx, var_table->bitmap); 3911 mutex_unlock(&var_table->bitmap_lock); 3912 3913 entry->address = var_table->hw_start_addr + 3914 (page_idx * var_table->stride_size); 3915 entry->page_idx = page_idx; 3916 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3917 3918 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3919 var_table->stride_size); 3920 if (err) 3921 goto err_insert; 3922 3923 return entry; 3924 3925 err_insert: 3926 mutex_lock(&var_table->bitmap_lock); 3927 clear_bit(page_idx, var_table->bitmap); 3928 mutex_unlock(&var_table->bitmap_lock); 3929 end: 3930 kfree(entry); 3931 return ERR_PTR(err); 3932 } 3933 3934 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3935 struct uverbs_attr_bundle *attrs) 3936 { 3937 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3938 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3939 struct mlx5_ib_ucontext *c; 3940 struct mlx5_user_mmap_entry *entry; 3941 u64 mmap_offset; 3942 u32 length; 3943 int err; 3944 3945 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3946 if (IS_ERR(c)) 3947 return PTR_ERR(c); 3948 3949 entry = alloc_var_entry(c); 3950 if (IS_ERR(entry)) 3951 return PTR_ERR(entry); 3952 3953 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3954 length = entry->rdma_entry.npages * PAGE_SIZE; 3955 uobj->object = entry; 3956 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3957 3958 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3959 &mmap_offset, sizeof(mmap_offset)); 3960 if (err) 3961 return err; 3962 3963 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3964 &entry->page_idx, sizeof(entry->page_idx)); 3965 if (err) 3966 return err; 3967 3968 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3969 &length, sizeof(length)); 3970 return err; 3971 } 3972 3973 DECLARE_UVERBS_NAMED_METHOD( 3974 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3975 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3976 MLX5_IB_OBJECT_VAR, 3977 UVERBS_ACCESS_NEW, 3978 UA_MANDATORY), 3979 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3980 UVERBS_ATTR_TYPE(u32), 3981 UA_MANDATORY), 3982 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3983 UVERBS_ATTR_TYPE(u32), 3984 UA_MANDATORY), 3985 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3986 UVERBS_ATTR_TYPE(u64), 3987 UA_MANDATORY)); 3988 3989 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3990 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3991 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3992 MLX5_IB_OBJECT_VAR, 3993 UVERBS_ACCESS_DESTROY, 3994 UA_MANDATORY)); 3995 3996 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3997 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3998 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3999 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 4000 4001 static bool var_is_supported(struct ib_device *device) 4002 { 4003 struct mlx5_ib_dev *dev = to_mdev(device); 4004 4005 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4006 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 4007 } 4008 4009 static struct mlx5_user_mmap_entry * 4010 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4011 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4012 { 4013 struct mlx5_user_mmap_entry *entry; 4014 struct mlx5_ib_dev *dev; 4015 u32 uar_index; 4016 int err; 4017 4018 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 4019 if (!entry) 4020 return ERR_PTR(-ENOMEM); 4021 4022 dev = to_mdev(c->ibucontext.device); 4023 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4024 if (err) 4025 goto end; 4026 4027 entry->page_idx = uar_index; 4028 entry->address = uar_index2paddress(dev, uar_index); 4029 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4030 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4031 else 4032 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4033 4034 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4035 if (err) 4036 goto err_insert; 4037 4038 return entry; 4039 4040 err_insert: 4041 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4042 end: 4043 kfree(entry); 4044 return ERR_PTR(err); 4045 } 4046 4047 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4048 struct uverbs_attr_bundle *attrs) 4049 { 4050 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4051 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4052 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4053 struct mlx5_ib_ucontext *c; 4054 struct mlx5_user_mmap_entry *entry; 4055 u64 mmap_offset; 4056 u32 length; 4057 int err; 4058 4059 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4060 if (IS_ERR(c)) 4061 return PTR_ERR(c); 4062 4063 err = uverbs_get_const(&alloc_type, attrs, 4064 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4065 if (err) 4066 return err; 4067 4068 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4069 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4070 return -EOPNOTSUPP; 4071 4072 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4073 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4074 return -EOPNOTSUPP; 4075 4076 entry = alloc_uar_entry(c, alloc_type); 4077 if (IS_ERR(entry)) 4078 return PTR_ERR(entry); 4079 4080 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4081 length = entry->rdma_entry.npages * PAGE_SIZE; 4082 uobj->object = entry; 4083 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4084 4085 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4086 &mmap_offset, sizeof(mmap_offset)); 4087 if (err) 4088 return err; 4089 4090 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4091 &entry->page_idx, sizeof(entry->page_idx)); 4092 if (err) 4093 return err; 4094 4095 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4096 &length, sizeof(length)); 4097 return err; 4098 } 4099 4100 DECLARE_UVERBS_NAMED_METHOD( 4101 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4102 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4103 MLX5_IB_OBJECT_UAR, 4104 UVERBS_ACCESS_NEW, 4105 UA_MANDATORY), 4106 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4107 enum mlx5_ib_uapi_uar_alloc_type, 4108 UA_MANDATORY), 4109 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4110 UVERBS_ATTR_TYPE(u32), 4111 UA_MANDATORY), 4112 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4113 UVERBS_ATTR_TYPE(u32), 4114 UA_MANDATORY), 4115 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4116 UVERBS_ATTR_TYPE(u64), 4117 UA_MANDATORY)); 4118 4119 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4120 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4121 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4122 MLX5_IB_OBJECT_UAR, 4123 UVERBS_ACCESS_DESTROY, 4124 UA_MANDATORY)); 4125 4126 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4127 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4128 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4129 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4130 4131 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4132 mlx5_ib_query_context, 4133 UVERBS_OBJECT_DEVICE, 4134 UVERBS_METHOD_QUERY_CONTEXT, 4135 UVERBS_ATTR_PTR_OUT( 4136 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4137 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4138 dump_fill_mkey), 4139 UA_MANDATORY)); 4140 4141 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4142 mlx5_ib_reg_dmabuf_mr, 4143 UVERBS_OBJECT_MR, 4144 UVERBS_METHOD_REG_DMABUF_MR, 4145 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4146 enum mlx5_ib_uapi_reg_dmabuf_flags, 4147 UA_OPTIONAL)); 4148 4149 static const struct uapi_definition mlx5_ib_defs[] = { 4150 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4151 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4152 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4153 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4154 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4155 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4156 4157 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4158 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4159 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4160 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4161 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4162 {} 4163 }; 4164 4165 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4166 { 4167 mlx5_ib_data_direct_cleanup(dev); 4168 mlx5_ib_cleanup_multiport_master(dev); 4169 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4170 mutex_destroy(&dev->cap_mask_mutex); 4171 WARN_ON(!xa_empty(&dev->sig_mrs)); 4172 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4173 mlx5r_macsec_dealloc_gids(dev); 4174 } 4175 4176 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4177 { 4178 struct mlx5_core_dev *mdev = dev->mdev; 4179 int err, i; 4180 4181 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4182 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4183 dev->ib_dev.dev.parent = mdev->device; 4184 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4185 4186 for (i = 0; i < dev->num_ports; i++) { 4187 spin_lock_init(&dev->port[i].mp.mpi_lock); 4188 dev->port[i].roce.dev = dev; 4189 dev->port[i].roce.native_port_num = i + 1; 4190 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4191 } 4192 4193 err = mlx5r_cmd_query_special_mkeys(dev); 4194 if (err) 4195 return err; 4196 4197 err = mlx5r_macsec_init_gids_and_devlist(dev); 4198 if (err) 4199 return err; 4200 4201 err = mlx5_ib_init_multiport_master(dev); 4202 if (err) 4203 goto err; 4204 4205 err = set_has_smi_cap(dev); 4206 if (err) 4207 goto err_mp; 4208 4209 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4210 if (err) 4211 goto err_mp; 4212 4213 if (mlx5_use_mad_ifc(dev)) 4214 get_ext_port_caps(dev); 4215 4216 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4217 4218 mutex_init(&dev->cap_mask_mutex); 4219 mutex_init(&dev->data_direct_lock); 4220 INIT_LIST_HEAD(&dev->qp_list); 4221 spin_lock_init(&dev->reset_flow_resource_lock); 4222 xa_init(&dev->odp_mkeys); 4223 xa_init(&dev->sig_mrs); 4224 atomic_set(&dev->mkey_var, 0); 4225 4226 spin_lock_init(&dev->dm.lock); 4227 dev->dm.dev = mdev; 4228 err = mlx5_ib_data_direct_init(dev); 4229 if (err) 4230 goto err_mp; 4231 4232 return 0; 4233 err_mp: 4234 mlx5_ib_cleanup_multiport_master(dev); 4235 err: 4236 mlx5r_macsec_dealloc_gids(dev); 4237 return err; 4238 } 4239 4240 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4241 enum rdma_nl_dev_type type, 4242 const char *name); 4243 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4244 4245 static const struct ib_device_ops mlx5_ib_dev_ops = { 4246 .owner = THIS_MODULE, 4247 .driver_id = RDMA_DRIVER_MLX5, 4248 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4249 4250 .add_gid = mlx5_ib_add_gid, 4251 .add_sub_dev = mlx5_ib_add_sub_dev, 4252 .alloc_mr = mlx5_ib_alloc_mr, 4253 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4254 .alloc_pd = mlx5_ib_alloc_pd, 4255 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4256 .attach_mcast = mlx5_ib_mcg_attach, 4257 .check_mr_status = mlx5_ib_check_mr_status, 4258 .create_ah = mlx5_ib_create_ah, 4259 .create_cq = mlx5_ib_create_cq, 4260 .create_qp = mlx5_ib_create_qp, 4261 .create_srq = mlx5_ib_create_srq, 4262 .create_user_ah = mlx5_ib_create_ah, 4263 .dealloc_pd = mlx5_ib_dealloc_pd, 4264 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4265 .del_gid = mlx5_ib_del_gid, 4266 .del_sub_dev = mlx5_ib_del_sub_dev, 4267 .dereg_mr = mlx5_ib_dereg_mr, 4268 .destroy_ah = mlx5_ib_destroy_ah, 4269 .destroy_cq = mlx5_ib_destroy_cq, 4270 .destroy_qp = mlx5_ib_destroy_qp, 4271 .destroy_srq = mlx5_ib_destroy_srq, 4272 .detach_mcast = mlx5_ib_mcg_detach, 4273 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4274 .drain_rq = mlx5_ib_drain_rq, 4275 .drain_sq = mlx5_ib_drain_sq, 4276 .device_group = &mlx5_attr_group, 4277 .get_dev_fw_str = get_dev_fw_str, 4278 .get_dma_mr = mlx5_ib_get_dma_mr, 4279 .get_link_layer = mlx5_ib_port_link_layer, 4280 .map_mr_sg = mlx5_ib_map_mr_sg, 4281 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4282 .mmap = mlx5_ib_mmap, 4283 .mmap_free = mlx5_ib_mmap_free, 4284 .modify_cq = mlx5_ib_modify_cq, 4285 .modify_device = mlx5_ib_modify_device, 4286 .modify_port = mlx5_ib_modify_port, 4287 .modify_qp = mlx5_ib_modify_qp, 4288 .modify_srq = mlx5_ib_modify_srq, 4289 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4290 .poll_cq = mlx5_ib_poll_cq, 4291 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4292 .post_recv = mlx5_ib_post_recv_nodrain, 4293 .post_send = mlx5_ib_post_send_nodrain, 4294 .post_srq_recv = mlx5_ib_post_srq_recv, 4295 .process_mad = mlx5_ib_process_mad, 4296 .query_ah = mlx5_ib_query_ah, 4297 .query_device = mlx5_ib_query_device, 4298 .query_gid = mlx5_ib_query_gid, 4299 .query_pkey = mlx5_ib_query_pkey, 4300 .query_qp = mlx5_ib_query_qp, 4301 .query_srq = mlx5_ib_query_srq, 4302 .query_ucontext = mlx5_ib_query_ucontext, 4303 .reg_user_mr = mlx5_ib_reg_user_mr, 4304 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4305 .req_notify_cq = mlx5_ib_arm_cq, 4306 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4307 .resize_cq = mlx5_ib_resize_cq, 4308 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4309 4310 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4311 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4312 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4313 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4314 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4315 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4316 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4317 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4318 }; 4319 4320 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4321 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4322 }; 4323 4324 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4325 .get_vf_config = mlx5_ib_get_vf_config, 4326 .get_vf_guid = mlx5_ib_get_vf_guid, 4327 .get_vf_stats = mlx5_ib_get_vf_stats, 4328 .set_vf_guid = mlx5_ib_set_vf_guid, 4329 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4330 }; 4331 4332 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4333 .alloc_mw = mlx5_ib_alloc_mw, 4334 .dealloc_mw = mlx5_ib_dealloc_mw, 4335 4336 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4337 }; 4338 4339 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4340 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4341 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4342 4343 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4344 }; 4345 4346 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4347 { 4348 struct mlx5_core_dev *mdev = dev->mdev; 4349 struct mlx5_var_table *var_table = &dev->var_table; 4350 u8 log_doorbell_bar_size; 4351 u8 log_doorbell_stride; 4352 u64 bar_size; 4353 4354 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4355 log_doorbell_bar_size); 4356 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4357 log_doorbell_stride); 4358 var_table->hw_start_addr = dev->mdev->bar_addr + 4359 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4360 doorbell_bar_offset); 4361 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4362 var_table->stride_size = 1ULL << log_doorbell_stride; 4363 var_table->num_var_hw_entries = div_u64(bar_size, 4364 var_table->stride_size); 4365 mutex_init(&var_table->bitmap_lock); 4366 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4367 GFP_KERNEL); 4368 return (var_table->bitmap) ? 0 : -ENOMEM; 4369 } 4370 4371 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4372 { 4373 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4374 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4375 4376 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4377 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4378 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4379 } 4380 4381 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4382 { 4383 int ret; 4384 4385 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4386 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4387 if (ret) 4388 return ret; 4389 } 4390 4391 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4392 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4393 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4394 if (ret) 4395 goto remove_local; 4396 } 4397 4398 return 0; 4399 4400 remove_local: 4401 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4402 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4403 return ret; 4404 } 4405 4406 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4407 { 4408 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4409 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4410 mlx5_ib_cleanup_ucaps(dev); 4411 4412 bitmap_free(dev->var_table.bitmap); 4413 } 4414 4415 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4416 { 4417 struct mlx5_core_dev *mdev = dev->mdev; 4418 int err; 4419 4420 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4421 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4422 ib_set_device_ops(&dev->ib_dev, 4423 &mlx5_ib_dev_ipoib_enhanced_ops); 4424 4425 if (mlx5_core_is_pf(mdev)) 4426 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4427 4428 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4429 4430 if (MLX5_CAP_GEN(mdev, imaicl)) 4431 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4432 4433 if (MLX5_CAP_GEN(mdev, xrc)) 4434 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4435 4436 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4437 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4438 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4439 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4440 4441 if (mdev->st) 4442 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4443 4444 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4445 4446 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4447 dev->ib_dev.driver_def = mlx5_ib_defs; 4448 4449 err = init_node_data(dev); 4450 if (err) 4451 return err; 4452 4453 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4454 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4455 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4456 mutex_init(&dev->lb.mutex); 4457 4458 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4459 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4460 err = mlx5_ib_init_var_table(dev); 4461 if (err) 4462 return err; 4463 } 4464 4465 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4466 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4467 err = mlx5_ib_init_ucaps(dev); 4468 if (err) 4469 return err; 4470 } 4471 4472 dev->ib_dev.use_cq_dim = true; 4473 4474 return 0; 4475 } 4476 4477 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4478 .get_port_immutable = mlx5_port_immutable, 4479 .query_port = mlx5_ib_query_port, 4480 }; 4481 4482 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4483 { 4484 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4485 return 0; 4486 } 4487 4488 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4489 .get_port_immutable = mlx5_port_rep_immutable, 4490 .query_port = mlx5_ib_rep_query_port, 4491 .query_pkey = mlx5_ib_rep_query_pkey, 4492 }; 4493 4494 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4495 { 4496 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4497 return 0; 4498 } 4499 4500 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4501 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4502 .create_wq = mlx5_ib_create_wq, 4503 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4504 .destroy_wq = mlx5_ib_destroy_wq, 4505 .modify_wq = mlx5_ib_modify_wq, 4506 4507 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4508 ib_rwq_ind_tbl), 4509 }; 4510 4511 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4512 { 4513 struct mlx5_core_dev *mdev = dev->mdev; 4514 enum rdma_link_layer ll; 4515 int port_type_cap; 4516 u32 port_num = 0; 4517 int err; 4518 4519 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4520 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4521 4522 if (ll == IB_LINK_LAYER_ETHERNET) { 4523 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4524 4525 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4526 4527 /* Register only for native ports */ 4528 mlx5_mdev_netdev_track(dev, port_num); 4529 4530 err = mlx5_enable_eth(dev); 4531 if (err) 4532 goto cleanup; 4533 } 4534 4535 return 0; 4536 cleanup: 4537 mlx5_mdev_netdev_untrack(dev, port_num); 4538 return err; 4539 } 4540 4541 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4542 { 4543 struct mlx5_core_dev *mdev = dev->mdev; 4544 enum rdma_link_layer ll; 4545 int port_type_cap; 4546 u32 port_num; 4547 4548 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4549 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4550 4551 if (ll == IB_LINK_LAYER_ETHERNET) { 4552 mlx5_disable_eth(dev); 4553 4554 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4555 mlx5_mdev_netdev_untrack(dev, port_num); 4556 } 4557 } 4558 4559 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4560 { 4561 mlx5_ib_init_cong_debugfs(dev, 4562 mlx5_core_native_port_num(dev->mdev) - 1); 4563 return 0; 4564 } 4565 4566 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4567 { 4568 mlx5_ib_cleanup_cong_debugfs(dev, 4569 mlx5_core_native_port_num(dev->mdev) - 1); 4570 } 4571 4572 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4573 { 4574 int err; 4575 4576 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4577 if (err) 4578 return err; 4579 4580 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4581 if (err) 4582 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4583 4584 return err; 4585 } 4586 4587 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4588 { 4589 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4590 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4591 } 4592 4593 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4594 { 4595 const char *name; 4596 4597 if (dev->sub_dev_name) { 4598 name = dev->sub_dev_name; 4599 ib_mark_name_assigned_by_user(&dev->ib_dev); 4600 } else if (!mlx5_lag_is_active(dev->mdev)) 4601 name = "mlx5_%d"; 4602 else 4603 name = "mlx5_bond_%d"; 4604 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4605 } 4606 4607 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4608 { 4609 mlx5_mkey_cache_cleanup(dev); 4610 mlx5r_umr_resource_cleanup(dev); 4611 mlx5r_umr_cleanup(dev); 4612 } 4613 4614 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4615 { 4616 ib_unregister_device(&dev->ib_dev); 4617 } 4618 4619 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4620 { 4621 int ret; 4622 4623 ret = mlx5r_umr_init(dev); 4624 if (ret) 4625 return ret; 4626 4627 ret = mlx5_mkey_cache_init(dev); 4628 if (ret) 4629 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4630 return ret; 4631 } 4632 4633 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4634 { 4635 struct dentry *root; 4636 4637 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4638 return 0; 4639 4640 mutex_init(&dev->delay_drop.lock); 4641 dev->delay_drop.dev = dev; 4642 dev->delay_drop.activate = false; 4643 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4644 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4645 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4646 atomic_set(&dev->delay_drop.events_cnt, 0); 4647 4648 if (!mlx5_debugfs_root) 4649 return 0; 4650 4651 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4652 dev->delay_drop.dir_debugfs = root; 4653 4654 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4655 &dev->delay_drop.events_cnt); 4656 debugfs_create_atomic_t("num_rqs", 0400, root, 4657 &dev->delay_drop.rqs_cnt); 4658 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4659 &fops_delay_drop_timeout); 4660 return 0; 4661 } 4662 4663 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4664 { 4665 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4666 return; 4667 4668 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4669 if (!dev->delay_drop.dir_debugfs) 4670 return; 4671 4672 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4673 dev->delay_drop.dir_debugfs = NULL; 4674 } 4675 4676 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4677 { 4678 struct mlx5_ib_resources *devr = &dev->devr; 4679 int port; 4680 4681 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4682 INIT_WORK(&devr->ports[port].pkey_change_work, 4683 pkey_change_handler); 4684 4685 dev->mdev_events.notifier_call = mlx5_ib_event; 4686 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4687 4688 mlx5r_macsec_event_register(dev); 4689 4690 return 0; 4691 } 4692 4693 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4694 { 4695 struct mlx5_ib_resources *devr = &dev->devr; 4696 int port; 4697 4698 mlx5r_macsec_event_unregister(dev); 4699 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4700 4701 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4702 cancel_work_sync(&devr->ports[port].pkey_change_work); 4703 } 4704 4705 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4706 struct mlx5_data_direct_dev *dev) 4707 { 4708 mutex_lock(&ibdev->data_direct_lock); 4709 ibdev->data_direct_dev = dev; 4710 mutex_unlock(&ibdev->data_direct_lock); 4711 } 4712 4713 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4714 { 4715 mutex_lock(&ibdev->data_direct_lock); 4716 mlx5_ib_revoke_data_direct_mrs(ibdev); 4717 ibdev->data_direct_dev = NULL; 4718 mutex_unlock(&ibdev->data_direct_lock); 4719 } 4720 4721 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4722 const struct mlx5_ib_profile *profile, 4723 int stage) 4724 { 4725 dev->ib_active = false; 4726 4727 /* Number of stages to cleanup */ 4728 while (stage) { 4729 stage--; 4730 if (profile->stage[stage].cleanup) 4731 profile->stage[stage].cleanup(dev); 4732 } 4733 4734 kfree(dev->port); 4735 ib_dealloc_device(&dev->ib_dev); 4736 } 4737 4738 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4739 const struct mlx5_ib_profile *profile) 4740 { 4741 int err; 4742 int i; 4743 4744 dev->profile = profile; 4745 4746 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4747 if (profile->stage[i].init) { 4748 err = profile->stage[i].init(dev); 4749 if (err) 4750 goto err_out; 4751 } 4752 } 4753 4754 dev->ib_active = true; 4755 return 0; 4756 4757 err_out: 4758 /* Clean up stages which were initialized */ 4759 while (i) { 4760 i--; 4761 if (profile->stage[i].cleanup) 4762 profile->stage[i].cleanup(dev); 4763 } 4764 return -ENOMEM; 4765 } 4766 4767 static const struct mlx5_ib_profile pf_profile = { 4768 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4769 mlx5_ib_stage_init_init, 4770 mlx5_ib_stage_init_cleanup), 4771 STAGE_CREATE(MLX5_IB_STAGE_FS, 4772 mlx5_ib_fs_init, 4773 mlx5_ib_fs_cleanup), 4774 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4775 mlx5_ib_stage_caps_init, 4776 mlx5_ib_stage_caps_cleanup), 4777 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4778 mlx5_ib_stage_non_default_cb, 4779 NULL), 4780 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4781 mlx5_ib_roce_init, 4782 mlx5_ib_roce_cleanup), 4783 STAGE_CREATE(MLX5_IB_STAGE_QP, 4784 mlx5_init_qp_table, 4785 mlx5_cleanup_qp_table), 4786 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4787 mlx5_init_srq_table, 4788 mlx5_cleanup_srq_table), 4789 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4790 mlx5_ib_dev_res_init, 4791 mlx5_ib_dev_res_cleanup), 4792 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4793 mlx5_ib_odp_init_one, 4794 mlx5_ib_odp_cleanup_one), 4795 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4796 mlx5_ib_counters_init, 4797 mlx5_ib_counters_cleanup), 4798 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4799 mlx5_ib_stage_cong_debugfs_init, 4800 mlx5_ib_stage_cong_debugfs_cleanup), 4801 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4802 mlx5_ib_stage_bfrag_init, 4803 mlx5_ib_stage_bfrag_cleanup), 4804 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4805 NULL, 4806 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4807 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4808 mlx5_ib_devx_init, 4809 mlx5_ib_devx_cleanup), 4810 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4811 mlx5_ib_stage_ib_reg_init, 4812 mlx5_ib_stage_ib_reg_cleanup), 4813 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4814 mlx5_ib_stage_dev_notifier_init, 4815 mlx5_ib_stage_dev_notifier_cleanup), 4816 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4817 mlx5_ib_stage_post_ib_reg_umr_init, 4818 NULL), 4819 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4820 mlx5_ib_stage_delay_drop_init, 4821 mlx5_ib_stage_delay_drop_cleanup), 4822 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4823 mlx5_ib_restrack_init, 4824 NULL), 4825 }; 4826 4827 const struct mlx5_ib_profile raw_eth_profile = { 4828 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4829 mlx5_ib_stage_init_init, 4830 mlx5_ib_stage_init_cleanup), 4831 STAGE_CREATE(MLX5_IB_STAGE_FS, 4832 mlx5_ib_fs_init, 4833 mlx5_ib_fs_cleanup), 4834 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4835 mlx5_ib_stage_caps_init, 4836 mlx5_ib_stage_caps_cleanup), 4837 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4838 mlx5_ib_stage_raw_eth_non_default_cb, 4839 NULL), 4840 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4841 mlx5_ib_roce_init, 4842 mlx5_ib_roce_cleanup), 4843 STAGE_CREATE(MLX5_IB_STAGE_QP, 4844 mlx5_init_qp_table, 4845 mlx5_cleanup_qp_table), 4846 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4847 mlx5_init_srq_table, 4848 mlx5_cleanup_srq_table), 4849 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4850 mlx5_ib_dev_res_init, 4851 mlx5_ib_dev_res_cleanup), 4852 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4853 mlx5_ib_counters_init, 4854 mlx5_ib_counters_cleanup), 4855 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4856 mlx5_ib_stage_cong_debugfs_init, 4857 mlx5_ib_stage_cong_debugfs_cleanup), 4858 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4859 mlx5_ib_stage_bfrag_init, 4860 mlx5_ib_stage_bfrag_cleanup), 4861 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4862 NULL, 4863 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4864 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4865 mlx5_ib_devx_init, 4866 mlx5_ib_devx_cleanup), 4867 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4868 mlx5_ib_stage_ib_reg_init, 4869 mlx5_ib_stage_ib_reg_cleanup), 4870 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4871 mlx5_ib_stage_dev_notifier_init, 4872 mlx5_ib_stage_dev_notifier_cleanup), 4873 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4874 mlx5_ib_stage_post_ib_reg_umr_init, 4875 NULL), 4876 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4877 mlx5_ib_stage_delay_drop_init, 4878 mlx5_ib_stage_delay_drop_cleanup), 4879 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4880 mlx5_ib_restrack_init, 4881 NULL), 4882 }; 4883 4884 static const struct mlx5_ib_profile plane_profile = { 4885 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4886 mlx5_ib_stage_init_init, 4887 mlx5_ib_stage_init_cleanup), 4888 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4889 mlx5_ib_stage_caps_init, 4890 mlx5_ib_stage_caps_cleanup), 4891 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4892 mlx5_ib_stage_non_default_cb, 4893 NULL), 4894 STAGE_CREATE(MLX5_IB_STAGE_QP, 4895 mlx5_init_qp_table, 4896 mlx5_cleanup_qp_table), 4897 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4898 mlx5_init_srq_table, 4899 mlx5_cleanup_srq_table), 4900 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4901 mlx5_ib_dev_res_init, 4902 mlx5_ib_dev_res_cleanup), 4903 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4904 mlx5_ib_stage_bfrag_init, 4905 mlx5_ib_stage_bfrag_cleanup), 4906 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4907 mlx5_ib_stage_ib_reg_init, 4908 mlx5_ib_stage_ib_reg_cleanup), 4909 }; 4910 4911 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4912 enum rdma_nl_dev_type type, 4913 const char *name) 4914 { 4915 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 4916 enum rdma_link_layer ll; 4917 int ret; 4918 4919 if (mparent->smi_dev) 4920 return ERR_PTR(-EEXIST); 4921 4922 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 4923 port_type)); 4924 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 4925 ll != IB_LINK_LAYER_INFINIBAND || 4926 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 4927 return ERR_PTR(-EOPNOTSUPP); 4928 4929 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4930 mlx5_core_net(mparent->mdev)); 4931 if (!mplane) 4932 return ERR_PTR(-ENOMEM); 4933 4934 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 4935 sizeof(*mplane->port), GFP_KERNEL); 4936 if (!mplane->port) { 4937 ret = -ENOMEM; 4938 goto fail_kcalloc; 4939 } 4940 4941 mplane->ib_dev.type = type; 4942 mplane->mdev = mparent->mdev; 4943 mplane->num_ports = mparent->num_plane; 4944 mplane->sub_dev_name = name; 4945 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 4946 4947 ret = __mlx5_ib_add(mplane, &plane_profile); 4948 if (ret) 4949 goto fail_ib_add; 4950 4951 mparent->smi_dev = mplane; 4952 return &mplane->ib_dev; 4953 4954 fail_ib_add: 4955 kfree(mplane->port); 4956 fail_kcalloc: 4957 ib_dealloc_device(&mplane->ib_dev); 4958 return ERR_PTR(ret); 4959 } 4960 4961 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 4962 { 4963 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 4964 4965 to_mdev(sub_dev->parent)->smi_dev = NULL; 4966 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 4967 } 4968 4969 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4970 const struct auxiliary_device_id *id) 4971 { 4972 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4973 struct mlx5_core_dev *mdev = idev->mdev; 4974 struct mlx5_ib_multiport_info *mpi; 4975 struct mlx5_ib_dev *dev; 4976 bool bound = false; 4977 int err; 4978 4979 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4980 if (!mpi) 4981 return -ENOMEM; 4982 4983 mpi->mdev = mdev; 4984 err = mlx5_query_nic_vport_system_image_guid(mdev, 4985 &mpi->sys_image_guid); 4986 if (err) { 4987 kfree(mpi); 4988 return err; 4989 } 4990 4991 mutex_lock(&mlx5_ib_multiport_mutex); 4992 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4993 if (dev->sys_image_guid == mpi->sys_image_guid && 4994 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 4995 bound = mlx5_ib_bind_slave_port(dev, mpi); 4996 4997 if (bound) { 4998 rdma_roce_rescan_device(&dev->ib_dev); 4999 mpi->ibdev->ib_active = true; 5000 break; 5001 } 5002 } 5003 5004 if (!bound) { 5005 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5006 dev_dbg(mdev->device, 5007 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5008 } 5009 mutex_unlock(&mlx5_ib_multiport_mutex); 5010 5011 auxiliary_set_drvdata(adev, mpi); 5012 return 0; 5013 } 5014 5015 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5016 { 5017 struct mlx5_ib_multiport_info *mpi; 5018 5019 mpi = auxiliary_get_drvdata(adev); 5020 mutex_lock(&mlx5_ib_multiport_mutex); 5021 if (mpi->ibdev) 5022 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5023 else 5024 list_del(&mpi->list); 5025 mutex_unlock(&mlx5_ib_multiport_mutex); 5026 kfree(mpi); 5027 } 5028 5029 static int mlx5r_probe(struct auxiliary_device *adev, 5030 const struct auxiliary_device_id *id) 5031 { 5032 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5033 struct mlx5_core_dev *mdev = idev->mdev; 5034 const struct mlx5_ib_profile *profile; 5035 int port_type_cap, num_ports, ret; 5036 enum rdma_link_layer ll; 5037 struct mlx5_ib_dev *dev; 5038 5039 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5040 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5041 5042 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5043 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5044 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5045 mlx5_core_net(mdev)); 5046 if (!dev) 5047 return -ENOMEM; 5048 5049 if (ll == IB_LINK_LAYER_INFINIBAND) { 5050 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5051 if (ret) 5052 goto fail; 5053 } 5054 5055 dev->port = kcalloc(num_ports, sizeof(*dev->port), 5056 GFP_KERNEL); 5057 if (!dev->port) { 5058 ret = -ENOMEM; 5059 goto fail; 5060 } 5061 5062 dev->mdev = mdev; 5063 dev->num_ports = num_ports; 5064 dev->ib_dev.phys_port_cnt = num_ports; 5065 5066 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5067 profile = &raw_eth_profile; 5068 else 5069 profile = &pf_profile; 5070 5071 ret = __mlx5_ib_add(dev, profile); 5072 if (ret) 5073 goto fail_ib_add; 5074 5075 auxiliary_set_drvdata(adev, dev); 5076 return 0; 5077 5078 fail_ib_add: 5079 kfree(dev->port); 5080 fail: 5081 ib_dealloc_device(&dev->ib_dev); 5082 return ret; 5083 } 5084 5085 static void mlx5r_remove(struct auxiliary_device *adev) 5086 { 5087 struct mlx5_ib_dev *dev; 5088 5089 dev = auxiliary_get_drvdata(adev); 5090 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5091 } 5092 5093 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5094 { .name = MLX5_ADEV_NAME ".multiport", }, 5095 {}, 5096 }; 5097 5098 static const struct auxiliary_device_id mlx5r_id_table[] = { 5099 { .name = MLX5_ADEV_NAME ".rdma", }, 5100 {}, 5101 }; 5102 5103 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5104 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5105 5106 static struct auxiliary_driver mlx5r_mp_driver = { 5107 .name = "multiport", 5108 .probe = mlx5r_mp_probe, 5109 .remove = mlx5r_mp_remove, 5110 .id_table = mlx5r_mp_id_table, 5111 }; 5112 5113 static struct auxiliary_driver mlx5r_driver = { 5114 .name = "rdma", 5115 .probe = mlx5r_probe, 5116 .remove = mlx5r_remove, 5117 .id_table = mlx5r_id_table, 5118 }; 5119 5120 static int __init mlx5_ib_init(void) 5121 { 5122 int ret; 5123 5124 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 5125 if (!xlt_emergency_page) 5126 return -ENOMEM; 5127 5128 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5129 if (!mlx5_ib_event_wq) { 5130 free_page((unsigned long)xlt_emergency_page); 5131 return -ENOMEM; 5132 } 5133 5134 ret = mlx5_ib_qp_event_init(); 5135 if (ret) 5136 goto qp_event_err; 5137 5138 mlx5_ib_odp_init(); 5139 ret = mlx5r_rep_init(); 5140 if (ret) 5141 goto rep_err; 5142 ret = mlx5_data_direct_driver_register(); 5143 if (ret) 5144 goto dd_err; 5145 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5146 if (ret) 5147 goto mp_err; 5148 ret = auxiliary_driver_register(&mlx5r_driver); 5149 if (ret) 5150 goto drv_err; 5151 5152 return 0; 5153 5154 drv_err: 5155 auxiliary_driver_unregister(&mlx5r_mp_driver); 5156 mp_err: 5157 mlx5_data_direct_driver_unregister(); 5158 dd_err: 5159 mlx5r_rep_cleanup(); 5160 rep_err: 5161 mlx5_ib_qp_event_cleanup(); 5162 qp_event_err: 5163 destroy_workqueue(mlx5_ib_event_wq); 5164 free_page((unsigned long)xlt_emergency_page); 5165 return ret; 5166 } 5167 5168 static void __exit mlx5_ib_cleanup(void) 5169 { 5170 mlx5_data_direct_driver_unregister(); 5171 auxiliary_driver_unregister(&mlx5r_driver); 5172 auxiliary_driver_unregister(&mlx5r_mp_driver); 5173 mlx5r_rep_cleanup(); 5174 5175 mlx5_ib_qp_event_cleanup(); 5176 destroy_workqueue(mlx5_ib_event_wq); 5177 free_page((unsigned long)xlt_emergency_page); 5178 } 5179 5180 module_init(mlx5_ib_init); 5181 module_exit(mlx5_ib_cleanup); 5182