1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/driver.h> 29 #include <linux/mlx5/lag.h> 30 #include <linux/list.h> 31 #include <rdma/ib_smi.h> 32 #include <rdma/ib_umem_odp.h> 33 #include <rdma/lag.h> 34 #include <linux/in.h> 35 #include <linux/etherdevice.h> 36 #include "mlx5_ib.h" 37 #include "ib_rep.h" 38 #include "cmd.h" 39 #include "devx.h" 40 #include "dm.h" 41 #include "fs.h" 42 #include "srq.h" 43 #include "qp.h" 44 #include "wr.h" 45 #include "restrack.h" 46 #include "counters.h" 47 #include "umr.h" 48 #include <rdma/uverbs_std_types.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_verbs.h> 51 #include <rdma/mlx5_user_ioctl_cmds.h> 52 #include <rdma/ib_ucaps.h> 53 #include "macsec.h" 54 #include "data_direct.h" 55 #include "dmah.h" 56 57 #define UVERBS_MODULE_NAME mlx5_ib 58 #include <rdma/uverbs_named_ioctl.h> 59 60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 61 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 62 MODULE_LICENSE("Dual BSD/GPL"); 63 64 struct mlx5_ib_event_work { 65 struct work_struct work; 66 union { 67 struct mlx5_ib_dev *dev; 68 struct mlx5_ib_multiport_info *mpi; 69 }; 70 bool is_slave; 71 unsigned int event; 72 void *param; 73 }; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static struct workqueue_struct *mlx5_ib_event_wq; 80 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 81 static LIST_HEAD(mlx5_ib_dev_list); 82 /* 83 * This mutex should be held when accessing either of the above lists 84 */ 85 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 86 87 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 88 { 89 struct mlx5_ib_dev *dev; 90 91 mutex_lock(&mlx5_ib_multiport_mutex); 92 dev = mpi->ibdev; 93 mutex_unlock(&mlx5_ib_multiport_mutex); 94 return dev; 95 } 96 97 static enum rdma_link_layer 98 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 99 { 100 switch (port_type_cap) { 101 case MLX5_CAP_PORT_TYPE_IB: 102 return IB_LINK_LAYER_INFINIBAND; 103 case MLX5_CAP_PORT_TYPE_ETH: 104 return IB_LINK_LAYER_ETHERNET; 105 default: 106 return IB_LINK_LAYER_UNSPECIFIED; 107 } 108 } 109 110 static enum rdma_link_layer 111 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 112 { 113 struct mlx5_ib_dev *dev = to_mdev(device); 114 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 115 116 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 117 } 118 119 static int get_port_state(struct ib_device *ibdev, 120 u32 port_num, 121 enum ib_port_state *state) 122 { 123 struct ib_port_attr attr; 124 int ret; 125 126 memset(&attr, 0, sizeof(attr)); 127 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 128 if (!ret) 129 *state = attr.state; 130 return ret; 131 } 132 133 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 134 struct net_device *ndev, 135 struct net_device *upper, 136 u32 *port_num) 137 { 138 struct net_device *rep_ndev; 139 struct mlx5_ib_port *port; 140 int i; 141 142 for (i = 0; i < dev->num_ports; i++) { 143 port = &dev->port[i]; 144 if (!port->rep) 145 continue; 146 147 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 148 *port_num = i + 1; 149 return &port->roce; 150 } 151 152 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 153 continue; 154 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 155 if (rep_ndev && rep_ndev == ndev) { 156 dev_put(rep_ndev); 157 *port_num = i + 1; 158 return &port->roce; 159 } 160 161 dev_put(rep_ndev); 162 } 163 164 return NULL; 165 } 166 167 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 168 struct net_device *ndev, 169 struct net_device *upper, 170 struct net_device *ib_ndev) 171 { 172 if (!dev->ib_active) 173 return false; 174 175 /* Event is about our upper device */ 176 if (upper == ndev) 177 return true; 178 179 /* RDMA device is not in lag and not in switchdev */ 180 if (!dev->is_rep && !upper && ndev == ib_ndev) 181 return true; 182 183 /* RDMA devie is in switchdev */ 184 if (dev->is_rep && ndev == ib_ndev) 185 return true; 186 187 return false; 188 } 189 190 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 191 { 192 struct mlx5_ib_port *port; 193 int i; 194 195 for (i = 0; i < ibdev->num_ports; i++) { 196 port = &ibdev->port[i]; 197 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 198 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 199 } 200 } 201 202 return NULL; 203 } 204 205 static int mlx5_netdev_event(struct notifier_block *this, 206 unsigned long event, void *ptr) 207 { 208 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 209 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 210 u32 port_num = roce->native_port_num; 211 struct net_device *ib_ndev = NULL; 212 struct mlx5_core_dev *mdev; 213 struct mlx5_ib_dev *ibdev; 214 215 ibdev = roce->dev; 216 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 217 if (!mdev) 218 return NOTIFY_DONE; 219 220 switch (event) { 221 case NETDEV_REGISTER: 222 /* Should already be registered during the load */ 223 if (ibdev->is_rep) 224 break; 225 226 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 227 /* Exit if already registered */ 228 if (ib_ndev) 229 goto put_ndev; 230 231 if (ndev->dev.parent == mdev->device) 232 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 233 break; 234 235 case NETDEV_UNREGISTER: 236 /* In case of reps, ib device goes away before the netdevs */ 237 if (ibdev->is_rep) 238 break; 239 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 240 if (ib_ndev == ndev) 241 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 242 goto put_ndev; 243 244 case NETDEV_CHANGE: 245 case NETDEV_UP: 246 case NETDEV_DOWN: { 247 struct net_device *upper = NULL; 248 249 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 250 !mlx5_core_mp_enabled(mdev)) 251 return NOTIFY_DONE; 252 253 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 254 struct net_device *lag_ndev; 255 256 if(mlx5_lag_is_roce(mdev)) 257 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 258 else /* sriov lag */ 259 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 260 261 if (lag_ndev) { 262 upper = netdev_master_upper_dev_get(lag_ndev); 263 dev_put(lag_ndev); 264 } else { 265 goto done; 266 } 267 } 268 269 if (ibdev->is_rep) 270 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 271 if (!roce) 272 return NOTIFY_DONE; 273 274 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 275 276 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 277 struct ib_event ibev = { }; 278 enum ib_port_state port_state; 279 280 if (get_port_state(&ibdev->ib_dev, port_num, 281 &port_state)) 282 goto put_ndev; 283 284 if (roce->last_port_state == port_state) 285 goto put_ndev; 286 287 roce->last_port_state = port_state; 288 ibev.device = &ibdev->ib_dev; 289 if (port_state == IB_PORT_DOWN) 290 ibev.event = IB_EVENT_PORT_ERR; 291 else if (port_state == IB_PORT_ACTIVE) 292 ibev.event = IB_EVENT_PORT_ACTIVE; 293 else 294 goto put_ndev; 295 296 ibev.element.port_num = port_num; 297 ib_dispatch_event(&ibev); 298 } 299 break; 300 } 301 302 default: 303 break; 304 } 305 put_ndev: 306 dev_put(ib_ndev); 307 done: 308 mlx5_ib_put_native_port_mdev(ibdev, port_num); 309 return NOTIFY_DONE; 310 } 311 312 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 313 u32 ib_port_num, 314 u32 *native_port_num) 315 { 316 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 317 ib_port_num); 318 struct mlx5_core_dev *mdev = NULL; 319 struct mlx5_ib_multiport_info *mpi; 320 struct mlx5_ib_port *port; 321 322 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 323 if (native_port_num) 324 *native_port_num = smi_to_native_portnum(ibdev, 325 ib_port_num); 326 return ibdev->mdev; 327 328 } 329 330 if (!mlx5_core_mp_enabled(ibdev->mdev) || 331 ll != IB_LINK_LAYER_ETHERNET) { 332 if (native_port_num) 333 *native_port_num = ib_port_num; 334 return ibdev->mdev; 335 } 336 337 if (native_port_num) 338 *native_port_num = 1; 339 340 port = &ibdev->port[ib_port_num - 1]; 341 spin_lock(&port->mp.mpi_lock); 342 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 343 if (mpi && !mpi->unaffiliate) { 344 mdev = mpi->mdev; 345 /* If it's the master no need to refcount, it'll exist 346 * as long as the ib_dev exists. 347 */ 348 if (!mpi->is_master) 349 mpi->mdev_refcnt++; 350 } 351 spin_unlock(&port->mp.mpi_lock); 352 353 return mdev; 354 } 355 356 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 357 { 358 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 359 port_num); 360 struct mlx5_ib_multiport_info *mpi; 361 struct mlx5_ib_port *port; 362 363 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 364 return; 365 366 port = &ibdev->port[port_num - 1]; 367 368 spin_lock(&port->mp.mpi_lock); 369 mpi = ibdev->port[port_num - 1].mp.mpi; 370 if (mpi->is_master) 371 goto out; 372 373 mpi->mdev_refcnt--; 374 if (mpi->unaffiliate) 375 complete(&mpi->unref_comp); 376 out: 377 spin_unlock(&port->mp.mpi_lock); 378 } 379 380 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 381 u16 *active_speed, u8 *active_width) 382 { 383 switch (eth_proto_oper) { 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 385 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 386 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 397 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_QDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 403 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 416 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 417 *active_width = IB_WIDTH_1X; 418 *active_speed = IB_SPEED_HDR; 419 break; 420 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 421 *active_width = IB_WIDTH_4X; 422 *active_speed = IB_SPEED_FDR; 423 break; 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 427 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_EDR; 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 return 0; 436 } 437 438 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 439 u8 *active_width) 440 { 441 switch (eth_proto_oper) { 442 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 443 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 444 *active_width = IB_WIDTH_1X; 445 *active_speed = IB_SPEED_SDR; 446 break; 447 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 448 *active_width = IB_WIDTH_1X; 449 *active_speed = IB_SPEED_DDR; 450 break; 451 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 452 *active_width = IB_WIDTH_1X; 453 *active_speed = IB_SPEED_QDR; 454 break; 455 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 456 *active_width = IB_WIDTH_4X; 457 *active_speed = IB_SPEED_QDR; 458 break; 459 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 460 *active_width = IB_WIDTH_1X; 461 *active_speed = IB_SPEED_EDR; 462 break; 463 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 464 *active_width = IB_WIDTH_2X; 465 *active_speed = IB_SPEED_EDR; 466 break; 467 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 468 *active_width = IB_WIDTH_1X; 469 *active_speed = IB_SPEED_HDR; 470 break; 471 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 472 *active_width = IB_WIDTH_4X; 473 *active_speed = IB_SPEED_EDR; 474 break; 475 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 476 *active_width = IB_WIDTH_2X; 477 *active_speed = IB_SPEED_HDR; 478 break; 479 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 480 *active_width = IB_WIDTH_1X; 481 *active_speed = IB_SPEED_NDR; 482 break; 483 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 484 *active_width = IB_WIDTH_4X; 485 *active_speed = IB_SPEED_HDR; 486 break; 487 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 488 *active_width = IB_WIDTH_2X; 489 *active_speed = IB_SPEED_NDR; 490 break; 491 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 492 *active_width = IB_WIDTH_1X; 493 *active_speed = IB_SPEED_XDR; 494 break; 495 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 496 *active_width = IB_WIDTH_8X; 497 *active_speed = IB_SPEED_HDR; 498 break; 499 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 500 *active_width = IB_WIDTH_4X; 501 *active_speed = IB_SPEED_NDR; 502 break; 503 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 504 *active_width = IB_WIDTH_2X; 505 *active_speed = IB_SPEED_XDR; 506 break; 507 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 508 *active_width = IB_WIDTH_8X; 509 *active_speed = IB_SPEED_NDR; 510 break; 511 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 512 *active_width = IB_WIDTH_4X; 513 *active_speed = IB_SPEED_XDR; 514 break; 515 case MLX5E_PROT_MASK(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8): 516 *active_width = IB_WIDTH_8X; 517 *active_speed = IB_SPEED_XDR; 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 527 u8 *active_width, bool ext) 528 { 529 return ext ? 530 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 531 active_width) : 532 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 533 active_width); 534 } 535 536 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 537 struct ib_port_attr *props) 538 { 539 struct mlx5_ib_dev *dev = to_mdev(device); 540 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 541 struct mlx5_core_dev *mdev; 542 struct net_device *ndev, *upper; 543 enum ib_mtu ndev_ib_mtu; 544 bool put_mdev = true; 545 u32 eth_prot_oper; 546 u32 mdev_port_num; 547 bool ext; 548 int err; 549 550 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 551 if (!mdev) { 552 /* This means the port isn't affiliated yet. Get the 553 * info for the master port instead. 554 */ 555 put_mdev = false; 556 mdev = dev->mdev; 557 mdev_port_num = 1; 558 port_num = 1; 559 } 560 561 /* Possible bad flows are checked before filling out props so in case 562 * of an error it will still be zeroed out. 563 * Use native port in case of reps 564 */ 565 if (dev->is_rep) { 566 struct mlx5_eswitch_rep *rep; 567 568 rep = dev->port[port_num - 1].rep; 569 if (rep) { 570 mdev = mlx5_eswitch_get_core_dev(rep->esw); 571 WARN_ON(!mdev); 572 } 573 mdev_port_num = 1; 574 } 575 576 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 577 mdev_port_num, 0); 578 579 if (err) 580 goto out; 581 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 582 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 583 584 props->active_width = IB_WIDTH_4X; 585 props->active_speed = IB_SPEED_QDR; 586 587 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 588 &props->active_width, ext); 589 590 if (!dev->is_rep && dev->mdev->roce.roce_en) { 591 u16 qkey_viol_cntr; 592 593 props->port_cap_flags |= IB_PORT_CM_SUP; 594 props->ip_gids = true; 595 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 596 roce_address_table_size); 597 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 598 props->qkey_viol_cntr = qkey_viol_cntr; 599 } 600 props->max_mtu = IB_MTU_4096; 601 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 602 props->pkey_tbl_len = 1; 603 props->state = IB_PORT_DOWN; 604 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 605 606 /* If this is a stub query for an unaffiliated port stop here */ 607 if (!put_mdev) 608 goto out; 609 610 ndev = ib_device_get_netdev(device, port_num); 611 if (!ndev) 612 goto out; 613 614 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 615 rcu_read_lock(); 616 upper = netdev_master_upper_dev_get_rcu(ndev); 617 if (upper) { 618 dev_put(ndev); 619 ndev = upper; 620 dev_hold(ndev); 621 } 622 rcu_read_unlock(); 623 } 624 625 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 626 props->state = IB_PORT_ACTIVE; 627 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 628 } 629 630 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 631 632 dev_put(ndev); 633 634 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 635 out: 636 if (put_mdev) 637 mlx5_ib_put_native_port_mdev(dev, port_num); 638 return err; 639 } 640 641 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 642 unsigned int index, const union ib_gid *gid, 643 const struct ib_gid_attr *attr) 644 { 645 enum ib_gid_type gid_type; 646 u16 vlan_id = 0xffff; 647 u8 roce_version = 0; 648 u8 roce_l3_type = 0; 649 u8 mac[ETH_ALEN]; 650 int ret; 651 652 gid_type = attr->gid_type; 653 if (gid) { 654 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 655 if (ret) 656 return ret; 657 } 658 659 switch (gid_type) { 660 case IB_GID_TYPE_ROCE: 661 roce_version = MLX5_ROCE_VERSION_1; 662 break; 663 case IB_GID_TYPE_ROCE_UDP_ENCAP: 664 roce_version = MLX5_ROCE_VERSION_2; 665 if (gid && ipv6_addr_v4mapped((void *)gid)) 666 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 667 else 668 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 669 break; 670 671 default: 672 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 673 } 674 675 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 676 roce_l3_type, gid->raw, mac, 677 vlan_id < VLAN_CFI_MASK, vlan_id, 678 port_num); 679 } 680 681 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 682 __always_unused void **context) 683 { 684 int ret; 685 686 ret = mlx5r_add_gid_macsec_operations(attr); 687 if (ret) 688 return ret; 689 690 return set_roce_addr(to_mdev(attr->device), attr->port_num, 691 attr->index, &attr->gid, attr); 692 } 693 694 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 695 __always_unused void **context) 696 { 697 int ret; 698 699 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 700 attr->index, NULL, attr); 701 if (ret) 702 return ret; 703 704 mlx5r_del_gid_macsec_operations(attr); 705 return 0; 706 } 707 708 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 709 const struct ib_gid_attr *attr) 710 { 711 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 712 return 0; 713 714 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 715 } 716 717 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 718 { 719 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 720 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 721 return 0; 722 } 723 724 enum { 725 MLX5_VPORT_ACCESS_METHOD_MAD, 726 MLX5_VPORT_ACCESS_METHOD_HCA, 727 MLX5_VPORT_ACCESS_METHOD_NIC, 728 }; 729 730 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 731 { 732 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 733 return MLX5_VPORT_ACCESS_METHOD_MAD; 734 735 if (mlx5_ib_port_link_layer(ibdev, 1) == 736 IB_LINK_LAYER_ETHERNET) 737 return MLX5_VPORT_ACCESS_METHOD_NIC; 738 739 return MLX5_VPORT_ACCESS_METHOD_HCA; 740 } 741 742 static void get_atomic_caps(struct mlx5_ib_dev *dev, 743 u8 atomic_size_qp, 744 struct ib_device_attr *props) 745 { 746 u8 tmp; 747 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 748 u8 atomic_req_8B_endianness_mode = 749 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 750 751 /* Check if HW supports 8 bytes standard atomic operations and capable 752 * of host endianness respond 753 */ 754 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 755 if (((atomic_operations & tmp) == tmp) && 756 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 757 (atomic_req_8B_endianness_mode)) { 758 props->atomic_cap = IB_ATOMIC_HCA; 759 } else { 760 props->atomic_cap = IB_ATOMIC_NONE; 761 } 762 } 763 764 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 765 struct ib_device_attr *props) 766 { 767 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 768 769 get_atomic_caps(dev, atomic_size_qp, props); 770 } 771 772 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 773 __be64 *sys_image_guid) 774 { 775 struct mlx5_ib_dev *dev = to_mdev(ibdev); 776 struct mlx5_core_dev *mdev = dev->mdev; 777 u64 tmp; 778 int err; 779 780 switch (mlx5_get_vport_access_method(ibdev)) { 781 case MLX5_VPORT_ACCESS_METHOD_MAD: 782 return mlx5_query_mad_ifc_system_image_guid(ibdev, 783 sys_image_guid); 784 785 case MLX5_VPORT_ACCESS_METHOD_HCA: 786 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 787 break; 788 789 case MLX5_VPORT_ACCESS_METHOD_NIC: 790 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 791 break; 792 793 default: 794 return -EINVAL; 795 } 796 797 if (!err) 798 *sys_image_guid = cpu_to_be64(tmp); 799 800 return err; 801 802 } 803 804 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 805 u16 *max_pkeys) 806 { 807 struct mlx5_ib_dev *dev = to_mdev(ibdev); 808 struct mlx5_core_dev *mdev = dev->mdev; 809 810 switch (mlx5_get_vport_access_method(ibdev)) { 811 case MLX5_VPORT_ACCESS_METHOD_MAD: 812 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 813 814 case MLX5_VPORT_ACCESS_METHOD_HCA: 815 case MLX5_VPORT_ACCESS_METHOD_NIC: 816 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 817 pkey_table_size)); 818 return 0; 819 820 default: 821 return -EINVAL; 822 } 823 } 824 825 static int mlx5_query_vendor_id(struct ib_device *ibdev, 826 u32 *vendor_id) 827 { 828 struct mlx5_ib_dev *dev = to_mdev(ibdev); 829 830 switch (mlx5_get_vport_access_method(ibdev)) { 831 case MLX5_VPORT_ACCESS_METHOD_MAD: 832 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 833 834 case MLX5_VPORT_ACCESS_METHOD_HCA: 835 case MLX5_VPORT_ACCESS_METHOD_NIC: 836 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 837 838 default: 839 return -EINVAL; 840 } 841 } 842 843 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 844 __be64 *node_guid) 845 { 846 u64 tmp; 847 int err; 848 849 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 850 case MLX5_VPORT_ACCESS_METHOD_MAD: 851 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 852 853 case MLX5_VPORT_ACCESS_METHOD_HCA: 854 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 855 break; 856 857 case MLX5_VPORT_ACCESS_METHOD_NIC: 858 err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if (!err) 866 *node_guid = cpu_to_be64(tmp); 867 868 return err; 869 } 870 871 struct mlx5_reg_node_desc { 872 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 873 }; 874 875 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 876 { 877 struct mlx5_reg_node_desc in; 878 879 if (mlx5_use_mad_ifc(dev)) 880 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 881 882 memset(&in, 0, sizeof(in)); 883 884 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 885 sizeof(struct mlx5_reg_node_desc), 886 MLX5_REG_NODE_DESC, 0, 0); 887 } 888 889 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 890 struct mlx5_ib_query_device_resp *resp) 891 { 892 struct mlx5_eswitch *esw = mdev->priv.eswitch; 893 u16 vport = mlx5_eswitch_manager_vport(mdev); 894 895 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 896 vport); 897 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 898 } 899 900 /* 901 * Calculate maximum SQ overhead across all QP types. 902 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 903 * have smaller overhead than the types calculated below, 904 * so they are implicitly included. 905 */ 906 static u32 mlx5_ib_calc_max_sq_overhead(void) 907 { 908 u32 max_overhead_xrc, overhead_ud_lso, a, b; 909 910 /* XRC_INI */ 911 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 912 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 913 a = sizeof(struct mlx5_wqe_atomic_seg) + 914 sizeof(struct mlx5_wqe_raddr_seg); 915 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 916 sizeof(struct mlx5_mkey_seg) + 917 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 918 max_overhead_xrc += max(a, b); 919 920 /* UD with LSO */ 921 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 922 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 923 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 924 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 925 926 return max(max_overhead_xrc, overhead_ud_lso); 927 } 928 929 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 930 { 931 struct mlx5_core_dev *mdev = dev->mdev; 932 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 933 u32 max_wqe_size; 934 /* max QP overhead + 1 SGE, no inline, no special features */ 935 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 936 sizeof(struct mlx5_wqe_data_seg); 937 938 max_wqe_size = roundup_pow_of_two(max_wqe_size); 939 940 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 941 942 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 943 } 944 945 static int mlx5_ib_query_device(struct ib_device *ibdev, 946 struct ib_device_attr *props, 947 struct ib_udata *uhw) 948 { 949 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 950 struct mlx5_ib_dev *dev = to_mdev(ibdev); 951 struct mlx5_core_dev *mdev = dev->mdev; 952 int err = -ENOMEM; 953 int max_sq_desc; 954 int max_rq_sg; 955 int max_sq_sg; 956 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 957 bool raw_support = !mlx5_core_mp_enabled(mdev); 958 struct mlx5_ib_query_device_resp resp = {}; 959 size_t resp_len; 960 u64 max_tso; 961 962 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 963 if (uhw_outlen && uhw_outlen < resp_len) 964 return -EINVAL; 965 966 resp.response_length = resp_len; 967 968 err = ib_is_udata_in_empty(uhw); 969 if (err) 970 return err; 971 972 memset(props, 0, sizeof(*props)); 973 err = mlx5_query_system_image_guid(ibdev, 974 &props->sys_image_guid); 975 if (err) 976 return err; 977 978 props->max_pkeys = dev->pkey_table_len; 979 980 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 981 if (err) 982 return err; 983 984 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 985 (fw_rev_min(dev->mdev) << 16) | 986 fw_rev_sub(dev->mdev); 987 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 988 IB_DEVICE_PORT_ACTIVE_EVENT | 989 IB_DEVICE_SYS_IMAGE_GUID | 990 IB_DEVICE_RC_RNR_NAK_GEN; 991 992 if (MLX5_CAP_GEN(mdev, pkv)) 993 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 994 if (MLX5_CAP_GEN(mdev, qkv)) 995 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 996 if (MLX5_CAP_GEN(mdev, apm)) 997 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 998 if (MLX5_CAP_GEN(mdev, xrc)) 999 props->device_cap_flags |= IB_DEVICE_XRC; 1000 if (MLX5_CAP_GEN(mdev, imaicl)) { 1001 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 1002 IB_DEVICE_MEM_WINDOW_TYPE_2B; 1003 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1004 /* We support 'Gappy' memory registration too */ 1005 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 1006 } 1007 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 1008 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1009 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 1010 if (MLX5_CAP_GEN(mdev, sho)) { 1011 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 1012 /* At this stage no support for signature handover */ 1013 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1014 IB_PROT_T10DIF_TYPE_2 | 1015 IB_PROT_T10DIF_TYPE_3; 1016 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1017 IB_GUARD_T10DIF_CSUM; 1018 } 1019 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1020 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1021 1022 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1023 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1024 /* Legacy bit to support old userspace libraries */ 1025 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1026 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1027 } 1028 1029 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1030 props->raw_packet_caps |= 1031 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1032 1033 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1034 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1035 if (max_tso) { 1036 resp.tso_caps.max_tso = 1 << max_tso; 1037 resp.tso_caps.supported_qpts |= 1038 1 << IB_QPT_RAW_PACKET; 1039 resp.response_length += sizeof(resp.tso_caps); 1040 } 1041 } 1042 1043 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1044 resp.rss_caps.rx_hash_function = 1045 MLX5_RX_HASH_FUNC_TOEPLITZ; 1046 resp.rss_caps.rx_hash_fields_mask = 1047 MLX5_RX_HASH_SRC_IPV4 | 1048 MLX5_RX_HASH_DST_IPV4 | 1049 MLX5_RX_HASH_SRC_IPV6 | 1050 MLX5_RX_HASH_DST_IPV6 | 1051 MLX5_RX_HASH_SRC_PORT_TCP | 1052 MLX5_RX_HASH_DST_PORT_TCP | 1053 MLX5_RX_HASH_SRC_PORT_UDP | 1054 MLX5_RX_HASH_DST_PORT_UDP | 1055 MLX5_RX_HASH_INNER; 1056 resp.response_length += sizeof(resp.rss_caps); 1057 } 1058 } else { 1059 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1060 resp.response_length += sizeof(resp.tso_caps); 1061 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1062 resp.response_length += sizeof(resp.rss_caps); 1063 } 1064 1065 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1066 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1067 props->kernel_cap_flags |= IBK_UD_TSO; 1068 } 1069 1070 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1071 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1072 raw_support) 1073 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1074 1075 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1076 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1077 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1078 1079 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1080 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1081 raw_support) { 1082 /* Legacy bit to support old userspace libraries */ 1083 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1084 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1085 } 1086 1087 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1088 props->max_dm_size = 1089 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1090 } 1091 1092 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1093 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1094 1095 if (MLX5_CAP_GEN(mdev, end_pad)) 1096 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1097 1098 props->vendor_part_id = mdev->pdev->device; 1099 props->hw_ver = mdev->pdev->revision; 1100 1101 props->max_mr_size = ~0ull; 1102 props->page_size_cap = ~(min_page_size - 1); 1103 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1104 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1105 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1106 sizeof(struct mlx5_wqe_data_seg); 1107 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1108 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1109 sizeof(struct mlx5_wqe_raddr_seg)) / 1110 sizeof(struct mlx5_wqe_data_seg); 1111 props->max_send_sge = max_sq_sg; 1112 props->max_recv_sge = max_rq_sg; 1113 props->max_sge_rd = MLX5_MAX_SGE_RD; 1114 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1115 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1116 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1117 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1118 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1119 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1120 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1121 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1122 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1123 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1124 props->max_srq_sge = max_rq_sg - 1; 1125 props->max_fast_reg_page_list_len = 1126 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1127 props->max_pi_fast_reg_page_list_len = 1128 props->max_fast_reg_page_list_len / 2; 1129 props->max_sgl_rd = 1130 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1131 get_atomic_caps_qp(dev, props); 1132 props->masked_atomic_cap = IB_ATOMIC_NONE; 1133 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1134 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1135 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1136 props->max_mcast_grp; 1137 props->max_ah = INT_MAX; 1138 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1139 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1140 1141 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1142 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1143 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1144 props->odp_caps = dev->odp_caps; 1145 if (!uhw) { 1146 /* ODP for kernel QPs is not implemented for receive 1147 * WQEs and SRQ WQEs 1148 */ 1149 props->odp_caps.per_transport_caps.rc_odp_caps &= 1150 ~(IB_ODP_SUPPORT_READ | 1151 IB_ODP_SUPPORT_SRQ_RECV); 1152 props->odp_caps.per_transport_caps.uc_odp_caps &= 1153 ~(IB_ODP_SUPPORT_READ | 1154 IB_ODP_SUPPORT_SRQ_RECV); 1155 props->odp_caps.per_transport_caps.ud_odp_caps &= 1156 ~(IB_ODP_SUPPORT_READ | 1157 IB_ODP_SUPPORT_SRQ_RECV); 1158 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1159 ~(IB_ODP_SUPPORT_READ | 1160 IB_ODP_SUPPORT_SRQ_RECV); 1161 } 1162 } 1163 1164 if (mlx5_core_is_vf(mdev)) 1165 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1166 1167 if (mlx5_ib_port_link_layer(ibdev, 1) == 1168 IB_LINK_LAYER_ETHERNET && raw_support) { 1169 props->rss_caps.max_rwq_indirection_tables = 1170 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1171 props->rss_caps.max_rwq_indirection_table_size = 1172 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1173 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1174 props->max_wq_type_rq = 1175 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1176 } 1177 1178 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1179 props->tm_caps.max_num_tags = 1180 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1181 props->tm_caps.max_ops = 1182 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1183 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1184 } 1185 1186 if (MLX5_CAP_GEN(mdev, tag_matching) && 1187 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1188 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1189 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1190 } 1191 1192 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1193 props->cq_caps.max_cq_moderation_count = 1194 MLX5_MAX_CQ_COUNT; 1195 props->cq_caps.max_cq_moderation_period = 1196 MLX5_MAX_CQ_PERIOD; 1197 } 1198 1199 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1200 resp.response_length += sizeof(resp.cqe_comp_caps); 1201 1202 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1203 resp.cqe_comp_caps.max_num = 1204 MLX5_CAP_GEN(dev->mdev, 1205 cqe_compression_max_num); 1206 1207 resp.cqe_comp_caps.supported_format = 1208 MLX5_IB_CQE_RES_FORMAT_HASH | 1209 MLX5_IB_CQE_RES_FORMAT_CSUM; 1210 1211 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1212 resp.cqe_comp_caps.supported_format |= 1213 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1214 } 1215 } 1216 1217 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen) { 1218 if (MLX5_CAP_GEN(mdev, qos)) { 1219 if (MLX5_CAP_QOS(mdev, packet_pacing) && raw_support) 1220 resp.packet_pacing_caps.supported_qpts |= 1221 BIT(IB_QPT_RAW_PACKET); 1222 if (MLX5_CAP_QOS(mdev, packet_pacing_req_ud)) 1223 resp.packet_pacing_caps.supported_qpts |= 1224 BIT(IB_QPT_UD); 1225 if (MLX5_CAP_QOS(mdev, packet_pacing_req_uc)) 1226 resp.packet_pacing_caps.supported_qpts |= 1227 BIT(IB_QPT_UC); 1228 1229 if (resp.packet_pacing_caps.supported_qpts) { 1230 resp.packet_pacing_caps.qp_rate_limit_max = 1231 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1232 resp.packet_pacing_caps.qp_rate_limit_min = 1233 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1234 1235 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1236 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1237 resp.packet_pacing_caps.cap_flags |= 1238 MLX5_IB_PP_SUPPORT_BURST; 1239 } 1240 } 1241 resp.response_length += sizeof(resp.packet_pacing_caps); 1242 } 1243 1244 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1245 uhw_outlen) { 1246 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1247 resp.mlx5_ib_support_multi_pkt_send_wqes = 1248 MLX5_IB_ALLOW_MPW; 1249 1250 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1251 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1252 MLX5_IB_SUPPORT_EMPW; 1253 1254 resp.response_length += 1255 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1256 } 1257 1258 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1259 resp.response_length += sizeof(resp.flags); 1260 1261 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1262 resp.flags |= 1263 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1264 1265 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1266 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1267 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1268 resp.flags |= 1269 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1270 1271 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1272 1273 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1274 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1275 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1276 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1277 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1278 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1279 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1280 } 1281 1282 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1283 resp.response_length += sizeof(resp.sw_parsing_caps); 1284 if (MLX5_CAP_ETH(mdev, swp)) { 1285 resp.sw_parsing_caps.sw_parsing_offloads |= 1286 MLX5_IB_SW_PARSING; 1287 1288 if (MLX5_CAP_ETH(mdev, swp_csum)) 1289 resp.sw_parsing_caps.sw_parsing_offloads |= 1290 MLX5_IB_SW_PARSING_CSUM; 1291 1292 if (MLX5_CAP_ETH(mdev, swp_lso)) 1293 resp.sw_parsing_caps.sw_parsing_offloads |= 1294 MLX5_IB_SW_PARSING_LSO; 1295 1296 if (resp.sw_parsing_caps.sw_parsing_offloads) 1297 resp.sw_parsing_caps.supported_qpts = 1298 BIT(IB_QPT_RAW_PACKET); 1299 } 1300 } 1301 1302 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1303 raw_support) { 1304 resp.response_length += sizeof(resp.striding_rq_caps); 1305 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1306 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1307 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1308 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1309 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1310 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1311 resp.striding_rq_caps 1312 .min_single_wqe_log_num_of_strides = 1313 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1314 else 1315 resp.striding_rq_caps 1316 .min_single_wqe_log_num_of_strides = 1317 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1318 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1319 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1320 resp.striding_rq_caps.supported_qpts = 1321 BIT(IB_QPT_RAW_PACKET); 1322 } 1323 } 1324 1325 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1326 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1327 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1328 resp.tunnel_offloads_caps |= 1329 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1330 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1331 resp.tunnel_offloads_caps |= 1332 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1333 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1334 resp.tunnel_offloads_caps |= 1335 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1336 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1337 resp.tunnel_offloads_caps |= 1338 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1339 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1340 resp.tunnel_offloads_caps |= 1341 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1342 } 1343 1344 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1345 resp.response_length += sizeof(resp.dci_streams_caps); 1346 1347 resp.dci_streams_caps.max_log_num_concurent = 1348 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1349 1350 resp.dci_streams_caps.max_log_num_errored = 1351 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1352 } 1353 1354 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1355 resp.response_length += sizeof(resp.reserved); 1356 1357 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1358 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1359 1360 resp.response_length += sizeof(resp.reg_c0); 1361 1362 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1363 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1364 fill_esw_mgr_reg_c0(mdev, &resp); 1365 } 1366 1367 if (uhw_outlen) { 1368 err = ib_respond_udata(uhw, resp); 1369 1370 if (err) 1371 return err; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1378 u8 *ib_width) 1379 { 1380 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1381 1382 if (active_width & MLX5_PTYS_WIDTH_1X) 1383 *ib_width = IB_WIDTH_1X; 1384 else if (active_width & MLX5_PTYS_WIDTH_2X) 1385 *ib_width = IB_WIDTH_2X; 1386 else if (active_width & MLX5_PTYS_WIDTH_4X) 1387 *ib_width = IB_WIDTH_4X; 1388 else if (active_width & MLX5_PTYS_WIDTH_8X) 1389 *ib_width = IB_WIDTH_8X; 1390 else if (active_width & MLX5_PTYS_WIDTH_12X) 1391 *ib_width = IB_WIDTH_12X; 1392 else { 1393 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1394 active_width); 1395 *ib_width = IB_WIDTH_4X; 1396 } 1397 1398 return; 1399 } 1400 1401 static int mlx5_mtu_to_ib_mtu(int mtu) 1402 { 1403 switch (mtu) { 1404 case 256: return 1; 1405 case 512: return 2; 1406 case 1024: return 3; 1407 case 2048: return 4; 1408 case 4096: return 5; 1409 default: 1410 pr_warn("invalid mtu\n"); 1411 return -1; 1412 } 1413 } 1414 1415 enum ib_max_vl_num { 1416 __IB_MAX_VL_0 = 1, 1417 __IB_MAX_VL_0_1 = 2, 1418 __IB_MAX_VL_0_3 = 3, 1419 __IB_MAX_VL_0_7 = 4, 1420 __IB_MAX_VL_0_14 = 5, 1421 }; 1422 1423 enum mlx5_vl_hw_cap { 1424 MLX5_VL_HW_0 = 1, 1425 MLX5_VL_HW_0_1 = 2, 1426 MLX5_VL_HW_0_2 = 3, 1427 MLX5_VL_HW_0_3 = 4, 1428 MLX5_VL_HW_0_4 = 5, 1429 MLX5_VL_HW_0_5 = 6, 1430 MLX5_VL_HW_0_6 = 7, 1431 MLX5_VL_HW_0_7 = 8, 1432 MLX5_VL_HW_0_14 = 15 1433 }; 1434 1435 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1436 u8 *max_vl_num) 1437 { 1438 switch (vl_hw_cap) { 1439 case MLX5_VL_HW_0: 1440 *max_vl_num = __IB_MAX_VL_0; 1441 break; 1442 case MLX5_VL_HW_0_1: 1443 *max_vl_num = __IB_MAX_VL_0_1; 1444 break; 1445 case MLX5_VL_HW_0_3: 1446 *max_vl_num = __IB_MAX_VL_0_3; 1447 break; 1448 case MLX5_VL_HW_0_7: 1449 *max_vl_num = __IB_MAX_VL_0_7; 1450 break; 1451 case MLX5_VL_HW_0_14: 1452 *max_vl_num = __IB_MAX_VL_0_14; 1453 break; 1454 1455 default: 1456 return -EINVAL; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1463 struct ib_port_attr *props) 1464 { 1465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1466 struct mlx5_core_dev *mdev = dev->mdev; 1467 struct mlx5_hca_vport_context *rep; 1468 u8 vl_hw_cap, plane_index = 0; 1469 u16 max_mtu; 1470 u16 oper_mtu; 1471 int err; 1472 u16 ib_link_width_oper; 1473 1474 rep = kzalloc_obj(*rep); 1475 if (!rep) { 1476 err = -ENOMEM; 1477 goto out; 1478 } 1479 1480 /* props being zeroed by the caller, avoid zeroing it here */ 1481 1482 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1483 plane_index = port; 1484 port = smi_to_native_portnum(dev, port); 1485 } 1486 1487 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1488 if (err) 1489 goto out; 1490 1491 props->lid = rep->lid; 1492 props->lmc = rep->lmc; 1493 props->sm_lid = rep->sm_lid; 1494 props->sm_sl = rep->sm_sl; 1495 props->state = rep->vport_state; 1496 props->phys_state = rep->port_physical_state; 1497 1498 props->port_cap_flags = rep->cap_mask1; 1499 if (dev->num_plane) { 1500 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1501 props->port_cap_flags &= ~IB_PORT_SM; 1502 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1503 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1504 1505 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1506 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1507 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1508 props->bad_pkey_cntr = rep->pkey_violation_counter; 1509 props->qkey_viol_cntr = rep->qkey_violation_counter; 1510 props->subnet_timeout = rep->subnet_timeout; 1511 props->init_type_reply = rep->init_type_reply; 1512 1513 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1514 props->port_cap_flags2 = rep->cap_mask2; 1515 1516 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1517 &props->active_speed, port, plane_index); 1518 if (err) 1519 goto out; 1520 1521 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1522 1523 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1524 1525 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1526 1527 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1528 1529 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1530 1531 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1532 if (err) 1533 goto out; 1534 1535 err = translate_max_vl_num(ibdev, vl_hw_cap, 1536 &props->max_vl_num); 1537 out: 1538 kfree(rep); 1539 return err; 1540 } 1541 1542 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1543 struct ib_port_attr *props) 1544 { 1545 unsigned int count; 1546 int ret; 1547 1548 switch (mlx5_get_vport_access_method(ibdev)) { 1549 case MLX5_VPORT_ACCESS_METHOD_MAD: 1550 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1551 break; 1552 1553 case MLX5_VPORT_ACCESS_METHOD_HCA: 1554 ret = mlx5_query_hca_port(ibdev, port, props); 1555 break; 1556 1557 case MLX5_VPORT_ACCESS_METHOD_NIC: 1558 ret = mlx5_query_port_roce(ibdev, port, props); 1559 break; 1560 1561 default: 1562 ret = -EINVAL; 1563 } 1564 1565 if (!ret && props) { 1566 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1567 struct mlx5_core_dev *mdev; 1568 bool put_mdev = true; 1569 1570 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1571 if (!mdev) { 1572 /* If the port isn't affiliated yet query the master. 1573 * The master and slave will have the same values. 1574 */ 1575 mdev = dev->mdev; 1576 port = 1; 1577 put_mdev = false; 1578 } 1579 count = mlx5_core_reserved_gids_count(mdev); 1580 if (put_mdev) 1581 mlx5_ib_put_native_port_mdev(dev, port); 1582 props->gid_tbl_len -= count; 1583 } 1584 return ret; 1585 } 1586 1587 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1588 struct ib_port_attr *props) 1589 { 1590 return mlx5_query_port_roce(ibdev, port, props); 1591 } 1592 1593 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1594 u16 *pkey) 1595 { 1596 /* Default special Pkey for representor device port as per the 1597 * IB specification 1.3 section 10.9.1.2. 1598 */ 1599 *pkey = 0xffff; 1600 return 0; 1601 } 1602 1603 static int mlx5_ib_query_port_speed_from_port(struct mlx5_ib_dev *dev, 1604 u32 port_num, u64 *speed) 1605 { 1606 struct ib_port_speed_info speed_info; 1607 struct ib_port_attr attr = {}; 1608 int err; 1609 1610 err = mlx5_ib_query_port(&dev->ib_dev, port_num, &attr); 1611 if (err) 1612 return err; 1613 1614 if (attr.state == IB_PORT_DOWN) { 1615 *speed = 0; 1616 return 0; 1617 } 1618 1619 err = ib_port_attr_to_speed_info(&attr, &speed_info); 1620 if (err) 1621 return err; 1622 1623 *speed = speed_info.rate; 1624 return 0; 1625 } 1626 1627 static int mlx5_ib_query_port_speed_from_vport(struct mlx5_core_dev *mdev, 1628 u8 op_mod, u16 vport, 1629 u8 other_vport, u64 *speed, 1630 struct mlx5_ib_dev *dev, 1631 u32 port_num) 1632 { 1633 u32 max_tx_speed; 1634 int err; 1635 1636 err = mlx5_query_vport_max_tx_speed(mdev, op_mod, vport, other_vport, 1637 &max_tx_speed); 1638 if (err) 1639 return err; 1640 1641 if (max_tx_speed == 0) 1642 /* Value 0 indicates field not supported, fallback */ 1643 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1644 speed); 1645 1646 *speed = max_tx_speed; 1647 return 0; 1648 } 1649 1650 static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, 1651 u32 port_num, u64 *speed) 1652 { 1653 struct mlx5_core_dev *mdev = dev->mdev; 1654 u32 bond_speed; 1655 int err; 1656 1657 err = mlx5_lag_query_bond_speed(mdev, &bond_speed); 1658 if (err) 1659 return err; 1660 1661 *speed = bond_speed / MLX5_MAX_TX_SPEED_UNIT; 1662 1663 return 0; 1664 } 1665 1666 static int mlx5_ib_query_port_speed_non_rep(struct mlx5_ib_dev *dev, 1667 u32 port_num, u64 *speed) 1668 { 1669 u16 op_mod = MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT; 1670 1671 if (mlx5_lag_is_roce(dev->mdev)) 1672 return mlx5_ib_query_port_speed_from_bond(dev, port_num, 1673 speed); 1674 1675 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 0, false, 1676 speed, dev, port_num); 1677 } 1678 1679 static int mlx5_ib_query_port_speed_rep(struct mlx5_ib_dev *dev, u32 port_num, 1680 u64 *speed) 1681 { 1682 struct mlx5_eswitch_rep *rep; 1683 struct mlx5_core_dev *mdev; 1684 u16 op_mod; 1685 1686 if (!dev->port[port_num - 1].rep) { 1687 mlx5_ib_warn(dev, "Representor doesn't exist for port %u\n", 1688 port_num); 1689 return -EINVAL; 1690 } 1691 1692 rep = dev->port[port_num - 1].rep; 1693 mdev = mlx5_eswitch_get_core_dev(rep->esw); 1694 if (!mdev) 1695 return -ENODEV; 1696 1697 if (rep->vport == MLX5_VPORT_UPLINK) { 1698 if (mlx5_lag_is_sriov(mdev)) 1699 return mlx5_ib_query_port_speed_from_bond(dev, 1700 port_num, 1701 speed); 1702 1703 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1704 speed); 1705 } 1706 1707 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; 1708 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 1709 rep->vport, true, speed, dev, 1710 port_num); 1711 } 1712 1713 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, u64 *speed) 1714 { 1715 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1716 1717 if (mlx5_ib_port_link_layer(ibdev, port_num) == 1718 IB_LINK_LAYER_INFINIBAND || mlx5_core_mp_enabled(dev->mdev)) 1719 return mlx5_ib_query_port_speed_from_port(dev, port_num, speed); 1720 else if (!dev->is_rep) 1721 return mlx5_ib_query_port_speed_non_rep(dev, port_num, speed); 1722 else 1723 return mlx5_ib_query_port_speed_rep(dev, port_num, speed); 1724 } 1725 1726 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1727 union ib_gid *gid) 1728 { 1729 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1730 struct mlx5_core_dev *mdev = dev->mdev; 1731 1732 switch (mlx5_get_vport_access_method(ibdev)) { 1733 case MLX5_VPORT_ACCESS_METHOD_MAD: 1734 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1735 1736 case MLX5_VPORT_ACCESS_METHOD_HCA: 1737 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1738 1739 default: 1740 return -EINVAL; 1741 } 1742 1743 } 1744 1745 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1746 u16 index, u16 *pkey) 1747 { 1748 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1749 struct mlx5_core_dev *mdev; 1750 bool put_mdev = true; 1751 u32 mdev_port_num; 1752 int err; 1753 1754 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1755 if (!mdev) { 1756 /* The port isn't affiliated yet, get the PKey from the master 1757 * port. For RoCE the PKey tables will be the same. 1758 */ 1759 put_mdev = false; 1760 mdev = dev->mdev; 1761 mdev_port_num = 1; 1762 } 1763 1764 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1765 index, pkey); 1766 if (put_mdev) 1767 mlx5_ib_put_native_port_mdev(dev, port); 1768 1769 return err; 1770 } 1771 1772 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1773 u16 *pkey) 1774 { 1775 switch (mlx5_get_vport_access_method(ibdev)) { 1776 case MLX5_VPORT_ACCESS_METHOD_MAD: 1777 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1778 1779 case MLX5_VPORT_ACCESS_METHOD_HCA: 1780 case MLX5_VPORT_ACCESS_METHOD_NIC: 1781 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1782 default: 1783 return -EINVAL; 1784 } 1785 } 1786 1787 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1788 struct ib_device_modify *props) 1789 { 1790 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1791 struct mlx5_reg_node_desc in; 1792 struct mlx5_reg_node_desc out; 1793 int err; 1794 1795 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1796 return -EOPNOTSUPP; 1797 1798 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1799 return 0; 1800 1801 /* 1802 * If possible, pass node desc to FW, so it can generate 1803 * a 144 trap. If cmd fails, just ignore. 1804 */ 1805 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1806 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1807 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1808 if (err) 1809 return err; 1810 1811 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1812 1813 return err; 1814 } 1815 1816 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1817 u32 value) 1818 { 1819 struct mlx5_hca_vport_context ctx = {}; 1820 struct mlx5_core_dev *mdev; 1821 u32 mdev_port_num; 1822 int err; 1823 1824 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1825 if (!mdev) 1826 return -ENODEV; 1827 1828 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1829 if (err) 1830 goto out; 1831 1832 if (~ctx.cap_mask1_perm & mask) { 1833 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1834 mask, ctx.cap_mask1_perm); 1835 err = -EINVAL; 1836 goto out; 1837 } 1838 1839 ctx.cap_mask1 = value; 1840 ctx.cap_mask1_perm = mask; 1841 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1842 0, &ctx); 1843 1844 out: 1845 mlx5_ib_put_native_port_mdev(dev, port_num); 1846 1847 return err; 1848 } 1849 1850 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1851 struct ib_port_modify *props) 1852 { 1853 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1854 struct ib_port_attr attr; 1855 u32 tmp; 1856 int err; 1857 u32 change_mask; 1858 u32 value; 1859 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1860 IB_LINK_LAYER_INFINIBAND); 1861 1862 /* CM layer calls ib_modify_port() regardless of the link layer. For 1863 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1864 */ 1865 if (!is_ib) 1866 return 0; 1867 1868 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1869 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1870 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1871 return set_port_caps_atomic(dev, port, change_mask, value); 1872 } 1873 1874 mutex_lock(&dev->cap_mask_mutex); 1875 1876 err = ib_query_port(ibdev, port, &attr); 1877 if (err) 1878 goto out; 1879 1880 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1881 ~props->clr_port_cap_mask; 1882 1883 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1884 1885 out: 1886 mutex_unlock(&dev->cap_mask_mutex); 1887 return err; 1888 } 1889 1890 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1891 { 1892 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1893 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1894 } 1895 1896 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1897 { 1898 /* Large page with non 4k uar support might limit the dynamic size */ 1899 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1900 return MLX5_MIN_DYN_BFREGS; 1901 1902 return MLX5_MAX_DYN_BFREGS; 1903 } 1904 1905 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1906 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1907 struct mlx5_bfreg_info *bfregi) 1908 { 1909 int uars_per_sys_page; 1910 int bfregs_per_sys_page; 1911 int ref_bfregs = req->total_num_bfregs; 1912 1913 if (req->total_num_bfregs == 0) 1914 return -EINVAL; 1915 1916 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1917 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1918 1919 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1920 return -ENOMEM; 1921 1922 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1923 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1924 /* This holds the required static allocation asked by the user */ 1925 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1926 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1927 return -EINVAL; 1928 1929 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1930 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1931 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1932 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1933 1934 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1935 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1936 lib_uar_4k ? "yes" : "no", ref_bfregs, 1937 req->total_num_bfregs, bfregi->total_num_bfregs, 1938 bfregi->num_sys_pages); 1939 1940 return 0; 1941 } 1942 1943 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1944 { 1945 struct mlx5_bfreg_info *bfregi; 1946 int err; 1947 int i; 1948 1949 bfregi = &context->bfregi; 1950 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1951 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1952 context->devx_uid); 1953 if (err) 1954 goto error; 1955 1956 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1957 } 1958 1959 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1960 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1961 1962 return 0; 1963 1964 error: 1965 for (--i; i >= 0; i--) 1966 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1967 context->devx_uid)) 1968 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1969 1970 return err; 1971 } 1972 1973 static void deallocate_uars(struct mlx5_ib_dev *dev, 1974 struct mlx5_ib_ucontext *context) 1975 { 1976 struct mlx5_bfreg_info *bfregi; 1977 int i; 1978 1979 bfregi = &context->bfregi; 1980 for (i = 0; i < bfregi->num_sys_pages; i++) 1981 if (i < bfregi->num_static_sys_pages || 1982 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1983 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1984 context->devx_uid); 1985 } 1986 1987 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1988 struct mlx5_core_dev *slave, 1989 struct mlx5_ib_lb_state *lb_state) 1990 { 1991 int err; 1992 1993 err = mlx5_nic_vport_update_local_lb(master, true); 1994 if (err) 1995 return err; 1996 1997 err = mlx5_nic_vport_update_local_lb(slave, true); 1998 if (err) 1999 goto out; 2000 2001 lb_state->force_enable = true; 2002 return 0; 2003 2004 out: 2005 mlx5_nic_vport_update_local_lb(master, false); 2006 return err; 2007 } 2008 2009 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 2010 struct mlx5_core_dev *slave, 2011 struct mlx5_ib_lb_state *lb_state) 2012 { 2013 mlx5_nic_vport_update_local_lb(slave, false); 2014 mlx5_nic_vport_update_local_lb(master, false); 2015 2016 lb_state->force_enable = false; 2017 } 2018 2019 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2020 { 2021 int err = 0; 2022 2023 if (dev->lb.force_enable) 2024 return 0; 2025 2026 mutex_lock(&dev->lb.mutex); 2027 if (td) 2028 dev->lb.user_td++; 2029 if (qp) 2030 dev->lb.qps++; 2031 2032 if (dev->lb.user_td == 2 || 2033 dev->lb.qps == 1) { 2034 if (!dev->lb.enabled) { 2035 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 2036 if (err) 2037 goto err_rollback; 2038 2039 dev->lb.enabled = true; 2040 } 2041 } 2042 2043 mutex_unlock(&dev->lb.mutex); 2044 2045 return err; 2046 2047 err_rollback: 2048 if (td) 2049 dev->lb.user_td--; 2050 if (qp) 2051 dev->lb.qps--; 2052 mutex_unlock(&dev->lb.mutex); 2053 return err; 2054 } 2055 2056 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2057 { 2058 if (dev->lb.force_enable) 2059 return; 2060 2061 mutex_lock(&dev->lb.mutex); 2062 if (td) 2063 dev->lb.user_td--; 2064 if (qp) 2065 dev->lb.qps--; 2066 2067 if (dev->lb.user_td == 1 && 2068 dev->lb.qps == 0) { 2069 if (dev->lb.enabled) { 2070 mlx5_nic_vport_update_local_lb(dev->mdev, false); 2071 dev->lb.enabled = false; 2072 } 2073 } 2074 2075 mutex_unlock(&dev->lb.mutex); 2076 } 2077 2078 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 2079 u16 uid) 2080 { 2081 int err; 2082 2083 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2084 return 0; 2085 2086 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 2087 if (err) 2088 return err; 2089 2090 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2091 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2092 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2093 return 0; 2094 2095 err = mlx5_ib_enable_lb(dev, true, false); 2096 if (err) 2097 mlx5_cmd_dealloc_transport_domain(dev->mdev, *tdn, uid); 2098 2099 return err; 2100 } 2101 2102 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 2103 u16 uid) 2104 { 2105 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2106 return; 2107 2108 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 2109 2110 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2111 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2112 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2113 return; 2114 2115 mlx5_ib_disable_lb(dev, true, false); 2116 } 2117 2118 static int set_ucontext_resp(struct ib_ucontext *uctx, 2119 struct mlx5_ib_alloc_ucontext_resp *resp) 2120 { 2121 struct ib_device *ibdev = uctx->device; 2122 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2123 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2124 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2125 2126 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 2127 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 2128 resp->comp_mask |= 2129 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 2130 } 2131 2132 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 2133 if (mlx5_wc_support_get(dev->mdev)) 2134 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 2135 log_bf_reg_size); 2136 resp->cache_line_size = cache_line_size(); 2137 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 2138 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 2139 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2140 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2141 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 2142 resp->cqe_version = context->cqe_version; 2143 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2144 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 2145 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2146 MLX5_CAP_GEN(dev->mdev, 2147 num_of_uars_per_page) : 1; 2148 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 2149 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 2150 resp->num_ports = dev->num_ports; 2151 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 2152 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 2153 2154 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 2155 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 2156 resp->eth_min_inline++; 2157 } 2158 2159 if (dev->mdev->clock_info) 2160 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2161 2162 /* 2163 * We don't want to expose information from the PCI bar that is located 2164 * after 4096 bytes, so if the arch only supports larger pages, let's 2165 * pretend we don't support reading the HCA's core clock. This is also 2166 * forced by mmap function. 2167 */ 2168 if (PAGE_SIZE <= 4096) { 2169 resp->comp_mask |= 2170 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2171 resp->hca_core_clock_offset = 2172 offsetof(struct mlx5_init_seg, 2173 internal_timer_h) % PAGE_SIZE; 2174 } 2175 2176 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2177 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2178 2179 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2180 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2181 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2182 resp->comp_mask |= 2183 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2184 2185 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2186 2187 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2188 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2189 2190 resp->comp_mask |= 2191 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2192 2193 return 0; 2194 } 2195 2196 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2197 { 2198 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2199 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2200 } 2201 2202 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2203 struct ib_udata *udata) 2204 { 2205 struct ib_device *ibdev = uctx->device; 2206 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2207 struct mlx5_ib_alloc_ucontext_req_v2 req; 2208 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2209 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2210 struct mlx5_bfreg_info *bfregi; 2211 int ver; 2212 int err; 2213 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2214 max_cqe_version); 2215 bool lib_uar_4k; 2216 bool lib_uar_dyn; 2217 2218 if (!dev->ib_active) 2219 return -EAGAIN; 2220 2221 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2222 ver = 0; 2223 else if (udata->inlen >= min_req_v2) 2224 ver = 2; 2225 else 2226 return -EINVAL; 2227 2228 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2229 if (err) 2230 return err; 2231 2232 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2233 return -EOPNOTSUPP; 2234 2235 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2236 return -EOPNOTSUPP; 2237 2238 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2239 MLX5_NON_FP_BFREGS_PER_UAR); 2240 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2241 return -EINVAL; 2242 2243 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2244 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2245 if (err < 0) 2246 goto out_ctx; 2247 context->devx_uid = err; 2248 2249 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2250 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2251 context->devx_uid); 2252 if (err) 2253 goto out_devx; 2254 } 2255 } 2256 2257 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2258 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2259 bfregi = &context->bfregi; 2260 2261 if (lib_uar_dyn) { 2262 bfregi->lib_uar_dyn = lib_uar_dyn; 2263 goto uar_done; 2264 } 2265 2266 /* updates req->total_num_bfregs */ 2267 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2268 if (err) 2269 goto out_ucap; 2270 2271 mutex_init(&bfregi->lock); 2272 bfregi->lib_uar_4k = lib_uar_4k; 2273 bfregi->count = kzalloc_objs(*bfregi->count, bfregi->total_num_bfregs); 2274 if (!bfregi->count) { 2275 err = -ENOMEM; 2276 goto out_ucap; 2277 } 2278 2279 bfregi->sys_pages = 2280 kzalloc_objs(*bfregi->sys_pages, bfregi->num_sys_pages); 2281 if (!bfregi->sys_pages) { 2282 err = -ENOMEM; 2283 goto out_count; 2284 } 2285 2286 err = allocate_uars(dev, context); 2287 if (err) 2288 goto out_sys_pages; 2289 2290 uar_done: 2291 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2292 context->devx_uid); 2293 if (err) 2294 goto out_uars; 2295 2296 INIT_LIST_HEAD(&context->db_page_list); 2297 mutex_init(&context->db_page_mutex); 2298 2299 context->cqe_version = min_t(__u8, 2300 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2301 req.max_cqe_version); 2302 2303 err = set_ucontext_resp(uctx, &resp); 2304 if (err) 2305 goto out_mdev; 2306 2307 resp.response_length = min(udata->outlen, sizeof(resp)); 2308 err = ib_respond_udata(udata, resp); 2309 if (err) 2310 goto out_mdev; 2311 2312 bfregi->ver = ver; 2313 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2314 context->lib_caps = req.lib_caps; 2315 print_lib_caps(dev, context->lib_caps); 2316 2317 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2318 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2319 2320 atomic_set(&context->tx_port_affinity, 2321 atomic_add_return( 2322 1, &dev->port[port].roce.tx_port_affinity)); 2323 } 2324 2325 return 0; 2326 2327 out_mdev: 2328 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2329 2330 out_uars: 2331 deallocate_uars(dev, context); 2332 2333 out_sys_pages: 2334 kfree(bfregi->sys_pages); 2335 2336 out_count: 2337 kfree(bfregi->count); 2338 2339 out_ucap: 2340 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2341 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2342 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2343 2344 out_devx: 2345 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2346 mlx5_ib_devx_destroy(dev, context->devx_uid); 2347 2348 out_ctx: 2349 return err; 2350 } 2351 2352 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2353 struct uverbs_attr_bundle *attrs) 2354 { 2355 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2356 int ret; 2357 2358 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2359 if (ret) 2360 return ret; 2361 2362 uctx_resp.response_length = 2363 min_t(size_t, 2364 uverbs_attr_get_len(attrs, 2365 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2366 sizeof(uctx_resp)); 2367 2368 ret = uverbs_copy_to_struct_or_zero(attrs, 2369 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2370 &uctx_resp, 2371 sizeof(uctx_resp)); 2372 return ret; 2373 } 2374 2375 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2376 { 2377 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2378 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2379 struct mlx5_bfreg_info *bfregi; 2380 2381 bfregi = &context->bfregi; 2382 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2383 2384 deallocate_uars(dev, context); 2385 kfree(bfregi->sys_pages); 2386 kfree(bfregi->count); 2387 2388 if (context->devx_uid) { 2389 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2390 mlx5_cmd_remove_privileged_uid(dev->mdev, 2391 context->devx_uid); 2392 mlx5_ib_devx_destroy(dev, context->devx_uid); 2393 } 2394 } 2395 2396 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2397 int uar_idx) 2398 { 2399 int fw_uars_per_page; 2400 2401 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2402 2403 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2404 } 2405 2406 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2407 int uar_idx) 2408 { 2409 unsigned int fw_uars_per_page; 2410 2411 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2412 MLX5_UARS_IN_PAGE : 1; 2413 2414 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2415 } 2416 2417 static int get_command(unsigned long offset) 2418 { 2419 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2420 } 2421 2422 static int get_arg(unsigned long offset) 2423 { 2424 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2425 } 2426 2427 static int get_index(unsigned long offset) 2428 { 2429 return get_arg(offset); 2430 } 2431 2432 /* Index resides in an extra byte to enable larger values than 255 */ 2433 static int get_extended_index(unsigned long offset) 2434 { 2435 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2436 } 2437 2438 2439 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2440 { 2441 } 2442 2443 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2444 { 2445 switch (cmd) { 2446 case MLX5_IB_MMAP_WC_PAGE: 2447 return "WC"; 2448 case MLX5_IB_MMAP_REGULAR_PAGE: 2449 return "best effort WC"; 2450 case MLX5_IB_MMAP_NC_PAGE: 2451 return "NC"; 2452 case MLX5_IB_MMAP_DEVICE_MEM: 2453 return "Device Memory"; 2454 default: 2455 return "Unknown"; 2456 } 2457 } 2458 2459 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2460 struct vm_area_struct *vma, 2461 struct mlx5_ib_ucontext *context) 2462 { 2463 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2464 !(vma->vm_flags & VM_SHARED)) 2465 return -EINVAL; 2466 2467 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2468 return -EOPNOTSUPP; 2469 2470 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2471 return -EPERM; 2472 vm_flags_clear(vma, VM_MAYWRITE); 2473 2474 if (!dev->mdev->clock_info) 2475 return -EOPNOTSUPP; 2476 2477 return vm_insert_page(vma, vma->vm_start, 2478 virt_to_page(dev->mdev->clock_info)); 2479 } 2480 2481 static int phys_addr_to_bar(struct pci_dev *pdev, phys_addr_t pa) 2482 { 2483 resource_size_t start, end; 2484 int bar; 2485 2486 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 2487 /* Skip BARs not present or not memory-mapped */ 2488 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) 2489 continue; 2490 2491 start = pci_resource_start(pdev, bar); 2492 end = pci_resource_end(pdev, bar); 2493 2494 if (!start || !end) 2495 continue; 2496 2497 if (pa >= start && pa <= end) 2498 return bar; 2499 } 2500 2501 return -1; 2502 } 2503 2504 static int mlx5_ib_mmap_get_pfns(struct rdma_user_mmap_entry *entry, 2505 struct phys_vec *phys_vec, 2506 struct p2pdma_provider **provider) 2507 { 2508 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2509 struct pci_dev *pdev = to_mdev(entry->ucontext->device)->mdev->pdev; 2510 int bar; 2511 2512 phys_vec->paddr = mentry->address; 2513 phys_vec->len = entry->npages * PAGE_SIZE; 2514 2515 bar = phys_addr_to_bar(pdev, phys_vec->paddr); 2516 if (bar < 0) 2517 return -EINVAL; 2518 2519 *provider = pcim_p2pdma_provider(pdev, bar); 2520 /* If the kernel was not compiled with CONFIG_PCI_P2PDMA the 2521 * functionality is not supported. 2522 */ 2523 if (!*provider) 2524 return -EOPNOTSUPP; 2525 2526 return 0; 2527 } 2528 2529 static struct rdma_user_mmap_entry * 2530 mlx5_ib_pgoff_to_mmap_entry(struct ib_ucontext *ucontext, off_t pg_off) 2531 { 2532 unsigned long entry_pgoff; 2533 unsigned long idx; 2534 u8 command; 2535 2536 pg_off = pg_off >> PAGE_SHIFT; 2537 command = get_command(pg_off); 2538 idx = get_extended_index(pg_off); 2539 2540 entry_pgoff = command << 16 | idx; 2541 2542 return rdma_user_mmap_entry_get_pgoff(ucontext, entry_pgoff); 2543 } 2544 2545 static void mlx5_ib_free_var_mmap_entry(struct mlx5_user_mmap_entry *mentry, 2546 struct mlx5_var_region *var_region) 2547 { 2548 mutex_lock(&var_region->bitmap_lock); 2549 clear_bit(mentry->page_idx, var_region->bitmap); 2550 mutex_unlock(&var_region->bitmap_lock); 2551 kfree(mentry); 2552 } 2553 2554 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2555 { 2556 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2557 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2558 struct mlx5_var_table *var_table = &dev->var_table; 2559 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2560 struct mlx5_var_region *var_region; 2561 2562 switch (mentry->mmap_flag) { 2563 case MLX5_IB_MMAP_TYPE_MEMIC: 2564 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2565 mlx5_ib_dm_mmap_free(dev, mentry); 2566 break; 2567 case MLX5_IB_MMAP_TYPE_VAR: 2568 var_region = &var_table->var_region; 2569 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2570 break; 2571 case MLX5_IB_MMAP_TYPE_TLP_VAR: 2572 var_region = &var_table->tlp_var_region; 2573 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2574 break; 2575 case MLX5_IB_MMAP_TYPE_UAR_WC: 2576 case MLX5_IB_MMAP_TYPE_UAR_NC: 2577 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2578 context->devx_uid); 2579 kfree(mentry); 2580 break; 2581 default: 2582 WARN_ON(true); 2583 } 2584 } 2585 2586 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2587 struct vm_area_struct *vma, 2588 struct mlx5_ib_ucontext *context) 2589 { 2590 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2591 int err; 2592 unsigned long idx; 2593 phys_addr_t pfn; 2594 pgprot_t prot; 2595 u32 bfreg_dyn_idx = 0; 2596 u32 uar_index; 2597 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2598 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2599 bfregi->num_static_sys_pages; 2600 2601 if (bfregi->lib_uar_dyn) 2602 return -EINVAL; 2603 2604 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2605 return -EINVAL; 2606 2607 if (dyn_uar) 2608 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2609 else 2610 idx = get_index(vma->vm_pgoff); 2611 2612 if (idx >= max_valid_idx) { 2613 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2614 idx, max_valid_idx); 2615 return -EINVAL; 2616 } 2617 2618 switch (cmd) { 2619 case MLX5_IB_MMAP_WC_PAGE: 2620 case MLX5_IB_MMAP_ALLOC_WC: 2621 case MLX5_IB_MMAP_REGULAR_PAGE: 2622 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2623 prot = pgprot_writecombine(vma->vm_page_prot); 2624 break; 2625 case MLX5_IB_MMAP_NC_PAGE: 2626 prot = pgprot_noncached(vma->vm_page_prot); 2627 break; 2628 default: 2629 return -EINVAL; 2630 } 2631 2632 if (dyn_uar) { 2633 int uars_per_page; 2634 2635 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2636 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2637 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2638 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2639 bfreg_dyn_idx, bfregi->total_num_bfregs); 2640 return -EINVAL; 2641 } 2642 2643 mutex_lock(&bfregi->lock); 2644 /* Fail if uar already allocated, first bfreg index of each 2645 * page holds its count. 2646 */ 2647 if (bfregi->count[bfreg_dyn_idx]) { 2648 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2649 mutex_unlock(&bfregi->lock); 2650 return -EINVAL; 2651 } 2652 2653 bfregi->count[bfreg_dyn_idx]++; 2654 mutex_unlock(&bfregi->lock); 2655 2656 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2657 context->devx_uid); 2658 if (err) { 2659 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2660 goto free_bfreg; 2661 } 2662 } else { 2663 uar_index = bfregi->sys_pages[idx]; 2664 } 2665 2666 pfn = uar_index2pfn(dev, uar_index); 2667 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2668 2669 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2670 prot, NULL); 2671 if (err) { 2672 mlx5_ib_err(dev, 2673 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2674 err, mmap_cmd2str(cmd)); 2675 goto err; 2676 } 2677 2678 if (dyn_uar) 2679 bfregi->sys_pages[idx] = uar_index; 2680 return 0; 2681 2682 err: 2683 if (!dyn_uar) 2684 return err; 2685 2686 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, context->devx_uid); 2687 2688 free_bfreg: 2689 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2690 2691 return err; 2692 } 2693 2694 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2695 { 2696 unsigned long idx; 2697 u8 command; 2698 2699 command = get_command(vma->vm_pgoff); 2700 idx = get_extended_index(vma->vm_pgoff); 2701 2702 return (command << 16 | idx); 2703 } 2704 2705 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2706 struct vm_area_struct *vma, 2707 struct ib_ucontext *ucontext) 2708 { 2709 struct mlx5_user_mmap_entry *mentry; 2710 struct rdma_user_mmap_entry *entry; 2711 unsigned long pgoff; 2712 pgprot_t prot; 2713 phys_addr_t pfn; 2714 int ret; 2715 2716 pgoff = mlx5_vma_to_pgoff(vma); 2717 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2718 if (!entry) 2719 return -EINVAL; 2720 2721 mentry = to_mmmap(entry); 2722 pfn = (mentry->address >> PAGE_SHIFT); 2723 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2724 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_TLP_VAR || 2725 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2726 prot = pgprot_noncached(vma->vm_page_prot); 2727 else 2728 prot = pgprot_writecombine(vma->vm_page_prot); 2729 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2730 entry->npages * PAGE_SIZE, 2731 prot, 2732 entry); 2733 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2734 return ret; 2735 } 2736 2737 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2738 { 2739 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2740 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2741 2742 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2743 (index & 0xFF)) << PAGE_SHIFT; 2744 } 2745 2746 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2747 { 2748 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2749 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2750 unsigned long command; 2751 phys_addr_t pfn; 2752 2753 command = get_command(vma->vm_pgoff); 2754 switch (command) { 2755 case MLX5_IB_MMAP_WC_PAGE: 2756 case MLX5_IB_MMAP_ALLOC_WC: 2757 if (!mlx5_wc_support_get(dev->mdev)) 2758 return -EPERM; 2759 fallthrough; 2760 case MLX5_IB_MMAP_NC_PAGE: 2761 case MLX5_IB_MMAP_REGULAR_PAGE: 2762 return uar_mmap(dev, command, vma, context); 2763 2764 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2765 return -ENOSYS; 2766 2767 case MLX5_IB_MMAP_CORE_CLOCK: 2768 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2769 return -EINVAL; 2770 2771 if (vma->vm_flags & VM_WRITE) 2772 return -EPERM; 2773 vm_flags_clear(vma, VM_MAYWRITE); 2774 2775 /* Don't expose to user-space information it shouldn't have */ 2776 if (PAGE_SIZE > 4096) 2777 return -EOPNOTSUPP; 2778 2779 pfn = (dev->mdev->bar_addr + 2780 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2781 PAGE_SHIFT; 2782 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2783 PAGE_SIZE, 2784 pgprot_noncached(vma->vm_page_prot), 2785 NULL); 2786 case MLX5_IB_MMAP_CLOCK_INFO: 2787 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2788 2789 default: 2790 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2791 } 2792 2793 return 0; 2794 } 2795 2796 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2797 { 2798 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2799 struct ib_device *ibdev = ibpd->device; 2800 struct mlx5_ib_alloc_pd_resp resp = {}; 2801 int err; 2802 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2803 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2804 u16 uid = 0; 2805 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2806 udata, struct mlx5_ib_ucontext, ibucontext); 2807 2808 uid = context ? context->devx_uid : 0; 2809 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2810 MLX5_SET(alloc_pd_in, in, uid, uid); 2811 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2812 if (err) 2813 return err; 2814 2815 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2816 pd->uid = uid; 2817 if (udata) { 2818 resp.pdn = pd->pdn; 2819 err = ib_respond_udata(udata, resp); 2820 if (err) { 2821 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2822 return err; 2823 } 2824 } 2825 2826 return 0; 2827 } 2828 2829 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2830 { 2831 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2832 struct mlx5_ib_pd *mpd = to_mpd(pd); 2833 2834 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2835 } 2836 2837 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2838 { 2839 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2840 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2841 int err; 2842 u16 uid; 2843 2844 uid = ibqp->pd ? 2845 to_mpd(ibqp->pd)->uid : 0; 2846 2847 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2848 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2849 return -EOPNOTSUPP; 2850 } 2851 2852 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2853 if (err) 2854 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2855 ibqp->qp_num, gid->raw); 2856 2857 return err; 2858 } 2859 2860 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2861 { 2862 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2863 int err; 2864 u16 uid; 2865 2866 uid = ibqp->pd ? 2867 to_mpd(ibqp->pd)->uid : 0; 2868 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2869 if (err) 2870 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2871 ibqp->qp_num, gid->raw); 2872 2873 return err; 2874 } 2875 2876 static int init_node_data(struct mlx5_ib_dev *dev) 2877 { 2878 int err; 2879 2880 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2881 if (err) 2882 return err; 2883 2884 dev->mdev->rev_id = dev->mdev->pdev->revision; 2885 2886 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2887 } 2888 2889 static ssize_t fw_pages_show(struct device *device, 2890 struct device_attribute *attr, char *buf) 2891 { 2892 struct mlx5_ib_dev *dev = 2893 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2894 2895 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2896 } 2897 static DEVICE_ATTR_RO(fw_pages); 2898 2899 static ssize_t reg_pages_show(struct device *device, 2900 struct device_attribute *attr, char *buf) 2901 { 2902 struct mlx5_ib_dev *dev = 2903 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2904 2905 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2906 } 2907 static DEVICE_ATTR_RO(reg_pages); 2908 2909 static ssize_t hca_type_show(struct device *device, 2910 struct device_attribute *attr, char *buf) 2911 { 2912 struct mlx5_ib_dev *dev = 2913 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2914 2915 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2916 } 2917 static DEVICE_ATTR_RO(hca_type); 2918 2919 static ssize_t hw_rev_show(struct device *device, 2920 struct device_attribute *attr, char *buf) 2921 { 2922 struct mlx5_ib_dev *dev = 2923 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2924 2925 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2926 } 2927 static DEVICE_ATTR_RO(hw_rev); 2928 2929 static ssize_t board_id_show(struct device *device, 2930 struct device_attribute *attr, char *buf) 2931 { 2932 struct mlx5_ib_dev *dev = 2933 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2934 2935 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2936 dev->mdev->board_id); 2937 } 2938 static DEVICE_ATTR_RO(board_id); 2939 2940 static struct attribute *mlx5_class_attributes[] = { 2941 &dev_attr_hw_rev.attr, 2942 &dev_attr_hca_type.attr, 2943 &dev_attr_board_id.attr, 2944 &dev_attr_fw_pages.attr, 2945 &dev_attr_reg_pages.attr, 2946 NULL, 2947 }; 2948 2949 static const struct attribute_group mlx5_attr_group = { 2950 .attrs = mlx5_class_attributes, 2951 }; 2952 2953 static void pkey_change_handler(struct work_struct *work) 2954 { 2955 struct mlx5_ib_port_resources *ports = 2956 container_of(work, struct mlx5_ib_port_resources, 2957 pkey_change_work); 2958 2959 if (!ports->gsi) 2960 /* 2961 * We got this event before device was fully configured 2962 * and MAD registration code wasn't called/finished yet. 2963 */ 2964 return; 2965 2966 mlx5_ib_gsi_pkey_change(ports->gsi); 2967 } 2968 2969 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2970 { 2971 struct mlx5_ib_qp *mqp; 2972 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2973 struct mlx5_core_cq *mcq; 2974 struct list_head cq_armed_list; 2975 unsigned long flags_qp; 2976 unsigned long flags_cq; 2977 unsigned long flags; 2978 2979 INIT_LIST_HEAD(&cq_armed_list); 2980 2981 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2982 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2983 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2984 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2985 if (mqp->sq.tail != mqp->sq.head) { 2986 send_mcq = to_mcq(mqp->ibqp.send_cq); 2987 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2988 if (send_mcq->mcq.comp && 2989 mqp->ibqp.send_cq->comp_handler) { 2990 if (!send_mcq->mcq.reset_notify_added) { 2991 send_mcq->mcq.reset_notify_added = 1; 2992 list_add_tail(&send_mcq->mcq.reset_notify, 2993 &cq_armed_list); 2994 } 2995 } 2996 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2997 } 2998 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2999 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3000 /* no handling is needed for SRQ */ 3001 if (!mqp->ibqp.srq) { 3002 if (mqp->rq.tail != mqp->rq.head) { 3003 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3004 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3005 if (recv_mcq->mcq.comp && 3006 mqp->ibqp.recv_cq->comp_handler) { 3007 if (!recv_mcq->mcq.reset_notify_added) { 3008 recv_mcq->mcq.reset_notify_added = 1; 3009 list_add_tail(&recv_mcq->mcq.reset_notify, 3010 &cq_armed_list); 3011 } 3012 } 3013 spin_unlock_irqrestore(&recv_mcq->lock, 3014 flags_cq); 3015 } 3016 } 3017 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3018 } 3019 /*At that point all inflight post send were put to be executed as of we 3020 * lock/unlock above locks Now need to arm all involved CQs. 3021 */ 3022 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3023 mcq->comp(mcq, NULL); 3024 } 3025 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3026 } 3027 3028 static void delay_drop_handler(struct work_struct *work) 3029 { 3030 int err; 3031 struct mlx5_ib_delay_drop *delay_drop = 3032 container_of(work, struct mlx5_ib_delay_drop, 3033 delay_drop_work); 3034 3035 atomic_inc(&delay_drop->events_cnt); 3036 3037 mutex_lock(&delay_drop->lock); 3038 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 3039 if (err) { 3040 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3041 delay_drop->timeout); 3042 delay_drop->activate = false; 3043 } 3044 mutex_unlock(&delay_drop->lock); 3045 } 3046 3047 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3048 struct ib_event *ibev) 3049 { 3050 u32 port = (eqe->data.port.port >> 4) & 0xf; 3051 3052 switch (eqe->sub_type) { 3053 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 3054 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3055 IB_LINK_LAYER_ETHERNET) 3056 schedule_work(&ibdev->delay_drop.delay_drop_work); 3057 break; 3058 default: /* do nothing */ 3059 return; 3060 } 3061 } 3062 3063 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3064 struct ib_event *ibev) 3065 { 3066 u32 port = (eqe->data.port.port >> 4) & 0xf; 3067 3068 ibev->element.port_num = port; 3069 3070 switch (eqe->sub_type) { 3071 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 3072 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 3073 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 3074 if (ibdev->ib_active) { 3075 struct ib_event speed_event = {}; 3076 3077 speed_event.device = &ibdev->ib_dev; 3078 speed_event.event = IB_EVENT_DEVICE_SPEED_CHANGE; 3079 ib_dispatch_event(&speed_event); 3080 } 3081 3082 /* In RoCE, port up/down events are handled in 3083 * mlx5_netdev_event(). 3084 */ 3085 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3086 IB_LINK_LAYER_ETHERNET) 3087 return -EINVAL; 3088 3089 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 3090 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3091 break; 3092 3093 case MLX5_PORT_CHANGE_SUBTYPE_LID: 3094 ibev->event = IB_EVENT_LID_CHANGE; 3095 break; 3096 3097 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 3098 ibev->event = IB_EVENT_PKEY_CHANGE; 3099 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3100 break; 3101 3102 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 3103 ibev->event = IB_EVENT_GID_CHANGE; 3104 break; 3105 3106 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 3107 ibev->event = IB_EVENT_CLIENT_REREGISTER; 3108 break; 3109 default: 3110 return -EINVAL; 3111 } 3112 3113 return 0; 3114 } 3115 3116 static void mlx5_ib_handle_event(struct work_struct *_work) 3117 { 3118 struct mlx5_ib_event_work *work = 3119 container_of(_work, struct mlx5_ib_event_work, work); 3120 struct mlx5_ib_dev *ibdev; 3121 struct ib_event ibev; 3122 3123 if (work->is_slave) { 3124 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 3125 if (!ibdev) 3126 goto out; 3127 } else { 3128 ibdev = work->dev; 3129 } 3130 3131 switch (work->event) { 3132 case MLX5_EVENT_TYPE_PORT_CHANGE: 3133 if (handle_port_change(ibdev, work->param, &ibev)) 3134 goto out; 3135 break; 3136 case MLX5_EVENT_TYPE_GENERAL_EVENT: 3137 handle_general_event(ibdev, work->param, &ibev); 3138 fallthrough; 3139 default: 3140 goto out; 3141 } 3142 3143 ibev.device = &ibdev->ib_dev; 3144 3145 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3146 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3147 goto out; 3148 } 3149 3150 if (ibdev->ib_active) 3151 ib_dispatch_event(&ibev); 3152 3153 out: 3154 kfree(work); 3155 } 3156 3157 static int mlx5_ib_event(struct notifier_block *nb, 3158 unsigned long event, void *param) 3159 { 3160 struct mlx5_ib_event_work *work; 3161 3162 work = kmalloc_obj(*work, GFP_ATOMIC); 3163 if (!work) 3164 return NOTIFY_DONE; 3165 3166 INIT_WORK(&work->work, mlx5_ib_handle_event); 3167 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 3168 work->is_slave = false; 3169 work->param = param; 3170 work->event = event; 3171 3172 queue_work(mlx5_ib_event_wq, &work->work); 3173 3174 return NOTIFY_OK; 3175 } 3176 3177 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 3178 unsigned long event, void *param) 3179 { 3180 struct mlx5_ib_event_work *work; 3181 3182 work = kmalloc_obj(*work, GFP_ATOMIC); 3183 if (!work) 3184 return NOTIFY_DONE; 3185 3186 INIT_WORK(&work->work, mlx5_ib_handle_event); 3187 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 3188 work->is_slave = true; 3189 work->param = param; 3190 work->event = event; 3191 queue_work(mlx5_ib_event_wq, &work->work); 3192 3193 return NOTIFY_OK; 3194 } 3195 3196 static void mlx5_ib_handle_sys_error_event(struct work_struct *_work) 3197 { 3198 struct mlx5_ib_event_work *work = 3199 container_of(_work, struct mlx5_ib_event_work, work); 3200 struct mlx5_ib_dev *ibdev = work->dev; 3201 struct ib_event ibev; 3202 3203 ibev.event = IB_EVENT_DEVICE_FATAL; 3204 mlx5_ib_handle_internal_error(ibdev); 3205 ibev.element.port_num = (u8)(unsigned long)work->param; 3206 ibev.device = &ibdev->ib_dev; 3207 3208 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3209 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3210 goto out; 3211 } 3212 3213 if (ibdev->ib_active) 3214 ib_dispatch_event(&ibev); 3215 3216 ibdev->ib_active = false; 3217 out: 3218 kfree(work); 3219 } 3220 3221 static int mlx5_ib_sys_error_event(struct notifier_block *nb, 3222 unsigned long event, void *param) 3223 { 3224 struct mlx5_ib_event_work *work; 3225 3226 if (event != MLX5_DEV_EVENT_SYS_ERROR) 3227 return NOTIFY_DONE; 3228 3229 work = kmalloc_obj(*work, GFP_ATOMIC); 3230 if (!work) 3231 return NOTIFY_DONE; 3232 3233 INIT_WORK(&work->work, mlx5_ib_handle_sys_error_event); 3234 work->dev = container_of(nb, struct mlx5_ib_dev, sys_error_events); 3235 work->is_slave = false; 3236 work->param = param; 3237 work->event = event; 3238 3239 queue_work(mlx5_ib_event_wq, &work->work); 3240 3241 return NOTIFY_OK; 3242 } 3243 3244 static int mlx5_ib_stage_sys_error_notifier_init(struct mlx5_ib_dev *dev) 3245 { 3246 dev->sys_error_events.notifier_call = mlx5_ib_sys_error_event; 3247 mlx5_notifier_register(dev->mdev, &dev->sys_error_events); 3248 return 0; 3249 } 3250 3251 static void mlx5_ib_stage_sys_error_notifier_cleanup(struct mlx5_ib_dev *dev) 3252 { 3253 mlx5_notifier_unregister(dev->mdev, &dev->sys_error_events); 3254 } 3255 3256 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 3257 { 3258 struct mlx5_hca_vport_context vport_ctx; 3259 int err; 3260 3261 *num_plane = 0; 3262 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 3263 return 0; 3264 3265 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 3266 if (err) 3267 return err; 3268 3269 *num_plane = vport_ctx.num_plane; 3270 return 0; 3271 } 3272 3273 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3274 { 3275 struct mlx5_hca_vport_context vport_ctx; 3276 int err; 3277 int port; 3278 3279 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 3280 return 0; 3281 3282 for (port = 1; port <= dev->num_ports; port++) { 3283 if (dev->num_plane) { 3284 dev->port_caps[port - 1].has_smi = false; 3285 continue; 3286 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 3287 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 3288 dev->port_caps[port - 1].has_smi = true; 3289 continue; 3290 } 3291 3292 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 3293 &vport_ctx); 3294 if (err) { 3295 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3296 port, err); 3297 return err; 3298 } 3299 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3300 } 3301 3302 return 0; 3303 } 3304 3305 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3306 { 3307 unsigned int port; 3308 3309 rdma_for_each_port (&dev->ib_dev, port) 3310 mlx5_query_ext_port_caps(dev, port); 3311 } 3312 3313 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3314 { 3315 switch (umr_fence_cap) { 3316 case MLX5_CAP_UMR_FENCE_NONE: 3317 return MLX5_FENCE_MODE_NONE; 3318 case MLX5_CAP_UMR_FENCE_SMALL: 3319 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3320 default: 3321 return MLX5_FENCE_MODE_STRONG_ORDERING; 3322 } 3323 } 3324 3325 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3326 { 3327 struct mlx5_ib_resources *devr = &dev->devr; 3328 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3329 struct ib_device *ibdev; 3330 struct ib_pd *pd; 3331 struct ib_cq *cq; 3332 int ret = 0; 3333 3334 3335 /* 3336 * devr->c0 is set once, never changed until device unload. 3337 * Avoid taking the mutex if initialization is already done. 3338 */ 3339 if (smp_load_acquire(&devr->c0)) 3340 return 0; 3341 3342 mutex_lock(&devr->cq_lock); 3343 if (devr->c0) 3344 goto unlock; 3345 3346 ibdev = &dev->ib_dev; 3347 pd = ib_alloc_pd(ibdev, 0); 3348 if (IS_ERR(pd)) { 3349 ret = PTR_ERR(pd); 3350 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n", 3351 pd); 3352 goto unlock; 3353 } 3354 3355 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3356 if (IS_ERR(cq)) { 3357 ret = PTR_ERR(cq); 3358 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n", 3359 cq); 3360 ib_dealloc_pd(pd); 3361 goto unlock; 3362 } 3363 3364 devr->p0 = pd; 3365 smp_store_release(&devr->c0, cq); 3366 3367 unlock: 3368 mutex_unlock(&devr->cq_lock); 3369 return ret; 3370 } 3371 3372 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3373 { 3374 struct mlx5_ib_resources *devr = &dev->devr; 3375 struct ib_srq_init_attr attr; 3376 struct ib_srq *s0, *s1; 3377 int ret = 0; 3378 3379 /* 3380 * devr->s1 is set once, never changed until device unload. 3381 * Avoid taking the mutex if initialization is already done. 3382 */ 3383 if (smp_load_acquire(&devr->s1)) 3384 return 0; 3385 3386 mutex_lock(&devr->srq_lock); 3387 if (devr->s1) 3388 goto unlock; 3389 3390 ret = mlx5_ib_dev_res_cq_init(dev); 3391 if (ret) 3392 goto unlock; 3393 3394 memset(&attr, 0, sizeof(attr)); 3395 attr.attr.max_sge = 1; 3396 attr.attr.max_wr = 1; 3397 attr.srq_type = IB_SRQT_XRC; 3398 attr.ext.cq = devr->c0; 3399 3400 s0 = ib_create_srq(devr->p0, &attr); 3401 if (IS_ERR(s0)) { 3402 ret = PTR_ERR(s0); 3403 mlx5_ib_err(dev, 3404 "Couldn't create SRQ 0 for res init, err=%pe\n", 3405 s0); 3406 goto unlock; 3407 } 3408 3409 memset(&attr, 0, sizeof(attr)); 3410 attr.attr.max_sge = 1; 3411 attr.attr.max_wr = 1; 3412 attr.srq_type = IB_SRQT_BASIC; 3413 3414 s1 = ib_create_srq(devr->p0, &attr); 3415 if (IS_ERR(s1)) { 3416 ret = PTR_ERR(s1); 3417 mlx5_ib_err(dev, 3418 "Couldn't create SRQ 1 for res init, err=%pe\n", 3419 s1); 3420 ib_destroy_srq(s0); 3421 goto unlock; 3422 } 3423 3424 devr->s0 = s0; 3425 smp_store_release(&devr->s1, s1); 3426 3427 unlock: 3428 mutex_unlock(&devr->srq_lock); 3429 return ret; 3430 } 3431 3432 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3433 { 3434 struct mlx5_ib_resources *devr = &dev->devr; 3435 int ret; 3436 3437 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3438 return -EOPNOTSUPP; 3439 3440 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3441 if (ret) 3442 return ret; 3443 3444 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3445 if (ret) { 3446 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3447 return ret; 3448 } 3449 3450 mutex_init(&devr->cq_lock); 3451 mutex_init(&devr->srq_lock); 3452 3453 return 0; 3454 } 3455 3456 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3457 { 3458 struct mlx5_ib_resources *devr = &dev->devr; 3459 3460 /* After s0/s1 init, they are not unset during the device lifetime. */ 3461 if (devr->s1) { 3462 ib_destroy_srq(devr->s1); 3463 ib_destroy_srq(devr->s0); 3464 } 3465 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3466 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3467 /* After p0/c0 init, they are not unset during the device lifetime. */ 3468 if (devr->c0) { 3469 ib_destroy_cq(devr->c0); 3470 ib_dealloc_pd(devr->p0); 3471 } 3472 mutex_destroy(&devr->cq_lock); 3473 mutex_destroy(&devr->srq_lock); 3474 } 3475 3476 static int 3477 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3478 { 3479 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3480 struct mlx5_core_dev *mdev = dev->mdev; 3481 bool ro_supp = false; 3482 void *mkc; 3483 u32 mkey; 3484 u32 pdn; 3485 u32 *in; 3486 int err; 3487 3488 err = mlx5_core_alloc_pd(mdev, &pdn); 3489 if (err) 3490 return err; 3491 3492 in = kvzalloc(inlen, GFP_KERNEL); 3493 if (!in) { 3494 err = -ENOMEM; 3495 goto err; 3496 } 3497 3498 MLX5_SET(create_mkey_in, in, data_direct, 1); 3499 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3500 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3501 MLX5_SET(mkc, mkc, lw, 1); 3502 MLX5_SET(mkc, mkc, lr, 1); 3503 MLX5_SET(mkc, mkc, rw, 1); 3504 MLX5_SET(mkc, mkc, rr, 1); 3505 MLX5_SET(mkc, mkc, a, 1); 3506 MLX5_SET(mkc, mkc, pd, pdn); 3507 MLX5_SET(mkc, mkc, length64, 1); 3508 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3509 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3510 if (err) 3511 goto err_mkey; 3512 3513 dev->ddr.mkey = mkey; 3514 dev->ddr.pdn = pdn; 3515 3516 /* create another mkey with RO support */ 3517 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { 3518 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 3519 ro_supp = true; 3520 } 3521 3522 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { 3523 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 3524 ro_supp = true; 3525 } 3526 3527 if (ro_supp) { 3528 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3529 /* RO is defined as best effort */ 3530 if (!err) { 3531 dev->ddr.mkey_ro = mkey; 3532 dev->ddr.mkey_ro_valid = true; 3533 } 3534 } 3535 3536 kvfree(in); 3537 return 0; 3538 3539 err_mkey: 3540 kvfree(in); 3541 err: 3542 mlx5_core_dealloc_pd(mdev, pdn); 3543 return err; 3544 } 3545 3546 static void 3547 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3548 { 3549 3550 if (dev->ddr.mkey_ro_valid) 3551 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro); 3552 3553 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3554 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3555 } 3556 3557 static u32 get_core_cap_flags(struct ib_device *ibdev, 3558 struct mlx5_hca_vport_context *rep) 3559 { 3560 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3561 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3562 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3563 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3564 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3565 u32 ret = 0; 3566 3567 if (rep->grh_required) 3568 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3569 3570 if (dev->num_plane) 3571 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3572 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3573 RDMA_CORE_CAP_AF_IB; 3574 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3575 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3576 3577 if (ll == IB_LINK_LAYER_INFINIBAND) 3578 return ret | RDMA_CORE_PORT_IBA_IB; 3579 3580 if (raw_support) 3581 ret |= RDMA_CORE_PORT_RAW_PACKET; 3582 3583 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3584 return ret; 3585 3586 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3587 return ret; 3588 3589 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3590 ret |= RDMA_CORE_PORT_IBA_ROCE; 3591 3592 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3593 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3594 3595 return ret; 3596 } 3597 3598 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3599 struct ib_port_immutable *immutable) 3600 { 3601 struct ib_port_attr attr; 3602 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3603 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3604 struct mlx5_hca_vport_context rep = {0}; 3605 int err; 3606 3607 err = ib_query_port(ibdev, port_num, &attr); 3608 if (err) 3609 return err; 3610 3611 if (ll == IB_LINK_LAYER_INFINIBAND) { 3612 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3613 port_num = smi_to_native_portnum(dev, port_num); 3614 3615 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3616 &rep); 3617 if (err) 3618 return err; 3619 } 3620 3621 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3622 immutable->gid_tbl_len = attr.gid_tbl_len; 3623 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3624 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3625 3626 return 0; 3627 } 3628 3629 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3630 struct ib_port_immutable *immutable) 3631 { 3632 struct ib_port_attr attr; 3633 int err; 3634 3635 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3636 3637 err = ib_query_port(ibdev, port_num, &attr); 3638 if (err) 3639 return err; 3640 3641 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3642 immutable->gid_tbl_len = attr.gid_tbl_len; 3643 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3644 3645 return 0; 3646 } 3647 3648 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3649 { 3650 struct mlx5_ib_dev *dev = 3651 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3652 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3653 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3654 fw_rev_sub(dev->mdev)); 3655 } 3656 3657 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3658 { 3659 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3660 lag_events); 3661 struct mlx5_core_dev *mdev = dev->mdev; 3662 struct ib_device *ibdev = &dev->ib_dev; 3663 struct net_device *old_ndev = NULL; 3664 struct mlx5_ib_port *port; 3665 struct net_device *ndev; 3666 u32 portnum = 0; 3667 int ret = 0; 3668 int i; 3669 3670 switch (event) { 3671 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3672 ndev = data; 3673 if (ndev) { 3674 if (!mlx5_lag_is_roce(mdev)) { 3675 // sriov lag 3676 for (i = 0; i < dev->num_ports; i++) { 3677 port = &dev->port[i]; 3678 if (port->rep && port->rep->vport == 3679 MLX5_VPORT_UPLINK) { 3680 portnum = i; 3681 break; 3682 } 3683 } 3684 } 3685 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3686 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3687 if (ret) 3688 goto out; 3689 3690 if (old_ndev) 3691 roce_del_all_netdev_gids(ibdev, portnum + 1, 3692 old_ndev); 3693 rdma_roce_rescan_port(ibdev, portnum + 1); 3694 } 3695 break; 3696 default: 3697 return NOTIFY_DONE; 3698 } 3699 3700 out: 3701 dev_put(old_ndev); 3702 return notifier_from_errno(ret); 3703 } 3704 3705 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3706 { 3707 dev->lag_events.notifier_call = lag_event; 3708 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3709 &dev->lag_events); 3710 } 3711 3712 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3713 { 3714 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3715 &dev->lag_events); 3716 } 3717 3718 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3719 { 3720 struct mlx5_flow_table_attr ft_attr = {}; 3721 struct mlx5_core_dev *mdev = dev->mdev; 3722 struct mlx5_flow_namespace *ns; 3723 int err; 3724 3725 ns = mlx5_get_flow_namespace(mdev, MLX5_FLOW_NAMESPACE_LAG); 3726 if (!ns || !mlx5_lag_is_active(mdev)) 3727 return 0; 3728 3729 err = mlx5_cmd_create_vport_lag(mdev); 3730 if (err) 3731 return err; 3732 3733 ft_attr.level = 0; 3734 ft_attr.prio = 0; 3735 ft_attr.max_fte = dev->num_ports; 3736 3737 err = mlx5_lag_demux_init(mdev, &ft_attr); 3738 if (err) 3739 goto err_destroy_vport_lag; 3740 3741 mlx5e_lag_event_register(dev); 3742 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3743 dev->lag_active = true; 3744 return 0; 3745 3746 err_destroy_vport_lag: 3747 mlx5_cmd_destroy_vport_lag(mdev); 3748 return err; 3749 } 3750 3751 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3752 { 3753 struct mlx5_core_dev *mdev = dev->mdev; 3754 3755 if (dev->lag_active) { 3756 dev->lag_active = false; 3757 3758 mlx5e_lag_event_unregister(dev); 3759 mlx5_lag_demux_cleanup(mdev); 3760 3761 mlx5_cmd_destroy_vport_lag(mdev); 3762 } 3763 } 3764 3765 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3766 struct net_device *netdev) 3767 { 3768 int err; 3769 3770 if (roce->tracking_netdev) 3771 return; 3772 roce->tracking_netdev = netdev; 3773 roce->nb.notifier_call = mlx5_netdev_event; 3774 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3775 WARN_ON(err); 3776 } 3777 3778 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3779 { 3780 if (!roce->tracking_netdev) 3781 return; 3782 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3783 &roce->nn); 3784 roce->tracking_netdev = NULL; 3785 } 3786 3787 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3788 unsigned long event, void *data) 3789 { 3790 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3791 struct net_device *netdev = data; 3792 3793 switch (event) { 3794 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3795 if (netdev) 3796 mlx5_netdev_notifier_register(roce, netdev); 3797 else 3798 mlx5_netdev_notifier_unregister(roce); 3799 break; 3800 default: 3801 return NOTIFY_DONE; 3802 } 3803 3804 return NOTIFY_OK; 3805 } 3806 3807 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3808 { 3809 struct mlx5_roce *roce = &dev->port[port_num].roce; 3810 3811 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3812 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3813 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3814 } 3815 3816 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3817 { 3818 struct mlx5_roce *roce = &dev->port[port_num].roce; 3819 3820 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3821 mlx5_netdev_notifier_unregister(roce); 3822 } 3823 3824 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3825 { 3826 int err; 3827 3828 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3829 err = mlx5_nic_vport_enable_roce(dev->mdev); 3830 if (err) 3831 return err; 3832 } 3833 3834 err = mlx5_eth_lag_init(dev); 3835 if (err) 3836 goto err_disable_roce; 3837 3838 return 0; 3839 3840 err_disable_roce: 3841 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3842 mlx5_nic_vport_disable_roce(dev->mdev); 3843 3844 return err; 3845 } 3846 3847 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3848 { 3849 mlx5_eth_lag_cleanup(dev); 3850 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3851 mlx5_nic_vport_disable_roce(dev->mdev); 3852 } 3853 3854 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3855 enum rdma_netdev_t type, 3856 struct rdma_netdev_alloc_params *params) 3857 { 3858 if (type != RDMA_NETDEV_IPOIB) 3859 return -EOPNOTSUPP; 3860 3861 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3862 } 3863 3864 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3865 size_t count, loff_t *pos) 3866 { 3867 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3868 char lbuf[20]; 3869 int len; 3870 3871 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3872 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3873 } 3874 3875 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3876 size_t count, loff_t *pos) 3877 { 3878 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3879 u32 timeout; 3880 u32 var; 3881 3882 if (kstrtouint_from_user(buf, count, 0, &var)) 3883 return -EFAULT; 3884 3885 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3886 1000); 3887 if (timeout != var) 3888 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3889 timeout); 3890 3891 delay_drop->timeout = timeout; 3892 3893 return count; 3894 } 3895 3896 static const struct file_operations fops_delay_drop_timeout = { 3897 .owner = THIS_MODULE, 3898 .open = simple_open, 3899 .write = delay_drop_timeout_write, 3900 .read = delay_drop_timeout_read, 3901 }; 3902 3903 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3904 struct mlx5_ib_multiport_info *mpi) 3905 { 3906 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3907 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3908 int comps; 3909 int err; 3910 int i; 3911 3912 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3913 3914 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3915 3916 mlx5_core_mp_event_replay(ibdev->mdev, 3917 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3918 NULL); 3919 mlx5_core_mp_event_replay(mpi->mdev, 3920 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3921 NULL); 3922 3923 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3924 3925 spin_lock(&port->mp.mpi_lock); 3926 if (!mpi->ibdev) { 3927 spin_unlock(&port->mp.mpi_lock); 3928 return; 3929 } 3930 3931 mpi->ibdev = NULL; 3932 3933 spin_unlock(&port->mp.mpi_lock); 3934 if (mpi->mdev_events.notifier_call) 3935 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3936 mpi->mdev_events.notifier_call = NULL; 3937 mlx5_mdev_netdev_untrack(ibdev, port_num); 3938 spin_lock(&port->mp.mpi_lock); 3939 3940 comps = mpi->mdev_refcnt; 3941 if (comps) { 3942 mpi->unaffiliate = true; 3943 init_completion(&mpi->unref_comp); 3944 spin_unlock(&port->mp.mpi_lock); 3945 3946 for (i = 0; i < comps; i++) 3947 wait_for_completion(&mpi->unref_comp); 3948 3949 spin_lock(&port->mp.mpi_lock); 3950 mpi->unaffiliate = false; 3951 } 3952 3953 port->mp.mpi = NULL; 3954 3955 spin_unlock(&port->mp.mpi_lock); 3956 3957 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3958 3959 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3960 /* Log an error, still needed to cleanup the pointers and add 3961 * it back to the list. 3962 */ 3963 if (err) 3964 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3965 port_num + 1); 3966 3967 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3968 } 3969 3970 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3971 struct mlx5_ib_multiport_info *mpi) 3972 { 3973 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3974 u64 key; 3975 int err; 3976 3977 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3978 3979 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3980 if (ibdev->port[port_num].mp.mpi) { 3981 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3982 port_num + 1); 3983 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3984 return false; 3985 } 3986 3987 ibdev->port[port_num].mp.mpi = mpi; 3988 mpi->ibdev = ibdev; 3989 mpi->mdev_events.notifier_call = NULL; 3990 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3991 3992 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3993 if (err) 3994 goto unbind; 3995 3996 mlx5_mdev_netdev_track(ibdev, port_num); 3997 3998 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3999 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 4000 4001 mlx5_ib_init_cong_debugfs(ibdev, port_num); 4002 4003 key = mpi->mdev->priv.adev_idx; 4004 mlx5_core_mp_event_replay(mpi->mdev, 4005 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 4006 &key); 4007 mlx5_core_mp_event_replay(ibdev->mdev, 4008 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 4009 &key); 4010 4011 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 4012 if (err) 4013 goto unbind; 4014 4015 return true; 4016 4017 unbind: 4018 mlx5_ib_unbind_slave_port(ibdev, mpi); 4019 return false; 4020 } 4021 4022 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 4023 { 4024 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 4025 int ret; 4026 4027 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 4028 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 4029 return 0; 4030 4031 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 4032 if (ret) 4033 return ret; 4034 4035 ret = mlx5_ib_create_data_direct_resources(dev); 4036 if (ret) 4037 return ret; 4038 4039 INIT_LIST_HEAD(&dev->data_direct_mr_list); 4040 ret = mlx5_data_direct_ib_reg(dev, vuid); 4041 if (ret) 4042 mlx5_ib_free_data_direct_resources(dev); 4043 4044 return ret; 4045 } 4046 4047 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 4048 { 4049 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 4050 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 4051 return; 4052 4053 mlx5_data_direct_ib_unreg(dev); 4054 mlx5_ib_free_data_direct_resources(dev); 4055 } 4056 4057 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4058 { 4059 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4060 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4061 port_num + 1); 4062 struct mlx5_ib_multiport_info *mpi; 4063 int err; 4064 u32 i; 4065 4066 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4067 return 0; 4068 4069 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4070 &dev->sys_image_guid); 4071 if (err) 4072 return err; 4073 4074 err = mlx5_nic_vport_enable_roce(dev->mdev); 4075 if (err) 4076 return err; 4077 4078 mutex_lock(&mlx5_ib_multiport_mutex); 4079 for (i = 0; i < dev->num_ports; i++) { 4080 bool bound = false; 4081 4082 /* build a stub multiport info struct for the native port. */ 4083 if (i == port_num) { 4084 mpi = kzalloc_obj(*mpi); 4085 if (!mpi) { 4086 mutex_unlock(&mlx5_ib_multiport_mutex); 4087 mlx5_nic_vport_disable_roce(dev->mdev); 4088 return -ENOMEM; 4089 } 4090 4091 mpi->is_master = true; 4092 mpi->mdev = dev->mdev; 4093 mpi->sys_image_guid = dev->sys_image_guid; 4094 dev->port[i].mp.mpi = mpi; 4095 mpi->ibdev = dev; 4096 mpi = NULL; 4097 continue; 4098 } 4099 4100 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4101 list) { 4102 if (dev->sys_image_guid == mpi->sys_image_guid && 4103 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 4104 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 4105 bound = mlx5_ib_bind_slave_port(dev, mpi); 4106 } 4107 4108 if (bound) { 4109 dev_dbg(mpi->mdev->device, 4110 "removing port from unaffiliated list.\n"); 4111 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4112 list_del(&mpi->list); 4113 break; 4114 } 4115 } 4116 if (!bound) 4117 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4118 i + 1); 4119 } 4120 4121 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4122 mutex_unlock(&mlx5_ib_multiport_mutex); 4123 return err; 4124 } 4125 4126 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4127 { 4128 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4129 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4130 port_num + 1); 4131 u32 i; 4132 4133 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4134 return; 4135 4136 mutex_lock(&mlx5_ib_multiport_mutex); 4137 for (i = 0; i < dev->num_ports; i++) { 4138 if (dev->port[i].mp.mpi) { 4139 /* Destroy the native port stub */ 4140 if (i == port_num) { 4141 kfree(dev->port[i].mp.mpi); 4142 dev->port[i].mp.mpi = NULL; 4143 } else { 4144 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 4145 i + 1); 4146 list_add_tail(&dev->port[i].mp.mpi->list, 4147 &mlx5_ib_unaffiliated_port_list); 4148 mlx5_ib_unbind_slave_port(dev, 4149 dev->port[i].mp.mpi); 4150 } 4151 } 4152 } 4153 4154 mlx5_ib_dbg(dev, "removing from devlist\n"); 4155 list_del(&dev->ib_dev_list); 4156 mutex_unlock(&mlx5_ib_multiport_mutex); 4157 4158 mlx5_nic_vport_disable_roce(dev->mdev); 4159 } 4160 4161 static int mmap_obj_cleanup(struct ib_uobject *uobject, 4162 enum rdma_remove_reason why, 4163 struct uverbs_attr_bundle *attrs) 4164 { 4165 struct mlx5_user_mmap_entry *obj = uobject->object; 4166 4167 rdma_user_mmap_entry_remove(&obj->rdma_entry); 4168 return 0; 4169 } 4170 4171 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 4172 struct mlx5_user_mmap_entry *entry, 4173 size_t length) 4174 { 4175 return rdma_user_mmap_entry_insert_range( 4176 &c->ibucontext, &entry->rdma_entry, length, 4177 (MLX5_IB_MMAP_OFFSET_START << 16), 4178 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 4179 } 4180 4181 static struct mlx5_user_mmap_entry * 4182 alloc_var_entry(struct mlx5_ib_ucontext *c, u32 flags) 4183 { 4184 struct mlx5_user_mmap_entry *entry; 4185 struct mlx5_var_region *var_region; 4186 struct mlx5_var_table *var_table; 4187 u32 page_idx; 4188 int err; 4189 4190 var_table = &to_mdev(c->ibucontext.device)->var_table; 4191 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) 4192 var_region = &var_table->tlp_var_region; 4193 else 4194 var_region = &var_table->var_region; 4195 4196 entry = kzalloc_obj(*entry); 4197 if (!entry) 4198 return ERR_PTR(-ENOMEM); 4199 4200 mutex_lock(&var_region->bitmap_lock); 4201 page_idx = find_first_zero_bit(var_region->bitmap, 4202 var_region->num_var_hw_entries); 4203 if (page_idx >= var_region->num_var_hw_entries) { 4204 err = -ENOSPC; 4205 mutex_unlock(&var_region->bitmap_lock); 4206 goto end; 4207 } 4208 4209 set_bit(page_idx, var_region->bitmap); 4210 mutex_unlock(&var_region->bitmap_lock); 4211 4212 entry->address = var_region->hw_start_addr + 4213 (page_idx * var_region->stride_size); 4214 entry->page_idx = page_idx; 4215 entry->mmap_flag = flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP ? 4216 MLX5_IB_MMAP_TYPE_TLP_VAR : 4217 MLX5_IB_MMAP_TYPE_VAR; 4218 4219 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 4220 var_region->stride_size); 4221 if (err) 4222 goto err_insert; 4223 4224 return entry; 4225 4226 err_insert: 4227 mutex_lock(&var_region->bitmap_lock); 4228 clear_bit(page_idx, var_region->bitmap); 4229 mutex_unlock(&var_region->bitmap_lock); 4230 end: 4231 kfree(entry); 4232 return ERR_PTR(err); 4233 } 4234 4235 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 4236 struct uverbs_attr_bundle *attrs) 4237 { 4238 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4239 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4240 struct mlx5_user_mmap_entry *entry; 4241 struct mlx5_ib_ucontext *c; 4242 u64 mmap_offset; 4243 u32 flags = 0; 4244 u32 length; 4245 int err; 4246 4247 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4248 if (IS_ERR(c)) 4249 return PTR_ERR(c); 4250 4251 err = uverbs_get_flags32(&flags, attrs, 4252 MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4253 MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP); 4254 if (err) 4255 return err; 4256 4257 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) { 4258 if (!MLX5_CAP_GEN(to_mdev(c->ibucontext.device)->mdev, 4259 tlp_device_emulation_manager)) 4260 return -EOPNOTSUPP; 4261 } else { 4262 if (!(MLX5_CAP_GEN_64(to_mdev(c->ibucontext.device)->mdev, 4263 general_obj_types) & 4264 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q)) 4265 return -EOPNOTSUPP; 4266 } 4267 4268 entry = alloc_var_entry(c, flags); 4269 if (IS_ERR(entry)) 4270 return PTR_ERR(entry); 4271 4272 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4273 length = entry->rdma_entry.npages * PAGE_SIZE; 4274 uobj->object = entry; 4275 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4276 4277 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4278 &mmap_offset, sizeof(mmap_offset)); 4279 if (err) 4280 return err; 4281 4282 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4283 &entry->page_idx, sizeof(entry->page_idx)); 4284 if (err) 4285 return err; 4286 4287 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4288 &length, sizeof(length)); 4289 return err; 4290 } 4291 4292 DECLARE_UVERBS_NAMED_METHOD( 4293 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 4294 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 4295 MLX5_IB_OBJECT_VAR, 4296 UVERBS_ACCESS_NEW, 4297 UA_MANDATORY), 4298 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4299 enum mlx5_ib_uapi_var_alloc_flags, 4300 UA_OPTIONAL), 4301 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4302 UVERBS_ATTR_TYPE(u32), 4303 UA_MANDATORY), 4304 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4305 UVERBS_ATTR_TYPE(u32), 4306 UA_MANDATORY), 4307 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4308 UVERBS_ATTR_TYPE(u64), 4309 UA_MANDATORY)); 4310 4311 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4312 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 4313 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 4314 MLX5_IB_OBJECT_VAR, 4315 UVERBS_ACCESS_DESTROY, 4316 UA_MANDATORY)); 4317 4318 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 4319 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4320 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 4321 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 4322 4323 static bool var_is_supported(struct ib_device *device) 4324 { 4325 struct mlx5_ib_dev *dev = to_mdev(device); 4326 4327 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4328 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) || 4329 MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager); 4330 } 4331 4332 static struct mlx5_user_mmap_entry * 4333 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4334 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4335 { 4336 struct mlx5_user_mmap_entry *entry; 4337 struct mlx5_ib_dev *dev; 4338 u32 uar_index; 4339 int err; 4340 4341 entry = kzalloc_obj(*entry); 4342 if (!entry) 4343 return ERR_PTR(-ENOMEM); 4344 4345 dev = to_mdev(c->ibucontext.device); 4346 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4347 if (err) 4348 goto end; 4349 4350 entry->page_idx = uar_index; 4351 entry->address = uar_index2paddress(dev, uar_index); 4352 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4353 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4354 else 4355 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4356 4357 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4358 if (err) 4359 goto err_insert; 4360 4361 return entry; 4362 4363 err_insert: 4364 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4365 end: 4366 kfree(entry); 4367 return ERR_PTR(err); 4368 } 4369 4370 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4371 struct uverbs_attr_bundle *attrs) 4372 { 4373 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4374 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4375 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4376 struct mlx5_ib_ucontext *c; 4377 struct mlx5_user_mmap_entry *entry; 4378 u64 mmap_offset; 4379 u32 length; 4380 int err; 4381 4382 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4383 if (IS_ERR(c)) 4384 return PTR_ERR(c); 4385 4386 err = uverbs_get_const(&alloc_type, attrs, 4387 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4388 if (err) 4389 return err; 4390 4391 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4392 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4393 return -EOPNOTSUPP; 4394 4395 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4396 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4397 return -EOPNOTSUPP; 4398 4399 entry = alloc_uar_entry(c, alloc_type); 4400 if (IS_ERR(entry)) 4401 return PTR_ERR(entry); 4402 4403 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4404 length = entry->rdma_entry.npages * PAGE_SIZE; 4405 uobj->object = entry; 4406 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4407 4408 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4409 &mmap_offset, sizeof(mmap_offset)); 4410 if (err) 4411 return err; 4412 4413 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4414 &entry->page_idx, sizeof(entry->page_idx)); 4415 if (err) 4416 return err; 4417 4418 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4419 &length, sizeof(length)); 4420 return err; 4421 } 4422 4423 DECLARE_UVERBS_NAMED_METHOD( 4424 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4425 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4426 MLX5_IB_OBJECT_UAR, 4427 UVERBS_ACCESS_NEW, 4428 UA_MANDATORY), 4429 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4430 enum mlx5_ib_uapi_uar_alloc_type, 4431 UA_MANDATORY), 4432 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4433 UVERBS_ATTR_TYPE(u32), 4434 UA_MANDATORY), 4435 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4436 UVERBS_ATTR_TYPE(u32), 4437 UA_MANDATORY), 4438 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4439 UVERBS_ATTR_TYPE(u64), 4440 UA_MANDATORY)); 4441 4442 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4443 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4444 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4445 MLX5_IB_OBJECT_UAR, 4446 UVERBS_ACCESS_DESTROY, 4447 UA_MANDATORY)); 4448 4449 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4450 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4451 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4452 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4453 4454 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4455 mlx5_ib_query_context, 4456 UVERBS_OBJECT_DEVICE, 4457 UVERBS_METHOD_QUERY_CONTEXT, 4458 UVERBS_ATTR_PTR_OUT( 4459 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4460 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4461 dump_fill_mkey), 4462 UA_MANDATORY)); 4463 4464 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4465 mlx5_ib_reg_dmabuf_mr, 4466 UVERBS_OBJECT_MR, 4467 UVERBS_METHOD_REG_DMABUF_MR, 4468 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4469 enum mlx5_ib_uapi_reg_dmabuf_flags, 4470 UA_OPTIONAL)); 4471 4472 static const struct uapi_definition mlx5_ib_defs[] = { 4473 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4474 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4475 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4476 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4477 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4478 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4479 UAPI_DEF_CHAIN(mlx5_ib_create_qp_defs), 4480 4481 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4482 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4483 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4484 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4485 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4486 {} 4487 }; 4488 4489 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4490 { 4491 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx); 4492 mlx5_ib_data_direct_cleanup(dev); 4493 mlx5_ib_cleanup_multiport_master(dev); 4494 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4495 mutex_destroy(&dev->cap_mask_mutex); 4496 WARN_ON(!xa_empty(&dev->sig_mrs)); 4497 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4498 mlx5r_macsec_dealloc_gids(dev); 4499 } 4500 4501 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4502 { 4503 struct mlx5_core_dev *mdev = dev->mdev; 4504 int err, i; 4505 4506 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4507 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4508 dev->ib_dev.dev.parent = mdev->device; 4509 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4510 4511 for (i = 0; i < dev->num_ports; i++) { 4512 spin_lock_init(&dev->port[i].mp.mpi_lock); 4513 dev->port[i].roce.dev = dev; 4514 dev->port[i].roce.native_port_num = i + 1; 4515 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4516 } 4517 4518 mutex_init(&dev->lb.mutex); 4519 4520 err = mlx5r_cmd_query_special_mkeys(dev); 4521 if (err) 4522 return err; 4523 4524 err = mlx5r_macsec_init_gids_and_devlist(dev); 4525 if (err) 4526 return err; 4527 4528 err = mlx5_ib_init_multiport_master(dev); 4529 if (err) 4530 goto err; 4531 4532 err = set_has_smi_cap(dev); 4533 if (err) 4534 goto err_mp; 4535 4536 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4537 if (err) 4538 goto err_mp; 4539 4540 if (mlx5_use_mad_ifc(dev)) 4541 get_ext_port_caps(dev); 4542 4543 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4544 4545 mutex_init(&dev->cap_mask_mutex); 4546 mutex_init(&dev->data_direct_lock); 4547 INIT_LIST_HEAD(&dev->qp_list); 4548 spin_lock_init(&dev->reset_flow_resource_lock); 4549 xa_init(&dev->odp_mkeys); 4550 xa_init(&dev->sig_mrs); 4551 atomic_set(&dev->mkey_var, 0); 4552 4553 spin_lock_init(&dev->dm.lock); 4554 dev->dm.dev = mdev; 4555 err = mlx5_ib_data_direct_init(dev); 4556 if (err) 4557 goto err_mp; 4558 4559 err = pcim_p2pdma_init(mdev->pdev); 4560 if (err && err != -EOPNOTSUPP) 4561 goto err_dd; 4562 4563 mlx5_cmd_init_async_ctx(mdev, &dev->async_ctx); 4564 4565 return 0; 4566 err_dd: 4567 mlx5_ib_data_direct_cleanup(dev); 4568 err_mp: 4569 mlx5_ib_cleanup_multiport_master(dev); 4570 err: 4571 mlx5r_macsec_dealloc_gids(dev); 4572 return err; 4573 } 4574 4575 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4576 enum rdma_nl_dev_type type, 4577 const char *name); 4578 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4579 4580 static const struct ib_device_ops mlx5_ib_dev_ops = { 4581 .owner = THIS_MODULE, 4582 .driver_id = RDMA_DRIVER_MLX5, 4583 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4584 4585 .add_gid = mlx5_ib_add_gid, 4586 .add_sub_dev = mlx5_ib_add_sub_dev, 4587 .alloc_mr = mlx5_ib_alloc_mr, 4588 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4589 .alloc_pd = mlx5_ib_alloc_pd, 4590 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4591 .attach_mcast = mlx5_ib_mcg_attach, 4592 .check_mr_status = mlx5_ib_check_mr_status, 4593 .create_ah = mlx5_ib_create_ah, 4594 .create_cq = mlx5_ib_create_cq, 4595 .create_user_cq = mlx5_ib_create_user_cq, 4596 .create_qp = mlx5_ib_create_qp, 4597 .create_srq = mlx5_ib_create_srq, 4598 .create_user_ah = mlx5_ib_create_ah, 4599 .dealloc_pd = mlx5_ib_dealloc_pd, 4600 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4601 .del_gid = mlx5_ib_del_gid, 4602 .del_sub_dev = mlx5_ib_del_sub_dev, 4603 .dereg_mr = mlx5_ib_dereg_mr, 4604 .destroy_ah = mlx5_ib_destroy_ah, 4605 .destroy_cq = mlx5_ib_destroy_cq, 4606 .destroy_qp = mlx5_ib_destroy_qp, 4607 .destroy_srq = mlx5_ib_destroy_srq, 4608 .detach_mcast = mlx5_ib_mcg_detach, 4609 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4610 .drain_rq = mlx5_ib_drain_rq, 4611 .drain_sq = mlx5_ib_drain_sq, 4612 .device_group = &mlx5_attr_group, 4613 .get_dev_fw_str = get_dev_fw_str, 4614 .get_dma_mr = mlx5_ib_get_dma_mr, 4615 .get_link_layer = mlx5_ib_port_link_layer, 4616 .map_mr_sg = mlx5_ib_map_mr_sg, 4617 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4618 .mmap = mlx5_ib_mmap, 4619 .mmap_free = mlx5_ib_mmap_free, 4620 .mmap_get_pfns = mlx5_ib_mmap_get_pfns, 4621 .modify_cq = mlx5_ib_modify_cq, 4622 .modify_device = mlx5_ib_modify_device, 4623 .modify_port = mlx5_ib_modify_port, 4624 .modify_qp = mlx5_ib_modify_qp, 4625 .modify_srq = mlx5_ib_modify_srq, 4626 .pgoff_to_mmap_entry = mlx5_ib_pgoff_to_mmap_entry, 4627 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4628 .poll_cq = mlx5_ib_poll_cq, 4629 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4630 .post_recv = mlx5_ib_post_recv_nodrain, 4631 .post_send = mlx5_ib_post_send_nodrain, 4632 .post_srq_recv = mlx5_ib_post_srq_recv, 4633 .process_mad = mlx5_ib_process_mad, 4634 .query_ah = mlx5_ib_query_ah, 4635 .query_device = mlx5_ib_query_device, 4636 .query_gid = mlx5_ib_query_gid, 4637 .query_pkey = mlx5_ib_query_pkey, 4638 .query_port_speed = mlx5_ib_query_port_speed, 4639 .query_qp = mlx5_ib_query_qp, 4640 .query_srq = mlx5_ib_query_srq, 4641 .query_ucontext = mlx5_ib_query_ucontext, 4642 .reg_user_mr = mlx5_ib_reg_user_mr, 4643 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4644 .req_notify_cq = mlx5_ib_arm_cq, 4645 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4646 .resize_user_cq = mlx5_ib_resize_cq, 4647 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4648 4649 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4650 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4651 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4652 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4653 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4654 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4655 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4656 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4657 }; 4658 4659 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4660 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4661 }; 4662 4663 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4664 .get_vf_config = mlx5_ib_get_vf_config, 4665 .get_vf_guid = mlx5_ib_get_vf_guid, 4666 .get_vf_stats = mlx5_ib_get_vf_stats, 4667 .set_vf_guid = mlx5_ib_set_vf_guid, 4668 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4669 }; 4670 4671 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4672 .alloc_mw = mlx5_ib_alloc_mw, 4673 .dealloc_mw = mlx5_ib_dealloc_mw, 4674 4675 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4676 }; 4677 4678 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4679 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4680 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4681 4682 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4683 }; 4684 4685 static int mlx5_ib_init_var_region(struct mlx5_ib_dev *dev) 4686 { 4687 struct mlx5_var_region *var_region = &dev->var_table.var_region; 4688 struct mlx5_core_dev *mdev = dev->mdev; 4689 u8 log_doorbell_bar_size; 4690 u8 log_doorbell_stride; 4691 u64 bar_size; 4692 4693 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4694 log_doorbell_bar_size); 4695 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4696 log_doorbell_stride); 4697 var_region->hw_start_addr = dev->mdev->bar_addr + 4698 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4699 doorbell_bar_offset); 4700 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4701 var_region->stride_size = 1ULL << log_doorbell_stride; 4702 var_region->num_var_hw_entries = div_u64(bar_size, 4703 var_region->stride_size); 4704 mutex_init(&var_region->bitmap_lock); 4705 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4706 GFP_KERNEL); 4707 return (var_region->bitmap) ? 0 : -ENOMEM; 4708 } 4709 4710 static int mlx5_ib_init_tlp_var_region(struct mlx5_ib_dev *dev) 4711 { 4712 struct mlx5_var_region *var_region = &dev->var_table.tlp_var_region; 4713 struct mlx5_core_dev *mdev = dev->mdev; 4714 u8 log_tlp_var_stride; 4715 4716 log_tlp_var_stride = 4717 MLX5_CAP_DEV_TLP_EMULATION(mdev, log_tlp_rsp_gw_page_stride); 4718 var_region->hw_start_addr = 4719 dev->mdev->bar_addr + 4720 MLX5_CAP64_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_pages_bar_offset); 4721 4722 var_region->stride_size = (1ULL << log_tlp_var_stride) * 4096; 4723 var_region->num_var_hw_entries = 4724 MLX5_CAP_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_num_pages); 4725 4726 mutex_init(&var_region->bitmap_lock); 4727 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4728 GFP_KERNEL); 4729 return (var_region->bitmap) ? 0 : -ENOMEM; 4730 } 4731 4732 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4733 { 4734 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4735 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4736 4737 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4738 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4739 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4740 } 4741 4742 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4743 { 4744 int ret; 4745 4746 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4747 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4748 if (ret) 4749 return ret; 4750 } 4751 4752 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4753 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4754 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4755 if (ret) 4756 goto remove_local; 4757 } 4758 4759 return 0; 4760 4761 remove_local: 4762 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4763 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4764 return ret; 4765 } 4766 4767 static void mlx5_ib_cleanup_var_table(struct mlx5_ib_dev *dev) 4768 { 4769 bitmap_free(dev->var_table.var_region.bitmap); 4770 bitmap_free(dev->var_table.tlp_var_region.bitmap); 4771 } 4772 4773 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4774 { 4775 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4776 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4777 mlx5_ib_cleanup_ucaps(dev); 4778 4779 mlx5_ib_cleanup_var_table(dev); 4780 } 4781 4782 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4783 { 4784 struct mlx5_core_dev *mdev = dev->mdev; 4785 int err; 4786 4787 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4788 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4789 ib_set_device_ops(&dev->ib_dev, 4790 &mlx5_ib_dev_ipoib_enhanced_ops); 4791 4792 if (mlx5_core_is_pf(mdev)) 4793 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4794 4795 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4796 4797 if (MLX5_CAP_GEN(mdev, imaicl)) 4798 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4799 4800 if (MLX5_CAP_GEN(mdev, xrc)) 4801 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4802 4803 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4804 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4805 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4806 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4807 4808 if (mdev->st) 4809 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4810 4811 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4812 4813 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4814 dev->ib_dev.driver_def = mlx5_ib_defs; 4815 4816 err = init_node_data(dev); 4817 if (err) 4818 return err; 4819 4820 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4821 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4822 err = mlx5_ib_init_var_region(dev); 4823 if (err) 4824 return err; 4825 } 4826 4827 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4828 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4829 err = mlx5_ib_init_ucaps(dev); 4830 if (err) 4831 goto err_ucaps; 4832 } 4833 4834 if (MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager)) { 4835 err = mlx5_ib_init_tlp_var_region(dev); 4836 if (err) 4837 goto err_tlp_var; 4838 } 4839 4840 dev->ib_dev.use_cq_dim = true; 4841 4842 return 0; 4843 4844 err_tlp_var: 4845 mlx5_ib_cleanup_ucaps(dev); 4846 err_ucaps: 4847 bitmap_free(dev->var_table.var_region.bitmap); 4848 return err; 4849 } 4850 4851 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4852 .get_port_immutable = mlx5_port_immutable, 4853 .query_port = mlx5_ib_query_port, 4854 }; 4855 4856 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4857 { 4858 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4859 return 0; 4860 } 4861 4862 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4863 .get_port_immutable = mlx5_port_rep_immutable, 4864 .query_port = mlx5_ib_rep_query_port, 4865 .query_pkey = mlx5_ib_rep_query_pkey, 4866 }; 4867 4868 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4869 { 4870 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4871 return 0; 4872 } 4873 4874 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4875 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4876 .create_wq = mlx5_ib_create_wq, 4877 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4878 .destroy_wq = mlx5_ib_destroy_wq, 4879 .modify_wq = mlx5_ib_modify_wq, 4880 4881 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4882 ib_rwq_ind_tbl), 4883 }; 4884 4885 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4886 { 4887 struct mlx5_core_dev *mdev = dev->mdev; 4888 enum rdma_link_layer ll; 4889 int port_type_cap; 4890 u32 port_num = 0; 4891 int err; 4892 4893 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4894 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4895 4896 if (ll == IB_LINK_LAYER_ETHERNET) { 4897 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4898 4899 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4900 4901 /* Register only for native ports */ 4902 mlx5_mdev_netdev_track(dev, port_num); 4903 4904 err = mlx5_enable_eth(dev); 4905 if (err) 4906 goto cleanup; 4907 } 4908 4909 return 0; 4910 cleanup: 4911 mlx5_mdev_netdev_untrack(dev, port_num); 4912 return err; 4913 } 4914 4915 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4916 { 4917 struct mlx5_core_dev *mdev = dev->mdev; 4918 enum rdma_link_layer ll; 4919 int port_type_cap; 4920 u32 port_num; 4921 4922 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4923 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4924 4925 if (ll == IB_LINK_LAYER_ETHERNET) { 4926 mlx5_disable_eth(dev); 4927 4928 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4929 mlx5_mdev_netdev_untrack(dev, port_num); 4930 } 4931 } 4932 4933 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4934 { 4935 mlx5_ib_init_cong_debugfs(dev, 4936 mlx5_core_native_port_num(dev->mdev) - 1); 4937 return 0; 4938 } 4939 4940 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4941 { 4942 mlx5_ib_cleanup_cong_debugfs(dev, 4943 mlx5_core_native_port_num(dev->mdev) - 1); 4944 } 4945 4946 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4947 { 4948 int err; 4949 4950 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4951 if (err) 4952 return err; 4953 4954 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4955 if (err) 4956 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4957 4958 return err; 4959 } 4960 4961 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4962 { 4963 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4964 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4965 } 4966 4967 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4968 { 4969 const char *name; 4970 4971 if (dev->sub_dev_name) { 4972 name = dev->sub_dev_name; 4973 ib_mark_name_assigned_by_user(&dev->ib_dev); 4974 } else if (!mlx5_lag_is_active(dev->mdev)) 4975 name = "mlx5_%d"; 4976 else 4977 name = "mlx5_bond_%d"; 4978 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4979 } 4980 4981 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4982 { 4983 mlx5r_frmr_pools_cleanup(&dev->ib_dev); 4984 mlx5r_umr_resource_cleanup(dev); 4985 mlx5r_umr_cleanup(dev); 4986 } 4987 4988 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4989 { 4990 ib_unregister_device(&dev->ib_dev); 4991 } 4992 4993 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4994 { 4995 int ret; 4996 4997 ret = mlx5r_umr_init(dev); 4998 if (ret) 4999 return ret; 5000 5001 ret = mlx5r_frmr_pools_init(&dev->ib_dev); 5002 if (ret) 5003 mlx5_ib_warn(dev, "frmr pools init failed %d\n", ret); 5004 5005 return ret; 5006 } 5007 5008 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5009 { 5010 struct dentry *root; 5011 5012 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5013 return 0; 5014 5015 mutex_init(&dev->delay_drop.lock); 5016 dev->delay_drop.dev = dev; 5017 dev->delay_drop.activate = false; 5018 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5019 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5020 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5021 atomic_set(&dev->delay_drop.events_cnt, 0); 5022 5023 if (!mlx5_debugfs_root) 5024 return 0; 5025 5026 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 5027 dev->delay_drop.dir_debugfs = root; 5028 5029 debugfs_create_atomic_t("num_timeout_events", 0400, root, 5030 &dev->delay_drop.events_cnt); 5031 debugfs_create_atomic_t("num_rqs", 0400, root, 5032 &dev->delay_drop.rqs_cnt); 5033 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 5034 &fops_delay_drop_timeout); 5035 return 0; 5036 } 5037 5038 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5039 { 5040 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5041 return; 5042 5043 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5044 if (!dev->delay_drop.dir_debugfs) 5045 return; 5046 5047 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 5048 dev->delay_drop.dir_debugfs = NULL; 5049 } 5050 5051 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 5052 { 5053 struct mlx5_ib_resources *devr = &dev->devr; 5054 int port; 5055 5056 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5057 INIT_WORK(&devr->ports[port].pkey_change_work, 5058 pkey_change_handler); 5059 5060 dev->mdev_events.notifier_call = mlx5_ib_event; 5061 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 5062 5063 mlx5r_macsec_event_register(dev); 5064 5065 return 0; 5066 } 5067 5068 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 5069 { 5070 struct mlx5_ib_resources *devr = &dev->devr; 5071 int port; 5072 5073 mlx5r_macsec_event_unregister(dev); 5074 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 5075 5076 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5077 cancel_work_sync(&devr->ports[port].pkey_change_work); 5078 } 5079 5080 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 5081 struct mlx5_data_direct_dev *dev) 5082 { 5083 mutex_lock(&ibdev->data_direct_lock); 5084 ibdev->data_direct_dev = dev; 5085 mutex_unlock(&ibdev->data_direct_lock); 5086 } 5087 5088 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 5089 { 5090 mutex_lock(&ibdev->data_direct_lock); 5091 mlx5_ib_revoke_data_direct_mrs(ibdev); 5092 ibdev->data_direct_dev = NULL; 5093 mutex_unlock(&ibdev->data_direct_lock); 5094 } 5095 5096 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5097 const struct mlx5_ib_profile *profile, 5098 int stage) 5099 { 5100 dev->ib_active = false; 5101 5102 /* Number of stages to cleanup */ 5103 while (stage) { 5104 stage--; 5105 if (profile->stage[stage].cleanup) 5106 profile->stage[stage].cleanup(dev); 5107 } 5108 5109 kfree(dev->port); 5110 ib_dealloc_device(&dev->ib_dev); 5111 } 5112 5113 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 5114 const struct mlx5_ib_profile *profile) 5115 { 5116 int err; 5117 int i; 5118 5119 dev->profile = profile; 5120 5121 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5122 if (profile->stage[i].init) { 5123 err = profile->stage[i].init(dev); 5124 if (err) 5125 goto err_out; 5126 } 5127 } 5128 5129 dev->ib_active = true; 5130 return 0; 5131 5132 err_out: 5133 /* Clean up stages which were initialized */ 5134 while (i) { 5135 i--; 5136 if (profile->stage[i].cleanup) 5137 profile->stage[i].cleanup(dev); 5138 } 5139 return err; 5140 } 5141 5142 static const struct mlx5_ib_profile pf_profile = { 5143 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5144 mlx5_ib_stage_init_init, 5145 mlx5_ib_stage_init_cleanup), 5146 STAGE_CREATE(MLX5_IB_STAGE_FS, 5147 mlx5_ib_fs_init, 5148 mlx5_ib_fs_cleanup), 5149 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5150 mlx5_ib_stage_caps_init, 5151 mlx5_ib_stage_caps_cleanup), 5152 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5153 mlx5_ib_stage_non_default_cb, 5154 NULL), 5155 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5156 mlx5_ib_roce_init, 5157 mlx5_ib_roce_cleanup), 5158 STAGE_CREATE(MLX5_IB_STAGE_QP, 5159 mlx5_init_qp_table, 5160 mlx5_cleanup_qp_table), 5161 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5162 mlx5_init_srq_table, 5163 mlx5_cleanup_srq_table), 5164 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5165 mlx5_ib_dev_res_init, 5166 mlx5_ib_dev_res_cleanup), 5167 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5168 mlx5_ib_odp_init_one, 5169 mlx5_ib_odp_cleanup_one), 5170 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5171 mlx5_ib_counters_init, 5172 mlx5_ib_counters_cleanup), 5173 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5174 mlx5_ib_stage_cong_debugfs_init, 5175 mlx5_ib_stage_cong_debugfs_cleanup), 5176 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5177 mlx5_ib_stage_bfrag_init, 5178 mlx5_ib_stage_bfrag_cleanup), 5179 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5180 NULL, 5181 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5182 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5183 mlx5_ib_devx_init, 5184 mlx5_ib_devx_cleanup), 5185 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5186 mlx5_ib_stage_sys_error_notifier_init, 5187 mlx5_ib_stage_sys_error_notifier_cleanup), 5188 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5189 mlx5_ib_stage_ib_reg_init, 5190 mlx5_ib_stage_ib_reg_cleanup), 5191 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5192 mlx5_ib_stage_dev_notifier_init, 5193 mlx5_ib_stage_dev_notifier_cleanup), 5194 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5195 mlx5_ib_stage_post_ib_reg_umr_init, 5196 NULL), 5197 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5198 mlx5_ib_stage_delay_drop_init, 5199 mlx5_ib_stage_delay_drop_cleanup), 5200 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5201 mlx5_ib_restrack_init, 5202 NULL), 5203 }; 5204 5205 const struct mlx5_ib_profile raw_eth_profile = { 5206 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5207 mlx5_ib_stage_init_init, 5208 mlx5_ib_stage_init_cleanup), 5209 STAGE_CREATE(MLX5_IB_STAGE_FS, 5210 mlx5_ib_fs_init, 5211 mlx5_ib_fs_cleanup), 5212 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5213 mlx5_ib_stage_caps_init, 5214 mlx5_ib_stage_caps_cleanup), 5215 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5216 mlx5_ib_stage_raw_eth_non_default_cb, 5217 NULL), 5218 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5219 mlx5_ib_roce_init, 5220 mlx5_ib_roce_cleanup), 5221 STAGE_CREATE(MLX5_IB_STAGE_QP, 5222 mlx5_init_qp_table, 5223 mlx5_cleanup_qp_table), 5224 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5225 mlx5_init_srq_table, 5226 mlx5_cleanup_srq_table), 5227 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5228 mlx5_ib_dev_res_init, 5229 mlx5_ib_dev_res_cleanup), 5230 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5231 mlx5_ib_counters_init, 5232 mlx5_ib_counters_cleanup), 5233 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5234 mlx5_ib_stage_cong_debugfs_init, 5235 mlx5_ib_stage_cong_debugfs_cleanup), 5236 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5237 mlx5_ib_stage_bfrag_init, 5238 mlx5_ib_stage_bfrag_cleanup), 5239 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5240 NULL, 5241 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5242 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5243 mlx5_ib_devx_init, 5244 mlx5_ib_devx_cleanup), 5245 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5246 mlx5_ib_stage_sys_error_notifier_init, 5247 mlx5_ib_stage_sys_error_notifier_cleanup), 5248 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5249 mlx5_ib_stage_ib_reg_init, 5250 mlx5_ib_stage_ib_reg_cleanup), 5251 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5252 mlx5_ib_stage_dev_notifier_init, 5253 mlx5_ib_stage_dev_notifier_cleanup), 5254 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5255 mlx5_ib_stage_post_ib_reg_umr_init, 5256 NULL), 5257 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5258 mlx5_ib_stage_delay_drop_init, 5259 mlx5_ib_stage_delay_drop_cleanup), 5260 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5261 mlx5_ib_restrack_init, 5262 NULL), 5263 }; 5264 5265 static const struct mlx5_ib_profile plane_profile = { 5266 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5267 mlx5_ib_stage_init_init, 5268 mlx5_ib_stage_init_cleanup), 5269 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5270 mlx5_ib_stage_caps_init, 5271 mlx5_ib_stage_caps_cleanup), 5272 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5273 mlx5_ib_stage_non_default_cb, 5274 NULL), 5275 STAGE_CREATE(MLX5_IB_STAGE_QP, 5276 mlx5_init_qp_table, 5277 mlx5_cleanup_qp_table), 5278 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5279 mlx5_init_srq_table, 5280 mlx5_cleanup_srq_table), 5281 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5282 mlx5_ib_dev_res_init, 5283 mlx5_ib_dev_res_cleanup), 5284 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5285 mlx5_ib_stage_bfrag_init, 5286 mlx5_ib_stage_bfrag_cleanup), 5287 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5288 mlx5_ib_stage_ib_reg_init, 5289 mlx5_ib_stage_ib_reg_cleanup), 5290 }; 5291 5292 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 5293 enum rdma_nl_dev_type type, 5294 const char *name) 5295 { 5296 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 5297 enum rdma_link_layer ll; 5298 int ret; 5299 5300 if (mparent->smi_dev) 5301 return ERR_PTR(-EEXIST); 5302 5303 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 5304 port_type)); 5305 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 5306 ll != IB_LINK_LAYER_INFINIBAND || 5307 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 5308 return ERR_PTR(-EOPNOTSUPP); 5309 5310 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5311 mlx5_core_net(mparent->mdev)); 5312 if (!mplane) 5313 return ERR_PTR(-ENOMEM); 5314 5315 mplane->port = kzalloc_objs(*mplane->port, 5316 mparent->num_plane * mparent->num_ports); 5317 if (!mplane->port) { 5318 ret = -ENOMEM; 5319 goto fail_kcalloc; 5320 } 5321 5322 mplane->ib_dev.type = type; 5323 mplane->mdev = mparent->mdev; 5324 mplane->num_ports = mparent->num_plane; 5325 mplane->sub_dev_name = name; 5326 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 5327 5328 ret = __mlx5_ib_add(mplane, &plane_profile); 5329 if (ret) 5330 goto fail_ib_add; 5331 5332 mparent->smi_dev = mplane; 5333 return &mplane->ib_dev; 5334 5335 fail_ib_add: 5336 kfree(mplane->port); 5337 fail_kcalloc: 5338 ib_dealloc_device(&mplane->ib_dev); 5339 return ERR_PTR(ret); 5340 } 5341 5342 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 5343 { 5344 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 5345 5346 to_mdev(sub_dev->parent)->smi_dev = NULL; 5347 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 5348 } 5349 5350 static int mlx5r_mp_probe(struct auxiliary_device *adev, 5351 const struct auxiliary_device_id *id) 5352 { 5353 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5354 struct mlx5_core_dev *mdev = idev->mdev; 5355 struct mlx5_ib_multiport_info *mpi; 5356 struct mlx5_ib_dev *dev; 5357 bool bound = false; 5358 int err; 5359 5360 mpi = kzalloc_obj(*mpi); 5361 if (!mpi) 5362 return -ENOMEM; 5363 5364 mpi->mdev = mdev; 5365 err = mlx5_query_nic_vport_system_image_guid(mdev, 5366 &mpi->sys_image_guid); 5367 if (err) { 5368 kfree(mpi); 5369 return err; 5370 } 5371 5372 mutex_lock(&mlx5_ib_multiport_mutex); 5373 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5374 if (dev->sys_image_guid == mpi->sys_image_guid && 5375 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 5376 bound = mlx5_ib_bind_slave_port(dev, mpi); 5377 5378 if (bound) { 5379 rdma_roce_rescan_device(&dev->ib_dev); 5380 mpi->ibdev->ib_active = true; 5381 break; 5382 } 5383 } 5384 5385 if (!bound) { 5386 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5387 dev_dbg(mdev->device, 5388 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5389 } 5390 mutex_unlock(&mlx5_ib_multiport_mutex); 5391 5392 auxiliary_set_drvdata(adev, mpi); 5393 return 0; 5394 } 5395 5396 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5397 { 5398 struct mlx5_ib_multiport_info *mpi; 5399 5400 mpi = auxiliary_get_drvdata(adev); 5401 mutex_lock(&mlx5_ib_multiport_mutex); 5402 if (mpi->ibdev) 5403 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5404 else 5405 list_del(&mpi->list); 5406 mutex_unlock(&mlx5_ib_multiport_mutex); 5407 kfree(mpi); 5408 } 5409 5410 static int mlx5r_probe(struct auxiliary_device *adev, 5411 const struct auxiliary_device_id *id) 5412 { 5413 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5414 struct mlx5_core_dev *mdev = idev->mdev; 5415 const struct mlx5_ib_profile *profile; 5416 int port_type_cap, num_ports, ret; 5417 enum rdma_link_layer ll; 5418 struct mlx5_ib_dev *dev; 5419 5420 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5421 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5422 5423 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5424 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5425 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5426 mlx5_core_net(mdev)); 5427 if (!dev) 5428 return -ENOMEM; 5429 5430 if (ll == IB_LINK_LAYER_INFINIBAND) { 5431 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5432 if (ret) 5433 goto fail; 5434 } 5435 5436 dev->port = kzalloc_objs(*dev->port, num_ports); 5437 if (!dev->port) { 5438 ret = -ENOMEM; 5439 goto fail; 5440 } 5441 5442 dev->mdev = mdev; 5443 dev->num_ports = num_ports; 5444 dev->ib_dev.phys_port_cnt = num_ports; 5445 5446 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5447 profile = &raw_eth_profile; 5448 else 5449 profile = &pf_profile; 5450 5451 ret = __mlx5_ib_add(dev, profile); 5452 if (ret) 5453 goto fail_ib_add; 5454 5455 auxiliary_set_drvdata(adev, dev); 5456 return 0; 5457 5458 fail_ib_add: 5459 kfree(dev->port); 5460 fail: 5461 ib_dealloc_device(&dev->ib_dev); 5462 return ret; 5463 } 5464 5465 static void mlx5r_remove(struct auxiliary_device *adev) 5466 { 5467 struct mlx5_ib_dev *dev; 5468 5469 dev = auxiliary_get_drvdata(adev); 5470 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5471 } 5472 5473 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5474 { .name = MLX5_ADEV_NAME ".multiport", }, 5475 {}, 5476 }; 5477 5478 static const struct auxiliary_device_id mlx5r_id_table[] = { 5479 { .name = MLX5_ADEV_NAME ".rdma", }, 5480 {}, 5481 }; 5482 5483 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5484 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5485 5486 static struct auxiliary_driver mlx5r_mp_driver = { 5487 .name = "multiport", 5488 .probe = mlx5r_mp_probe, 5489 .remove = mlx5r_mp_remove, 5490 .id_table = mlx5r_mp_id_table, 5491 }; 5492 5493 static struct auxiliary_driver mlx5r_driver = { 5494 .name = "rdma", 5495 .probe = mlx5r_probe, 5496 .remove = mlx5r_remove, 5497 .id_table = mlx5r_id_table, 5498 }; 5499 5500 static int __init mlx5_ib_init(void) 5501 { 5502 int ret; 5503 5504 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 5505 if (!xlt_emergency_page) 5506 return -ENOMEM; 5507 5508 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5509 if (!mlx5_ib_event_wq) { 5510 free_page((unsigned long)xlt_emergency_page); 5511 return -ENOMEM; 5512 } 5513 5514 ret = mlx5_ib_qp_event_init(); 5515 if (ret) 5516 goto qp_event_err; 5517 5518 mlx5_ib_odp_init(); 5519 ret = mlx5r_rep_init(); 5520 if (ret) 5521 goto rep_err; 5522 ret = mlx5_data_direct_driver_register(); 5523 if (ret) 5524 goto dd_err; 5525 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5526 if (ret) 5527 goto mp_err; 5528 ret = auxiliary_driver_register(&mlx5r_driver); 5529 if (ret) 5530 goto drv_err; 5531 5532 return 0; 5533 5534 drv_err: 5535 auxiliary_driver_unregister(&mlx5r_mp_driver); 5536 mp_err: 5537 mlx5_data_direct_driver_unregister(); 5538 dd_err: 5539 mlx5r_rep_cleanup(); 5540 rep_err: 5541 mlx5_ib_qp_event_cleanup(); 5542 qp_event_err: 5543 destroy_workqueue(mlx5_ib_event_wq); 5544 free_page((unsigned long)xlt_emergency_page); 5545 return ret; 5546 } 5547 5548 static void __exit mlx5_ib_cleanup(void) 5549 { 5550 mlx5_data_direct_driver_unregister(); 5551 auxiliary_driver_unregister(&mlx5r_driver); 5552 auxiliary_driver_unregister(&mlx5r_mp_driver); 5553 mlx5r_rep_cleanup(); 5554 5555 mlx5_ib_qp_event_cleanup(); 5556 destroy_workqueue(mlx5_ib_event_wq); 5557 free_page((unsigned long)xlt_emergency_page); 5558 } 5559 5560 module_init(mlx5_ib_init); 5561 module_exit(mlx5_ib_cleanup); 5562