1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/delay.h> 45 #include <rdma/ib_user_verbs.h> 46 #include <rdma/ib_addr.h> 47 #include <rdma/ib_cache.h> 48 #include <linux/mlx5/port.h> 49 #include <linux/mlx5/vport.h> 50 #include <linux/list.h> 51 #include <rdma/ib_smi.h> 52 #include <rdma/ib_umem.h> 53 #include <linux/in.h> 54 #include <linux/etherdevice.h> 55 #include <linux/mlx5/fs.h> 56 #include "user.h" 57 #include "mlx5_ib.h" 58 59 #define DRIVER_NAME "mlx5_ib" 60 #define DRIVER_VERSION "2.2-1" 61 #define DRIVER_RELDATE "Feb 2014" 62 63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 65 MODULE_LICENSE("Dual BSD/GPL"); 66 MODULE_VERSION(DRIVER_VERSION); 67 68 static int deprecated_prof_sel = 2; 69 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 70 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 71 72 static char mlx5_version[] = 73 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 74 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 75 76 enum { 77 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 78 }; 79 80 static enum rdma_link_layer 81 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 82 { 83 switch (port_type_cap) { 84 case MLX5_CAP_PORT_TYPE_IB: 85 return IB_LINK_LAYER_INFINIBAND; 86 case MLX5_CAP_PORT_TYPE_ETH: 87 return IB_LINK_LAYER_ETHERNET; 88 default: 89 return IB_LINK_LAYER_UNSPECIFIED; 90 } 91 } 92 93 static enum rdma_link_layer 94 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 95 { 96 struct mlx5_ib_dev *dev = to_mdev(device); 97 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 98 99 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 100 } 101 102 static int mlx5_netdev_event(struct notifier_block *this, 103 unsigned long event, void *ptr) 104 { 105 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 106 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 107 roce.nb); 108 109 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 110 return NOTIFY_DONE; 111 112 write_lock(&ibdev->roce.netdev_lock); 113 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 114 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 115 write_unlock(&ibdev->roce.netdev_lock); 116 117 return NOTIFY_DONE; 118 } 119 120 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 121 u8 port_num) 122 { 123 struct mlx5_ib_dev *ibdev = to_mdev(device); 124 struct net_device *ndev; 125 126 /* Ensure ndev does not disappear before we invoke dev_hold() 127 */ 128 read_lock(&ibdev->roce.netdev_lock); 129 ndev = ibdev->roce.netdev; 130 if (ndev) 131 dev_hold(ndev); 132 read_unlock(&ibdev->roce.netdev_lock); 133 134 return ndev; 135 } 136 137 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 138 struct ib_port_attr *props) 139 { 140 struct mlx5_ib_dev *dev = to_mdev(device); 141 struct net_device *ndev; 142 enum ib_mtu ndev_ib_mtu; 143 u16 qkey_viol_cntr; 144 145 memset(props, 0, sizeof(*props)); 146 147 props->port_cap_flags |= IB_PORT_CM_SUP; 148 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 149 150 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 151 roce_address_table_size); 152 props->max_mtu = IB_MTU_4096; 153 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 154 props->pkey_tbl_len = 1; 155 props->state = IB_PORT_DOWN; 156 props->phys_state = 3; 157 158 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 159 props->qkey_viol_cntr = qkey_viol_cntr; 160 161 ndev = mlx5_ib_get_netdev(device, port_num); 162 if (!ndev) 163 return 0; 164 165 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 166 props->state = IB_PORT_ACTIVE; 167 props->phys_state = 5; 168 } 169 170 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 171 172 dev_put(ndev); 173 174 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 175 176 props->active_width = IB_WIDTH_4X; /* TODO */ 177 props->active_speed = IB_SPEED_QDR; /* TODO */ 178 179 return 0; 180 } 181 182 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 183 const struct ib_gid_attr *attr, 184 void *mlx5_addr) 185 { 186 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 187 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 188 source_l3_address); 189 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 190 source_mac_47_32); 191 192 if (!gid) 193 return; 194 195 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 196 197 if (is_vlan_dev(attr->ndev)) { 198 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 199 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 200 } 201 202 switch (attr->gid_type) { 203 case IB_GID_TYPE_IB: 204 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 205 break; 206 case IB_GID_TYPE_ROCE_UDP_ENCAP: 207 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 208 break; 209 210 default: 211 WARN_ON(true); 212 } 213 214 if (attr->gid_type != IB_GID_TYPE_IB) { 215 if (ipv6_addr_v4mapped((void *)gid)) 216 MLX5_SET_RA(mlx5_addr, roce_l3_type, 217 MLX5_ROCE_L3_TYPE_IPV4); 218 else 219 MLX5_SET_RA(mlx5_addr, roce_l3_type, 220 MLX5_ROCE_L3_TYPE_IPV6); 221 } 222 223 if ((attr->gid_type == IB_GID_TYPE_IB) || 224 !ipv6_addr_v4mapped((void *)gid)) 225 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 226 else 227 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 228 } 229 230 static int set_roce_addr(struct ib_device *device, u8 port_num, 231 unsigned int index, 232 const union ib_gid *gid, 233 const struct ib_gid_attr *attr) 234 { 235 struct mlx5_ib_dev *dev = to_mdev(device); 236 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 237 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 238 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 239 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 240 241 if (ll != IB_LINK_LAYER_ETHERNET) 242 return -EINVAL; 243 244 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 245 246 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 247 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 248 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 249 } 250 251 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 252 unsigned int index, const union ib_gid *gid, 253 const struct ib_gid_attr *attr, 254 __always_unused void **context) 255 { 256 return set_roce_addr(device, port_num, index, gid, attr); 257 } 258 259 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 260 unsigned int index, __always_unused void **context) 261 { 262 return set_roce_addr(device, port_num, index, NULL, NULL); 263 } 264 265 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 266 int index) 267 { 268 struct ib_gid_attr attr; 269 union ib_gid gid; 270 271 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 272 return 0; 273 274 if (!attr.ndev) 275 return 0; 276 277 dev_put(attr.ndev); 278 279 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 280 return 0; 281 282 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 283 } 284 285 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 286 { 287 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 288 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 289 return 0; 290 } 291 292 enum { 293 MLX5_VPORT_ACCESS_METHOD_MAD, 294 MLX5_VPORT_ACCESS_METHOD_HCA, 295 MLX5_VPORT_ACCESS_METHOD_NIC, 296 }; 297 298 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 299 { 300 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 301 return MLX5_VPORT_ACCESS_METHOD_MAD; 302 303 if (mlx5_ib_port_link_layer(ibdev, 1) == 304 IB_LINK_LAYER_ETHERNET) 305 return MLX5_VPORT_ACCESS_METHOD_NIC; 306 307 return MLX5_VPORT_ACCESS_METHOD_HCA; 308 } 309 310 static void get_atomic_caps(struct mlx5_ib_dev *dev, 311 struct ib_device_attr *props) 312 { 313 u8 tmp; 314 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 315 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 316 u8 atomic_req_8B_endianness_mode = 317 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 318 319 /* Check if HW supports 8 bytes standard atomic operations and capable 320 * of host endianness respond 321 */ 322 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 323 if (((atomic_operations & tmp) == tmp) && 324 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 325 (atomic_req_8B_endianness_mode)) { 326 props->atomic_cap = IB_ATOMIC_HCA; 327 } else { 328 props->atomic_cap = IB_ATOMIC_NONE; 329 } 330 } 331 332 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 333 __be64 *sys_image_guid) 334 { 335 struct mlx5_ib_dev *dev = to_mdev(ibdev); 336 struct mlx5_core_dev *mdev = dev->mdev; 337 u64 tmp; 338 int err; 339 340 switch (mlx5_get_vport_access_method(ibdev)) { 341 case MLX5_VPORT_ACCESS_METHOD_MAD: 342 return mlx5_query_mad_ifc_system_image_guid(ibdev, 343 sys_image_guid); 344 345 case MLX5_VPORT_ACCESS_METHOD_HCA: 346 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 347 break; 348 349 case MLX5_VPORT_ACCESS_METHOD_NIC: 350 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 351 break; 352 353 default: 354 return -EINVAL; 355 } 356 357 if (!err) 358 *sys_image_guid = cpu_to_be64(tmp); 359 360 return err; 361 362 } 363 364 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 365 u16 *max_pkeys) 366 { 367 struct mlx5_ib_dev *dev = to_mdev(ibdev); 368 struct mlx5_core_dev *mdev = dev->mdev; 369 370 switch (mlx5_get_vport_access_method(ibdev)) { 371 case MLX5_VPORT_ACCESS_METHOD_MAD: 372 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 373 374 case MLX5_VPORT_ACCESS_METHOD_HCA: 375 case MLX5_VPORT_ACCESS_METHOD_NIC: 376 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 377 pkey_table_size)); 378 return 0; 379 380 default: 381 return -EINVAL; 382 } 383 } 384 385 static int mlx5_query_vendor_id(struct ib_device *ibdev, 386 u32 *vendor_id) 387 { 388 struct mlx5_ib_dev *dev = to_mdev(ibdev); 389 390 switch (mlx5_get_vport_access_method(ibdev)) { 391 case MLX5_VPORT_ACCESS_METHOD_MAD: 392 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 393 394 case MLX5_VPORT_ACCESS_METHOD_HCA: 395 case MLX5_VPORT_ACCESS_METHOD_NIC: 396 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 397 398 default: 399 return -EINVAL; 400 } 401 } 402 403 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 404 __be64 *node_guid) 405 { 406 u64 tmp; 407 int err; 408 409 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 410 case MLX5_VPORT_ACCESS_METHOD_MAD: 411 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 412 413 case MLX5_VPORT_ACCESS_METHOD_HCA: 414 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 415 break; 416 417 case MLX5_VPORT_ACCESS_METHOD_NIC: 418 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 419 break; 420 421 default: 422 return -EINVAL; 423 } 424 425 if (!err) 426 *node_guid = cpu_to_be64(tmp); 427 428 return err; 429 } 430 431 struct mlx5_reg_node_desc { 432 u8 desc[64]; 433 }; 434 435 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 436 { 437 struct mlx5_reg_node_desc in; 438 439 if (mlx5_use_mad_ifc(dev)) 440 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 441 442 memset(&in, 0, sizeof(in)); 443 444 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 445 sizeof(struct mlx5_reg_node_desc), 446 MLX5_REG_NODE_DESC, 0, 0); 447 } 448 449 static int mlx5_ib_query_device(struct ib_device *ibdev, 450 struct ib_device_attr *props, 451 struct ib_udata *uhw) 452 { 453 struct mlx5_ib_dev *dev = to_mdev(ibdev); 454 struct mlx5_core_dev *mdev = dev->mdev; 455 int err = -ENOMEM; 456 int max_rq_sg; 457 int max_sq_sg; 458 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 459 struct mlx5_ib_query_device_resp resp = {}; 460 size_t resp_len; 461 u64 max_tso; 462 463 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 464 if (uhw->outlen && uhw->outlen < resp_len) 465 return -EINVAL; 466 else 467 resp.response_length = resp_len; 468 469 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 470 return -EINVAL; 471 472 memset(props, 0, sizeof(*props)); 473 err = mlx5_query_system_image_guid(ibdev, 474 &props->sys_image_guid); 475 if (err) 476 return err; 477 478 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 479 if (err) 480 return err; 481 482 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 483 if (err) 484 return err; 485 486 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 487 (fw_rev_min(dev->mdev) << 16) | 488 fw_rev_sub(dev->mdev); 489 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 490 IB_DEVICE_PORT_ACTIVE_EVENT | 491 IB_DEVICE_SYS_IMAGE_GUID | 492 IB_DEVICE_RC_RNR_NAK_GEN; 493 494 if (MLX5_CAP_GEN(mdev, pkv)) 495 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 496 if (MLX5_CAP_GEN(mdev, qkv)) 497 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 498 if (MLX5_CAP_GEN(mdev, apm)) 499 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 500 if (MLX5_CAP_GEN(mdev, xrc)) 501 props->device_cap_flags |= IB_DEVICE_XRC; 502 if (MLX5_CAP_GEN(mdev, imaicl)) { 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 504 IB_DEVICE_MEM_WINDOW_TYPE_2B; 505 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 506 /* We support 'Gappy' memory registration too */ 507 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 508 } 509 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 510 if (MLX5_CAP_GEN(mdev, sho)) { 511 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 512 /* At this stage no support for signature handover */ 513 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 514 IB_PROT_T10DIF_TYPE_2 | 515 IB_PROT_T10DIF_TYPE_3; 516 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 517 IB_GUARD_T10DIF_CSUM; 518 } 519 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 520 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 521 522 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 523 if (MLX5_CAP_ETH(mdev, csum_cap)) 524 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 525 526 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 527 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 528 if (max_tso) { 529 resp.tso_caps.max_tso = 1 << max_tso; 530 resp.tso_caps.supported_qpts |= 531 1 << IB_QPT_RAW_PACKET; 532 resp.response_length += sizeof(resp.tso_caps); 533 } 534 } 535 } 536 537 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 538 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 539 props->device_cap_flags |= IB_DEVICE_UD_TSO; 540 } 541 542 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 543 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 544 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 545 546 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 547 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 548 549 props->vendor_part_id = mdev->pdev->device; 550 props->hw_ver = mdev->pdev->revision; 551 552 props->max_mr_size = ~0ull; 553 props->page_size_cap = ~(min_page_size - 1); 554 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 555 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 556 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 557 sizeof(struct mlx5_wqe_data_seg); 558 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 559 sizeof(struct mlx5_wqe_ctrl_seg)) / 560 sizeof(struct mlx5_wqe_data_seg); 561 props->max_sge = min(max_rq_sg, max_sq_sg); 562 props->max_sge_rd = MLX5_MAX_SGE_RD; 563 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 564 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 565 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 566 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 567 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 568 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 569 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 570 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 571 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 572 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 573 props->max_srq_sge = max_rq_sg - 1; 574 props->max_fast_reg_page_list_len = 575 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 576 get_atomic_caps(dev, props); 577 props->masked_atomic_cap = IB_ATOMIC_NONE; 578 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 579 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 580 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 581 props->max_mcast_grp; 582 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 583 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 584 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 585 586 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 587 if (MLX5_CAP_GEN(mdev, pg)) 588 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 589 props->odp_caps = dev->odp_caps; 590 #endif 591 592 if (MLX5_CAP_GEN(mdev, cd)) 593 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 594 595 if (!mlx5_core_is_pf(mdev)) 596 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 597 598 if (uhw->outlen) { 599 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 600 601 if (err) 602 return err; 603 } 604 605 return 0; 606 } 607 608 enum mlx5_ib_width { 609 MLX5_IB_WIDTH_1X = 1 << 0, 610 MLX5_IB_WIDTH_2X = 1 << 1, 611 MLX5_IB_WIDTH_4X = 1 << 2, 612 MLX5_IB_WIDTH_8X = 1 << 3, 613 MLX5_IB_WIDTH_12X = 1 << 4 614 }; 615 616 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 617 u8 *ib_width) 618 { 619 struct mlx5_ib_dev *dev = to_mdev(ibdev); 620 int err = 0; 621 622 if (active_width & MLX5_IB_WIDTH_1X) { 623 *ib_width = IB_WIDTH_1X; 624 } else if (active_width & MLX5_IB_WIDTH_2X) { 625 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 626 (int)active_width); 627 err = -EINVAL; 628 } else if (active_width & MLX5_IB_WIDTH_4X) { 629 *ib_width = IB_WIDTH_4X; 630 } else if (active_width & MLX5_IB_WIDTH_8X) { 631 *ib_width = IB_WIDTH_8X; 632 } else if (active_width & MLX5_IB_WIDTH_12X) { 633 *ib_width = IB_WIDTH_12X; 634 } else { 635 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 636 (int)active_width); 637 err = -EINVAL; 638 } 639 640 return err; 641 } 642 643 static int mlx5_mtu_to_ib_mtu(int mtu) 644 { 645 switch (mtu) { 646 case 256: return 1; 647 case 512: return 2; 648 case 1024: return 3; 649 case 2048: return 4; 650 case 4096: return 5; 651 default: 652 pr_warn("invalid mtu\n"); 653 return -1; 654 } 655 } 656 657 enum ib_max_vl_num { 658 __IB_MAX_VL_0 = 1, 659 __IB_MAX_VL_0_1 = 2, 660 __IB_MAX_VL_0_3 = 3, 661 __IB_MAX_VL_0_7 = 4, 662 __IB_MAX_VL_0_14 = 5, 663 }; 664 665 enum mlx5_vl_hw_cap { 666 MLX5_VL_HW_0 = 1, 667 MLX5_VL_HW_0_1 = 2, 668 MLX5_VL_HW_0_2 = 3, 669 MLX5_VL_HW_0_3 = 4, 670 MLX5_VL_HW_0_4 = 5, 671 MLX5_VL_HW_0_5 = 6, 672 MLX5_VL_HW_0_6 = 7, 673 MLX5_VL_HW_0_7 = 8, 674 MLX5_VL_HW_0_14 = 15 675 }; 676 677 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 678 u8 *max_vl_num) 679 { 680 switch (vl_hw_cap) { 681 case MLX5_VL_HW_0: 682 *max_vl_num = __IB_MAX_VL_0; 683 break; 684 case MLX5_VL_HW_0_1: 685 *max_vl_num = __IB_MAX_VL_0_1; 686 break; 687 case MLX5_VL_HW_0_3: 688 *max_vl_num = __IB_MAX_VL_0_3; 689 break; 690 case MLX5_VL_HW_0_7: 691 *max_vl_num = __IB_MAX_VL_0_7; 692 break; 693 case MLX5_VL_HW_0_14: 694 *max_vl_num = __IB_MAX_VL_0_14; 695 break; 696 697 default: 698 return -EINVAL; 699 } 700 701 return 0; 702 } 703 704 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 705 struct ib_port_attr *props) 706 { 707 struct mlx5_ib_dev *dev = to_mdev(ibdev); 708 struct mlx5_core_dev *mdev = dev->mdev; 709 struct mlx5_hca_vport_context *rep; 710 u16 max_mtu; 711 u16 oper_mtu; 712 int err; 713 u8 ib_link_width_oper; 714 u8 vl_hw_cap; 715 716 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 717 if (!rep) { 718 err = -ENOMEM; 719 goto out; 720 } 721 722 memset(props, 0, sizeof(*props)); 723 724 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 725 if (err) 726 goto out; 727 728 props->lid = rep->lid; 729 props->lmc = rep->lmc; 730 props->sm_lid = rep->sm_lid; 731 props->sm_sl = rep->sm_sl; 732 props->state = rep->vport_state; 733 props->phys_state = rep->port_physical_state; 734 props->port_cap_flags = rep->cap_mask1; 735 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 736 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 737 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 738 props->bad_pkey_cntr = rep->pkey_violation_counter; 739 props->qkey_viol_cntr = rep->qkey_violation_counter; 740 props->subnet_timeout = rep->subnet_timeout; 741 props->init_type_reply = rep->init_type_reply; 742 props->grh_required = rep->grh_required; 743 744 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 745 if (err) 746 goto out; 747 748 err = translate_active_width(ibdev, ib_link_width_oper, 749 &props->active_width); 750 if (err) 751 goto out; 752 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 753 if (err) 754 goto out; 755 756 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 757 758 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 759 760 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 761 762 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 763 764 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 765 if (err) 766 goto out; 767 768 err = translate_max_vl_num(ibdev, vl_hw_cap, 769 &props->max_vl_num); 770 out: 771 kfree(rep); 772 return err; 773 } 774 775 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 776 struct ib_port_attr *props) 777 { 778 switch (mlx5_get_vport_access_method(ibdev)) { 779 case MLX5_VPORT_ACCESS_METHOD_MAD: 780 return mlx5_query_mad_ifc_port(ibdev, port, props); 781 782 case MLX5_VPORT_ACCESS_METHOD_HCA: 783 return mlx5_query_hca_port(ibdev, port, props); 784 785 case MLX5_VPORT_ACCESS_METHOD_NIC: 786 return mlx5_query_port_roce(ibdev, port, props); 787 788 default: 789 return -EINVAL; 790 } 791 } 792 793 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 794 union ib_gid *gid) 795 { 796 struct mlx5_ib_dev *dev = to_mdev(ibdev); 797 struct mlx5_core_dev *mdev = dev->mdev; 798 799 switch (mlx5_get_vport_access_method(ibdev)) { 800 case MLX5_VPORT_ACCESS_METHOD_MAD: 801 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 802 803 case MLX5_VPORT_ACCESS_METHOD_HCA: 804 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 805 806 default: 807 return -EINVAL; 808 } 809 810 } 811 812 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 813 u16 *pkey) 814 { 815 struct mlx5_ib_dev *dev = to_mdev(ibdev); 816 struct mlx5_core_dev *mdev = dev->mdev; 817 818 switch (mlx5_get_vport_access_method(ibdev)) { 819 case MLX5_VPORT_ACCESS_METHOD_MAD: 820 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 821 822 case MLX5_VPORT_ACCESS_METHOD_HCA: 823 case MLX5_VPORT_ACCESS_METHOD_NIC: 824 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 825 pkey); 826 default: 827 return -EINVAL; 828 } 829 } 830 831 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 832 struct ib_device_modify *props) 833 { 834 struct mlx5_ib_dev *dev = to_mdev(ibdev); 835 struct mlx5_reg_node_desc in; 836 struct mlx5_reg_node_desc out; 837 int err; 838 839 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 840 return -EOPNOTSUPP; 841 842 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 843 return 0; 844 845 /* 846 * If possible, pass node desc to FW, so it can generate 847 * a 144 trap. If cmd fails, just ignore. 848 */ 849 memcpy(&in, props->node_desc, 64); 850 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 851 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 852 if (err) 853 return err; 854 855 memcpy(ibdev->node_desc, props->node_desc, 64); 856 857 return err; 858 } 859 860 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 861 struct ib_port_modify *props) 862 { 863 struct mlx5_ib_dev *dev = to_mdev(ibdev); 864 struct ib_port_attr attr; 865 u32 tmp; 866 int err; 867 868 mutex_lock(&dev->cap_mask_mutex); 869 870 err = mlx5_ib_query_port(ibdev, port, &attr); 871 if (err) 872 goto out; 873 874 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 875 ~props->clr_port_cap_mask; 876 877 err = mlx5_set_port_caps(dev->mdev, port, tmp); 878 879 out: 880 mutex_unlock(&dev->cap_mask_mutex); 881 return err; 882 } 883 884 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 885 struct ib_udata *udata) 886 { 887 struct mlx5_ib_dev *dev = to_mdev(ibdev); 888 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 889 struct mlx5_ib_alloc_ucontext_resp resp = {}; 890 struct mlx5_ib_ucontext *context; 891 struct mlx5_uuar_info *uuari; 892 struct mlx5_uar *uars; 893 int gross_uuars; 894 int num_uars; 895 int ver; 896 int uuarn; 897 int err; 898 int i; 899 size_t reqlen; 900 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 901 max_cqe_version); 902 903 if (!dev->ib_active) 904 return ERR_PTR(-EAGAIN); 905 906 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 907 return ERR_PTR(-EINVAL); 908 909 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 910 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 911 ver = 0; 912 else if (reqlen >= min_req_v2) 913 ver = 2; 914 else 915 return ERR_PTR(-EINVAL); 916 917 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 918 if (err) 919 return ERR_PTR(err); 920 921 if (req.flags) 922 return ERR_PTR(-EINVAL); 923 924 if (req.total_num_uuars > MLX5_MAX_UUARS) 925 return ERR_PTR(-ENOMEM); 926 927 if (req.total_num_uuars == 0) 928 return ERR_PTR(-EINVAL); 929 930 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 931 return ERR_PTR(-EOPNOTSUPP); 932 933 if (reqlen > sizeof(req) && 934 !ib_is_udata_cleared(udata, sizeof(req), 935 reqlen - sizeof(req))) 936 return ERR_PTR(-EOPNOTSUPP); 937 938 req.total_num_uuars = ALIGN(req.total_num_uuars, 939 MLX5_NON_FP_BF_REGS_PER_PAGE); 940 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 941 return ERR_PTR(-EINVAL); 942 943 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 944 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 945 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 946 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 947 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 948 resp.cache_line_size = L1_CACHE_BYTES; 949 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 950 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 951 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 952 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 953 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 954 resp.cqe_version = min_t(__u8, 955 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 956 req.max_cqe_version); 957 resp.response_length = min(offsetof(typeof(resp), response_length) + 958 sizeof(resp.response_length), udata->outlen); 959 960 context = kzalloc(sizeof(*context), GFP_KERNEL); 961 if (!context) 962 return ERR_PTR(-ENOMEM); 963 964 uuari = &context->uuari; 965 mutex_init(&uuari->lock); 966 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 967 if (!uars) { 968 err = -ENOMEM; 969 goto out_ctx; 970 } 971 972 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 973 sizeof(*uuari->bitmap), 974 GFP_KERNEL); 975 if (!uuari->bitmap) { 976 err = -ENOMEM; 977 goto out_uar_ctx; 978 } 979 /* 980 * clear all fast path uuars 981 */ 982 for (i = 0; i < gross_uuars; i++) { 983 uuarn = i & 3; 984 if (uuarn == 2 || uuarn == 3) 985 set_bit(i, uuari->bitmap); 986 } 987 988 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 989 if (!uuari->count) { 990 err = -ENOMEM; 991 goto out_bitmap; 992 } 993 994 for (i = 0; i < num_uars; i++) { 995 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 996 if (err) 997 goto out_count; 998 } 999 1000 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1001 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1002 #endif 1003 1004 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1005 err = mlx5_core_alloc_transport_domain(dev->mdev, 1006 &context->tdn); 1007 if (err) 1008 goto out_uars; 1009 } 1010 1011 INIT_LIST_HEAD(&context->vma_private_list); 1012 INIT_LIST_HEAD(&context->db_page_list); 1013 mutex_init(&context->db_page_mutex); 1014 1015 resp.tot_uuars = req.total_num_uuars; 1016 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1017 1018 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1019 resp.response_length += sizeof(resp.cqe_version); 1020 1021 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1022 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE; 1023 resp.response_length += sizeof(resp.cmds_supp_uhw); 1024 } 1025 1026 /* 1027 * We don't want to expose information from the PCI bar that is located 1028 * after 4096 bytes, so if the arch only supports larger pages, let's 1029 * pretend we don't support reading the HCA's core clock. This is also 1030 * forced by mmap function. 1031 */ 1032 if (PAGE_SIZE <= 4096 && 1033 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1034 resp.comp_mask |= 1035 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1036 resp.hca_core_clock_offset = 1037 offsetof(struct mlx5_init_seg, internal_timer_h) % 1038 PAGE_SIZE; 1039 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1040 sizeof(resp.reserved2); 1041 } 1042 1043 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1044 if (err) 1045 goto out_td; 1046 1047 uuari->ver = ver; 1048 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1049 uuari->uars = uars; 1050 uuari->num_uars = num_uars; 1051 context->cqe_version = resp.cqe_version; 1052 1053 return &context->ibucontext; 1054 1055 out_td: 1056 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1057 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1058 1059 out_uars: 1060 for (i--; i >= 0; i--) 1061 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1062 out_count: 1063 kfree(uuari->count); 1064 1065 out_bitmap: 1066 kfree(uuari->bitmap); 1067 1068 out_uar_ctx: 1069 kfree(uars); 1070 1071 out_ctx: 1072 kfree(context); 1073 return ERR_PTR(err); 1074 } 1075 1076 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1077 { 1078 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1079 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1080 struct mlx5_uuar_info *uuari = &context->uuari; 1081 int i; 1082 1083 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1084 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1085 1086 for (i = 0; i < uuari->num_uars; i++) { 1087 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1088 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1089 } 1090 1091 kfree(uuari->count); 1092 kfree(uuari->bitmap); 1093 kfree(uuari->uars); 1094 kfree(context); 1095 1096 return 0; 1097 } 1098 1099 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1100 { 1101 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1102 } 1103 1104 static int get_command(unsigned long offset) 1105 { 1106 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1107 } 1108 1109 static int get_arg(unsigned long offset) 1110 { 1111 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1112 } 1113 1114 static int get_index(unsigned long offset) 1115 { 1116 return get_arg(offset); 1117 } 1118 1119 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1120 { 1121 /* vma_open is called when a new VMA is created on top of our VMA. This 1122 * is done through either mremap flow or split_vma (usually due to 1123 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1124 * as this VMA is strongly hardware related. Therefore we set the 1125 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1126 * calling us again and trying to do incorrect actions. We assume that 1127 * the original VMA size is exactly a single page, and therefore all 1128 * "splitting" operation will not happen to it. 1129 */ 1130 area->vm_ops = NULL; 1131 } 1132 1133 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1134 { 1135 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1136 1137 /* It's guaranteed that all VMAs opened on a FD are closed before the 1138 * file itself is closed, therefore no sync is needed with the regular 1139 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1140 * However need a sync with accessing the vma as part of 1141 * mlx5_ib_disassociate_ucontext. 1142 * The close operation is usually called under mm->mmap_sem except when 1143 * process is exiting. 1144 * The exiting case is handled explicitly as part of 1145 * mlx5_ib_disassociate_ucontext. 1146 */ 1147 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1148 1149 /* setting the vma context pointer to null in the mlx5_ib driver's 1150 * private data, to protect a race condition in 1151 * mlx5_ib_disassociate_ucontext(). 1152 */ 1153 mlx5_ib_vma_priv_data->vma = NULL; 1154 list_del(&mlx5_ib_vma_priv_data->list); 1155 kfree(mlx5_ib_vma_priv_data); 1156 } 1157 1158 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1159 .open = mlx5_ib_vma_open, 1160 .close = mlx5_ib_vma_close 1161 }; 1162 1163 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1164 struct mlx5_ib_ucontext *ctx) 1165 { 1166 struct mlx5_ib_vma_private_data *vma_prv; 1167 struct list_head *vma_head = &ctx->vma_private_list; 1168 1169 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1170 if (!vma_prv) 1171 return -ENOMEM; 1172 1173 vma_prv->vma = vma; 1174 vma->vm_private_data = vma_prv; 1175 vma->vm_ops = &mlx5_ib_vm_ops; 1176 1177 list_add(&vma_prv->list, vma_head); 1178 1179 return 0; 1180 } 1181 1182 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1183 { 1184 int ret; 1185 struct vm_area_struct *vma; 1186 struct mlx5_ib_vma_private_data *vma_private, *n; 1187 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1188 struct task_struct *owning_process = NULL; 1189 struct mm_struct *owning_mm = NULL; 1190 1191 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1192 if (!owning_process) 1193 return; 1194 1195 owning_mm = get_task_mm(owning_process); 1196 if (!owning_mm) { 1197 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1198 while (1) { 1199 put_task_struct(owning_process); 1200 usleep_range(1000, 2000); 1201 owning_process = get_pid_task(ibcontext->tgid, 1202 PIDTYPE_PID); 1203 if (!owning_process || 1204 owning_process->state == TASK_DEAD) { 1205 pr_info("disassociate ucontext done, task was terminated\n"); 1206 /* in case task was dead need to release the 1207 * task struct. 1208 */ 1209 if (owning_process) 1210 put_task_struct(owning_process); 1211 return; 1212 } 1213 } 1214 } 1215 1216 /* need to protect from a race on closing the vma as part of 1217 * mlx5_ib_vma_close. 1218 */ 1219 down_read(&owning_mm->mmap_sem); 1220 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1221 list) { 1222 vma = vma_private->vma; 1223 ret = zap_vma_ptes(vma, vma->vm_start, 1224 PAGE_SIZE); 1225 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1226 /* context going to be destroyed, should 1227 * not access ops any more. 1228 */ 1229 vma->vm_ops = NULL; 1230 list_del(&vma_private->list); 1231 kfree(vma_private); 1232 } 1233 up_read(&owning_mm->mmap_sem); 1234 mmput(owning_mm); 1235 put_task_struct(owning_process); 1236 } 1237 1238 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1239 { 1240 switch (cmd) { 1241 case MLX5_IB_MMAP_WC_PAGE: 1242 return "WC"; 1243 case MLX5_IB_MMAP_REGULAR_PAGE: 1244 return "best effort WC"; 1245 case MLX5_IB_MMAP_NC_PAGE: 1246 return "NC"; 1247 default: 1248 return NULL; 1249 } 1250 } 1251 1252 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1253 struct vm_area_struct *vma, 1254 struct mlx5_ib_ucontext *context) 1255 { 1256 struct mlx5_uuar_info *uuari = &context->uuari; 1257 int err; 1258 unsigned long idx; 1259 phys_addr_t pfn, pa; 1260 pgprot_t prot; 1261 1262 switch (cmd) { 1263 case MLX5_IB_MMAP_WC_PAGE: 1264 /* Some architectures don't support WC memory */ 1265 #if defined(CONFIG_X86) 1266 if (!pat_enabled()) 1267 return -EPERM; 1268 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1269 return -EPERM; 1270 #endif 1271 /* fall through */ 1272 case MLX5_IB_MMAP_REGULAR_PAGE: 1273 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1274 prot = pgprot_writecombine(vma->vm_page_prot); 1275 break; 1276 case MLX5_IB_MMAP_NC_PAGE: 1277 prot = pgprot_noncached(vma->vm_page_prot); 1278 break; 1279 default: 1280 return -EINVAL; 1281 } 1282 1283 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1284 return -EINVAL; 1285 1286 idx = get_index(vma->vm_pgoff); 1287 if (idx >= uuari->num_uars) 1288 return -EINVAL; 1289 1290 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1291 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1292 1293 vma->vm_page_prot = prot; 1294 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1295 PAGE_SIZE, vma->vm_page_prot); 1296 if (err) { 1297 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1298 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1299 return -EAGAIN; 1300 } 1301 1302 pa = pfn << PAGE_SHIFT; 1303 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1304 vma->vm_start, &pa); 1305 1306 return mlx5_ib_set_vma_data(vma, context); 1307 } 1308 1309 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1310 { 1311 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1312 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1313 unsigned long command; 1314 phys_addr_t pfn; 1315 1316 command = get_command(vma->vm_pgoff); 1317 switch (command) { 1318 case MLX5_IB_MMAP_WC_PAGE: 1319 case MLX5_IB_MMAP_NC_PAGE: 1320 case MLX5_IB_MMAP_REGULAR_PAGE: 1321 return uar_mmap(dev, command, vma, context); 1322 1323 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1324 return -ENOSYS; 1325 1326 case MLX5_IB_MMAP_CORE_CLOCK: 1327 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1328 return -EINVAL; 1329 1330 if (vma->vm_flags & VM_WRITE) 1331 return -EPERM; 1332 1333 /* Don't expose to user-space information it shouldn't have */ 1334 if (PAGE_SIZE > 4096) 1335 return -EOPNOTSUPP; 1336 1337 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1338 pfn = (dev->mdev->iseg_base + 1339 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1340 PAGE_SHIFT; 1341 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1342 PAGE_SIZE, vma->vm_page_prot)) 1343 return -EAGAIN; 1344 1345 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1346 vma->vm_start, 1347 (unsigned long long)pfn << PAGE_SHIFT); 1348 break; 1349 1350 default: 1351 return -EINVAL; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1358 struct ib_ucontext *context, 1359 struct ib_udata *udata) 1360 { 1361 struct mlx5_ib_alloc_pd_resp resp; 1362 struct mlx5_ib_pd *pd; 1363 int err; 1364 1365 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1366 if (!pd) 1367 return ERR_PTR(-ENOMEM); 1368 1369 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1370 if (err) { 1371 kfree(pd); 1372 return ERR_PTR(err); 1373 } 1374 1375 if (context) { 1376 resp.pdn = pd->pdn; 1377 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1378 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1379 kfree(pd); 1380 return ERR_PTR(-EFAULT); 1381 } 1382 } 1383 1384 return &pd->ibpd; 1385 } 1386 1387 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1388 { 1389 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1390 struct mlx5_ib_pd *mpd = to_mpd(pd); 1391 1392 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1393 kfree(mpd); 1394 1395 return 0; 1396 } 1397 1398 static bool outer_header_zero(u32 *match_criteria) 1399 { 1400 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1401 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1402 outer_headers); 1403 1404 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1405 outer_headers_c + 1, 1406 size - 1); 1407 } 1408 1409 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1410 union ib_flow_spec *ib_spec) 1411 { 1412 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1413 outer_headers); 1414 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1415 outer_headers); 1416 switch (ib_spec->type) { 1417 case IB_FLOW_SPEC_ETH: 1418 if (ib_spec->size != sizeof(ib_spec->eth)) 1419 return -EINVAL; 1420 1421 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1422 dmac_47_16), 1423 ib_spec->eth.mask.dst_mac); 1424 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1425 dmac_47_16), 1426 ib_spec->eth.val.dst_mac); 1427 1428 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1429 smac_47_16), 1430 ib_spec->eth.mask.src_mac); 1431 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1432 smac_47_16), 1433 ib_spec->eth.val.src_mac); 1434 1435 if (ib_spec->eth.mask.vlan_tag) { 1436 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1437 vlan_tag, 1); 1438 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1439 vlan_tag, 1); 1440 1441 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1442 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1443 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1444 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1445 1446 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1447 first_cfi, 1448 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1449 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1450 first_cfi, 1451 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1452 1453 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1454 first_prio, 1455 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1456 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1457 first_prio, 1458 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1459 } 1460 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1461 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1462 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1463 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1464 break; 1465 case IB_FLOW_SPEC_IPV4: 1466 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1467 return -EINVAL; 1468 1469 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1470 ethertype, 0xffff); 1471 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1472 ethertype, ETH_P_IP); 1473 1474 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1475 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1476 &ib_spec->ipv4.mask.src_ip, 1477 sizeof(ib_spec->ipv4.mask.src_ip)); 1478 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1479 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1480 &ib_spec->ipv4.val.src_ip, 1481 sizeof(ib_spec->ipv4.val.src_ip)); 1482 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1483 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1484 &ib_spec->ipv4.mask.dst_ip, 1485 sizeof(ib_spec->ipv4.mask.dst_ip)); 1486 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1487 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1488 &ib_spec->ipv4.val.dst_ip, 1489 sizeof(ib_spec->ipv4.val.dst_ip)); 1490 break; 1491 case IB_FLOW_SPEC_IPV6: 1492 if (ib_spec->size != sizeof(ib_spec->ipv6)) 1493 return -EINVAL; 1494 1495 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1496 ethertype, 0xffff); 1497 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1498 ethertype, ETH_P_IPV6); 1499 1500 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1501 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1502 &ib_spec->ipv6.mask.src_ip, 1503 sizeof(ib_spec->ipv6.mask.src_ip)); 1504 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1505 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1506 &ib_spec->ipv6.val.src_ip, 1507 sizeof(ib_spec->ipv6.val.src_ip)); 1508 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1509 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1510 &ib_spec->ipv6.mask.dst_ip, 1511 sizeof(ib_spec->ipv6.mask.dst_ip)); 1512 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1513 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1514 &ib_spec->ipv6.val.dst_ip, 1515 sizeof(ib_spec->ipv6.val.dst_ip)); 1516 break; 1517 case IB_FLOW_SPEC_TCP: 1518 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1519 return -EINVAL; 1520 1521 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1522 0xff); 1523 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1524 IPPROTO_TCP); 1525 1526 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1527 ntohs(ib_spec->tcp_udp.mask.src_port)); 1528 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1529 ntohs(ib_spec->tcp_udp.val.src_port)); 1530 1531 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1532 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1533 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1534 ntohs(ib_spec->tcp_udp.val.dst_port)); 1535 break; 1536 case IB_FLOW_SPEC_UDP: 1537 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1538 return -EINVAL; 1539 1540 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1541 0xff); 1542 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1543 IPPROTO_UDP); 1544 1545 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1546 ntohs(ib_spec->tcp_udp.mask.src_port)); 1547 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1548 ntohs(ib_spec->tcp_udp.val.src_port)); 1549 1550 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1551 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1552 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1553 ntohs(ib_spec->tcp_udp.val.dst_port)); 1554 break; 1555 default: 1556 return -EINVAL; 1557 } 1558 1559 return 0; 1560 } 1561 1562 /* If a flow could catch both multicast and unicast packets, 1563 * it won't fall into the multicast flow steering table and this rule 1564 * could steal other multicast packets. 1565 */ 1566 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1567 { 1568 struct ib_flow_spec_eth *eth_spec; 1569 1570 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1571 ib_attr->size < sizeof(struct ib_flow_attr) + 1572 sizeof(struct ib_flow_spec_eth) || 1573 ib_attr->num_of_specs < 1) 1574 return false; 1575 1576 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1577 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1578 eth_spec->size != sizeof(*eth_spec)) 1579 return false; 1580 1581 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1582 is_multicast_ether_addr(eth_spec->val.dst_mac); 1583 } 1584 1585 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1586 { 1587 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1588 bool has_ipv4_spec = false; 1589 bool eth_type_ipv4 = true; 1590 unsigned int spec_index; 1591 1592 /* Validate that ethertype is correct */ 1593 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1594 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1595 ib_spec->eth.mask.ether_type) { 1596 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1597 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1598 eth_type_ipv4 = false; 1599 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1600 has_ipv4_spec = true; 1601 } 1602 ib_spec = (void *)ib_spec + ib_spec->size; 1603 } 1604 return !has_ipv4_spec || eth_type_ipv4; 1605 } 1606 1607 static void put_flow_table(struct mlx5_ib_dev *dev, 1608 struct mlx5_ib_flow_prio *prio, bool ft_added) 1609 { 1610 prio->refcount -= !!ft_added; 1611 if (!prio->refcount) { 1612 mlx5_destroy_flow_table(prio->flow_table); 1613 prio->flow_table = NULL; 1614 } 1615 } 1616 1617 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1618 { 1619 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1620 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1621 struct mlx5_ib_flow_handler, 1622 ibflow); 1623 struct mlx5_ib_flow_handler *iter, *tmp; 1624 1625 mutex_lock(&dev->flow_db.lock); 1626 1627 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1628 mlx5_del_flow_rule(iter->rule); 1629 list_del(&iter->list); 1630 kfree(iter); 1631 } 1632 1633 mlx5_del_flow_rule(handler->rule); 1634 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1635 mutex_unlock(&dev->flow_db.lock); 1636 1637 kfree(handler); 1638 1639 return 0; 1640 } 1641 1642 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1643 { 1644 priority *= 2; 1645 if (!dont_trap) 1646 priority++; 1647 return priority; 1648 } 1649 1650 #define MLX5_FS_MAX_TYPES 10 1651 #define MLX5_FS_MAX_ENTRIES 32000UL 1652 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1653 struct ib_flow_attr *flow_attr) 1654 { 1655 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1656 struct mlx5_flow_namespace *ns = NULL; 1657 struct mlx5_ib_flow_prio *prio; 1658 struct mlx5_flow_table *ft; 1659 int num_entries; 1660 int num_groups; 1661 int priority; 1662 int err = 0; 1663 1664 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1665 if (flow_is_multicast_only(flow_attr) && 1666 !dont_trap) 1667 priority = MLX5_IB_FLOW_MCAST_PRIO; 1668 else 1669 priority = ib_prio_to_core_prio(flow_attr->priority, 1670 dont_trap); 1671 ns = mlx5_get_flow_namespace(dev->mdev, 1672 MLX5_FLOW_NAMESPACE_BYPASS); 1673 num_entries = MLX5_FS_MAX_ENTRIES; 1674 num_groups = MLX5_FS_MAX_TYPES; 1675 prio = &dev->flow_db.prios[priority]; 1676 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1677 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1678 ns = mlx5_get_flow_namespace(dev->mdev, 1679 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1680 build_leftovers_ft_param(&priority, 1681 &num_entries, 1682 &num_groups); 1683 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1684 } 1685 1686 if (!ns) 1687 return ERR_PTR(-ENOTSUPP); 1688 1689 ft = prio->flow_table; 1690 if (!ft) { 1691 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1692 num_entries, 1693 num_groups, 1694 0); 1695 1696 if (!IS_ERR(ft)) { 1697 prio->refcount = 0; 1698 prio->flow_table = ft; 1699 } else { 1700 err = PTR_ERR(ft); 1701 } 1702 } 1703 1704 return err ? ERR_PTR(err) : prio; 1705 } 1706 1707 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1708 struct mlx5_ib_flow_prio *ft_prio, 1709 struct ib_flow_attr *flow_attr, 1710 struct mlx5_flow_destination *dst) 1711 { 1712 struct mlx5_flow_table *ft = ft_prio->flow_table; 1713 struct mlx5_ib_flow_handler *handler; 1714 struct mlx5_flow_spec *spec; 1715 void *ib_flow = flow_attr + 1; 1716 unsigned int spec_index; 1717 u32 action; 1718 int err = 0; 1719 1720 if (!is_valid_attr(flow_attr)) 1721 return ERR_PTR(-EINVAL); 1722 1723 spec = mlx5_vzalloc(sizeof(*spec)); 1724 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1725 if (!handler || !spec) { 1726 err = -ENOMEM; 1727 goto free; 1728 } 1729 1730 INIT_LIST_HEAD(&handler->list); 1731 1732 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1733 err = parse_flow_attr(spec->match_criteria, 1734 spec->match_value, ib_flow); 1735 if (err < 0) 1736 goto free; 1737 1738 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1739 } 1740 1741 /* Outer header support only */ 1742 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria)) 1743 << 0; 1744 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1745 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1746 handler->rule = mlx5_add_flow_rule(ft, spec, 1747 action, 1748 MLX5_FS_DEFAULT_FLOW_TAG, 1749 dst); 1750 1751 if (IS_ERR(handler->rule)) { 1752 err = PTR_ERR(handler->rule); 1753 goto free; 1754 } 1755 1756 handler->prio = ft_prio - dev->flow_db.prios; 1757 1758 ft_prio->flow_table = ft; 1759 free: 1760 if (err) 1761 kfree(handler); 1762 kvfree(spec); 1763 return err ? ERR_PTR(err) : handler; 1764 } 1765 1766 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 1767 struct mlx5_ib_flow_prio *ft_prio, 1768 struct ib_flow_attr *flow_attr, 1769 struct mlx5_flow_destination *dst) 1770 { 1771 struct mlx5_ib_flow_handler *handler_dst = NULL; 1772 struct mlx5_ib_flow_handler *handler = NULL; 1773 1774 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 1775 if (!IS_ERR(handler)) { 1776 handler_dst = create_flow_rule(dev, ft_prio, 1777 flow_attr, dst); 1778 if (IS_ERR(handler_dst)) { 1779 mlx5_del_flow_rule(handler->rule); 1780 kfree(handler); 1781 handler = handler_dst; 1782 } else { 1783 list_add(&handler_dst->list, &handler->list); 1784 } 1785 } 1786 1787 return handler; 1788 } 1789 enum { 1790 LEFTOVERS_MC, 1791 LEFTOVERS_UC, 1792 }; 1793 1794 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1795 struct mlx5_ib_flow_prio *ft_prio, 1796 struct ib_flow_attr *flow_attr, 1797 struct mlx5_flow_destination *dst) 1798 { 1799 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1800 struct mlx5_ib_flow_handler *handler = NULL; 1801 1802 static struct { 1803 struct ib_flow_attr flow_attr; 1804 struct ib_flow_spec_eth eth_flow; 1805 } leftovers_specs[] = { 1806 [LEFTOVERS_MC] = { 1807 .flow_attr = { 1808 .num_of_specs = 1, 1809 .size = sizeof(leftovers_specs[0]) 1810 }, 1811 .eth_flow = { 1812 .type = IB_FLOW_SPEC_ETH, 1813 .size = sizeof(struct ib_flow_spec_eth), 1814 .mask = {.dst_mac = {0x1} }, 1815 .val = {.dst_mac = {0x1} } 1816 } 1817 }, 1818 [LEFTOVERS_UC] = { 1819 .flow_attr = { 1820 .num_of_specs = 1, 1821 .size = sizeof(leftovers_specs[0]) 1822 }, 1823 .eth_flow = { 1824 .type = IB_FLOW_SPEC_ETH, 1825 .size = sizeof(struct ib_flow_spec_eth), 1826 .mask = {.dst_mac = {0x1} }, 1827 .val = {.dst_mac = {} } 1828 } 1829 } 1830 }; 1831 1832 handler = create_flow_rule(dev, ft_prio, 1833 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1834 dst); 1835 if (!IS_ERR(handler) && 1836 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1837 handler_ucast = create_flow_rule(dev, ft_prio, 1838 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1839 dst); 1840 if (IS_ERR(handler_ucast)) { 1841 kfree(handler); 1842 handler = handler_ucast; 1843 } else { 1844 list_add(&handler_ucast->list, &handler->list); 1845 } 1846 } 1847 1848 return handler; 1849 } 1850 1851 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1852 struct ib_flow_attr *flow_attr, 1853 int domain) 1854 { 1855 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1856 struct mlx5_ib_qp *mqp = to_mqp(qp); 1857 struct mlx5_ib_flow_handler *handler = NULL; 1858 struct mlx5_flow_destination *dst = NULL; 1859 struct mlx5_ib_flow_prio *ft_prio; 1860 int err; 1861 1862 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1863 return ERR_PTR(-ENOSPC); 1864 1865 if (domain != IB_FLOW_DOMAIN_USER || 1866 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1867 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 1868 return ERR_PTR(-EINVAL); 1869 1870 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1871 if (!dst) 1872 return ERR_PTR(-ENOMEM); 1873 1874 mutex_lock(&dev->flow_db.lock); 1875 1876 ft_prio = get_flow_table(dev, flow_attr); 1877 if (IS_ERR(ft_prio)) { 1878 err = PTR_ERR(ft_prio); 1879 goto unlock; 1880 } 1881 1882 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1883 if (mqp->flags & MLX5_IB_QP_RSS) 1884 dst->tir_num = mqp->rss_qp.tirn; 1885 else 1886 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 1887 1888 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1889 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 1890 handler = create_dont_trap_rule(dev, ft_prio, 1891 flow_attr, dst); 1892 } else { 1893 handler = create_flow_rule(dev, ft_prio, flow_attr, 1894 dst); 1895 } 1896 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1897 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1898 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1899 dst); 1900 } else { 1901 err = -EINVAL; 1902 goto destroy_ft; 1903 } 1904 1905 if (IS_ERR(handler)) { 1906 err = PTR_ERR(handler); 1907 handler = NULL; 1908 goto destroy_ft; 1909 } 1910 1911 ft_prio->refcount++; 1912 mutex_unlock(&dev->flow_db.lock); 1913 kfree(dst); 1914 1915 return &handler->ibflow; 1916 1917 destroy_ft: 1918 put_flow_table(dev, ft_prio, false); 1919 unlock: 1920 mutex_unlock(&dev->flow_db.lock); 1921 kfree(dst); 1922 kfree(handler); 1923 return ERR_PTR(err); 1924 } 1925 1926 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1927 { 1928 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1929 int err; 1930 1931 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1932 if (err) 1933 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1934 ibqp->qp_num, gid->raw); 1935 1936 return err; 1937 } 1938 1939 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1940 { 1941 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1942 int err; 1943 1944 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1945 if (err) 1946 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1947 ibqp->qp_num, gid->raw); 1948 1949 return err; 1950 } 1951 1952 static int init_node_data(struct mlx5_ib_dev *dev) 1953 { 1954 int err; 1955 1956 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1957 if (err) 1958 return err; 1959 1960 dev->mdev->rev_id = dev->mdev->pdev->revision; 1961 1962 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1963 } 1964 1965 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1966 char *buf) 1967 { 1968 struct mlx5_ib_dev *dev = 1969 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1970 1971 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1972 } 1973 1974 static ssize_t show_reg_pages(struct device *device, 1975 struct device_attribute *attr, char *buf) 1976 { 1977 struct mlx5_ib_dev *dev = 1978 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1979 1980 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1981 } 1982 1983 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1984 char *buf) 1985 { 1986 struct mlx5_ib_dev *dev = 1987 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1988 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1989 } 1990 1991 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1992 char *buf) 1993 { 1994 struct mlx5_ib_dev *dev = 1995 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1996 return sprintf(buf, "%x\n", dev->mdev->rev_id); 1997 } 1998 1999 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2000 char *buf) 2001 { 2002 struct mlx5_ib_dev *dev = 2003 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2004 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2005 dev->mdev->board_id); 2006 } 2007 2008 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2009 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2010 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2011 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2012 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2013 2014 static struct device_attribute *mlx5_class_attributes[] = { 2015 &dev_attr_hw_rev, 2016 &dev_attr_hca_type, 2017 &dev_attr_board_id, 2018 &dev_attr_fw_pages, 2019 &dev_attr_reg_pages, 2020 }; 2021 2022 static void pkey_change_handler(struct work_struct *work) 2023 { 2024 struct mlx5_ib_port_resources *ports = 2025 container_of(work, struct mlx5_ib_port_resources, 2026 pkey_change_work); 2027 2028 mutex_lock(&ports->devr->mutex); 2029 mlx5_ib_gsi_pkey_change(ports->gsi); 2030 mutex_unlock(&ports->devr->mutex); 2031 } 2032 2033 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2034 { 2035 struct mlx5_ib_qp *mqp; 2036 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2037 struct mlx5_core_cq *mcq; 2038 struct list_head cq_armed_list; 2039 unsigned long flags_qp; 2040 unsigned long flags_cq; 2041 unsigned long flags; 2042 2043 INIT_LIST_HEAD(&cq_armed_list); 2044 2045 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2046 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2047 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2048 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2049 if (mqp->sq.tail != mqp->sq.head) { 2050 send_mcq = to_mcq(mqp->ibqp.send_cq); 2051 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2052 if (send_mcq->mcq.comp && 2053 mqp->ibqp.send_cq->comp_handler) { 2054 if (!send_mcq->mcq.reset_notify_added) { 2055 send_mcq->mcq.reset_notify_added = 1; 2056 list_add_tail(&send_mcq->mcq.reset_notify, 2057 &cq_armed_list); 2058 } 2059 } 2060 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2061 } 2062 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2063 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2064 /* no handling is needed for SRQ */ 2065 if (!mqp->ibqp.srq) { 2066 if (mqp->rq.tail != mqp->rq.head) { 2067 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2068 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2069 if (recv_mcq->mcq.comp && 2070 mqp->ibqp.recv_cq->comp_handler) { 2071 if (!recv_mcq->mcq.reset_notify_added) { 2072 recv_mcq->mcq.reset_notify_added = 1; 2073 list_add_tail(&recv_mcq->mcq.reset_notify, 2074 &cq_armed_list); 2075 } 2076 } 2077 spin_unlock_irqrestore(&recv_mcq->lock, 2078 flags_cq); 2079 } 2080 } 2081 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2082 } 2083 /*At that point all inflight post send were put to be executed as of we 2084 * lock/unlock above locks Now need to arm all involved CQs. 2085 */ 2086 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2087 mcq->comp(mcq); 2088 } 2089 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2090 } 2091 2092 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2093 enum mlx5_dev_event event, unsigned long param) 2094 { 2095 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2096 struct ib_event ibev; 2097 2098 u8 port = 0; 2099 2100 switch (event) { 2101 case MLX5_DEV_EVENT_SYS_ERROR: 2102 ibdev->ib_active = false; 2103 ibev.event = IB_EVENT_DEVICE_FATAL; 2104 mlx5_ib_handle_internal_error(ibdev); 2105 break; 2106 2107 case MLX5_DEV_EVENT_PORT_UP: 2108 ibev.event = IB_EVENT_PORT_ACTIVE; 2109 port = (u8)param; 2110 break; 2111 2112 case MLX5_DEV_EVENT_PORT_DOWN: 2113 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2114 ibev.event = IB_EVENT_PORT_ERR; 2115 port = (u8)param; 2116 break; 2117 2118 case MLX5_DEV_EVENT_LID_CHANGE: 2119 ibev.event = IB_EVENT_LID_CHANGE; 2120 port = (u8)param; 2121 break; 2122 2123 case MLX5_DEV_EVENT_PKEY_CHANGE: 2124 ibev.event = IB_EVENT_PKEY_CHANGE; 2125 port = (u8)param; 2126 2127 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2128 break; 2129 2130 case MLX5_DEV_EVENT_GUID_CHANGE: 2131 ibev.event = IB_EVENT_GID_CHANGE; 2132 port = (u8)param; 2133 break; 2134 2135 case MLX5_DEV_EVENT_CLIENT_REREG: 2136 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2137 port = (u8)param; 2138 break; 2139 } 2140 2141 ibev.device = &ibdev->ib_dev; 2142 ibev.element.port_num = port; 2143 2144 if (port < 1 || port > ibdev->num_ports) { 2145 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2146 return; 2147 } 2148 2149 if (ibdev->ib_active) 2150 ib_dispatch_event(&ibev); 2151 } 2152 2153 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2154 { 2155 int port; 2156 2157 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2158 mlx5_query_ext_port_caps(dev, port); 2159 } 2160 2161 static int get_port_caps(struct mlx5_ib_dev *dev) 2162 { 2163 struct ib_device_attr *dprops = NULL; 2164 struct ib_port_attr *pprops = NULL; 2165 int err = -ENOMEM; 2166 int port; 2167 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2168 2169 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2170 if (!pprops) 2171 goto out; 2172 2173 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2174 if (!dprops) 2175 goto out; 2176 2177 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2178 if (err) { 2179 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2180 goto out; 2181 } 2182 2183 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2184 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2185 if (err) { 2186 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2187 port, err); 2188 break; 2189 } 2190 dev->mdev->port_caps[port - 1].pkey_table_len = 2191 dprops->max_pkeys; 2192 dev->mdev->port_caps[port - 1].gid_table_len = 2193 pprops->gid_tbl_len; 2194 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2195 dprops->max_pkeys, pprops->gid_tbl_len); 2196 } 2197 2198 out: 2199 kfree(pprops); 2200 kfree(dprops); 2201 2202 return err; 2203 } 2204 2205 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2206 { 2207 int err; 2208 2209 err = mlx5_mr_cache_cleanup(dev); 2210 if (err) 2211 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2212 2213 mlx5_ib_destroy_qp(dev->umrc.qp); 2214 ib_free_cq(dev->umrc.cq); 2215 ib_dealloc_pd(dev->umrc.pd); 2216 } 2217 2218 enum { 2219 MAX_UMR_WR = 128, 2220 }; 2221 2222 static int create_umr_res(struct mlx5_ib_dev *dev) 2223 { 2224 struct ib_qp_init_attr *init_attr = NULL; 2225 struct ib_qp_attr *attr = NULL; 2226 struct ib_pd *pd; 2227 struct ib_cq *cq; 2228 struct ib_qp *qp; 2229 int ret; 2230 2231 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2232 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2233 if (!attr || !init_attr) { 2234 ret = -ENOMEM; 2235 goto error_0; 2236 } 2237 2238 pd = ib_alloc_pd(&dev->ib_dev); 2239 if (IS_ERR(pd)) { 2240 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2241 ret = PTR_ERR(pd); 2242 goto error_0; 2243 } 2244 2245 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2246 if (IS_ERR(cq)) { 2247 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2248 ret = PTR_ERR(cq); 2249 goto error_2; 2250 } 2251 2252 init_attr->send_cq = cq; 2253 init_attr->recv_cq = cq; 2254 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2255 init_attr->cap.max_send_wr = MAX_UMR_WR; 2256 init_attr->cap.max_send_sge = 1; 2257 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2258 init_attr->port_num = 1; 2259 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2260 if (IS_ERR(qp)) { 2261 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2262 ret = PTR_ERR(qp); 2263 goto error_3; 2264 } 2265 qp->device = &dev->ib_dev; 2266 qp->real_qp = qp; 2267 qp->uobject = NULL; 2268 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2269 2270 attr->qp_state = IB_QPS_INIT; 2271 attr->port_num = 1; 2272 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2273 IB_QP_PORT, NULL); 2274 if (ret) { 2275 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2276 goto error_4; 2277 } 2278 2279 memset(attr, 0, sizeof(*attr)); 2280 attr->qp_state = IB_QPS_RTR; 2281 attr->path_mtu = IB_MTU_256; 2282 2283 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2284 if (ret) { 2285 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2286 goto error_4; 2287 } 2288 2289 memset(attr, 0, sizeof(*attr)); 2290 attr->qp_state = IB_QPS_RTS; 2291 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2292 if (ret) { 2293 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2294 goto error_4; 2295 } 2296 2297 dev->umrc.qp = qp; 2298 dev->umrc.cq = cq; 2299 dev->umrc.pd = pd; 2300 2301 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2302 ret = mlx5_mr_cache_init(dev); 2303 if (ret) { 2304 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2305 goto error_4; 2306 } 2307 2308 kfree(attr); 2309 kfree(init_attr); 2310 2311 return 0; 2312 2313 error_4: 2314 mlx5_ib_destroy_qp(qp); 2315 2316 error_3: 2317 ib_free_cq(cq); 2318 2319 error_2: 2320 ib_dealloc_pd(pd); 2321 2322 error_0: 2323 kfree(attr); 2324 kfree(init_attr); 2325 return ret; 2326 } 2327 2328 static int create_dev_resources(struct mlx5_ib_resources *devr) 2329 { 2330 struct ib_srq_init_attr attr; 2331 struct mlx5_ib_dev *dev; 2332 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2333 int port; 2334 int ret = 0; 2335 2336 dev = container_of(devr, struct mlx5_ib_dev, devr); 2337 2338 mutex_init(&devr->mutex); 2339 2340 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2341 if (IS_ERR(devr->p0)) { 2342 ret = PTR_ERR(devr->p0); 2343 goto error0; 2344 } 2345 devr->p0->device = &dev->ib_dev; 2346 devr->p0->uobject = NULL; 2347 atomic_set(&devr->p0->usecnt, 0); 2348 2349 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2350 if (IS_ERR(devr->c0)) { 2351 ret = PTR_ERR(devr->c0); 2352 goto error1; 2353 } 2354 devr->c0->device = &dev->ib_dev; 2355 devr->c0->uobject = NULL; 2356 devr->c0->comp_handler = NULL; 2357 devr->c0->event_handler = NULL; 2358 devr->c0->cq_context = NULL; 2359 atomic_set(&devr->c0->usecnt, 0); 2360 2361 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2362 if (IS_ERR(devr->x0)) { 2363 ret = PTR_ERR(devr->x0); 2364 goto error2; 2365 } 2366 devr->x0->device = &dev->ib_dev; 2367 devr->x0->inode = NULL; 2368 atomic_set(&devr->x0->usecnt, 0); 2369 mutex_init(&devr->x0->tgt_qp_mutex); 2370 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2371 2372 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2373 if (IS_ERR(devr->x1)) { 2374 ret = PTR_ERR(devr->x1); 2375 goto error3; 2376 } 2377 devr->x1->device = &dev->ib_dev; 2378 devr->x1->inode = NULL; 2379 atomic_set(&devr->x1->usecnt, 0); 2380 mutex_init(&devr->x1->tgt_qp_mutex); 2381 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2382 2383 memset(&attr, 0, sizeof(attr)); 2384 attr.attr.max_sge = 1; 2385 attr.attr.max_wr = 1; 2386 attr.srq_type = IB_SRQT_XRC; 2387 attr.ext.xrc.cq = devr->c0; 2388 attr.ext.xrc.xrcd = devr->x0; 2389 2390 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2391 if (IS_ERR(devr->s0)) { 2392 ret = PTR_ERR(devr->s0); 2393 goto error4; 2394 } 2395 devr->s0->device = &dev->ib_dev; 2396 devr->s0->pd = devr->p0; 2397 devr->s0->uobject = NULL; 2398 devr->s0->event_handler = NULL; 2399 devr->s0->srq_context = NULL; 2400 devr->s0->srq_type = IB_SRQT_XRC; 2401 devr->s0->ext.xrc.xrcd = devr->x0; 2402 devr->s0->ext.xrc.cq = devr->c0; 2403 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2404 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2405 atomic_inc(&devr->p0->usecnt); 2406 atomic_set(&devr->s0->usecnt, 0); 2407 2408 memset(&attr, 0, sizeof(attr)); 2409 attr.attr.max_sge = 1; 2410 attr.attr.max_wr = 1; 2411 attr.srq_type = IB_SRQT_BASIC; 2412 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2413 if (IS_ERR(devr->s1)) { 2414 ret = PTR_ERR(devr->s1); 2415 goto error5; 2416 } 2417 devr->s1->device = &dev->ib_dev; 2418 devr->s1->pd = devr->p0; 2419 devr->s1->uobject = NULL; 2420 devr->s1->event_handler = NULL; 2421 devr->s1->srq_context = NULL; 2422 devr->s1->srq_type = IB_SRQT_BASIC; 2423 devr->s1->ext.xrc.cq = devr->c0; 2424 atomic_inc(&devr->p0->usecnt); 2425 atomic_set(&devr->s0->usecnt, 0); 2426 2427 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2428 INIT_WORK(&devr->ports[port].pkey_change_work, 2429 pkey_change_handler); 2430 devr->ports[port].devr = devr; 2431 } 2432 2433 return 0; 2434 2435 error5: 2436 mlx5_ib_destroy_srq(devr->s0); 2437 error4: 2438 mlx5_ib_dealloc_xrcd(devr->x1); 2439 error3: 2440 mlx5_ib_dealloc_xrcd(devr->x0); 2441 error2: 2442 mlx5_ib_destroy_cq(devr->c0); 2443 error1: 2444 mlx5_ib_dealloc_pd(devr->p0); 2445 error0: 2446 return ret; 2447 } 2448 2449 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2450 { 2451 struct mlx5_ib_dev *dev = 2452 container_of(devr, struct mlx5_ib_dev, devr); 2453 int port; 2454 2455 mlx5_ib_destroy_srq(devr->s1); 2456 mlx5_ib_destroy_srq(devr->s0); 2457 mlx5_ib_dealloc_xrcd(devr->x0); 2458 mlx5_ib_dealloc_xrcd(devr->x1); 2459 mlx5_ib_destroy_cq(devr->c0); 2460 mlx5_ib_dealloc_pd(devr->p0); 2461 2462 /* Make sure no change P_Key work items are still executing */ 2463 for (port = 0; port < dev->num_ports; ++port) 2464 cancel_work_sync(&devr->ports[port].pkey_change_work); 2465 } 2466 2467 static u32 get_core_cap_flags(struct ib_device *ibdev) 2468 { 2469 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2470 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2471 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2472 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2473 u32 ret = 0; 2474 2475 if (ll == IB_LINK_LAYER_INFINIBAND) 2476 return RDMA_CORE_PORT_IBA_IB; 2477 2478 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2479 return 0; 2480 2481 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2482 return 0; 2483 2484 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2485 ret |= RDMA_CORE_PORT_IBA_ROCE; 2486 2487 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2488 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2489 2490 return ret; 2491 } 2492 2493 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2494 struct ib_port_immutable *immutable) 2495 { 2496 struct ib_port_attr attr; 2497 int err; 2498 2499 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2500 if (err) 2501 return err; 2502 2503 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2504 immutable->gid_tbl_len = attr.gid_tbl_len; 2505 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2506 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2507 2508 return 0; 2509 } 2510 2511 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2512 size_t str_len) 2513 { 2514 struct mlx5_ib_dev *dev = 2515 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2516 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2517 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2518 } 2519 2520 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2521 { 2522 int err; 2523 2524 dev->roce.nb.notifier_call = mlx5_netdev_event; 2525 err = register_netdevice_notifier(&dev->roce.nb); 2526 if (err) 2527 return err; 2528 2529 err = mlx5_nic_vport_enable_roce(dev->mdev); 2530 if (err) 2531 goto err_unregister_netdevice_notifier; 2532 2533 return 0; 2534 2535 err_unregister_netdevice_notifier: 2536 unregister_netdevice_notifier(&dev->roce.nb); 2537 return err; 2538 } 2539 2540 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2541 { 2542 mlx5_nic_vport_disable_roce(dev->mdev); 2543 unregister_netdevice_notifier(&dev->roce.nb); 2544 } 2545 2546 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2547 { 2548 unsigned int i; 2549 2550 for (i = 0; i < dev->num_ports; i++) 2551 mlx5_core_dealloc_q_counter(dev->mdev, 2552 dev->port[i].q_cnt_id); 2553 } 2554 2555 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2556 { 2557 int i; 2558 int ret; 2559 2560 for (i = 0; i < dev->num_ports; i++) { 2561 ret = mlx5_core_alloc_q_counter(dev->mdev, 2562 &dev->port[i].q_cnt_id); 2563 if (ret) { 2564 mlx5_ib_warn(dev, 2565 "couldn't allocate queue counter for port %d, err %d\n", 2566 i + 1, ret); 2567 goto dealloc_counters; 2568 } 2569 } 2570 2571 return 0; 2572 2573 dealloc_counters: 2574 while (--i >= 0) 2575 mlx5_core_dealloc_q_counter(dev->mdev, 2576 dev->port[i].q_cnt_id); 2577 2578 return ret; 2579 } 2580 2581 static const char * const names[] = { 2582 "rx_write_requests", 2583 "rx_read_requests", 2584 "rx_atomic_requests", 2585 "out_of_buffer", 2586 "out_of_sequence", 2587 "duplicate_request", 2588 "rnr_nak_retry_err", 2589 "packet_seq_err", 2590 "implied_nak_seq_err", 2591 "local_ack_timeout_err", 2592 }; 2593 2594 static const size_t stats_offsets[] = { 2595 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 2596 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 2597 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 2598 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 2599 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 2600 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 2601 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 2602 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 2603 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 2604 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 2605 }; 2606 2607 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 2608 u8 port_num) 2609 { 2610 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 2611 2612 /* We support only per port stats */ 2613 if (port_num == 0) 2614 return NULL; 2615 2616 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 2617 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2618 } 2619 2620 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 2621 struct rdma_hw_stats *stats, 2622 u8 port, int index) 2623 { 2624 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2625 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 2626 void *out; 2627 __be32 val; 2628 int ret; 2629 int i; 2630 2631 if (!port || !stats) 2632 return -ENOSYS; 2633 2634 out = mlx5_vzalloc(outlen); 2635 if (!out) 2636 return -ENOMEM; 2637 2638 ret = mlx5_core_query_q_counter(dev->mdev, 2639 dev->port[port - 1].q_cnt_id, 0, 2640 out, outlen); 2641 if (ret) 2642 goto free; 2643 2644 for (i = 0; i < ARRAY_SIZE(names); i++) { 2645 val = *(__be32 *)(out + stats_offsets[i]); 2646 stats->value[i] = (u64)be32_to_cpu(val); 2647 } 2648 free: 2649 kvfree(out); 2650 return ARRAY_SIZE(names); 2651 } 2652 2653 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2654 { 2655 struct mlx5_ib_dev *dev; 2656 enum rdma_link_layer ll; 2657 int port_type_cap; 2658 int err; 2659 int i; 2660 2661 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2662 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2663 2664 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2665 return NULL; 2666 2667 printk_once(KERN_INFO "%s", mlx5_version); 2668 2669 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2670 if (!dev) 2671 return NULL; 2672 2673 dev->mdev = mdev; 2674 2675 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 2676 GFP_KERNEL); 2677 if (!dev->port) 2678 goto err_dealloc; 2679 2680 rwlock_init(&dev->roce.netdev_lock); 2681 err = get_port_caps(dev); 2682 if (err) 2683 goto err_free_port; 2684 2685 if (mlx5_use_mad_ifc(dev)) 2686 get_ext_port_caps(dev); 2687 2688 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2689 2690 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2691 dev->ib_dev.owner = THIS_MODULE; 2692 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2693 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2694 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2695 dev->ib_dev.phys_port_cnt = dev->num_ports; 2696 dev->ib_dev.num_comp_vectors = 2697 dev->mdev->priv.eq_table.num_comp_vectors; 2698 dev->ib_dev.dma_device = &mdev->pdev->dev; 2699 2700 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2701 dev->ib_dev.uverbs_cmd_mask = 2702 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2703 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2704 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2705 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2706 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2707 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2708 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2709 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2710 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2711 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2712 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2713 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2714 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2715 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2716 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2717 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2718 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2719 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2720 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2721 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2722 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2723 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2724 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2725 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2726 dev->ib_dev.uverbs_ex_cmd_mask = 2727 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2728 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2729 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2730 2731 dev->ib_dev.query_device = mlx5_ib_query_device; 2732 dev->ib_dev.query_port = mlx5_ib_query_port; 2733 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2734 if (ll == IB_LINK_LAYER_ETHERNET) 2735 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2736 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2737 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2738 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2739 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2740 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2741 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2742 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2743 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2744 dev->ib_dev.mmap = mlx5_ib_mmap; 2745 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2746 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2747 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2748 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2749 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2750 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2751 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2752 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2753 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2754 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2755 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2756 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2757 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2758 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2759 dev->ib_dev.post_send = mlx5_ib_post_send; 2760 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2761 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2762 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2763 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2764 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2765 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2766 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2767 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2768 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2769 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 2770 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2771 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2772 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2773 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2774 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2775 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2776 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2777 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2778 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 2779 if (mlx5_core_is_pf(mdev)) { 2780 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 2781 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 2782 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 2783 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 2784 } 2785 2786 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 2787 2788 mlx5_ib_internal_fill_odp_caps(dev); 2789 2790 if (MLX5_CAP_GEN(mdev, imaicl)) { 2791 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 2792 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 2793 dev->ib_dev.uverbs_cmd_mask |= 2794 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2795 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2796 } 2797 2798 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 2799 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 2800 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 2801 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 2802 } 2803 2804 if (MLX5_CAP_GEN(mdev, xrc)) { 2805 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2806 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2807 dev->ib_dev.uverbs_cmd_mask |= 2808 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2809 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2810 } 2811 2812 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2813 IB_LINK_LAYER_ETHERNET) { 2814 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2815 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2816 dev->ib_dev.create_wq = mlx5_ib_create_wq; 2817 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 2818 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 2819 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 2820 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 2821 dev->ib_dev.uverbs_ex_cmd_mask |= 2822 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2823 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 2824 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2825 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2826 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2827 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2828 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2829 } 2830 err = init_node_data(dev); 2831 if (err) 2832 goto err_dealloc; 2833 2834 mutex_init(&dev->flow_db.lock); 2835 mutex_init(&dev->cap_mask_mutex); 2836 INIT_LIST_HEAD(&dev->qp_list); 2837 spin_lock_init(&dev->reset_flow_resource_lock); 2838 2839 if (ll == IB_LINK_LAYER_ETHERNET) { 2840 err = mlx5_enable_roce(dev); 2841 if (err) 2842 goto err_dealloc; 2843 } 2844 2845 err = create_dev_resources(&dev->devr); 2846 if (err) 2847 goto err_disable_roce; 2848 2849 err = mlx5_ib_odp_init_one(dev); 2850 if (err) 2851 goto err_rsrc; 2852 2853 err = mlx5_ib_alloc_q_counters(dev); 2854 if (err) 2855 goto err_odp; 2856 2857 err = ib_register_device(&dev->ib_dev, NULL); 2858 if (err) 2859 goto err_q_cnt; 2860 2861 err = create_umr_res(dev); 2862 if (err) 2863 goto err_dev; 2864 2865 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2866 err = device_create_file(&dev->ib_dev.dev, 2867 mlx5_class_attributes[i]); 2868 if (err) 2869 goto err_umrc; 2870 } 2871 2872 dev->ib_active = true; 2873 2874 return dev; 2875 2876 err_umrc: 2877 destroy_umrc_res(dev); 2878 2879 err_dev: 2880 ib_unregister_device(&dev->ib_dev); 2881 2882 err_q_cnt: 2883 mlx5_ib_dealloc_q_counters(dev); 2884 2885 err_odp: 2886 mlx5_ib_odp_remove_one(dev); 2887 2888 err_rsrc: 2889 destroy_dev_resources(&dev->devr); 2890 2891 err_disable_roce: 2892 if (ll == IB_LINK_LAYER_ETHERNET) 2893 mlx5_disable_roce(dev); 2894 2895 err_free_port: 2896 kfree(dev->port); 2897 2898 err_dealloc: 2899 ib_dealloc_device((struct ib_device *)dev); 2900 2901 return NULL; 2902 } 2903 2904 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2905 { 2906 struct mlx5_ib_dev *dev = context; 2907 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2908 2909 ib_unregister_device(&dev->ib_dev); 2910 mlx5_ib_dealloc_q_counters(dev); 2911 destroy_umrc_res(dev); 2912 mlx5_ib_odp_remove_one(dev); 2913 destroy_dev_resources(&dev->devr); 2914 if (ll == IB_LINK_LAYER_ETHERNET) 2915 mlx5_disable_roce(dev); 2916 kfree(dev->port); 2917 ib_dealloc_device(&dev->ib_dev); 2918 } 2919 2920 static struct mlx5_interface mlx5_ib_interface = { 2921 .add = mlx5_ib_add, 2922 .remove = mlx5_ib_remove, 2923 .event = mlx5_ib_event, 2924 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2925 }; 2926 2927 static int __init mlx5_ib_init(void) 2928 { 2929 int err; 2930 2931 if (deprecated_prof_sel != 2) 2932 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2933 2934 err = mlx5_ib_odp_init(); 2935 if (err) 2936 return err; 2937 2938 err = mlx5_register_interface(&mlx5_ib_interface); 2939 if (err) 2940 goto clean_odp; 2941 2942 return err; 2943 2944 clean_odp: 2945 mlx5_ib_odp_cleanup(); 2946 return err; 2947 } 2948 2949 static void __exit mlx5_ib_cleanup(void) 2950 { 2951 mlx5_unregister_interface(&mlx5_ib_interface); 2952 mlx5_ib_odp_cleanup(); 2953 } 2954 2955 module_init(mlx5_ib_init); 2956 module_exit(mlx5_ib_cleanup); 2957