1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/mlx5/driver.h> 28 #include <linux/list.h> 29 #include <rdma/ib_smi.h> 30 #include <rdma/ib_umem_odp.h> 31 #include <rdma/lag.h> 32 #include <linux/in.h> 33 #include <linux/etherdevice.h> 34 #include "mlx5_ib.h" 35 #include "ib_rep.h" 36 #include "cmd.h" 37 #include "devx.h" 38 #include "dm.h" 39 #include "fs.h" 40 #include "srq.h" 41 #include "qp.h" 42 #include "wr.h" 43 #include "restrack.h" 44 #include "counters.h" 45 #include "umr.h" 46 #include <rdma/uverbs_std_types.h> 47 #include <rdma/uverbs_ioctl.h> 48 #include <rdma/mlx5_user_ioctl_verbs.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 #include <rdma/ib_ucaps.h> 51 #include "macsec.h" 52 #include "data_direct.h" 53 #include "dmah.h" 54 55 #define UVERBS_MODULE_NAME mlx5_ib 56 #include <rdma/uverbs_named_ioctl.h> 57 58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 59 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 62 struct mlx5_ib_event_work { 63 struct work_struct work; 64 union { 65 struct mlx5_ib_dev *dev; 66 struct mlx5_ib_multiport_info *mpi; 67 }; 68 bool is_slave; 69 unsigned int event; 70 void *param; 71 }; 72 73 enum { 74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 75 }; 76 77 static struct workqueue_struct *mlx5_ib_event_wq; 78 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 79 static LIST_HEAD(mlx5_ib_dev_list); 80 /* 81 * This mutex should be held when accessing either of the above lists 82 */ 83 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 84 85 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 86 { 87 struct mlx5_ib_dev *dev; 88 89 mutex_lock(&mlx5_ib_multiport_mutex); 90 dev = mpi->ibdev; 91 mutex_unlock(&mlx5_ib_multiport_mutex); 92 return dev; 93 } 94 95 static enum rdma_link_layer 96 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 97 { 98 switch (port_type_cap) { 99 case MLX5_CAP_PORT_TYPE_IB: 100 return IB_LINK_LAYER_INFINIBAND; 101 case MLX5_CAP_PORT_TYPE_ETH: 102 return IB_LINK_LAYER_ETHERNET; 103 default: 104 return IB_LINK_LAYER_UNSPECIFIED; 105 } 106 } 107 108 static enum rdma_link_layer 109 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 110 { 111 struct mlx5_ib_dev *dev = to_mdev(device); 112 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 113 114 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 115 } 116 117 static int get_port_state(struct ib_device *ibdev, 118 u32 port_num, 119 enum ib_port_state *state) 120 { 121 struct ib_port_attr attr; 122 int ret; 123 124 memset(&attr, 0, sizeof(attr)); 125 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 126 if (!ret) 127 *state = attr.state; 128 return ret; 129 } 130 131 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 132 struct net_device *ndev, 133 struct net_device *upper, 134 u32 *port_num) 135 { 136 struct net_device *rep_ndev; 137 struct mlx5_ib_port *port; 138 int i; 139 140 for (i = 0; i < dev->num_ports; i++) { 141 port = &dev->port[i]; 142 if (!port->rep) 143 continue; 144 145 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 146 *port_num = i + 1; 147 return &port->roce; 148 } 149 150 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 151 continue; 152 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 153 if (rep_ndev && rep_ndev == ndev) { 154 dev_put(rep_ndev); 155 *port_num = i + 1; 156 return &port->roce; 157 } 158 159 dev_put(rep_ndev); 160 } 161 162 return NULL; 163 } 164 165 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 166 struct net_device *ndev, 167 struct net_device *upper, 168 struct net_device *ib_ndev) 169 { 170 if (!dev->ib_active) 171 return false; 172 173 /* Event is about our upper device */ 174 if (upper == ndev) 175 return true; 176 177 /* RDMA device is not in lag and not in switchdev */ 178 if (!dev->is_rep && !upper && ndev == ib_ndev) 179 return true; 180 181 /* RDMA devie is in switchdev */ 182 if (dev->is_rep && ndev == ib_ndev) 183 return true; 184 185 return false; 186 } 187 188 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 189 { 190 struct mlx5_ib_port *port; 191 int i; 192 193 for (i = 0; i < ibdev->num_ports; i++) { 194 port = &ibdev->port[i]; 195 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 196 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 197 } 198 } 199 200 return NULL; 201 } 202 203 static int mlx5_netdev_event(struct notifier_block *this, 204 unsigned long event, void *ptr) 205 { 206 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 207 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 208 u32 port_num = roce->native_port_num; 209 struct net_device *ib_ndev = NULL; 210 struct mlx5_core_dev *mdev; 211 struct mlx5_ib_dev *ibdev; 212 213 ibdev = roce->dev; 214 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 215 if (!mdev) 216 return NOTIFY_DONE; 217 218 switch (event) { 219 case NETDEV_REGISTER: 220 /* Should already be registered during the load */ 221 if (ibdev->is_rep) 222 break; 223 224 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 225 /* Exit if already registered */ 226 if (ib_ndev) 227 goto put_ndev; 228 229 if (ndev->dev.parent == mdev->device) 230 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 231 break; 232 233 case NETDEV_UNREGISTER: 234 /* In case of reps, ib device goes away before the netdevs */ 235 if (ibdev->is_rep) 236 break; 237 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 238 if (ib_ndev == ndev) 239 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 240 goto put_ndev; 241 242 case NETDEV_CHANGE: 243 case NETDEV_UP: 244 case NETDEV_DOWN: { 245 struct net_device *upper = NULL; 246 247 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 248 !mlx5_core_mp_enabled(mdev)) 249 return NOTIFY_DONE; 250 251 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 252 struct net_device *lag_ndev; 253 254 if(mlx5_lag_is_roce(mdev)) 255 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 256 else /* sriov lag */ 257 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 258 259 if (lag_ndev) { 260 upper = netdev_master_upper_dev_get(lag_ndev); 261 dev_put(lag_ndev); 262 } else { 263 goto done; 264 } 265 } 266 267 if (ibdev->is_rep) 268 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 269 if (!roce) 270 return NOTIFY_DONE; 271 272 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 273 274 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 275 struct ib_event ibev = { }; 276 enum ib_port_state port_state; 277 278 if (get_port_state(&ibdev->ib_dev, port_num, 279 &port_state)) 280 goto put_ndev; 281 282 if (roce->last_port_state == port_state) 283 goto put_ndev; 284 285 roce->last_port_state = port_state; 286 ibev.device = &ibdev->ib_dev; 287 if (port_state == IB_PORT_DOWN) 288 ibev.event = IB_EVENT_PORT_ERR; 289 else if (port_state == IB_PORT_ACTIVE) 290 ibev.event = IB_EVENT_PORT_ACTIVE; 291 else 292 goto put_ndev; 293 294 ibev.element.port_num = port_num; 295 ib_dispatch_event(&ibev); 296 } 297 break; 298 } 299 300 default: 301 break; 302 } 303 put_ndev: 304 dev_put(ib_ndev); 305 done: 306 mlx5_ib_put_native_port_mdev(ibdev, port_num); 307 return NOTIFY_DONE; 308 } 309 310 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 311 u32 ib_port_num, 312 u32 *native_port_num) 313 { 314 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 315 ib_port_num); 316 struct mlx5_core_dev *mdev = NULL; 317 struct mlx5_ib_multiport_info *mpi; 318 struct mlx5_ib_port *port; 319 320 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 321 if (native_port_num) 322 *native_port_num = smi_to_native_portnum(ibdev, 323 ib_port_num); 324 return ibdev->mdev; 325 326 } 327 328 if (!mlx5_core_mp_enabled(ibdev->mdev) || 329 ll != IB_LINK_LAYER_ETHERNET) { 330 if (native_port_num) 331 *native_port_num = ib_port_num; 332 return ibdev->mdev; 333 } 334 335 if (native_port_num) 336 *native_port_num = 1; 337 338 port = &ibdev->port[ib_port_num - 1]; 339 spin_lock(&port->mp.mpi_lock); 340 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 341 if (mpi && !mpi->unaffiliate) { 342 mdev = mpi->mdev; 343 /* If it's the master no need to refcount, it'll exist 344 * as long as the ib_dev exists. 345 */ 346 if (!mpi->is_master) 347 mpi->mdev_refcnt++; 348 } 349 spin_unlock(&port->mp.mpi_lock); 350 351 return mdev; 352 } 353 354 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 355 { 356 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 357 port_num); 358 struct mlx5_ib_multiport_info *mpi; 359 struct mlx5_ib_port *port; 360 361 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 362 return; 363 364 port = &ibdev->port[port_num - 1]; 365 366 spin_lock(&port->mp.mpi_lock); 367 mpi = ibdev->port[port_num - 1].mp.mpi; 368 if (mpi->is_master) 369 goto out; 370 371 mpi->mdev_refcnt--; 372 if (mpi->unaffiliate) 373 complete(&mpi->unref_comp); 374 out: 375 spin_unlock(&port->mp.mpi_lock); 376 } 377 378 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 379 u16 *active_speed, u8 *active_width) 380 { 381 switch (eth_proto_oper) { 382 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 383 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 384 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 385 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 386 *active_width = IB_WIDTH_1X; 387 *active_speed = IB_SPEED_SDR; 388 break; 389 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_EDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 409 *active_width = IB_WIDTH_4X; 410 *active_speed = IB_SPEED_QDR; 411 break; 412 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 415 *active_width = IB_WIDTH_1X; 416 *active_speed = IB_SPEED_HDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 419 *active_width = IB_WIDTH_4X; 420 *active_speed = IB_SPEED_FDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 return 0; 434 } 435 436 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 437 u8 *active_width) 438 { 439 switch (eth_proto_oper) { 440 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 441 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 442 *active_width = IB_WIDTH_1X; 443 *active_speed = IB_SPEED_SDR; 444 break; 445 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 446 *active_width = IB_WIDTH_1X; 447 *active_speed = IB_SPEED_DDR; 448 break; 449 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 450 *active_width = IB_WIDTH_1X; 451 *active_speed = IB_SPEED_QDR; 452 break; 453 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 454 *active_width = IB_WIDTH_4X; 455 *active_speed = IB_SPEED_QDR; 456 break; 457 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 458 *active_width = IB_WIDTH_1X; 459 *active_speed = IB_SPEED_EDR; 460 break; 461 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 462 *active_width = IB_WIDTH_2X; 463 *active_speed = IB_SPEED_EDR; 464 break; 465 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 466 *active_width = IB_WIDTH_1X; 467 *active_speed = IB_SPEED_HDR; 468 break; 469 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 470 *active_width = IB_WIDTH_4X; 471 *active_speed = IB_SPEED_EDR; 472 break; 473 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 474 *active_width = IB_WIDTH_2X; 475 *active_speed = IB_SPEED_HDR; 476 break; 477 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 478 *active_width = IB_WIDTH_1X; 479 *active_speed = IB_SPEED_NDR; 480 break; 481 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 482 *active_width = IB_WIDTH_4X; 483 *active_speed = IB_SPEED_HDR; 484 break; 485 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 486 *active_width = IB_WIDTH_2X; 487 *active_speed = IB_SPEED_NDR; 488 break; 489 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 490 *active_width = IB_WIDTH_1X; 491 *active_speed = IB_SPEED_XDR; 492 break; 493 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 494 *active_width = IB_WIDTH_8X; 495 *active_speed = IB_SPEED_HDR; 496 break; 497 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 498 *active_width = IB_WIDTH_4X; 499 *active_speed = IB_SPEED_NDR; 500 break; 501 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 502 *active_width = IB_WIDTH_2X; 503 *active_speed = IB_SPEED_XDR; 504 break; 505 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 506 *active_width = IB_WIDTH_8X; 507 *active_speed = IB_SPEED_NDR; 508 break; 509 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 510 *active_width = IB_WIDTH_4X; 511 *active_speed = IB_SPEED_XDR; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 return 0; 518 } 519 520 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 521 u8 *active_width, bool ext) 522 { 523 return ext ? 524 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 525 active_width) : 526 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 527 active_width); 528 } 529 530 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 531 struct ib_port_attr *props) 532 { 533 struct mlx5_ib_dev *dev = to_mdev(device); 534 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 535 struct mlx5_core_dev *mdev; 536 struct net_device *ndev, *upper; 537 enum ib_mtu ndev_ib_mtu; 538 bool put_mdev = true; 539 u32 eth_prot_oper; 540 u32 mdev_port_num; 541 bool ext; 542 int err; 543 544 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 545 if (!mdev) { 546 /* This means the port isn't affiliated yet. Get the 547 * info for the master port instead. 548 */ 549 put_mdev = false; 550 mdev = dev->mdev; 551 mdev_port_num = 1; 552 port_num = 1; 553 } 554 555 /* Possible bad flows are checked before filling out props so in case 556 * of an error it will still be zeroed out. 557 * Use native port in case of reps 558 */ 559 if (dev->is_rep) 560 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 561 1, 0); 562 else 563 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 564 mdev_port_num, 0); 565 if (err) 566 goto out; 567 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 568 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 569 570 props->active_width = IB_WIDTH_4X; 571 props->active_speed = IB_SPEED_QDR; 572 573 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 574 &props->active_width, ext); 575 576 if (!dev->is_rep && dev->mdev->roce.roce_en) { 577 u16 qkey_viol_cntr; 578 579 props->port_cap_flags |= IB_PORT_CM_SUP; 580 props->ip_gids = true; 581 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 582 roce_address_table_size); 583 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 584 props->qkey_viol_cntr = qkey_viol_cntr; 585 } 586 props->max_mtu = IB_MTU_4096; 587 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 588 props->pkey_tbl_len = 1; 589 props->state = IB_PORT_DOWN; 590 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 591 592 /* If this is a stub query for an unaffiliated port stop here */ 593 if (!put_mdev) 594 goto out; 595 596 ndev = ib_device_get_netdev(device, port_num); 597 if (!ndev) 598 goto out; 599 600 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 601 rcu_read_lock(); 602 upper = netdev_master_upper_dev_get_rcu(ndev); 603 if (upper) { 604 dev_put(ndev); 605 ndev = upper; 606 dev_hold(ndev); 607 } 608 rcu_read_unlock(); 609 } 610 611 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 612 props->state = IB_PORT_ACTIVE; 613 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 614 } 615 616 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 617 618 dev_put(ndev); 619 620 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 621 out: 622 if (put_mdev) 623 mlx5_ib_put_native_port_mdev(dev, port_num); 624 return err; 625 } 626 627 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 628 unsigned int index, const union ib_gid *gid, 629 const struct ib_gid_attr *attr) 630 { 631 enum ib_gid_type gid_type; 632 u16 vlan_id = 0xffff; 633 u8 roce_version = 0; 634 u8 roce_l3_type = 0; 635 u8 mac[ETH_ALEN]; 636 int ret; 637 638 gid_type = attr->gid_type; 639 if (gid) { 640 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 641 if (ret) 642 return ret; 643 } 644 645 switch (gid_type) { 646 case IB_GID_TYPE_ROCE: 647 roce_version = MLX5_ROCE_VERSION_1; 648 break; 649 case IB_GID_TYPE_ROCE_UDP_ENCAP: 650 roce_version = MLX5_ROCE_VERSION_2; 651 if (gid && ipv6_addr_v4mapped((void *)gid)) 652 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 653 else 654 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 655 break; 656 657 default: 658 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 659 } 660 661 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 662 roce_l3_type, gid->raw, mac, 663 vlan_id < VLAN_CFI_MASK, vlan_id, 664 port_num); 665 } 666 667 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 668 __always_unused void **context) 669 { 670 int ret; 671 672 ret = mlx5r_add_gid_macsec_operations(attr); 673 if (ret) 674 return ret; 675 676 return set_roce_addr(to_mdev(attr->device), attr->port_num, 677 attr->index, &attr->gid, attr); 678 } 679 680 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 681 __always_unused void **context) 682 { 683 int ret; 684 685 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 686 attr->index, NULL, attr); 687 if (ret) 688 return ret; 689 690 mlx5r_del_gid_macsec_operations(attr); 691 return 0; 692 } 693 694 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 695 const struct ib_gid_attr *attr) 696 { 697 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 698 return 0; 699 700 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 701 } 702 703 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 704 { 705 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 706 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 707 return 0; 708 } 709 710 enum { 711 MLX5_VPORT_ACCESS_METHOD_MAD, 712 MLX5_VPORT_ACCESS_METHOD_HCA, 713 MLX5_VPORT_ACCESS_METHOD_NIC, 714 }; 715 716 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 717 { 718 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 719 return MLX5_VPORT_ACCESS_METHOD_MAD; 720 721 if (mlx5_ib_port_link_layer(ibdev, 1) == 722 IB_LINK_LAYER_ETHERNET) 723 return MLX5_VPORT_ACCESS_METHOD_NIC; 724 725 return MLX5_VPORT_ACCESS_METHOD_HCA; 726 } 727 728 static void get_atomic_caps(struct mlx5_ib_dev *dev, 729 u8 atomic_size_qp, 730 struct ib_device_attr *props) 731 { 732 u8 tmp; 733 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 734 u8 atomic_req_8B_endianness_mode = 735 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 736 737 /* Check if HW supports 8 bytes standard atomic operations and capable 738 * of host endianness respond 739 */ 740 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 741 if (((atomic_operations & tmp) == tmp) && 742 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 743 (atomic_req_8B_endianness_mode)) { 744 props->atomic_cap = IB_ATOMIC_HCA; 745 } else { 746 props->atomic_cap = IB_ATOMIC_NONE; 747 } 748 } 749 750 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 751 struct ib_device_attr *props) 752 { 753 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 754 755 get_atomic_caps(dev, atomic_size_qp, props); 756 } 757 758 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 759 __be64 *sys_image_guid) 760 { 761 struct mlx5_ib_dev *dev = to_mdev(ibdev); 762 struct mlx5_core_dev *mdev = dev->mdev; 763 u64 tmp; 764 int err; 765 766 switch (mlx5_get_vport_access_method(ibdev)) { 767 case MLX5_VPORT_ACCESS_METHOD_MAD: 768 return mlx5_query_mad_ifc_system_image_guid(ibdev, 769 sys_image_guid); 770 771 case MLX5_VPORT_ACCESS_METHOD_HCA: 772 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 773 break; 774 775 case MLX5_VPORT_ACCESS_METHOD_NIC: 776 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 777 break; 778 779 default: 780 return -EINVAL; 781 } 782 783 if (!err) 784 *sys_image_guid = cpu_to_be64(tmp); 785 786 return err; 787 788 } 789 790 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 791 u16 *max_pkeys) 792 { 793 struct mlx5_ib_dev *dev = to_mdev(ibdev); 794 struct mlx5_core_dev *mdev = dev->mdev; 795 796 switch (mlx5_get_vport_access_method(ibdev)) { 797 case MLX5_VPORT_ACCESS_METHOD_MAD: 798 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 799 800 case MLX5_VPORT_ACCESS_METHOD_HCA: 801 case MLX5_VPORT_ACCESS_METHOD_NIC: 802 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 803 pkey_table_size)); 804 return 0; 805 806 default: 807 return -EINVAL; 808 } 809 } 810 811 static int mlx5_query_vendor_id(struct ib_device *ibdev, 812 u32 *vendor_id) 813 { 814 struct mlx5_ib_dev *dev = to_mdev(ibdev); 815 816 switch (mlx5_get_vport_access_method(ibdev)) { 817 case MLX5_VPORT_ACCESS_METHOD_MAD: 818 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 819 820 case MLX5_VPORT_ACCESS_METHOD_HCA: 821 case MLX5_VPORT_ACCESS_METHOD_NIC: 822 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 823 824 default: 825 return -EINVAL; 826 } 827 } 828 829 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 830 __be64 *node_guid) 831 { 832 u64 tmp; 833 int err; 834 835 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 836 case MLX5_VPORT_ACCESS_METHOD_MAD: 837 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 838 839 case MLX5_VPORT_ACCESS_METHOD_HCA: 840 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 841 break; 842 843 case MLX5_VPORT_ACCESS_METHOD_NIC: 844 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 845 break; 846 847 default: 848 return -EINVAL; 849 } 850 851 if (!err) 852 *node_guid = cpu_to_be64(tmp); 853 854 return err; 855 } 856 857 struct mlx5_reg_node_desc { 858 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 859 }; 860 861 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 862 { 863 struct mlx5_reg_node_desc in; 864 865 if (mlx5_use_mad_ifc(dev)) 866 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 867 868 memset(&in, 0, sizeof(in)); 869 870 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 871 sizeof(struct mlx5_reg_node_desc), 872 MLX5_REG_NODE_DESC, 0, 0); 873 } 874 875 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 876 struct mlx5_ib_query_device_resp *resp) 877 { 878 struct mlx5_eswitch *esw = mdev->priv.eswitch; 879 u16 vport = mlx5_eswitch_manager_vport(mdev); 880 881 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 882 vport); 883 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 884 } 885 886 static int mlx5_ib_query_device(struct ib_device *ibdev, 887 struct ib_device_attr *props, 888 struct ib_udata *uhw) 889 { 890 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 891 struct mlx5_ib_dev *dev = to_mdev(ibdev); 892 struct mlx5_core_dev *mdev = dev->mdev; 893 int err = -ENOMEM; 894 int max_sq_desc; 895 int max_rq_sg; 896 int max_sq_sg; 897 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 898 bool raw_support = !mlx5_core_mp_enabled(mdev); 899 struct mlx5_ib_query_device_resp resp = {}; 900 size_t resp_len; 901 u64 max_tso; 902 903 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 904 if (uhw_outlen && uhw_outlen < resp_len) 905 return -EINVAL; 906 907 resp.response_length = resp_len; 908 909 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 910 return -EINVAL; 911 912 memset(props, 0, sizeof(*props)); 913 err = mlx5_query_system_image_guid(ibdev, 914 &props->sys_image_guid); 915 if (err) 916 return err; 917 918 props->max_pkeys = dev->pkey_table_len; 919 920 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 921 if (err) 922 return err; 923 924 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 925 (fw_rev_min(dev->mdev) << 16) | 926 fw_rev_sub(dev->mdev); 927 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 928 IB_DEVICE_PORT_ACTIVE_EVENT | 929 IB_DEVICE_SYS_IMAGE_GUID | 930 IB_DEVICE_RC_RNR_NAK_GEN; 931 932 if (MLX5_CAP_GEN(mdev, pkv)) 933 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 934 if (MLX5_CAP_GEN(mdev, qkv)) 935 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 936 if (MLX5_CAP_GEN(mdev, apm)) 937 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 938 if (MLX5_CAP_GEN(mdev, xrc)) 939 props->device_cap_flags |= IB_DEVICE_XRC; 940 if (MLX5_CAP_GEN(mdev, imaicl)) { 941 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 942 IB_DEVICE_MEM_WINDOW_TYPE_2B; 943 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 944 /* We support 'Gappy' memory registration too */ 945 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 946 } 947 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 948 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 949 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 950 if (MLX5_CAP_GEN(mdev, sho)) { 951 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 952 /* At this stage no support for signature handover */ 953 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 954 IB_PROT_T10DIF_TYPE_2 | 955 IB_PROT_T10DIF_TYPE_3; 956 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 957 IB_GUARD_T10DIF_CSUM; 958 } 959 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 960 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 961 962 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 963 if (MLX5_CAP_ETH(mdev, csum_cap)) { 964 /* Legacy bit to support old userspace libraries */ 965 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 966 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 967 } 968 969 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 970 props->raw_packet_caps |= 971 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 972 973 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 974 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 975 if (max_tso) { 976 resp.tso_caps.max_tso = 1 << max_tso; 977 resp.tso_caps.supported_qpts |= 978 1 << IB_QPT_RAW_PACKET; 979 resp.response_length += sizeof(resp.tso_caps); 980 } 981 } 982 983 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 984 resp.rss_caps.rx_hash_function = 985 MLX5_RX_HASH_FUNC_TOEPLITZ; 986 resp.rss_caps.rx_hash_fields_mask = 987 MLX5_RX_HASH_SRC_IPV4 | 988 MLX5_RX_HASH_DST_IPV4 | 989 MLX5_RX_HASH_SRC_IPV6 | 990 MLX5_RX_HASH_DST_IPV6 | 991 MLX5_RX_HASH_SRC_PORT_TCP | 992 MLX5_RX_HASH_DST_PORT_TCP | 993 MLX5_RX_HASH_SRC_PORT_UDP | 994 MLX5_RX_HASH_DST_PORT_UDP | 995 MLX5_RX_HASH_INNER; 996 resp.response_length += sizeof(resp.rss_caps); 997 } 998 } else { 999 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1000 resp.response_length += sizeof(resp.tso_caps); 1001 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1002 resp.response_length += sizeof(resp.rss_caps); 1003 } 1004 1005 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1006 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1007 props->kernel_cap_flags |= IBK_UD_TSO; 1008 } 1009 1010 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1011 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1012 raw_support) 1013 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1014 1015 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1016 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1017 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1018 1019 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1020 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1021 raw_support) { 1022 /* Legacy bit to support old userspace libraries */ 1023 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1024 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1025 } 1026 1027 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1028 props->max_dm_size = 1029 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1030 } 1031 1032 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1033 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1034 1035 if (MLX5_CAP_GEN(mdev, end_pad)) 1036 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1037 1038 props->vendor_part_id = mdev->pdev->device; 1039 props->hw_ver = mdev->pdev->revision; 1040 1041 props->max_mr_size = ~0ull; 1042 props->page_size_cap = ~(min_page_size - 1); 1043 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1044 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1045 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1046 sizeof(struct mlx5_wqe_data_seg); 1047 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1048 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1049 sizeof(struct mlx5_wqe_raddr_seg)) / 1050 sizeof(struct mlx5_wqe_data_seg); 1051 props->max_send_sge = max_sq_sg; 1052 props->max_recv_sge = max_rq_sg; 1053 props->max_sge_rd = MLX5_MAX_SGE_RD; 1054 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1055 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1056 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1057 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1058 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1059 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1060 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1061 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1062 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1063 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1064 props->max_srq_sge = max_rq_sg - 1; 1065 props->max_fast_reg_page_list_len = 1066 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1067 props->max_pi_fast_reg_page_list_len = 1068 props->max_fast_reg_page_list_len / 2; 1069 props->max_sgl_rd = 1070 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1071 get_atomic_caps_qp(dev, props); 1072 props->masked_atomic_cap = IB_ATOMIC_NONE; 1073 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1074 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1075 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1076 props->max_mcast_grp; 1077 props->max_ah = INT_MAX; 1078 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1079 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1080 1081 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1082 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1083 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1084 props->odp_caps = dev->odp_caps; 1085 if (!uhw) { 1086 /* ODP for kernel QPs is not implemented for receive 1087 * WQEs and SRQ WQEs 1088 */ 1089 props->odp_caps.per_transport_caps.rc_odp_caps &= 1090 ~(IB_ODP_SUPPORT_READ | 1091 IB_ODP_SUPPORT_SRQ_RECV); 1092 props->odp_caps.per_transport_caps.uc_odp_caps &= 1093 ~(IB_ODP_SUPPORT_READ | 1094 IB_ODP_SUPPORT_SRQ_RECV); 1095 props->odp_caps.per_transport_caps.ud_odp_caps &= 1096 ~(IB_ODP_SUPPORT_READ | 1097 IB_ODP_SUPPORT_SRQ_RECV); 1098 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1099 ~(IB_ODP_SUPPORT_READ | 1100 IB_ODP_SUPPORT_SRQ_RECV); 1101 } 1102 } 1103 1104 if (mlx5_core_is_vf(mdev)) 1105 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1106 1107 if (mlx5_ib_port_link_layer(ibdev, 1) == 1108 IB_LINK_LAYER_ETHERNET && raw_support) { 1109 props->rss_caps.max_rwq_indirection_tables = 1110 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1111 props->rss_caps.max_rwq_indirection_table_size = 1112 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1113 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1114 props->max_wq_type_rq = 1115 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1116 } 1117 1118 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1119 props->tm_caps.max_num_tags = 1120 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1121 props->tm_caps.max_ops = 1122 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1123 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1124 } 1125 1126 if (MLX5_CAP_GEN(mdev, tag_matching) && 1127 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1128 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1129 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1130 } 1131 1132 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1133 props->cq_caps.max_cq_moderation_count = 1134 MLX5_MAX_CQ_COUNT; 1135 props->cq_caps.max_cq_moderation_period = 1136 MLX5_MAX_CQ_PERIOD; 1137 } 1138 1139 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1140 resp.response_length += sizeof(resp.cqe_comp_caps); 1141 1142 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1143 resp.cqe_comp_caps.max_num = 1144 MLX5_CAP_GEN(dev->mdev, 1145 cqe_compression_max_num); 1146 1147 resp.cqe_comp_caps.supported_format = 1148 MLX5_IB_CQE_RES_FORMAT_HASH | 1149 MLX5_IB_CQE_RES_FORMAT_CSUM; 1150 1151 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1152 resp.cqe_comp_caps.supported_format |= 1153 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1154 } 1155 } 1156 1157 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1158 raw_support) { 1159 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1160 MLX5_CAP_GEN(mdev, qos)) { 1161 resp.packet_pacing_caps.qp_rate_limit_max = 1162 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1163 resp.packet_pacing_caps.qp_rate_limit_min = 1164 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1165 resp.packet_pacing_caps.supported_qpts |= 1166 1 << IB_QPT_RAW_PACKET; 1167 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1168 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1169 resp.packet_pacing_caps.cap_flags |= 1170 MLX5_IB_PP_SUPPORT_BURST; 1171 } 1172 resp.response_length += sizeof(resp.packet_pacing_caps); 1173 } 1174 1175 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1176 uhw_outlen) { 1177 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1178 resp.mlx5_ib_support_multi_pkt_send_wqes = 1179 MLX5_IB_ALLOW_MPW; 1180 1181 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1182 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1183 MLX5_IB_SUPPORT_EMPW; 1184 1185 resp.response_length += 1186 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1187 } 1188 1189 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1190 resp.response_length += sizeof(resp.flags); 1191 1192 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1193 resp.flags |= 1194 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1195 1196 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1197 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1198 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1199 resp.flags |= 1200 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1201 1202 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1203 1204 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1205 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1206 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1207 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1208 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1209 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1210 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1211 } 1212 1213 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1214 resp.response_length += sizeof(resp.sw_parsing_caps); 1215 if (MLX5_CAP_ETH(mdev, swp)) { 1216 resp.sw_parsing_caps.sw_parsing_offloads |= 1217 MLX5_IB_SW_PARSING; 1218 1219 if (MLX5_CAP_ETH(mdev, swp_csum)) 1220 resp.sw_parsing_caps.sw_parsing_offloads |= 1221 MLX5_IB_SW_PARSING_CSUM; 1222 1223 if (MLX5_CAP_ETH(mdev, swp_lso)) 1224 resp.sw_parsing_caps.sw_parsing_offloads |= 1225 MLX5_IB_SW_PARSING_LSO; 1226 1227 if (resp.sw_parsing_caps.sw_parsing_offloads) 1228 resp.sw_parsing_caps.supported_qpts = 1229 BIT(IB_QPT_RAW_PACKET); 1230 } 1231 } 1232 1233 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1234 raw_support) { 1235 resp.response_length += sizeof(resp.striding_rq_caps); 1236 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1237 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1238 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1239 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1240 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1241 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1242 resp.striding_rq_caps 1243 .min_single_wqe_log_num_of_strides = 1244 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1245 else 1246 resp.striding_rq_caps 1247 .min_single_wqe_log_num_of_strides = 1248 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1249 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1250 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1251 resp.striding_rq_caps.supported_qpts = 1252 BIT(IB_QPT_RAW_PACKET); 1253 } 1254 } 1255 1256 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1257 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1258 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1259 resp.tunnel_offloads_caps |= 1260 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1261 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1262 resp.tunnel_offloads_caps |= 1263 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1264 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1265 resp.tunnel_offloads_caps |= 1266 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1267 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1268 resp.tunnel_offloads_caps |= 1269 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1270 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1271 resp.tunnel_offloads_caps |= 1272 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1273 } 1274 1275 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1276 resp.response_length += sizeof(resp.dci_streams_caps); 1277 1278 resp.dci_streams_caps.max_log_num_concurent = 1279 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1280 1281 resp.dci_streams_caps.max_log_num_errored = 1282 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1283 } 1284 1285 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1286 resp.response_length += sizeof(resp.reserved); 1287 1288 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1289 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1290 1291 resp.response_length += sizeof(resp.reg_c0); 1292 1293 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1294 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1295 fill_esw_mgr_reg_c0(mdev, &resp); 1296 } 1297 1298 if (uhw_outlen) { 1299 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1300 1301 if (err) 1302 return err; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1309 u8 *ib_width) 1310 { 1311 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1312 1313 if (active_width & MLX5_PTYS_WIDTH_1X) 1314 *ib_width = IB_WIDTH_1X; 1315 else if (active_width & MLX5_PTYS_WIDTH_2X) 1316 *ib_width = IB_WIDTH_2X; 1317 else if (active_width & MLX5_PTYS_WIDTH_4X) 1318 *ib_width = IB_WIDTH_4X; 1319 else if (active_width & MLX5_PTYS_WIDTH_8X) 1320 *ib_width = IB_WIDTH_8X; 1321 else if (active_width & MLX5_PTYS_WIDTH_12X) 1322 *ib_width = IB_WIDTH_12X; 1323 else { 1324 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1325 active_width); 1326 *ib_width = IB_WIDTH_4X; 1327 } 1328 1329 return; 1330 } 1331 1332 static int mlx5_mtu_to_ib_mtu(int mtu) 1333 { 1334 switch (mtu) { 1335 case 256: return 1; 1336 case 512: return 2; 1337 case 1024: return 3; 1338 case 2048: return 4; 1339 case 4096: return 5; 1340 default: 1341 pr_warn("invalid mtu\n"); 1342 return -1; 1343 } 1344 } 1345 1346 enum ib_max_vl_num { 1347 __IB_MAX_VL_0 = 1, 1348 __IB_MAX_VL_0_1 = 2, 1349 __IB_MAX_VL_0_3 = 3, 1350 __IB_MAX_VL_0_7 = 4, 1351 __IB_MAX_VL_0_14 = 5, 1352 }; 1353 1354 enum mlx5_vl_hw_cap { 1355 MLX5_VL_HW_0 = 1, 1356 MLX5_VL_HW_0_1 = 2, 1357 MLX5_VL_HW_0_2 = 3, 1358 MLX5_VL_HW_0_3 = 4, 1359 MLX5_VL_HW_0_4 = 5, 1360 MLX5_VL_HW_0_5 = 6, 1361 MLX5_VL_HW_0_6 = 7, 1362 MLX5_VL_HW_0_7 = 8, 1363 MLX5_VL_HW_0_14 = 15 1364 }; 1365 1366 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1367 u8 *max_vl_num) 1368 { 1369 switch (vl_hw_cap) { 1370 case MLX5_VL_HW_0: 1371 *max_vl_num = __IB_MAX_VL_0; 1372 break; 1373 case MLX5_VL_HW_0_1: 1374 *max_vl_num = __IB_MAX_VL_0_1; 1375 break; 1376 case MLX5_VL_HW_0_3: 1377 *max_vl_num = __IB_MAX_VL_0_3; 1378 break; 1379 case MLX5_VL_HW_0_7: 1380 *max_vl_num = __IB_MAX_VL_0_7; 1381 break; 1382 case MLX5_VL_HW_0_14: 1383 *max_vl_num = __IB_MAX_VL_0_14; 1384 break; 1385 1386 default: 1387 return -EINVAL; 1388 } 1389 1390 return 0; 1391 } 1392 1393 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1394 struct ib_port_attr *props) 1395 { 1396 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1397 struct mlx5_core_dev *mdev = dev->mdev; 1398 struct mlx5_hca_vport_context *rep; 1399 u8 vl_hw_cap, plane_index = 0; 1400 u16 max_mtu; 1401 u16 oper_mtu; 1402 int err; 1403 u16 ib_link_width_oper; 1404 1405 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1406 if (!rep) { 1407 err = -ENOMEM; 1408 goto out; 1409 } 1410 1411 /* props being zeroed by the caller, avoid zeroing it here */ 1412 1413 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1414 plane_index = port; 1415 port = smi_to_native_portnum(dev, port); 1416 } 1417 1418 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1419 if (err) 1420 goto out; 1421 1422 props->lid = rep->lid; 1423 props->lmc = rep->lmc; 1424 props->sm_lid = rep->sm_lid; 1425 props->sm_sl = rep->sm_sl; 1426 props->state = rep->vport_state; 1427 props->phys_state = rep->port_physical_state; 1428 1429 props->port_cap_flags = rep->cap_mask1; 1430 if (dev->num_plane) { 1431 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1432 props->port_cap_flags &= ~IB_PORT_SM; 1433 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1434 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1435 1436 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1437 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1438 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1439 props->bad_pkey_cntr = rep->pkey_violation_counter; 1440 props->qkey_viol_cntr = rep->qkey_violation_counter; 1441 props->subnet_timeout = rep->subnet_timeout; 1442 props->init_type_reply = rep->init_type_reply; 1443 1444 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1445 props->port_cap_flags2 = rep->cap_mask2; 1446 1447 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1448 &props->active_speed, port, plane_index); 1449 if (err) 1450 goto out; 1451 1452 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1453 1454 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1455 1456 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1457 1458 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1459 1460 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1461 1462 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1463 if (err) 1464 goto out; 1465 1466 err = translate_max_vl_num(ibdev, vl_hw_cap, 1467 &props->max_vl_num); 1468 out: 1469 kfree(rep); 1470 return err; 1471 } 1472 1473 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1474 struct ib_port_attr *props) 1475 { 1476 unsigned int count; 1477 int ret; 1478 1479 switch (mlx5_get_vport_access_method(ibdev)) { 1480 case MLX5_VPORT_ACCESS_METHOD_MAD: 1481 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1482 break; 1483 1484 case MLX5_VPORT_ACCESS_METHOD_HCA: 1485 ret = mlx5_query_hca_port(ibdev, port, props); 1486 break; 1487 1488 case MLX5_VPORT_ACCESS_METHOD_NIC: 1489 ret = mlx5_query_port_roce(ibdev, port, props); 1490 break; 1491 1492 default: 1493 ret = -EINVAL; 1494 } 1495 1496 if (!ret && props) { 1497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1498 struct mlx5_core_dev *mdev; 1499 bool put_mdev = true; 1500 1501 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1502 if (!mdev) { 1503 /* If the port isn't affiliated yet query the master. 1504 * The master and slave will have the same values. 1505 */ 1506 mdev = dev->mdev; 1507 port = 1; 1508 put_mdev = false; 1509 } 1510 count = mlx5_core_reserved_gids_count(mdev); 1511 if (put_mdev) 1512 mlx5_ib_put_native_port_mdev(dev, port); 1513 props->gid_tbl_len -= count; 1514 } 1515 return ret; 1516 } 1517 1518 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1519 struct ib_port_attr *props) 1520 { 1521 return mlx5_query_port_roce(ibdev, port, props); 1522 } 1523 1524 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1525 u16 *pkey) 1526 { 1527 /* Default special Pkey for representor device port as per the 1528 * IB specification 1.3 section 10.9.1.2. 1529 */ 1530 *pkey = 0xffff; 1531 return 0; 1532 } 1533 1534 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1535 union ib_gid *gid) 1536 { 1537 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1538 struct mlx5_core_dev *mdev = dev->mdev; 1539 1540 switch (mlx5_get_vport_access_method(ibdev)) { 1541 case MLX5_VPORT_ACCESS_METHOD_MAD: 1542 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1543 1544 case MLX5_VPORT_ACCESS_METHOD_HCA: 1545 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1546 1547 default: 1548 return -EINVAL; 1549 } 1550 1551 } 1552 1553 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1554 u16 index, u16 *pkey) 1555 { 1556 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1557 struct mlx5_core_dev *mdev; 1558 bool put_mdev = true; 1559 u32 mdev_port_num; 1560 int err; 1561 1562 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1563 if (!mdev) { 1564 /* The port isn't affiliated yet, get the PKey from the master 1565 * port. For RoCE the PKey tables will be the same. 1566 */ 1567 put_mdev = false; 1568 mdev = dev->mdev; 1569 mdev_port_num = 1; 1570 } 1571 1572 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1573 index, pkey); 1574 if (put_mdev) 1575 mlx5_ib_put_native_port_mdev(dev, port); 1576 1577 return err; 1578 } 1579 1580 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1581 u16 *pkey) 1582 { 1583 switch (mlx5_get_vport_access_method(ibdev)) { 1584 case MLX5_VPORT_ACCESS_METHOD_MAD: 1585 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1586 1587 case MLX5_VPORT_ACCESS_METHOD_HCA: 1588 case MLX5_VPORT_ACCESS_METHOD_NIC: 1589 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1590 default: 1591 return -EINVAL; 1592 } 1593 } 1594 1595 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1596 struct ib_device_modify *props) 1597 { 1598 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1599 struct mlx5_reg_node_desc in; 1600 struct mlx5_reg_node_desc out; 1601 int err; 1602 1603 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1604 return -EOPNOTSUPP; 1605 1606 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1607 return 0; 1608 1609 /* 1610 * If possible, pass node desc to FW, so it can generate 1611 * a 144 trap. If cmd fails, just ignore. 1612 */ 1613 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1614 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1615 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1616 if (err) 1617 return err; 1618 1619 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1620 1621 return err; 1622 } 1623 1624 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1625 u32 value) 1626 { 1627 struct mlx5_hca_vport_context ctx = {}; 1628 struct mlx5_core_dev *mdev; 1629 u32 mdev_port_num; 1630 int err; 1631 1632 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1633 if (!mdev) 1634 return -ENODEV; 1635 1636 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1637 if (err) 1638 goto out; 1639 1640 if (~ctx.cap_mask1_perm & mask) { 1641 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1642 mask, ctx.cap_mask1_perm); 1643 err = -EINVAL; 1644 goto out; 1645 } 1646 1647 ctx.cap_mask1 = value; 1648 ctx.cap_mask1_perm = mask; 1649 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1650 0, &ctx); 1651 1652 out: 1653 mlx5_ib_put_native_port_mdev(dev, port_num); 1654 1655 return err; 1656 } 1657 1658 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1659 struct ib_port_modify *props) 1660 { 1661 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1662 struct ib_port_attr attr; 1663 u32 tmp; 1664 int err; 1665 u32 change_mask; 1666 u32 value; 1667 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1668 IB_LINK_LAYER_INFINIBAND); 1669 1670 /* CM layer calls ib_modify_port() regardless of the link layer. For 1671 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1672 */ 1673 if (!is_ib) 1674 return 0; 1675 1676 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1677 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1678 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1679 return set_port_caps_atomic(dev, port, change_mask, value); 1680 } 1681 1682 mutex_lock(&dev->cap_mask_mutex); 1683 1684 err = ib_query_port(ibdev, port, &attr); 1685 if (err) 1686 goto out; 1687 1688 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1689 ~props->clr_port_cap_mask; 1690 1691 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1692 1693 out: 1694 mutex_unlock(&dev->cap_mask_mutex); 1695 return err; 1696 } 1697 1698 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1699 { 1700 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1701 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1702 } 1703 1704 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1705 { 1706 /* Large page with non 4k uar support might limit the dynamic size */ 1707 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1708 return MLX5_MIN_DYN_BFREGS; 1709 1710 return MLX5_MAX_DYN_BFREGS; 1711 } 1712 1713 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1714 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1715 struct mlx5_bfreg_info *bfregi) 1716 { 1717 int uars_per_sys_page; 1718 int bfregs_per_sys_page; 1719 int ref_bfregs = req->total_num_bfregs; 1720 1721 if (req->total_num_bfregs == 0) 1722 return -EINVAL; 1723 1724 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1725 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1726 1727 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1728 return -ENOMEM; 1729 1730 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1731 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1732 /* This holds the required static allocation asked by the user */ 1733 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1734 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1735 return -EINVAL; 1736 1737 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1738 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1739 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1740 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1741 1742 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1743 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1744 lib_uar_4k ? "yes" : "no", ref_bfregs, 1745 req->total_num_bfregs, bfregi->total_num_bfregs, 1746 bfregi->num_sys_pages); 1747 1748 return 0; 1749 } 1750 1751 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1752 { 1753 struct mlx5_bfreg_info *bfregi; 1754 int err; 1755 int i; 1756 1757 bfregi = &context->bfregi; 1758 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1759 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1760 context->devx_uid); 1761 if (err) 1762 goto error; 1763 1764 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1765 } 1766 1767 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1768 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1769 1770 return 0; 1771 1772 error: 1773 for (--i; i >= 0; i--) 1774 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1775 context->devx_uid)) 1776 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1777 1778 return err; 1779 } 1780 1781 static void deallocate_uars(struct mlx5_ib_dev *dev, 1782 struct mlx5_ib_ucontext *context) 1783 { 1784 struct mlx5_bfreg_info *bfregi; 1785 int i; 1786 1787 bfregi = &context->bfregi; 1788 for (i = 0; i < bfregi->num_sys_pages; i++) 1789 if (i < bfregi->num_static_sys_pages || 1790 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1791 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1792 context->devx_uid); 1793 } 1794 1795 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1796 { 1797 int err = 0; 1798 1799 mutex_lock(&dev->lb.mutex); 1800 if (td) 1801 dev->lb.user_td++; 1802 if (qp) 1803 dev->lb.qps++; 1804 1805 if (dev->lb.user_td == 2 || 1806 dev->lb.qps == 1) { 1807 if (!dev->lb.enabled) { 1808 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1809 dev->lb.enabled = true; 1810 } 1811 } 1812 1813 mutex_unlock(&dev->lb.mutex); 1814 1815 return err; 1816 } 1817 1818 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1819 { 1820 mutex_lock(&dev->lb.mutex); 1821 if (td) 1822 dev->lb.user_td--; 1823 if (qp) 1824 dev->lb.qps--; 1825 1826 if (dev->lb.user_td == 1 && 1827 dev->lb.qps == 0) { 1828 if (dev->lb.enabled) { 1829 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1830 dev->lb.enabled = false; 1831 } 1832 } 1833 1834 mutex_unlock(&dev->lb.mutex); 1835 } 1836 1837 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1838 u16 uid) 1839 { 1840 int err; 1841 1842 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1843 return 0; 1844 1845 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1846 if (err) 1847 return err; 1848 1849 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1850 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1851 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1852 return err; 1853 1854 return mlx5_ib_enable_lb(dev, true, false); 1855 } 1856 1857 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1858 u16 uid) 1859 { 1860 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1861 return; 1862 1863 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1864 1865 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1866 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1867 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1868 return; 1869 1870 mlx5_ib_disable_lb(dev, true, false); 1871 } 1872 1873 static int set_ucontext_resp(struct ib_ucontext *uctx, 1874 struct mlx5_ib_alloc_ucontext_resp *resp) 1875 { 1876 struct ib_device *ibdev = uctx->device; 1877 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1878 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1879 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1880 1881 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1882 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1883 resp->comp_mask |= 1884 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1885 } 1886 1887 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1888 if (mlx5_wc_support_get(dev->mdev)) 1889 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1890 log_bf_reg_size); 1891 resp->cache_line_size = cache_line_size(); 1892 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1893 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1894 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1895 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1896 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1897 resp->cqe_version = context->cqe_version; 1898 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1899 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1900 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1901 MLX5_CAP_GEN(dev->mdev, 1902 num_of_uars_per_page) : 1; 1903 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1904 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1905 resp->num_ports = dev->num_ports; 1906 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1907 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1908 1909 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1910 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1911 resp->eth_min_inline++; 1912 } 1913 1914 if (dev->mdev->clock_info) 1915 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1916 1917 /* 1918 * We don't want to expose information from the PCI bar that is located 1919 * after 4096 bytes, so if the arch only supports larger pages, let's 1920 * pretend we don't support reading the HCA's core clock. This is also 1921 * forced by mmap function. 1922 */ 1923 if (PAGE_SIZE <= 4096) { 1924 resp->comp_mask |= 1925 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1926 resp->hca_core_clock_offset = 1927 offsetof(struct mlx5_init_seg, 1928 internal_timer_h) % PAGE_SIZE; 1929 } 1930 1931 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1932 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1933 1934 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1935 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1936 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1937 resp->comp_mask |= 1938 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1939 1940 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1941 1942 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1943 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1944 1945 resp->comp_mask |= 1946 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1947 1948 return 0; 1949 } 1950 1951 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 1952 { 1953 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 1954 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 1955 } 1956 1957 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1958 struct ib_udata *udata) 1959 { 1960 struct ib_device *ibdev = uctx->device; 1961 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1962 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1963 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1964 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1965 struct mlx5_bfreg_info *bfregi; 1966 int ver; 1967 int err; 1968 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1969 max_cqe_version); 1970 bool lib_uar_4k; 1971 bool lib_uar_dyn; 1972 1973 if (!dev->ib_active) 1974 return -EAGAIN; 1975 1976 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1977 ver = 0; 1978 else if (udata->inlen >= min_req_v2) 1979 ver = 2; 1980 else 1981 return -EINVAL; 1982 1983 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1984 if (err) 1985 return err; 1986 1987 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1988 return -EOPNOTSUPP; 1989 1990 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1991 return -EOPNOTSUPP; 1992 1993 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1994 MLX5_NON_FP_BFREGS_PER_UAR); 1995 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1996 return -EINVAL; 1997 1998 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1999 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2000 if (err < 0) 2001 goto out_ctx; 2002 context->devx_uid = err; 2003 2004 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2005 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2006 context->devx_uid); 2007 if (err) 2008 goto out_devx; 2009 } 2010 } 2011 2012 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2013 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2014 bfregi = &context->bfregi; 2015 2016 if (lib_uar_dyn) { 2017 bfregi->lib_uar_dyn = lib_uar_dyn; 2018 goto uar_done; 2019 } 2020 2021 /* updates req->total_num_bfregs */ 2022 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2023 if (err) 2024 goto out_ucap; 2025 2026 mutex_init(&bfregi->lock); 2027 bfregi->lib_uar_4k = lib_uar_4k; 2028 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2029 GFP_KERNEL); 2030 if (!bfregi->count) { 2031 err = -ENOMEM; 2032 goto out_ucap; 2033 } 2034 2035 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2036 sizeof(*bfregi->sys_pages), 2037 GFP_KERNEL); 2038 if (!bfregi->sys_pages) { 2039 err = -ENOMEM; 2040 goto out_count; 2041 } 2042 2043 err = allocate_uars(dev, context); 2044 if (err) 2045 goto out_sys_pages; 2046 2047 uar_done: 2048 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2049 context->devx_uid); 2050 if (err) 2051 goto out_uars; 2052 2053 INIT_LIST_HEAD(&context->db_page_list); 2054 mutex_init(&context->db_page_mutex); 2055 2056 context->cqe_version = min_t(__u8, 2057 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2058 req.max_cqe_version); 2059 2060 err = set_ucontext_resp(uctx, &resp); 2061 if (err) 2062 goto out_mdev; 2063 2064 resp.response_length = min(udata->outlen, sizeof(resp)); 2065 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2066 if (err) 2067 goto out_mdev; 2068 2069 bfregi->ver = ver; 2070 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2071 context->lib_caps = req.lib_caps; 2072 print_lib_caps(dev, context->lib_caps); 2073 2074 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2075 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2076 2077 atomic_set(&context->tx_port_affinity, 2078 atomic_add_return( 2079 1, &dev->port[port].roce.tx_port_affinity)); 2080 } 2081 2082 return 0; 2083 2084 out_mdev: 2085 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2086 2087 out_uars: 2088 deallocate_uars(dev, context); 2089 2090 out_sys_pages: 2091 kfree(bfregi->sys_pages); 2092 2093 out_count: 2094 kfree(bfregi->count); 2095 2096 out_ucap: 2097 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2098 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2099 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2100 2101 out_devx: 2102 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2103 mlx5_ib_devx_destroy(dev, context->devx_uid); 2104 2105 out_ctx: 2106 return err; 2107 } 2108 2109 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2110 struct uverbs_attr_bundle *attrs) 2111 { 2112 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2113 int ret; 2114 2115 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2116 if (ret) 2117 return ret; 2118 2119 uctx_resp.response_length = 2120 min_t(size_t, 2121 uverbs_attr_get_len(attrs, 2122 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2123 sizeof(uctx_resp)); 2124 2125 ret = uverbs_copy_to_struct_or_zero(attrs, 2126 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2127 &uctx_resp, 2128 sizeof(uctx_resp)); 2129 return ret; 2130 } 2131 2132 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2133 { 2134 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2135 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2136 struct mlx5_bfreg_info *bfregi; 2137 2138 bfregi = &context->bfregi; 2139 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2140 2141 deallocate_uars(dev, context); 2142 kfree(bfregi->sys_pages); 2143 kfree(bfregi->count); 2144 2145 if (context->devx_uid) { 2146 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2147 mlx5_cmd_remove_privileged_uid(dev->mdev, 2148 context->devx_uid); 2149 mlx5_ib_devx_destroy(dev, context->devx_uid); 2150 } 2151 } 2152 2153 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2154 int uar_idx) 2155 { 2156 int fw_uars_per_page; 2157 2158 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2159 2160 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2161 } 2162 2163 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2164 int uar_idx) 2165 { 2166 unsigned int fw_uars_per_page; 2167 2168 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2169 MLX5_UARS_IN_PAGE : 1; 2170 2171 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2172 } 2173 2174 static int get_command(unsigned long offset) 2175 { 2176 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2177 } 2178 2179 static int get_arg(unsigned long offset) 2180 { 2181 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2182 } 2183 2184 static int get_index(unsigned long offset) 2185 { 2186 return get_arg(offset); 2187 } 2188 2189 /* Index resides in an extra byte to enable larger values than 255 */ 2190 static int get_extended_index(unsigned long offset) 2191 { 2192 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2193 } 2194 2195 2196 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2197 { 2198 } 2199 2200 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2201 { 2202 switch (cmd) { 2203 case MLX5_IB_MMAP_WC_PAGE: 2204 return "WC"; 2205 case MLX5_IB_MMAP_REGULAR_PAGE: 2206 return "best effort WC"; 2207 case MLX5_IB_MMAP_NC_PAGE: 2208 return "NC"; 2209 case MLX5_IB_MMAP_DEVICE_MEM: 2210 return "Device Memory"; 2211 default: 2212 return "Unknown"; 2213 } 2214 } 2215 2216 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2217 struct vm_area_struct *vma, 2218 struct mlx5_ib_ucontext *context) 2219 { 2220 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2221 !(vma->vm_flags & VM_SHARED)) 2222 return -EINVAL; 2223 2224 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2225 return -EOPNOTSUPP; 2226 2227 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2228 return -EPERM; 2229 vm_flags_clear(vma, VM_MAYWRITE); 2230 2231 if (!dev->mdev->clock_info) 2232 return -EOPNOTSUPP; 2233 2234 return vm_insert_page(vma, vma->vm_start, 2235 virt_to_page(dev->mdev->clock_info)); 2236 } 2237 2238 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2239 { 2240 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2241 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2242 struct mlx5_var_table *var_table = &dev->var_table; 2243 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2244 2245 switch (mentry->mmap_flag) { 2246 case MLX5_IB_MMAP_TYPE_MEMIC: 2247 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2248 mlx5_ib_dm_mmap_free(dev, mentry); 2249 break; 2250 case MLX5_IB_MMAP_TYPE_VAR: 2251 mutex_lock(&var_table->bitmap_lock); 2252 clear_bit(mentry->page_idx, var_table->bitmap); 2253 mutex_unlock(&var_table->bitmap_lock); 2254 kfree(mentry); 2255 break; 2256 case MLX5_IB_MMAP_TYPE_UAR_WC: 2257 case MLX5_IB_MMAP_TYPE_UAR_NC: 2258 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2259 context->devx_uid); 2260 kfree(mentry); 2261 break; 2262 default: 2263 WARN_ON(true); 2264 } 2265 } 2266 2267 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2268 struct vm_area_struct *vma, 2269 struct mlx5_ib_ucontext *context) 2270 { 2271 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2272 int err; 2273 unsigned long idx; 2274 phys_addr_t pfn; 2275 pgprot_t prot; 2276 u32 bfreg_dyn_idx = 0; 2277 u32 uar_index; 2278 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2279 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2280 bfregi->num_static_sys_pages; 2281 2282 if (bfregi->lib_uar_dyn) 2283 return -EINVAL; 2284 2285 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2286 return -EINVAL; 2287 2288 if (dyn_uar) 2289 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2290 else 2291 idx = get_index(vma->vm_pgoff); 2292 2293 if (idx >= max_valid_idx) { 2294 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2295 idx, max_valid_idx); 2296 return -EINVAL; 2297 } 2298 2299 switch (cmd) { 2300 case MLX5_IB_MMAP_WC_PAGE: 2301 case MLX5_IB_MMAP_ALLOC_WC: 2302 case MLX5_IB_MMAP_REGULAR_PAGE: 2303 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2304 prot = pgprot_writecombine(vma->vm_page_prot); 2305 break; 2306 case MLX5_IB_MMAP_NC_PAGE: 2307 prot = pgprot_noncached(vma->vm_page_prot); 2308 break; 2309 default: 2310 return -EINVAL; 2311 } 2312 2313 if (dyn_uar) { 2314 int uars_per_page; 2315 2316 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2317 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2318 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2319 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2320 bfreg_dyn_idx, bfregi->total_num_bfregs); 2321 return -EINVAL; 2322 } 2323 2324 mutex_lock(&bfregi->lock); 2325 /* Fail if uar already allocated, first bfreg index of each 2326 * page holds its count. 2327 */ 2328 if (bfregi->count[bfreg_dyn_idx]) { 2329 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2330 mutex_unlock(&bfregi->lock); 2331 return -EINVAL; 2332 } 2333 2334 bfregi->count[bfreg_dyn_idx]++; 2335 mutex_unlock(&bfregi->lock); 2336 2337 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2338 context->devx_uid); 2339 if (err) { 2340 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2341 goto free_bfreg; 2342 } 2343 } else { 2344 uar_index = bfregi->sys_pages[idx]; 2345 } 2346 2347 pfn = uar_index2pfn(dev, uar_index); 2348 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2349 2350 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2351 prot, NULL); 2352 if (err) { 2353 mlx5_ib_err(dev, 2354 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2355 err, mmap_cmd2str(cmd)); 2356 goto err; 2357 } 2358 2359 if (dyn_uar) 2360 bfregi->sys_pages[idx] = uar_index; 2361 return 0; 2362 2363 err: 2364 if (!dyn_uar) 2365 return err; 2366 2367 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2368 2369 free_bfreg: 2370 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2371 2372 return err; 2373 } 2374 2375 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2376 { 2377 unsigned long idx; 2378 u8 command; 2379 2380 command = get_command(vma->vm_pgoff); 2381 idx = get_extended_index(vma->vm_pgoff); 2382 2383 return (command << 16 | idx); 2384 } 2385 2386 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2387 struct vm_area_struct *vma, 2388 struct ib_ucontext *ucontext) 2389 { 2390 struct mlx5_user_mmap_entry *mentry; 2391 struct rdma_user_mmap_entry *entry; 2392 unsigned long pgoff; 2393 pgprot_t prot; 2394 phys_addr_t pfn; 2395 int ret; 2396 2397 pgoff = mlx5_vma_to_pgoff(vma); 2398 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2399 if (!entry) 2400 return -EINVAL; 2401 2402 mentry = to_mmmap(entry); 2403 pfn = (mentry->address >> PAGE_SHIFT); 2404 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2405 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2406 prot = pgprot_noncached(vma->vm_page_prot); 2407 else 2408 prot = pgprot_writecombine(vma->vm_page_prot); 2409 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2410 entry->npages * PAGE_SIZE, 2411 prot, 2412 entry); 2413 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2414 return ret; 2415 } 2416 2417 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2418 { 2419 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2420 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2421 2422 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2423 (index & 0xFF)) << PAGE_SHIFT; 2424 } 2425 2426 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2427 { 2428 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2429 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2430 unsigned long command; 2431 phys_addr_t pfn; 2432 2433 command = get_command(vma->vm_pgoff); 2434 switch (command) { 2435 case MLX5_IB_MMAP_WC_PAGE: 2436 case MLX5_IB_MMAP_ALLOC_WC: 2437 if (!mlx5_wc_support_get(dev->mdev)) 2438 return -EPERM; 2439 fallthrough; 2440 case MLX5_IB_MMAP_NC_PAGE: 2441 case MLX5_IB_MMAP_REGULAR_PAGE: 2442 return uar_mmap(dev, command, vma, context); 2443 2444 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2445 return -ENOSYS; 2446 2447 case MLX5_IB_MMAP_CORE_CLOCK: 2448 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2449 return -EINVAL; 2450 2451 if (vma->vm_flags & VM_WRITE) 2452 return -EPERM; 2453 vm_flags_clear(vma, VM_MAYWRITE); 2454 2455 /* Don't expose to user-space information it shouldn't have */ 2456 if (PAGE_SIZE > 4096) 2457 return -EOPNOTSUPP; 2458 2459 pfn = (dev->mdev->iseg_base + 2460 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2461 PAGE_SHIFT; 2462 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2463 PAGE_SIZE, 2464 pgprot_noncached(vma->vm_page_prot), 2465 NULL); 2466 case MLX5_IB_MMAP_CLOCK_INFO: 2467 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2468 2469 default: 2470 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2477 { 2478 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2479 struct ib_device *ibdev = ibpd->device; 2480 struct mlx5_ib_alloc_pd_resp resp; 2481 int err; 2482 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2483 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2484 u16 uid = 0; 2485 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2486 udata, struct mlx5_ib_ucontext, ibucontext); 2487 2488 uid = context ? context->devx_uid : 0; 2489 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2490 MLX5_SET(alloc_pd_in, in, uid, uid); 2491 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2492 if (err) 2493 return err; 2494 2495 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2496 pd->uid = uid; 2497 if (udata) { 2498 resp.pdn = pd->pdn; 2499 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2500 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2501 return -EFAULT; 2502 } 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2509 { 2510 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2511 struct mlx5_ib_pd *mpd = to_mpd(pd); 2512 2513 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2514 } 2515 2516 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2517 { 2518 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2519 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2520 int err; 2521 u16 uid; 2522 2523 uid = ibqp->pd ? 2524 to_mpd(ibqp->pd)->uid : 0; 2525 2526 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2527 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2528 return -EOPNOTSUPP; 2529 } 2530 2531 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2532 if (err) 2533 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2534 ibqp->qp_num, gid->raw); 2535 2536 return err; 2537 } 2538 2539 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2540 { 2541 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2542 int err; 2543 u16 uid; 2544 2545 uid = ibqp->pd ? 2546 to_mpd(ibqp->pd)->uid : 0; 2547 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2548 if (err) 2549 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2550 ibqp->qp_num, gid->raw); 2551 2552 return err; 2553 } 2554 2555 static int init_node_data(struct mlx5_ib_dev *dev) 2556 { 2557 int err; 2558 2559 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2560 if (err) 2561 return err; 2562 2563 dev->mdev->rev_id = dev->mdev->pdev->revision; 2564 2565 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2566 } 2567 2568 static ssize_t fw_pages_show(struct device *device, 2569 struct device_attribute *attr, char *buf) 2570 { 2571 struct mlx5_ib_dev *dev = 2572 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2573 2574 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2575 } 2576 static DEVICE_ATTR_RO(fw_pages); 2577 2578 static ssize_t reg_pages_show(struct device *device, 2579 struct device_attribute *attr, char *buf) 2580 { 2581 struct mlx5_ib_dev *dev = 2582 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2583 2584 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2585 } 2586 static DEVICE_ATTR_RO(reg_pages); 2587 2588 static ssize_t hca_type_show(struct device *device, 2589 struct device_attribute *attr, char *buf) 2590 { 2591 struct mlx5_ib_dev *dev = 2592 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2593 2594 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2595 } 2596 static DEVICE_ATTR_RO(hca_type); 2597 2598 static ssize_t hw_rev_show(struct device *device, 2599 struct device_attribute *attr, char *buf) 2600 { 2601 struct mlx5_ib_dev *dev = 2602 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2603 2604 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2605 } 2606 static DEVICE_ATTR_RO(hw_rev); 2607 2608 static ssize_t board_id_show(struct device *device, 2609 struct device_attribute *attr, char *buf) 2610 { 2611 struct mlx5_ib_dev *dev = 2612 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2613 2614 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2615 dev->mdev->board_id); 2616 } 2617 static DEVICE_ATTR_RO(board_id); 2618 2619 static struct attribute *mlx5_class_attributes[] = { 2620 &dev_attr_hw_rev.attr, 2621 &dev_attr_hca_type.attr, 2622 &dev_attr_board_id.attr, 2623 &dev_attr_fw_pages.attr, 2624 &dev_attr_reg_pages.attr, 2625 NULL, 2626 }; 2627 2628 static const struct attribute_group mlx5_attr_group = { 2629 .attrs = mlx5_class_attributes, 2630 }; 2631 2632 static void pkey_change_handler(struct work_struct *work) 2633 { 2634 struct mlx5_ib_port_resources *ports = 2635 container_of(work, struct mlx5_ib_port_resources, 2636 pkey_change_work); 2637 2638 if (!ports->gsi) 2639 /* 2640 * We got this event before device was fully configured 2641 * and MAD registration code wasn't called/finished yet. 2642 */ 2643 return; 2644 2645 mlx5_ib_gsi_pkey_change(ports->gsi); 2646 } 2647 2648 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2649 { 2650 struct mlx5_ib_qp *mqp; 2651 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2652 struct mlx5_core_cq *mcq; 2653 struct list_head cq_armed_list; 2654 unsigned long flags_qp; 2655 unsigned long flags_cq; 2656 unsigned long flags; 2657 2658 INIT_LIST_HEAD(&cq_armed_list); 2659 2660 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2661 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2662 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2663 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2664 if (mqp->sq.tail != mqp->sq.head) { 2665 send_mcq = to_mcq(mqp->ibqp.send_cq); 2666 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2667 if (send_mcq->mcq.comp && 2668 mqp->ibqp.send_cq->comp_handler) { 2669 if (!send_mcq->mcq.reset_notify_added) { 2670 send_mcq->mcq.reset_notify_added = 1; 2671 list_add_tail(&send_mcq->mcq.reset_notify, 2672 &cq_armed_list); 2673 } 2674 } 2675 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2676 } 2677 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2678 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2679 /* no handling is needed for SRQ */ 2680 if (!mqp->ibqp.srq) { 2681 if (mqp->rq.tail != mqp->rq.head) { 2682 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2683 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2684 if (recv_mcq->mcq.comp && 2685 mqp->ibqp.recv_cq->comp_handler) { 2686 if (!recv_mcq->mcq.reset_notify_added) { 2687 recv_mcq->mcq.reset_notify_added = 1; 2688 list_add_tail(&recv_mcq->mcq.reset_notify, 2689 &cq_armed_list); 2690 } 2691 } 2692 spin_unlock_irqrestore(&recv_mcq->lock, 2693 flags_cq); 2694 } 2695 } 2696 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2697 } 2698 /*At that point all inflight post send were put to be executed as of we 2699 * lock/unlock above locks Now need to arm all involved CQs. 2700 */ 2701 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2702 mcq->comp(mcq, NULL); 2703 } 2704 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2705 } 2706 2707 static void delay_drop_handler(struct work_struct *work) 2708 { 2709 int err; 2710 struct mlx5_ib_delay_drop *delay_drop = 2711 container_of(work, struct mlx5_ib_delay_drop, 2712 delay_drop_work); 2713 2714 atomic_inc(&delay_drop->events_cnt); 2715 2716 mutex_lock(&delay_drop->lock); 2717 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2718 if (err) { 2719 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2720 delay_drop->timeout); 2721 delay_drop->activate = false; 2722 } 2723 mutex_unlock(&delay_drop->lock); 2724 } 2725 2726 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2727 struct ib_event *ibev) 2728 { 2729 u32 port = (eqe->data.port.port >> 4) & 0xf; 2730 2731 switch (eqe->sub_type) { 2732 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2733 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2734 IB_LINK_LAYER_ETHERNET) 2735 schedule_work(&ibdev->delay_drop.delay_drop_work); 2736 break; 2737 default: /* do nothing */ 2738 return; 2739 } 2740 } 2741 2742 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2743 struct ib_event *ibev) 2744 { 2745 u32 port = (eqe->data.port.port >> 4) & 0xf; 2746 2747 ibev->element.port_num = port; 2748 2749 switch (eqe->sub_type) { 2750 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2751 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2752 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2753 /* In RoCE, port up/down events are handled in 2754 * mlx5_netdev_event(). 2755 */ 2756 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2757 IB_LINK_LAYER_ETHERNET) 2758 return -EINVAL; 2759 2760 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2761 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2762 break; 2763 2764 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2765 ibev->event = IB_EVENT_LID_CHANGE; 2766 break; 2767 2768 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2769 ibev->event = IB_EVENT_PKEY_CHANGE; 2770 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2771 break; 2772 2773 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2774 ibev->event = IB_EVENT_GID_CHANGE; 2775 break; 2776 2777 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2778 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2779 break; 2780 default: 2781 return -EINVAL; 2782 } 2783 2784 return 0; 2785 } 2786 2787 static void mlx5_ib_handle_event(struct work_struct *_work) 2788 { 2789 struct mlx5_ib_event_work *work = 2790 container_of(_work, struct mlx5_ib_event_work, work); 2791 struct mlx5_ib_dev *ibdev; 2792 struct ib_event ibev; 2793 bool fatal = false; 2794 2795 if (work->is_slave) { 2796 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2797 if (!ibdev) 2798 goto out; 2799 } else { 2800 ibdev = work->dev; 2801 } 2802 2803 switch (work->event) { 2804 case MLX5_DEV_EVENT_SYS_ERROR: 2805 ibev.event = IB_EVENT_DEVICE_FATAL; 2806 mlx5_ib_handle_internal_error(ibdev); 2807 ibev.element.port_num = (u8)(unsigned long)work->param; 2808 fatal = true; 2809 break; 2810 case MLX5_EVENT_TYPE_PORT_CHANGE: 2811 if (handle_port_change(ibdev, work->param, &ibev)) 2812 goto out; 2813 break; 2814 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2815 handle_general_event(ibdev, work->param, &ibev); 2816 fallthrough; 2817 default: 2818 goto out; 2819 } 2820 2821 ibev.device = &ibdev->ib_dev; 2822 2823 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2824 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2825 goto out; 2826 } 2827 2828 if (ibdev->ib_active) 2829 ib_dispatch_event(&ibev); 2830 2831 if (fatal) 2832 ibdev->ib_active = false; 2833 out: 2834 kfree(work); 2835 } 2836 2837 static int mlx5_ib_event(struct notifier_block *nb, 2838 unsigned long event, void *param) 2839 { 2840 struct mlx5_ib_event_work *work; 2841 2842 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2843 if (!work) 2844 return NOTIFY_DONE; 2845 2846 INIT_WORK(&work->work, mlx5_ib_handle_event); 2847 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2848 work->is_slave = false; 2849 work->param = param; 2850 work->event = event; 2851 2852 queue_work(mlx5_ib_event_wq, &work->work); 2853 2854 return NOTIFY_OK; 2855 } 2856 2857 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2858 unsigned long event, void *param) 2859 { 2860 struct mlx5_ib_event_work *work; 2861 2862 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2863 if (!work) 2864 return NOTIFY_DONE; 2865 2866 INIT_WORK(&work->work, mlx5_ib_handle_event); 2867 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2868 work->is_slave = true; 2869 work->param = param; 2870 work->event = event; 2871 queue_work(mlx5_ib_event_wq, &work->work); 2872 2873 return NOTIFY_OK; 2874 } 2875 2876 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 2877 { 2878 struct mlx5_hca_vport_context vport_ctx; 2879 int err; 2880 2881 *num_plane = 0; 2882 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 2883 return 0; 2884 2885 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 2886 if (err) 2887 return err; 2888 2889 *num_plane = vport_ctx.num_plane; 2890 return 0; 2891 } 2892 2893 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2894 { 2895 struct mlx5_hca_vport_context vport_ctx; 2896 int err; 2897 int port; 2898 2899 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2900 return 0; 2901 2902 for (port = 1; port <= dev->num_ports; port++) { 2903 if (dev->num_plane) { 2904 dev->port_caps[port - 1].has_smi = false; 2905 continue; 2906 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 2907 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 2908 dev->port_caps[port - 1].has_smi = true; 2909 continue; 2910 } 2911 2912 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2913 &vport_ctx); 2914 if (err) { 2915 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2916 port, err); 2917 return err; 2918 } 2919 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2920 } 2921 2922 return 0; 2923 } 2924 2925 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2926 { 2927 unsigned int port; 2928 2929 rdma_for_each_port (&dev->ib_dev, port) 2930 mlx5_query_ext_port_caps(dev, port); 2931 } 2932 2933 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2934 { 2935 switch (umr_fence_cap) { 2936 case MLX5_CAP_UMR_FENCE_NONE: 2937 return MLX5_FENCE_MODE_NONE; 2938 case MLX5_CAP_UMR_FENCE_SMALL: 2939 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2940 default: 2941 return MLX5_FENCE_MODE_STRONG_ORDERING; 2942 } 2943 } 2944 2945 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 2946 { 2947 struct mlx5_ib_resources *devr = &dev->devr; 2948 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2949 struct ib_device *ibdev; 2950 struct ib_pd *pd; 2951 struct ib_cq *cq; 2952 int ret = 0; 2953 2954 2955 /* 2956 * devr->c0 is set once, never changed until device unload. 2957 * Avoid taking the mutex if initialization is already done. 2958 */ 2959 if (devr->c0) 2960 return 0; 2961 2962 mutex_lock(&devr->cq_lock); 2963 if (devr->c0) 2964 goto unlock; 2965 2966 ibdev = &dev->ib_dev; 2967 pd = ib_alloc_pd(ibdev, 0); 2968 if (IS_ERR(pd)) { 2969 ret = PTR_ERR(pd); 2970 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret); 2971 goto unlock; 2972 } 2973 2974 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2975 if (IS_ERR(cq)) { 2976 ret = PTR_ERR(cq); 2977 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret); 2978 ib_dealloc_pd(pd); 2979 goto unlock; 2980 } 2981 2982 devr->p0 = pd; 2983 devr->c0 = cq; 2984 2985 unlock: 2986 mutex_unlock(&devr->cq_lock); 2987 return ret; 2988 } 2989 2990 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 2991 { 2992 struct mlx5_ib_resources *devr = &dev->devr; 2993 struct ib_srq_init_attr attr; 2994 struct ib_srq *s0, *s1; 2995 int ret = 0; 2996 2997 /* 2998 * devr->s1 is set once, never changed until device unload. 2999 * Avoid taking the mutex if initialization is already done. 3000 */ 3001 if (devr->s1) 3002 return 0; 3003 3004 mutex_lock(&devr->srq_lock); 3005 if (devr->s1) 3006 goto unlock; 3007 3008 ret = mlx5_ib_dev_res_cq_init(dev); 3009 if (ret) 3010 goto unlock; 3011 3012 memset(&attr, 0, sizeof(attr)); 3013 attr.attr.max_sge = 1; 3014 attr.attr.max_wr = 1; 3015 attr.srq_type = IB_SRQT_XRC; 3016 attr.ext.cq = devr->c0; 3017 3018 s0 = ib_create_srq(devr->p0, &attr); 3019 if (IS_ERR(s0)) { 3020 ret = PTR_ERR(s0); 3021 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret); 3022 goto unlock; 3023 } 3024 3025 memset(&attr, 0, sizeof(attr)); 3026 attr.attr.max_sge = 1; 3027 attr.attr.max_wr = 1; 3028 attr.srq_type = IB_SRQT_BASIC; 3029 3030 s1 = ib_create_srq(devr->p0, &attr); 3031 if (IS_ERR(s1)) { 3032 ret = PTR_ERR(s1); 3033 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret); 3034 ib_destroy_srq(s0); 3035 } 3036 3037 devr->s0 = s0; 3038 devr->s1 = s1; 3039 3040 unlock: 3041 mutex_unlock(&devr->srq_lock); 3042 return ret; 3043 } 3044 3045 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3046 { 3047 struct mlx5_ib_resources *devr = &dev->devr; 3048 int ret; 3049 3050 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3051 return -EOPNOTSUPP; 3052 3053 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3054 if (ret) 3055 return ret; 3056 3057 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3058 if (ret) { 3059 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3060 return ret; 3061 } 3062 3063 mutex_init(&devr->cq_lock); 3064 mutex_init(&devr->srq_lock); 3065 3066 return 0; 3067 } 3068 3069 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3070 { 3071 struct mlx5_ib_resources *devr = &dev->devr; 3072 3073 /* After s0/s1 init, they are not unset during the device lifetime. */ 3074 if (devr->s1) { 3075 ib_destroy_srq(devr->s1); 3076 ib_destroy_srq(devr->s0); 3077 } 3078 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3079 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3080 /* After p0/c0 init, they are not unset during the device lifetime. */ 3081 if (devr->c0) { 3082 ib_destroy_cq(devr->c0); 3083 ib_dealloc_pd(devr->p0); 3084 } 3085 mutex_destroy(&devr->cq_lock); 3086 mutex_destroy(&devr->srq_lock); 3087 } 3088 3089 static int 3090 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3091 { 3092 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3093 struct mlx5_core_dev *mdev = dev->mdev; 3094 void *mkc; 3095 u32 mkey; 3096 u32 pdn; 3097 u32 *in; 3098 int err; 3099 3100 err = mlx5_core_alloc_pd(mdev, &pdn); 3101 if (err) 3102 return err; 3103 3104 in = kvzalloc(inlen, GFP_KERNEL); 3105 if (!in) { 3106 err = -ENOMEM; 3107 goto err; 3108 } 3109 3110 MLX5_SET(create_mkey_in, in, data_direct, 1); 3111 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3112 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3113 MLX5_SET(mkc, mkc, lw, 1); 3114 MLX5_SET(mkc, mkc, lr, 1); 3115 MLX5_SET(mkc, mkc, rw, 1); 3116 MLX5_SET(mkc, mkc, rr, 1); 3117 MLX5_SET(mkc, mkc, a, 1); 3118 MLX5_SET(mkc, mkc, pd, pdn); 3119 MLX5_SET(mkc, mkc, length64, 1); 3120 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3121 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3122 kvfree(in); 3123 if (err) 3124 goto err; 3125 3126 dev->ddr.mkey = mkey; 3127 dev->ddr.pdn = pdn; 3128 return 0; 3129 3130 err: 3131 mlx5_core_dealloc_pd(mdev, pdn); 3132 return err; 3133 } 3134 3135 static void 3136 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3137 { 3138 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3139 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3140 } 3141 3142 static u32 get_core_cap_flags(struct ib_device *ibdev, 3143 struct mlx5_hca_vport_context *rep) 3144 { 3145 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3146 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3147 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3148 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3149 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3150 u32 ret = 0; 3151 3152 if (rep->grh_required) 3153 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3154 3155 if (dev->num_plane) 3156 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3157 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3158 RDMA_CORE_CAP_AF_IB; 3159 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3160 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3161 3162 if (ll == IB_LINK_LAYER_INFINIBAND) 3163 return ret | RDMA_CORE_PORT_IBA_IB; 3164 3165 if (raw_support) 3166 ret |= RDMA_CORE_PORT_RAW_PACKET; 3167 3168 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3169 return ret; 3170 3171 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3172 return ret; 3173 3174 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3175 ret |= RDMA_CORE_PORT_IBA_ROCE; 3176 3177 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3178 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3179 3180 return ret; 3181 } 3182 3183 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3184 struct ib_port_immutable *immutable) 3185 { 3186 struct ib_port_attr attr; 3187 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3188 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3189 struct mlx5_hca_vport_context rep = {0}; 3190 int err; 3191 3192 err = ib_query_port(ibdev, port_num, &attr); 3193 if (err) 3194 return err; 3195 3196 if (ll == IB_LINK_LAYER_INFINIBAND) { 3197 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3198 port_num = smi_to_native_portnum(dev, port_num); 3199 3200 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3201 &rep); 3202 if (err) 3203 return err; 3204 } 3205 3206 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3207 immutable->gid_tbl_len = attr.gid_tbl_len; 3208 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3209 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3210 3211 return 0; 3212 } 3213 3214 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3215 struct ib_port_immutable *immutable) 3216 { 3217 struct ib_port_attr attr; 3218 int err; 3219 3220 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3221 3222 err = ib_query_port(ibdev, port_num, &attr); 3223 if (err) 3224 return err; 3225 3226 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3227 immutable->gid_tbl_len = attr.gid_tbl_len; 3228 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3229 3230 return 0; 3231 } 3232 3233 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3234 { 3235 struct mlx5_ib_dev *dev = 3236 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3237 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3238 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3239 fw_rev_sub(dev->mdev)); 3240 } 3241 3242 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3243 { 3244 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3245 lag_events); 3246 struct mlx5_core_dev *mdev = dev->mdev; 3247 struct ib_device *ibdev = &dev->ib_dev; 3248 struct net_device *old_ndev = NULL; 3249 struct mlx5_ib_port *port; 3250 struct net_device *ndev; 3251 u32 portnum = 0; 3252 int ret = 0; 3253 int i; 3254 3255 switch (event) { 3256 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3257 ndev = data; 3258 if (ndev) { 3259 if (!mlx5_lag_is_roce(mdev)) { 3260 // sriov lag 3261 for (i = 0; i < dev->num_ports; i++) { 3262 port = &dev->port[i]; 3263 if (port->rep && port->rep->vport == 3264 MLX5_VPORT_UPLINK) { 3265 portnum = i; 3266 break; 3267 } 3268 } 3269 } 3270 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3271 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3272 if (ret) 3273 goto out; 3274 3275 if (old_ndev) 3276 roce_del_all_netdev_gids(ibdev, portnum + 1, 3277 old_ndev); 3278 rdma_roce_rescan_port(ibdev, portnum + 1); 3279 } 3280 break; 3281 default: 3282 return NOTIFY_DONE; 3283 } 3284 3285 out: 3286 dev_put(old_ndev); 3287 return notifier_from_errno(ret); 3288 } 3289 3290 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3291 { 3292 dev->lag_events.notifier_call = lag_event; 3293 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3294 &dev->lag_events); 3295 } 3296 3297 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3298 { 3299 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3300 &dev->lag_events); 3301 } 3302 3303 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3304 { 3305 struct mlx5_core_dev *mdev = dev->mdev; 3306 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3307 MLX5_FLOW_NAMESPACE_LAG); 3308 struct mlx5_flow_table *ft; 3309 int err; 3310 3311 if (!ns || !mlx5_lag_is_active(mdev)) 3312 return 0; 3313 3314 err = mlx5_cmd_create_vport_lag(mdev); 3315 if (err) 3316 return err; 3317 3318 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3319 if (IS_ERR(ft)) { 3320 err = PTR_ERR(ft); 3321 goto err_destroy_vport_lag; 3322 } 3323 3324 mlx5e_lag_event_register(dev); 3325 dev->flow_db->lag_demux_ft = ft; 3326 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3327 dev->lag_active = true; 3328 return 0; 3329 3330 err_destroy_vport_lag: 3331 mlx5_cmd_destroy_vport_lag(mdev); 3332 return err; 3333 } 3334 3335 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3336 { 3337 struct mlx5_core_dev *mdev = dev->mdev; 3338 3339 if (dev->lag_active) { 3340 dev->lag_active = false; 3341 3342 mlx5e_lag_event_unregister(dev); 3343 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3344 dev->flow_db->lag_demux_ft = NULL; 3345 3346 mlx5_cmd_destroy_vport_lag(mdev); 3347 } 3348 } 3349 3350 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3351 struct net_device *netdev) 3352 { 3353 int err; 3354 3355 if (roce->tracking_netdev) 3356 return; 3357 roce->tracking_netdev = netdev; 3358 roce->nb.notifier_call = mlx5_netdev_event; 3359 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3360 WARN_ON(err); 3361 } 3362 3363 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3364 { 3365 if (!roce->tracking_netdev) 3366 return; 3367 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3368 &roce->nn); 3369 roce->tracking_netdev = NULL; 3370 } 3371 3372 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3373 unsigned long event, void *data) 3374 { 3375 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3376 struct net_device *netdev = data; 3377 3378 switch (event) { 3379 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3380 if (netdev) 3381 mlx5_netdev_notifier_register(roce, netdev); 3382 else 3383 mlx5_netdev_notifier_unregister(roce); 3384 break; 3385 default: 3386 return NOTIFY_DONE; 3387 } 3388 3389 return NOTIFY_OK; 3390 } 3391 3392 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3393 { 3394 struct mlx5_roce *roce = &dev->port[port_num].roce; 3395 3396 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3397 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3398 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3399 } 3400 3401 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3402 { 3403 struct mlx5_roce *roce = &dev->port[port_num].roce; 3404 3405 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3406 mlx5_netdev_notifier_unregister(roce); 3407 } 3408 3409 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3410 { 3411 int err; 3412 3413 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3414 err = mlx5_nic_vport_enable_roce(dev->mdev); 3415 if (err) 3416 return err; 3417 } 3418 3419 err = mlx5_eth_lag_init(dev); 3420 if (err) 3421 goto err_disable_roce; 3422 3423 return 0; 3424 3425 err_disable_roce: 3426 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3427 mlx5_nic_vport_disable_roce(dev->mdev); 3428 3429 return err; 3430 } 3431 3432 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3433 { 3434 mlx5_eth_lag_cleanup(dev); 3435 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3436 mlx5_nic_vport_disable_roce(dev->mdev); 3437 } 3438 3439 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3440 enum rdma_netdev_t type, 3441 struct rdma_netdev_alloc_params *params) 3442 { 3443 if (type != RDMA_NETDEV_IPOIB) 3444 return -EOPNOTSUPP; 3445 3446 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3447 } 3448 3449 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3450 size_t count, loff_t *pos) 3451 { 3452 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3453 char lbuf[20]; 3454 int len; 3455 3456 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3457 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3458 } 3459 3460 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3461 size_t count, loff_t *pos) 3462 { 3463 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3464 u32 timeout; 3465 u32 var; 3466 3467 if (kstrtouint_from_user(buf, count, 0, &var)) 3468 return -EFAULT; 3469 3470 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3471 1000); 3472 if (timeout != var) 3473 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3474 timeout); 3475 3476 delay_drop->timeout = timeout; 3477 3478 return count; 3479 } 3480 3481 static const struct file_operations fops_delay_drop_timeout = { 3482 .owner = THIS_MODULE, 3483 .open = simple_open, 3484 .write = delay_drop_timeout_write, 3485 .read = delay_drop_timeout_read, 3486 }; 3487 3488 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3489 struct mlx5_ib_multiport_info *mpi) 3490 { 3491 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3492 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3493 int comps; 3494 int err; 3495 int i; 3496 3497 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3498 3499 mlx5_core_mp_event_replay(ibdev->mdev, 3500 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3501 NULL); 3502 mlx5_core_mp_event_replay(mpi->mdev, 3503 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3504 NULL); 3505 3506 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3507 3508 spin_lock(&port->mp.mpi_lock); 3509 if (!mpi->ibdev) { 3510 spin_unlock(&port->mp.mpi_lock); 3511 return; 3512 } 3513 3514 mpi->ibdev = NULL; 3515 3516 spin_unlock(&port->mp.mpi_lock); 3517 if (mpi->mdev_events.notifier_call) 3518 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3519 mpi->mdev_events.notifier_call = NULL; 3520 mlx5_mdev_netdev_untrack(ibdev, port_num); 3521 spin_lock(&port->mp.mpi_lock); 3522 3523 comps = mpi->mdev_refcnt; 3524 if (comps) { 3525 mpi->unaffiliate = true; 3526 init_completion(&mpi->unref_comp); 3527 spin_unlock(&port->mp.mpi_lock); 3528 3529 for (i = 0; i < comps; i++) 3530 wait_for_completion(&mpi->unref_comp); 3531 3532 spin_lock(&port->mp.mpi_lock); 3533 mpi->unaffiliate = false; 3534 } 3535 3536 port->mp.mpi = NULL; 3537 3538 spin_unlock(&port->mp.mpi_lock); 3539 3540 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3541 3542 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3543 /* Log an error, still needed to cleanup the pointers and add 3544 * it back to the list. 3545 */ 3546 if (err) 3547 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3548 port_num + 1); 3549 3550 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3551 } 3552 3553 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3554 struct mlx5_ib_multiport_info *mpi) 3555 { 3556 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3557 u64 key; 3558 int err; 3559 3560 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3561 3562 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3563 if (ibdev->port[port_num].mp.mpi) { 3564 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3565 port_num + 1); 3566 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3567 return false; 3568 } 3569 3570 ibdev->port[port_num].mp.mpi = mpi; 3571 mpi->ibdev = ibdev; 3572 mpi->mdev_events.notifier_call = NULL; 3573 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3574 3575 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3576 if (err) 3577 goto unbind; 3578 3579 mlx5_mdev_netdev_track(ibdev, port_num); 3580 3581 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3582 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3583 3584 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3585 3586 key = mpi->mdev->priv.adev_idx; 3587 mlx5_core_mp_event_replay(mpi->mdev, 3588 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3589 &key); 3590 mlx5_core_mp_event_replay(ibdev->mdev, 3591 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3592 &key); 3593 3594 return true; 3595 3596 unbind: 3597 mlx5_ib_unbind_slave_port(ibdev, mpi); 3598 return false; 3599 } 3600 3601 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3602 { 3603 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3604 int ret; 3605 3606 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3607 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3608 return 0; 3609 3610 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3611 if (ret) 3612 return ret; 3613 3614 ret = mlx5_ib_create_data_direct_resources(dev); 3615 if (ret) 3616 return ret; 3617 3618 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3619 ret = mlx5_data_direct_ib_reg(dev, vuid); 3620 if (ret) 3621 mlx5_ib_free_data_direct_resources(dev); 3622 3623 return ret; 3624 } 3625 3626 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3627 { 3628 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3629 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3630 return; 3631 3632 mlx5_data_direct_ib_unreg(dev); 3633 mlx5_ib_free_data_direct_resources(dev); 3634 } 3635 3636 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3637 { 3638 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3639 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3640 port_num + 1); 3641 struct mlx5_ib_multiport_info *mpi; 3642 int err; 3643 u32 i; 3644 3645 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3646 return 0; 3647 3648 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3649 &dev->sys_image_guid); 3650 if (err) 3651 return err; 3652 3653 err = mlx5_nic_vport_enable_roce(dev->mdev); 3654 if (err) 3655 return err; 3656 3657 mutex_lock(&mlx5_ib_multiport_mutex); 3658 for (i = 0; i < dev->num_ports; i++) { 3659 bool bound = false; 3660 3661 /* build a stub multiport info struct for the native port. */ 3662 if (i == port_num) { 3663 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3664 if (!mpi) { 3665 mutex_unlock(&mlx5_ib_multiport_mutex); 3666 mlx5_nic_vport_disable_roce(dev->mdev); 3667 return -ENOMEM; 3668 } 3669 3670 mpi->is_master = true; 3671 mpi->mdev = dev->mdev; 3672 mpi->sys_image_guid = dev->sys_image_guid; 3673 dev->port[i].mp.mpi = mpi; 3674 mpi->ibdev = dev; 3675 mpi = NULL; 3676 continue; 3677 } 3678 3679 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3680 list) { 3681 if (dev->sys_image_guid == mpi->sys_image_guid && 3682 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 3683 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 3684 bound = mlx5_ib_bind_slave_port(dev, mpi); 3685 } 3686 3687 if (bound) { 3688 dev_dbg(mpi->mdev->device, 3689 "removing port from unaffiliated list.\n"); 3690 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3691 list_del(&mpi->list); 3692 break; 3693 } 3694 } 3695 if (!bound) 3696 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3697 i + 1); 3698 } 3699 3700 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3701 mutex_unlock(&mlx5_ib_multiport_mutex); 3702 return err; 3703 } 3704 3705 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3706 { 3707 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3708 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3709 port_num + 1); 3710 u32 i; 3711 3712 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3713 return; 3714 3715 mutex_lock(&mlx5_ib_multiport_mutex); 3716 for (i = 0; i < dev->num_ports; i++) { 3717 if (dev->port[i].mp.mpi) { 3718 /* Destroy the native port stub */ 3719 if (i == port_num) { 3720 kfree(dev->port[i].mp.mpi); 3721 dev->port[i].mp.mpi = NULL; 3722 } else { 3723 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3724 i + 1); 3725 list_add_tail(&dev->port[i].mp.mpi->list, 3726 &mlx5_ib_unaffiliated_port_list); 3727 mlx5_ib_unbind_slave_port(dev, 3728 dev->port[i].mp.mpi); 3729 } 3730 } 3731 } 3732 3733 mlx5_ib_dbg(dev, "removing from devlist\n"); 3734 list_del(&dev->ib_dev_list); 3735 mutex_unlock(&mlx5_ib_multiport_mutex); 3736 3737 mlx5_nic_vport_disable_roce(dev->mdev); 3738 } 3739 3740 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3741 enum rdma_remove_reason why, 3742 struct uverbs_attr_bundle *attrs) 3743 { 3744 struct mlx5_user_mmap_entry *obj = uobject->object; 3745 3746 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3747 return 0; 3748 } 3749 3750 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3751 struct mlx5_user_mmap_entry *entry, 3752 size_t length) 3753 { 3754 return rdma_user_mmap_entry_insert_range( 3755 &c->ibucontext, &entry->rdma_entry, length, 3756 (MLX5_IB_MMAP_OFFSET_START << 16), 3757 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3758 } 3759 3760 static struct mlx5_user_mmap_entry * 3761 alloc_var_entry(struct mlx5_ib_ucontext *c) 3762 { 3763 struct mlx5_user_mmap_entry *entry; 3764 struct mlx5_var_table *var_table; 3765 u32 page_idx; 3766 int err; 3767 3768 var_table = &to_mdev(c->ibucontext.device)->var_table; 3769 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3770 if (!entry) 3771 return ERR_PTR(-ENOMEM); 3772 3773 mutex_lock(&var_table->bitmap_lock); 3774 page_idx = find_first_zero_bit(var_table->bitmap, 3775 var_table->num_var_hw_entries); 3776 if (page_idx >= var_table->num_var_hw_entries) { 3777 err = -ENOSPC; 3778 mutex_unlock(&var_table->bitmap_lock); 3779 goto end; 3780 } 3781 3782 set_bit(page_idx, var_table->bitmap); 3783 mutex_unlock(&var_table->bitmap_lock); 3784 3785 entry->address = var_table->hw_start_addr + 3786 (page_idx * var_table->stride_size); 3787 entry->page_idx = page_idx; 3788 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3789 3790 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3791 var_table->stride_size); 3792 if (err) 3793 goto err_insert; 3794 3795 return entry; 3796 3797 err_insert: 3798 mutex_lock(&var_table->bitmap_lock); 3799 clear_bit(page_idx, var_table->bitmap); 3800 mutex_unlock(&var_table->bitmap_lock); 3801 end: 3802 kfree(entry); 3803 return ERR_PTR(err); 3804 } 3805 3806 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3807 struct uverbs_attr_bundle *attrs) 3808 { 3809 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3810 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3811 struct mlx5_ib_ucontext *c; 3812 struct mlx5_user_mmap_entry *entry; 3813 u64 mmap_offset; 3814 u32 length; 3815 int err; 3816 3817 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3818 if (IS_ERR(c)) 3819 return PTR_ERR(c); 3820 3821 entry = alloc_var_entry(c); 3822 if (IS_ERR(entry)) 3823 return PTR_ERR(entry); 3824 3825 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3826 length = entry->rdma_entry.npages * PAGE_SIZE; 3827 uobj->object = entry; 3828 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3829 3830 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3831 &mmap_offset, sizeof(mmap_offset)); 3832 if (err) 3833 return err; 3834 3835 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3836 &entry->page_idx, sizeof(entry->page_idx)); 3837 if (err) 3838 return err; 3839 3840 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3841 &length, sizeof(length)); 3842 return err; 3843 } 3844 3845 DECLARE_UVERBS_NAMED_METHOD( 3846 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3847 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3848 MLX5_IB_OBJECT_VAR, 3849 UVERBS_ACCESS_NEW, 3850 UA_MANDATORY), 3851 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3852 UVERBS_ATTR_TYPE(u32), 3853 UA_MANDATORY), 3854 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3855 UVERBS_ATTR_TYPE(u32), 3856 UA_MANDATORY), 3857 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3858 UVERBS_ATTR_TYPE(u64), 3859 UA_MANDATORY)); 3860 3861 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3862 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3863 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3864 MLX5_IB_OBJECT_VAR, 3865 UVERBS_ACCESS_DESTROY, 3866 UA_MANDATORY)); 3867 3868 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3869 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3870 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3871 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3872 3873 static bool var_is_supported(struct ib_device *device) 3874 { 3875 struct mlx5_ib_dev *dev = to_mdev(device); 3876 3877 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3878 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3879 } 3880 3881 static struct mlx5_user_mmap_entry * 3882 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3883 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3884 { 3885 struct mlx5_user_mmap_entry *entry; 3886 struct mlx5_ib_dev *dev; 3887 u32 uar_index; 3888 int err; 3889 3890 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3891 if (!entry) 3892 return ERR_PTR(-ENOMEM); 3893 3894 dev = to_mdev(c->ibucontext.device); 3895 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3896 if (err) 3897 goto end; 3898 3899 entry->page_idx = uar_index; 3900 entry->address = uar_index2paddress(dev, uar_index); 3901 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3902 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3903 else 3904 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3905 3906 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3907 if (err) 3908 goto err_insert; 3909 3910 return entry; 3911 3912 err_insert: 3913 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3914 end: 3915 kfree(entry); 3916 return ERR_PTR(err); 3917 } 3918 3919 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3920 struct uverbs_attr_bundle *attrs) 3921 { 3922 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3923 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3924 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3925 struct mlx5_ib_ucontext *c; 3926 struct mlx5_user_mmap_entry *entry; 3927 u64 mmap_offset; 3928 u32 length; 3929 int err; 3930 3931 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3932 if (IS_ERR(c)) 3933 return PTR_ERR(c); 3934 3935 err = uverbs_get_const(&alloc_type, attrs, 3936 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3937 if (err) 3938 return err; 3939 3940 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3941 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3942 return -EOPNOTSUPP; 3943 3944 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 3945 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3946 return -EOPNOTSUPP; 3947 3948 entry = alloc_uar_entry(c, alloc_type); 3949 if (IS_ERR(entry)) 3950 return PTR_ERR(entry); 3951 3952 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3953 length = entry->rdma_entry.npages * PAGE_SIZE; 3954 uobj->object = entry; 3955 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3956 3957 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3958 &mmap_offset, sizeof(mmap_offset)); 3959 if (err) 3960 return err; 3961 3962 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3963 &entry->page_idx, sizeof(entry->page_idx)); 3964 if (err) 3965 return err; 3966 3967 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3968 &length, sizeof(length)); 3969 return err; 3970 } 3971 3972 DECLARE_UVERBS_NAMED_METHOD( 3973 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3974 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3975 MLX5_IB_OBJECT_UAR, 3976 UVERBS_ACCESS_NEW, 3977 UA_MANDATORY), 3978 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3979 enum mlx5_ib_uapi_uar_alloc_type, 3980 UA_MANDATORY), 3981 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3982 UVERBS_ATTR_TYPE(u32), 3983 UA_MANDATORY), 3984 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3985 UVERBS_ATTR_TYPE(u32), 3986 UA_MANDATORY), 3987 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3988 UVERBS_ATTR_TYPE(u64), 3989 UA_MANDATORY)); 3990 3991 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3992 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3993 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3994 MLX5_IB_OBJECT_UAR, 3995 UVERBS_ACCESS_DESTROY, 3996 UA_MANDATORY)); 3997 3998 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3999 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4000 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4001 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4002 4003 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4004 mlx5_ib_query_context, 4005 UVERBS_OBJECT_DEVICE, 4006 UVERBS_METHOD_QUERY_CONTEXT, 4007 UVERBS_ATTR_PTR_OUT( 4008 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4009 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4010 dump_fill_mkey), 4011 UA_MANDATORY)); 4012 4013 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4014 mlx5_ib_reg_dmabuf_mr, 4015 UVERBS_OBJECT_MR, 4016 UVERBS_METHOD_REG_DMABUF_MR, 4017 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4018 enum mlx5_ib_uapi_reg_dmabuf_flags, 4019 UA_OPTIONAL)); 4020 4021 static const struct uapi_definition mlx5_ib_defs[] = { 4022 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4023 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4024 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4025 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4026 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4027 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4028 4029 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4030 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4031 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4032 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4033 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4034 {} 4035 }; 4036 4037 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4038 { 4039 mlx5_ib_data_direct_cleanup(dev); 4040 mlx5_ib_cleanup_multiport_master(dev); 4041 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4042 mutex_destroy(&dev->cap_mask_mutex); 4043 WARN_ON(!xa_empty(&dev->sig_mrs)); 4044 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4045 mlx5r_macsec_dealloc_gids(dev); 4046 } 4047 4048 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4049 { 4050 struct mlx5_core_dev *mdev = dev->mdev; 4051 int err, i; 4052 4053 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4054 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4055 dev->ib_dev.dev.parent = mdev->device; 4056 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4057 4058 for (i = 0; i < dev->num_ports; i++) { 4059 spin_lock_init(&dev->port[i].mp.mpi_lock); 4060 dev->port[i].roce.dev = dev; 4061 dev->port[i].roce.native_port_num = i + 1; 4062 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4063 } 4064 4065 err = mlx5r_cmd_query_special_mkeys(dev); 4066 if (err) 4067 return err; 4068 4069 err = mlx5r_macsec_init_gids_and_devlist(dev); 4070 if (err) 4071 return err; 4072 4073 err = mlx5_ib_init_multiport_master(dev); 4074 if (err) 4075 goto err; 4076 4077 err = set_has_smi_cap(dev); 4078 if (err) 4079 goto err_mp; 4080 4081 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4082 if (err) 4083 goto err_mp; 4084 4085 if (mlx5_use_mad_ifc(dev)) 4086 get_ext_port_caps(dev); 4087 4088 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4089 4090 mutex_init(&dev->cap_mask_mutex); 4091 mutex_init(&dev->data_direct_lock); 4092 INIT_LIST_HEAD(&dev->qp_list); 4093 spin_lock_init(&dev->reset_flow_resource_lock); 4094 xa_init(&dev->odp_mkeys); 4095 xa_init(&dev->sig_mrs); 4096 atomic_set(&dev->mkey_var, 0); 4097 4098 spin_lock_init(&dev->dm.lock); 4099 dev->dm.dev = mdev; 4100 err = mlx5_ib_data_direct_init(dev); 4101 if (err) 4102 goto err_mp; 4103 4104 return 0; 4105 err_mp: 4106 mlx5_ib_cleanup_multiport_master(dev); 4107 err: 4108 mlx5r_macsec_dealloc_gids(dev); 4109 return err; 4110 } 4111 4112 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4113 enum rdma_nl_dev_type type, 4114 const char *name); 4115 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4116 4117 static const struct ib_device_ops mlx5_ib_dev_ops = { 4118 .owner = THIS_MODULE, 4119 .driver_id = RDMA_DRIVER_MLX5, 4120 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4121 4122 .add_gid = mlx5_ib_add_gid, 4123 .add_sub_dev = mlx5_ib_add_sub_dev, 4124 .alloc_mr = mlx5_ib_alloc_mr, 4125 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4126 .alloc_pd = mlx5_ib_alloc_pd, 4127 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4128 .attach_mcast = mlx5_ib_mcg_attach, 4129 .check_mr_status = mlx5_ib_check_mr_status, 4130 .create_ah = mlx5_ib_create_ah, 4131 .create_cq = mlx5_ib_create_cq, 4132 .create_qp = mlx5_ib_create_qp, 4133 .create_srq = mlx5_ib_create_srq, 4134 .create_user_ah = mlx5_ib_create_ah, 4135 .dealloc_pd = mlx5_ib_dealloc_pd, 4136 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4137 .del_gid = mlx5_ib_del_gid, 4138 .del_sub_dev = mlx5_ib_del_sub_dev, 4139 .dereg_mr = mlx5_ib_dereg_mr, 4140 .destroy_ah = mlx5_ib_destroy_ah, 4141 .destroy_cq = mlx5_ib_destroy_cq, 4142 .destroy_qp = mlx5_ib_destroy_qp, 4143 .destroy_srq = mlx5_ib_destroy_srq, 4144 .detach_mcast = mlx5_ib_mcg_detach, 4145 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4146 .drain_rq = mlx5_ib_drain_rq, 4147 .drain_sq = mlx5_ib_drain_sq, 4148 .device_group = &mlx5_attr_group, 4149 .get_dev_fw_str = get_dev_fw_str, 4150 .get_dma_mr = mlx5_ib_get_dma_mr, 4151 .get_link_layer = mlx5_ib_port_link_layer, 4152 .map_mr_sg = mlx5_ib_map_mr_sg, 4153 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4154 .mmap = mlx5_ib_mmap, 4155 .mmap_free = mlx5_ib_mmap_free, 4156 .modify_cq = mlx5_ib_modify_cq, 4157 .modify_device = mlx5_ib_modify_device, 4158 .modify_port = mlx5_ib_modify_port, 4159 .modify_qp = mlx5_ib_modify_qp, 4160 .modify_srq = mlx5_ib_modify_srq, 4161 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4162 .poll_cq = mlx5_ib_poll_cq, 4163 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4164 .post_recv = mlx5_ib_post_recv_nodrain, 4165 .post_send = mlx5_ib_post_send_nodrain, 4166 .post_srq_recv = mlx5_ib_post_srq_recv, 4167 .process_mad = mlx5_ib_process_mad, 4168 .query_ah = mlx5_ib_query_ah, 4169 .query_device = mlx5_ib_query_device, 4170 .query_gid = mlx5_ib_query_gid, 4171 .query_pkey = mlx5_ib_query_pkey, 4172 .query_qp = mlx5_ib_query_qp, 4173 .query_srq = mlx5_ib_query_srq, 4174 .query_ucontext = mlx5_ib_query_ucontext, 4175 .reg_user_mr = mlx5_ib_reg_user_mr, 4176 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4177 .req_notify_cq = mlx5_ib_arm_cq, 4178 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4179 .resize_cq = mlx5_ib_resize_cq, 4180 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4181 4182 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4183 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4184 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4185 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4186 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4187 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4188 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4189 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4190 }; 4191 4192 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4193 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4194 }; 4195 4196 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4197 .get_vf_config = mlx5_ib_get_vf_config, 4198 .get_vf_guid = mlx5_ib_get_vf_guid, 4199 .get_vf_stats = mlx5_ib_get_vf_stats, 4200 .set_vf_guid = mlx5_ib_set_vf_guid, 4201 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4202 }; 4203 4204 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4205 .alloc_mw = mlx5_ib_alloc_mw, 4206 .dealloc_mw = mlx5_ib_dealloc_mw, 4207 4208 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4209 }; 4210 4211 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4212 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4213 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4214 4215 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4216 }; 4217 4218 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4219 { 4220 struct mlx5_core_dev *mdev = dev->mdev; 4221 struct mlx5_var_table *var_table = &dev->var_table; 4222 u8 log_doorbell_bar_size; 4223 u8 log_doorbell_stride; 4224 u64 bar_size; 4225 4226 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4227 log_doorbell_bar_size); 4228 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4229 log_doorbell_stride); 4230 var_table->hw_start_addr = dev->mdev->bar_addr + 4231 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4232 doorbell_bar_offset); 4233 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4234 var_table->stride_size = 1ULL << log_doorbell_stride; 4235 var_table->num_var_hw_entries = div_u64(bar_size, 4236 var_table->stride_size); 4237 mutex_init(&var_table->bitmap_lock); 4238 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4239 GFP_KERNEL); 4240 return (var_table->bitmap) ? 0 : -ENOMEM; 4241 } 4242 4243 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4244 { 4245 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4246 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4247 4248 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4249 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4250 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4251 } 4252 4253 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4254 { 4255 int ret; 4256 4257 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4258 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4259 if (ret) 4260 return ret; 4261 } 4262 4263 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4264 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4265 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4266 if (ret) 4267 goto remove_local; 4268 } 4269 4270 return 0; 4271 4272 remove_local: 4273 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4274 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4275 return ret; 4276 } 4277 4278 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4279 { 4280 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4281 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4282 mlx5_ib_cleanup_ucaps(dev); 4283 4284 bitmap_free(dev->var_table.bitmap); 4285 } 4286 4287 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4288 { 4289 struct mlx5_core_dev *mdev = dev->mdev; 4290 int err; 4291 4292 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4293 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4294 ib_set_device_ops(&dev->ib_dev, 4295 &mlx5_ib_dev_ipoib_enhanced_ops); 4296 4297 if (mlx5_core_is_pf(mdev)) 4298 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4299 4300 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4301 4302 if (MLX5_CAP_GEN(mdev, imaicl)) 4303 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4304 4305 if (MLX5_CAP_GEN(mdev, xrc)) 4306 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4307 4308 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4309 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4310 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4311 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4312 4313 if (mdev->st) 4314 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4315 4316 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4317 4318 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4319 dev->ib_dev.driver_def = mlx5_ib_defs; 4320 4321 err = init_node_data(dev); 4322 if (err) 4323 return err; 4324 4325 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4326 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4327 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4328 mutex_init(&dev->lb.mutex); 4329 4330 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4331 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4332 err = mlx5_ib_init_var_table(dev); 4333 if (err) 4334 return err; 4335 } 4336 4337 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4338 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4339 err = mlx5_ib_init_ucaps(dev); 4340 if (err) 4341 return err; 4342 } 4343 4344 dev->ib_dev.use_cq_dim = true; 4345 4346 return 0; 4347 } 4348 4349 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4350 .get_port_immutable = mlx5_port_immutable, 4351 .query_port = mlx5_ib_query_port, 4352 }; 4353 4354 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4355 { 4356 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4357 return 0; 4358 } 4359 4360 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4361 .get_port_immutable = mlx5_port_rep_immutable, 4362 .query_port = mlx5_ib_rep_query_port, 4363 .query_pkey = mlx5_ib_rep_query_pkey, 4364 }; 4365 4366 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4367 { 4368 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4369 return 0; 4370 } 4371 4372 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4373 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4374 .create_wq = mlx5_ib_create_wq, 4375 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4376 .destroy_wq = mlx5_ib_destroy_wq, 4377 .modify_wq = mlx5_ib_modify_wq, 4378 4379 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4380 ib_rwq_ind_tbl), 4381 }; 4382 4383 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4384 { 4385 struct mlx5_core_dev *mdev = dev->mdev; 4386 enum rdma_link_layer ll; 4387 int port_type_cap; 4388 u32 port_num = 0; 4389 int err; 4390 4391 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4392 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4393 4394 if (ll == IB_LINK_LAYER_ETHERNET) { 4395 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4396 4397 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4398 4399 /* Register only for native ports */ 4400 mlx5_mdev_netdev_track(dev, port_num); 4401 4402 err = mlx5_enable_eth(dev); 4403 if (err) 4404 goto cleanup; 4405 } 4406 4407 return 0; 4408 cleanup: 4409 mlx5_mdev_netdev_untrack(dev, port_num); 4410 return err; 4411 } 4412 4413 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4414 { 4415 struct mlx5_core_dev *mdev = dev->mdev; 4416 enum rdma_link_layer ll; 4417 int port_type_cap; 4418 u32 port_num; 4419 4420 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4421 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4422 4423 if (ll == IB_LINK_LAYER_ETHERNET) { 4424 mlx5_disable_eth(dev); 4425 4426 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4427 mlx5_mdev_netdev_untrack(dev, port_num); 4428 } 4429 } 4430 4431 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4432 { 4433 mlx5_ib_init_cong_debugfs(dev, 4434 mlx5_core_native_port_num(dev->mdev) - 1); 4435 return 0; 4436 } 4437 4438 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4439 { 4440 mlx5_ib_cleanup_cong_debugfs(dev, 4441 mlx5_core_native_port_num(dev->mdev) - 1); 4442 } 4443 4444 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4445 { 4446 int err; 4447 4448 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4449 if (err) 4450 return err; 4451 4452 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4453 if (err) 4454 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4455 4456 return err; 4457 } 4458 4459 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4460 { 4461 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4462 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4463 } 4464 4465 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4466 { 4467 const char *name; 4468 4469 if (dev->sub_dev_name) { 4470 name = dev->sub_dev_name; 4471 ib_mark_name_assigned_by_user(&dev->ib_dev); 4472 } else if (!mlx5_lag_is_active(dev->mdev)) 4473 name = "mlx5_%d"; 4474 else 4475 name = "mlx5_bond_%d"; 4476 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4477 } 4478 4479 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4480 { 4481 mlx5_mkey_cache_cleanup(dev); 4482 mlx5r_umr_resource_cleanup(dev); 4483 mlx5r_umr_cleanup(dev); 4484 } 4485 4486 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4487 { 4488 ib_unregister_device(&dev->ib_dev); 4489 } 4490 4491 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4492 { 4493 int ret; 4494 4495 ret = mlx5r_umr_init(dev); 4496 if (ret) 4497 return ret; 4498 4499 ret = mlx5_mkey_cache_init(dev); 4500 if (ret) 4501 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4502 return ret; 4503 } 4504 4505 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4506 { 4507 struct dentry *root; 4508 4509 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4510 return 0; 4511 4512 mutex_init(&dev->delay_drop.lock); 4513 dev->delay_drop.dev = dev; 4514 dev->delay_drop.activate = false; 4515 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4516 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4517 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4518 atomic_set(&dev->delay_drop.events_cnt, 0); 4519 4520 if (!mlx5_debugfs_root) 4521 return 0; 4522 4523 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4524 dev->delay_drop.dir_debugfs = root; 4525 4526 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4527 &dev->delay_drop.events_cnt); 4528 debugfs_create_atomic_t("num_rqs", 0400, root, 4529 &dev->delay_drop.rqs_cnt); 4530 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4531 &fops_delay_drop_timeout); 4532 return 0; 4533 } 4534 4535 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4536 { 4537 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4538 return; 4539 4540 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4541 if (!dev->delay_drop.dir_debugfs) 4542 return; 4543 4544 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4545 dev->delay_drop.dir_debugfs = NULL; 4546 } 4547 4548 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4549 { 4550 struct mlx5_ib_resources *devr = &dev->devr; 4551 int port; 4552 4553 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4554 INIT_WORK(&devr->ports[port].pkey_change_work, 4555 pkey_change_handler); 4556 4557 dev->mdev_events.notifier_call = mlx5_ib_event; 4558 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4559 4560 mlx5r_macsec_event_register(dev); 4561 4562 return 0; 4563 } 4564 4565 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4566 { 4567 struct mlx5_ib_resources *devr = &dev->devr; 4568 int port; 4569 4570 mlx5r_macsec_event_unregister(dev); 4571 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4572 4573 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4574 cancel_work_sync(&devr->ports[port].pkey_change_work); 4575 } 4576 4577 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4578 struct mlx5_data_direct_dev *dev) 4579 { 4580 mutex_lock(&ibdev->data_direct_lock); 4581 ibdev->data_direct_dev = dev; 4582 mutex_unlock(&ibdev->data_direct_lock); 4583 } 4584 4585 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4586 { 4587 mutex_lock(&ibdev->data_direct_lock); 4588 mlx5_ib_revoke_data_direct_mrs(ibdev); 4589 ibdev->data_direct_dev = NULL; 4590 mutex_unlock(&ibdev->data_direct_lock); 4591 } 4592 4593 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4594 const struct mlx5_ib_profile *profile, 4595 int stage) 4596 { 4597 dev->ib_active = false; 4598 4599 /* Number of stages to cleanup */ 4600 while (stage) { 4601 stage--; 4602 if (profile->stage[stage].cleanup) 4603 profile->stage[stage].cleanup(dev); 4604 } 4605 4606 kfree(dev->port); 4607 ib_dealloc_device(&dev->ib_dev); 4608 } 4609 4610 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4611 const struct mlx5_ib_profile *profile) 4612 { 4613 int err; 4614 int i; 4615 4616 dev->profile = profile; 4617 4618 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4619 if (profile->stage[i].init) { 4620 err = profile->stage[i].init(dev); 4621 if (err) 4622 goto err_out; 4623 } 4624 } 4625 4626 dev->ib_active = true; 4627 return 0; 4628 4629 err_out: 4630 /* Clean up stages which were initialized */ 4631 while (i) { 4632 i--; 4633 if (profile->stage[i].cleanup) 4634 profile->stage[i].cleanup(dev); 4635 } 4636 return -ENOMEM; 4637 } 4638 4639 static const struct mlx5_ib_profile pf_profile = { 4640 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4641 mlx5_ib_stage_init_init, 4642 mlx5_ib_stage_init_cleanup), 4643 STAGE_CREATE(MLX5_IB_STAGE_FS, 4644 mlx5_ib_fs_init, 4645 mlx5_ib_fs_cleanup), 4646 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4647 mlx5_ib_stage_caps_init, 4648 mlx5_ib_stage_caps_cleanup), 4649 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4650 mlx5_ib_stage_non_default_cb, 4651 NULL), 4652 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4653 mlx5_ib_roce_init, 4654 mlx5_ib_roce_cleanup), 4655 STAGE_CREATE(MLX5_IB_STAGE_QP, 4656 mlx5_init_qp_table, 4657 mlx5_cleanup_qp_table), 4658 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4659 mlx5_init_srq_table, 4660 mlx5_cleanup_srq_table), 4661 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4662 mlx5_ib_dev_res_init, 4663 mlx5_ib_dev_res_cleanup), 4664 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4665 mlx5_ib_odp_init_one, 4666 mlx5_ib_odp_cleanup_one), 4667 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4668 mlx5_ib_counters_init, 4669 mlx5_ib_counters_cleanup), 4670 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4671 mlx5_ib_stage_cong_debugfs_init, 4672 mlx5_ib_stage_cong_debugfs_cleanup), 4673 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4674 mlx5_ib_stage_bfrag_init, 4675 mlx5_ib_stage_bfrag_cleanup), 4676 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4677 NULL, 4678 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4679 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4680 mlx5_ib_devx_init, 4681 mlx5_ib_devx_cleanup), 4682 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4683 mlx5_ib_stage_ib_reg_init, 4684 mlx5_ib_stage_ib_reg_cleanup), 4685 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4686 mlx5_ib_stage_dev_notifier_init, 4687 mlx5_ib_stage_dev_notifier_cleanup), 4688 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4689 mlx5_ib_stage_post_ib_reg_umr_init, 4690 NULL), 4691 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4692 mlx5_ib_stage_delay_drop_init, 4693 mlx5_ib_stage_delay_drop_cleanup), 4694 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4695 mlx5_ib_restrack_init, 4696 NULL), 4697 }; 4698 4699 const struct mlx5_ib_profile raw_eth_profile = { 4700 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4701 mlx5_ib_stage_init_init, 4702 mlx5_ib_stage_init_cleanup), 4703 STAGE_CREATE(MLX5_IB_STAGE_FS, 4704 mlx5_ib_fs_init, 4705 mlx5_ib_fs_cleanup), 4706 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4707 mlx5_ib_stage_caps_init, 4708 mlx5_ib_stage_caps_cleanup), 4709 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4710 mlx5_ib_stage_raw_eth_non_default_cb, 4711 NULL), 4712 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4713 mlx5_ib_roce_init, 4714 mlx5_ib_roce_cleanup), 4715 STAGE_CREATE(MLX5_IB_STAGE_QP, 4716 mlx5_init_qp_table, 4717 mlx5_cleanup_qp_table), 4718 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4719 mlx5_init_srq_table, 4720 mlx5_cleanup_srq_table), 4721 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4722 mlx5_ib_dev_res_init, 4723 mlx5_ib_dev_res_cleanup), 4724 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4725 mlx5_ib_counters_init, 4726 mlx5_ib_counters_cleanup), 4727 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4728 mlx5_ib_stage_cong_debugfs_init, 4729 mlx5_ib_stage_cong_debugfs_cleanup), 4730 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4731 mlx5_ib_stage_bfrag_init, 4732 mlx5_ib_stage_bfrag_cleanup), 4733 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4734 NULL, 4735 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4736 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4737 mlx5_ib_devx_init, 4738 mlx5_ib_devx_cleanup), 4739 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4740 mlx5_ib_stage_ib_reg_init, 4741 mlx5_ib_stage_ib_reg_cleanup), 4742 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4743 mlx5_ib_stage_dev_notifier_init, 4744 mlx5_ib_stage_dev_notifier_cleanup), 4745 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4746 mlx5_ib_stage_post_ib_reg_umr_init, 4747 NULL), 4748 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4749 mlx5_ib_stage_delay_drop_init, 4750 mlx5_ib_stage_delay_drop_cleanup), 4751 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4752 mlx5_ib_restrack_init, 4753 NULL), 4754 }; 4755 4756 static const struct mlx5_ib_profile plane_profile = { 4757 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4758 mlx5_ib_stage_init_init, 4759 mlx5_ib_stage_init_cleanup), 4760 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4761 mlx5_ib_stage_caps_init, 4762 mlx5_ib_stage_caps_cleanup), 4763 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4764 mlx5_ib_stage_non_default_cb, 4765 NULL), 4766 STAGE_CREATE(MLX5_IB_STAGE_QP, 4767 mlx5_init_qp_table, 4768 mlx5_cleanup_qp_table), 4769 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4770 mlx5_init_srq_table, 4771 mlx5_cleanup_srq_table), 4772 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4773 mlx5_ib_dev_res_init, 4774 mlx5_ib_dev_res_cleanup), 4775 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4776 mlx5_ib_stage_bfrag_init, 4777 mlx5_ib_stage_bfrag_cleanup), 4778 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4779 mlx5_ib_stage_ib_reg_init, 4780 mlx5_ib_stage_ib_reg_cleanup), 4781 }; 4782 4783 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4784 enum rdma_nl_dev_type type, 4785 const char *name) 4786 { 4787 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 4788 enum rdma_link_layer ll; 4789 int ret; 4790 4791 if (mparent->smi_dev) 4792 return ERR_PTR(-EEXIST); 4793 4794 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 4795 port_type)); 4796 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 4797 ll != IB_LINK_LAYER_INFINIBAND || 4798 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 4799 return ERR_PTR(-EOPNOTSUPP); 4800 4801 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4802 mlx5_core_net(mparent->mdev)); 4803 if (!mplane) 4804 return ERR_PTR(-ENOMEM); 4805 4806 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 4807 sizeof(*mplane->port), GFP_KERNEL); 4808 if (!mplane->port) { 4809 ret = -ENOMEM; 4810 goto fail_kcalloc; 4811 } 4812 4813 mplane->ib_dev.type = type; 4814 mplane->mdev = mparent->mdev; 4815 mplane->num_ports = mparent->num_plane; 4816 mplane->sub_dev_name = name; 4817 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 4818 4819 ret = __mlx5_ib_add(mplane, &plane_profile); 4820 if (ret) 4821 goto fail_ib_add; 4822 4823 mparent->smi_dev = mplane; 4824 return &mplane->ib_dev; 4825 4826 fail_ib_add: 4827 kfree(mplane->port); 4828 fail_kcalloc: 4829 ib_dealloc_device(&mplane->ib_dev); 4830 return ERR_PTR(ret); 4831 } 4832 4833 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 4834 { 4835 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 4836 4837 to_mdev(sub_dev->parent)->smi_dev = NULL; 4838 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 4839 } 4840 4841 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4842 const struct auxiliary_device_id *id) 4843 { 4844 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4845 struct mlx5_core_dev *mdev = idev->mdev; 4846 struct mlx5_ib_multiport_info *mpi; 4847 struct mlx5_ib_dev *dev; 4848 bool bound = false; 4849 int err; 4850 4851 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4852 if (!mpi) 4853 return -ENOMEM; 4854 4855 mpi->mdev = mdev; 4856 err = mlx5_query_nic_vport_system_image_guid(mdev, 4857 &mpi->sys_image_guid); 4858 if (err) { 4859 kfree(mpi); 4860 return err; 4861 } 4862 4863 mutex_lock(&mlx5_ib_multiport_mutex); 4864 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4865 if (dev->sys_image_guid == mpi->sys_image_guid && 4866 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 4867 bound = mlx5_ib_bind_slave_port(dev, mpi); 4868 4869 if (bound) { 4870 rdma_roce_rescan_device(&dev->ib_dev); 4871 mpi->ibdev->ib_active = true; 4872 break; 4873 } 4874 } 4875 4876 if (!bound) { 4877 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4878 dev_dbg(mdev->device, 4879 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4880 } 4881 mutex_unlock(&mlx5_ib_multiport_mutex); 4882 4883 auxiliary_set_drvdata(adev, mpi); 4884 return 0; 4885 } 4886 4887 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4888 { 4889 struct mlx5_ib_multiport_info *mpi; 4890 4891 mpi = auxiliary_get_drvdata(adev); 4892 mutex_lock(&mlx5_ib_multiport_mutex); 4893 if (mpi->ibdev) 4894 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4895 else 4896 list_del(&mpi->list); 4897 mutex_unlock(&mlx5_ib_multiport_mutex); 4898 kfree(mpi); 4899 } 4900 4901 static int mlx5r_probe(struct auxiliary_device *adev, 4902 const struct auxiliary_device_id *id) 4903 { 4904 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4905 struct mlx5_core_dev *mdev = idev->mdev; 4906 const struct mlx5_ib_profile *profile; 4907 int port_type_cap, num_ports, ret; 4908 enum rdma_link_layer ll; 4909 struct mlx5_ib_dev *dev; 4910 4911 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4912 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4913 4914 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4915 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4916 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4917 mlx5_core_net(mdev)); 4918 if (!dev) 4919 return -ENOMEM; 4920 4921 if (ll == IB_LINK_LAYER_INFINIBAND) { 4922 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 4923 if (ret) 4924 goto fail; 4925 } 4926 4927 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4928 GFP_KERNEL); 4929 if (!dev->port) { 4930 ret = -ENOMEM; 4931 goto fail; 4932 } 4933 4934 dev->mdev = mdev; 4935 dev->num_ports = num_ports; 4936 dev->ib_dev.phys_port_cnt = num_ports; 4937 4938 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4939 profile = &raw_eth_profile; 4940 else 4941 profile = &pf_profile; 4942 4943 ret = __mlx5_ib_add(dev, profile); 4944 if (ret) 4945 goto fail_ib_add; 4946 4947 auxiliary_set_drvdata(adev, dev); 4948 return 0; 4949 4950 fail_ib_add: 4951 kfree(dev->port); 4952 fail: 4953 ib_dealloc_device(&dev->ib_dev); 4954 return ret; 4955 } 4956 4957 static void mlx5r_remove(struct auxiliary_device *adev) 4958 { 4959 struct mlx5_ib_dev *dev; 4960 4961 dev = auxiliary_get_drvdata(adev); 4962 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4963 } 4964 4965 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4966 { .name = MLX5_ADEV_NAME ".multiport", }, 4967 {}, 4968 }; 4969 4970 static const struct auxiliary_device_id mlx5r_id_table[] = { 4971 { .name = MLX5_ADEV_NAME ".rdma", }, 4972 {}, 4973 }; 4974 4975 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4976 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4977 4978 static struct auxiliary_driver mlx5r_mp_driver = { 4979 .name = "multiport", 4980 .probe = mlx5r_mp_probe, 4981 .remove = mlx5r_mp_remove, 4982 .id_table = mlx5r_mp_id_table, 4983 }; 4984 4985 static struct auxiliary_driver mlx5r_driver = { 4986 .name = "rdma", 4987 .probe = mlx5r_probe, 4988 .remove = mlx5r_remove, 4989 .id_table = mlx5r_id_table, 4990 }; 4991 4992 static int __init mlx5_ib_init(void) 4993 { 4994 int ret; 4995 4996 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4997 if (!xlt_emergency_page) 4998 return -ENOMEM; 4999 5000 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5001 if (!mlx5_ib_event_wq) { 5002 free_page((unsigned long)xlt_emergency_page); 5003 return -ENOMEM; 5004 } 5005 5006 ret = mlx5_ib_qp_event_init(); 5007 if (ret) 5008 goto qp_event_err; 5009 5010 mlx5_ib_odp_init(); 5011 ret = mlx5r_rep_init(); 5012 if (ret) 5013 goto rep_err; 5014 ret = mlx5_data_direct_driver_register(); 5015 if (ret) 5016 goto dd_err; 5017 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5018 if (ret) 5019 goto mp_err; 5020 ret = auxiliary_driver_register(&mlx5r_driver); 5021 if (ret) 5022 goto drv_err; 5023 5024 return 0; 5025 5026 drv_err: 5027 auxiliary_driver_unregister(&mlx5r_mp_driver); 5028 mp_err: 5029 mlx5_data_direct_driver_unregister(); 5030 dd_err: 5031 mlx5r_rep_cleanup(); 5032 rep_err: 5033 mlx5_ib_qp_event_cleanup(); 5034 qp_event_err: 5035 destroy_workqueue(mlx5_ib_event_wq); 5036 free_page((unsigned long)xlt_emergency_page); 5037 return ret; 5038 } 5039 5040 static void __exit mlx5_ib_cleanup(void) 5041 { 5042 mlx5_data_direct_driver_unregister(); 5043 auxiliary_driver_unregister(&mlx5r_driver); 5044 auxiliary_driver_unregister(&mlx5r_mp_driver); 5045 mlx5r_rep_cleanup(); 5046 5047 mlx5_ib_qp_event_cleanup(); 5048 destroy_workqueue(mlx5_ib_event_wq); 5049 free_page((unsigned long)xlt_emergency_page); 5050 } 5051 5052 module_init(mlx5_ib_init); 5053 module_exit(mlx5_ib_cleanup); 5054