1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/driver.h> 29 #include <linux/mlx5/lag.h> 30 #include <linux/list.h> 31 #include <rdma/ib_smi.h> 32 #include <rdma/ib_umem_odp.h> 33 #include <rdma/lag.h> 34 #include <linux/in.h> 35 #include <linux/etherdevice.h> 36 #include "mlx5_ib.h" 37 #include "ib_rep.h" 38 #include "cmd.h" 39 #include "devx.h" 40 #include "dm.h" 41 #include "fs.h" 42 #include "srq.h" 43 #include "qp.h" 44 #include "wr.h" 45 #include "restrack.h" 46 #include "counters.h" 47 #include "umr.h" 48 #include <rdma/uverbs_std_types.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_verbs.h> 51 #include <rdma/mlx5_user_ioctl_cmds.h> 52 #include <rdma/ib_ucaps.h> 53 #include "macsec.h" 54 #include "data_direct.h" 55 #include "dmah.h" 56 57 #define UVERBS_MODULE_NAME mlx5_ib 58 #include <rdma/uverbs_named_ioctl.h> 59 60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 61 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 62 MODULE_LICENSE("Dual BSD/GPL"); 63 64 struct mlx5_ib_event_work { 65 struct work_struct work; 66 union { 67 struct mlx5_ib_dev *dev; 68 struct mlx5_ib_multiport_info *mpi; 69 }; 70 bool is_slave; 71 unsigned int event; 72 void *param; 73 }; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static struct workqueue_struct *mlx5_ib_event_wq; 80 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 81 static LIST_HEAD(mlx5_ib_dev_list); 82 /* 83 * This mutex should be held when accessing either of the above lists 84 */ 85 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 86 87 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 88 { 89 struct mlx5_ib_dev *dev; 90 91 mutex_lock(&mlx5_ib_multiport_mutex); 92 dev = mpi->ibdev; 93 mutex_unlock(&mlx5_ib_multiport_mutex); 94 return dev; 95 } 96 97 static enum rdma_link_layer 98 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 99 { 100 switch (port_type_cap) { 101 case MLX5_CAP_PORT_TYPE_IB: 102 return IB_LINK_LAYER_INFINIBAND; 103 case MLX5_CAP_PORT_TYPE_ETH: 104 return IB_LINK_LAYER_ETHERNET; 105 default: 106 return IB_LINK_LAYER_UNSPECIFIED; 107 } 108 } 109 110 static enum rdma_link_layer 111 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 112 { 113 struct mlx5_ib_dev *dev = to_mdev(device); 114 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 115 116 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 117 } 118 119 static int get_port_state(struct ib_device *ibdev, 120 u32 port_num, 121 enum ib_port_state *state) 122 { 123 struct ib_port_attr attr; 124 int ret; 125 126 memset(&attr, 0, sizeof(attr)); 127 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 128 if (!ret) 129 *state = attr.state; 130 return ret; 131 } 132 133 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 134 struct net_device *ndev, 135 struct net_device *upper, 136 u32 *port_num) 137 { 138 struct net_device *rep_ndev; 139 struct mlx5_ib_port *port; 140 int i; 141 142 for (i = 0; i < dev->num_ports; i++) { 143 port = &dev->port[i]; 144 if (!port->rep) 145 continue; 146 147 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 148 *port_num = i + 1; 149 return &port->roce; 150 } 151 152 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 153 continue; 154 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 155 if (rep_ndev && rep_ndev == ndev) { 156 dev_put(rep_ndev); 157 *port_num = i + 1; 158 return &port->roce; 159 } 160 161 dev_put(rep_ndev); 162 } 163 164 return NULL; 165 } 166 167 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 168 struct net_device *ndev, 169 struct net_device *upper, 170 struct net_device *ib_ndev) 171 { 172 if (!dev->ib_active) 173 return false; 174 175 /* Event is about our upper device */ 176 if (upper == ndev) 177 return true; 178 179 /* RDMA device is not in lag and not in switchdev */ 180 if (!dev->is_rep && !upper && ndev == ib_ndev) 181 return true; 182 183 /* RDMA devie is in switchdev */ 184 if (dev->is_rep && ndev == ib_ndev) 185 return true; 186 187 return false; 188 } 189 190 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 191 { 192 struct mlx5_ib_port *port; 193 int i; 194 195 for (i = 0; i < ibdev->num_ports; i++) { 196 port = &ibdev->port[i]; 197 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 198 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 199 } 200 } 201 202 return NULL; 203 } 204 205 static int mlx5_netdev_event(struct notifier_block *this, 206 unsigned long event, void *ptr) 207 { 208 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 209 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 210 u32 port_num = roce->native_port_num; 211 struct net_device *ib_ndev = NULL; 212 struct mlx5_core_dev *mdev; 213 struct mlx5_ib_dev *ibdev; 214 215 ibdev = roce->dev; 216 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 217 if (!mdev) 218 return NOTIFY_DONE; 219 220 switch (event) { 221 case NETDEV_REGISTER: 222 /* Should already be registered during the load */ 223 if (ibdev->is_rep) 224 break; 225 226 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 227 /* Exit if already registered */ 228 if (ib_ndev) 229 goto put_ndev; 230 231 if (ndev->dev.parent == mdev->device) 232 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 233 break; 234 235 case NETDEV_UNREGISTER: 236 /* In case of reps, ib device goes away before the netdevs */ 237 if (ibdev->is_rep) 238 break; 239 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 240 if (ib_ndev == ndev) 241 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 242 goto put_ndev; 243 244 case NETDEV_CHANGE: 245 case NETDEV_UP: 246 case NETDEV_DOWN: { 247 struct net_device *upper = NULL; 248 249 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 250 !mlx5_core_mp_enabled(mdev)) 251 return NOTIFY_DONE; 252 253 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 254 struct net_device *lag_ndev; 255 256 if(mlx5_lag_is_roce(mdev)) 257 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 258 else /* sriov lag */ 259 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 260 261 if (lag_ndev) { 262 upper = netdev_master_upper_dev_get(lag_ndev); 263 dev_put(lag_ndev); 264 } else { 265 goto done; 266 } 267 } 268 269 if (ibdev->is_rep) 270 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 271 if (!roce) 272 return NOTIFY_DONE; 273 274 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 275 276 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 277 struct ib_event ibev = { }; 278 enum ib_port_state port_state; 279 280 if (get_port_state(&ibdev->ib_dev, port_num, 281 &port_state)) 282 goto put_ndev; 283 284 if (roce->last_port_state == port_state) 285 goto put_ndev; 286 287 roce->last_port_state = port_state; 288 ibev.device = &ibdev->ib_dev; 289 if (port_state == IB_PORT_DOWN) 290 ibev.event = IB_EVENT_PORT_ERR; 291 else if (port_state == IB_PORT_ACTIVE) 292 ibev.event = IB_EVENT_PORT_ACTIVE; 293 else 294 goto put_ndev; 295 296 ibev.element.port_num = port_num; 297 ib_dispatch_event(&ibev); 298 } 299 break; 300 } 301 302 default: 303 break; 304 } 305 put_ndev: 306 dev_put(ib_ndev); 307 done: 308 mlx5_ib_put_native_port_mdev(ibdev, port_num); 309 return NOTIFY_DONE; 310 } 311 312 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 313 u32 ib_port_num, 314 u32 *native_port_num) 315 { 316 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 317 ib_port_num); 318 struct mlx5_core_dev *mdev = NULL; 319 struct mlx5_ib_multiport_info *mpi; 320 struct mlx5_ib_port *port; 321 322 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 323 if (native_port_num) 324 *native_port_num = smi_to_native_portnum(ibdev, 325 ib_port_num); 326 return ibdev->mdev; 327 328 } 329 330 if (!mlx5_core_mp_enabled(ibdev->mdev) || 331 ll != IB_LINK_LAYER_ETHERNET) { 332 if (native_port_num) 333 *native_port_num = ib_port_num; 334 return ibdev->mdev; 335 } 336 337 if (native_port_num) 338 *native_port_num = 1; 339 340 port = &ibdev->port[ib_port_num - 1]; 341 spin_lock(&port->mp.mpi_lock); 342 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 343 if (mpi && !mpi->unaffiliate) { 344 mdev = mpi->mdev; 345 /* If it's the master no need to refcount, it'll exist 346 * as long as the ib_dev exists. 347 */ 348 if (!mpi->is_master) 349 mpi->mdev_refcnt++; 350 } 351 spin_unlock(&port->mp.mpi_lock); 352 353 return mdev; 354 } 355 356 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 357 { 358 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 359 port_num); 360 struct mlx5_ib_multiport_info *mpi; 361 struct mlx5_ib_port *port; 362 363 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 364 return; 365 366 port = &ibdev->port[port_num - 1]; 367 368 spin_lock(&port->mp.mpi_lock); 369 mpi = ibdev->port[port_num - 1].mp.mpi; 370 if (mpi->is_master) 371 goto out; 372 373 mpi->mdev_refcnt--; 374 if (mpi->unaffiliate) 375 complete(&mpi->unref_comp); 376 out: 377 spin_unlock(&port->mp.mpi_lock); 378 } 379 380 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 381 u16 *active_speed, u8 *active_width) 382 { 383 switch (eth_proto_oper) { 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 385 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 386 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 397 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_QDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 403 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 416 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 417 *active_width = IB_WIDTH_1X; 418 *active_speed = IB_SPEED_HDR; 419 break; 420 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 421 *active_width = IB_WIDTH_4X; 422 *active_speed = IB_SPEED_FDR; 423 break; 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 427 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_EDR; 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 return 0; 436 } 437 438 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 439 u8 *active_width) 440 { 441 switch (eth_proto_oper) { 442 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 443 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 444 *active_width = IB_WIDTH_1X; 445 *active_speed = IB_SPEED_SDR; 446 break; 447 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 448 *active_width = IB_WIDTH_1X; 449 *active_speed = IB_SPEED_DDR; 450 break; 451 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 452 *active_width = IB_WIDTH_1X; 453 *active_speed = IB_SPEED_QDR; 454 break; 455 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 456 *active_width = IB_WIDTH_4X; 457 *active_speed = IB_SPEED_QDR; 458 break; 459 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 460 *active_width = IB_WIDTH_1X; 461 *active_speed = IB_SPEED_EDR; 462 break; 463 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 464 *active_width = IB_WIDTH_2X; 465 *active_speed = IB_SPEED_EDR; 466 break; 467 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 468 *active_width = IB_WIDTH_1X; 469 *active_speed = IB_SPEED_HDR; 470 break; 471 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 472 *active_width = IB_WIDTH_4X; 473 *active_speed = IB_SPEED_EDR; 474 break; 475 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 476 *active_width = IB_WIDTH_2X; 477 *active_speed = IB_SPEED_HDR; 478 break; 479 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 480 *active_width = IB_WIDTH_1X; 481 *active_speed = IB_SPEED_NDR; 482 break; 483 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 484 *active_width = IB_WIDTH_4X; 485 *active_speed = IB_SPEED_HDR; 486 break; 487 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 488 *active_width = IB_WIDTH_2X; 489 *active_speed = IB_SPEED_NDR; 490 break; 491 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 492 *active_width = IB_WIDTH_1X; 493 *active_speed = IB_SPEED_XDR; 494 break; 495 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 496 *active_width = IB_WIDTH_8X; 497 *active_speed = IB_SPEED_HDR; 498 break; 499 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 500 *active_width = IB_WIDTH_4X; 501 *active_speed = IB_SPEED_NDR; 502 break; 503 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 504 *active_width = IB_WIDTH_2X; 505 *active_speed = IB_SPEED_XDR; 506 break; 507 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 508 *active_width = IB_WIDTH_8X; 509 *active_speed = IB_SPEED_NDR; 510 break; 511 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 512 *active_width = IB_WIDTH_4X; 513 *active_speed = IB_SPEED_XDR; 514 break; 515 case MLX5E_PROT_MASK(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8): 516 *active_width = IB_WIDTH_8X; 517 *active_speed = IB_SPEED_XDR; 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 527 u8 *active_width, bool ext) 528 { 529 return ext ? 530 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 531 active_width) : 532 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 533 active_width); 534 } 535 536 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 537 struct ib_port_attr *props) 538 { 539 struct mlx5_ib_dev *dev = to_mdev(device); 540 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 541 struct mlx5_core_dev *mdev; 542 struct net_device *ndev, *upper; 543 enum ib_mtu ndev_ib_mtu; 544 bool put_mdev = true; 545 u32 eth_prot_oper; 546 u32 mdev_port_num; 547 bool ext; 548 int err; 549 550 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 551 if (!mdev) { 552 /* This means the port isn't affiliated yet. Get the 553 * info for the master port instead. 554 */ 555 put_mdev = false; 556 mdev = dev->mdev; 557 mdev_port_num = 1; 558 port_num = 1; 559 } 560 561 /* Possible bad flows are checked before filling out props so in case 562 * of an error it will still be zeroed out. 563 * Use native port in case of reps 564 */ 565 if (dev->is_rep) { 566 struct mlx5_eswitch_rep *rep; 567 568 rep = dev->port[port_num - 1].rep; 569 if (rep) { 570 mdev = mlx5_eswitch_get_core_dev(rep->esw); 571 WARN_ON(!mdev); 572 } 573 mdev_port_num = 1; 574 } 575 576 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 577 mdev_port_num, 0); 578 579 if (err) 580 goto out; 581 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 582 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 583 584 props->active_width = IB_WIDTH_4X; 585 props->active_speed = IB_SPEED_QDR; 586 587 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 588 &props->active_width, ext); 589 590 if (!dev->is_rep && dev->mdev->roce.roce_en) { 591 u16 qkey_viol_cntr; 592 593 props->port_cap_flags |= IB_PORT_CM_SUP; 594 props->ip_gids = true; 595 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 596 roce_address_table_size); 597 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 598 props->qkey_viol_cntr = qkey_viol_cntr; 599 } 600 props->max_mtu = IB_MTU_4096; 601 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 602 props->pkey_tbl_len = 1; 603 props->state = IB_PORT_DOWN; 604 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 605 606 /* If this is a stub query for an unaffiliated port stop here */ 607 if (!put_mdev) 608 goto out; 609 610 ndev = ib_device_get_netdev(device, port_num); 611 if (!ndev) 612 goto out; 613 614 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 615 rcu_read_lock(); 616 upper = netdev_master_upper_dev_get_rcu(ndev); 617 if (upper) { 618 dev_put(ndev); 619 ndev = upper; 620 dev_hold(ndev); 621 } 622 rcu_read_unlock(); 623 } 624 625 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 626 props->state = IB_PORT_ACTIVE; 627 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 628 } 629 630 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 631 632 dev_put(ndev); 633 634 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 635 out: 636 if (put_mdev) 637 mlx5_ib_put_native_port_mdev(dev, port_num); 638 return err; 639 } 640 641 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 642 unsigned int index, const union ib_gid *gid, 643 const struct ib_gid_attr *attr) 644 { 645 enum ib_gid_type gid_type; 646 u16 vlan_id = 0xffff; 647 u8 roce_version = 0; 648 u8 roce_l3_type = 0; 649 u8 mac[ETH_ALEN]; 650 int ret; 651 652 gid_type = attr->gid_type; 653 if (gid) { 654 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 655 if (ret) 656 return ret; 657 } 658 659 switch (gid_type) { 660 case IB_GID_TYPE_ROCE: 661 roce_version = MLX5_ROCE_VERSION_1; 662 break; 663 case IB_GID_TYPE_ROCE_UDP_ENCAP: 664 roce_version = MLX5_ROCE_VERSION_2; 665 if (gid && ipv6_addr_v4mapped((void *)gid)) 666 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 667 else 668 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 669 break; 670 671 default: 672 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 673 } 674 675 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 676 roce_l3_type, gid->raw, mac, 677 vlan_id < VLAN_CFI_MASK, vlan_id, 678 port_num); 679 } 680 681 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 682 __always_unused void **context) 683 { 684 int ret; 685 686 ret = mlx5r_add_gid_macsec_operations(attr); 687 if (ret) 688 return ret; 689 690 return set_roce_addr(to_mdev(attr->device), attr->port_num, 691 attr->index, &attr->gid, attr); 692 } 693 694 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 695 __always_unused void **context) 696 { 697 int ret; 698 699 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 700 attr->index, NULL, attr); 701 if (ret) 702 return ret; 703 704 mlx5r_del_gid_macsec_operations(attr); 705 return 0; 706 } 707 708 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 709 const struct ib_gid_attr *attr) 710 { 711 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 712 return 0; 713 714 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 715 } 716 717 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 718 { 719 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 720 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 721 return 0; 722 } 723 724 enum { 725 MLX5_VPORT_ACCESS_METHOD_MAD, 726 MLX5_VPORT_ACCESS_METHOD_HCA, 727 MLX5_VPORT_ACCESS_METHOD_NIC, 728 }; 729 730 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 731 { 732 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 733 return MLX5_VPORT_ACCESS_METHOD_MAD; 734 735 if (mlx5_ib_port_link_layer(ibdev, 1) == 736 IB_LINK_LAYER_ETHERNET) 737 return MLX5_VPORT_ACCESS_METHOD_NIC; 738 739 return MLX5_VPORT_ACCESS_METHOD_HCA; 740 } 741 742 static void get_atomic_caps(struct mlx5_ib_dev *dev, 743 u8 atomic_size_qp, 744 struct ib_device_attr *props) 745 { 746 u8 tmp; 747 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 748 u8 atomic_req_8B_endianness_mode = 749 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 750 751 /* Check if HW supports 8 bytes standard atomic operations and capable 752 * of host endianness respond 753 */ 754 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 755 if (((atomic_operations & tmp) == tmp) && 756 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 757 (atomic_req_8B_endianness_mode)) { 758 props->atomic_cap = IB_ATOMIC_HCA; 759 } else { 760 props->atomic_cap = IB_ATOMIC_NONE; 761 } 762 } 763 764 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 765 struct ib_device_attr *props) 766 { 767 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 768 769 get_atomic_caps(dev, atomic_size_qp, props); 770 } 771 772 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 773 __be64 *sys_image_guid) 774 { 775 struct mlx5_ib_dev *dev = to_mdev(ibdev); 776 struct mlx5_core_dev *mdev = dev->mdev; 777 u64 tmp; 778 int err; 779 780 switch (mlx5_get_vport_access_method(ibdev)) { 781 case MLX5_VPORT_ACCESS_METHOD_MAD: 782 return mlx5_query_mad_ifc_system_image_guid(ibdev, 783 sys_image_guid); 784 785 case MLX5_VPORT_ACCESS_METHOD_HCA: 786 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 787 break; 788 789 case MLX5_VPORT_ACCESS_METHOD_NIC: 790 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 791 break; 792 793 default: 794 return -EINVAL; 795 } 796 797 if (!err) 798 *sys_image_guid = cpu_to_be64(tmp); 799 800 return err; 801 802 } 803 804 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 805 u16 *max_pkeys) 806 { 807 struct mlx5_ib_dev *dev = to_mdev(ibdev); 808 struct mlx5_core_dev *mdev = dev->mdev; 809 810 switch (mlx5_get_vport_access_method(ibdev)) { 811 case MLX5_VPORT_ACCESS_METHOD_MAD: 812 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 813 814 case MLX5_VPORT_ACCESS_METHOD_HCA: 815 case MLX5_VPORT_ACCESS_METHOD_NIC: 816 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 817 pkey_table_size)); 818 return 0; 819 820 default: 821 return -EINVAL; 822 } 823 } 824 825 static int mlx5_query_vendor_id(struct ib_device *ibdev, 826 u32 *vendor_id) 827 { 828 struct mlx5_ib_dev *dev = to_mdev(ibdev); 829 830 switch (mlx5_get_vport_access_method(ibdev)) { 831 case MLX5_VPORT_ACCESS_METHOD_MAD: 832 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 833 834 case MLX5_VPORT_ACCESS_METHOD_HCA: 835 case MLX5_VPORT_ACCESS_METHOD_NIC: 836 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 837 838 default: 839 return -EINVAL; 840 } 841 } 842 843 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 844 __be64 *node_guid) 845 { 846 u64 tmp; 847 int err; 848 849 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 850 case MLX5_VPORT_ACCESS_METHOD_MAD: 851 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 852 853 case MLX5_VPORT_ACCESS_METHOD_HCA: 854 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 855 break; 856 857 case MLX5_VPORT_ACCESS_METHOD_NIC: 858 err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if (!err) 866 *node_guid = cpu_to_be64(tmp); 867 868 return err; 869 } 870 871 struct mlx5_reg_node_desc { 872 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 873 }; 874 875 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 876 { 877 struct mlx5_reg_node_desc in; 878 879 if (mlx5_use_mad_ifc(dev)) 880 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 881 882 memset(&in, 0, sizeof(in)); 883 884 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 885 sizeof(struct mlx5_reg_node_desc), 886 MLX5_REG_NODE_DESC, 0, 0); 887 } 888 889 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 890 struct mlx5_ib_query_device_resp *resp) 891 { 892 struct mlx5_eswitch *esw = mdev->priv.eswitch; 893 u16 vport = mlx5_eswitch_manager_vport(mdev); 894 895 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 896 vport); 897 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 898 } 899 900 /* 901 * Calculate maximum SQ overhead across all QP types. 902 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 903 * have smaller overhead than the types calculated below, 904 * so they are implicitly included. 905 */ 906 static u32 mlx5_ib_calc_max_sq_overhead(void) 907 { 908 u32 max_overhead_xrc, overhead_ud_lso, a, b; 909 910 /* XRC_INI */ 911 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 912 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 913 a = sizeof(struct mlx5_wqe_atomic_seg) + 914 sizeof(struct mlx5_wqe_raddr_seg); 915 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 916 sizeof(struct mlx5_mkey_seg) + 917 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 918 max_overhead_xrc += max(a, b); 919 920 /* UD with LSO */ 921 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 922 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 923 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 924 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 925 926 return max(max_overhead_xrc, overhead_ud_lso); 927 } 928 929 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 930 { 931 struct mlx5_core_dev *mdev = dev->mdev; 932 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 933 u32 max_wqe_size; 934 /* max QP overhead + 1 SGE, no inline, no special features */ 935 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 936 sizeof(struct mlx5_wqe_data_seg); 937 938 max_wqe_size = roundup_pow_of_two(max_wqe_size); 939 940 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 941 942 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 943 } 944 945 static int mlx5_ib_query_device(struct ib_device *ibdev, 946 struct ib_device_attr *props, 947 struct ib_udata *uhw) 948 { 949 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 950 struct mlx5_ib_dev *dev = to_mdev(ibdev); 951 struct mlx5_core_dev *mdev = dev->mdev; 952 int err = -ENOMEM; 953 int max_sq_desc; 954 int max_rq_sg; 955 int max_sq_sg; 956 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 957 bool raw_support = !mlx5_core_mp_enabled(mdev); 958 struct mlx5_ib_query_device_resp resp = {}; 959 size_t resp_len; 960 u64 max_tso; 961 962 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 963 if (uhw_outlen && uhw_outlen < resp_len) 964 return -EINVAL; 965 966 resp.response_length = resp_len; 967 968 err = ib_is_udata_in_empty(uhw); 969 if (err) 970 return err; 971 972 err = mlx5_query_system_image_guid(ibdev, 973 &props->sys_image_guid); 974 if (err) 975 return err; 976 977 props->max_pkeys = dev->pkey_table_len; 978 979 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 980 if (err) 981 return err; 982 983 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 984 (fw_rev_min(dev->mdev) << 16) | 985 fw_rev_sub(dev->mdev); 986 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 987 IB_DEVICE_PORT_ACTIVE_EVENT | 988 IB_DEVICE_SYS_IMAGE_GUID | 989 IB_DEVICE_RC_RNR_NAK_GEN; 990 991 if (MLX5_CAP_GEN(mdev, pkv)) 992 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 993 if (MLX5_CAP_GEN(mdev, qkv)) 994 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 995 if (MLX5_CAP_GEN(mdev, apm)) 996 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 997 if (MLX5_CAP_GEN(mdev, xrc)) 998 props->device_cap_flags |= IB_DEVICE_XRC; 999 if (MLX5_CAP_GEN(mdev, imaicl)) { 1000 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 1001 IB_DEVICE_MEM_WINDOW_TYPE_2B; 1002 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1003 /* We support 'Gappy' memory registration too */ 1004 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 1005 } 1006 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 1007 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1008 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 1009 if (MLX5_CAP_GEN(mdev, sho)) { 1010 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 1011 /* At this stage no support for signature handover */ 1012 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1013 IB_PROT_T10DIF_TYPE_2 | 1014 IB_PROT_T10DIF_TYPE_3; 1015 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1016 IB_GUARD_T10DIF_CSUM; 1017 } 1018 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1019 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1020 1021 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1022 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1023 /* Legacy bit to support old userspace libraries */ 1024 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1025 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1026 } 1027 1028 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1029 props->raw_packet_caps |= 1030 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1031 1032 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1033 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1034 if (max_tso) { 1035 resp.tso_caps.max_tso = 1 << max_tso; 1036 resp.tso_caps.supported_qpts |= 1037 1 << IB_QPT_RAW_PACKET; 1038 resp.response_length += sizeof(resp.tso_caps); 1039 } 1040 } 1041 1042 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1043 resp.rss_caps.rx_hash_function = 1044 MLX5_RX_HASH_FUNC_TOEPLITZ; 1045 resp.rss_caps.rx_hash_fields_mask = 1046 MLX5_RX_HASH_SRC_IPV4 | 1047 MLX5_RX_HASH_DST_IPV4 | 1048 MLX5_RX_HASH_SRC_IPV6 | 1049 MLX5_RX_HASH_DST_IPV6 | 1050 MLX5_RX_HASH_SRC_PORT_TCP | 1051 MLX5_RX_HASH_DST_PORT_TCP | 1052 MLX5_RX_HASH_SRC_PORT_UDP | 1053 MLX5_RX_HASH_DST_PORT_UDP | 1054 MLX5_RX_HASH_INNER; 1055 resp.response_length += sizeof(resp.rss_caps); 1056 } 1057 } else { 1058 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1059 resp.response_length += sizeof(resp.tso_caps); 1060 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1061 resp.response_length += sizeof(resp.rss_caps); 1062 } 1063 1064 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1065 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1066 props->kernel_cap_flags |= IBK_UD_TSO; 1067 } 1068 1069 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1070 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1071 raw_support) 1072 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1073 1074 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1075 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1076 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1077 1078 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1079 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1080 raw_support) { 1081 /* Legacy bit to support old userspace libraries */ 1082 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1083 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1084 } 1085 1086 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1087 props->max_dm_size = 1088 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1089 } 1090 1091 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1092 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1093 1094 if (MLX5_CAP_GEN(mdev, end_pad)) 1095 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1096 1097 props->vendor_part_id = mdev->pdev->device; 1098 props->hw_ver = mdev->pdev->revision; 1099 1100 props->max_mr_size = ~0ull; 1101 props->page_size_cap = ~(min_page_size - 1); 1102 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1103 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1104 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1105 sizeof(struct mlx5_wqe_data_seg); 1106 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1107 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1108 sizeof(struct mlx5_wqe_raddr_seg)) / 1109 sizeof(struct mlx5_wqe_data_seg); 1110 props->max_send_sge = max_sq_sg; 1111 props->max_recv_sge = max_rq_sg; 1112 props->max_sge_rd = MLX5_MAX_SGE_RD; 1113 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1114 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1115 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1116 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1117 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1118 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1119 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1120 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1121 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1122 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1123 props->max_srq_sge = max_rq_sg - 1; 1124 props->max_fast_reg_page_list_len = 1125 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1126 props->max_pi_fast_reg_page_list_len = 1127 props->max_fast_reg_page_list_len / 2; 1128 props->max_sgl_rd = 1129 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1130 get_atomic_caps_qp(dev, props); 1131 props->masked_atomic_cap = IB_ATOMIC_NONE; 1132 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1133 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1134 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1135 props->max_mcast_grp; 1136 props->max_ah = INT_MAX; 1137 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1138 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1139 1140 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1141 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1142 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1143 props->odp_caps = dev->odp_caps; 1144 if (!uhw) { 1145 /* ODP for kernel QPs is not implemented for receive 1146 * WQEs and SRQ WQEs 1147 */ 1148 props->odp_caps.per_transport_caps.rc_odp_caps &= 1149 ~(IB_ODP_SUPPORT_READ | 1150 IB_ODP_SUPPORT_SRQ_RECV); 1151 props->odp_caps.per_transport_caps.uc_odp_caps &= 1152 ~(IB_ODP_SUPPORT_READ | 1153 IB_ODP_SUPPORT_SRQ_RECV); 1154 props->odp_caps.per_transport_caps.ud_odp_caps &= 1155 ~(IB_ODP_SUPPORT_READ | 1156 IB_ODP_SUPPORT_SRQ_RECV); 1157 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1158 ~(IB_ODP_SUPPORT_READ | 1159 IB_ODP_SUPPORT_SRQ_RECV); 1160 } 1161 } 1162 1163 if (mlx5_core_is_vf(mdev)) 1164 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1165 1166 if (mlx5_ib_port_link_layer(ibdev, 1) == 1167 IB_LINK_LAYER_ETHERNET && raw_support) { 1168 props->rss_caps.max_rwq_indirection_tables = 1169 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1170 props->rss_caps.max_rwq_indirection_table_size = 1171 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1172 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1173 props->max_wq_type_rq = 1174 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1175 } 1176 1177 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1178 props->tm_caps.max_num_tags = 1179 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1180 props->tm_caps.max_ops = 1181 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1182 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1183 } 1184 1185 if (MLX5_CAP_GEN(mdev, tag_matching) && 1186 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1187 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1188 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1189 } 1190 1191 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1192 props->cq_caps.max_cq_moderation_count = 1193 MLX5_MAX_CQ_COUNT; 1194 props->cq_caps.max_cq_moderation_period = 1195 MLX5_MAX_CQ_PERIOD; 1196 } 1197 1198 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1199 resp.response_length += sizeof(resp.cqe_comp_caps); 1200 1201 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1202 resp.cqe_comp_caps.max_num = 1203 MLX5_CAP_GEN(dev->mdev, 1204 cqe_compression_max_num); 1205 1206 resp.cqe_comp_caps.supported_format = 1207 MLX5_IB_CQE_RES_FORMAT_HASH | 1208 MLX5_IB_CQE_RES_FORMAT_CSUM; 1209 1210 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1211 resp.cqe_comp_caps.supported_format |= 1212 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1213 } 1214 } 1215 1216 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen) { 1217 if (MLX5_CAP_GEN(mdev, qos)) { 1218 if (MLX5_CAP_QOS(mdev, packet_pacing) && raw_support) 1219 resp.packet_pacing_caps.supported_qpts |= 1220 BIT(IB_QPT_RAW_PACKET); 1221 if (MLX5_CAP_QOS(mdev, packet_pacing_req_ud)) 1222 resp.packet_pacing_caps.supported_qpts |= 1223 BIT(IB_QPT_UD); 1224 if (MLX5_CAP_QOS(mdev, packet_pacing_req_uc)) 1225 resp.packet_pacing_caps.supported_qpts |= 1226 BIT(IB_QPT_UC); 1227 1228 if (resp.packet_pacing_caps.supported_qpts) { 1229 resp.packet_pacing_caps.qp_rate_limit_max = 1230 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1231 resp.packet_pacing_caps.qp_rate_limit_min = 1232 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1233 1234 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1235 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1236 resp.packet_pacing_caps.cap_flags |= 1237 MLX5_IB_PP_SUPPORT_BURST; 1238 } 1239 } 1240 resp.response_length += sizeof(resp.packet_pacing_caps); 1241 } 1242 1243 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1244 uhw_outlen) { 1245 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1246 resp.mlx5_ib_support_multi_pkt_send_wqes = 1247 MLX5_IB_ALLOW_MPW; 1248 1249 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1250 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1251 MLX5_IB_SUPPORT_EMPW; 1252 1253 resp.response_length += 1254 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1255 } 1256 1257 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1258 resp.response_length += sizeof(resp.flags); 1259 1260 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1261 resp.flags |= 1262 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1263 1264 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1265 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1266 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1267 resp.flags |= 1268 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1269 1270 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1271 1272 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1273 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1274 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1275 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1276 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1277 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1278 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1279 } 1280 1281 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1282 resp.response_length += sizeof(resp.sw_parsing_caps); 1283 if (MLX5_CAP_ETH(mdev, swp)) { 1284 resp.sw_parsing_caps.sw_parsing_offloads |= 1285 MLX5_IB_SW_PARSING; 1286 1287 if (MLX5_CAP_ETH(mdev, swp_csum)) 1288 resp.sw_parsing_caps.sw_parsing_offloads |= 1289 MLX5_IB_SW_PARSING_CSUM; 1290 1291 if (MLX5_CAP_ETH(mdev, swp_lso)) 1292 resp.sw_parsing_caps.sw_parsing_offloads |= 1293 MLX5_IB_SW_PARSING_LSO; 1294 1295 if (resp.sw_parsing_caps.sw_parsing_offloads) 1296 resp.sw_parsing_caps.supported_qpts = 1297 BIT(IB_QPT_RAW_PACKET); 1298 } 1299 } 1300 1301 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1302 raw_support) { 1303 resp.response_length += sizeof(resp.striding_rq_caps); 1304 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1305 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1306 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1307 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1308 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1309 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1310 resp.striding_rq_caps 1311 .min_single_wqe_log_num_of_strides = 1312 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1313 else 1314 resp.striding_rq_caps 1315 .min_single_wqe_log_num_of_strides = 1316 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1317 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1318 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1319 resp.striding_rq_caps.supported_qpts = 1320 BIT(IB_QPT_RAW_PACKET); 1321 } 1322 } 1323 1324 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1325 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1326 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1327 resp.tunnel_offloads_caps |= 1328 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1329 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1330 resp.tunnel_offloads_caps |= 1331 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1332 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1333 resp.tunnel_offloads_caps |= 1334 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1335 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1336 resp.tunnel_offloads_caps |= 1337 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1338 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1339 resp.tunnel_offloads_caps |= 1340 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1341 } 1342 1343 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1344 resp.response_length += sizeof(resp.dci_streams_caps); 1345 1346 resp.dci_streams_caps.max_log_num_concurent = 1347 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1348 1349 resp.dci_streams_caps.max_log_num_errored = 1350 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1351 } 1352 1353 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1354 resp.response_length += sizeof(resp.reserved); 1355 1356 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1357 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1358 1359 resp.response_length += sizeof(resp.reg_c0); 1360 1361 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1362 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1363 fill_esw_mgr_reg_c0(mdev, &resp); 1364 } 1365 1366 if (uhw_outlen) { 1367 err = ib_respond_udata(uhw, resp); 1368 1369 if (err) 1370 return err; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1377 u8 *ib_width) 1378 { 1379 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1380 1381 if (active_width & MLX5_PTYS_WIDTH_1X) 1382 *ib_width = IB_WIDTH_1X; 1383 else if (active_width & MLX5_PTYS_WIDTH_2X) 1384 *ib_width = IB_WIDTH_2X; 1385 else if (active_width & MLX5_PTYS_WIDTH_4X) 1386 *ib_width = IB_WIDTH_4X; 1387 else if (active_width & MLX5_PTYS_WIDTH_8X) 1388 *ib_width = IB_WIDTH_8X; 1389 else if (active_width & MLX5_PTYS_WIDTH_12X) 1390 *ib_width = IB_WIDTH_12X; 1391 else { 1392 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1393 active_width); 1394 *ib_width = IB_WIDTH_4X; 1395 } 1396 1397 return; 1398 } 1399 1400 static int mlx5_mtu_to_ib_mtu(int mtu) 1401 { 1402 switch (mtu) { 1403 case 256: return 1; 1404 case 512: return 2; 1405 case 1024: return 3; 1406 case 2048: return 4; 1407 case 4096: return 5; 1408 default: 1409 pr_warn("invalid mtu\n"); 1410 return -1; 1411 } 1412 } 1413 1414 enum ib_max_vl_num { 1415 __IB_MAX_VL_0 = 1, 1416 __IB_MAX_VL_0_1 = 2, 1417 __IB_MAX_VL_0_3 = 3, 1418 __IB_MAX_VL_0_7 = 4, 1419 __IB_MAX_VL_0_14 = 5, 1420 }; 1421 1422 enum mlx5_vl_hw_cap { 1423 MLX5_VL_HW_0 = 1, 1424 MLX5_VL_HW_0_1 = 2, 1425 MLX5_VL_HW_0_2 = 3, 1426 MLX5_VL_HW_0_3 = 4, 1427 MLX5_VL_HW_0_4 = 5, 1428 MLX5_VL_HW_0_5 = 6, 1429 MLX5_VL_HW_0_6 = 7, 1430 MLX5_VL_HW_0_7 = 8, 1431 MLX5_VL_HW_0_14 = 15 1432 }; 1433 1434 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1435 u8 *max_vl_num) 1436 { 1437 switch (vl_hw_cap) { 1438 case MLX5_VL_HW_0: 1439 *max_vl_num = __IB_MAX_VL_0; 1440 break; 1441 case MLX5_VL_HW_0_1: 1442 *max_vl_num = __IB_MAX_VL_0_1; 1443 break; 1444 case MLX5_VL_HW_0_3: 1445 *max_vl_num = __IB_MAX_VL_0_3; 1446 break; 1447 case MLX5_VL_HW_0_7: 1448 *max_vl_num = __IB_MAX_VL_0_7; 1449 break; 1450 case MLX5_VL_HW_0_14: 1451 *max_vl_num = __IB_MAX_VL_0_14; 1452 break; 1453 1454 default: 1455 return -EINVAL; 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1462 struct ib_port_attr *props) 1463 { 1464 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1465 struct mlx5_core_dev *mdev = dev->mdev; 1466 struct mlx5_hca_vport_context *rep; 1467 u8 vl_hw_cap, plane_index = 0; 1468 u16 max_mtu; 1469 u16 oper_mtu; 1470 int err; 1471 u16 ib_link_width_oper; 1472 1473 rep = kzalloc_obj(*rep); 1474 if (!rep) { 1475 err = -ENOMEM; 1476 goto out; 1477 } 1478 1479 /* props being zeroed by the caller, avoid zeroing it here */ 1480 1481 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1482 plane_index = port; 1483 port = smi_to_native_portnum(dev, port); 1484 } 1485 1486 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1487 if (err) 1488 goto out; 1489 1490 props->lid = rep->lid; 1491 props->lmc = rep->lmc; 1492 props->sm_lid = rep->sm_lid; 1493 props->sm_sl = rep->sm_sl; 1494 props->state = rep->vport_state; 1495 props->phys_state = rep->port_physical_state; 1496 1497 props->port_cap_flags = rep->cap_mask1; 1498 if (dev->num_plane) { 1499 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1500 props->port_cap_flags &= ~IB_PORT_SM; 1501 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1502 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1503 1504 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1505 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1506 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1507 props->bad_pkey_cntr = rep->pkey_violation_counter; 1508 props->qkey_viol_cntr = rep->qkey_violation_counter; 1509 props->subnet_timeout = rep->subnet_timeout; 1510 props->init_type_reply = rep->init_type_reply; 1511 1512 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1513 props->port_cap_flags2 = rep->cap_mask2; 1514 1515 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1516 &props->active_speed, port, plane_index); 1517 if (err) 1518 goto out; 1519 1520 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1521 1522 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1523 1524 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1525 1526 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1527 1528 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1529 1530 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1531 if (err) 1532 goto out; 1533 1534 err = translate_max_vl_num(ibdev, vl_hw_cap, 1535 &props->max_vl_num); 1536 out: 1537 kfree(rep); 1538 return err; 1539 } 1540 1541 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1542 struct ib_port_attr *props) 1543 { 1544 unsigned int count; 1545 int ret; 1546 1547 switch (mlx5_get_vport_access_method(ibdev)) { 1548 case MLX5_VPORT_ACCESS_METHOD_MAD: 1549 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1550 break; 1551 1552 case MLX5_VPORT_ACCESS_METHOD_HCA: 1553 ret = mlx5_query_hca_port(ibdev, port, props); 1554 break; 1555 1556 case MLX5_VPORT_ACCESS_METHOD_NIC: 1557 ret = mlx5_query_port_roce(ibdev, port, props); 1558 break; 1559 1560 default: 1561 ret = -EINVAL; 1562 } 1563 1564 if (!ret && props) { 1565 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1566 struct mlx5_core_dev *mdev; 1567 bool put_mdev = true; 1568 1569 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1570 if (!mdev) { 1571 /* If the port isn't affiliated yet query the master. 1572 * The master and slave will have the same values. 1573 */ 1574 mdev = dev->mdev; 1575 port = 1; 1576 put_mdev = false; 1577 } 1578 count = mlx5_core_reserved_gids_count(mdev); 1579 if (put_mdev) 1580 mlx5_ib_put_native_port_mdev(dev, port); 1581 props->gid_tbl_len -= count; 1582 } 1583 return ret; 1584 } 1585 1586 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1587 struct ib_port_attr *props) 1588 { 1589 return mlx5_query_port_roce(ibdev, port, props); 1590 } 1591 1592 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1593 u16 *pkey) 1594 { 1595 /* Default special Pkey for representor device port as per the 1596 * IB specification 1.3 section 10.9.1.2. 1597 */ 1598 *pkey = 0xffff; 1599 return 0; 1600 } 1601 1602 static int mlx5_ib_query_port_speed_from_port(struct mlx5_ib_dev *dev, 1603 u32 port_num, u64 *speed) 1604 { 1605 struct ib_port_speed_info speed_info; 1606 struct ib_port_attr attr = {}; 1607 int err; 1608 1609 err = mlx5_ib_query_port(&dev->ib_dev, port_num, &attr); 1610 if (err) 1611 return err; 1612 1613 if (attr.state == IB_PORT_DOWN) { 1614 *speed = 0; 1615 return 0; 1616 } 1617 1618 err = ib_port_attr_to_speed_info(&attr, &speed_info); 1619 if (err) 1620 return err; 1621 1622 *speed = speed_info.rate; 1623 return 0; 1624 } 1625 1626 static int mlx5_ib_query_port_speed_from_vport(struct mlx5_core_dev *mdev, 1627 u8 op_mod, u16 vport, 1628 u8 other_vport, u64 *speed, 1629 struct mlx5_ib_dev *dev, 1630 u32 port_num) 1631 { 1632 u32 max_tx_speed; 1633 int err; 1634 1635 err = mlx5_query_vport_max_tx_speed(mdev, op_mod, vport, other_vport, 1636 &max_tx_speed); 1637 if (err) 1638 return err; 1639 1640 if (max_tx_speed == 0) 1641 /* Value 0 indicates field not supported, fallback */ 1642 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1643 speed); 1644 1645 *speed = max_tx_speed; 1646 return 0; 1647 } 1648 1649 static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, 1650 u32 port_num, u64 *speed) 1651 { 1652 struct mlx5_core_dev *mdev = dev->mdev; 1653 u32 bond_speed; 1654 int err; 1655 1656 err = mlx5_lag_query_bond_speed(mdev, &bond_speed); 1657 if (err) 1658 return err; 1659 1660 *speed = bond_speed / MLX5_MAX_TX_SPEED_UNIT; 1661 1662 return 0; 1663 } 1664 1665 static int mlx5_ib_query_port_speed_non_rep(struct mlx5_ib_dev *dev, 1666 u32 port_num, u64 *speed) 1667 { 1668 u16 op_mod = MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT; 1669 1670 if (mlx5_lag_is_roce(dev->mdev)) 1671 return mlx5_ib_query_port_speed_from_bond(dev, port_num, 1672 speed); 1673 1674 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 0, false, 1675 speed, dev, port_num); 1676 } 1677 1678 static int mlx5_ib_query_port_speed_rep(struct mlx5_ib_dev *dev, u32 port_num, 1679 u64 *speed) 1680 { 1681 struct mlx5_eswitch_rep *rep; 1682 struct mlx5_core_dev *mdev; 1683 u16 op_mod; 1684 1685 if (!dev->port[port_num - 1].rep) { 1686 mlx5_ib_warn(dev, "Representor doesn't exist for port %u\n", 1687 port_num); 1688 return -EINVAL; 1689 } 1690 1691 rep = dev->port[port_num - 1].rep; 1692 mdev = mlx5_eswitch_get_core_dev(rep->esw); 1693 if (!mdev) 1694 return -ENODEV; 1695 1696 if (rep->vport == MLX5_VPORT_UPLINK) { 1697 if (mlx5_lag_is_sriov(mdev)) 1698 return mlx5_ib_query_port_speed_from_bond(dev, 1699 port_num, 1700 speed); 1701 1702 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1703 speed); 1704 } 1705 1706 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; 1707 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 1708 rep->vport, true, speed, dev, 1709 port_num); 1710 } 1711 1712 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, u64 *speed) 1713 { 1714 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1715 1716 if (mlx5_ib_port_link_layer(ibdev, port_num) == 1717 IB_LINK_LAYER_INFINIBAND || mlx5_core_mp_enabled(dev->mdev)) 1718 return mlx5_ib_query_port_speed_from_port(dev, port_num, speed); 1719 else if (!dev->is_rep) 1720 return mlx5_ib_query_port_speed_non_rep(dev, port_num, speed); 1721 else 1722 return mlx5_ib_query_port_speed_rep(dev, port_num, speed); 1723 } 1724 1725 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1726 union ib_gid *gid) 1727 { 1728 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1729 struct mlx5_core_dev *mdev = dev->mdev; 1730 1731 switch (mlx5_get_vport_access_method(ibdev)) { 1732 case MLX5_VPORT_ACCESS_METHOD_MAD: 1733 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1734 1735 case MLX5_VPORT_ACCESS_METHOD_HCA: 1736 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1737 1738 default: 1739 return -EINVAL; 1740 } 1741 1742 } 1743 1744 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1745 u16 index, u16 *pkey) 1746 { 1747 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1748 struct mlx5_core_dev *mdev; 1749 bool put_mdev = true; 1750 u32 mdev_port_num; 1751 int err; 1752 1753 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1754 if (!mdev) { 1755 /* The port isn't affiliated yet, get the PKey from the master 1756 * port. For RoCE the PKey tables will be the same. 1757 */ 1758 put_mdev = false; 1759 mdev = dev->mdev; 1760 mdev_port_num = 1; 1761 } 1762 1763 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1764 index, pkey); 1765 if (put_mdev) 1766 mlx5_ib_put_native_port_mdev(dev, port); 1767 1768 return err; 1769 } 1770 1771 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1772 u16 *pkey) 1773 { 1774 switch (mlx5_get_vport_access_method(ibdev)) { 1775 case MLX5_VPORT_ACCESS_METHOD_MAD: 1776 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1777 1778 case MLX5_VPORT_ACCESS_METHOD_HCA: 1779 case MLX5_VPORT_ACCESS_METHOD_NIC: 1780 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1781 default: 1782 return -EINVAL; 1783 } 1784 } 1785 1786 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1787 struct ib_device_modify *props) 1788 { 1789 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1790 struct mlx5_reg_node_desc in; 1791 struct mlx5_reg_node_desc out; 1792 int err; 1793 1794 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1795 return -EOPNOTSUPP; 1796 1797 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1798 return 0; 1799 1800 /* 1801 * If possible, pass node desc to FW, so it can generate 1802 * a 144 trap. If cmd fails, just ignore. 1803 */ 1804 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1805 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1806 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1807 if (err) 1808 return err; 1809 1810 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1811 1812 return err; 1813 } 1814 1815 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1816 u32 value) 1817 { 1818 struct mlx5_hca_vport_context ctx = {}; 1819 struct mlx5_core_dev *mdev; 1820 u32 mdev_port_num; 1821 int err; 1822 1823 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1824 if (!mdev) 1825 return -ENODEV; 1826 1827 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1828 if (err) 1829 goto out; 1830 1831 if (~ctx.cap_mask1_perm & mask) { 1832 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1833 mask, ctx.cap_mask1_perm); 1834 err = -EINVAL; 1835 goto out; 1836 } 1837 1838 ctx.cap_mask1 = value; 1839 ctx.cap_mask1_perm = mask; 1840 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1841 0, &ctx); 1842 1843 out: 1844 mlx5_ib_put_native_port_mdev(dev, port_num); 1845 1846 return err; 1847 } 1848 1849 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1850 struct ib_port_modify *props) 1851 { 1852 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1853 struct ib_port_attr attr; 1854 u32 tmp; 1855 int err; 1856 u32 change_mask; 1857 u32 value; 1858 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1859 IB_LINK_LAYER_INFINIBAND); 1860 1861 /* CM layer calls ib_modify_port() regardless of the link layer. For 1862 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1863 */ 1864 if (!is_ib) 1865 return 0; 1866 1867 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1868 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1869 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1870 return set_port_caps_atomic(dev, port, change_mask, value); 1871 } 1872 1873 mutex_lock(&dev->cap_mask_mutex); 1874 1875 err = ib_query_port(ibdev, port, &attr); 1876 if (err) 1877 goto out; 1878 1879 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1880 ~props->clr_port_cap_mask; 1881 1882 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1883 1884 out: 1885 mutex_unlock(&dev->cap_mask_mutex); 1886 return err; 1887 } 1888 1889 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1890 { 1891 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1892 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1893 } 1894 1895 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1896 { 1897 /* Large page with non 4k uar support might limit the dynamic size */ 1898 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1899 return MLX5_MIN_DYN_BFREGS; 1900 1901 return MLX5_MAX_DYN_BFREGS; 1902 } 1903 1904 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1905 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1906 struct mlx5_bfreg_info *bfregi) 1907 { 1908 int uars_per_sys_page; 1909 int bfregs_per_sys_page; 1910 int ref_bfregs = req->total_num_bfregs; 1911 1912 if (req->total_num_bfregs == 0) 1913 return -EINVAL; 1914 1915 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1916 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1917 1918 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1919 return -ENOMEM; 1920 1921 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1922 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1923 /* This holds the required static allocation asked by the user */ 1924 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1925 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1926 return -EINVAL; 1927 1928 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1929 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1930 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1931 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1932 1933 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1934 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1935 lib_uar_4k ? "yes" : "no", ref_bfregs, 1936 req->total_num_bfregs, bfregi->total_num_bfregs, 1937 bfregi->num_sys_pages); 1938 1939 return 0; 1940 } 1941 1942 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1943 { 1944 struct mlx5_bfreg_info *bfregi; 1945 int err; 1946 int i; 1947 1948 bfregi = &context->bfregi; 1949 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1950 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1951 context->devx_uid); 1952 if (err) 1953 goto error; 1954 1955 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1956 } 1957 1958 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1959 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1960 1961 return 0; 1962 1963 error: 1964 for (--i; i >= 0; i--) 1965 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1966 context->devx_uid)) 1967 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1968 1969 return err; 1970 } 1971 1972 static void deallocate_uars(struct mlx5_ib_dev *dev, 1973 struct mlx5_ib_ucontext *context) 1974 { 1975 struct mlx5_bfreg_info *bfregi; 1976 int i; 1977 1978 bfregi = &context->bfregi; 1979 for (i = 0; i < bfregi->num_sys_pages; i++) 1980 if (i < bfregi->num_static_sys_pages || 1981 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1982 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1983 context->devx_uid); 1984 } 1985 1986 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1987 struct mlx5_core_dev *slave, 1988 struct mlx5_ib_lb_state *lb_state) 1989 { 1990 int err; 1991 1992 err = mlx5_nic_vport_update_local_lb(master, true); 1993 if (err) 1994 return err; 1995 1996 err = mlx5_nic_vport_update_local_lb(slave, true); 1997 if (err) 1998 goto out; 1999 2000 lb_state->force_enable = true; 2001 return 0; 2002 2003 out: 2004 mlx5_nic_vport_update_local_lb(master, false); 2005 return err; 2006 } 2007 2008 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 2009 struct mlx5_core_dev *slave, 2010 struct mlx5_ib_lb_state *lb_state) 2011 { 2012 mlx5_nic_vport_update_local_lb(slave, false); 2013 mlx5_nic_vport_update_local_lb(master, false); 2014 2015 lb_state->force_enable = false; 2016 } 2017 2018 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2019 { 2020 int err = 0; 2021 2022 if (dev->lb.force_enable) 2023 return 0; 2024 2025 mutex_lock(&dev->lb.mutex); 2026 if (td) 2027 dev->lb.user_td++; 2028 if (qp) 2029 dev->lb.qps++; 2030 2031 if (dev->lb.user_td == 2 || 2032 dev->lb.qps == 1) { 2033 if (!dev->lb.enabled) { 2034 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 2035 if (err) 2036 goto err_rollback; 2037 2038 dev->lb.enabled = true; 2039 } 2040 } 2041 2042 mutex_unlock(&dev->lb.mutex); 2043 2044 return err; 2045 2046 err_rollback: 2047 if (td) 2048 dev->lb.user_td--; 2049 if (qp) 2050 dev->lb.qps--; 2051 mutex_unlock(&dev->lb.mutex); 2052 return err; 2053 } 2054 2055 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2056 { 2057 if (dev->lb.force_enable) 2058 return; 2059 2060 mutex_lock(&dev->lb.mutex); 2061 if (td) 2062 dev->lb.user_td--; 2063 if (qp) 2064 dev->lb.qps--; 2065 2066 if (dev->lb.user_td == 1 && 2067 dev->lb.qps == 0) { 2068 if (dev->lb.enabled) { 2069 mlx5_nic_vport_update_local_lb(dev->mdev, false); 2070 dev->lb.enabled = false; 2071 } 2072 } 2073 2074 mutex_unlock(&dev->lb.mutex); 2075 } 2076 2077 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 2078 u16 uid) 2079 { 2080 int err; 2081 2082 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2083 return 0; 2084 2085 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 2086 if (err) 2087 return err; 2088 2089 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2090 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2091 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2092 return 0; 2093 2094 err = mlx5_ib_enable_lb(dev, true, false); 2095 if (err) 2096 mlx5_cmd_dealloc_transport_domain(dev->mdev, *tdn, uid); 2097 2098 return err; 2099 } 2100 2101 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 2102 u16 uid) 2103 { 2104 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2105 return; 2106 2107 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 2108 2109 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2110 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2111 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2112 return; 2113 2114 mlx5_ib_disable_lb(dev, true, false); 2115 } 2116 2117 static int set_ucontext_resp(struct ib_ucontext *uctx, 2118 struct mlx5_ib_alloc_ucontext_resp *resp) 2119 { 2120 struct ib_device *ibdev = uctx->device; 2121 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2122 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2123 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2124 2125 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 2126 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 2127 resp->comp_mask |= 2128 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 2129 } 2130 2131 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 2132 if (mlx5_wc_support_get(dev->mdev)) 2133 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 2134 log_bf_reg_size); 2135 resp->cache_line_size = cache_line_size(); 2136 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 2137 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 2138 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2139 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2140 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 2141 resp->cqe_version = context->cqe_version; 2142 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2143 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 2144 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2145 MLX5_CAP_GEN(dev->mdev, 2146 num_of_uars_per_page) : 1; 2147 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 2148 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 2149 resp->num_ports = dev->num_ports; 2150 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 2151 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 2152 2153 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 2154 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 2155 resp->eth_min_inline++; 2156 } 2157 2158 if (dev->mdev->clock_info) 2159 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2160 2161 /* 2162 * We don't want to expose information from the PCI bar that is located 2163 * after 4096 bytes, so if the arch only supports larger pages, let's 2164 * pretend we don't support reading the HCA's core clock. This is also 2165 * forced by mmap function. 2166 */ 2167 if (PAGE_SIZE <= 4096) { 2168 resp->comp_mask |= 2169 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2170 resp->hca_core_clock_offset = 2171 offsetof(struct mlx5_init_seg, 2172 internal_timer_h) % PAGE_SIZE; 2173 } 2174 2175 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2176 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2177 2178 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2179 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2180 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2181 resp->comp_mask |= 2182 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2183 2184 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2185 2186 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2187 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2188 2189 resp->comp_mask |= 2190 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2191 2192 return 0; 2193 } 2194 2195 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2196 { 2197 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2198 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2199 } 2200 2201 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2202 struct ib_udata *udata) 2203 { 2204 struct ib_device *ibdev = uctx->device; 2205 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2206 struct mlx5_ib_alloc_ucontext_req_v2 req; 2207 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2208 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2209 struct mlx5_bfreg_info *bfregi; 2210 int ver; 2211 int err; 2212 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2213 max_cqe_version); 2214 bool lib_uar_4k; 2215 bool lib_uar_dyn; 2216 2217 if (!dev->ib_active) 2218 return -EAGAIN; 2219 2220 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2221 ver = 0; 2222 else if (udata->inlen >= min_req_v2) 2223 ver = 2; 2224 else 2225 return -EINVAL; 2226 2227 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2228 if (err) 2229 return err; 2230 2231 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2232 return -EOPNOTSUPP; 2233 2234 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2235 return -EOPNOTSUPP; 2236 2237 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2238 MLX5_NON_FP_BFREGS_PER_UAR); 2239 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2240 return -EINVAL; 2241 2242 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2243 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2244 if (err < 0) 2245 goto out_ctx; 2246 context->devx_uid = err; 2247 2248 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2249 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2250 context->devx_uid); 2251 if (err) 2252 goto out_devx; 2253 } 2254 } 2255 2256 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2257 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2258 bfregi = &context->bfregi; 2259 2260 if (lib_uar_dyn) { 2261 bfregi->lib_uar_dyn = lib_uar_dyn; 2262 goto uar_done; 2263 } 2264 2265 /* updates req->total_num_bfregs */ 2266 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2267 if (err) 2268 goto out_ucap; 2269 2270 mutex_init(&bfregi->lock); 2271 bfregi->lib_uar_4k = lib_uar_4k; 2272 bfregi->count = kzalloc_objs(*bfregi->count, bfregi->total_num_bfregs); 2273 if (!bfregi->count) { 2274 err = -ENOMEM; 2275 goto out_ucap; 2276 } 2277 2278 bfregi->sys_pages = 2279 kzalloc_objs(*bfregi->sys_pages, bfregi->num_sys_pages); 2280 if (!bfregi->sys_pages) { 2281 err = -ENOMEM; 2282 goto out_count; 2283 } 2284 2285 err = allocate_uars(dev, context); 2286 if (err) 2287 goto out_sys_pages; 2288 2289 uar_done: 2290 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2291 context->devx_uid); 2292 if (err) 2293 goto out_uars; 2294 2295 INIT_LIST_HEAD(&context->db_page_list); 2296 mutex_init(&context->db_page_mutex); 2297 2298 context->cqe_version = min_t(__u8, 2299 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2300 req.max_cqe_version); 2301 2302 err = set_ucontext_resp(uctx, &resp); 2303 if (err) 2304 goto out_mdev; 2305 2306 resp.response_length = min(udata->outlen, sizeof(resp)); 2307 err = ib_respond_udata(udata, resp); 2308 if (err) 2309 goto out_mdev; 2310 2311 bfregi->ver = ver; 2312 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2313 context->lib_caps = req.lib_caps; 2314 print_lib_caps(dev, context->lib_caps); 2315 2316 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2317 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2318 2319 atomic_set(&context->tx_port_affinity, 2320 atomic_add_return( 2321 1, &dev->port[port].roce.tx_port_affinity)); 2322 } 2323 2324 return 0; 2325 2326 out_mdev: 2327 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2328 2329 out_uars: 2330 deallocate_uars(dev, context); 2331 2332 out_sys_pages: 2333 kfree(bfregi->sys_pages); 2334 2335 out_count: 2336 kfree(bfregi->count); 2337 2338 out_ucap: 2339 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2340 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2341 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2342 2343 out_devx: 2344 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2345 mlx5_ib_devx_destroy(dev, context->devx_uid); 2346 2347 out_ctx: 2348 return err; 2349 } 2350 2351 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2352 struct uverbs_attr_bundle *attrs) 2353 { 2354 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2355 int ret; 2356 2357 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2358 if (ret) 2359 return ret; 2360 2361 uctx_resp.response_length = 2362 min_t(size_t, 2363 uverbs_attr_get_len(attrs, 2364 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2365 sizeof(uctx_resp)); 2366 2367 ret = uverbs_copy_to_struct_or_zero(attrs, 2368 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2369 &uctx_resp, 2370 sizeof(uctx_resp)); 2371 return ret; 2372 } 2373 2374 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2375 { 2376 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2377 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2378 struct mlx5_bfreg_info *bfregi; 2379 2380 bfregi = &context->bfregi; 2381 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2382 2383 deallocate_uars(dev, context); 2384 kfree(bfregi->sys_pages); 2385 kfree(bfregi->count); 2386 2387 if (context->devx_uid) { 2388 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2389 mlx5_cmd_remove_privileged_uid(dev->mdev, 2390 context->devx_uid); 2391 mlx5_ib_devx_destroy(dev, context->devx_uid); 2392 } 2393 } 2394 2395 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2396 int uar_idx) 2397 { 2398 int fw_uars_per_page; 2399 2400 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2401 2402 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2403 } 2404 2405 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2406 int uar_idx) 2407 { 2408 unsigned int fw_uars_per_page; 2409 2410 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2411 MLX5_UARS_IN_PAGE : 1; 2412 2413 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2414 } 2415 2416 static int get_command(unsigned long offset) 2417 { 2418 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2419 } 2420 2421 static int get_arg(unsigned long offset) 2422 { 2423 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2424 } 2425 2426 static int get_index(unsigned long offset) 2427 { 2428 return get_arg(offset); 2429 } 2430 2431 /* Index resides in an extra byte to enable larger values than 255 */ 2432 static int get_extended_index(unsigned long offset) 2433 { 2434 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2435 } 2436 2437 2438 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2439 { 2440 } 2441 2442 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2443 { 2444 switch (cmd) { 2445 case MLX5_IB_MMAP_WC_PAGE: 2446 return "WC"; 2447 case MLX5_IB_MMAP_REGULAR_PAGE: 2448 return "best effort WC"; 2449 case MLX5_IB_MMAP_NC_PAGE: 2450 return "NC"; 2451 case MLX5_IB_MMAP_DEVICE_MEM: 2452 return "Device Memory"; 2453 default: 2454 return "Unknown"; 2455 } 2456 } 2457 2458 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2459 struct vm_area_struct *vma, 2460 struct mlx5_ib_ucontext *context) 2461 { 2462 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2463 !(vma->vm_flags & VM_SHARED)) 2464 return -EINVAL; 2465 2466 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2467 return -EOPNOTSUPP; 2468 2469 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2470 return -EPERM; 2471 vm_flags_clear(vma, VM_MAYWRITE); 2472 2473 if (!dev->mdev->clock_info) 2474 return -EOPNOTSUPP; 2475 2476 return vm_insert_page(vma, vma->vm_start, 2477 virt_to_page(dev->mdev->clock_info)); 2478 } 2479 2480 static int phys_addr_to_bar(struct pci_dev *pdev, phys_addr_t pa) 2481 { 2482 resource_size_t start, end; 2483 int bar; 2484 2485 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 2486 /* Skip BARs not present or not memory-mapped */ 2487 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) 2488 continue; 2489 2490 start = pci_resource_start(pdev, bar); 2491 end = pci_resource_end(pdev, bar); 2492 2493 if (!start || !end) 2494 continue; 2495 2496 if (pa >= start && pa <= end) 2497 return bar; 2498 } 2499 2500 return -1; 2501 } 2502 2503 static int mlx5_ib_mmap_get_pfns(struct rdma_user_mmap_entry *entry, 2504 struct phys_vec *phys_vec, 2505 struct p2pdma_provider **provider) 2506 { 2507 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2508 struct pci_dev *pdev = to_mdev(entry->ucontext->device)->mdev->pdev; 2509 int bar; 2510 2511 phys_vec->paddr = mentry->address; 2512 phys_vec->len = entry->npages * PAGE_SIZE; 2513 2514 bar = phys_addr_to_bar(pdev, phys_vec->paddr); 2515 if (bar < 0) 2516 return -EINVAL; 2517 2518 *provider = pcim_p2pdma_provider(pdev, bar); 2519 /* If the kernel was not compiled with CONFIG_PCI_P2PDMA the 2520 * functionality is not supported. 2521 */ 2522 if (!*provider) 2523 return -EOPNOTSUPP; 2524 2525 return 0; 2526 } 2527 2528 static struct rdma_user_mmap_entry * 2529 mlx5_ib_pgoff_to_mmap_entry(struct ib_ucontext *ucontext, off_t pg_off) 2530 { 2531 unsigned long entry_pgoff; 2532 unsigned long idx; 2533 u8 command; 2534 2535 pg_off = pg_off >> PAGE_SHIFT; 2536 command = get_command(pg_off); 2537 idx = get_extended_index(pg_off); 2538 2539 entry_pgoff = command << 16 | idx; 2540 2541 return rdma_user_mmap_entry_get_pgoff(ucontext, entry_pgoff); 2542 } 2543 2544 static void mlx5_ib_free_var_mmap_entry(struct mlx5_user_mmap_entry *mentry, 2545 struct mlx5_var_region *var_region) 2546 { 2547 mutex_lock(&var_region->bitmap_lock); 2548 clear_bit(mentry->page_idx, var_region->bitmap); 2549 mutex_unlock(&var_region->bitmap_lock); 2550 kfree(mentry); 2551 } 2552 2553 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2554 { 2555 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2556 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2557 struct mlx5_var_table *var_table = &dev->var_table; 2558 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2559 struct mlx5_var_region *var_region; 2560 2561 switch (mentry->mmap_flag) { 2562 case MLX5_IB_MMAP_TYPE_MEMIC: 2563 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2564 mlx5_ib_dm_mmap_free(dev, mentry); 2565 break; 2566 case MLX5_IB_MMAP_TYPE_VAR: 2567 var_region = &var_table->var_region; 2568 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2569 break; 2570 case MLX5_IB_MMAP_TYPE_TLP_VAR: 2571 var_region = &var_table->tlp_var_region; 2572 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2573 break; 2574 case MLX5_IB_MMAP_TYPE_UAR_WC: 2575 case MLX5_IB_MMAP_TYPE_UAR_NC: 2576 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2577 context->devx_uid); 2578 kfree(mentry); 2579 break; 2580 default: 2581 WARN_ON(true); 2582 } 2583 } 2584 2585 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2586 struct vm_area_struct *vma, 2587 struct mlx5_ib_ucontext *context) 2588 { 2589 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2590 int err; 2591 unsigned long idx; 2592 phys_addr_t pfn; 2593 pgprot_t prot; 2594 u32 bfreg_dyn_idx = 0; 2595 u32 uar_index; 2596 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2597 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2598 bfregi->num_static_sys_pages; 2599 2600 if (bfregi->lib_uar_dyn) 2601 return -EINVAL; 2602 2603 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2604 return -EINVAL; 2605 2606 if (dyn_uar) 2607 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2608 else 2609 idx = get_index(vma->vm_pgoff); 2610 2611 if (idx >= max_valid_idx) { 2612 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2613 idx, max_valid_idx); 2614 return -EINVAL; 2615 } 2616 2617 switch (cmd) { 2618 case MLX5_IB_MMAP_WC_PAGE: 2619 case MLX5_IB_MMAP_ALLOC_WC: 2620 case MLX5_IB_MMAP_REGULAR_PAGE: 2621 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2622 prot = pgprot_writecombine(vma->vm_page_prot); 2623 break; 2624 case MLX5_IB_MMAP_NC_PAGE: 2625 prot = pgprot_noncached(vma->vm_page_prot); 2626 break; 2627 default: 2628 return -EINVAL; 2629 } 2630 2631 if (dyn_uar) { 2632 int uars_per_page; 2633 2634 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2635 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2636 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2637 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2638 bfreg_dyn_idx, bfregi->total_num_bfregs); 2639 return -EINVAL; 2640 } 2641 2642 mutex_lock(&bfregi->lock); 2643 /* Fail if uar already allocated, first bfreg index of each 2644 * page holds its count. 2645 */ 2646 if (bfregi->count[bfreg_dyn_idx]) { 2647 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2648 mutex_unlock(&bfregi->lock); 2649 return -EINVAL; 2650 } 2651 2652 bfregi->count[bfreg_dyn_idx]++; 2653 mutex_unlock(&bfregi->lock); 2654 2655 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2656 context->devx_uid); 2657 if (err) { 2658 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2659 goto free_bfreg; 2660 } 2661 } else { 2662 uar_index = bfregi->sys_pages[idx]; 2663 } 2664 2665 pfn = uar_index2pfn(dev, uar_index); 2666 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2667 2668 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2669 prot, NULL); 2670 if (err) { 2671 mlx5_ib_err(dev, 2672 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2673 err, mmap_cmd2str(cmd)); 2674 goto err; 2675 } 2676 2677 if (dyn_uar) 2678 bfregi->sys_pages[idx] = uar_index; 2679 return 0; 2680 2681 err: 2682 if (!dyn_uar) 2683 return err; 2684 2685 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, context->devx_uid); 2686 2687 free_bfreg: 2688 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2689 2690 return err; 2691 } 2692 2693 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2694 { 2695 unsigned long idx; 2696 u8 command; 2697 2698 command = get_command(vma->vm_pgoff); 2699 idx = get_extended_index(vma->vm_pgoff); 2700 2701 return (command << 16 | idx); 2702 } 2703 2704 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2705 struct vm_area_struct *vma, 2706 struct ib_ucontext *ucontext) 2707 { 2708 struct mlx5_user_mmap_entry *mentry; 2709 struct rdma_user_mmap_entry *entry; 2710 unsigned long pgoff; 2711 pgprot_t prot; 2712 phys_addr_t pfn; 2713 int ret; 2714 2715 pgoff = mlx5_vma_to_pgoff(vma); 2716 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2717 if (!entry) 2718 return -EINVAL; 2719 2720 mentry = to_mmmap(entry); 2721 pfn = (mentry->address >> PAGE_SHIFT); 2722 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2723 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_TLP_VAR || 2724 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2725 prot = pgprot_noncached(vma->vm_page_prot); 2726 else 2727 prot = pgprot_writecombine(vma->vm_page_prot); 2728 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2729 entry->npages * PAGE_SIZE, 2730 prot, 2731 entry); 2732 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2733 return ret; 2734 } 2735 2736 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2737 { 2738 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2739 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2740 2741 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2742 (index & 0xFF)) << PAGE_SHIFT; 2743 } 2744 2745 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2746 { 2747 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2748 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2749 unsigned long command; 2750 phys_addr_t pfn; 2751 2752 command = get_command(vma->vm_pgoff); 2753 switch (command) { 2754 case MLX5_IB_MMAP_WC_PAGE: 2755 case MLX5_IB_MMAP_ALLOC_WC: 2756 if (!mlx5_wc_support_get(dev->mdev)) 2757 return -EPERM; 2758 fallthrough; 2759 case MLX5_IB_MMAP_NC_PAGE: 2760 case MLX5_IB_MMAP_REGULAR_PAGE: 2761 return uar_mmap(dev, command, vma, context); 2762 2763 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2764 return -ENOSYS; 2765 2766 case MLX5_IB_MMAP_CORE_CLOCK: 2767 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2768 return -EINVAL; 2769 2770 if (vma->vm_flags & VM_WRITE) 2771 return -EPERM; 2772 vm_flags_clear(vma, VM_MAYWRITE); 2773 2774 /* Don't expose to user-space information it shouldn't have */ 2775 if (PAGE_SIZE > 4096) 2776 return -EOPNOTSUPP; 2777 2778 pfn = (dev->mdev->bar_addr + 2779 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2780 PAGE_SHIFT; 2781 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2782 PAGE_SIZE, 2783 pgprot_noncached(vma->vm_page_prot), 2784 NULL); 2785 case MLX5_IB_MMAP_CLOCK_INFO: 2786 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2787 2788 default: 2789 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2790 } 2791 2792 return 0; 2793 } 2794 2795 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2796 { 2797 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2798 struct ib_device *ibdev = ibpd->device; 2799 struct mlx5_ib_alloc_pd_resp resp = {}; 2800 int err; 2801 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2802 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2803 u16 uid = 0; 2804 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2805 udata, struct mlx5_ib_ucontext, ibucontext); 2806 2807 uid = context ? context->devx_uid : 0; 2808 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2809 MLX5_SET(alloc_pd_in, in, uid, uid); 2810 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2811 if (err) 2812 return err; 2813 2814 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2815 pd->uid = uid; 2816 if (udata) { 2817 resp.pdn = pd->pdn; 2818 err = ib_respond_udata(udata, resp); 2819 if (err) { 2820 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2821 return err; 2822 } 2823 } 2824 2825 return 0; 2826 } 2827 2828 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2829 { 2830 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2831 struct mlx5_ib_pd *mpd = to_mpd(pd); 2832 2833 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2834 } 2835 2836 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2837 { 2838 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2839 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2840 int err; 2841 u16 uid; 2842 2843 uid = ibqp->pd ? 2844 to_mpd(ibqp->pd)->uid : 0; 2845 2846 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2847 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2848 return -EOPNOTSUPP; 2849 } 2850 2851 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2852 if (err) 2853 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2854 ibqp->qp_num, gid->raw); 2855 2856 return err; 2857 } 2858 2859 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2860 { 2861 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2862 int err; 2863 u16 uid; 2864 2865 uid = ibqp->pd ? 2866 to_mpd(ibqp->pd)->uid : 0; 2867 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2868 if (err) 2869 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2870 ibqp->qp_num, gid->raw); 2871 2872 return err; 2873 } 2874 2875 static int init_node_data(struct mlx5_ib_dev *dev) 2876 { 2877 int err; 2878 2879 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2880 if (err) 2881 return err; 2882 2883 dev->mdev->rev_id = dev->mdev->pdev->revision; 2884 2885 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2886 } 2887 2888 static ssize_t fw_pages_show(struct device *device, 2889 struct device_attribute *attr, char *buf) 2890 { 2891 struct mlx5_ib_dev *dev = 2892 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2893 2894 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2895 } 2896 static DEVICE_ATTR_RO(fw_pages); 2897 2898 static ssize_t reg_pages_show(struct device *device, 2899 struct device_attribute *attr, char *buf) 2900 { 2901 struct mlx5_ib_dev *dev = 2902 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2903 2904 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2905 } 2906 static DEVICE_ATTR_RO(reg_pages); 2907 2908 static ssize_t hca_type_show(struct device *device, 2909 struct device_attribute *attr, char *buf) 2910 { 2911 struct mlx5_ib_dev *dev = 2912 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2913 2914 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2915 } 2916 static DEVICE_ATTR_RO(hca_type); 2917 2918 static ssize_t hw_rev_show(struct device *device, 2919 struct device_attribute *attr, char *buf) 2920 { 2921 struct mlx5_ib_dev *dev = 2922 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2923 2924 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2925 } 2926 static DEVICE_ATTR_RO(hw_rev); 2927 2928 static ssize_t board_id_show(struct device *device, 2929 struct device_attribute *attr, char *buf) 2930 { 2931 struct mlx5_ib_dev *dev = 2932 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2933 2934 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2935 dev->mdev->board_id); 2936 } 2937 static DEVICE_ATTR_RO(board_id); 2938 2939 static struct attribute *mlx5_class_attributes[] = { 2940 &dev_attr_hw_rev.attr, 2941 &dev_attr_hca_type.attr, 2942 &dev_attr_board_id.attr, 2943 &dev_attr_fw_pages.attr, 2944 &dev_attr_reg_pages.attr, 2945 NULL, 2946 }; 2947 2948 static const struct attribute_group mlx5_attr_group = { 2949 .attrs = mlx5_class_attributes, 2950 }; 2951 2952 static void pkey_change_handler(struct work_struct *work) 2953 { 2954 struct mlx5_ib_port_resources *ports = 2955 container_of(work, struct mlx5_ib_port_resources, 2956 pkey_change_work); 2957 2958 if (!ports->gsi) 2959 /* 2960 * We got this event before device was fully configured 2961 * and MAD registration code wasn't called/finished yet. 2962 */ 2963 return; 2964 2965 mlx5_ib_gsi_pkey_change(ports->gsi); 2966 } 2967 2968 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2969 { 2970 struct mlx5_ib_qp *mqp; 2971 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2972 struct mlx5_core_cq *mcq; 2973 struct list_head cq_armed_list; 2974 unsigned long flags_qp; 2975 unsigned long flags_cq; 2976 unsigned long flags; 2977 2978 INIT_LIST_HEAD(&cq_armed_list); 2979 2980 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2981 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2982 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2983 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2984 if (mqp->sq.tail != mqp->sq.head) { 2985 send_mcq = to_mcq(mqp->ibqp.send_cq); 2986 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2987 if (send_mcq->mcq.comp && 2988 mqp->ibqp.send_cq->comp_handler) { 2989 if (!send_mcq->mcq.reset_notify_added) { 2990 send_mcq->mcq.reset_notify_added = 1; 2991 list_add_tail(&send_mcq->mcq.reset_notify, 2992 &cq_armed_list); 2993 } 2994 } 2995 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2996 } 2997 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2998 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2999 /* no handling is needed for SRQ */ 3000 if (!mqp->ibqp.srq) { 3001 if (mqp->rq.tail != mqp->rq.head) { 3002 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3003 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3004 if (recv_mcq->mcq.comp && 3005 mqp->ibqp.recv_cq->comp_handler) { 3006 if (!recv_mcq->mcq.reset_notify_added) { 3007 recv_mcq->mcq.reset_notify_added = 1; 3008 list_add_tail(&recv_mcq->mcq.reset_notify, 3009 &cq_armed_list); 3010 } 3011 } 3012 spin_unlock_irqrestore(&recv_mcq->lock, 3013 flags_cq); 3014 } 3015 } 3016 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3017 } 3018 /*At that point all inflight post send were put to be executed as of we 3019 * lock/unlock above locks Now need to arm all involved CQs. 3020 */ 3021 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3022 mcq->comp(mcq, NULL); 3023 } 3024 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3025 } 3026 3027 static void delay_drop_handler(struct work_struct *work) 3028 { 3029 int err; 3030 struct mlx5_ib_delay_drop *delay_drop = 3031 container_of(work, struct mlx5_ib_delay_drop, 3032 delay_drop_work); 3033 3034 atomic_inc(&delay_drop->events_cnt); 3035 3036 mutex_lock(&delay_drop->lock); 3037 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 3038 if (err) { 3039 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3040 delay_drop->timeout); 3041 delay_drop->activate = false; 3042 } 3043 mutex_unlock(&delay_drop->lock); 3044 } 3045 3046 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3047 struct ib_event *ibev) 3048 { 3049 u32 port = (eqe->data.port.port >> 4) & 0xf; 3050 3051 switch (eqe->sub_type) { 3052 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 3053 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3054 IB_LINK_LAYER_ETHERNET) 3055 schedule_work(&ibdev->delay_drop.delay_drop_work); 3056 break; 3057 default: /* do nothing */ 3058 return; 3059 } 3060 } 3061 3062 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3063 struct ib_event *ibev) 3064 { 3065 u32 port = (eqe->data.port.port >> 4) & 0xf; 3066 3067 ibev->element.port_num = port; 3068 3069 switch (eqe->sub_type) { 3070 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 3071 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 3072 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 3073 if (ibdev->ib_active) { 3074 struct ib_event speed_event = {}; 3075 3076 speed_event.device = &ibdev->ib_dev; 3077 speed_event.event = IB_EVENT_DEVICE_SPEED_CHANGE; 3078 ib_dispatch_event(&speed_event); 3079 } 3080 3081 /* In RoCE, port up/down events are handled in 3082 * mlx5_netdev_event(). 3083 */ 3084 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3085 IB_LINK_LAYER_ETHERNET) 3086 return -EINVAL; 3087 3088 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 3089 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3090 break; 3091 3092 case MLX5_PORT_CHANGE_SUBTYPE_LID: 3093 ibev->event = IB_EVENT_LID_CHANGE; 3094 break; 3095 3096 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 3097 ibev->event = IB_EVENT_PKEY_CHANGE; 3098 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3099 break; 3100 3101 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 3102 ibev->event = IB_EVENT_GID_CHANGE; 3103 break; 3104 3105 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 3106 ibev->event = IB_EVENT_CLIENT_REREGISTER; 3107 break; 3108 default: 3109 return -EINVAL; 3110 } 3111 3112 return 0; 3113 } 3114 3115 static void mlx5_ib_handle_event(struct work_struct *_work) 3116 { 3117 struct mlx5_ib_event_work *work = 3118 container_of(_work, struct mlx5_ib_event_work, work); 3119 struct mlx5_ib_dev *ibdev; 3120 struct ib_event ibev; 3121 3122 if (work->is_slave) { 3123 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 3124 if (!ibdev) 3125 goto out; 3126 } else { 3127 ibdev = work->dev; 3128 } 3129 3130 switch (work->event) { 3131 case MLX5_EVENT_TYPE_PORT_CHANGE: 3132 if (handle_port_change(ibdev, work->param, &ibev)) 3133 goto out; 3134 break; 3135 case MLX5_EVENT_TYPE_GENERAL_EVENT: 3136 handle_general_event(ibdev, work->param, &ibev); 3137 fallthrough; 3138 default: 3139 goto out; 3140 } 3141 3142 ibev.device = &ibdev->ib_dev; 3143 3144 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3145 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3146 goto out; 3147 } 3148 3149 if (ibdev->ib_active) 3150 ib_dispatch_event(&ibev); 3151 3152 out: 3153 kfree(work); 3154 } 3155 3156 static int mlx5_ib_event(struct notifier_block *nb, 3157 unsigned long event, void *param) 3158 { 3159 struct mlx5_ib_event_work *work; 3160 3161 work = kmalloc_obj(*work, GFP_ATOMIC); 3162 if (!work) 3163 return NOTIFY_DONE; 3164 3165 INIT_WORK(&work->work, mlx5_ib_handle_event); 3166 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 3167 work->is_slave = false; 3168 work->param = param; 3169 work->event = event; 3170 3171 queue_work(mlx5_ib_event_wq, &work->work); 3172 3173 return NOTIFY_OK; 3174 } 3175 3176 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 3177 unsigned long event, void *param) 3178 { 3179 struct mlx5_ib_event_work *work; 3180 3181 work = kmalloc_obj(*work, GFP_ATOMIC); 3182 if (!work) 3183 return NOTIFY_DONE; 3184 3185 INIT_WORK(&work->work, mlx5_ib_handle_event); 3186 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 3187 work->is_slave = true; 3188 work->param = param; 3189 work->event = event; 3190 queue_work(mlx5_ib_event_wq, &work->work); 3191 3192 return NOTIFY_OK; 3193 } 3194 3195 static void mlx5_ib_handle_sys_error_event(struct work_struct *_work) 3196 { 3197 struct mlx5_ib_event_work *work = 3198 container_of(_work, struct mlx5_ib_event_work, work); 3199 struct mlx5_ib_dev *ibdev = work->dev; 3200 struct ib_event ibev; 3201 3202 ibev.event = IB_EVENT_DEVICE_FATAL; 3203 mlx5_ib_handle_internal_error(ibdev); 3204 ibev.element.port_num = (u8)(unsigned long)work->param; 3205 ibev.device = &ibdev->ib_dev; 3206 3207 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3208 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3209 goto out; 3210 } 3211 3212 if (ibdev->ib_active) 3213 ib_dispatch_event(&ibev); 3214 3215 ibdev->ib_active = false; 3216 out: 3217 kfree(work); 3218 } 3219 3220 static int mlx5_ib_sys_error_event(struct notifier_block *nb, 3221 unsigned long event, void *param) 3222 { 3223 struct mlx5_ib_event_work *work; 3224 3225 if (event != MLX5_DEV_EVENT_SYS_ERROR) 3226 return NOTIFY_DONE; 3227 3228 work = kmalloc_obj(*work, GFP_ATOMIC); 3229 if (!work) 3230 return NOTIFY_DONE; 3231 3232 INIT_WORK(&work->work, mlx5_ib_handle_sys_error_event); 3233 work->dev = container_of(nb, struct mlx5_ib_dev, sys_error_events); 3234 work->is_slave = false; 3235 work->param = param; 3236 work->event = event; 3237 3238 queue_work(mlx5_ib_event_wq, &work->work); 3239 3240 return NOTIFY_OK; 3241 } 3242 3243 static int mlx5_ib_stage_sys_error_notifier_init(struct mlx5_ib_dev *dev) 3244 { 3245 dev->sys_error_events.notifier_call = mlx5_ib_sys_error_event; 3246 mlx5_notifier_register(dev->mdev, &dev->sys_error_events); 3247 return 0; 3248 } 3249 3250 static void mlx5_ib_stage_sys_error_notifier_cleanup(struct mlx5_ib_dev *dev) 3251 { 3252 mlx5_notifier_unregister(dev->mdev, &dev->sys_error_events); 3253 } 3254 3255 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 3256 { 3257 struct mlx5_hca_vport_context vport_ctx; 3258 int err; 3259 3260 *num_plane = 0; 3261 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 3262 return 0; 3263 3264 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 3265 if (err) 3266 return err; 3267 3268 *num_plane = vport_ctx.num_plane; 3269 return 0; 3270 } 3271 3272 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3273 { 3274 struct mlx5_hca_vport_context vport_ctx; 3275 int err; 3276 int port; 3277 3278 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 3279 return 0; 3280 3281 for (port = 1; port <= dev->num_ports; port++) { 3282 if (dev->num_plane) { 3283 dev->port_caps[port - 1].has_smi = false; 3284 continue; 3285 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 3286 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 3287 dev->port_caps[port - 1].has_smi = true; 3288 continue; 3289 } 3290 3291 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 3292 &vport_ctx); 3293 if (err) { 3294 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3295 port, err); 3296 return err; 3297 } 3298 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3305 { 3306 unsigned int port; 3307 3308 rdma_for_each_port (&dev->ib_dev, port) 3309 mlx5_query_ext_port_caps(dev, port); 3310 } 3311 3312 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3313 { 3314 switch (umr_fence_cap) { 3315 case MLX5_CAP_UMR_FENCE_NONE: 3316 return MLX5_FENCE_MODE_NONE; 3317 case MLX5_CAP_UMR_FENCE_SMALL: 3318 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3319 default: 3320 return MLX5_FENCE_MODE_STRONG_ORDERING; 3321 } 3322 } 3323 3324 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3325 { 3326 struct mlx5_ib_resources *devr = &dev->devr; 3327 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3328 struct ib_device *ibdev; 3329 struct ib_pd *pd; 3330 struct ib_cq *cq; 3331 int ret = 0; 3332 3333 3334 /* 3335 * devr->c0 is set once, never changed until device unload. 3336 * Avoid taking the mutex if initialization is already done. 3337 */ 3338 if (smp_load_acquire(&devr->c0)) 3339 return 0; 3340 3341 mutex_lock(&devr->cq_lock); 3342 if (devr->c0) 3343 goto unlock; 3344 3345 ibdev = &dev->ib_dev; 3346 pd = ib_alloc_pd(ibdev, 0); 3347 if (IS_ERR(pd)) { 3348 ret = PTR_ERR(pd); 3349 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n", 3350 pd); 3351 goto unlock; 3352 } 3353 3354 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3355 if (IS_ERR(cq)) { 3356 ret = PTR_ERR(cq); 3357 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n", 3358 cq); 3359 ib_dealloc_pd(pd); 3360 goto unlock; 3361 } 3362 3363 devr->p0 = pd; 3364 smp_store_release(&devr->c0, cq); 3365 3366 unlock: 3367 mutex_unlock(&devr->cq_lock); 3368 return ret; 3369 } 3370 3371 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3372 { 3373 struct mlx5_ib_resources *devr = &dev->devr; 3374 struct ib_srq_init_attr attr; 3375 struct ib_srq *s0, *s1; 3376 int ret = 0; 3377 3378 /* 3379 * devr->s1 is set once, never changed until device unload. 3380 * Avoid taking the mutex if initialization is already done. 3381 */ 3382 if (smp_load_acquire(&devr->s1)) 3383 return 0; 3384 3385 mutex_lock(&devr->srq_lock); 3386 if (devr->s1) 3387 goto unlock; 3388 3389 ret = mlx5_ib_dev_res_cq_init(dev); 3390 if (ret) 3391 goto unlock; 3392 3393 memset(&attr, 0, sizeof(attr)); 3394 attr.attr.max_sge = 1; 3395 attr.attr.max_wr = 1; 3396 attr.srq_type = IB_SRQT_XRC; 3397 attr.ext.cq = devr->c0; 3398 3399 s0 = ib_create_srq(devr->p0, &attr); 3400 if (IS_ERR(s0)) { 3401 ret = PTR_ERR(s0); 3402 mlx5_ib_err(dev, 3403 "Couldn't create SRQ 0 for res init, err=%pe\n", 3404 s0); 3405 goto unlock; 3406 } 3407 3408 memset(&attr, 0, sizeof(attr)); 3409 attr.attr.max_sge = 1; 3410 attr.attr.max_wr = 1; 3411 attr.srq_type = IB_SRQT_BASIC; 3412 3413 s1 = ib_create_srq(devr->p0, &attr); 3414 if (IS_ERR(s1)) { 3415 ret = PTR_ERR(s1); 3416 mlx5_ib_err(dev, 3417 "Couldn't create SRQ 1 for res init, err=%pe\n", 3418 s1); 3419 ib_destroy_srq(s0); 3420 goto unlock; 3421 } 3422 3423 devr->s0 = s0; 3424 smp_store_release(&devr->s1, s1); 3425 3426 unlock: 3427 mutex_unlock(&devr->srq_lock); 3428 return ret; 3429 } 3430 3431 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3432 { 3433 struct mlx5_ib_resources *devr = &dev->devr; 3434 int ret; 3435 3436 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3437 return -EOPNOTSUPP; 3438 3439 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3440 if (ret) 3441 return ret; 3442 3443 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3444 if (ret) { 3445 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3446 return ret; 3447 } 3448 3449 mutex_init(&devr->cq_lock); 3450 mutex_init(&devr->srq_lock); 3451 3452 return 0; 3453 } 3454 3455 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3456 { 3457 struct mlx5_ib_resources *devr = &dev->devr; 3458 3459 /* After s0/s1 init, they are not unset during the device lifetime. */ 3460 if (devr->s1) { 3461 ib_destroy_srq(devr->s1); 3462 ib_destroy_srq(devr->s0); 3463 } 3464 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3465 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3466 /* After p0/c0 init, they are not unset during the device lifetime. */ 3467 if (devr->c0) { 3468 ib_destroy_cq(devr->c0); 3469 ib_dealloc_pd(devr->p0); 3470 } 3471 mutex_destroy(&devr->cq_lock); 3472 mutex_destroy(&devr->srq_lock); 3473 } 3474 3475 static int 3476 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3477 { 3478 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3479 struct mlx5_core_dev *mdev = dev->mdev; 3480 bool ro_supp = false; 3481 void *mkc; 3482 u32 mkey; 3483 u32 pdn; 3484 u32 *in; 3485 int err; 3486 3487 err = mlx5_core_alloc_pd(mdev, &pdn); 3488 if (err) 3489 return err; 3490 3491 in = kvzalloc(inlen, GFP_KERNEL); 3492 if (!in) { 3493 err = -ENOMEM; 3494 goto err; 3495 } 3496 3497 MLX5_SET(create_mkey_in, in, data_direct, 1); 3498 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3499 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3500 MLX5_SET(mkc, mkc, lw, 1); 3501 MLX5_SET(mkc, mkc, lr, 1); 3502 MLX5_SET(mkc, mkc, rw, 1); 3503 MLX5_SET(mkc, mkc, rr, 1); 3504 MLX5_SET(mkc, mkc, a, 1); 3505 MLX5_SET(mkc, mkc, pd, pdn); 3506 MLX5_SET(mkc, mkc, length64, 1); 3507 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3508 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3509 if (err) 3510 goto err_mkey; 3511 3512 dev->ddr.mkey = mkey; 3513 dev->ddr.pdn = pdn; 3514 3515 /* create another mkey with RO support */ 3516 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { 3517 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 3518 ro_supp = true; 3519 } 3520 3521 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { 3522 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 3523 ro_supp = true; 3524 } 3525 3526 if (ro_supp) { 3527 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3528 /* RO is defined as best effort */ 3529 if (!err) { 3530 dev->ddr.mkey_ro = mkey; 3531 dev->ddr.mkey_ro_valid = true; 3532 } 3533 } 3534 3535 kvfree(in); 3536 return 0; 3537 3538 err_mkey: 3539 kvfree(in); 3540 err: 3541 mlx5_core_dealloc_pd(mdev, pdn); 3542 return err; 3543 } 3544 3545 static void 3546 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3547 { 3548 3549 if (dev->ddr.mkey_ro_valid) 3550 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro); 3551 3552 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3553 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3554 } 3555 3556 static u32 get_core_cap_flags(struct ib_device *ibdev, 3557 struct mlx5_hca_vport_context *rep) 3558 { 3559 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3560 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3561 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3562 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3563 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3564 u32 ret = 0; 3565 3566 if (rep->grh_required) 3567 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3568 3569 if (dev->num_plane) 3570 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3571 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3572 RDMA_CORE_CAP_AF_IB; 3573 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3574 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3575 3576 if (ll == IB_LINK_LAYER_INFINIBAND) 3577 return ret | RDMA_CORE_PORT_IBA_IB; 3578 3579 if (raw_support) 3580 ret |= RDMA_CORE_PORT_RAW_PACKET; 3581 3582 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3583 return ret; 3584 3585 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3586 return ret; 3587 3588 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3589 ret |= RDMA_CORE_PORT_IBA_ROCE; 3590 3591 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3592 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3593 3594 return ret; 3595 } 3596 3597 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3598 struct ib_port_immutable *immutable) 3599 { 3600 struct ib_port_attr attr; 3601 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3602 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3603 struct mlx5_hca_vport_context rep = {0}; 3604 int err; 3605 3606 err = ib_query_port(ibdev, port_num, &attr); 3607 if (err) 3608 return err; 3609 3610 if (ll == IB_LINK_LAYER_INFINIBAND) { 3611 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3612 port_num = smi_to_native_portnum(dev, port_num); 3613 3614 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3615 &rep); 3616 if (err) 3617 return err; 3618 } 3619 3620 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3621 immutable->gid_tbl_len = attr.gid_tbl_len; 3622 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3623 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3624 3625 return 0; 3626 } 3627 3628 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3629 struct ib_port_immutable *immutable) 3630 { 3631 struct ib_port_attr attr; 3632 int err; 3633 3634 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3635 3636 err = ib_query_port(ibdev, port_num, &attr); 3637 if (err) 3638 return err; 3639 3640 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3641 immutable->gid_tbl_len = attr.gid_tbl_len; 3642 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3643 3644 return 0; 3645 } 3646 3647 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3648 { 3649 struct mlx5_ib_dev *dev = 3650 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3651 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3652 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3653 fw_rev_sub(dev->mdev)); 3654 } 3655 3656 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3657 { 3658 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3659 lag_events); 3660 struct mlx5_core_dev *mdev = dev->mdev; 3661 struct ib_device *ibdev = &dev->ib_dev; 3662 struct net_device *old_ndev = NULL; 3663 struct mlx5_ib_port *port; 3664 struct net_device *ndev; 3665 u32 portnum = 0; 3666 int ret = 0; 3667 int i; 3668 3669 switch (event) { 3670 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3671 ndev = data; 3672 if (ndev) { 3673 if (!mlx5_lag_is_roce(mdev)) { 3674 // sriov lag 3675 for (i = 0; i < dev->num_ports; i++) { 3676 port = &dev->port[i]; 3677 if (port->rep && port->rep->vport == 3678 MLX5_VPORT_UPLINK) { 3679 portnum = i; 3680 break; 3681 } 3682 } 3683 } 3684 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3685 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3686 if (ret) 3687 goto out; 3688 3689 if (old_ndev) 3690 roce_del_all_netdev_gids(ibdev, portnum + 1, 3691 old_ndev); 3692 rdma_roce_rescan_port(ibdev, portnum + 1); 3693 } 3694 break; 3695 default: 3696 return NOTIFY_DONE; 3697 } 3698 3699 out: 3700 dev_put(old_ndev); 3701 return notifier_from_errno(ret); 3702 } 3703 3704 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3705 { 3706 dev->lag_events.notifier_call = lag_event; 3707 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3708 &dev->lag_events); 3709 } 3710 3711 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3712 { 3713 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3714 &dev->lag_events); 3715 } 3716 3717 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3718 { 3719 struct mlx5_flow_table_attr ft_attr = {}; 3720 struct mlx5_core_dev *mdev = dev->mdev; 3721 struct mlx5_flow_namespace *ns; 3722 int err; 3723 3724 ns = mlx5_get_flow_namespace(mdev, MLX5_FLOW_NAMESPACE_LAG); 3725 if (!ns || !mlx5_lag_is_active(mdev)) 3726 return 0; 3727 3728 err = mlx5_cmd_create_vport_lag(mdev); 3729 if (err) 3730 return err; 3731 3732 ft_attr.level = 0; 3733 ft_attr.prio = 0; 3734 ft_attr.max_fte = dev->num_ports; 3735 3736 err = mlx5_lag_demux_init(mdev, &ft_attr); 3737 if (err) 3738 goto err_destroy_vport_lag; 3739 3740 mlx5e_lag_event_register(dev); 3741 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3742 dev->lag_active = true; 3743 return 0; 3744 3745 err_destroy_vport_lag: 3746 mlx5_cmd_destroy_vport_lag(mdev); 3747 return err; 3748 } 3749 3750 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3751 { 3752 struct mlx5_core_dev *mdev = dev->mdev; 3753 3754 if (dev->lag_active) { 3755 dev->lag_active = false; 3756 3757 mlx5e_lag_event_unregister(dev); 3758 mlx5_lag_demux_cleanup(mdev); 3759 3760 mlx5_cmd_destroy_vport_lag(mdev); 3761 } 3762 } 3763 3764 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3765 struct net_device *netdev) 3766 { 3767 int err; 3768 3769 if (roce->tracking_netdev) 3770 return; 3771 roce->tracking_netdev = netdev; 3772 roce->nb.notifier_call = mlx5_netdev_event; 3773 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3774 WARN_ON(err); 3775 } 3776 3777 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3778 { 3779 if (!roce->tracking_netdev) 3780 return; 3781 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3782 &roce->nn); 3783 roce->tracking_netdev = NULL; 3784 } 3785 3786 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3787 unsigned long event, void *data) 3788 { 3789 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3790 struct net_device *netdev = data; 3791 3792 switch (event) { 3793 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3794 if (netdev) 3795 mlx5_netdev_notifier_register(roce, netdev); 3796 else 3797 mlx5_netdev_notifier_unregister(roce); 3798 break; 3799 default: 3800 return NOTIFY_DONE; 3801 } 3802 3803 return NOTIFY_OK; 3804 } 3805 3806 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3807 { 3808 struct mlx5_roce *roce = &dev->port[port_num].roce; 3809 3810 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3811 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3812 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3813 } 3814 3815 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3816 { 3817 struct mlx5_roce *roce = &dev->port[port_num].roce; 3818 3819 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3820 mlx5_netdev_notifier_unregister(roce); 3821 } 3822 3823 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3824 { 3825 int err; 3826 3827 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3828 err = mlx5_nic_vport_enable_roce(dev->mdev); 3829 if (err) 3830 return err; 3831 } 3832 3833 err = mlx5_eth_lag_init(dev); 3834 if (err) 3835 goto err_disable_roce; 3836 3837 return 0; 3838 3839 err_disable_roce: 3840 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3841 mlx5_nic_vport_disable_roce(dev->mdev); 3842 3843 return err; 3844 } 3845 3846 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3847 { 3848 mlx5_eth_lag_cleanup(dev); 3849 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3850 mlx5_nic_vport_disable_roce(dev->mdev); 3851 } 3852 3853 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3854 enum rdma_netdev_t type, 3855 struct rdma_netdev_alloc_params *params) 3856 { 3857 if (type != RDMA_NETDEV_IPOIB) 3858 return -EOPNOTSUPP; 3859 3860 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3861 } 3862 3863 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3864 size_t count, loff_t *pos) 3865 { 3866 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3867 char lbuf[20]; 3868 int len; 3869 3870 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3871 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3872 } 3873 3874 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3875 size_t count, loff_t *pos) 3876 { 3877 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3878 u32 timeout; 3879 u32 var; 3880 3881 if (kstrtouint_from_user(buf, count, 0, &var)) 3882 return -EFAULT; 3883 3884 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3885 1000); 3886 if (timeout != var) 3887 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3888 timeout); 3889 3890 delay_drop->timeout = timeout; 3891 3892 return count; 3893 } 3894 3895 static const struct file_operations fops_delay_drop_timeout = { 3896 .owner = THIS_MODULE, 3897 .open = simple_open, 3898 .write = delay_drop_timeout_write, 3899 .read = delay_drop_timeout_read, 3900 }; 3901 3902 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3903 struct mlx5_ib_multiport_info *mpi) 3904 { 3905 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3906 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3907 int comps; 3908 int err; 3909 int i; 3910 3911 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3912 3913 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3914 3915 mlx5_core_mp_event_replay(ibdev->mdev, 3916 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3917 NULL); 3918 mlx5_core_mp_event_replay(mpi->mdev, 3919 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3920 NULL); 3921 3922 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3923 3924 spin_lock(&port->mp.mpi_lock); 3925 if (!mpi->ibdev) { 3926 spin_unlock(&port->mp.mpi_lock); 3927 return; 3928 } 3929 3930 mpi->ibdev = NULL; 3931 3932 spin_unlock(&port->mp.mpi_lock); 3933 if (mpi->mdev_events.notifier_call) 3934 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3935 mpi->mdev_events.notifier_call = NULL; 3936 mlx5_mdev_netdev_untrack(ibdev, port_num); 3937 spin_lock(&port->mp.mpi_lock); 3938 3939 comps = mpi->mdev_refcnt; 3940 if (comps) { 3941 mpi->unaffiliate = true; 3942 init_completion(&mpi->unref_comp); 3943 spin_unlock(&port->mp.mpi_lock); 3944 3945 for (i = 0; i < comps; i++) 3946 wait_for_completion(&mpi->unref_comp); 3947 3948 spin_lock(&port->mp.mpi_lock); 3949 mpi->unaffiliate = false; 3950 } 3951 3952 port->mp.mpi = NULL; 3953 3954 spin_unlock(&port->mp.mpi_lock); 3955 3956 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3957 3958 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3959 /* Log an error, still needed to cleanup the pointers and add 3960 * it back to the list. 3961 */ 3962 if (err) 3963 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3964 port_num + 1); 3965 3966 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3967 } 3968 3969 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3970 struct mlx5_ib_multiport_info *mpi) 3971 { 3972 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3973 u64 key; 3974 int err; 3975 3976 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3977 3978 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3979 if (ibdev->port[port_num].mp.mpi) { 3980 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3981 port_num + 1); 3982 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3983 return false; 3984 } 3985 3986 ibdev->port[port_num].mp.mpi = mpi; 3987 mpi->ibdev = ibdev; 3988 mpi->mdev_events.notifier_call = NULL; 3989 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3990 3991 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3992 if (err) 3993 goto unbind; 3994 3995 mlx5_mdev_netdev_track(ibdev, port_num); 3996 3997 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3998 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3999 4000 mlx5_ib_init_cong_debugfs(ibdev, port_num); 4001 4002 key = mpi->mdev->priv.adev_idx; 4003 mlx5_core_mp_event_replay(mpi->mdev, 4004 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 4005 &key); 4006 mlx5_core_mp_event_replay(ibdev->mdev, 4007 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 4008 &key); 4009 4010 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 4011 if (err) 4012 goto unbind; 4013 4014 return true; 4015 4016 unbind: 4017 mlx5_ib_unbind_slave_port(ibdev, mpi); 4018 return false; 4019 } 4020 4021 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 4022 { 4023 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 4024 int ret; 4025 4026 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 4027 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 4028 return 0; 4029 4030 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 4031 if (ret) 4032 return ret; 4033 4034 ret = mlx5_ib_create_data_direct_resources(dev); 4035 if (ret) 4036 return ret; 4037 4038 INIT_LIST_HEAD(&dev->data_direct_mr_list); 4039 ret = mlx5_data_direct_ib_reg(dev, vuid); 4040 if (ret) 4041 mlx5_ib_free_data_direct_resources(dev); 4042 4043 return ret; 4044 } 4045 4046 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 4047 { 4048 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 4049 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 4050 return; 4051 4052 mlx5_data_direct_ib_unreg(dev); 4053 mlx5_ib_free_data_direct_resources(dev); 4054 } 4055 4056 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4057 { 4058 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4059 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4060 port_num + 1); 4061 struct mlx5_ib_multiport_info *mpi; 4062 int err; 4063 u32 i; 4064 4065 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4066 return 0; 4067 4068 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4069 &dev->sys_image_guid); 4070 if (err) 4071 return err; 4072 4073 err = mlx5_nic_vport_enable_roce(dev->mdev); 4074 if (err) 4075 return err; 4076 4077 mutex_lock(&mlx5_ib_multiport_mutex); 4078 for (i = 0; i < dev->num_ports; i++) { 4079 bool bound = false; 4080 4081 /* build a stub multiport info struct for the native port. */ 4082 if (i == port_num) { 4083 mpi = kzalloc_obj(*mpi); 4084 if (!mpi) { 4085 mutex_unlock(&mlx5_ib_multiport_mutex); 4086 mlx5_nic_vport_disable_roce(dev->mdev); 4087 return -ENOMEM; 4088 } 4089 4090 mpi->is_master = true; 4091 mpi->mdev = dev->mdev; 4092 mpi->sys_image_guid = dev->sys_image_guid; 4093 dev->port[i].mp.mpi = mpi; 4094 mpi->ibdev = dev; 4095 mpi = NULL; 4096 continue; 4097 } 4098 4099 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4100 list) { 4101 if (dev->sys_image_guid == mpi->sys_image_guid && 4102 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 4103 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 4104 bound = mlx5_ib_bind_slave_port(dev, mpi); 4105 } 4106 4107 if (bound) { 4108 dev_dbg(mpi->mdev->device, 4109 "removing port from unaffiliated list.\n"); 4110 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4111 list_del(&mpi->list); 4112 break; 4113 } 4114 } 4115 if (!bound) 4116 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4117 i + 1); 4118 } 4119 4120 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4121 mutex_unlock(&mlx5_ib_multiport_mutex); 4122 return err; 4123 } 4124 4125 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4126 { 4127 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4128 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4129 port_num + 1); 4130 u32 i; 4131 4132 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4133 return; 4134 4135 mutex_lock(&mlx5_ib_multiport_mutex); 4136 for (i = 0; i < dev->num_ports; i++) { 4137 if (dev->port[i].mp.mpi) { 4138 /* Destroy the native port stub */ 4139 if (i == port_num) { 4140 kfree(dev->port[i].mp.mpi); 4141 dev->port[i].mp.mpi = NULL; 4142 } else { 4143 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 4144 i + 1); 4145 list_add_tail(&dev->port[i].mp.mpi->list, 4146 &mlx5_ib_unaffiliated_port_list); 4147 mlx5_ib_unbind_slave_port(dev, 4148 dev->port[i].mp.mpi); 4149 } 4150 } 4151 } 4152 4153 mlx5_ib_dbg(dev, "removing from devlist\n"); 4154 list_del(&dev->ib_dev_list); 4155 mutex_unlock(&mlx5_ib_multiport_mutex); 4156 4157 mlx5_nic_vport_disable_roce(dev->mdev); 4158 } 4159 4160 static int mmap_obj_cleanup(struct ib_uobject *uobject, 4161 enum rdma_remove_reason why, 4162 struct uverbs_attr_bundle *attrs) 4163 { 4164 struct mlx5_user_mmap_entry *obj = uobject->object; 4165 4166 rdma_user_mmap_entry_remove(&obj->rdma_entry); 4167 return 0; 4168 } 4169 4170 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 4171 struct mlx5_user_mmap_entry *entry, 4172 size_t length) 4173 { 4174 return rdma_user_mmap_entry_insert_range( 4175 &c->ibucontext, &entry->rdma_entry, length, 4176 (MLX5_IB_MMAP_OFFSET_START << 16), 4177 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 4178 } 4179 4180 static struct mlx5_user_mmap_entry * 4181 alloc_var_entry(struct mlx5_ib_ucontext *c, u32 flags) 4182 { 4183 struct mlx5_user_mmap_entry *entry; 4184 struct mlx5_var_region *var_region; 4185 struct mlx5_var_table *var_table; 4186 u32 page_idx; 4187 int err; 4188 4189 var_table = &to_mdev(c->ibucontext.device)->var_table; 4190 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) 4191 var_region = &var_table->tlp_var_region; 4192 else 4193 var_region = &var_table->var_region; 4194 4195 entry = kzalloc_obj(*entry); 4196 if (!entry) 4197 return ERR_PTR(-ENOMEM); 4198 4199 mutex_lock(&var_region->bitmap_lock); 4200 page_idx = find_first_zero_bit(var_region->bitmap, 4201 var_region->num_var_hw_entries); 4202 if (page_idx >= var_region->num_var_hw_entries) { 4203 err = -ENOSPC; 4204 mutex_unlock(&var_region->bitmap_lock); 4205 goto end; 4206 } 4207 4208 set_bit(page_idx, var_region->bitmap); 4209 mutex_unlock(&var_region->bitmap_lock); 4210 4211 entry->address = var_region->hw_start_addr + 4212 (page_idx * var_region->stride_size); 4213 entry->page_idx = page_idx; 4214 entry->mmap_flag = flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP ? 4215 MLX5_IB_MMAP_TYPE_TLP_VAR : 4216 MLX5_IB_MMAP_TYPE_VAR; 4217 4218 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 4219 var_region->stride_size); 4220 if (err) 4221 goto err_insert; 4222 4223 return entry; 4224 4225 err_insert: 4226 mutex_lock(&var_region->bitmap_lock); 4227 clear_bit(page_idx, var_region->bitmap); 4228 mutex_unlock(&var_region->bitmap_lock); 4229 end: 4230 kfree(entry); 4231 return ERR_PTR(err); 4232 } 4233 4234 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 4235 struct uverbs_attr_bundle *attrs) 4236 { 4237 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4238 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4239 struct mlx5_user_mmap_entry *entry; 4240 struct mlx5_ib_ucontext *c; 4241 u64 mmap_offset; 4242 u32 flags = 0; 4243 u32 length; 4244 int err; 4245 4246 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4247 if (IS_ERR(c)) 4248 return PTR_ERR(c); 4249 4250 err = uverbs_get_flags32(&flags, attrs, 4251 MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4252 MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP); 4253 if (err) 4254 return err; 4255 4256 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) { 4257 if (!MLX5_CAP_GEN(to_mdev(c->ibucontext.device)->mdev, 4258 tlp_device_emulation_manager)) 4259 return -EOPNOTSUPP; 4260 } else { 4261 if (!(MLX5_CAP_GEN_64(to_mdev(c->ibucontext.device)->mdev, 4262 general_obj_types) & 4263 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q)) 4264 return -EOPNOTSUPP; 4265 } 4266 4267 entry = alloc_var_entry(c, flags); 4268 if (IS_ERR(entry)) 4269 return PTR_ERR(entry); 4270 4271 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4272 length = entry->rdma_entry.npages * PAGE_SIZE; 4273 uobj->object = entry; 4274 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4275 4276 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4277 &mmap_offset, sizeof(mmap_offset)); 4278 if (err) 4279 return err; 4280 4281 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4282 &entry->page_idx, sizeof(entry->page_idx)); 4283 if (err) 4284 return err; 4285 4286 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4287 &length, sizeof(length)); 4288 return err; 4289 } 4290 4291 DECLARE_UVERBS_NAMED_METHOD( 4292 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 4293 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 4294 MLX5_IB_OBJECT_VAR, 4295 UVERBS_ACCESS_NEW, 4296 UA_MANDATORY), 4297 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4298 enum mlx5_ib_uapi_var_alloc_flags, 4299 UA_OPTIONAL), 4300 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4301 UVERBS_ATTR_TYPE(u32), 4302 UA_MANDATORY), 4303 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4304 UVERBS_ATTR_TYPE(u32), 4305 UA_MANDATORY), 4306 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4307 UVERBS_ATTR_TYPE(u64), 4308 UA_MANDATORY)); 4309 4310 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4311 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 4312 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 4313 MLX5_IB_OBJECT_VAR, 4314 UVERBS_ACCESS_DESTROY, 4315 UA_MANDATORY)); 4316 4317 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 4318 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4319 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 4320 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 4321 4322 static bool var_is_supported(struct ib_device *device) 4323 { 4324 struct mlx5_ib_dev *dev = to_mdev(device); 4325 4326 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4327 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) || 4328 MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager); 4329 } 4330 4331 static struct mlx5_user_mmap_entry * 4332 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4333 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4334 { 4335 struct mlx5_user_mmap_entry *entry; 4336 struct mlx5_ib_dev *dev; 4337 u32 uar_index; 4338 int err; 4339 4340 entry = kzalloc_obj(*entry); 4341 if (!entry) 4342 return ERR_PTR(-ENOMEM); 4343 4344 dev = to_mdev(c->ibucontext.device); 4345 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4346 if (err) 4347 goto end; 4348 4349 entry->page_idx = uar_index; 4350 entry->address = uar_index2paddress(dev, uar_index); 4351 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4352 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4353 else 4354 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4355 4356 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4357 if (err) 4358 goto err_insert; 4359 4360 return entry; 4361 4362 err_insert: 4363 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4364 end: 4365 kfree(entry); 4366 return ERR_PTR(err); 4367 } 4368 4369 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4370 struct uverbs_attr_bundle *attrs) 4371 { 4372 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4373 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4374 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4375 struct mlx5_ib_ucontext *c; 4376 struct mlx5_user_mmap_entry *entry; 4377 u64 mmap_offset; 4378 u32 length; 4379 int err; 4380 4381 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4382 if (IS_ERR(c)) 4383 return PTR_ERR(c); 4384 4385 err = uverbs_get_const(&alloc_type, attrs, 4386 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4387 if (err) 4388 return err; 4389 4390 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4391 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4392 return -EOPNOTSUPP; 4393 4394 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4395 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4396 return -EOPNOTSUPP; 4397 4398 entry = alloc_uar_entry(c, alloc_type); 4399 if (IS_ERR(entry)) 4400 return PTR_ERR(entry); 4401 4402 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4403 length = entry->rdma_entry.npages * PAGE_SIZE; 4404 uobj->object = entry; 4405 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4406 4407 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4408 &mmap_offset, sizeof(mmap_offset)); 4409 if (err) 4410 return err; 4411 4412 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4413 &entry->page_idx, sizeof(entry->page_idx)); 4414 if (err) 4415 return err; 4416 4417 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4418 &length, sizeof(length)); 4419 return err; 4420 } 4421 4422 DECLARE_UVERBS_NAMED_METHOD( 4423 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4424 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4425 MLX5_IB_OBJECT_UAR, 4426 UVERBS_ACCESS_NEW, 4427 UA_MANDATORY), 4428 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4429 enum mlx5_ib_uapi_uar_alloc_type, 4430 UA_MANDATORY), 4431 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4432 UVERBS_ATTR_TYPE(u32), 4433 UA_MANDATORY), 4434 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4435 UVERBS_ATTR_TYPE(u32), 4436 UA_MANDATORY), 4437 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4438 UVERBS_ATTR_TYPE(u64), 4439 UA_MANDATORY)); 4440 4441 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4442 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4443 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4444 MLX5_IB_OBJECT_UAR, 4445 UVERBS_ACCESS_DESTROY, 4446 UA_MANDATORY)); 4447 4448 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4449 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4450 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4451 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4452 4453 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4454 mlx5_ib_query_context, 4455 UVERBS_OBJECT_DEVICE, 4456 UVERBS_METHOD_QUERY_CONTEXT, 4457 UVERBS_ATTR_PTR_OUT( 4458 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4459 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4460 dump_fill_mkey), 4461 UA_MANDATORY)); 4462 4463 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4464 mlx5_ib_reg_dmabuf_mr, 4465 UVERBS_OBJECT_MR, 4466 UVERBS_METHOD_REG_DMABUF_MR, 4467 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4468 enum mlx5_ib_uapi_reg_dmabuf_flags, 4469 UA_OPTIONAL)); 4470 4471 static const struct uapi_definition mlx5_ib_defs[] = { 4472 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4473 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4474 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4475 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4476 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4477 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4478 UAPI_DEF_CHAIN(mlx5_ib_create_qp_defs), 4479 UAPI_DEF_CHAIN(mlx5_ib_create_srq_defs), 4480 4481 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4482 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4483 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4484 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4485 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4486 {} 4487 }; 4488 4489 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4490 { 4491 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx); 4492 mlx5_ib_data_direct_cleanup(dev); 4493 mlx5_ib_cleanup_multiport_master(dev); 4494 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4495 mutex_destroy(&dev->cap_mask_mutex); 4496 WARN_ON(!xa_empty(&dev->sig_mrs)); 4497 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4498 mlx5r_macsec_dealloc_gids(dev); 4499 } 4500 4501 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4502 { 4503 struct mlx5_core_dev *mdev = dev->mdev; 4504 int err, i; 4505 4506 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4507 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4508 dev->ib_dev.dev.parent = mdev->device; 4509 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4510 4511 for (i = 0; i < dev->num_ports; i++) { 4512 spin_lock_init(&dev->port[i].mp.mpi_lock); 4513 dev->port[i].roce.dev = dev; 4514 dev->port[i].roce.native_port_num = i + 1; 4515 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4516 } 4517 4518 mutex_init(&dev->lb.mutex); 4519 4520 err = mlx5r_cmd_query_special_mkeys(dev); 4521 if (err) 4522 return err; 4523 4524 err = mlx5r_macsec_init_gids_and_devlist(dev); 4525 if (err) 4526 return err; 4527 4528 err = mlx5_ib_init_multiport_master(dev); 4529 if (err) 4530 goto err; 4531 4532 err = set_has_smi_cap(dev); 4533 if (err) 4534 goto err_mp; 4535 4536 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4537 if (err) 4538 goto err_mp; 4539 4540 if (mlx5_use_mad_ifc(dev)) 4541 get_ext_port_caps(dev); 4542 4543 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4544 4545 mutex_init(&dev->cap_mask_mutex); 4546 mutex_init(&dev->data_direct_lock); 4547 INIT_LIST_HEAD(&dev->qp_list); 4548 spin_lock_init(&dev->reset_flow_resource_lock); 4549 xa_init(&dev->odp_mkeys); 4550 xa_init(&dev->sig_mrs); 4551 atomic_set(&dev->mkey_var, 0); 4552 4553 spin_lock_init(&dev->dm.lock); 4554 dev->dm.dev = mdev; 4555 err = mlx5_ib_data_direct_init(dev); 4556 if (err) 4557 goto err_mp; 4558 4559 err = pcim_p2pdma_init(mdev->pdev); 4560 if (err && err != -EOPNOTSUPP) 4561 goto err_dd; 4562 4563 mlx5_cmd_init_async_ctx(mdev, &dev->async_ctx); 4564 4565 return 0; 4566 err_dd: 4567 mlx5_ib_data_direct_cleanup(dev); 4568 err_mp: 4569 mlx5_ib_cleanup_multiport_master(dev); 4570 err: 4571 mlx5r_macsec_dealloc_gids(dev); 4572 return err; 4573 } 4574 4575 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4576 enum rdma_nl_dev_type type, 4577 const char *name); 4578 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4579 4580 static const struct ib_device_ops mlx5_ib_dev_ops = { 4581 .owner = THIS_MODULE, 4582 .driver_id = RDMA_DRIVER_MLX5, 4583 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4584 4585 .add_gid = mlx5_ib_add_gid, 4586 .add_sub_dev = mlx5_ib_add_sub_dev, 4587 .alloc_mr = mlx5_ib_alloc_mr, 4588 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4589 .alloc_pd = mlx5_ib_alloc_pd, 4590 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4591 .attach_mcast = mlx5_ib_mcg_attach, 4592 .check_mr_status = mlx5_ib_check_mr_status, 4593 .create_ah = mlx5_ib_create_ah, 4594 .create_cq = mlx5_ib_create_cq, 4595 .create_user_cq = mlx5_ib_create_user_cq, 4596 .create_qp = mlx5_ib_create_qp, 4597 .create_srq = mlx5_ib_create_srq, 4598 .create_user_ah = mlx5_ib_create_ah, 4599 .dealloc_pd = mlx5_ib_dealloc_pd, 4600 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4601 .del_gid = mlx5_ib_del_gid, 4602 .del_sub_dev = mlx5_ib_del_sub_dev, 4603 .dereg_mr = mlx5_ib_dereg_mr, 4604 .destroy_ah = mlx5_ib_destroy_ah, 4605 .destroy_cq = mlx5_ib_destroy_cq, 4606 .destroy_qp = mlx5_ib_destroy_qp, 4607 .destroy_srq = mlx5_ib_destroy_srq, 4608 .detach_mcast = mlx5_ib_mcg_detach, 4609 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4610 .drain_rq = mlx5_ib_drain_rq, 4611 .drain_sq = mlx5_ib_drain_sq, 4612 .device_group = &mlx5_attr_group, 4613 .get_dev_fw_str = get_dev_fw_str, 4614 .get_dma_mr = mlx5_ib_get_dma_mr, 4615 .get_link_layer = mlx5_ib_port_link_layer, 4616 .map_mr_sg = mlx5_ib_map_mr_sg, 4617 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4618 .mmap = mlx5_ib_mmap, 4619 .mmap_free = mlx5_ib_mmap_free, 4620 .mmap_get_pfns = mlx5_ib_mmap_get_pfns, 4621 .modify_cq = mlx5_ib_modify_cq, 4622 .modify_device = mlx5_ib_modify_device, 4623 .modify_port = mlx5_ib_modify_port, 4624 .modify_qp = mlx5_ib_modify_qp, 4625 .modify_srq = mlx5_ib_modify_srq, 4626 .pgoff_to_mmap_entry = mlx5_ib_pgoff_to_mmap_entry, 4627 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4628 .poll_cq = mlx5_ib_poll_cq, 4629 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4630 .post_recv = mlx5_ib_post_recv_nodrain, 4631 .post_send = mlx5_ib_post_send_nodrain, 4632 .post_srq_recv = mlx5_ib_post_srq_recv, 4633 .process_mad = mlx5_ib_process_mad, 4634 .query_ah = mlx5_ib_query_ah, 4635 .query_device = mlx5_ib_query_device, 4636 .query_gid = mlx5_ib_query_gid, 4637 .query_pkey = mlx5_ib_query_pkey, 4638 .query_port_speed = mlx5_ib_query_port_speed, 4639 .query_qp = mlx5_ib_query_qp, 4640 .query_srq = mlx5_ib_query_srq, 4641 .query_ucontext = mlx5_ib_query_ucontext, 4642 .reg_user_mr = mlx5_ib_reg_user_mr, 4643 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4644 .req_notify_cq = mlx5_ib_arm_cq, 4645 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4646 .resize_user_cq = mlx5_ib_resize_cq, 4647 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4648 4649 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4650 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4651 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4652 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4653 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4654 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4655 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4656 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4657 }; 4658 4659 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4660 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4661 }; 4662 4663 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4664 .get_vf_config = mlx5_ib_get_vf_config, 4665 .get_vf_guid = mlx5_ib_get_vf_guid, 4666 .get_vf_stats = mlx5_ib_get_vf_stats, 4667 .set_vf_guid = mlx5_ib_set_vf_guid, 4668 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4669 }; 4670 4671 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4672 .alloc_mw = mlx5_ib_alloc_mw, 4673 .dealloc_mw = mlx5_ib_dealloc_mw, 4674 4675 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4676 }; 4677 4678 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4679 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4680 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4681 4682 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4683 }; 4684 4685 static int mlx5_ib_init_var_region(struct mlx5_ib_dev *dev) 4686 { 4687 struct mlx5_var_region *var_region = &dev->var_table.var_region; 4688 struct mlx5_core_dev *mdev = dev->mdev; 4689 u8 log_doorbell_bar_size; 4690 u8 log_doorbell_stride; 4691 u64 bar_size; 4692 4693 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4694 log_doorbell_bar_size); 4695 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4696 log_doorbell_stride); 4697 var_region->hw_start_addr = dev->mdev->bar_addr + 4698 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4699 doorbell_bar_offset); 4700 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4701 var_region->stride_size = 1ULL << log_doorbell_stride; 4702 var_region->num_var_hw_entries = div_u64(bar_size, 4703 var_region->stride_size); 4704 mutex_init(&var_region->bitmap_lock); 4705 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4706 GFP_KERNEL); 4707 return (var_region->bitmap) ? 0 : -ENOMEM; 4708 } 4709 4710 static int mlx5_ib_init_tlp_var_region(struct mlx5_ib_dev *dev) 4711 { 4712 struct mlx5_var_region *var_region = &dev->var_table.tlp_var_region; 4713 struct mlx5_core_dev *mdev = dev->mdev; 4714 u8 log_tlp_var_stride; 4715 4716 log_tlp_var_stride = 4717 MLX5_CAP_DEV_TLP_EMULATION(mdev, log_tlp_rsp_gw_page_stride); 4718 var_region->hw_start_addr = 4719 dev->mdev->bar_addr + 4720 MLX5_CAP64_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_pages_bar_offset); 4721 4722 var_region->stride_size = (1ULL << log_tlp_var_stride) * 4096; 4723 var_region->num_var_hw_entries = 4724 MLX5_CAP_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_num_pages); 4725 4726 mutex_init(&var_region->bitmap_lock); 4727 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4728 GFP_KERNEL); 4729 return (var_region->bitmap) ? 0 : -ENOMEM; 4730 } 4731 4732 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4733 { 4734 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4735 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4736 4737 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4738 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4739 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4740 } 4741 4742 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4743 { 4744 int ret; 4745 4746 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4747 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4748 if (ret) 4749 return ret; 4750 } 4751 4752 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4753 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4754 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4755 if (ret) 4756 goto remove_local; 4757 } 4758 4759 return 0; 4760 4761 remove_local: 4762 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4763 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4764 return ret; 4765 } 4766 4767 static void mlx5_ib_cleanup_var_table(struct mlx5_ib_dev *dev) 4768 { 4769 bitmap_free(dev->var_table.var_region.bitmap); 4770 bitmap_free(dev->var_table.tlp_var_region.bitmap); 4771 } 4772 4773 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4774 { 4775 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4776 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4777 mlx5_ib_cleanup_ucaps(dev); 4778 4779 mlx5_ib_cleanup_var_table(dev); 4780 } 4781 4782 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4783 { 4784 struct mlx5_core_dev *mdev = dev->mdev; 4785 int err; 4786 4787 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4788 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4789 ib_set_device_ops(&dev->ib_dev, 4790 &mlx5_ib_dev_ipoib_enhanced_ops); 4791 4792 if (mlx5_core_is_pf(mdev)) 4793 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4794 4795 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4796 4797 if (MLX5_CAP_GEN(mdev, imaicl)) 4798 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4799 4800 if (MLX5_CAP_GEN(mdev, xrc)) 4801 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4802 4803 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4804 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4805 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4806 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4807 4808 if (mdev->st) 4809 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4810 4811 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4812 4813 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4814 dev->ib_dev.driver_def = mlx5_ib_defs; 4815 4816 err = init_node_data(dev); 4817 if (err) 4818 return err; 4819 4820 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4821 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4822 err = mlx5_ib_init_var_region(dev); 4823 if (err) 4824 return err; 4825 } 4826 4827 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4828 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4829 err = mlx5_ib_init_ucaps(dev); 4830 if (err) 4831 goto err_ucaps; 4832 } 4833 4834 if (MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager)) { 4835 err = mlx5_ib_init_tlp_var_region(dev); 4836 if (err) 4837 goto err_tlp_var; 4838 } 4839 4840 dev->ib_dev.use_cq_dim = true; 4841 4842 return 0; 4843 4844 err_tlp_var: 4845 mlx5_ib_cleanup_ucaps(dev); 4846 err_ucaps: 4847 bitmap_free(dev->var_table.var_region.bitmap); 4848 return err; 4849 } 4850 4851 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4852 .get_port_immutable = mlx5_port_immutable, 4853 .query_port = mlx5_ib_query_port, 4854 }; 4855 4856 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4857 { 4858 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4859 return 0; 4860 } 4861 4862 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4863 .get_port_immutable = mlx5_port_rep_immutable, 4864 .query_port = mlx5_ib_rep_query_port, 4865 .query_pkey = mlx5_ib_rep_query_pkey, 4866 }; 4867 4868 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4869 { 4870 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4871 return 0; 4872 } 4873 4874 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4875 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4876 .create_wq = mlx5_ib_create_wq, 4877 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4878 .destroy_wq = mlx5_ib_destroy_wq, 4879 .modify_wq = mlx5_ib_modify_wq, 4880 4881 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4882 ib_rwq_ind_tbl), 4883 }; 4884 4885 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4886 { 4887 struct mlx5_core_dev *mdev = dev->mdev; 4888 enum rdma_link_layer ll; 4889 int port_type_cap; 4890 u32 port_num = 0; 4891 int err; 4892 4893 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4894 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4895 4896 if (ll == IB_LINK_LAYER_ETHERNET) { 4897 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4898 4899 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4900 4901 /* Register only for native ports */ 4902 mlx5_mdev_netdev_track(dev, port_num); 4903 4904 err = mlx5_enable_eth(dev); 4905 if (err) 4906 goto cleanup; 4907 } 4908 4909 return 0; 4910 cleanup: 4911 mlx5_mdev_netdev_untrack(dev, port_num); 4912 return err; 4913 } 4914 4915 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4916 { 4917 struct mlx5_core_dev *mdev = dev->mdev; 4918 enum rdma_link_layer ll; 4919 int port_type_cap; 4920 u32 port_num; 4921 4922 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4923 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4924 4925 if (ll == IB_LINK_LAYER_ETHERNET) { 4926 mlx5_disable_eth(dev); 4927 4928 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4929 mlx5_mdev_netdev_untrack(dev, port_num); 4930 } 4931 } 4932 4933 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4934 { 4935 mlx5_ib_init_cong_debugfs(dev, 4936 mlx5_core_native_port_num(dev->mdev) - 1); 4937 return 0; 4938 } 4939 4940 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4941 { 4942 mlx5_ib_cleanup_cong_debugfs(dev, 4943 mlx5_core_native_port_num(dev->mdev) - 1); 4944 } 4945 4946 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4947 { 4948 int err; 4949 4950 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4951 if (err) 4952 return err; 4953 4954 if (MLX5_CAP_GEN(dev->mdev, qp_latency_sensitive_disable)) 4955 return 0; 4956 4957 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4958 if (err) 4959 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4960 4961 return err; 4962 } 4963 4964 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4965 { 4966 if (!MLX5_CAP_GEN(dev->mdev, qp_latency_sensitive_disable)) 4967 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4968 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4969 } 4970 4971 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4972 { 4973 const char *name; 4974 4975 if (dev->sub_dev_name) { 4976 name = dev->sub_dev_name; 4977 ib_mark_name_assigned_by_user(&dev->ib_dev); 4978 } else if (!mlx5_lag_is_active(dev->mdev)) 4979 name = "mlx5_%d"; 4980 else 4981 name = "mlx5_bond_%d"; 4982 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4983 } 4984 4985 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4986 { 4987 mlx5r_frmr_pools_cleanup(&dev->ib_dev); 4988 mlx5r_umr_resource_cleanup(dev); 4989 mlx5r_umr_cleanup(dev); 4990 } 4991 4992 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4993 { 4994 ib_unregister_device(&dev->ib_dev); 4995 } 4996 4997 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4998 { 4999 int ret; 5000 5001 ret = mlx5r_umr_init(dev); 5002 if (ret) 5003 return ret; 5004 5005 ret = mlx5r_frmr_pools_init(&dev->ib_dev); 5006 if (ret) 5007 mlx5_ib_warn(dev, "frmr pools init failed %d\n", ret); 5008 5009 return ret; 5010 } 5011 5012 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5013 { 5014 struct dentry *root; 5015 5016 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5017 return 0; 5018 5019 mutex_init(&dev->delay_drop.lock); 5020 dev->delay_drop.dev = dev; 5021 dev->delay_drop.activate = false; 5022 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5023 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5024 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5025 atomic_set(&dev->delay_drop.events_cnt, 0); 5026 5027 if (!mlx5_debugfs_root) 5028 return 0; 5029 5030 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 5031 dev->delay_drop.dir_debugfs = root; 5032 5033 debugfs_create_atomic_t("num_timeout_events", 0400, root, 5034 &dev->delay_drop.events_cnt); 5035 debugfs_create_atomic_t("num_rqs", 0400, root, 5036 &dev->delay_drop.rqs_cnt); 5037 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 5038 &fops_delay_drop_timeout); 5039 return 0; 5040 } 5041 5042 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5043 { 5044 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5045 return; 5046 5047 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5048 if (!dev->delay_drop.dir_debugfs) 5049 return; 5050 5051 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 5052 dev->delay_drop.dir_debugfs = NULL; 5053 } 5054 5055 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 5056 { 5057 struct mlx5_ib_resources *devr = &dev->devr; 5058 int port; 5059 5060 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5061 INIT_WORK(&devr->ports[port].pkey_change_work, 5062 pkey_change_handler); 5063 5064 dev->mdev_events.notifier_call = mlx5_ib_event; 5065 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 5066 5067 mlx5r_macsec_event_register(dev); 5068 5069 return 0; 5070 } 5071 5072 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 5073 { 5074 struct mlx5_ib_resources *devr = &dev->devr; 5075 int port; 5076 5077 mlx5r_macsec_event_unregister(dev); 5078 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 5079 5080 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5081 cancel_work_sync(&devr->ports[port].pkey_change_work); 5082 } 5083 5084 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 5085 struct mlx5_data_direct_dev *dev) 5086 { 5087 mutex_lock(&ibdev->data_direct_lock); 5088 ibdev->data_direct_dev = dev; 5089 mutex_unlock(&ibdev->data_direct_lock); 5090 } 5091 5092 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 5093 { 5094 mutex_lock(&ibdev->data_direct_lock); 5095 mlx5_ib_revoke_data_direct_mrs(ibdev); 5096 ibdev->data_direct_dev = NULL; 5097 mutex_unlock(&ibdev->data_direct_lock); 5098 } 5099 5100 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5101 const struct mlx5_ib_profile *profile, 5102 int stage) 5103 { 5104 dev->ib_active = false; 5105 5106 /* Number of stages to cleanup */ 5107 while (stage) { 5108 stage--; 5109 if (profile->stage[stage].cleanup) 5110 profile->stage[stage].cleanup(dev); 5111 } 5112 5113 kfree(dev->port); 5114 ib_dealloc_device(&dev->ib_dev); 5115 } 5116 5117 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 5118 const struct mlx5_ib_profile *profile) 5119 { 5120 int err; 5121 int i; 5122 5123 dev->profile = profile; 5124 5125 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5126 if (profile->stage[i].init) { 5127 err = profile->stage[i].init(dev); 5128 if (err) 5129 goto err_out; 5130 } 5131 } 5132 5133 dev->ib_active = true; 5134 return 0; 5135 5136 err_out: 5137 /* Clean up stages which were initialized */ 5138 while (i) { 5139 i--; 5140 if (profile->stage[i].cleanup) 5141 profile->stage[i].cleanup(dev); 5142 } 5143 return err; 5144 } 5145 5146 static const struct mlx5_ib_profile pf_profile = { 5147 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5148 mlx5_ib_stage_init_init, 5149 mlx5_ib_stage_init_cleanup), 5150 STAGE_CREATE(MLX5_IB_STAGE_FS, 5151 mlx5_ib_fs_init, 5152 mlx5_ib_fs_cleanup), 5153 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5154 mlx5_ib_stage_caps_init, 5155 mlx5_ib_stage_caps_cleanup), 5156 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5157 mlx5_ib_stage_non_default_cb, 5158 NULL), 5159 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5160 mlx5_ib_roce_init, 5161 mlx5_ib_roce_cleanup), 5162 STAGE_CREATE(MLX5_IB_STAGE_QP, 5163 mlx5_init_qp_table, 5164 mlx5_cleanup_qp_table), 5165 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5166 mlx5_init_srq_table, 5167 mlx5_cleanup_srq_table), 5168 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5169 mlx5_ib_dev_res_init, 5170 mlx5_ib_dev_res_cleanup), 5171 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5172 mlx5_ib_odp_init_one, 5173 mlx5_ib_odp_cleanup_one), 5174 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5175 mlx5_ib_counters_init, 5176 mlx5_ib_counters_cleanup), 5177 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5178 mlx5_ib_stage_cong_debugfs_init, 5179 mlx5_ib_stage_cong_debugfs_cleanup), 5180 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5181 mlx5_ib_stage_bfrag_init, 5182 mlx5_ib_stage_bfrag_cleanup), 5183 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5184 NULL, 5185 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5186 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5187 mlx5_ib_devx_init, 5188 mlx5_ib_devx_cleanup), 5189 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5190 mlx5_ib_stage_sys_error_notifier_init, 5191 mlx5_ib_stage_sys_error_notifier_cleanup), 5192 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5193 mlx5_ib_stage_ib_reg_init, 5194 mlx5_ib_stage_ib_reg_cleanup), 5195 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5196 mlx5_ib_stage_dev_notifier_init, 5197 mlx5_ib_stage_dev_notifier_cleanup), 5198 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5199 mlx5_ib_stage_post_ib_reg_umr_init, 5200 NULL), 5201 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5202 mlx5_ib_stage_delay_drop_init, 5203 mlx5_ib_stage_delay_drop_cleanup), 5204 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5205 mlx5_ib_restrack_init, 5206 NULL), 5207 }; 5208 5209 const struct mlx5_ib_profile raw_eth_profile = { 5210 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5211 mlx5_ib_stage_init_init, 5212 mlx5_ib_stage_init_cleanup), 5213 STAGE_CREATE(MLX5_IB_STAGE_FS, 5214 mlx5_ib_fs_init, 5215 mlx5_ib_fs_cleanup), 5216 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5217 mlx5_ib_stage_caps_init, 5218 mlx5_ib_stage_caps_cleanup), 5219 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5220 mlx5_ib_stage_raw_eth_non_default_cb, 5221 NULL), 5222 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5223 mlx5_ib_roce_init, 5224 mlx5_ib_roce_cleanup), 5225 STAGE_CREATE(MLX5_IB_STAGE_QP, 5226 mlx5_init_qp_table, 5227 mlx5_cleanup_qp_table), 5228 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5229 mlx5_init_srq_table, 5230 mlx5_cleanup_srq_table), 5231 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5232 mlx5_ib_dev_res_init, 5233 mlx5_ib_dev_res_cleanup), 5234 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5235 mlx5_ib_counters_init, 5236 mlx5_ib_counters_cleanup), 5237 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5238 mlx5_ib_stage_cong_debugfs_init, 5239 mlx5_ib_stage_cong_debugfs_cleanup), 5240 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5241 mlx5_ib_stage_bfrag_init, 5242 mlx5_ib_stage_bfrag_cleanup), 5243 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5244 NULL, 5245 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5246 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5247 mlx5_ib_devx_init, 5248 mlx5_ib_devx_cleanup), 5249 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5250 mlx5_ib_stage_sys_error_notifier_init, 5251 mlx5_ib_stage_sys_error_notifier_cleanup), 5252 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5253 mlx5_ib_stage_ib_reg_init, 5254 mlx5_ib_stage_ib_reg_cleanup), 5255 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5256 mlx5_ib_stage_dev_notifier_init, 5257 mlx5_ib_stage_dev_notifier_cleanup), 5258 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5259 mlx5_ib_stage_post_ib_reg_umr_init, 5260 NULL), 5261 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5262 mlx5_ib_stage_delay_drop_init, 5263 mlx5_ib_stage_delay_drop_cleanup), 5264 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5265 mlx5_ib_restrack_init, 5266 NULL), 5267 }; 5268 5269 static const struct mlx5_ib_profile plane_profile = { 5270 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5271 mlx5_ib_stage_init_init, 5272 mlx5_ib_stage_init_cleanup), 5273 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5274 mlx5_ib_stage_caps_init, 5275 mlx5_ib_stage_caps_cleanup), 5276 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5277 mlx5_ib_stage_non_default_cb, 5278 NULL), 5279 STAGE_CREATE(MLX5_IB_STAGE_QP, 5280 mlx5_init_qp_table, 5281 mlx5_cleanup_qp_table), 5282 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5283 mlx5_init_srq_table, 5284 mlx5_cleanup_srq_table), 5285 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5286 mlx5_ib_dev_res_init, 5287 mlx5_ib_dev_res_cleanup), 5288 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5289 mlx5_ib_stage_bfrag_init, 5290 mlx5_ib_stage_bfrag_cleanup), 5291 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5292 mlx5_ib_stage_ib_reg_init, 5293 mlx5_ib_stage_ib_reg_cleanup), 5294 }; 5295 5296 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 5297 enum rdma_nl_dev_type type, 5298 const char *name) 5299 { 5300 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 5301 enum rdma_link_layer ll; 5302 int ret; 5303 5304 if (mparent->smi_dev) 5305 return ERR_PTR(-EEXIST); 5306 5307 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 5308 port_type)); 5309 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 5310 ll != IB_LINK_LAYER_INFINIBAND || 5311 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 5312 return ERR_PTR(-EOPNOTSUPP); 5313 5314 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5315 mlx5_core_net(mparent->mdev)); 5316 if (!mplane) 5317 return ERR_PTR(-ENOMEM); 5318 5319 mplane->port = kzalloc_objs(*mplane->port, 5320 mparent->num_plane * mparent->num_ports); 5321 if (!mplane->port) { 5322 ret = -ENOMEM; 5323 goto fail_kcalloc; 5324 } 5325 5326 mplane->ib_dev.type = type; 5327 mplane->mdev = mparent->mdev; 5328 mplane->num_ports = mparent->num_plane; 5329 mplane->sub_dev_name = name; 5330 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 5331 5332 ret = __mlx5_ib_add(mplane, &plane_profile); 5333 if (ret) 5334 goto fail_ib_add; 5335 5336 mparent->smi_dev = mplane; 5337 return &mplane->ib_dev; 5338 5339 fail_ib_add: 5340 kfree(mplane->port); 5341 fail_kcalloc: 5342 ib_dealloc_device(&mplane->ib_dev); 5343 return ERR_PTR(ret); 5344 } 5345 5346 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 5347 { 5348 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 5349 5350 to_mdev(sub_dev->parent)->smi_dev = NULL; 5351 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 5352 } 5353 5354 static int mlx5r_mp_probe(struct auxiliary_device *adev, 5355 const struct auxiliary_device_id *id) 5356 { 5357 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5358 struct mlx5_core_dev *mdev = idev->mdev; 5359 struct mlx5_ib_multiport_info *mpi; 5360 struct mlx5_ib_dev *dev; 5361 bool bound = false; 5362 int err; 5363 5364 mpi = kzalloc_obj(*mpi); 5365 if (!mpi) 5366 return -ENOMEM; 5367 5368 mpi->mdev = mdev; 5369 err = mlx5_query_nic_vport_system_image_guid(mdev, 5370 &mpi->sys_image_guid); 5371 if (err) { 5372 kfree(mpi); 5373 return err; 5374 } 5375 5376 mutex_lock(&mlx5_ib_multiport_mutex); 5377 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5378 if (dev->sys_image_guid == mpi->sys_image_guid && 5379 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 5380 bound = mlx5_ib_bind_slave_port(dev, mpi); 5381 5382 if (bound) { 5383 rdma_roce_rescan_device(&dev->ib_dev); 5384 mpi->ibdev->ib_active = true; 5385 break; 5386 } 5387 } 5388 5389 if (!bound) { 5390 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5391 dev_dbg(mdev->device, 5392 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5393 } 5394 mutex_unlock(&mlx5_ib_multiport_mutex); 5395 5396 auxiliary_set_drvdata(adev, mpi); 5397 return 0; 5398 } 5399 5400 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5401 { 5402 struct mlx5_ib_multiport_info *mpi; 5403 5404 mpi = auxiliary_get_drvdata(adev); 5405 mutex_lock(&mlx5_ib_multiport_mutex); 5406 if (mpi->ibdev) 5407 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5408 else 5409 list_del(&mpi->list); 5410 mutex_unlock(&mlx5_ib_multiport_mutex); 5411 kfree(mpi); 5412 } 5413 5414 static int mlx5r_probe(struct auxiliary_device *adev, 5415 const struct auxiliary_device_id *id) 5416 { 5417 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5418 struct mlx5_core_dev *mdev = idev->mdev; 5419 const struct mlx5_ib_profile *profile; 5420 int port_type_cap, num_ports, ret; 5421 enum rdma_link_layer ll; 5422 struct mlx5_ib_dev *dev; 5423 5424 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5425 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5426 5427 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5428 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5429 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5430 mlx5_core_net(mdev)); 5431 if (!dev) 5432 return -ENOMEM; 5433 5434 if (ll == IB_LINK_LAYER_INFINIBAND) { 5435 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5436 if (ret) 5437 goto fail; 5438 } 5439 5440 dev->port = kzalloc_objs(*dev->port, num_ports); 5441 if (!dev->port) { 5442 ret = -ENOMEM; 5443 goto fail; 5444 } 5445 5446 dev->mdev = mdev; 5447 dev->num_ports = num_ports; 5448 dev->ib_dev.phys_port_cnt = num_ports; 5449 5450 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5451 profile = &raw_eth_profile; 5452 else 5453 profile = &pf_profile; 5454 5455 ret = __mlx5_ib_add(dev, profile); 5456 if (ret) 5457 goto fail_ib_add; 5458 5459 auxiliary_set_drvdata(adev, dev); 5460 return 0; 5461 5462 fail_ib_add: 5463 kfree(dev->port); 5464 fail: 5465 ib_dealloc_device(&dev->ib_dev); 5466 return ret; 5467 } 5468 5469 static void mlx5r_remove(struct auxiliary_device *adev) 5470 { 5471 struct mlx5_ib_dev *dev; 5472 5473 dev = auxiliary_get_drvdata(adev); 5474 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5475 } 5476 5477 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5478 { .name = MLX5_ADEV_NAME ".multiport", }, 5479 {}, 5480 }; 5481 5482 static const struct auxiliary_device_id mlx5r_id_table[] = { 5483 { .name = MLX5_ADEV_NAME ".rdma", }, 5484 {}, 5485 }; 5486 5487 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5488 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5489 5490 static struct auxiliary_driver mlx5r_mp_driver = { 5491 .name = "multiport", 5492 .probe = mlx5r_mp_probe, 5493 .remove = mlx5r_mp_remove, 5494 .id_table = mlx5r_mp_id_table, 5495 }; 5496 5497 static struct auxiliary_driver mlx5r_driver = { 5498 .name = "rdma", 5499 .probe = mlx5r_probe, 5500 .remove = mlx5r_remove, 5501 .id_table = mlx5r_id_table, 5502 }; 5503 5504 static int __init mlx5_ib_init(void) 5505 { 5506 int ret; 5507 5508 xlt_emergency_page = kmalloc(PAGE_SIZE, GFP_KERNEL); 5509 if (!xlt_emergency_page) 5510 return -ENOMEM; 5511 5512 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5513 if (!mlx5_ib_event_wq) { 5514 kfree(xlt_emergency_page); 5515 return -ENOMEM; 5516 } 5517 5518 ret = mlx5_ib_qp_event_init(); 5519 if (ret) 5520 goto qp_event_err; 5521 5522 mlx5_ib_odp_init(); 5523 ret = mlx5r_rep_init(); 5524 if (ret) 5525 goto rep_err; 5526 ret = mlx5_data_direct_driver_register(); 5527 if (ret) 5528 goto dd_err; 5529 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5530 if (ret) 5531 goto mp_err; 5532 ret = auxiliary_driver_register(&mlx5r_driver); 5533 if (ret) 5534 goto drv_err; 5535 5536 return 0; 5537 5538 drv_err: 5539 auxiliary_driver_unregister(&mlx5r_mp_driver); 5540 mp_err: 5541 mlx5_data_direct_driver_unregister(); 5542 dd_err: 5543 mlx5r_rep_cleanup(); 5544 rep_err: 5545 rcu_barrier(); 5546 mlx5_ib_qp_event_cleanup(); 5547 qp_event_err: 5548 destroy_workqueue(mlx5_ib_event_wq); 5549 kfree(xlt_emergency_page); 5550 return ret; 5551 } 5552 5553 static void __exit mlx5_ib_cleanup(void) 5554 { 5555 mlx5_data_direct_driver_unregister(); 5556 auxiliary_driver_unregister(&mlx5r_driver); 5557 auxiliary_driver_unregister(&mlx5r_mp_driver); 5558 mlx5r_rep_cleanup(); 5559 rcu_barrier(); 5560 5561 mlx5_ib_qp_event_cleanup(); 5562 destroy_workqueue(mlx5_ib_event_wq); 5563 kfree(xlt_emergency_page); 5564 } 5565 5566 module_init(mlx5_ib_init); 5567 module_exit(mlx5_ib_cleanup); 5568