1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "fs.h" 38 #include "srq.h" 39 #include "qp.h" 40 #include "wr.h" 41 #include "restrack.h" 42 #include "counters.h" 43 #include <linux/mlx5/accel.h> 44 #include <rdma/uverbs_std_types.h> 45 #include <rdma/mlx5_user_ioctl_verbs.h> 46 #include <rdma/mlx5_user_ioctl_cmds.h> 47 #include <rdma/ib_umem_odp.h> 48 49 #define UVERBS_MODULE_NAME mlx5_ib 50 #include <rdma/uverbs_named_ioctl.h> 51 52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 53 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 54 MODULE_LICENSE("Dual BSD/GPL"); 55 56 struct mlx5_ib_event_work { 57 struct work_struct work; 58 union { 59 struct mlx5_ib_dev *dev; 60 struct mlx5_ib_multiport_info *mpi; 61 }; 62 bool is_slave; 63 unsigned int event; 64 void *param; 65 }; 66 67 enum { 68 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 69 }; 70 71 static struct workqueue_struct *mlx5_ib_event_wq; 72 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 73 static LIST_HEAD(mlx5_ib_dev_list); 74 /* 75 * This mutex should be held when accessing either of the above lists 76 */ 77 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 78 79 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 80 { 81 struct mlx5_ib_dev *dev; 82 83 mutex_lock(&mlx5_ib_multiport_mutex); 84 dev = mpi->ibdev; 85 mutex_unlock(&mlx5_ib_multiport_mutex); 86 return dev; 87 } 88 89 static enum rdma_link_layer 90 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 91 { 92 switch (port_type_cap) { 93 case MLX5_CAP_PORT_TYPE_IB: 94 return IB_LINK_LAYER_INFINIBAND; 95 case MLX5_CAP_PORT_TYPE_ETH: 96 return IB_LINK_LAYER_ETHERNET; 97 default: 98 return IB_LINK_LAYER_UNSPECIFIED; 99 } 100 } 101 102 static enum rdma_link_layer 103 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 104 { 105 struct mlx5_ib_dev *dev = to_mdev(device); 106 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 107 108 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 109 } 110 111 static int get_port_state(struct ib_device *ibdev, 112 u8 port_num, 113 enum ib_port_state *state) 114 { 115 struct ib_port_attr attr; 116 int ret; 117 118 memset(&attr, 0, sizeof(attr)); 119 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 120 if (!ret) 121 *state = attr.state; 122 return ret; 123 } 124 125 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 126 struct net_device *ndev, 127 u8 *port_num) 128 { 129 struct net_device *rep_ndev; 130 struct mlx5_ib_port *port; 131 int i; 132 133 for (i = 0; i < dev->num_ports; i++) { 134 port = &dev->port[i]; 135 if (!port->rep) 136 continue; 137 138 read_lock(&port->roce.netdev_lock); 139 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 140 port->rep->vport); 141 if (rep_ndev == ndev) { 142 read_unlock(&port->roce.netdev_lock); 143 *port_num = i + 1; 144 return &port->roce; 145 } 146 read_unlock(&port->roce.netdev_lock); 147 } 148 149 return NULL; 150 } 151 152 static int mlx5_netdev_event(struct notifier_block *this, 153 unsigned long event, void *ptr) 154 { 155 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 156 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 157 u8 port_num = roce->native_port_num; 158 struct mlx5_core_dev *mdev; 159 struct mlx5_ib_dev *ibdev; 160 161 ibdev = roce->dev; 162 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 163 if (!mdev) 164 return NOTIFY_DONE; 165 166 switch (event) { 167 case NETDEV_REGISTER: 168 /* Should already be registered during the load */ 169 if (ibdev->is_rep) 170 break; 171 write_lock(&roce->netdev_lock); 172 if (ndev->dev.parent == mdev->device) 173 roce->netdev = ndev; 174 write_unlock(&roce->netdev_lock); 175 break; 176 177 case NETDEV_UNREGISTER: 178 /* In case of reps, ib device goes away before the netdevs */ 179 write_lock(&roce->netdev_lock); 180 if (roce->netdev == ndev) 181 roce->netdev = NULL; 182 write_unlock(&roce->netdev_lock); 183 break; 184 185 case NETDEV_CHANGE: 186 case NETDEV_UP: 187 case NETDEV_DOWN: { 188 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 189 struct net_device *upper = NULL; 190 191 if (lag_ndev) { 192 upper = netdev_master_upper_dev_get(lag_ndev); 193 dev_put(lag_ndev); 194 } 195 196 if (ibdev->is_rep) 197 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 198 if (!roce) 199 return NOTIFY_DONE; 200 if ((upper == ndev || (!upper && ndev == roce->netdev)) 201 && ibdev->ib_active) { 202 struct ib_event ibev = { }; 203 enum ib_port_state port_state; 204 205 if (get_port_state(&ibdev->ib_dev, port_num, 206 &port_state)) 207 goto done; 208 209 if (roce->last_port_state == port_state) 210 goto done; 211 212 roce->last_port_state = port_state; 213 ibev.device = &ibdev->ib_dev; 214 if (port_state == IB_PORT_DOWN) 215 ibev.event = IB_EVENT_PORT_ERR; 216 else if (port_state == IB_PORT_ACTIVE) 217 ibev.event = IB_EVENT_PORT_ACTIVE; 218 else 219 goto done; 220 221 ibev.element.port_num = port_num; 222 ib_dispatch_event(&ibev); 223 } 224 break; 225 } 226 227 default: 228 break; 229 } 230 done: 231 mlx5_ib_put_native_port_mdev(ibdev, port_num); 232 return NOTIFY_DONE; 233 } 234 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 236 u8 port_num) 237 { 238 struct mlx5_ib_dev *ibdev = to_mdev(device); 239 struct net_device *ndev; 240 struct mlx5_core_dev *mdev; 241 242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 243 if (!mdev) 244 return NULL; 245 246 ndev = mlx5_lag_get_roce_netdev(mdev); 247 if (ndev) 248 goto out; 249 250 /* Ensure ndev does not disappear before we invoke dev_hold() 251 */ 252 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 253 ndev = ibdev->port[port_num - 1].roce.netdev; 254 if (ndev) 255 dev_hold(ndev); 256 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 257 258 out: 259 mlx5_ib_put_native_port_mdev(ibdev, port_num); 260 return ndev; 261 } 262 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 264 u8 ib_port_num, 265 u8 *native_port_num) 266 { 267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 268 ib_port_num); 269 struct mlx5_core_dev *mdev = NULL; 270 struct mlx5_ib_multiport_info *mpi; 271 struct mlx5_ib_port *port; 272 273 if (!mlx5_core_mp_enabled(ibdev->mdev) || 274 ll != IB_LINK_LAYER_ETHERNET) { 275 if (native_port_num) 276 *native_port_num = ib_port_num; 277 return ibdev->mdev; 278 } 279 280 if (native_port_num) 281 *native_port_num = 1; 282 283 port = &ibdev->port[ib_port_num - 1]; 284 spin_lock(&port->mp.mpi_lock); 285 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 286 if (mpi && !mpi->unaffiliate) { 287 mdev = mpi->mdev; 288 /* If it's the master no need to refcount, it'll exist 289 * as long as the ib_dev exists. 290 */ 291 if (!mpi->is_master) 292 mpi->mdev_refcnt++; 293 } 294 spin_unlock(&port->mp.mpi_lock); 295 296 return mdev; 297 } 298 299 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 300 { 301 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 302 port_num); 303 struct mlx5_ib_multiport_info *mpi; 304 struct mlx5_ib_port *port; 305 306 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 307 return; 308 309 port = &ibdev->port[port_num - 1]; 310 311 spin_lock(&port->mp.mpi_lock); 312 mpi = ibdev->port[port_num - 1].mp.mpi; 313 if (mpi->is_master) 314 goto out; 315 316 mpi->mdev_refcnt--; 317 if (mpi->unaffiliate) 318 complete(&mpi->unref_comp); 319 out: 320 spin_unlock(&port->mp.mpi_lock); 321 } 322 323 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 324 u16 *active_speed, u8 *active_width) 325 { 326 switch (eth_proto_oper) { 327 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 328 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 329 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 330 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 331 *active_width = IB_WIDTH_1X; 332 *active_speed = IB_SPEED_SDR; 333 break; 334 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 335 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 336 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 341 *active_width = IB_WIDTH_1X; 342 *active_speed = IB_SPEED_QDR; 343 break; 344 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 345 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 346 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 347 *active_width = IB_WIDTH_1X; 348 *active_speed = IB_SPEED_EDR; 349 break; 350 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 351 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 352 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 354 *active_width = IB_WIDTH_4X; 355 *active_speed = IB_SPEED_QDR; 356 break; 357 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 358 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 359 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 360 *active_width = IB_WIDTH_1X; 361 *active_speed = IB_SPEED_HDR; 362 break; 363 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 364 *active_width = IB_WIDTH_4X; 365 *active_speed = IB_SPEED_FDR; 366 break; 367 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 368 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 369 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 371 *active_width = IB_WIDTH_4X; 372 *active_speed = IB_SPEED_EDR; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 return 0; 379 } 380 381 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 382 u8 *active_width) 383 { 384 switch (eth_proto_oper) { 385 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 386 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 387 *active_width = IB_WIDTH_1X; 388 *active_speed = IB_SPEED_SDR; 389 break; 390 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 391 *active_width = IB_WIDTH_1X; 392 *active_speed = IB_SPEED_DDR; 393 break; 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 395 *active_width = IB_WIDTH_1X; 396 *active_speed = IB_SPEED_QDR; 397 break; 398 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 399 *active_width = IB_WIDTH_4X; 400 *active_speed = IB_SPEED_QDR; 401 break; 402 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_EDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 407 *active_width = IB_WIDTH_2X; 408 *active_speed = IB_SPEED_EDR; 409 break; 410 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 411 *active_width = IB_WIDTH_1X; 412 *active_speed = IB_SPEED_HDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 415 *active_width = IB_WIDTH_4X; 416 *active_speed = IB_SPEED_EDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 419 *active_width = IB_WIDTH_2X; 420 *active_speed = IB_SPEED_HDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 423 *active_width = IB_WIDTH_1X; 424 *active_speed = IB_SPEED_NDR; 425 break; 426 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_HDR; 429 break; 430 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 431 *active_width = IB_WIDTH_2X; 432 *active_speed = IB_SPEED_NDR; 433 break; 434 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 435 *active_width = IB_WIDTH_4X; 436 *active_speed = IB_SPEED_NDR; 437 break; 438 default: 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 446 u8 *active_width, bool ext) 447 { 448 return ext ? 449 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 450 active_width) : 451 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 452 active_width); 453 } 454 455 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 456 struct ib_port_attr *props) 457 { 458 struct mlx5_ib_dev *dev = to_mdev(device); 459 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 460 struct mlx5_core_dev *mdev; 461 struct net_device *ndev, *upper; 462 enum ib_mtu ndev_ib_mtu; 463 bool put_mdev = true; 464 u32 eth_prot_oper; 465 u8 mdev_port_num; 466 bool ext; 467 int err; 468 469 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 470 if (!mdev) { 471 /* This means the port isn't affiliated yet. Get the 472 * info for the master port instead. 473 */ 474 put_mdev = false; 475 mdev = dev->mdev; 476 mdev_port_num = 1; 477 port_num = 1; 478 } 479 480 /* Possible bad flows are checked before filling out props so in case 481 * of an error it will still be zeroed out. 482 * Use native port in case of reps 483 */ 484 if (dev->is_rep) 485 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 486 1); 487 else 488 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 489 mdev_port_num); 490 if (err) 491 goto out; 492 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 493 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 494 495 props->active_width = IB_WIDTH_4X; 496 props->active_speed = IB_SPEED_QDR; 497 498 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 499 &props->active_width, ext); 500 501 if (!dev->is_rep && mlx5_is_roce_enabled(mdev)) { 502 u16 qkey_viol_cntr; 503 504 props->port_cap_flags |= IB_PORT_CM_SUP; 505 props->ip_gids = true; 506 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 507 roce_address_table_size); 508 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 509 props->qkey_viol_cntr = qkey_viol_cntr; 510 } 511 props->max_mtu = IB_MTU_4096; 512 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 513 props->pkey_tbl_len = 1; 514 props->state = IB_PORT_DOWN; 515 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 516 517 /* If this is a stub query for an unaffiliated port stop here */ 518 if (!put_mdev) 519 goto out; 520 521 ndev = mlx5_ib_get_netdev(device, port_num); 522 if (!ndev) 523 goto out; 524 525 if (dev->lag_active) { 526 rcu_read_lock(); 527 upper = netdev_master_upper_dev_get_rcu(ndev); 528 if (upper) { 529 dev_put(ndev); 530 ndev = upper; 531 dev_hold(ndev); 532 } 533 rcu_read_unlock(); 534 } 535 536 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 537 props->state = IB_PORT_ACTIVE; 538 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 539 } 540 541 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 542 543 dev_put(ndev); 544 545 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 546 out: 547 if (put_mdev) 548 mlx5_ib_put_native_port_mdev(dev, port_num); 549 return err; 550 } 551 552 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 553 unsigned int index, const union ib_gid *gid, 554 const struct ib_gid_attr *attr) 555 { 556 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 557 u16 vlan_id = 0xffff; 558 u8 roce_version = 0; 559 u8 roce_l3_type = 0; 560 u8 mac[ETH_ALEN]; 561 int ret; 562 563 if (gid) { 564 gid_type = attr->gid_type; 565 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 566 if (ret) 567 return ret; 568 } 569 570 switch (gid_type) { 571 case IB_GID_TYPE_ROCE: 572 roce_version = MLX5_ROCE_VERSION_1; 573 break; 574 case IB_GID_TYPE_ROCE_UDP_ENCAP: 575 roce_version = MLX5_ROCE_VERSION_2; 576 if (ipv6_addr_v4mapped((void *)gid)) 577 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 578 else 579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 580 break; 581 582 default: 583 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 584 } 585 586 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 587 roce_l3_type, gid->raw, mac, 588 vlan_id < VLAN_CFI_MASK, vlan_id, 589 port_num); 590 } 591 592 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 593 __always_unused void **context) 594 { 595 return set_roce_addr(to_mdev(attr->device), attr->port_num, 596 attr->index, &attr->gid, attr); 597 } 598 599 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 600 __always_unused void **context) 601 { 602 return set_roce_addr(to_mdev(attr->device), attr->port_num, 603 attr->index, NULL, NULL); 604 } 605 606 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 607 const struct ib_gid_attr *attr) 608 { 609 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 610 return 0; 611 612 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 613 } 614 615 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 616 { 617 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 618 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 619 return 0; 620 } 621 622 enum { 623 MLX5_VPORT_ACCESS_METHOD_MAD, 624 MLX5_VPORT_ACCESS_METHOD_HCA, 625 MLX5_VPORT_ACCESS_METHOD_NIC, 626 }; 627 628 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 629 { 630 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 631 return MLX5_VPORT_ACCESS_METHOD_MAD; 632 633 if (mlx5_ib_port_link_layer(ibdev, 1) == 634 IB_LINK_LAYER_ETHERNET) 635 return MLX5_VPORT_ACCESS_METHOD_NIC; 636 637 return MLX5_VPORT_ACCESS_METHOD_HCA; 638 } 639 640 static void get_atomic_caps(struct mlx5_ib_dev *dev, 641 u8 atomic_size_qp, 642 struct ib_device_attr *props) 643 { 644 u8 tmp; 645 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 646 u8 atomic_req_8B_endianness_mode = 647 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 648 649 /* Check if HW supports 8 bytes standard atomic operations and capable 650 * of host endianness respond 651 */ 652 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 653 if (((atomic_operations & tmp) == tmp) && 654 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 655 (atomic_req_8B_endianness_mode)) { 656 props->atomic_cap = IB_ATOMIC_HCA; 657 } else { 658 props->atomic_cap = IB_ATOMIC_NONE; 659 } 660 } 661 662 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 663 struct ib_device_attr *props) 664 { 665 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 666 667 get_atomic_caps(dev, atomic_size_qp, props); 668 } 669 670 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 671 __be64 *sys_image_guid) 672 { 673 struct mlx5_ib_dev *dev = to_mdev(ibdev); 674 struct mlx5_core_dev *mdev = dev->mdev; 675 u64 tmp; 676 int err; 677 678 switch (mlx5_get_vport_access_method(ibdev)) { 679 case MLX5_VPORT_ACCESS_METHOD_MAD: 680 return mlx5_query_mad_ifc_system_image_guid(ibdev, 681 sys_image_guid); 682 683 case MLX5_VPORT_ACCESS_METHOD_HCA: 684 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 685 break; 686 687 case MLX5_VPORT_ACCESS_METHOD_NIC: 688 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 689 break; 690 691 default: 692 return -EINVAL; 693 } 694 695 if (!err) 696 *sys_image_guid = cpu_to_be64(tmp); 697 698 return err; 699 700 } 701 702 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 703 u16 *max_pkeys) 704 { 705 struct mlx5_ib_dev *dev = to_mdev(ibdev); 706 struct mlx5_core_dev *mdev = dev->mdev; 707 708 switch (mlx5_get_vport_access_method(ibdev)) { 709 case MLX5_VPORT_ACCESS_METHOD_MAD: 710 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 711 712 case MLX5_VPORT_ACCESS_METHOD_HCA: 713 case MLX5_VPORT_ACCESS_METHOD_NIC: 714 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 715 pkey_table_size)); 716 return 0; 717 718 default: 719 return -EINVAL; 720 } 721 } 722 723 static int mlx5_query_vendor_id(struct ib_device *ibdev, 724 u32 *vendor_id) 725 { 726 struct mlx5_ib_dev *dev = to_mdev(ibdev); 727 728 switch (mlx5_get_vport_access_method(ibdev)) { 729 case MLX5_VPORT_ACCESS_METHOD_MAD: 730 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 731 732 case MLX5_VPORT_ACCESS_METHOD_HCA: 733 case MLX5_VPORT_ACCESS_METHOD_NIC: 734 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 735 736 default: 737 return -EINVAL; 738 } 739 } 740 741 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 742 __be64 *node_guid) 743 { 744 u64 tmp; 745 int err; 746 747 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 748 case MLX5_VPORT_ACCESS_METHOD_MAD: 749 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 750 751 case MLX5_VPORT_ACCESS_METHOD_HCA: 752 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 753 break; 754 755 case MLX5_VPORT_ACCESS_METHOD_NIC: 756 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 757 break; 758 759 default: 760 return -EINVAL; 761 } 762 763 if (!err) 764 *node_guid = cpu_to_be64(tmp); 765 766 return err; 767 } 768 769 struct mlx5_reg_node_desc { 770 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 771 }; 772 773 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 774 { 775 struct mlx5_reg_node_desc in; 776 777 if (mlx5_use_mad_ifc(dev)) 778 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 779 780 memset(&in, 0, sizeof(in)); 781 782 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 783 sizeof(struct mlx5_reg_node_desc), 784 MLX5_REG_NODE_DESC, 0, 0); 785 } 786 787 static int mlx5_ib_query_device(struct ib_device *ibdev, 788 struct ib_device_attr *props, 789 struct ib_udata *uhw) 790 { 791 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 792 struct mlx5_ib_dev *dev = to_mdev(ibdev); 793 struct mlx5_core_dev *mdev = dev->mdev; 794 int err = -ENOMEM; 795 int max_sq_desc; 796 int max_rq_sg; 797 int max_sq_sg; 798 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 799 bool raw_support = !mlx5_core_mp_enabled(mdev); 800 struct mlx5_ib_query_device_resp resp = {}; 801 size_t resp_len; 802 u64 max_tso; 803 804 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 805 if (uhw_outlen && uhw_outlen < resp_len) 806 return -EINVAL; 807 808 resp.response_length = resp_len; 809 810 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 811 return -EINVAL; 812 813 memset(props, 0, sizeof(*props)); 814 err = mlx5_query_system_image_guid(ibdev, 815 &props->sys_image_guid); 816 if (err) 817 return err; 818 819 props->max_pkeys = dev->pkey_table_len; 820 821 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 822 if (err) 823 return err; 824 825 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 826 (fw_rev_min(dev->mdev) << 16) | 827 fw_rev_sub(dev->mdev); 828 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 829 IB_DEVICE_PORT_ACTIVE_EVENT | 830 IB_DEVICE_SYS_IMAGE_GUID | 831 IB_DEVICE_RC_RNR_NAK_GEN; 832 833 if (MLX5_CAP_GEN(mdev, pkv)) 834 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 835 if (MLX5_CAP_GEN(mdev, qkv)) 836 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 837 if (MLX5_CAP_GEN(mdev, apm)) 838 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 839 if (MLX5_CAP_GEN(mdev, xrc)) 840 props->device_cap_flags |= IB_DEVICE_XRC; 841 if (MLX5_CAP_GEN(mdev, imaicl)) { 842 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 843 IB_DEVICE_MEM_WINDOW_TYPE_2B; 844 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 845 /* We support 'Gappy' memory registration too */ 846 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 847 } 848 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 849 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 850 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 851 if (MLX5_CAP_GEN(mdev, sho)) { 852 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 853 /* At this stage no support for signature handover */ 854 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 855 IB_PROT_T10DIF_TYPE_2 | 856 IB_PROT_T10DIF_TYPE_3; 857 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 858 IB_GUARD_T10DIF_CSUM; 859 } 860 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 861 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 862 863 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 864 if (MLX5_CAP_ETH(mdev, csum_cap)) { 865 /* Legacy bit to support old userspace libraries */ 866 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 867 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 868 } 869 870 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 871 props->raw_packet_caps |= 872 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 873 874 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 875 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 876 if (max_tso) { 877 resp.tso_caps.max_tso = 1 << max_tso; 878 resp.tso_caps.supported_qpts |= 879 1 << IB_QPT_RAW_PACKET; 880 resp.response_length += sizeof(resp.tso_caps); 881 } 882 } 883 884 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 885 resp.rss_caps.rx_hash_function = 886 MLX5_RX_HASH_FUNC_TOEPLITZ; 887 resp.rss_caps.rx_hash_fields_mask = 888 MLX5_RX_HASH_SRC_IPV4 | 889 MLX5_RX_HASH_DST_IPV4 | 890 MLX5_RX_HASH_SRC_IPV6 | 891 MLX5_RX_HASH_DST_IPV6 | 892 MLX5_RX_HASH_SRC_PORT_TCP | 893 MLX5_RX_HASH_DST_PORT_TCP | 894 MLX5_RX_HASH_SRC_PORT_UDP | 895 MLX5_RX_HASH_DST_PORT_UDP | 896 MLX5_RX_HASH_INNER; 897 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 898 MLX5_ACCEL_IPSEC_CAP_DEVICE) 899 resp.rss_caps.rx_hash_fields_mask |= 900 MLX5_RX_HASH_IPSEC_SPI; 901 resp.response_length += sizeof(resp.rss_caps); 902 } 903 } else { 904 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 905 resp.response_length += sizeof(resp.tso_caps); 906 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 907 resp.response_length += sizeof(resp.rss_caps); 908 } 909 910 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 911 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 912 props->device_cap_flags |= IB_DEVICE_UD_TSO; 913 } 914 915 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 916 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 917 raw_support) 918 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 919 920 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 921 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 922 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 923 924 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 925 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 926 raw_support) { 927 /* Legacy bit to support old userspace libraries */ 928 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 929 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 930 } 931 932 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 933 props->max_dm_size = 934 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 935 } 936 937 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 938 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 939 940 if (MLX5_CAP_GEN(mdev, end_pad)) 941 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 942 943 props->vendor_part_id = mdev->pdev->device; 944 props->hw_ver = mdev->pdev->revision; 945 946 props->max_mr_size = ~0ull; 947 props->page_size_cap = ~(min_page_size - 1); 948 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 949 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 950 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 951 sizeof(struct mlx5_wqe_data_seg); 952 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 953 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 954 sizeof(struct mlx5_wqe_raddr_seg)) / 955 sizeof(struct mlx5_wqe_data_seg); 956 props->max_send_sge = max_sq_sg; 957 props->max_recv_sge = max_rq_sg; 958 props->max_sge_rd = MLX5_MAX_SGE_RD; 959 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 960 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 961 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 962 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 963 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 964 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 965 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 966 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 967 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 968 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 969 props->max_srq_sge = max_rq_sg - 1; 970 props->max_fast_reg_page_list_len = 971 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 972 props->max_pi_fast_reg_page_list_len = 973 props->max_fast_reg_page_list_len / 2; 974 props->max_sgl_rd = 975 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 976 get_atomic_caps_qp(dev, props); 977 props->masked_atomic_cap = IB_ATOMIC_NONE; 978 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 979 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 980 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 981 props->max_mcast_grp; 982 props->max_ah = INT_MAX; 983 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 984 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 985 986 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 987 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 988 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 989 props->odp_caps = dev->odp_caps; 990 if (!uhw) { 991 /* ODP for kernel QPs is not implemented for receive 992 * WQEs and SRQ WQEs 993 */ 994 props->odp_caps.per_transport_caps.rc_odp_caps &= 995 ~(IB_ODP_SUPPORT_READ | 996 IB_ODP_SUPPORT_SRQ_RECV); 997 props->odp_caps.per_transport_caps.uc_odp_caps &= 998 ~(IB_ODP_SUPPORT_READ | 999 IB_ODP_SUPPORT_SRQ_RECV); 1000 props->odp_caps.per_transport_caps.ud_odp_caps &= 1001 ~(IB_ODP_SUPPORT_READ | 1002 IB_ODP_SUPPORT_SRQ_RECV); 1003 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1004 ~(IB_ODP_SUPPORT_READ | 1005 IB_ODP_SUPPORT_SRQ_RECV); 1006 } 1007 } 1008 1009 if (MLX5_CAP_GEN(mdev, cd)) 1010 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1011 1012 if (mlx5_core_is_vf(mdev)) 1013 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1014 1015 if (mlx5_ib_port_link_layer(ibdev, 1) == 1016 IB_LINK_LAYER_ETHERNET && raw_support) { 1017 props->rss_caps.max_rwq_indirection_tables = 1018 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1019 props->rss_caps.max_rwq_indirection_table_size = 1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1021 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1022 props->max_wq_type_rq = 1023 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1024 } 1025 1026 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1027 props->tm_caps.max_num_tags = 1028 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1029 props->tm_caps.max_ops = 1030 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1031 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1032 } 1033 1034 if (MLX5_CAP_GEN(mdev, tag_matching) && 1035 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1036 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1037 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1038 } 1039 1040 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1041 props->cq_caps.max_cq_moderation_count = 1042 MLX5_MAX_CQ_COUNT; 1043 props->cq_caps.max_cq_moderation_period = 1044 MLX5_MAX_CQ_PERIOD; 1045 } 1046 1047 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1048 resp.response_length += sizeof(resp.cqe_comp_caps); 1049 1050 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1051 resp.cqe_comp_caps.max_num = 1052 MLX5_CAP_GEN(dev->mdev, 1053 cqe_compression_max_num); 1054 1055 resp.cqe_comp_caps.supported_format = 1056 MLX5_IB_CQE_RES_FORMAT_HASH | 1057 MLX5_IB_CQE_RES_FORMAT_CSUM; 1058 1059 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1060 resp.cqe_comp_caps.supported_format |= 1061 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1062 } 1063 } 1064 1065 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1066 raw_support) { 1067 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1068 MLX5_CAP_GEN(mdev, qos)) { 1069 resp.packet_pacing_caps.qp_rate_limit_max = 1070 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1071 resp.packet_pacing_caps.qp_rate_limit_min = 1072 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1073 resp.packet_pacing_caps.supported_qpts |= 1074 1 << IB_QPT_RAW_PACKET; 1075 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1076 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1077 resp.packet_pacing_caps.cap_flags |= 1078 MLX5_IB_PP_SUPPORT_BURST; 1079 } 1080 resp.response_length += sizeof(resp.packet_pacing_caps); 1081 } 1082 1083 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1084 uhw_outlen) { 1085 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1086 resp.mlx5_ib_support_multi_pkt_send_wqes = 1087 MLX5_IB_ALLOW_MPW; 1088 1089 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1090 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1091 MLX5_IB_SUPPORT_EMPW; 1092 1093 resp.response_length += 1094 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1095 } 1096 1097 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1098 resp.response_length += sizeof(resp.flags); 1099 1100 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1101 resp.flags |= 1102 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1103 1104 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1105 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1106 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1107 resp.flags |= 1108 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1109 1110 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1111 } 1112 1113 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1114 resp.response_length += sizeof(resp.sw_parsing_caps); 1115 if (MLX5_CAP_ETH(mdev, swp)) { 1116 resp.sw_parsing_caps.sw_parsing_offloads |= 1117 MLX5_IB_SW_PARSING; 1118 1119 if (MLX5_CAP_ETH(mdev, swp_csum)) 1120 resp.sw_parsing_caps.sw_parsing_offloads |= 1121 MLX5_IB_SW_PARSING_CSUM; 1122 1123 if (MLX5_CAP_ETH(mdev, swp_lso)) 1124 resp.sw_parsing_caps.sw_parsing_offloads |= 1125 MLX5_IB_SW_PARSING_LSO; 1126 1127 if (resp.sw_parsing_caps.sw_parsing_offloads) 1128 resp.sw_parsing_caps.supported_qpts = 1129 BIT(IB_QPT_RAW_PACKET); 1130 } 1131 } 1132 1133 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1134 raw_support) { 1135 resp.response_length += sizeof(resp.striding_rq_caps); 1136 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1137 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1138 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1139 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1140 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1141 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1142 resp.striding_rq_caps 1143 .min_single_wqe_log_num_of_strides = 1144 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1145 else 1146 resp.striding_rq_caps 1147 .min_single_wqe_log_num_of_strides = 1148 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1149 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1150 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1151 resp.striding_rq_caps.supported_qpts = 1152 BIT(IB_QPT_RAW_PACKET); 1153 } 1154 } 1155 1156 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1157 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1158 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1159 resp.tunnel_offloads_caps |= 1160 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1161 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1162 resp.tunnel_offloads_caps |= 1163 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1164 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1165 resp.tunnel_offloads_caps |= 1166 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1167 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1168 resp.tunnel_offloads_caps |= 1169 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1171 resp.tunnel_offloads_caps |= 1172 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1173 } 1174 1175 if (uhw_outlen) { 1176 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1177 1178 if (err) 1179 return err; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1186 u8 *ib_width) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 1190 if (active_width & MLX5_PTYS_WIDTH_1X) 1191 *ib_width = IB_WIDTH_1X; 1192 else if (active_width & MLX5_PTYS_WIDTH_2X) 1193 *ib_width = IB_WIDTH_2X; 1194 else if (active_width & MLX5_PTYS_WIDTH_4X) 1195 *ib_width = IB_WIDTH_4X; 1196 else if (active_width & MLX5_PTYS_WIDTH_8X) 1197 *ib_width = IB_WIDTH_8X; 1198 else if (active_width & MLX5_PTYS_WIDTH_12X) 1199 *ib_width = IB_WIDTH_12X; 1200 else { 1201 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1202 active_width); 1203 *ib_width = IB_WIDTH_4X; 1204 } 1205 1206 return; 1207 } 1208 1209 static int mlx5_mtu_to_ib_mtu(int mtu) 1210 { 1211 switch (mtu) { 1212 case 256: return 1; 1213 case 512: return 2; 1214 case 1024: return 3; 1215 case 2048: return 4; 1216 case 4096: return 5; 1217 default: 1218 pr_warn("invalid mtu\n"); 1219 return -1; 1220 } 1221 } 1222 1223 enum ib_max_vl_num { 1224 __IB_MAX_VL_0 = 1, 1225 __IB_MAX_VL_0_1 = 2, 1226 __IB_MAX_VL_0_3 = 3, 1227 __IB_MAX_VL_0_7 = 4, 1228 __IB_MAX_VL_0_14 = 5, 1229 }; 1230 1231 enum mlx5_vl_hw_cap { 1232 MLX5_VL_HW_0 = 1, 1233 MLX5_VL_HW_0_1 = 2, 1234 MLX5_VL_HW_0_2 = 3, 1235 MLX5_VL_HW_0_3 = 4, 1236 MLX5_VL_HW_0_4 = 5, 1237 MLX5_VL_HW_0_5 = 6, 1238 MLX5_VL_HW_0_6 = 7, 1239 MLX5_VL_HW_0_7 = 8, 1240 MLX5_VL_HW_0_14 = 15 1241 }; 1242 1243 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1244 u8 *max_vl_num) 1245 { 1246 switch (vl_hw_cap) { 1247 case MLX5_VL_HW_0: 1248 *max_vl_num = __IB_MAX_VL_0; 1249 break; 1250 case MLX5_VL_HW_0_1: 1251 *max_vl_num = __IB_MAX_VL_0_1; 1252 break; 1253 case MLX5_VL_HW_0_3: 1254 *max_vl_num = __IB_MAX_VL_0_3; 1255 break; 1256 case MLX5_VL_HW_0_7: 1257 *max_vl_num = __IB_MAX_VL_0_7; 1258 break; 1259 case MLX5_VL_HW_0_14: 1260 *max_vl_num = __IB_MAX_VL_0_14; 1261 break; 1262 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1271 struct ib_port_attr *props) 1272 { 1273 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1274 struct mlx5_core_dev *mdev = dev->mdev; 1275 struct mlx5_hca_vport_context *rep; 1276 u16 max_mtu; 1277 u16 oper_mtu; 1278 int err; 1279 u16 ib_link_width_oper; 1280 u8 vl_hw_cap; 1281 1282 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1283 if (!rep) { 1284 err = -ENOMEM; 1285 goto out; 1286 } 1287 1288 /* props being zeroed by the caller, avoid zeroing it here */ 1289 1290 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1291 if (err) 1292 goto out; 1293 1294 props->lid = rep->lid; 1295 props->lmc = rep->lmc; 1296 props->sm_lid = rep->sm_lid; 1297 props->sm_sl = rep->sm_sl; 1298 props->state = rep->vport_state; 1299 props->phys_state = rep->port_physical_state; 1300 props->port_cap_flags = rep->cap_mask1; 1301 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1302 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1303 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1304 props->bad_pkey_cntr = rep->pkey_violation_counter; 1305 props->qkey_viol_cntr = rep->qkey_violation_counter; 1306 props->subnet_timeout = rep->subnet_timeout; 1307 props->init_type_reply = rep->init_type_reply; 1308 1309 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1310 props->port_cap_flags2 = rep->cap_mask2; 1311 1312 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1313 &props->active_speed, port); 1314 if (err) 1315 goto out; 1316 1317 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1318 1319 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1320 1321 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1322 1323 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1324 1325 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1326 1327 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1328 if (err) 1329 goto out; 1330 1331 err = translate_max_vl_num(ibdev, vl_hw_cap, 1332 &props->max_vl_num); 1333 out: 1334 kfree(rep); 1335 return err; 1336 } 1337 1338 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1339 struct ib_port_attr *props) 1340 { 1341 unsigned int count; 1342 int ret; 1343 1344 switch (mlx5_get_vport_access_method(ibdev)) { 1345 case MLX5_VPORT_ACCESS_METHOD_MAD: 1346 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1347 break; 1348 1349 case MLX5_VPORT_ACCESS_METHOD_HCA: 1350 ret = mlx5_query_hca_port(ibdev, port, props); 1351 break; 1352 1353 case MLX5_VPORT_ACCESS_METHOD_NIC: 1354 ret = mlx5_query_port_roce(ibdev, port, props); 1355 break; 1356 1357 default: 1358 ret = -EINVAL; 1359 } 1360 1361 if (!ret && props) { 1362 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1363 struct mlx5_core_dev *mdev; 1364 bool put_mdev = true; 1365 1366 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1367 if (!mdev) { 1368 /* If the port isn't affiliated yet query the master. 1369 * The master and slave will have the same values. 1370 */ 1371 mdev = dev->mdev; 1372 port = 1; 1373 put_mdev = false; 1374 } 1375 count = mlx5_core_reserved_gids_count(mdev); 1376 if (put_mdev) 1377 mlx5_ib_put_native_port_mdev(dev, port); 1378 props->gid_tbl_len -= count; 1379 } 1380 return ret; 1381 } 1382 1383 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1384 struct ib_port_attr *props) 1385 { 1386 return mlx5_query_port_roce(ibdev, port, props); 1387 } 1388 1389 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1390 u16 *pkey) 1391 { 1392 /* Default special Pkey for representor device port as per the 1393 * IB specification 1.3 section 10.9.1.2. 1394 */ 1395 *pkey = 0xffff; 1396 return 0; 1397 } 1398 1399 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1400 union ib_gid *gid) 1401 { 1402 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1403 struct mlx5_core_dev *mdev = dev->mdev; 1404 1405 switch (mlx5_get_vport_access_method(ibdev)) { 1406 case MLX5_VPORT_ACCESS_METHOD_MAD: 1407 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1408 1409 case MLX5_VPORT_ACCESS_METHOD_HCA: 1410 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1411 1412 default: 1413 return -EINVAL; 1414 } 1415 1416 } 1417 1418 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1419 u16 index, u16 *pkey) 1420 { 1421 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1422 struct mlx5_core_dev *mdev; 1423 bool put_mdev = true; 1424 u8 mdev_port_num; 1425 int err; 1426 1427 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1428 if (!mdev) { 1429 /* The port isn't affiliated yet, get the PKey from the master 1430 * port. For RoCE the PKey tables will be the same. 1431 */ 1432 put_mdev = false; 1433 mdev = dev->mdev; 1434 mdev_port_num = 1; 1435 } 1436 1437 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1438 index, pkey); 1439 if (put_mdev) 1440 mlx5_ib_put_native_port_mdev(dev, port); 1441 1442 return err; 1443 } 1444 1445 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1446 u16 *pkey) 1447 { 1448 switch (mlx5_get_vport_access_method(ibdev)) { 1449 case MLX5_VPORT_ACCESS_METHOD_MAD: 1450 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1451 1452 case MLX5_VPORT_ACCESS_METHOD_HCA: 1453 case MLX5_VPORT_ACCESS_METHOD_NIC: 1454 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1455 default: 1456 return -EINVAL; 1457 } 1458 } 1459 1460 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1461 struct ib_device_modify *props) 1462 { 1463 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1464 struct mlx5_reg_node_desc in; 1465 struct mlx5_reg_node_desc out; 1466 int err; 1467 1468 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1469 return -EOPNOTSUPP; 1470 1471 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1472 return 0; 1473 1474 /* 1475 * If possible, pass node desc to FW, so it can generate 1476 * a 144 trap. If cmd fails, just ignore. 1477 */ 1478 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1479 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1480 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1481 if (err) 1482 return err; 1483 1484 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1485 1486 return err; 1487 } 1488 1489 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1490 u32 value) 1491 { 1492 struct mlx5_hca_vport_context ctx = {}; 1493 struct mlx5_core_dev *mdev; 1494 u8 mdev_port_num; 1495 int err; 1496 1497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1498 if (!mdev) 1499 return -ENODEV; 1500 1501 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1502 if (err) 1503 goto out; 1504 1505 if (~ctx.cap_mask1_perm & mask) { 1506 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1507 mask, ctx.cap_mask1_perm); 1508 err = -EINVAL; 1509 goto out; 1510 } 1511 1512 ctx.cap_mask1 = value; 1513 ctx.cap_mask1_perm = mask; 1514 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1515 0, &ctx); 1516 1517 out: 1518 mlx5_ib_put_native_port_mdev(dev, port_num); 1519 1520 return err; 1521 } 1522 1523 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1524 struct ib_port_modify *props) 1525 { 1526 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1527 struct ib_port_attr attr; 1528 u32 tmp; 1529 int err; 1530 u32 change_mask; 1531 u32 value; 1532 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1533 IB_LINK_LAYER_INFINIBAND); 1534 1535 /* CM layer calls ib_modify_port() regardless of the link layer. For 1536 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1537 */ 1538 if (!is_ib) 1539 return 0; 1540 1541 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1542 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1543 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1544 return set_port_caps_atomic(dev, port, change_mask, value); 1545 } 1546 1547 mutex_lock(&dev->cap_mask_mutex); 1548 1549 err = ib_query_port(ibdev, port, &attr); 1550 if (err) 1551 goto out; 1552 1553 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1554 ~props->clr_port_cap_mask; 1555 1556 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1557 1558 out: 1559 mutex_unlock(&dev->cap_mask_mutex); 1560 return err; 1561 } 1562 1563 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1564 { 1565 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1566 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1567 } 1568 1569 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1570 { 1571 /* Large page with non 4k uar support might limit the dynamic size */ 1572 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1573 return MLX5_MIN_DYN_BFREGS; 1574 1575 return MLX5_MAX_DYN_BFREGS; 1576 } 1577 1578 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1579 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1580 struct mlx5_bfreg_info *bfregi) 1581 { 1582 int uars_per_sys_page; 1583 int bfregs_per_sys_page; 1584 int ref_bfregs = req->total_num_bfregs; 1585 1586 if (req->total_num_bfregs == 0) 1587 return -EINVAL; 1588 1589 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1590 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1591 1592 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1593 return -ENOMEM; 1594 1595 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1596 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1597 /* This holds the required static allocation asked by the user */ 1598 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1599 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1600 return -EINVAL; 1601 1602 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1603 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1604 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1605 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1606 1607 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1608 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1609 lib_uar_4k ? "yes" : "no", ref_bfregs, 1610 req->total_num_bfregs, bfregi->total_num_bfregs, 1611 bfregi->num_sys_pages); 1612 1613 return 0; 1614 } 1615 1616 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1617 { 1618 struct mlx5_bfreg_info *bfregi; 1619 int err; 1620 int i; 1621 1622 bfregi = &context->bfregi; 1623 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1624 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1625 if (err) 1626 goto error; 1627 1628 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1629 } 1630 1631 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1632 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1633 1634 return 0; 1635 1636 error: 1637 for (--i; i >= 0; i--) 1638 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1639 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1640 1641 return err; 1642 } 1643 1644 static void deallocate_uars(struct mlx5_ib_dev *dev, 1645 struct mlx5_ib_ucontext *context) 1646 { 1647 struct mlx5_bfreg_info *bfregi; 1648 int i; 1649 1650 bfregi = &context->bfregi; 1651 for (i = 0; i < bfregi->num_sys_pages; i++) 1652 if (i < bfregi->num_static_sys_pages || 1653 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1654 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1655 } 1656 1657 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1658 { 1659 int err = 0; 1660 1661 mutex_lock(&dev->lb.mutex); 1662 if (td) 1663 dev->lb.user_td++; 1664 if (qp) 1665 dev->lb.qps++; 1666 1667 if (dev->lb.user_td == 2 || 1668 dev->lb.qps == 1) { 1669 if (!dev->lb.enabled) { 1670 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1671 dev->lb.enabled = true; 1672 } 1673 } 1674 1675 mutex_unlock(&dev->lb.mutex); 1676 1677 return err; 1678 } 1679 1680 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1681 { 1682 mutex_lock(&dev->lb.mutex); 1683 if (td) 1684 dev->lb.user_td--; 1685 if (qp) 1686 dev->lb.qps--; 1687 1688 if (dev->lb.user_td == 1 && 1689 dev->lb.qps == 0) { 1690 if (dev->lb.enabled) { 1691 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1692 dev->lb.enabled = false; 1693 } 1694 } 1695 1696 mutex_unlock(&dev->lb.mutex); 1697 } 1698 1699 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1700 u16 uid) 1701 { 1702 int err; 1703 1704 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1705 return 0; 1706 1707 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1708 if (err) 1709 return err; 1710 1711 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1712 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1713 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1714 return err; 1715 1716 return mlx5_ib_enable_lb(dev, true, false); 1717 } 1718 1719 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1720 u16 uid) 1721 { 1722 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1723 return; 1724 1725 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1726 1727 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1728 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1729 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1730 return; 1731 1732 mlx5_ib_disable_lb(dev, true, false); 1733 } 1734 1735 static int set_ucontext_resp(struct ib_ucontext *uctx, 1736 struct mlx5_ib_alloc_ucontext_resp *resp) 1737 { 1738 struct ib_device *ibdev = uctx->device; 1739 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1740 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1741 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1742 int err; 1743 1744 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1745 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1746 &resp->dump_fill_mkey); 1747 if (err) 1748 return err; 1749 resp->comp_mask |= 1750 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1751 } 1752 1753 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1754 if (dev->wc_support) 1755 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1756 log_bf_reg_size); 1757 resp->cache_line_size = cache_line_size(); 1758 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1759 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1760 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1761 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1762 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1763 resp->cqe_version = context->cqe_version; 1764 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1765 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1766 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1767 MLX5_CAP_GEN(dev->mdev, 1768 num_of_uars_per_page) : 1; 1769 1770 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1771 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1772 if (mlx5_get_flow_namespace(dev->mdev, 1773 MLX5_FLOW_NAMESPACE_EGRESS)) 1774 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1775 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1776 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1777 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1778 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1779 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1780 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1781 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1782 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1783 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1784 } 1785 1786 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1787 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1788 resp->num_ports = dev->num_ports; 1789 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1790 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1791 1792 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1793 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1794 resp->eth_min_inline++; 1795 } 1796 1797 if (dev->mdev->clock_info) 1798 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1799 1800 /* 1801 * We don't want to expose information from the PCI bar that is located 1802 * after 4096 bytes, so if the arch only supports larger pages, let's 1803 * pretend we don't support reading the HCA's core clock. This is also 1804 * forced by mmap function. 1805 */ 1806 if (PAGE_SIZE <= 4096) { 1807 resp->comp_mask |= 1808 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1809 resp->hca_core_clock_offset = 1810 offsetof(struct mlx5_init_seg, 1811 internal_timer_h) % PAGE_SIZE; 1812 } 1813 1814 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1815 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1816 1817 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1818 return 0; 1819 } 1820 1821 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1822 struct ib_udata *udata) 1823 { 1824 struct ib_device *ibdev = uctx->device; 1825 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1826 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1827 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1828 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1829 struct mlx5_bfreg_info *bfregi; 1830 int ver; 1831 int err; 1832 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1833 max_cqe_version); 1834 bool lib_uar_4k; 1835 bool lib_uar_dyn; 1836 1837 if (!dev->ib_active) 1838 return -EAGAIN; 1839 1840 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1841 ver = 0; 1842 else if (udata->inlen >= min_req_v2) 1843 ver = 2; 1844 else 1845 return -EINVAL; 1846 1847 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1848 if (err) 1849 return err; 1850 1851 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1852 return -EOPNOTSUPP; 1853 1854 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1855 return -EOPNOTSUPP; 1856 1857 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1858 MLX5_NON_FP_BFREGS_PER_UAR); 1859 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1860 return -EINVAL; 1861 1862 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1863 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1864 bfregi = &context->bfregi; 1865 1866 if (lib_uar_dyn) { 1867 bfregi->lib_uar_dyn = lib_uar_dyn; 1868 goto uar_done; 1869 } 1870 1871 /* updates req->total_num_bfregs */ 1872 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1873 if (err) 1874 goto out_ctx; 1875 1876 mutex_init(&bfregi->lock); 1877 bfregi->lib_uar_4k = lib_uar_4k; 1878 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1879 GFP_KERNEL); 1880 if (!bfregi->count) { 1881 err = -ENOMEM; 1882 goto out_ctx; 1883 } 1884 1885 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1886 sizeof(*bfregi->sys_pages), 1887 GFP_KERNEL); 1888 if (!bfregi->sys_pages) { 1889 err = -ENOMEM; 1890 goto out_count; 1891 } 1892 1893 err = allocate_uars(dev, context); 1894 if (err) 1895 goto out_sys_pages; 1896 1897 uar_done: 1898 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1899 err = mlx5_ib_devx_create(dev, true); 1900 if (err < 0) 1901 goto out_uars; 1902 context->devx_uid = err; 1903 } 1904 1905 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1906 context->devx_uid); 1907 if (err) 1908 goto out_devx; 1909 1910 INIT_LIST_HEAD(&context->db_page_list); 1911 mutex_init(&context->db_page_mutex); 1912 1913 context->cqe_version = min_t(__u8, 1914 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1915 req.max_cqe_version); 1916 1917 err = set_ucontext_resp(uctx, &resp); 1918 if (err) 1919 goto out_mdev; 1920 1921 resp.response_length = min(udata->outlen, sizeof(resp)); 1922 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1923 if (err) 1924 goto out_mdev; 1925 1926 bfregi->ver = ver; 1927 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1928 context->lib_caps = req.lib_caps; 1929 print_lib_caps(dev, context->lib_caps); 1930 1931 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1932 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1933 1934 atomic_set(&context->tx_port_affinity, 1935 atomic_add_return( 1936 1, &dev->port[port].roce.tx_port_affinity)); 1937 } 1938 1939 return 0; 1940 1941 out_mdev: 1942 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1943 out_devx: 1944 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1945 mlx5_ib_devx_destroy(dev, context->devx_uid); 1946 1947 out_uars: 1948 deallocate_uars(dev, context); 1949 1950 out_sys_pages: 1951 kfree(bfregi->sys_pages); 1952 1953 out_count: 1954 kfree(bfregi->count); 1955 1956 out_ctx: 1957 return err; 1958 } 1959 1960 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1961 struct uverbs_attr_bundle *attrs) 1962 { 1963 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1964 int ret; 1965 1966 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1967 if (ret) 1968 return ret; 1969 1970 uctx_resp.response_length = 1971 min_t(size_t, 1972 uverbs_attr_get_len(attrs, 1973 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1974 sizeof(uctx_resp)); 1975 1976 ret = uverbs_copy_to_struct_or_zero(attrs, 1977 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1978 &uctx_resp, 1979 sizeof(uctx_resp)); 1980 return ret; 1981 } 1982 1983 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1984 { 1985 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1986 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1987 struct mlx5_bfreg_info *bfregi; 1988 1989 bfregi = &context->bfregi; 1990 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1991 1992 if (context->devx_uid) 1993 mlx5_ib_devx_destroy(dev, context->devx_uid); 1994 1995 deallocate_uars(dev, context); 1996 kfree(bfregi->sys_pages); 1997 kfree(bfregi->count); 1998 } 1999 2000 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2001 int uar_idx) 2002 { 2003 int fw_uars_per_page; 2004 2005 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2006 2007 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2008 } 2009 2010 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2011 int uar_idx) 2012 { 2013 unsigned int fw_uars_per_page; 2014 2015 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2016 MLX5_UARS_IN_PAGE : 1; 2017 2018 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2019 } 2020 2021 static int get_command(unsigned long offset) 2022 { 2023 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2024 } 2025 2026 static int get_arg(unsigned long offset) 2027 { 2028 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2029 } 2030 2031 static int get_index(unsigned long offset) 2032 { 2033 return get_arg(offset); 2034 } 2035 2036 /* Index resides in an extra byte to enable larger values than 255 */ 2037 static int get_extended_index(unsigned long offset) 2038 { 2039 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2040 } 2041 2042 2043 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2044 { 2045 } 2046 2047 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2048 { 2049 switch (cmd) { 2050 case MLX5_IB_MMAP_WC_PAGE: 2051 return "WC"; 2052 case MLX5_IB_MMAP_REGULAR_PAGE: 2053 return "best effort WC"; 2054 case MLX5_IB_MMAP_NC_PAGE: 2055 return "NC"; 2056 case MLX5_IB_MMAP_DEVICE_MEM: 2057 return "Device Memory"; 2058 default: 2059 return NULL; 2060 } 2061 } 2062 2063 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2064 struct vm_area_struct *vma, 2065 struct mlx5_ib_ucontext *context) 2066 { 2067 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2068 !(vma->vm_flags & VM_SHARED)) 2069 return -EINVAL; 2070 2071 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2072 return -EOPNOTSUPP; 2073 2074 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2075 return -EPERM; 2076 vma->vm_flags &= ~VM_MAYWRITE; 2077 2078 if (!dev->mdev->clock_info) 2079 return -EOPNOTSUPP; 2080 2081 return vm_insert_page(vma, vma->vm_start, 2082 virt_to_page(dev->mdev->clock_info)); 2083 } 2084 2085 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2086 { 2087 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2088 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2089 struct mlx5_var_table *var_table = &dev->var_table; 2090 struct mlx5_ib_dm *mdm; 2091 2092 switch (mentry->mmap_flag) { 2093 case MLX5_IB_MMAP_TYPE_MEMIC: 2094 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2095 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2096 mdm->size); 2097 kfree(mdm); 2098 break; 2099 case MLX5_IB_MMAP_TYPE_VAR: 2100 mutex_lock(&var_table->bitmap_lock); 2101 clear_bit(mentry->page_idx, var_table->bitmap); 2102 mutex_unlock(&var_table->bitmap_lock); 2103 kfree(mentry); 2104 break; 2105 case MLX5_IB_MMAP_TYPE_UAR_WC: 2106 case MLX5_IB_MMAP_TYPE_UAR_NC: 2107 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2108 kfree(mentry); 2109 break; 2110 default: 2111 WARN_ON(true); 2112 } 2113 } 2114 2115 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2116 struct vm_area_struct *vma, 2117 struct mlx5_ib_ucontext *context) 2118 { 2119 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2120 int err; 2121 unsigned long idx; 2122 phys_addr_t pfn; 2123 pgprot_t prot; 2124 u32 bfreg_dyn_idx = 0; 2125 u32 uar_index; 2126 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2127 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2128 bfregi->num_static_sys_pages; 2129 2130 if (bfregi->lib_uar_dyn) 2131 return -EINVAL; 2132 2133 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2134 return -EINVAL; 2135 2136 if (dyn_uar) 2137 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2138 else 2139 idx = get_index(vma->vm_pgoff); 2140 2141 if (idx >= max_valid_idx) { 2142 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2143 idx, max_valid_idx); 2144 return -EINVAL; 2145 } 2146 2147 switch (cmd) { 2148 case MLX5_IB_MMAP_WC_PAGE: 2149 case MLX5_IB_MMAP_ALLOC_WC: 2150 case MLX5_IB_MMAP_REGULAR_PAGE: 2151 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2152 prot = pgprot_writecombine(vma->vm_page_prot); 2153 break; 2154 case MLX5_IB_MMAP_NC_PAGE: 2155 prot = pgprot_noncached(vma->vm_page_prot); 2156 break; 2157 default: 2158 return -EINVAL; 2159 } 2160 2161 if (dyn_uar) { 2162 int uars_per_page; 2163 2164 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2165 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2166 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2167 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2168 bfreg_dyn_idx, bfregi->total_num_bfregs); 2169 return -EINVAL; 2170 } 2171 2172 mutex_lock(&bfregi->lock); 2173 /* Fail if uar already allocated, first bfreg index of each 2174 * page holds its count. 2175 */ 2176 if (bfregi->count[bfreg_dyn_idx]) { 2177 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2178 mutex_unlock(&bfregi->lock); 2179 return -EINVAL; 2180 } 2181 2182 bfregi->count[bfreg_dyn_idx]++; 2183 mutex_unlock(&bfregi->lock); 2184 2185 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2186 if (err) { 2187 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2188 goto free_bfreg; 2189 } 2190 } else { 2191 uar_index = bfregi->sys_pages[idx]; 2192 } 2193 2194 pfn = uar_index2pfn(dev, uar_index); 2195 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2196 2197 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2198 prot, NULL); 2199 if (err) { 2200 mlx5_ib_err(dev, 2201 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2202 err, mmap_cmd2str(cmd)); 2203 goto err; 2204 } 2205 2206 if (dyn_uar) 2207 bfregi->sys_pages[idx] = uar_index; 2208 return 0; 2209 2210 err: 2211 if (!dyn_uar) 2212 return err; 2213 2214 mlx5_cmd_free_uar(dev->mdev, idx); 2215 2216 free_bfreg: 2217 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2218 2219 return err; 2220 } 2221 2222 static int add_dm_mmap_entry(struct ib_ucontext *context, 2223 struct mlx5_ib_dm *mdm, 2224 u64 address) 2225 { 2226 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2227 mdm->mentry.address = address; 2228 return rdma_user_mmap_entry_insert_range( 2229 context, &mdm->mentry.rdma_entry, 2230 mdm->size, 2231 MLX5_IB_MMAP_DEVICE_MEM << 16, 2232 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2233 } 2234 2235 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2236 { 2237 unsigned long idx; 2238 u8 command; 2239 2240 command = get_command(vma->vm_pgoff); 2241 idx = get_extended_index(vma->vm_pgoff); 2242 2243 return (command << 16 | idx); 2244 } 2245 2246 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2247 struct vm_area_struct *vma, 2248 struct ib_ucontext *ucontext) 2249 { 2250 struct mlx5_user_mmap_entry *mentry; 2251 struct rdma_user_mmap_entry *entry; 2252 unsigned long pgoff; 2253 pgprot_t prot; 2254 phys_addr_t pfn; 2255 int ret; 2256 2257 pgoff = mlx5_vma_to_pgoff(vma); 2258 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2259 if (!entry) 2260 return -EINVAL; 2261 2262 mentry = to_mmmap(entry); 2263 pfn = (mentry->address >> PAGE_SHIFT); 2264 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2265 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2266 prot = pgprot_noncached(vma->vm_page_prot); 2267 else 2268 prot = pgprot_writecombine(vma->vm_page_prot); 2269 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2270 entry->npages * PAGE_SIZE, 2271 prot, 2272 entry); 2273 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2274 return ret; 2275 } 2276 2277 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2278 { 2279 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2280 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2281 2282 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2283 (index & 0xFF)) << PAGE_SHIFT; 2284 } 2285 2286 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2287 { 2288 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2289 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2290 unsigned long command; 2291 phys_addr_t pfn; 2292 2293 command = get_command(vma->vm_pgoff); 2294 switch (command) { 2295 case MLX5_IB_MMAP_WC_PAGE: 2296 case MLX5_IB_MMAP_ALLOC_WC: 2297 if (!dev->wc_support) 2298 return -EPERM; 2299 fallthrough; 2300 case MLX5_IB_MMAP_NC_PAGE: 2301 case MLX5_IB_MMAP_REGULAR_PAGE: 2302 return uar_mmap(dev, command, vma, context); 2303 2304 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2305 return -ENOSYS; 2306 2307 case MLX5_IB_MMAP_CORE_CLOCK: 2308 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2309 return -EINVAL; 2310 2311 if (vma->vm_flags & VM_WRITE) 2312 return -EPERM; 2313 vma->vm_flags &= ~VM_MAYWRITE; 2314 2315 /* Don't expose to user-space information it shouldn't have */ 2316 if (PAGE_SIZE > 4096) 2317 return -EOPNOTSUPP; 2318 2319 pfn = (dev->mdev->iseg_base + 2320 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2321 PAGE_SHIFT; 2322 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2323 PAGE_SIZE, 2324 pgprot_noncached(vma->vm_page_prot), 2325 NULL); 2326 case MLX5_IB_MMAP_CLOCK_INFO: 2327 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2328 2329 default: 2330 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2331 } 2332 2333 return 0; 2334 } 2335 2336 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2337 u32 type) 2338 { 2339 switch (type) { 2340 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2341 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2342 return -EOPNOTSUPP; 2343 break; 2344 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2345 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2346 if (!capable(CAP_SYS_RAWIO) || 2347 !capable(CAP_NET_RAW)) 2348 return -EPERM; 2349 2350 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2351 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) || 2352 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) || 2353 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2))) 2354 return -EOPNOTSUPP; 2355 break; 2356 } 2357 2358 return 0; 2359 } 2360 2361 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2362 struct mlx5_ib_dm *dm, 2363 struct ib_dm_alloc_attr *attr, 2364 struct uverbs_attr_bundle *attrs) 2365 { 2366 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2367 u64 start_offset; 2368 u16 page_idx; 2369 int err; 2370 u64 address; 2371 2372 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2373 2374 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2375 dm->size, attr->alignment); 2376 if (err) 2377 return err; 2378 2379 address = dm->dev_addr & PAGE_MASK; 2380 err = add_dm_mmap_entry(ctx, dm, address); 2381 if (err) 2382 goto err_dealloc; 2383 2384 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2385 err = uverbs_copy_to(attrs, 2386 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2387 &page_idx, 2388 sizeof(page_idx)); 2389 if (err) 2390 goto err_copy; 2391 2392 start_offset = dm->dev_addr & ~PAGE_MASK; 2393 err = uverbs_copy_to(attrs, 2394 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2395 &start_offset, sizeof(start_offset)); 2396 if (err) 2397 goto err_copy; 2398 2399 return 0; 2400 2401 err_copy: 2402 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2403 err_dealloc: 2404 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2405 2406 return err; 2407 } 2408 2409 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2410 struct mlx5_ib_dm *dm, 2411 struct ib_dm_alloc_attr *attr, 2412 struct uverbs_attr_bundle *attrs, 2413 int type) 2414 { 2415 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2416 u64 act_size; 2417 int err; 2418 2419 /* Allocation size must a multiple of the basic block size 2420 * and a power of 2. 2421 */ 2422 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2423 act_size = roundup_pow_of_two(act_size); 2424 2425 dm->size = act_size; 2426 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2427 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2428 &dm->icm_dm.obj_id); 2429 if (err) 2430 return err; 2431 2432 err = uverbs_copy_to(attrs, 2433 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2434 &dm->dev_addr, sizeof(dm->dev_addr)); 2435 if (err) 2436 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2437 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2438 dm->icm_dm.obj_id); 2439 2440 return err; 2441 } 2442 2443 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2444 struct ib_ucontext *context, 2445 struct ib_dm_alloc_attr *attr, 2446 struct uverbs_attr_bundle *attrs) 2447 { 2448 struct mlx5_ib_dm *dm; 2449 enum mlx5_ib_uapi_dm_type type; 2450 int err; 2451 2452 err = uverbs_get_const_default(&type, attrs, 2453 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2454 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2455 if (err) 2456 return ERR_PTR(err); 2457 2458 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2459 type, attr->length, attr->alignment); 2460 2461 err = check_dm_type_support(to_mdev(ibdev), type); 2462 if (err) 2463 return ERR_PTR(err); 2464 2465 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2466 if (!dm) 2467 return ERR_PTR(-ENOMEM); 2468 2469 dm->type = type; 2470 2471 switch (type) { 2472 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2473 err = handle_alloc_dm_memic(context, dm, 2474 attr, 2475 attrs); 2476 break; 2477 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2478 err = handle_alloc_dm_sw_icm(context, dm, 2479 attr, attrs, 2480 MLX5_SW_ICM_TYPE_STEERING); 2481 break; 2482 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2483 err = handle_alloc_dm_sw_icm(context, dm, 2484 attr, attrs, 2485 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2486 break; 2487 default: 2488 err = -EOPNOTSUPP; 2489 } 2490 2491 if (err) 2492 goto err_free; 2493 2494 return &dm->ibdm; 2495 2496 err_free: 2497 kfree(dm); 2498 return ERR_PTR(err); 2499 } 2500 2501 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2502 { 2503 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2504 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2505 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2506 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2507 int ret; 2508 2509 switch (dm->type) { 2510 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2511 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2512 return 0; 2513 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2514 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2515 dm->size, ctx->devx_uid, dm->dev_addr, 2516 dm->icm_dm.obj_id); 2517 if (ret) 2518 return ret; 2519 break; 2520 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2521 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2522 dm->size, ctx->devx_uid, dm->dev_addr, 2523 dm->icm_dm.obj_id); 2524 if (ret) 2525 return ret; 2526 break; 2527 default: 2528 return -EOPNOTSUPP; 2529 } 2530 2531 kfree(dm); 2532 2533 return 0; 2534 } 2535 2536 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2537 { 2538 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2539 struct ib_device *ibdev = ibpd->device; 2540 struct mlx5_ib_alloc_pd_resp resp; 2541 int err; 2542 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2543 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2544 u16 uid = 0; 2545 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2546 udata, struct mlx5_ib_ucontext, ibucontext); 2547 2548 uid = context ? context->devx_uid : 0; 2549 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2550 MLX5_SET(alloc_pd_in, in, uid, uid); 2551 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2552 if (err) 2553 return err; 2554 2555 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2556 pd->uid = uid; 2557 if (udata) { 2558 resp.pdn = pd->pdn; 2559 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2560 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2561 return -EFAULT; 2562 } 2563 } 2564 2565 return 0; 2566 } 2567 2568 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2569 { 2570 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2571 struct mlx5_ib_pd *mpd = to_mpd(pd); 2572 2573 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2574 } 2575 2576 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2577 { 2578 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2579 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2580 int err; 2581 u16 uid; 2582 2583 uid = ibqp->pd ? 2584 to_mpd(ibqp->pd)->uid : 0; 2585 2586 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2587 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2588 return -EOPNOTSUPP; 2589 } 2590 2591 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2592 if (err) 2593 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2594 ibqp->qp_num, gid->raw); 2595 2596 return err; 2597 } 2598 2599 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2600 { 2601 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2602 int err; 2603 u16 uid; 2604 2605 uid = ibqp->pd ? 2606 to_mpd(ibqp->pd)->uid : 0; 2607 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2608 if (err) 2609 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2610 ibqp->qp_num, gid->raw); 2611 2612 return err; 2613 } 2614 2615 static int init_node_data(struct mlx5_ib_dev *dev) 2616 { 2617 int err; 2618 2619 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2620 if (err) 2621 return err; 2622 2623 dev->mdev->rev_id = dev->mdev->pdev->revision; 2624 2625 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2626 } 2627 2628 static ssize_t fw_pages_show(struct device *device, 2629 struct device_attribute *attr, char *buf) 2630 { 2631 struct mlx5_ib_dev *dev = 2632 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2633 2634 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2635 } 2636 static DEVICE_ATTR_RO(fw_pages); 2637 2638 static ssize_t reg_pages_show(struct device *device, 2639 struct device_attribute *attr, char *buf) 2640 { 2641 struct mlx5_ib_dev *dev = 2642 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2643 2644 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2645 } 2646 static DEVICE_ATTR_RO(reg_pages); 2647 2648 static ssize_t hca_type_show(struct device *device, 2649 struct device_attribute *attr, char *buf) 2650 { 2651 struct mlx5_ib_dev *dev = 2652 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2653 2654 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2655 } 2656 static DEVICE_ATTR_RO(hca_type); 2657 2658 static ssize_t hw_rev_show(struct device *device, 2659 struct device_attribute *attr, char *buf) 2660 { 2661 struct mlx5_ib_dev *dev = 2662 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2663 2664 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2665 } 2666 static DEVICE_ATTR_RO(hw_rev); 2667 2668 static ssize_t board_id_show(struct device *device, 2669 struct device_attribute *attr, char *buf) 2670 { 2671 struct mlx5_ib_dev *dev = 2672 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2673 2674 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2675 dev->mdev->board_id); 2676 } 2677 static DEVICE_ATTR_RO(board_id); 2678 2679 static struct attribute *mlx5_class_attributes[] = { 2680 &dev_attr_hw_rev.attr, 2681 &dev_attr_hca_type.attr, 2682 &dev_attr_board_id.attr, 2683 &dev_attr_fw_pages.attr, 2684 &dev_attr_reg_pages.attr, 2685 NULL, 2686 }; 2687 2688 static const struct attribute_group mlx5_attr_group = { 2689 .attrs = mlx5_class_attributes, 2690 }; 2691 2692 static void pkey_change_handler(struct work_struct *work) 2693 { 2694 struct mlx5_ib_port_resources *ports = 2695 container_of(work, struct mlx5_ib_port_resources, 2696 pkey_change_work); 2697 2698 mlx5_ib_gsi_pkey_change(ports->gsi); 2699 } 2700 2701 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2702 { 2703 struct mlx5_ib_qp *mqp; 2704 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2705 struct mlx5_core_cq *mcq; 2706 struct list_head cq_armed_list; 2707 unsigned long flags_qp; 2708 unsigned long flags_cq; 2709 unsigned long flags; 2710 2711 INIT_LIST_HEAD(&cq_armed_list); 2712 2713 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2714 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2715 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2716 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2717 if (mqp->sq.tail != mqp->sq.head) { 2718 send_mcq = to_mcq(mqp->ibqp.send_cq); 2719 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2720 if (send_mcq->mcq.comp && 2721 mqp->ibqp.send_cq->comp_handler) { 2722 if (!send_mcq->mcq.reset_notify_added) { 2723 send_mcq->mcq.reset_notify_added = 1; 2724 list_add_tail(&send_mcq->mcq.reset_notify, 2725 &cq_armed_list); 2726 } 2727 } 2728 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2729 } 2730 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2731 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2732 /* no handling is needed for SRQ */ 2733 if (!mqp->ibqp.srq) { 2734 if (mqp->rq.tail != mqp->rq.head) { 2735 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2736 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2737 if (recv_mcq->mcq.comp && 2738 mqp->ibqp.recv_cq->comp_handler) { 2739 if (!recv_mcq->mcq.reset_notify_added) { 2740 recv_mcq->mcq.reset_notify_added = 1; 2741 list_add_tail(&recv_mcq->mcq.reset_notify, 2742 &cq_armed_list); 2743 } 2744 } 2745 spin_unlock_irqrestore(&recv_mcq->lock, 2746 flags_cq); 2747 } 2748 } 2749 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2750 } 2751 /*At that point all inflight post send were put to be executed as of we 2752 * lock/unlock above locks Now need to arm all involved CQs. 2753 */ 2754 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2755 mcq->comp(mcq, NULL); 2756 } 2757 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2758 } 2759 2760 static void delay_drop_handler(struct work_struct *work) 2761 { 2762 int err; 2763 struct mlx5_ib_delay_drop *delay_drop = 2764 container_of(work, struct mlx5_ib_delay_drop, 2765 delay_drop_work); 2766 2767 atomic_inc(&delay_drop->events_cnt); 2768 2769 mutex_lock(&delay_drop->lock); 2770 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2771 if (err) { 2772 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2773 delay_drop->timeout); 2774 delay_drop->activate = false; 2775 } 2776 mutex_unlock(&delay_drop->lock); 2777 } 2778 2779 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2780 struct ib_event *ibev) 2781 { 2782 u8 port = (eqe->data.port.port >> 4) & 0xf; 2783 2784 switch (eqe->sub_type) { 2785 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2786 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2787 IB_LINK_LAYER_ETHERNET) 2788 schedule_work(&ibdev->delay_drop.delay_drop_work); 2789 break; 2790 default: /* do nothing */ 2791 return; 2792 } 2793 } 2794 2795 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2796 struct ib_event *ibev) 2797 { 2798 u8 port = (eqe->data.port.port >> 4) & 0xf; 2799 2800 ibev->element.port_num = port; 2801 2802 switch (eqe->sub_type) { 2803 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2804 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2805 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2806 /* In RoCE, port up/down events are handled in 2807 * mlx5_netdev_event(). 2808 */ 2809 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2810 IB_LINK_LAYER_ETHERNET) 2811 return -EINVAL; 2812 2813 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2814 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2815 break; 2816 2817 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2818 ibev->event = IB_EVENT_LID_CHANGE; 2819 break; 2820 2821 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2822 ibev->event = IB_EVENT_PKEY_CHANGE; 2823 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2824 break; 2825 2826 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2827 ibev->event = IB_EVENT_GID_CHANGE; 2828 break; 2829 2830 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2831 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2832 break; 2833 default: 2834 return -EINVAL; 2835 } 2836 2837 return 0; 2838 } 2839 2840 static void mlx5_ib_handle_event(struct work_struct *_work) 2841 { 2842 struct mlx5_ib_event_work *work = 2843 container_of(_work, struct mlx5_ib_event_work, work); 2844 struct mlx5_ib_dev *ibdev; 2845 struct ib_event ibev; 2846 bool fatal = false; 2847 2848 if (work->is_slave) { 2849 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2850 if (!ibdev) 2851 goto out; 2852 } else { 2853 ibdev = work->dev; 2854 } 2855 2856 switch (work->event) { 2857 case MLX5_DEV_EVENT_SYS_ERROR: 2858 ibev.event = IB_EVENT_DEVICE_FATAL; 2859 mlx5_ib_handle_internal_error(ibdev); 2860 ibev.element.port_num = (u8)(unsigned long)work->param; 2861 fatal = true; 2862 break; 2863 case MLX5_EVENT_TYPE_PORT_CHANGE: 2864 if (handle_port_change(ibdev, work->param, &ibev)) 2865 goto out; 2866 break; 2867 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2868 handle_general_event(ibdev, work->param, &ibev); 2869 fallthrough; 2870 default: 2871 goto out; 2872 } 2873 2874 ibev.device = &ibdev->ib_dev; 2875 2876 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2877 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2878 goto out; 2879 } 2880 2881 if (ibdev->ib_active) 2882 ib_dispatch_event(&ibev); 2883 2884 if (fatal) 2885 ibdev->ib_active = false; 2886 out: 2887 kfree(work); 2888 } 2889 2890 static int mlx5_ib_event(struct notifier_block *nb, 2891 unsigned long event, void *param) 2892 { 2893 struct mlx5_ib_event_work *work; 2894 2895 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2896 if (!work) 2897 return NOTIFY_DONE; 2898 2899 INIT_WORK(&work->work, mlx5_ib_handle_event); 2900 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2901 work->is_slave = false; 2902 work->param = param; 2903 work->event = event; 2904 2905 queue_work(mlx5_ib_event_wq, &work->work); 2906 2907 return NOTIFY_OK; 2908 } 2909 2910 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2911 unsigned long event, void *param) 2912 { 2913 struct mlx5_ib_event_work *work; 2914 2915 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2916 if (!work) 2917 return NOTIFY_DONE; 2918 2919 INIT_WORK(&work->work, mlx5_ib_handle_event); 2920 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2921 work->is_slave = true; 2922 work->param = param; 2923 work->event = event; 2924 queue_work(mlx5_ib_event_wq, &work->work); 2925 2926 return NOTIFY_OK; 2927 } 2928 2929 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2930 { 2931 struct mlx5_hca_vport_context vport_ctx; 2932 int err; 2933 int port; 2934 2935 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2936 dev->port_caps[port - 1].has_smi = false; 2937 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2938 MLX5_CAP_PORT_TYPE_IB) { 2939 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2940 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2941 port, 0, 2942 &vport_ctx); 2943 if (err) { 2944 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2945 port, err); 2946 return err; 2947 } 2948 dev->port_caps[port - 1].has_smi = 2949 vport_ctx.has_smi; 2950 } else { 2951 dev->port_caps[port - 1].has_smi = true; 2952 } 2953 } 2954 } 2955 return 0; 2956 } 2957 2958 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2959 { 2960 unsigned int port; 2961 2962 rdma_for_each_port (&dev->ib_dev, port) 2963 mlx5_query_ext_port_caps(dev, port); 2964 } 2965 2966 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2967 { 2968 switch (umr_fence_cap) { 2969 case MLX5_CAP_UMR_FENCE_NONE: 2970 return MLX5_FENCE_MODE_NONE; 2971 case MLX5_CAP_UMR_FENCE_SMALL: 2972 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2973 default: 2974 return MLX5_FENCE_MODE_STRONG_ORDERING; 2975 } 2976 } 2977 2978 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2979 { 2980 struct mlx5_ib_resources *devr = &dev->devr; 2981 struct ib_srq_init_attr attr; 2982 struct ib_device *ibdev; 2983 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2984 int port; 2985 int ret = 0; 2986 2987 ibdev = &dev->ib_dev; 2988 2989 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2990 return -EOPNOTSUPP; 2991 2992 mutex_init(&devr->mutex); 2993 2994 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2995 if (!devr->p0) 2996 return -ENOMEM; 2997 2998 devr->p0->device = ibdev; 2999 devr->p0->uobject = NULL; 3000 atomic_set(&devr->p0->usecnt, 0); 3001 3002 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3003 if (ret) 3004 goto error0; 3005 3006 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3007 if (!devr->c0) { 3008 ret = -ENOMEM; 3009 goto error1; 3010 } 3011 3012 devr->c0->device = &dev->ib_dev; 3013 atomic_set(&devr->c0->usecnt, 0); 3014 3015 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3016 if (ret) 3017 goto err_create_cq; 3018 3019 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3020 if (ret) 3021 goto error2; 3022 3023 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3024 if (ret) 3025 goto error3; 3026 3027 memset(&attr, 0, sizeof(attr)); 3028 attr.attr.max_sge = 1; 3029 attr.attr.max_wr = 1; 3030 attr.srq_type = IB_SRQT_XRC; 3031 attr.ext.cq = devr->c0; 3032 3033 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3034 if (!devr->s0) { 3035 ret = -ENOMEM; 3036 goto error4; 3037 } 3038 3039 devr->s0->device = &dev->ib_dev; 3040 devr->s0->pd = devr->p0; 3041 devr->s0->srq_type = IB_SRQT_XRC; 3042 devr->s0->ext.cq = devr->c0; 3043 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3044 if (ret) 3045 goto err_create; 3046 3047 atomic_inc(&devr->s0->ext.cq->usecnt); 3048 atomic_inc(&devr->p0->usecnt); 3049 atomic_set(&devr->s0->usecnt, 0); 3050 3051 memset(&attr, 0, sizeof(attr)); 3052 attr.attr.max_sge = 1; 3053 attr.attr.max_wr = 1; 3054 attr.srq_type = IB_SRQT_BASIC; 3055 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3056 if (!devr->s1) { 3057 ret = -ENOMEM; 3058 goto error5; 3059 } 3060 3061 devr->s1->device = &dev->ib_dev; 3062 devr->s1->pd = devr->p0; 3063 devr->s1->srq_type = IB_SRQT_BASIC; 3064 devr->s1->ext.cq = devr->c0; 3065 3066 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3067 if (ret) 3068 goto error6; 3069 3070 atomic_inc(&devr->p0->usecnt); 3071 atomic_set(&devr->s1->usecnt, 0); 3072 3073 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3074 INIT_WORK(&devr->ports[port].pkey_change_work, 3075 pkey_change_handler); 3076 3077 return 0; 3078 3079 error6: 3080 kfree(devr->s1); 3081 error5: 3082 mlx5_ib_destroy_srq(devr->s0, NULL); 3083 err_create: 3084 kfree(devr->s0); 3085 error4: 3086 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3087 error3: 3088 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3089 error2: 3090 mlx5_ib_destroy_cq(devr->c0, NULL); 3091 err_create_cq: 3092 kfree(devr->c0); 3093 error1: 3094 mlx5_ib_dealloc_pd(devr->p0, NULL); 3095 error0: 3096 kfree(devr->p0); 3097 return ret; 3098 } 3099 3100 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3101 { 3102 struct mlx5_ib_resources *devr = &dev->devr; 3103 int port; 3104 3105 mlx5_ib_destroy_srq(devr->s1, NULL); 3106 kfree(devr->s1); 3107 mlx5_ib_destroy_srq(devr->s0, NULL); 3108 kfree(devr->s0); 3109 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3110 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3111 mlx5_ib_destroy_cq(devr->c0, NULL); 3112 kfree(devr->c0); 3113 mlx5_ib_dealloc_pd(devr->p0, NULL); 3114 kfree(devr->p0); 3115 3116 /* Make sure no change P_Key work items are still executing */ 3117 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3118 cancel_work_sync(&devr->ports[port].pkey_change_work); 3119 } 3120 3121 static u32 get_core_cap_flags(struct ib_device *ibdev, 3122 struct mlx5_hca_vport_context *rep) 3123 { 3124 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3125 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3126 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3127 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3128 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3129 u32 ret = 0; 3130 3131 if (rep->grh_required) 3132 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3133 3134 if (ll == IB_LINK_LAYER_INFINIBAND) 3135 return ret | RDMA_CORE_PORT_IBA_IB; 3136 3137 if (raw_support) 3138 ret |= RDMA_CORE_PORT_RAW_PACKET; 3139 3140 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3141 return ret; 3142 3143 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3144 return ret; 3145 3146 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3147 ret |= RDMA_CORE_PORT_IBA_ROCE; 3148 3149 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3150 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3151 3152 return ret; 3153 } 3154 3155 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3156 struct ib_port_immutable *immutable) 3157 { 3158 struct ib_port_attr attr; 3159 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3160 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3161 struct mlx5_hca_vport_context rep = {0}; 3162 int err; 3163 3164 err = ib_query_port(ibdev, port_num, &attr); 3165 if (err) 3166 return err; 3167 3168 if (ll == IB_LINK_LAYER_INFINIBAND) { 3169 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3170 &rep); 3171 if (err) 3172 return err; 3173 } 3174 3175 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3176 immutable->gid_tbl_len = attr.gid_tbl_len; 3177 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3178 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3179 3180 return 0; 3181 } 3182 3183 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3184 struct ib_port_immutable *immutable) 3185 { 3186 struct ib_port_attr attr; 3187 int err; 3188 3189 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3190 3191 err = ib_query_port(ibdev, port_num, &attr); 3192 if (err) 3193 return err; 3194 3195 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3196 immutable->gid_tbl_len = attr.gid_tbl_len; 3197 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3198 3199 return 0; 3200 } 3201 3202 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3203 { 3204 struct mlx5_ib_dev *dev = 3205 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3206 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3207 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3208 fw_rev_sub(dev->mdev)); 3209 } 3210 3211 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3212 { 3213 struct mlx5_core_dev *mdev = dev->mdev; 3214 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3215 MLX5_FLOW_NAMESPACE_LAG); 3216 struct mlx5_flow_table *ft; 3217 int err; 3218 3219 if (!ns || !mlx5_lag_is_roce(mdev)) 3220 return 0; 3221 3222 err = mlx5_cmd_create_vport_lag(mdev); 3223 if (err) 3224 return err; 3225 3226 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3227 if (IS_ERR(ft)) { 3228 err = PTR_ERR(ft); 3229 goto err_destroy_vport_lag; 3230 } 3231 3232 dev->flow_db->lag_demux_ft = ft; 3233 dev->lag_active = true; 3234 return 0; 3235 3236 err_destroy_vport_lag: 3237 mlx5_cmd_destroy_vport_lag(mdev); 3238 return err; 3239 } 3240 3241 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3242 { 3243 struct mlx5_core_dev *mdev = dev->mdev; 3244 3245 if (dev->lag_active) { 3246 dev->lag_active = false; 3247 3248 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3249 dev->flow_db->lag_demux_ft = NULL; 3250 3251 mlx5_cmd_destroy_vport_lag(mdev); 3252 } 3253 } 3254 3255 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3256 { 3257 int err; 3258 3259 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3260 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3261 if (err) { 3262 dev->port[port_num].roce.nb.notifier_call = NULL; 3263 return err; 3264 } 3265 3266 return 0; 3267 } 3268 3269 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3270 { 3271 if (dev->port[port_num].roce.nb.notifier_call) { 3272 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3273 dev->port[port_num].roce.nb.notifier_call = NULL; 3274 } 3275 } 3276 3277 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3278 { 3279 int err; 3280 3281 err = mlx5_nic_vport_enable_roce(dev->mdev); 3282 if (err) 3283 return err; 3284 3285 err = mlx5_eth_lag_init(dev); 3286 if (err) 3287 goto err_disable_roce; 3288 3289 return 0; 3290 3291 err_disable_roce: 3292 mlx5_nic_vport_disable_roce(dev->mdev); 3293 3294 return err; 3295 } 3296 3297 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3298 { 3299 mlx5_eth_lag_cleanup(dev); 3300 mlx5_nic_vport_disable_roce(dev->mdev); 3301 } 3302 3303 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3304 enum rdma_netdev_t type, 3305 struct rdma_netdev_alloc_params *params) 3306 { 3307 if (type != RDMA_NETDEV_IPOIB) 3308 return -EOPNOTSUPP; 3309 3310 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3311 } 3312 3313 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3314 size_t count, loff_t *pos) 3315 { 3316 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3317 char lbuf[20]; 3318 int len; 3319 3320 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3321 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3322 } 3323 3324 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3325 size_t count, loff_t *pos) 3326 { 3327 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3328 u32 timeout; 3329 u32 var; 3330 3331 if (kstrtouint_from_user(buf, count, 0, &var)) 3332 return -EFAULT; 3333 3334 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3335 1000); 3336 if (timeout != var) 3337 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3338 timeout); 3339 3340 delay_drop->timeout = timeout; 3341 3342 return count; 3343 } 3344 3345 static const struct file_operations fops_delay_drop_timeout = { 3346 .owner = THIS_MODULE, 3347 .open = simple_open, 3348 .write = delay_drop_timeout_write, 3349 .read = delay_drop_timeout_read, 3350 }; 3351 3352 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3353 struct mlx5_ib_multiport_info *mpi) 3354 { 3355 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3356 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3357 int comps; 3358 int err; 3359 int i; 3360 3361 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3362 3363 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3364 3365 spin_lock(&port->mp.mpi_lock); 3366 if (!mpi->ibdev) { 3367 spin_unlock(&port->mp.mpi_lock); 3368 return; 3369 } 3370 3371 mpi->ibdev = NULL; 3372 3373 spin_unlock(&port->mp.mpi_lock); 3374 if (mpi->mdev_events.notifier_call) 3375 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3376 mpi->mdev_events.notifier_call = NULL; 3377 mlx5_remove_netdev_notifier(ibdev, port_num); 3378 spin_lock(&port->mp.mpi_lock); 3379 3380 comps = mpi->mdev_refcnt; 3381 if (comps) { 3382 mpi->unaffiliate = true; 3383 init_completion(&mpi->unref_comp); 3384 spin_unlock(&port->mp.mpi_lock); 3385 3386 for (i = 0; i < comps; i++) 3387 wait_for_completion(&mpi->unref_comp); 3388 3389 spin_lock(&port->mp.mpi_lock); 3390 mpi->unaffiliate = false; 3391 } 3392 3393 port->mp.mpi = NULL; 3394 3395 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3396 3397 spin_unlock(&port->mp.mpi_lock); 3398 3399 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3400 3401 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3402 /* Log an error, still needed to cleanup the pointers and add 3403 * it back to the list. 3404 */ 3405 if (err) 3406 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3407 port_num + 1); 3408 3409 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3410 } 3411 3412 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3413 struct mlx5_ib_multiport_info *mpi) 3414 { 3415 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3416 int err; 3417 3418 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3419 3420 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3421 if (ibdev->port[port_num].mp.mpi) { 3422 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3423 port_num + 1); 3424 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3425 return false; 3426 } 3427 3428 ibdev->port[port_num].mp.mpi = mpi; 3429 mpi->ibdev = ibdev; 3430 mpi->mdev_events.notifier_call = NULL; 3431 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3432 3433 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3434 if (err) 3435 goto unbind; 3436 3437 err = mlx5_add_netdev_notifier(ibdev, port_num); 3438 if (err) { 3439 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3440 port_num + 1); 3441 goto unbind; 3442 } 3443 3444 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3445 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3446 3447 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3448 3449 return true; 3450 3451 unbind: 3452 mlx5_ib_unbind_slave_port(ibdev, mpi); 3453 return false; 3454 } 3455 3456 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3457 { 3458 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3459 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3460 port_num + 1); 3461 struct mlx5_ib_multiport_info *mpi; 3462 int err; 3463 int i; 3464 3465 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3466 return 0; 3467 3468 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3469 &dev->sys_image_guid); 3470 if (err) 3471 return err; 3472 3473 err = mlx5_nic_vport_enable_roce(dev->mdev); 3474 if (err) 3475 return err; 3476 3477 mutex_lock(&mlx5_ib_multiport_mutex); 3478 for (i = 0; i < dev->num_ports; i++) { 3479 bool bound = false; 3480 3481 /* build a stub multiport info struct for the native port. */ 3482 if (i == port_num) { 3483 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3484 if (!mpi) { 3485 mutex_unlock(&mlx5_ib_multiport_mutex); 3486 mlx5_nic_vport_disable_roce(dev->mdev); 3487 return -ENOMEM; 3488 } 3489 3490 mpi->is_master = true; 3491 mpi->mdev = dev->mdev; 3492 mpi->sys_image_guid = dev->sys_image_guid; 3493 dev->port[i].mp.mpi = mpi; 3494 mpi->ibdev = dev; 3495 mpi = NULL; 3496 continue; 3497 } 3498 3499 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3500 list) { 3501 if (dev->sys_image_guid == mpi->sys_image_guid && 3502 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3503 bound = mlx5_ib_bind_slave_port(dev, mpi); 3504 } 3505 3506 if (bound) { 3507 dev_dbg(mpi->mdev->device, 3508 "removing port from unaffiliated list.\n"); 3509 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3510 list_del(&mpi->list); 3511 break; 3512 } 3513 } 3514 if (!bound) 3515 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3516 i + 1); 3517 } 3518 3519 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3520 mutex_unlock(&mlx5_ib_multiport_mutex); 3521 return err; 3522 } 3523 3524 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3525 { 3526 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3527 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3528 port_num + 1); 3529 int i; 3530 3531 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3532 return; 3533 3534 mutex_lock(&mlx5_ib_multiport_mutex); 3535 for (i = 0; i < dev->num_ports; i++) { 3536 if (dev->port[i].mp.mpi) { 3537 /* Destroy the native port stub */ 3538 if (i == port_num) { 3539 kfree(dev->port[i].mp.mpi); 3540 dev->port[i].mp.mpi = NULL; 3541 } else { 3542 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3543 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3544 } 3545 } 3546 } 3547 3548 mlx5_ib_dbg(dev, "removing from devlist\n"); 3549 list_del(&dev->ib_dev_list); 3550 mutex_unlock(&mlx5_ib_multiport_mutex); 3551 3552 mlx5_nic_vport_disable_roce(dev->mdev); 3553 } 3554 3555 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3556 enum rdma_remove_reason why, 3557 struct uverbs_attr_bundle *attrs) 3558 { 3559 struct mlx5_user_mmap_entry *obj = uobject->object; 3560 3561 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3562 return 0; 3563 } 3564 3565 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3566 struct mlx5_user_mmap_entry *entry, 3567 size_t length) 3568 { 3569 return rdma_user_mmap_entry_insert_range( 3570 &c->ibucontext, &entry->rdma_entry, length, 3571 (MLX5_IB_MMAP_OFFSET_START << 16), 3572 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3573 } 3574 3575 static struct mlx5_user_mmap_entry * 3576 alloc_var_entry(struct mlx5_ib_ucontext *c) 3577 { 3578 struct mlx5_user_mmap_entry *entry; 3579 struct mlx5_var_table *var_table; 3580 u32 page_idx; 3581 int err; 3582 3583 var_table = &to_mdev(c->ibucontext.device)->var_table; 3584 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3585 if (!entry) 3586 return ERR_PTR(-ENOMEM); 3587 3588 mutex_lock(&var_table->bitmap_lock); 3589 page_idx = find_first_zero_bit(var_table->bitmap, 3590 var_table->num_var_hw_entries); 3591 if (page_idx >= var_table->num_var_hw_entries) { 3592 err = -ENOSPC; 3593 mutex_unlock(&var_table->bitmap_lock); 3594 goto end; 3595 } 3596 3597 set_bit(page_idx, var_table->bitmap); 3598 mutex_unlock(&var_table->bitmap_lock); 3599 3600 entry->address = var_table->hw_start_addr + 3601 (page_idx * var_table->stride_size); 3602 entry->page_idx = page_idx; 3603 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3604 3605 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3606 var_table->stride_size); 3607 if (err) 3608 goto err_insert; 3609 3610 return entry; 3611 3612 err_insert: 3613 mutex_lock(&var_table->bitmap_lock); 3614 clear_bit(page_idx, var_table->bitmap); 3615 mutex_unlock(&var_table->bitmap_lock); 3616 end: 3617 kfree(entry); 3618 return ERR_PTR(err); 3619 } 3620 3621 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3622 struct uverbs_attr_bundle *attrs) 3623 { 3624 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3625 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3626 struct mlx5_ib_ucontext *c; 3627 struct mlx5_user_mmap_entry *entry; 3628 u64 mmap_offset; 3629 u32 length; 3630 int err; 3631 3632 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3633 if (IS_ERR(c)) 3634 return PTR_ERR(c); 3635 3636 entry = alloc_var_entry(c); 3637 if (IS_ERR(entry)) 3638 return PTR_ERR(entry); 3639 3640 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3641 length = entry->rdma_entry.npages * PAGE_SIZE; 3642 uobj->object = entry; 3643 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3644 3645 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3646 &mmap_offset, sizeof(mmap_offset)); 3647 if (err) 3648 return err; 3649 3650 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3651 &entry->page_idx, sizeof(entry->page_idx)); 3652 if (err) 3653 return err; 3654 3655 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3656 &length, sizeof(length)); 3657 return err; 3658 } 3659 3660 DECLARE_UVERBS_NAMED_METHOD( 3661 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3662 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3663 MLX5_IB_OBJECT_VAR, 3664 UVERBS_ACCESS_NEW, 3665 UA_MANDATORY), 3666 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3667 UVERBS_ATTR_TYPE(u32), 3668 UA_MANDATORY), 3669 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3670 UVERBS_ATTR_TYPE(u32), 3671 UA_MANDATORY), 3672 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3673 UVERBS_ATTR_TYPE(u64), 3674 UA_MANDATORY)); 3675 3676 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3677 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3678 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3679 MLX5_IB_OBJECT_VAR, 3680 UVERBS_ACCESS_DESTROY, 3681 UA_MANDATORY)); 3682 3683 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3684 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3685 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3686 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3687 3688 static bool var_is_supported(struct ib_device *device) 3689 { 3690 struct mlx5_ib_dev *dev = to_mdev(device); 3691 3692 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3693 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3694 } 3695 3696 static struct mlx5_user_mmap_entry * 3697 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3698 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3699 { 3700 struct mlx5_user_mmap_entry *entry; 3701 struct mlx5_ib_dev *dev; 3702 u32 uar_index; 3703 int err; 3704 3705 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3706 if (!entry) 3707 return ERR_PTR(-ENOMEM); 3708 3709 dev = to_mdev(c->ibucontext.device); 3710 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3711 if (err) 3712 goto end; 3713 3714 entry->page_idx = uar_index; 3715 entry->address = uar_index2paddress(dev, uar_index); 3716 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3717 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3718 else 3719 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3720 3721 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3722 if (err) 3723 goto err_insert; 3724 3725 return entry; 3726 3727 err_insert: 3728 mlx5_cmd_free_uar(dev->mdev, uar_index); 3729 end: 3730 kfree(entry); 3731 return ERR_PTR(err); 3732 } 3733 3734 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3735 struct uverbs_attr_bundle *attrs) 3736 { 3737 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3738 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3739 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3740 struct mlx5_ib_ucontext *c; 3741 struct mlx5_user_mmap_entry *entry; 3742 u64 mmap_offset; 3743 u32 length; 3744 int err; 3745 3746 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3747 if (IS_ERR(c)) 3748 return PTR_ERR(c); 3749 3750 err = uverbs_get_const(&alloc_type, attrs, 3751 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3752 if (err) 3753 return err; 3754 3755 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3756 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3757 return -EOPNOTSUPP; 3758 3759 if (!to_mdev(c->ibucontext.device)->wc_support && 3760 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3761 return -EOPNOTSUPP; 3762 3763 entry = alloc_uar_entry(c, alloc_type); 3764 if (IS_ERR(entry)) 3765 return PTR_ERR(entry); 3766 3767 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3768 length = entry->rdma_entry.npages * PAGE_SIZE; 3769 uobj->object = entry; 3770 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3771 3772 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3773 &mmap_offset, sizeof(mmap_offset)); 3774 if (err) 3775 return err; 3776 3777 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3778 &entry->page_idx, sizeof(entry->page_idx)); 3779 if (err) 3780 return err; 3781 3782 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3783 &length, sizeof(length)); 3784 return err; 3785 } 3786 3787 DECLARE_UVERBS_NAMED_METHOD( 3788 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3789 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3790 MLX5_IB_OBJECT_UAR, 3791 UVERBS_ACCESS_NEW, 3792 UA_MANDATORY), 3793 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3794 enum mlx5_ib_uapi_uar_alloc_type, 3795 UA_MANDATORY), 3796 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3797 UVERBS_ATTR_TYPE(u32), 3798 UA_MANDATORY), 3799 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3800 UVERBS_ATTR_TYPE(u32), 3801 UA_MANDATORY), 3802 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3803 UVERBS_ATTR_TYPE(u64), 3804 UA_MANDATORY)); 3805 3806 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3807 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3808 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3809 MLX5_IB_OBJECT_UAR, 3810 UVERBS_ACCESS_DESTROY, 3811 UA_MANDATORY)); 3812 3813 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3814 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3815 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3816 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3817 3818 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3819 mlx5_ib_dm, 3820 UVERBS_OBJECT_DM, 3821 UVERBS_METHOD_DM_ALLOC, 3822 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3823 UVERBS_ATTR_TYPE(u64), 3824 UA_MANDATORY), 3825 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3826 UVERBS_ATTR_TYPE(u16), 3827 UA_OPTIONAL), 3828 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3829 enum mlx5_ib_uapi_dm_type, 3830 UA_OPTIONAL)); 3831 3832 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3833 mlx5_ib_flow_action, 3834 UVERBS_OBJECT_FLOW_ACTION, 3835 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3836 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3837 enum mlx5_ib_uapi_flow_action_flags)); 3838 3839 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3840 mlx5_ib_query_context, 3841 UVERBS_OBJECT_DEVICE, 3842 UVERBS_METHOD_QUERY_CONTEXT, 3843 UVERBS_ATTR_PTR_OUT( 3844 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3845 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3846 dump_fill_mkey), 3847 UA_MANDATORY)); 3848 3849 static const struct uapi_definition mlx5_ib_defs[] = { 3850 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3851 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3852 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3853 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3854 3855 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3856 &mlx5_ib_flow_action), 3857 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3858 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3859 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3860 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3861 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3862 {} 3863 }; 3864 3865 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3866 { 3867 mlx5_ib_cleanup_multiport_master(dev); 3868 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3869 mutex_destroy(&dev->cap_mask_mutex); 3870 WARN_ON(!xa_empty(&dev->sig_mrs)); 3871 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3872 } 3873 3874 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3875 { 3876 struct mlx5_core_dev *mdev = dev->mdev; 3877 int err; 3878 int i; 3879 3880 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3881 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3882 dev->ib_dev.phys_port_cnt = dev->num_ports; 3883 dev->ib_dev.dev.parent = mdev->device; 3884 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3885 3886 for (i = 0; i < dev->num_ports; i++) { 3887 spin_lock_init(&dev->port[i].mp.mpi_lock); 3888 rwlock_init(&dev->port[i].roce.netdev_lock); 3889 dev->port[i].roce.dev = dev; 3890 dev->port[i].roce.native_port_num = i + 1; 3891 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3892 } 3893 3894 mlx5_ib_internal_fill_odp_caps(dev); 3895 3896 err = mlx5_ib_init_multiport_master(dev); 3897 if (err) 3898 return err; 3899 3900 err = set_has_smi_cap(dev); 3901 if (err) 3902 goto err_mp; 3903 3904 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3905 if (err) 3906 goto err_mp; 3907 3908 if (mlx5_use_mad_ifc(dev)) 3909 get_ext_port_caps(dev); 3910 3911 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3912 3913 mutex_init(&dev->cap_mask_mutex); 3914 INIT_LIST_HEAD(&dev->qp_list); 3915 spin_lock_init(&dev->reset_flow_resource_lock); 3916 xa_init(&dev->odp_mkeys); 3917 xa_init(&dev->sig_mrs); 3918 atomic_set(&dev->mkey_var, 0); 3919 3920 spin_lock_init(&dev->dm.lock); 3921 dev->dm.dev = mdev; 3922 return 0; 3923 3924 err_mp: 3925 mlx5_ib_cleanup_multiport_master(dev); 3926 return err; 3927 } 3928 3929 static int mlx5_ib_enable_driver(struct ib_device *dev) 3930 { 3931 struct mlx5_ib_dev *mdev = to_mdev(dev); 3932 int ret; 3933 3934 ret = mlx5_ib_test_wc(mdev); 3935 mlx5_ib_dbg(mdev, "Write-Combining %s", 3936 mdev->wc_support ? "supported" : "not supported"); 3937 3938 return ret; 3939 } 3940 3941 static const struct ib_device_ops mlx5_ib_dev_ops = { 3942 .owner = THIS_MODULE, 3943 .driver_id = RDMA_DRIVER_MLX5, 3944 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3945 3946 .add_gid = mlx5_ib_add_gid, 3947 .alloc_mr = mlx5_ib_alloc_mr, 3948 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3949 .alloc_pd = mlx5_ib_alloc_pd, 3950 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3951 .attach_mcast = mlx5_ib_mcg_attach, 3952 .check_mr_status = mlx5_ib_check_mr_status, 3953 .create_ah = mlx5_ib_create_ah, 3954 .create_cq = mlx5_ib_create_cq, 3955 .create_qp = mlx5_ib_create_qp, 3956 .create_srq = mlx5_ib_create_srq, 3957 .create_user_ah = mlx5_ib_create_ah, 3958 .dealloc_pd = mlx5_ib_dealloc_pd, 3959 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3960 .del_gid = mlx5_ib_del_gid, 3961 .dereg_mr = mlx5_ib_dereg_mr, 3962 .destroy_ah = mlx5_ib_destroy_ah, 3963 .destroy_cq = mlx5_ib_destroy_cq, 3964 .destroy_qp = mlx5_ib_destroy_qp, 3965 .destroy_srq = mlx5_ib_destroy_srq, 3966 .detach_mcast = mlx5_ib_mcg_detach, 3967 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3968 .drain_rq = mlx5_ib_drain_rq, 3969 .drain_sq = mlx5_ib_drain_sq, 3970 .enable_driver = mlx5_ib_enable_driver, 3971 .get_dev_fw_str = get_dev_fw_str, 3972 .get_dma_mr = mlx5_ib_get_dma_mr, 3973 .get_link_layer = mlx5_ib_port_link_layer, 3974 .map_mr_sg = mlx5_ib_map_mr_sg, 3975 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3976 .mmap = mlx5_ib_mmap, 3977 .mmap_free = mlx5_ib_mmap_free, 3978 .modify_cq = mlx5_ib_modify_cq, 3979 .modify_device = mlx5_ib_modify_device, 3980 .modify_port = mlx5_ib_modify_port, 3981 .modify_qp = mlx5_ib_modify_qp, 3982 .modify_srq = mlx5_ib_modify_srq, 3983 .poll_cq = mlx5_ib_poll_cq, 3984 .post_recv = mlx5_ib_post_recv_nodrain, 3985 .post_send = mlx5_ib_post_send_nodrain, 3986 .post_srq_recv = mlx5_ib_post_srq_recv, 3987 .process_mad = mlx5_ib_process_mad, 3988 .query_ah = mlx5_ib_query_ah, 3989 .query_device = mlx5_ib_query_device, 3990 .query_gid = mlx5_ib_query_gid, 3991 .query_pkey = mlx5_ib_query_pkey, 3992 .query_qp = mlx5_ib_query_qp, 3993 .query_srq = mlx5_ib_query_srq, 3994 .query_ucontext = mlx5_ib_query_ucontext, 3995 .reg_user_mr = mlx5_ib_reg_user_mr, 3996 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3997 .req_notify_cq = mlx5_ib_arm_cq, 3998 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3999 .resize_cq = mlx5_ib_resize_cq, 4000 4001 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4002 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4003 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4004 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4005 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4006 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4007 }; 4008 4009 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4010 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4011 }; 4012 4013 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4014 .get_vf_config = mlx5_ib_get_vf_config, 4015 .get_vf_guid = mlx5_ib_get_vf_guid, 4016 .get_vf_stats = mlx5_ib_get_vf_stats, 4017 .set_vf_guid = mlx5_ib_set_vf_guid, 4018 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4019 }; 4020 4021 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4022 .alloc_mw = mlx5_ib_alloc_mw, 4023 .dealloc_mw = mlx5_ib_dealloc_mw, 4024 4025 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4026 }; 4027 4028 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4029 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4030 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4031 4032 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4033 }; 4034 4035 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4036 .alloc_dm = mlx5_ib_alloc_dm, 4037 .dealloc_dm = mlx5_ib_dealloc_dm, 4038 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4039 }; 4040 4041 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4042 { 4043 struct mlx5_core_dev *mdev = dev->mdev; 4044 struct mlx5_var_table *var_table = &dev->var_table; 4045 u8 log_doorbell_bar_size; 4046 u8 log_doorbell_stride; 4047 u64 bar_size; 4048 4049 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4050 log_doorbell_bar_size); 4051 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4052 log_doorbell_stride); 4053 var_table->hw_start_addr = dev->mdev->bar_addr + 4054 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4055 doorbell_bar_offset); 4056 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4057 var_table->stride_size = 1ULL << log_doorbell_stride; 4058 var_table->num_var_hw_entries = div_u64(bar_size, 4059 var_table->stride_size); 4060 mutex_init(&var_table->bitmap_lock); 4061 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4062 GFP_KERNEL); 4063 return (var_table->bitmap) ? 0 : -ENOMEM; 4064 } 4065 4066 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4067 { 4068 bitmap_free(dev->var_table.bitmap); 4069 } 4070 4071 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4072 { 4073 struct mlx5_core_dev *mdev = dev->mdev; 4074 int err; 4075 4076 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4077 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4078 ib_set_device_ops(&dev->ib_dev, 4079 &mlx5_ib_dev_ipoib_enhanced_ops); 4080 4081 if (mlx5_core_is_pf(mdev)) 4082 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4083 4084 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4085 4086 if (MLX5_CAP_GEN(mdev, imaicl)) 4087 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4088 4089 if (MLX5_CAP_GEN(mdev, xrc)) 4090 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4091 4092 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4093 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4094 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4095 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4096 4097 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4098 4099 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4100 dev->ib_dev.driver_def = mlx5_ib_defs; 4101 4102 err = init_node_data(dev); 4103 if (err) 4104 return err; 4105 4106 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4107 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4108 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4109 mutex_init(&dev->lb.mutex); 4110 4111 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4112 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4113 err = mlx5_ib_init_var_table(dev); 4114 if (err) 4115 return err; 4116 } 4117 4118 dev->ib_dev.use_cq_dim = true; 4119 4120 return 0; 4121 } 4122 4123 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4124 .get_port_immutable = mlx5_port_immutable, 4125 .query_port = mlx5_ib_query_port, 4126 }; 4127 4128 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4129 { 4130 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4131 return 0; 4132 } 4133 4134 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4135 .get_port_immutable = mlx5_port_rep_immutable, 4136 .query_port = mlx5_ib_rep_query_port, 4137 .query_pkey = mlx5_ib_rep_query_pkey, 4138 }; 4139 4140 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4141 { 4142 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4143 return 0; 4144 } 4145 4146 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4147 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4148 .create_wq = mlx5_ib_create_wq, 4149 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4150 .destroy_wq = mlx5_ib_destroy_wq, 4151 .get_netdev = mlx5_ib_get_netdev, 4152 .modify_wq = mlx5_ib_modify_wq, 4153 4154 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4155 ib_rwq_ind_tbl), 4156 }; 4157 4158 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4159 { 4160 struct mlx5_core_dev *mdev = dev->mdev; 4161 enum rdma_link_layer ll; 4162 int port_type_cap; 4163 u8 port_num = 0; 4164 int err; 4165 4166 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4167 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4168 4169 if (ll == IB_LINK_LAYER_ETHERNET) { 4170 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4171 4172 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4173 4174 /* Register only for native ports */ 4175 err = mlx5_add_netdev_notifier(dev, port_num); 4176 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4177 /* 4178 * We don't enable ETH interface for 4179 * 1. IB representors 4180 * 2. User disabled ROCE through devlink interface 4181 */ 4182 return err; 4183 4184 err = mlx5_enable_eth(dev); 4185 if (err) 4186 goto cleanup; 4187 } 4188 4189 return 0; 4190 cleanup: 4191 mlx5_remove_netdev_notifier(dev, port_num); 4192 return err; 4193 } 4194 4195 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4196 { 4197 struct mlx5_core_dev *mdev = dev->mdev; 4198 enum rdma_link_layer ll; 4199 int port_type_cap; 4200 u8 port_num; 4201 4202 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4203 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4204 4205 if (ll == IB_LINK_LAYER_ETHERNET) { 4206 if (!dev->is_rep) 4207 mlx5_disable_eth(dev); 4208 4209 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4210 mlx5_remove_netdev_notifier(dev, port_num); 4211 } 4212 } 4213 4214 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4215 { 4216 mlx5_ib_init_cong_debugfs(dev, 4217 mlx5_core_native_port_num(dev->mdev) - 1); 4218 return 0; 4219 } 4220 4221 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4222 { 4223 mlx5_ib_cleanup_cong_debugfs(dev, 4224 mlx5_core_native_port_num(dev->mdev) - 1); 4225 } 4226 4227 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4228 { 4229 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4230 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4231 } 4232 4233 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4234 { 4235 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4236 } 4237 4238 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4239 { 4240 int err; 4241 4242 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4243 if (err) 4244 return err; 4245 4246 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4247 if (err) 4248 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4249 4250 return err; 4251 } 4252 4253 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4254 { 4255 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4256 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4257 } 4258 4259 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4260 { 4261 const char *name; 4262 4263 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4264 if (!mlx5_lag_is_roce(dev->mdev)) 4265 name = "mlx5_%d"; 4266 else 4267 name = "mlx5_bond_%d"; 4268 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4269 } 4270 4271 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4272 { 4273 int err; 4274 4275 err = mlx5_mr_cache_cleanup(dev); 4276 if (err) 4277 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4278 4279 if (dev->umrc.qp) 4280 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4281 if (dev->umrc.cq) 4282 ib_free_cq(dev->umrc.cq); 4283 if (dev->umrc.pd) 4284 ib_dealloc_pd(dev->umrc.pd); 4285 } 4286 4287 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4288 { 4289 ib_unregister_device(&dev->ib_dev); 4290 } 4291 4292 enum { 4293 MAX_UMR_WR = 128, 4294 }; 4295 4296 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4297 { 4298 struct ib_qp_init_attr *init_attr = NULL; 4299 struct ib_qp_attr *attr = NULL; 4300 struct ib_pd *pd; 4301 struct ib_cq *cq; 4302 struct ib_qp *qp; 4303 int ret; 4304 4305 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4306 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4307 if (!attr || !init_attr) { 4308 ret = -ENOMEM; 4309 goto error_0; 4310 } 4311 4312 pd = ib_alloc_pd(&dev->ib_dev, 0); 4313 if (IS_ERR(pd)) { 4314 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4315 ret = PTR_ERR(pd); 4316 goto error_0; 4317 } 4318 4319 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4320 if (IS_ERR(cq)) { 4321 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4322 ret = PTR_ERR(cq); 4323 goto error_2; 4324 } 4325 4326 init_attr->send_cq = cq; 4327 init_attr->recv_cq = cq; 4328 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4329 init_attr->cap.max_send_wr = MAX_UMR_WR; 4330 init_attr->cap.max_send_sge = 1; 4331 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4332 init_attr->port_num = 1; 4333 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4334 if (IS_ERR(qp)) { 4335 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4336 ret = PTR_ERR(qp); 4337 goto error_3; 4338 } 4339 qp->device = &dev->ib_dev; 4340 qp->real_qp = qp; 4341 qp->uobject = NULL; 4342 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4343 qp->send_cq = init_attr->send_cq; 4344 qp->recv_cq = init_attr->recv_cq; 4345 4346 attr->qp_state = IB_QPS_INIT; 4347 attr->port_num = 1; 4348 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4349 IB_QP_PORT, NULL); 4350 if (ret) { 4351 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4352 goto error_4; 4353 } 4354 4355 memset(attr, 0, sizeof(*attr)); 4356 attr->qp_state = IB_QPS_RTR; 4357 attr->path_mtu = IB_MTU_256; 4358 4359 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4360 if (ret) { 4361 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4362 goto error_4; 4363 } 4364 4365 memset(attr, 0, sizeof(*attr)); 4366 attr->qp_state = IB_QPS_RTS; 4367 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4368 if (ret) { 4369 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4370 goto error_4; 4371 } 4372 4373 dev->umrc.qp = qp; 4374 dev->umrc.cq = cq; 4375 dev->umrc.pd = pd; 4376 4377 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4378 ret = mlx5_mr_cache_init(dev); 4379 if (ret) { 4380 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4381 goto error_4; 4382 } 4383 4384 kfree(attr); 4385 kfree(init_attr); 4386 4387 return 0; 4388 4389 error_4: 4390 mlx5_ib_destroy_qp(qp, NULL); 4391 dev->umrc.qp = NULL; 4392 4393 error_3: 4394 ib_free_cq(cq); 4395 dev->umrc.cq = NULL; 4396 4397 error_2: 4398 ib_dealloc_pd(pd); 4399 dev->umrc.pd = NULL; 4400 4401 error_0: 4402 kfree(attr); 4403 kfree(init_attr); 4404 return ret; 4405 } 4406 4407 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4408 { 4409 struct dentry *root; 4410 4411 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4412 return 0; 4413 4414 mutex_init(&dev->delay_drop.lock); 4415 dev->delay_drop.dev = dev; 4416 dev->delay_drop.activate = false; 4417 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4418 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4419 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4420 atomic_set(&dev->delay_drop.events_cnt, 0); 4421 4422 if (!mlx5_debugfs_root) 4423 return 0; 4424 4425 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4426 dev->delay_drop.dir_debugfs = root; 4427 4428 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4429 &dev->delay_drop.events_cnt); 4430 debugfs_create_atomic_t("num_rqs", 0400, root, 4431 &dev->delay_drop.rqs_cnt); 4432 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4433 &fops_delay_drop_timeout); 4434 return 0; 4435 } 4436 4437 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4438 { 4439 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4440 return; 4441 4442 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4443 if (!dev->delay_drop.dir_debugfs) 4444 return; 4445 4446 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4447 dev->delay_drop.dir_debugfs = NULL; 4448 } 4449 4450 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4451 { 4452 dev->mdev_events.notifier_call = mlx5_ib_event; 4453 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4454 return 0; 4455 } 4456 4457 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4458 { 4459 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4460 } 4461 4462 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4463 const struct mlx5_ib_profile *profile, 4464 int stage) 4465 { 4466 dev->ib_active = false; 4467 4468 /* Number of stages to cleanup */ 4469 while (stage) { 4470 stage--; 4471 if (profile->stage[stage].cleanup) 4472 profile->stage[stage].cleanup(dev); 4473 } 4474 4475 kfree(dev->port); 4476 ib_dealloc_device(&dev->ib_dev); 4477 } 4478 4479 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4480 const struct mlx5_ib_profile *profile) 4481 { 4482 int err; 4483 int i; 4484 4485 dev->profile = profile; 4486 4487 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4488 if (profile->stage[i].init) { 4489 err = profile->stage[i].init(dev); 4490 if (err) 4491 goto err_out; 4492 } 4493 } 4494 4495 dev->ib_active = true; 4496 return 0; 4497 4498 err_out: 4499 /* Clean up stages which were initialized */ 4500 while (i) { 4501 i--; 4502 if (profile->stage[i].cleanup) 4503 profile->stage[i].cleanup(dev); 4504 } 4505 return -ENOMEM; 4506 } 4507 4508 static const struct mlx5_ib_profile pf_profile = { 4509 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4510 mlx5_ib_stage_init_init, 4511 mlx5_ib_stage_init_cleanup), 4512 STAGE_CREATE(MLX5_IB_STAGE_FS, 4513 mlx5_ib_fs_init, 4514 mlx5_ib_fs_cleanup), 4515 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4516 mlx5_ib_stage_caps_init, 4517 mlx5_ib_stage_caps_cleanup), 4518 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4519 mlx5_ib_stage_non_default_cb, 4520 NULL), 4521 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4522 mlx5_ib_roce_init, 4523 mlx5_ib_roce_cleanup), 4524 STAGE_CREATE(MLX5_IB_STAGE_QP, 4525 mlx5_init_qp_table, 4526 mlx5_cleanup_qp_table), 4527 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4528 mlx5_init_srq_table, 4529 mlx5_cleanup_srq_table), 4530 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4531 mlx5_ib_dev_res_init, 4532 mlx5_ib_dev_res_cleanup), 4533 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4534 mlx5_ib_stage_dev_notifier_init, 4535 mlx5_ib_stage_dev_notifier_cleanup), 4536 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4537 mlx5_ib_odp_init_one, 4538 mlx5_ib_odp_cleanup_one), 4539 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4540 mlx5_ib_counters_init, 4541 mlx5_ib_counters_cleanup), 4542 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4543 mlx5_ib_stage_cong_debugfs_init, 4544 mlx5_ib_stage_cong_debugfs_cleanup), 4545 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4546 mlx5_ib_stage_uar_init, 4547 mlx5_ib_stage_uar_cleanup), 4548 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4549 mlx5_ib_stage_bfrag_init, 4550 mlx5_ib_stage_bfrag_cleanup), 4551 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4552 NULL, 4553 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4554 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4555 mlx5_ib_devx_init, 4556 mlx5_ib_devx_cleanup), 4557 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4558 mlx5_ib_stage_ib_reg_init, 4559 mlx5_ib_stage_ib_reg_cleanup), 4560 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4561 mlx5_ib_stage_post_ib_reg_umr_init, 4562 NULL), 4563 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4564 mlx5_ib_stage_delay_drop_init, 4565 mlx5_ib_stage_delay_drop_cleanup), 4566 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4567 mlx5_ib_restrack_init, 4568 NULL), 4569 }; 4570 4571 const struct mlx5_ib_profile raw_eth_profile = { 4572 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4573 mlx5_ib_stage_init_init, 4574 mlx5_ib_stage_init_cleanup), 4575 STAGE_CREATE(MLX5_IB_STAGE_FS, 4576 mlx5_ib_fs_init, 4577 mlx5_ib_fs_cleanup), 4578 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4579 mlx5_ib_stage_caps_init, 4580 mlx5_ib_stage_caps_cleanup), 4581 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4582 mlx5_ib_stage_raw_eth_non_default_cb, 4583 NULL), 4584 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4585 mlx5_ib_roce_init, 4586 mlx5_ib_roce_cleanup), 4587 STAGE_CREATE(MLX5_IB_STAGE_QP, 4588 mlx5_init_qp_table, 4589 mlx5_cleanup_qp_table), 4590 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4591 mlx5_init_srq_table, 4592 mlx5_cleanup_srq_table), 4593 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4594 mlx5_ib_dev_res_init, 4595 mlx5_ib_dev_res_cleanup), 4596 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4597 mlx5_ib_stage_dev_notifier_init, 4598 mlx5_ib_stage_dev_notifier_cleanup), 4599 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4600 mlx5_ib_counters_init, 4601 mlx5_ib_counters_cleanup), 4602 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4603 mlx5_ib_stage_cong_debugfs_init, 4604 mlx5_ib_stage_cong_debugfs_cleanup), 4605 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4606 mlx5_ib_stage_uar_init, 4607 mlx5_ib_stage_uar_cleanup), 4608 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4609 mlx5_ib_stage_bfrag_init, 4610 mlx5_ib_stage_bfrag_cleanup), 4611 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4612 NULL, 4613 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4614 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4615 mlx5_ib_devx_init, 4616 mlx5_ib_devx_cleanup), 4617 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4618 mlx5_ib_stage_ib_reg_init, 4619 mlx5_ib_stage_ib_reg_cleanup), 4620 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4621 mlx5_ib_stage_post_ib_reg_umr_init, 4622 NULL), 4623 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4624 mlx5_ib_restrack_init, 4625 NULL), 4626 }; 4627 4628 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4629 const struct auxiliary_device_id *id) 4630 { 4631 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4632 struct mlx5_core_dev *mdev = idev->mdev; 4633 struct mlx5_ib_multiport_info *mpi; 4634 struct mlx5_ib_dev *dev; 4635 bool bound = false; 4636 int err; 4637 4638 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4639 if (!mpi) 4640 return -ENOMEM; 4641 4642 mpi->mdev = mdev; 4643 err = mlx5_query_nic_vport_system_image_guid(mdev, 4644 &mpi->sys_image_guid); 4645 if (err) { 4646 kfree(mpi); 4647 return err; 4648 } 4649 4650 mutex_lock(&mlx5_ib_multiport_mutex); 4651 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4652 if (dev->sys_image_guid == mpi->sys_image_guid) 4653 bound = mlx5_ib_bind_slave_port(dev, mpi); 4654 4655 if (bound) { 4656 rdma_roce_rescan_device(&dev->ib_dev); 4657 break; 4658 } 4659 } 4660 4661 if (!bound) { 4662 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4663 dev_dbg(mdev->device, 4664 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4665 } 4666 mutex_unlock(&mlx5_ib_multiport_mutex); 4667 4668 dev_set_drvdata(&adev->dev, mpi); 4669 return 0; 4670 } 4671 4672 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4673 { 4674 struct mlx5_ib_multiport_info *mpi; 4675 4676 mpi = dev_get_drvdata(&adev->dev); 4677 mutex_lock(&mlx5_ib_multiport_mutex); 4678 if (mpi->ibdev) 4679 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4680 list_del(&mpi->list); 4681 mutex_unlock(&mlx5_ib_multiport_mutex); 4682 kfree(mpi); 4683 } 4684 4685 static int mlx5r_probe(struct auxiliary_device *adev, 4686 const struct auxiliary_device_id *id) 4687 { 4688 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4689 struct mlx5_core_dev *mdev = idev->mdev; 4690 const struct mlx5_ib_profile *profile; 4691 int port_type_cap, num_ports, ret; 4692 enum rdma_link_layer ll; 4693 struct mlx5_ib_dev *dev; 4694 4695 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4696 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4697 4698 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4699 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4700 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4701 if (!dev) 4702 return -ENOMEM; 4703 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4704 GFP_KERNEL); 4705 if (!dev->port) { 4706 ib_dealloc_device(&dev->ib_dev); 4707 return -ENOMEM; 4708 } 4709 4710 dev->mdev = mdev; 4711 dev->num_ports = num_ports; 4712 4713 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4714 profile = &raw_eth_profile; 4715 else 4716 profile = &pf_profile; 4717 4718 ret = __mlx5_ib_add(dev, profile); 4719 if (ret) { 4720 kfree(dev->port); 4721 ib_dealloc_device(&dev->ib_dev); 4722 return ret; 4723 } 4724 4725 dev_set_drvdata(&adev->dev, dev); 4726 return 0; 4727 } 4728 4729 static void mlx5r_remove(struct auxiliary_device *adev) 4730 { 4731 struct mlx5_ib_dev *dev; 4732 4733 dev = dev_get_drvdata(&adev->dev); 4734 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4735 } 4736 4737 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4738 { .name = MLX5_ADEV_NAME ".multiport", }, 4739 {}, 4740 }; 4741 4742 static const struct auxiliary_device_id mlx5r_id_table[] = { 4743 { .name = MLX5_ADEV_NAME ".rdma", }, 4744 {}, 4745 }; 4746 4747 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4748 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4749 4750 static struct auxiliary_driver mlx5r_mp_driver = { 4751 .name = "multiport", 4752 .probe = mlx5r_mp_probe, 4753 .remove = mlx5r_mp_remove, 4754 .id_table = mlx5r_mp_id_table, 4755 }; 4756 4757 static struct auxiliary_driver mlx5r_driver = { 4758 .name = "rdma", 4759 .probe = mlx5r_probe, 4760 .remove = mlx5r_remove, 4761 .id_table = mlx5r_id_table, 4762 }; 4763 4764 static int __init mlx5_ib_init(void) 4765 { 4766 int ret; 4767 4768 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4769 if (!xlt_emergency_page) 4770 return -ENOMEM; 4771 4772 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4773 if (!mlx5_ib_event_wq) { 4774 free_page((unsigned long)xlt_emergency_page); 4775 return -ENOMEM; 4776 } 4777 4778 mlx5_ib_odp_init(); 4779 ret = mlx5r_rep_init(); 4780 if (ret) 4781 goto rep_err; 4782 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4783 if (ret) 4784 goto mp_err; 4785 ret = auxiliary_driver_register(&mlx5r_driver); 4786 if (ret) 4787 goto drv_err; 4788 return 0; 4789 4790 drv_err: 4791 auxiliary_driver_unregister(&mlx5r_mp_driver); 4792 mp_err: 4793 mlx5r_rep_cleanup(); 4794 rep_err: 4795 destroy_workqueue(mlx5_ib_event_wq); 4796 free_page((unsigned long)xlt_emergency_page); 4797 return ret; 4798 } 4799 4800 static void __exit mlx5_ib_cleanup(void) 4801 { 4802 auxiliary_driver_unregister(&mlx5r_driver); 4803 auxiliary_driver_unregister(&mlx5r_mp_driver); 4804 mlx5r_rep_cleanup(); 4805 4806 destroy_workqueue(mlx5_ib_event_wq); 4807 free_page((unsigned long)xlt_emergency_page); 4808 } 4809 4810 module_init(mlx5_ib_init); 4811 module_exit(mlx5_ib_cleanup); 4812