1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include <rdma/uverbs_std_types.h> 45 #include <rdma/uverbs_ioctl.h> 46 #include <rdma/mlx5_user_ioctl_verbs.h> 47 #include <rdma/mlx5_user_ioctl_cmds.h> 48 #include <rdma/ib_umem_odp.h> 49 50 #define UVERBS_MODULE_NAME mlx5_ib 51 #include <rdma/uverbs_named_ioctl.h> 52 53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 54 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 57 struct mlx5_ib_event_work { 58 struct work_struct work; 59 union { 60 struct mlx5_ib_dev *dev; 61 struct mlx5_ib_multiport_info *mpi; 62 }; 63 bool is_slave; 64 unsigned int event; 65 void *param; 66 }; 67 68 enum { 69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 70 }; 71 72 static struct workqueue_struct *mlx5_ib_event_wq; 73 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 74 static LIST_HEAD(mlx5_ib_dev_list); 75 /* 76 * This mutex should be held when accessing either of the above lists 77 */ 78 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 79 80 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 81 { 82 struct mlx5_ib_dev *dev; 83 84 mutex_lock(&mlx5_ib_multiport_mutex); 85 dev = mpi->ibdev; 86 mutex_unlock(&mlx5_ib_multiport_mutex); 87 return dev; 88 } 89 90 static enum rdma_link_layer 91 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 92 { 93 switch (port_type_cap) { 94 case MLX5_CAP_PORT_TYPE_IB: 95 return IB_LINK_LAYER_INFINIBAND; 96 case MLX5_CAP_PORT_TYPE_ETH: 97 return IB_LINK_LAYER_ETHERNET; 98 default: 99 return IB_LINK_LAYER_UNSPECIFIED; 100 } 101 } 102 103 static enum rdma_link_layer 104 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 105 { 106 struct mlx5_ib_dev *dev = to_mdev(device); 107 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 108 109 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 110 } 111 112 static int get_port_state(struct ib_device *ibdev, 113 u32 port_num, 114 enum ib_port_state *state) 115 { 116 struct ib_port_attr attr; 117 int ret; 118 119 memset(&attr, 0, sizeof(attr)); 120 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 121 if (!ret) 122 *state = attr.state; 123 return ret; 124 } 125 126 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 127 struct net_device *ndev, 128 struct net_device *upper, 129 u32 *port_num) 130 { 131 struct net_device *rep_ndev; 132 struct mlx5_ib_port *port; 133 int i; 134 135 for (i = 0; i < dev->num_ports; i++) { 136 port = &dev->port[i]; 137 if (!port->rep) 138 continue; 139 140 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 141 *port_num = i + 1; 142 return &port->roce; 143 } 144 145 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 146 continue; 147 148 read_lock(&port->roce.netdev_lock); 149 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 150 port->rep->vport); 151 if (rep_ndev == ndev) { 152 read_unlock(&port->roce.netdev_lock); 153 *port_num = i + 1; 154 return &port->roce; 155 } 156 read_unlock(&port->roce.netdev_lock); 157 } 158 159 return NULL; 160 } 161 162 static int mlx5_netdev_event(struct notifier_block *this, 163 unsigned long event, void *ptr) 164 { 165 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 166 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 167 u32 port_num = roce->native_port_num; 168 struct mlx5_core_dev *mdev; 169 struct mlx5_ib_dev *ibdev; 170 171 ibdev = roce->dev; 172 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 173 if (!mdev) 174 return NOTIFY_DONE; 175 176 switch (event) { 177 case NETDEV_REGISTER: 178 /* Should already be registered during the load */ 179 if (ibdev->is_rep) 180 break; 181 write_lock(&roce->netdev_lock); 182 if (ndev->dev.parent == mdev->device) 183 roce->netdev = ndev; 184 write_unlock(&roce->netdev_lock); 185 break; 186 187 case NETDEV_UNREGISTER: 188 /* In case of reps, ib device goes away before the netdevs */ 189 write_lock(&roce->netdev_lock); 190 if (roce->netdev == ndev) 191 roce->netdev = NULL; 192 write_unlock(&roce->netdev_lock); 193 break; 194 195 case NETDEV_CHANGE: 196 case NETDEV_UP: 197 case NETDEV_DOWN: { 198 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 199 struct net_device *upper = NULL; 200 201 if (lag_ndev) { 202 upper = netdev_master_upper_dev_get(lag_ndev); 203 dev_put(lag_ndev); 204 } 205 206 if (ibdev->is_rep) 207 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 208 if (!roce) 209 return NOTIFY_DONE; 210 if ((upper == ndev || 211 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 212 ibdev->ib_active) { 213 struct ib_event ibev = { }; 214 enum ib_port_state port_state; 215 216 if (get_port_state(&ibdev->ib_dev, port_num, 217 &port_state)) 218 goto done; 219 220 if (roce->last_port_state == port_state) 221 goto done; 222 223 roce->last_port_state = port_state; 224 ibev.device = &ibdev->ib_dev; 225 if (port_state == IB_PORT_DOWN) 226 ibev.event = IB_EVENT_PORT_ERR; 227 else if (port_state == IB_PORT_ACTIVE) 228 ibev.event = IB_EVENT_PORT_ACTIVE; 229 else 230 goto done; 231 232 ibev.element.port_num = port_num; 233 ib_dispatch_event(&ibev); 234 } 235 break; 236 } 237 238 default: 239 break; 240 } 241 done: 242 mlx5_ib_put_native_port_mdev(ibdev, port_num); 243 return NOTIFY_DONE; 244 } 245 246 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 247 u32 port_num) 248 { 249 struct mlx5_ib_dev *ibdev = to_mdev(device); 250 struct net_device *ndev; 251 struct mlx5_core_dev *mdev; 252 253 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 254 if (!mdev) 255 return NULL; 256 257 ndev = mlx5_lag_get_roce_netdev(mdev); 258 if (ndev) 259 goto out; 260 261 /* Ensure ndev does not disappear before we invoke dev_hold() 262 */ 263 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 264 ndev = ibdev->port[port_num - 1].roce.netdev; 265 if (ndev) 266 dev_hold(ndev); 267 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 268 269 out: 270 mlx5_ib_put_native_port_mdev(ibdev, port_num); 271 return ndev; 272 } 273 274 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 275 u32 ib_port_num, 276 u32 *native_port_num) 277 { 278 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 279 ib_port_num); 280 struct mlx5_core_dev *mdev = NULL; 281 struct mlx5_ib_multiport_info *mpi; 282 struct mlx5_ib_port *port; 283 284 if (!mlx5_core_mp_enabled(ibdev->mdev) || 285 ll != IB_LINK_LAYER_ETHERNET) { 286 if (native_port_num) 287 *native_port_num = ib_port_num; 288 return ibdev->mdev; 289 } 290 291 if (native_port_num) 292 *native_port_num = 1; 293 294 port = &ibdev->port[ib_port_num - 1]; 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 297 if (mpi && !mpi->unaffiliate) { 298 mdev = mpi->mdev; 299 /* If it's the master no need to refcount, it'll exist 300 * as long as the ib_dev exists. 301 */ 302 if (!mpi->is_master) 303 mpi->mdev_refcnt++; 304 } 305 spin_unlock(&port->mp.mpi_lock); 306 307 return mdev; 308 } 309 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 311 { 312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 313 port_num); 314 struct mlx5_ib_multiport_info *mpi; 315 struct mlx5_ib_port *port; 316 317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 318 return; 319 320 port = &ibdev->port[port_num - 1]; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[port_num - 1].mp.mpi; 324 if (mpi->is_master) 325 goto out; 326 327 mpi->mdev_refcnt--; 328 if (mpi->unaffiliate) 329 complete(&mpi->unref_comp); 330 out: 331 spin_unlock(&port->mp.mpi_lock); 332 } 333 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 335 u16 *active_speed, u8 *active_width) 336 { 337 switch (eth_proto_oper) { 338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_SDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 352 *active_width = IB_WIDTH_1X; 353 *active_speed = IB_SPEED_QDR; 354 break; 355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 358 *active_width = IB_WIDTH_1X; 359 *active_speed = IB_SPEED_EDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_QDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_HDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_FDR; 377 break; 378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 382 *active_width = IB_WIDTH_4X; 383 *active_speed = IB_SPEED_EDR; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 393 u8 *active_width) 394 { 395 switch (eth_proto_oper) { 396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_SDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_DDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 406 *active_width = IB_WIDTH_1X; 407 *active_speed = IB_SPEED_QDR; 408 break; 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_EDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 418 *active_width = IB_WIDTH_2X; 419 *active_speed = IB_SPEED_EDR; 420 break; 421 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 422 *active_width = IB_WIDTH_1X; 423 *active_speed = IB_SPEED_HDR; 424 break; 425 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 430 *active_width = IB_WIDTH_2X; 431 *active_speed = IB_SPEED_HDR; 432 break; 433 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 434 *active_width = IB_WIDTH_1X; 435 *active_speed = IB_SPEED_NDR; 436 break; 437 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 438 *active_width = IB_WIDTH_4X; 439 *active_speed = IB_SPEED_HDR; 440 break; 441 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 442 *active_width = IB_WIDTH_2X; 443 *active_speed = IB_SPEED_NDR; 444 break; 445 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 446 *active_width = IB_WIDTH_4X; 447 *active_speed = IB_SPEED_NDR; 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 return 0; 454 } 455 456 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 457 u8 *active_width, bool ext) 458 { 459 return ext ? 460 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 461 active_width) : 462 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 463 active_width); 464 } 465 466 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 467 struct ib_port_attr *props) 468 { 469 struct mlx5_ib_dev *dev = to_mdev(device); 470 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 471 struct mlx5_core_dev *mdev; 472 struct net_device *ndev, *upper; 473 enum ib_mtu ndev_ib_mtu; 474 bool put_mdev = true; 475 u32 eth_prot_oper; 476 u32 mdev_port_num; 477 bool ext; 478 int err; 479 480 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 481 if (!mdev) { 482 /* This means the port isn't affiliated yet. Get the 483 * info for the master port instead. 484 */ 485 put_mdev = false; 486 mdev = dev->mdev; 487 mdev_port_num = 1; 488 port_num = 1; 489 } 490 491 /* Possible bad flows are checked before filling out props so in case 492 * of an error it will still be zeroed out. 493 * Use native port in case of reps 494 */ 495 if (dev->is_rep) 496 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 497 1); 498 else 499 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 500 mdev_port_num); 501 if (err) 502 goto out; 503 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 504 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 505 506 props->active_width = IB_WIDTH_4X; 507 props->active_speed = IB_SPEED_QDR; 508 509 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 510 &props->active_width, ext); 511 512 if (!dev->is_rep && dev->mdev->roce.roce_en) { 513 u16 qkey_viol_cntr; 514 515 props->port_cap_flags |= IB_PORT_CM_SUP; 516 props->ip_gids = true; 517 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 518 roce_address_table_size); 519 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 520 props->qkey_viol_cntr = qkey_viol_cntr; 521 } 522 props->max_mtu = IB_MTU_4096; 523 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 524 props->pkey_tbl_len = 1; 525 props->state = IB_PORT_DOWN; 526 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 527 528 /* If this is a stub query for an unaffiliated port stop here */ 529 if (!put_mdev) 530 goto out; 531 532 ndev = mlx5_ib_get_netdev(device, port_num); 533 if (!ndev) 534 goto out; 535 536 if (dev->lag_active) { 537 rcu_read_lock(); 538 upper = netdev_master_upper_dev_get_rcu(ndev); 539 if (upper) { 540 dev_put(ndev); 541 ndev = upper; 542 dev_hold(ndev); 543 } 544 rcu_read_unlock(); 545 } 546 547 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 548 props->state = IB_PORT_ACTIVE; 549 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 550 } 551 552 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 553 554 dev_put(ndev); 555 556 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 557 out: 558 if (put_mdev) 559 mlx5_ib_put_native_port_mdev(dev, port_num); 560 return err; 561 } 562 563 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 564 unsigned int index, const union ib_gid *gid, 565 const struct ib_gid_attr *attr) 566 { 567 enum ib_gid_type gid_type; 568 u16 vlan_id = 0xffff; 569 u8 roce_version = 0; 570 u8 roce_l3_type = 0; 571 u8 mac[ETH_ALEN]; 572 int ret; 573 574 gid_type = attr->gid_type; 575 if (gid) { 576 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 577 if (ret) 578 return ret; 579 } 580 581 switch (gid_type) { 582 case IB_GID_TYPE_ROCE: 583 roce_version = MLX5_ROCE_VERSION_1; 584 break; 585 case IB_GID_TYPE_ROCE_UDP_ENCAP: 586 roce_version = MLX5_ROCE_VERSION_2; 587 if (gid && ipv6_addr_v4mapped((void *)gid)) 588 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 589 else 590 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 591 break; 592 593 default: 594 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 595 } 596 597 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 598 roce_l3_type, gid->raw, mac, 599 vlan_id < VLAN_CFI_MASK, vlan_id, 600 port_num); 601 } 602 603 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 604 __always_unused void **context) 605 { 606 return set_roce_addr(to_mdev(attr->device), attr->port_num, 607 attr->index, &attr->gid, attr); 608 } 609 610 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 611 __always_unused void **context) 612 { 613 return set_roce_addr(to_mdev(attr->device), attr->port_num, 614 attr->index, NULL, attr); 615 } 616 617 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 618 const struct ib_gid_attr *attr) 619 { 620 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 621 return 0; 622 623 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 624 } 625 626 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 627 { 628 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 629 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 630 return 0; 631 } 632 633 enum { 634 MLX5_VPORT_ACCESS_METHOD_MAD, 635 MLX5_VPORT_ACCESS_METHOD_HCA, 636 MLX5_VPORT_ACCESS_METHOD_NIC, 637 }; 638 639 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 640 { 641 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 642 return MLX5_VPORT_ACCESS_METHOD_MAD; 643 644 if (mlx5_ib_port_link_layer(ibdev, 1) == 645 IB_LINK_LAYER_ETHERNET) 646 return MLX5_VPORT_ACCESS_METHOD_NIC; 647 648 return MLX5_VPORT_ACCESS_METHOD_HCA; 649 } 650 651 static void get_atomic_caps(struct mlx5_ib_dev *dev, 652 u8 atomic_size_qp, 653 struct ib_device_attr *props) 654 { 655 u8 tmp; 656 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 657 u8 atomic_req_8B_endianness_mode = 658 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 659 660 /* Check if HW supports 8 bytes standard atomic operations and capable 661 * of host endianness respond 662 */ 663 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 664 if (((atomic_operations & tmp) == tmp) && 665 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 666 (atomic_req_8B_endianness_mode)) { 667 props->atomic_cap = IB_ATOMIC_HCA; 668 } else { 669 props->atomic_cap = IB_ATOMIC_NONE; 670 } 671 } 672 673 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 674 struct ib_device_attr *props) 675 { 676 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 677 678 get_atomic_caps(dev, atomic_size_qp, props); 679 } 680 681 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 682 __be64 *sys_image_guid) 683 { 684 struct mlx5_ib_dev *dev = to_mdev(ibdev); 685 struct mlx5_core_dev *mdev = dev->mdev; 686 u64 tmp; 687 int err; 688 689 switch (mlx5_get_vport_access_method(ibdev)) { 690 case MLX5_VPORT_ACCESS_METHOD_MAD: 691 return mlx5_query_mad_ifc_system_image_guid(ibdev, 692 sys_image_guid); 693 694 case MLX5_VPORT_ACCESS_METHOD_HCA: 695 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 696 break; 697 698 case MLX5_VPORT_ACCESS_METHOD_NIC: 699 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 700 break; 701 702 default: 703 return -EINVAL; 704 } 705 706 if (!err) 707 *sys_image_guid = cpu_to_be64(tmp); 708 709 return err; 710 711 } 712 713 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 714 u16 *max_pkeys) 715 { 716 struct mlx5_ib_dev *dev = to_mdev(ibdev); 717 struct mlx5_core_dev *mdev = dev->mdev; 718 719 switch (mlx5_get_vport_access_method(ibdev)) { 720 case MLX5_VPORT_ACCESS_METHOD_MAD: 721 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 722 723 case MLX5_VPORT_ACCESS_METHOD_HCA: 724 case MLX5_VPORT_ACCESS_METHOD_NIC: 725 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 726 pkey_table_size)); 727 return 0; 728 729 default: 730 return -EINVAL; 731 } 732 } 733 734 static int mlx5_query_vendor_id(struct ib_device *ibdev, 735 u32 *vendor_id) 736 { 737 struct mlx5_ib_dev *dev = to_mdev(ibdev); 738 739 switch (mlx5_get_vport_access_method(ibdev)) { 740 case MLX5_VPORT_ACCESS_METHOD_MAD: 741 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 742 743 case MLX5_VPORT_ACCESS_METHOD_HCA: 744 case MLX5_VPORT_ACCESS_METHOD_NIC: 745 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 746 747 default: 748 return -EINVAL; 749 } 750 } 751 752 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 753 __be64 *node_guid) 754 { 755 u64 tmp; 756 int err; 757 758 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 759 case MLX5_VPORT_ACCESS_METHOD_MAD: 760 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 761 762 case MLX5_VPORT_ACCESS_METHOD_HCA: 763 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 764 break; 765 766 case MLX5_VPORT_ACCESS_METHOD_NIC: 767 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 768 break; 769 770 default: 771 return -EINVAL; 772 } 773 774 if (!err) 775 *node_guid = cpu_to_be64(tmp); 776 777 return err; 778 } 779 780 struct mlx5_reg_node_desc { 781 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 782 }; 783 784 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 785 { 786 struct mlx5_reg_node_desc in; 787 788 if (mlx5_use_mad_ifc(dev)) 789 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 790 791 memset(&in, 0, sizeof(in)); 792 793 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 794 sizeof(struct mlx5_reg_node_desc), 795 MLX5_REG_NODE_DESC, 0, 0); 796 } 797 798 static int mlx5_ib_query_device(struct ib_device *ibdev, 799 struct ib_device_attr *props, 800 struct ib_udata *uhw) 801 { 802 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 803 struct mlx5_ib_dev *dev = to_mdev(ibdev); 804 struct mlx5_core_dev *mdev = dev->mdev; 805 int err = -ENOMEM; 806 int max_sq_desc; 807 int max_rq_sg; 808 int max_sq_sg; 809 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 810 bool raw_support = !mlx5_core_mp_enabled(mdev); 811 struct mlx5_ib_query_device_resp resp = {}; 812 size_t resp_len; 813 u64 max_tso; 814 815 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 816 if (uhw_outlen && uhw_outlen < resp_len) 817 return -EINVAL; 818 819 resp.response_length = resp_len; 820 821 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 822 return -EINVAL; 823 824 memset(props, 0, sizeof(*props)); 825 err = mlx5_query_system_image_guid(ibdev, 826 &props->sys_image_guid); 827 if (err) 828 return err; 829 830 props->max_pkeys = dev->pkey_table_len; 831 832 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 833 if (err) 834 return err; 835 836 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 837 (fw_rev_min(dev->mdev) << 16) | 838 fw_rev_sub(dev->mdev); 839 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 840 IB_DEVICE_PORT_ACTIVE_EVENT | 841 IB_DEVICE_SYS_IMAGE_GUID | 842 IB_DEVICE_RC_RNR_NAK_GEN; 843 844 if (MLX5_CAP_GEN(mdev, pkv)) 845 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 846 if (MLX5_CAP_GEN(mdev, qkv)) 847 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 848 if (MLX5_CAP_GEN(mdev, apm)) 849 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 850 if (MLX5_CAP_GEN(mdev, xrc)) 851 props->device_cap_flags |= IB_DEVICE_XRC; 852 if (MLX5_CAP_GEN(mdev, imaicl)) { 853 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 854 IB_DEVICE_MEM_WINDOW_TYPE_2B; 855 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 856 /* We support 'Gappy' memory registration too */ 857 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 858 } 859 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 860 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 861 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 862 if (MLX5_CAP_GEN(mdev, sho)) { 863 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 864 /* At this stage no support for signature handover */ 865 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 866 IB_PROT_T10DIF_TYPE_2 | 867 IB_PROT_T10DIF_TYPE_3; 868 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 869 IB_GUARD_T10DIF_CSUM; 870 } 871 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 872 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 873 874 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 875 if (MLX5_CAP_ETH(mdev, csum_cap)) { 876 /* Legacy bit to support old userspace libraries */ 877 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 878 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 879 } 880 881 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 882 props->raw_packet_caps |= 883 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 884 885 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 886 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 887 if (max_tso) { 888 resp.tso_caps.max_tso = 1 << max_tso; 889 resp.tso_caps.supported_qpts |= 890 1 << IB_QPT_RAW_PACKET; 891 resp.response_length += sizeof(resp.tso_caps); 892 } 893 } 894 895 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 896 resp.rss_caps.rx_hash_function = 897 MLX5_RX_HASH_FUNC_TOEPLITZ; 898 resp.rss_caps.rx_hash_fields_mask = 899 MLX5_RX_HASH_SRC_IPV4 | 900 MLX5_RX_HASH_DST_IPV4 | 901 MLX5_RX_HASH_SRC_IPV6 | 902 MLX5_RX_HASH_DST_IPV6 | 903 MLX5_RX_HASH_SRC_PORT_TCP | 904 MLX5_RX_HASH_DST_PORT_TCP | 905 MLX5_RX_HASH_SRC_PORT_UDP | 906 MLX5_RX_HASH_DST_PORT_UDP | 907 MLX5_RX_HASH_INNER; 908 resp.response_length += sizeof(resp.rss_caps); 909 } 910 } else { 911 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 912 resp.response_length += sizeof(resp.tso_caps); 913 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 914 resp.response_length += sizeof(resp.rss_caps); 915 } 916 917 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 918 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 919 props->device_cap_flags |= IB_DEVICE_UD_TSO; 920 } 921 922 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 923 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 924 raw_support) 925 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 926 927 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 928 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 929 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 930 931 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 932 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 933 raw_support) { 934 /* Legacy bit to support old userspace libraries */ 935 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 936 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 937 } 938 939 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 940 props->max_dm_size = 941 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 942 } 943 944 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 945 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 946 947 if (MLX5_CAP_GEN(mdev, end_pad)) 948 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 949 950 props->vendor_part_id = mdev->pdev->device; 951 props->hw_ver = mdev->pdev->revision; 952 953 props->max_mr_size = ~0ull; 954 props->page_size_cap = ~(min_page_size - 1); 955 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 956 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 957 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 958 sizeof(struct mlx5_wqe_data_seg); 959 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 960 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 961 sizeof(struct mlx5_wqe_raddr_seg)) / 962 sizeof(struct mlx5_wqe_data_seg); 963 props->max_send_sge = max_sq_sg; 964 props->max_recv_sge = max_rq_sg; 965 props->max_sge_rd = MLX5_MAX_SGE_RD; 966 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 967 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 968 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 969 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 970 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 971 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 972 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 973 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 974 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 975 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 976 props->max_srq_sge = max_rq_sg - 1; 977 props->max_fast_reg_page_list_len = 978 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 979 props->max_pi_fast_reg_page_list_len = 980 props->max_fast_reg_page_list_len / 2; 981 props->max_sgl_rd = 982 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 983 get_atomic_caps_qp(dev, props); 984 props->masked_atomic_cap = IB_ATOMIC_NONE; 985 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 986 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 987 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 988 props->max_mcast_grp; 989 props->max_ah = INT_MAX; 990 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 991 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 992 993 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 994 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 995 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 996 props->odp_caps = dev->odp_caps; 997 if (!uhw) { 998 /* ODP for kernel QPs is not implemented for receive 999 * WQEs and SRQ WQEs 1000 */ 1001 props->odp_caps.per_transport_caps.rc_odp_caps &= 1002 ~(IB_ODP_SUPPORT_READ | 1003 IB_ODP_SUPPORT_SRQ_RECV); 1004 props->odp_caps.per_transport_caps.uc_odp_caps &= 1005 ~(IB_ODP_SUPPORT_READ | 1006 IB_ODP_SUPPORT_SRQ_RECV); 1007 props->odp_caps.per_transport_caps.ud_odp_caps &= 1008 ~(IB_ODP_SUPPORT_READ | 1009 IB_ODP_SUPPORT_SRQ_RECV); 1010 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1011 ~(IB_ODP_SUPPORT_READ | 1012 IB_ODP_SUPPORT_SRQ_RECV); 1013 } 1014 } 1015 1016 if (MLX5_CAP_GEN(mdev, cd)) 1017 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1018 1019 if (mlx5_core_is_vf(mdev)) 1020 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1021 1022 if (mlx5_ib_port_link_layer(ibdev, 1) == 1023 IB_LINK_LAYER_ETHERNET && raw_support) { 1024 props->rss_caps.max_rwq_indirection_tables = 1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1026 props->rss_caps.max_rwq_indirection_table_size = 1027 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1028 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1029 props->max_wq_type_rq = 1030 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1031 } 1032 1033 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1034 props->tm_caps.max_num_tags = 1035 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1036 props->tm_caps.max_ops = 1037 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1038 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1039 } 1040 1041 if (MLX5_CAP_GEN(mdev, tag_matching) && 1042 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1043 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1044 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1045 } 1046 1047 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1048 props->cq_caps.max_cq_moderation_count = 1049 MLX5_MAX_CQ_COUNT; 1050 props->cq_caps.max_cq_moderation_period = 1051 MLX5_MAX_CQ_PERIOD; 1052 } 1053 1054 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1055 resp.response_length += sizeof(resp.cqe_comp_caps); 1056 1057 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1058 resp.cqe_comp_caps.max_num = 1059 MLX5_CAP_GEN(dev->mdev, 1060 cqe_compression_max_num); 1061 1062 resp.cqe_comp_caps.supported_format = 1063 MLX5_IB_CQE_RES_FORMAT_HASH | 1064 MLX5_IB_CQE_RES_FORMAT_CSUM; 1065 1066 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1067 resp.cqe_comp_caps.supported_format |= 1068 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1069 } 1070 } 1071 1072 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1073 raw_support) { 1074 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1075 MLX5_CAP_GEN(mdev, qos)) { 1076 resp.packet_pacing_caps.qp_rate_limit_max = 1077 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1078 resp.packet_pacing_caps.qp_rate_limit_min = 1079 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1080 resp.packet_pacing_caps.supported_qpts |= 1081 1 << IB_QPT_RAW_PACKET; 1082 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1083 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1084 resp.packet_pacing_caps.cap_flags |= 1085 MLX5_IB_PP_SUPPORT_BURST; 1086 } 1087 resp.response_length += sizeof(resp.packet_pacing_caps); 1088 } 1089 1090 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1091 uhw_outlen) { 1092 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1093 resp.mlx5_ib_support_multi_pkt_send_wqes = 1094 MLX5_IB_ALLOW_MPW; 1095 1096 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1097 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1098 MLX5_IB_SUPPORT_EMPW; 1099 1100 resp.response_length += 1101 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1102 } 1103 1104 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1105 resp.response_length += sizeof(resp.flags); 1106 1107 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1108 resp.flags |= 1109 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1110 1111 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1113 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1114 resp.flags |= 1115 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1116 1117 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1118 } 1119 1120 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1121 resp.response_length += sizeof(resp.sw_parsing_caps); 1122 if (MLX5_CAP_ETH(mdev, swp)) { 1123 resp.sw_parsing_caps.sw_parsing_offloads |= 1124 MLX5_IB_SW_PARSING; 1125 1126 if (MLX5_CAP_ETH(mdev, swp_csum)) 1127 resp.sw_parsing_caps.sw_parsing_offloads |= 1128 MLX5_IB_SW_PARSING_CSUM; 1129 1130 if (MLX5_CAP_ETH(mdev, swp_lso)) 1131 resp.sw_parsing_caps.sw_parsing_offloads |= 1132 MLX5_IB_SW_PARSING_LSO; 1133 1134 if (resp.sw_parsing_caps.sw_parsing_offloads) 1135 resp.sw_parsing_caps.supported_qpts = 1136 BIT(IB_QPT_RAW_PACKET); 1137 } 1138 } 1139 1140 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1141 raw_support) { 1142 resp.response_length += sizeof(resp.striding_rq_caps); 1143 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1144 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1145 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1146 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1147 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1148 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1149 resp.striding_rq_caps 1150 .min_single_wqe_log_num_of_strides = 1151 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1152 else 1153 resp.striding_rq_caps 1154 .min_single_wqe_log_num_of_strides = 1155 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1156 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1157 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1158 resp.striding_rq_caps.supported_qpts = 1159 BIT(IB_QPT_RAW_PACKET); 1160 } 1161 } 1162 1163 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1164 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1165 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1166 resp.tunnel_offloads_caps |= 1167 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1168 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1169 resp.tunnel_offloads_caps |= 1170 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1171 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1172 resp.tunnel_offloads_caps |= 1173 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1174 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1175 resp.tunnel_offloads_caps |= 1176 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1177 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1178 resp.tunnel_offloads_caps |= 1179 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1180 } 1181 1182 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1183 resp.response_length += sizeof(resp.dci_streams_caps); 1184 1185 resp.dci_streams_caps.max_log_num_concurent = 1186 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1187 1188 resp.dci_streams_caps.max_log_num_errored = 1189 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1190 } 1191 1192 if (uhw_outlen) { 1193 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1194 1195 if (err) 1196 return err; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1203 u8 *ib_width) 1204 { 1205 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1206 1207 if (active_width & MLX5_PTYS_WIDTH_1X) 1208 *ib_width = IB_WIDTH_1X; 1209 else if (active_width & MLX5_PTYS_WIDTH_2X) 1210 *ib_width = IB_WIDTH_2X; 1211 else if (active_width & MLX5_PTYS_WIDTH_4X) 1212 *ib_width = IB_WIDTH_4X; 1213 else if (active_width & MLX5_PTYS_WIDTH_8X) 1214 *ib_width = IB_WIDTH_8X; 1215 else if (active_width & MLX5_PTYS_WIDTH_12X) 1216 *ib_width = IB_WIDTH_12X; 1217 else { 1218 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1219 active_width); 1220 *ib_width = IB_WIDTH_4X; 1221 } 1222 1223 return; 1224 } 1225 1226 static int mlx5_mtu_to_ib_mtu(int mtu) 1227 { 1228 switch (mtu) { 1229 case 256: return 1; 1230 case 512: return 2; 1231 case 1024: return 3; 1232 case 2048: return 4; 1233 case 4096: return 5; 1234 default: 1235 pr_warn("invalid mtu\n"); 1236 return -1; 1237 } 1238 } 1239 1240 enum ib_max_vl_num { 1241 __IB_MAX_VL_0 = 1, 1242 __IB_MAX_VL_0_1 = 2, 1243 __IB_MAX_VL_0_3 = 3, 1244 __IB_MAX_VL_0_7 = 4, 1245 __IB_MAX_VL_0_14 = 5, 1246 }; 1247 1248 enum mlx5_vl_hw_cap { 1249 MLX5_VL_HW_0 = 1, 1250 MLX5_VL_HW_0_1 = 2, 1251 MLX5_VL_HW_0_2 = 3, 1252 MLX5_VL_HW_0_3 = 4, 1253 MLX5_VL_HW_0_4 = 5, 1254 MLX5_VL_HW_0_5 = 6, 1255 MLX5_VL_HW_0_6 = 7, 1256 MLX5_VL_HW_0_7 = 8, 1257 MLX5_VL_HW_0_14 = 15 1258 }; 1259 1260 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1261 u8 *max_vl_num) 1262 { 1263 switch (vl_hw_cap) { 1264 case MLX5_VL_HW_0: 1265 *max_vl_num = __IB_MAX_VL_0; 1266 break; 1267 case MLX5_VL_HW_0_1: 1268 *max_vl_num = __IB_MAX_VL_0_1; 1269 break; 1270 case MLX5_VL_HW_0_3: 1271 *max_vl_num = __IB_MAX_VL_0_3; 1272 break; 1273 case MLX5_VL_HW_0_7: 1274 *max_vl_num = __IB_MAX_VL_0_7; 1275 break; 1276 case MLX5_VL_HW_0_14: 1277 *max_vl_num = __IB_MAX_VL_0_14; 1278 break; 1279 1280 default: 1281 return -EINVAL; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1288 struct ib_port_attr *props) 1289 { 1290 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1291 struct mlx5_core_dev *mdev = dev->mdev; 1292 struct mlx5_hca_vport_context *rep; 1293 u16 max_mtu; 1294 u16 oper_mtu; 1295 int err; 1296 u16 ib_link_width_oper; 1297 u8 vl_hw_cap; 1298 1299 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1300 if (!rep) { 1301 err = -ENOMEM; 1302 goto out; 1303 } 1304 1305 /* props being zeroed by the caller, avoid zeroing it here */ 1306 1307 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1308 if (err) 1309 goto out; 1310 1311 props->lid = rep->lid; 1312 props->lmc = rep->lmc; 1313 props->sm_lid = rep->sm_lid; 1314 props->sm_sl = rep->sm_sl; 1315 props->state = rep->vport_state; 1316 props->phys_state = rep->port_physical_state; 1317 props->port_cap_flags = rep->cap_mask1; 1318 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1319 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1320 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1321 props->bad_pkey_cntr = rep->pkey_violation_counter; 1322 props->qkey_viol_cntr = rep->qkey_violation_counter; 1323 props->subnet_timeout = rep->subnet_timeout; 1324 props->init_type_reply = rep->init_type_reply; 1325 1326 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1327 props->port_cap_flags2 = rep->cap_mask2; 1328 1329 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1330 &props->active_speed, port); 1331 if (err) 1332 goto out; 1333 1334 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1335 1336 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1337 1338 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1339 1340 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1341 1342 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1343 1344 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1345 if (err) 1346 goto out; 1347 1348 err = translate_max_vl_num(ibdev, vl_hw_cap, 1349 &props->max_vl_num); 1350 out: 1351 kfree(rep); 1352 return err; 1353 } 1354 1355 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1356 struct ib_port_attr *props) 1357 { 1358 unsigned int count; 1359 int ret; 1360 1361 switch (mlx5_get_vport_access_method(ibdev)) { 1362 case MLX5_VPORT_ACCESS_METHOD_MAD: 1363 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1364 break; 1365 1366 case MLX5_VPORT_ACCESS_METHOD_HCA: 1367 ret = mlx5_query_hca_port(ibdev, port, props); 1368 break; 1369 1370 case MLX5_VPORT_ACCESS_METHOD_NIC: 1371 ret = mlx5_query_port_roce(ibdev, port, props); 1372 break; 1373 1374 default: 1375 ret = -EINVAL; 1376 } 1377 1378 if (!ret && props) { 1379 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1380 struct mlx5_core_dev *mdev; 1381 bool put_mdev = true; 1382 1383 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1384 if (!mdev) { 1385 /* If the port isn't affiliated yet query the master. 1386 * The master and slave will have the same values. 1387 */ 1388 mdev = dev->mdev; 1389 port = 1; 1390 put_mdev = false; 1391 } 1392 count = mlx5_core_reserved_gids_count(mdev); 1393 if (put_mdev) 1394 mlx5_ib_put_native_port_mdev(dev, port); 1395 props->gid_tbl_len -= count; 1396 } 1397 return ret; 1398 } 1399 1400 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1401 struct ib_port_attr *props) 1402 { 1403 return mlx5_query_port_roce(ibdev, port, props); 1404 } 1405 1406 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1407 u16 *pkey) 1408 { 1409 /* Default special Pkey for representor device port as per the 1410 * IB specification 1.3 section 10.9.1.2. 1411 */ 1412 *pkey = 0xffff; 1413 return 0; 1414 } 1415 1416 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1417 union ib_gid *gid) 1418 { 1419 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1420 struct mlx5_core_dev *mdev = dev->mdev; 1421 1422 switch (mlx5_get_vport_access_method(ibdev)) { 1423 case MLX5_VPORT_ACCESS_METHOD_MAD: 1424 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1425 1426 case MLX5_VPORT_ACCESS_METHOD_HCA: 1427 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1428 1429 default: 1430 return -EINVAL; 1431 } 1432 1433 } 1434 1435 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1436 u16 index, u16 *pkey) 1437 { 1438 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1439 struct mlx5_core_dev *mdev; 1440 bool put_mdev = true; 1441 u32 mdev_port_num; 1442 int err; 1443 1444 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1445 if (!mdev) { 1446 /* The port isn't affiliated yet, get the PKey from the master 1447 * port. For RoCE the PKey tables will be the same. 1448 */ 1449 put_mdev = false; 1450 mdev = dev->mdev; 1451 mdev_port_num = 1; 1452 } 1453 1454 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1455 index, pkey); 1456 if (put_mdev) 1457 mlx5_ib_put_native_port_mdev(dev, port); 1458 1459 return err; 1460 } 1461 1462 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1463 u16 *pkey) 1464 { 1465 switch (mlx5_get_vport_access_method(ibdev)) { 1466 case MLX5_VPORT_ACCESS_METHOD_MAD: 1467 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1468 1469 case MLX5_VPORT_ACCESS_METHOD_HCA: 1470 case MLX5_VPORT_ACCESS_METHOD_NIC: 1471 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1472 default: 1473 return -EINVAL; 1474 } 1475 } 1476 1477 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1478 struct ib_device_modify *props) 1479 { 1480 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1481 struct mlx5_reg_node_desc in; 1482 struct mlx5_reg_node_desc out; 1483 int err; 1484 1485 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1486 return -EOPNOTSUPP; 1487 1488 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1489 return 0; 1490 1491 /* 1492 * If possible, pass node desc to FW, so it can generate 1493 * a 144 trap. If cmd fails, just ignore. 1494 */ 1495 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1496 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1497 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1498 if (err) 1499 return err; 1500 1501 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1502 1503 return err; 1504 } 1505 1506 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1507 u32 value) 1508 { 1509 struct mlx5_hca_vport_context ctx = {}; 1510 struct mlx5_core_dev *mdev; 1511 u32 mdev_port_num; 1512 int err; 1513 1514 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1515 if (!mdev) 1516 return -ENODEV; 1517 1518 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1519 if (err) 1520 goto out; 1521 1522 if (~ctx.cap_mask1_perm & mask) { 1523 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1524 mask, ctx.cap_mask1_perm); 1525 err = -EINVAL; 1526 goto out; 1527 } 1528 1529 ctx.cap_mask1 = value; 1530 ctx.cap_mask1_perm = mask; 1531 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1532 0, &ctx); 1533 1534 out: 1535 mlx5_ib_put_native_port_mdev(dev, port_num); 1536 1537 return err; 1538 } 1539 1540 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1541 struct ib_port_modify *props) 1542 { 1543 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1544 struct ib_port_attr attr; 1545 u32 tmp; 1546 int err; 1547 u32 change_mask; 1548 u32 value; 1549 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1550 IB_LINK_LAYER_INFINIBAND); 1551 1552 /* CM layer calls ib_modify_port() regardless of the link layer. For 1553 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1554 */ 1555 if (!is_ib) 1556 return 0; 1557 1558 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1559 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1560 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1561 return set_port_caps_atomic(dev, port, change_mask, value); 1562 } 1563 1564 mutex_lock(&dev->cap_mask_mutex); 1565 1566 err = ib_query_port(ibdev, port, &attr); 1567 if (err) 1568 goto out; 1569 1570 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1571 ~props->clr_port_cap_mask; 1572 1573 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1574 1575 out: 1576 mutex_unlock(&dev->cap_mask_mutex); 1577 return err; 1578 } 1579 1580 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1581 { 1582 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1583 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1584 } 1585 1586 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1587 { 1588 /* Large page with non 4k uar support might limit the dynamic size */ 1589 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1590 return MLX5_MIN_DYN_BFREGS; 1591 1592 return MLX5_MAX_DYN_BFREGS; 1593 } 1594 1595 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1596 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1597 struct mlx5_bfreg_info *bfregi) 1598 { 1599 int uars_per_sys_page; 1600 int bfregs_per_sys_page; 1601 int ref_bfregs = req->total_num_bfregs; 1602 1603 if (req->total_num_bfregs == 0) 1604 return -EINVAL; 1605 1606 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1607 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1608 1609 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1610 return -ENOMEM; 1611 1612 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1613 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1614 /* This holds the required static allocation asked by the user */ 1615 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1616 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1617 return -EINVAL; 1618 1619 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1620 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1621 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1622 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1623 1624 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1625 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1626 lib_uar_4k ? "yes" : "no", ref_bfregs, 1627 req->total_num_bfregs, bfregi->total_num_bfregs, 1628 bfregi->num_sys_pages); 1629 1630 return 0; 1631 } 1632 1633 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1634 { 1635 struct mlx5_bfreg_info *bfregi; 1636 int err; 1637 int i; 1638 1639 bfregi = &context->bfregi; 1640 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1641 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1642 context->devx_uid); 1643 if (err) 1644 goto error; 1645 1646 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1647 } 1648 1649 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1650 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1651 1652 return 0; 1653 1654 error: 1655 for (--i; i >= 0; i--) 1656 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1657 context->devx_uid)) 1658 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1659 1660 return err; 1661 } 1662 1663 static void deallocate_uars(struct mlx5_ib_dev *dev, 1664 struct mlx5_ib_ucontext *context) 1665 { 1666 struct mlx5_bfreg_info *bfregi; 1667 int i; 1668 1669 bfregi = &context->bfregi; 1670 for (i = 0; i < bfregi->num_sys_pages; i++) 1671 if (i < bfregi->num_static_sys_pages || 1672 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1673 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1674 context->devx_uid); 1675 } 1676 1677 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1678 { 1679 int err = 0; 1680 1681 mutex_lock(&dev->lb.mutex); 1682 if (td) 1683 dev->lb.user_td++; 1684 if (qp) 1685 dev->lb.qps++; 1686 1687 if (dev->lb.user_td == 2 || 1688 dev->lb.qps == 1) { 1689 if (!dev->lb.enabled) { 1690 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1691 dev->lb.enabled = true; 1692 } 1693 } 1694 1695 mutex_unlock(&dev->lb.mutex); 1696 1697 return err; 1698 } 1699 1700 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1701 { 1702 mutex_lock(&dev->lb.mutex); 1703 if (td) 1704 dev->lb.user_td--; 1705 if (qp) 1706 dev->lb.qps--; 1707 1708 if (dev->lb.user_td == 1 && 1709 dev->lb.qps == 0) { 1710 if (dev->lb.enabled) { 1711 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1712 dev->lb.enabled = false; 1713 } 1714 } 1715 1716 mutex_unlock(&dev->lb.mutex); 1717 } 1718 1719 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1720 u16 uid) 1721 { 1722 int err; 1723 1724 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1725 return 0; 1726 1727 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1728 if (err) 1729 return err; 1730 1731 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1732 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1733 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1734 return err; 1735 1736 return mlx5_ib_enable_lb(dev, true, false); 1737 } 1738 1739 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1740 u16 uid) 1741 { 1742 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1743 return; 1744 1745 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1746 1747 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1748 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1749 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1750 return; 1751 1752 mlx5_ib_disable_lb(dev, true, false); 1753 } 1754 1755 static int set_ucontext_resp(struct ib_ucontext *uctx, 1756 struct mlx5_ib_alloc_ucontext_resp *resp) 1757 { 1758 struct ib_device *ibdev = uctx->device; 1759 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1760 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1761 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1762 int err; 1763 1764 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1765 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1766 &resp->dump_fill_mkey); 1767 if (err) 1768 return err; 1769 resp->comp_mask |= 1770 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1771 } 1772 1773 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1774 if (dev->wc_support) 1775 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1776 log_bf_reg_size); 1777 resp->cache_line_size = cache_line_size(); 1778 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1779 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1780 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1781 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1782 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1783 resp->cqe_version = context->cqe_version; 1784 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1785 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1786 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1787 MLX5_CAP_GEN(dev->mdev, 1788 num_of_uars_per_page) : 1; 1789 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1790 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1791 resp->num_ports = dev->num_ports; 1792 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1793 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1794 1795 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1796 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1797 resp->eth_min_inline++; 1798 } 1799 1800 if (dev->mdev->clock_info) 1801 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1802 1803 /* 1804 * We don't want to expose information from the PCI bar that is located 1805 * after 4096 bytes, so if the arch only supports larger pages, let's 1806 * pretend we don't support reading the HCA's core clock. This is also 1807 * forced by mmap function. 1808 */ 1809 if (PAGE_SIZE <= 4096) { 1810 resp->comp_mask |= 1811 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1812 resp->hca_core_clock_offset = 1813 offsetof(struct mlx5_init_seg, 1814 internal_timer_h) % PAGE_SIZE; 1815 } 1816 1817 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1818 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1819 1820 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1821 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1822 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1823 resp->comp_mask |= 1824 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1825 1826 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1827 1828 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1829 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1830 1831 return 0; 1832 } 1833 1834 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1835 struct ib_udata *udata) 1836 { 1837 struct ib_device *ibdev = uctx->device; 1838 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1839 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1840 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1841 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1842 struct mlx5_bfreg_info *bfregi; 1843 int ver; 1844 int err; 1845 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1846 max_cqe_version); 1847 bool lib_uar_4k; 1848 bool lib_uar_dyn; 1849 1850 if (!dev->ib_active) 1851 return -EAGAIN; 1852 1853 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1854 ver = 0; 1855 else if (udata->inlen >= min_req_v2) 1856 ver = 2; 1857 else 1858 return -EINVAL; 1859 1860 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1861 if (err) 1862 return err; 1863 1864 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1865 return -EOPNOTSUPP; 1866 1867 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1868 return -EOPNOTSUPP; 1869 1870 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1871 MLX5_NON_FP_BFREGS_PER_UAR); 1872 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1873 return -EINVAL; 1874 1875 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1876 err = mlx5_ib_devx_create(dev, true); 1877 if (err < 0) 1878 goto out_ctx; 1879 context->devx_uid = err; 1880 } 1881 1882 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1883 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1884 bfregi = &context->bfregi; 1885 1886 if (lib_uar_dyn) { 1887 bfregi->lib_uar_dyn = lib_uar_dyn; 1888 goto uar_done; 1889 } 1890 1891 /* updates req->total_num_bfregs */ 1892 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1893 if (err) 1894 goto out_devx; 1895 1896 mutex_init(&bfregi->lock); 1897 bfregi->lib_uar_4k = lib_uar_4k; 1898 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1899 GFP_KERNEL); 1900 if (!bfregi->count) { 1901 err = -ENOMEM; 1902 goto out_devx; 1903 } 1904 1905 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1906 sizeof(*bfregi->sys_pages), 1907 GFP_KERNEL); 1908 if (!bfregi->sys_pages) { 1909 err = -ENOMEM; 1910 goto out_count; 1911 } 1912 1913 err = allocate_uars(dev, context); 1914 if (err) 1915 goto out_sys_pages; 1916 1917 uar_done: 1918 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1919 context->devx_uid); 1920 if (err) 1921 goto out_uars; 1922 1923 INIT_LIST_HEAD(&context->db_page_list); 1924 mutex_init(&context->db_page_mutex); 1925 1926 context->cqe_version = min_t(__u8, 1927 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1928 req.max_cqe_version); 1929 1930 err = set_ucontext_resp(uctx, &resp); 1931 if (err) 1932 goto out_mdev; 1933 1934 resp.response_length = min(udata->outlen, sizeof(resp)); 1935 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1936 if (err) 1937 goto out_mdev; 1938 1939 bfregi->ver = ver; 1940 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1941 context->lib_caps = req.lib_caps; 1942 print_lib_caps(dev, context->lib_caps); 1943 1944 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1945 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1946 1947 atomic_set(&context->tx_port_affinity, 1948 atomic_add_return( 1949 1, &dev->port[port].roce.tx_port_affinity)); 1950 } 1951 1952 return 0; 1953 1954 out_mdev: 1955 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1956 1957 out_uars: 1958 deallocate_uars(dev, context); 1959 1960 out_sys_pages: 1961 kfree(bfregi->sys_pages); 1962 1963 out_count: 1964 kfree(bfregi->count); 1965 1966 out_devx: 1967 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1968 mlx5_ib_devx_destroy(dev, context->devx_uid); 1969 1970 out_ctx: 1971 return err; 1972 } 1973 1974 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1975 struct uverbs_attr_bundle *attrs) 1976 { 1977 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1978 int ret; 1979 1980 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1981 if (ret) 1982 return ret; 1983 1984 uctx_resp.response_length = 1985 min_t(size_t, 1986 uverbs_attr_get_len(attrs, 1987 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1988 sizeof(uctx_resp)); 1989 1990 ret = uverbs_copy_to_struct_or_zero(attrs, 1991 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1992 &uctx_resp, 1993 sizeof(uctx_resp)); 1994 return ret; 1995 } 1996 1997 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1998 { 1999 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2000 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2001 struct mlx5_bfreg_info *bfregi; 2002 2003 bfregi = &context->bfregi; 2004 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2005 2006 deallocate_uars(dev, context); 2007 kfree(bfregi->sys_pages); 2008 kfree(bfregi->count); 2009 2010 if (context->devx_uid) 2011 mlx5_ib_devx_destroy(dev, context->devx_uid); 2012 } 2013 2014 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2015 int uar_idx) 2016 { 2017 int fw_uars_per_page; 2018 2019 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2020 2021 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2022 } 2023 2024 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2025 int uar_idx) 2026 { 2027 unsigned int fw_uars_per_page; 2028 2029 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2030 MLX5_UARS_IN_PAGE : 1; 2031 2032 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2033 } 2034 2035 static int get_command(unsigned long offset) 2036 { 2037 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2038 } 2039 2040 static int get_arg(unsigned long offset) 2041 { 2042 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2043 } 2044 2045 static int get_index(unsigned long offset) 2046 { 2047 return get_arg(offset); 2048 } 2049 2050 /* Index resides in an extra byte to enable larger values than 255 */ 2051 static int get_extended_index(unsigned long offset) 2052 { 2053 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2054 } 2055 2056 2057 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2058 { 2059 } 2060 2061 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2062 { 2063 switch (cmd) { 2064 case MLX5_IB_MMAP_WC_PAGE: 2065 return "WC"; 2066 case MLX5_IB_MMAP_REGULAR_PAGE: 2067 return "best effort WC"; 2068 case MLX5_IB_MMAP_NC_PAGE: 2069 return "NC"; 2070 case MLX5_IB_MMAP_DEVICE_MEM: 2071 return "Device Memory"; 2072 default: 2073 return NULL; 2074 } 2075 } 2076 2077 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2078 struct vm_area_struct *vma, 2079 struct mlx5_ib_ucontext *context) 2080 { 2081 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2082 !(vma->vm_flags & VM_SHARED)) 2083 return -EINVAL; 2084 2085 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2086 return -EOPNOTSUPP; 2087 2088 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2089 return -EPERM; 2090 vma->vm_flags &= ~VM_MAYWRITE; 2091 2092 if (!dev->mdev->clock_info) 2093 return -EOPNOTSUPP; 2094 2095 return vm_insert_page(vma, vma->vm_start, 2096 virt_to_page(dev->mdev->clock_info)); 2097 } 2098 2099 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2100 { 2101 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2102 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2103 struct mlx5_var_table *var_table = &dev->var_table; 2104 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2105 2106 switch (mentry->mmap_flag) { 2107 case MLX5_IB_MMAP_TYPE_MEMIC: 2108 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2109 mlx5_ib_dm_mmap_free(dev, mentry); 2110 break; 2111 case MLX5_IB_MMAP_TYPE_VAR: 2112 mutex_lock(&var_table->bitmap_lock); 2113 clear_bit(mentry->page_idx, var_table->bitmap); 2114 mutex_unlock(&var_table->bitmap_lock); 2115 kfree(mentry); 2116 break; 2117 case MLX5_IB_MMAP_TYPE_UAR_WC: 2118 case MLX5_IB_MMAP_TYPE_UAR_NC: 2119 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2120 context->devx_uid); 2121 kfree(mentry); 2122 break; 2123 default: 2124 WARN_ON(true); 2125 } 2126 } 2127 2128 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2129 struct vm_area_struct *vma, 2130 struct mlx5_ib_ucontext *context) 2131 { 2132 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2133 int err; 2134 unsigned long idx; 2135 phys_addr_t pfn; 2136 pgprot_t prot; 2137 u32 bfreg_dyn_idx = 0; 2138 u32 uar_index; 2139 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2140 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2141 bfregi->num_static_sys_pages; 2142 2143 if (bfregi->lib_uar_dyn) 2144 return -EINVAL; 2145 2146 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2147 return -EINVAL; 2148 2149 if (dyn_uar) 2150 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2151 else 2152 idx = get_index(vma->vm_pgoff); 2153 2154 if (idx >= max_valid_idx) { 2155 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2156 idx, max_valid_idx); 2157 return -EINVAL; 2158 } 2159 2160 switch (cmd) { 2161 case MLX5_IB_MMAP_WC_PAGE: 2162 case MLX5_IB_MMAP_ALLOC_WC: 2163 case MLX5_IB_MMAP_REGULAR_PAGE: 2164 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2165 prot = pgprot_writecombine(vma->vm_page_prot); 2166 break; 2167 case MLX5_IB_MMAP_NC_PAGE: 2168 prot = pgprot_noncached(vma->vm_page_prot); 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 if (dyn_uar) { 2175 int uars_per_page; 2176 2177 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2178 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2179 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2180 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2181 bfreg_dyn_idx, bfregi->total_num_bfregs); 2182 return -EINVAL; 2183 } 2184 2185 mutex_lock(&bfregi->lock); 2186 /* Fail if uar already allocated, first bfreg index of each 2187 * page holds its count. 2188 */ 2189 if (bfregi->count[bfreg_dyn_idx]) { 2190 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2191 mutex_unlock(&bfregi->lock); 2192 return -EINVAL; 2193 } 2194 2195 bfregi->count[bfreg_dyn_idx]++; 2196 mutex_unlock(&bfregi->lock); 2197 2198 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2199 context->devx_uid); 2200 if (err) { 2201 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2202 goto free_bfreg; 2203 } 2204 } else { 2205 uar_index = bfregi->sys_pages[idx]; 2206 } 2207 2208 pfn = uar_index2pfn(dev, uar_index); 2209 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2210 2211 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2212 prot, NULL); 2213 if (err) { 2214 mlx5_ib_err(dev, 2215 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2216 err, mmap_cmd2str(cmd)); 2217 goto err; 2218 } 2219 2220 if (dyn_uar) 2221 bfregi->sys_pages[idx] = uar_index; 2222 return 0; 2223 2224 err: 2225 if (!dyn_uar) 2226 return err; 2227 2228 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2229 2230 free_bfreg: 2231 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2232 2233 return err; 2234 } 2235 2236 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2237 { 2238 unsigned long idx; 2239 u8 command; 2240 2241 command = get_command(vma->vm_pgoff); 2242 idx = get_extended_index(vma->vm_pgoff); 2243 2244 return (command << 16 | idx); 2245 } 2246 2247 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2248 struct vm_area_struct *vma, 2249 struct ib_ucontext *ucontext) 2250 { 2251 struct mlx5_user_mmap_entry *mentry; 2252 struct rdma_user_mmap_entry *entry; 2253 unsigned long pgoff; 2254 pgprot_t prot; 2255 phys_addr_t pfn; 2256 int ret; 2257 2258 pgoff = mlx5_vma_to_pgoff(vma); 2259 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2260 if (!entry) 2261 return -EINVAL; 2262 2263 mentry = to_mmmap(entry); 2264 pfn = (mentry->address >> PAGE_SHIFT); 2265 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2266 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2267 prot = pgprot_noncached(vma->vm_page_prot); 2268 else 2269 prot = pgprot_writecombine(vma->vm_page_prot); 2270 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2271 entry->npages * PAGE_SIZE, 2272 prot, 2273 entry); 2274 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2275 return ret; 2276 } 2277 2278 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2279 { 2280 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2281 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2282 2283 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2284 (index & 0xFF)) << PAGE_SHIFT; 2285 } 2286 2287 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2288 { 2289 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2290 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2291 unsigned long command; 2292 phys_addr_t pfn; 2293 2294 command = get_command(vma->vm_pgoff); 2295 switch (command) { 2296 case MLX5_IB_MMAP_WC_PAGE: 2297 case MLX5_IB_MMAP_ALLOC_WC: 2298 if (!dev->wc_support) 2299 return -EPERM; 2300 fallthrough; 2301 case MLX5_IB_MMAP_NC_PAGE: 2302 case MLX5_IB_MMAP_REGULAR_PAGE: 2303 return uar_mmap(dev, command, vma, context); 2304 2305 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2306 return -ENOSYS; 2307 2308 case MLX5_IB_MMAP_CORE_CLOCK: 2309 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2310 return -EINVAL; 2311 2312 if (vma->vm_flags & VM_WRITE) 2313 return -EPERM; 2314 vma->vm_flags &= ~VM_MAYWRITE; 2315 2316 /* Don't expose to user-space information it shouldn't have */ 2317 if (PAGE_SIZE > 4096) 2318 return -EOPNOTSUPP; 2319 2320 pfn = (dev->mdev->iseg_base + 2321 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2322 PAGE_SHIFT; 2323 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2324 PAGE_SIZE, 2325 pgprot_noncached(vma->vm_page_prot), 2326 NULL); 2327 case MLX5_IB_MMAP_CLOCK_INFO: 2328 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2329 2330 default: 2331 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2332 } 2333 2334 return 0; 2335 } 2336 2337 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2338 { 2339 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2340 struct ib_device *ibdev = ibpd->device; 2341 struct mlx5_ib_alloc_pd_resp resp; 2342 int err; 2343 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2344 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2345 u16 uid = 0; 2346 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2347 udata, struct mlx5_ib_ucontext, ibucontext); 2348 2349 uid = context ? context->devx_uid : 0; 2350 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2351 MLX5_SET(alloc_pd_in, in, uid, uid); 2352 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2353 if (err) 2354 return err; 2355 2356 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2357 pd->uid = uid; 2358 if (udata) { 2359 resp.pdn = pd->pdn; 2360 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2361 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2362 return -EFAULT; 2363 } 2364 } 2365 2366 return 0; 2367 } 2368 2369 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2370 { 2371 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2372 struct mlx5_ib_pd *mpd = to_mpd(pd); 2373 2374 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2375 } 2376 2377 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2378 { 2379 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2380 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2381 int err; 2382 u16 uid; 2383 2384 uid = ibqp->pd ? 2385 to_mpd(ibqp->pd)->uid : 0; 2386 2387 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2388 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2389 return -EOPNOTSUPP; 2390 } 2391 2392 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2393 if (err) 2394 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2395 ibqp->qp_num, gid->raw); 2396 2397 return err; 2398 } 2399 2400 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2401 { 2402 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2403 int err; 2404 u16 uid; 2405 2406 uid = ibqp->pd ? 2407 to_mpd(ibqp->pd)->uid : 0; 2408 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2409 if (err) 2410 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2411 ibqp->qp_num, gid->raw); 2412 2413 return err; 2414 } 2415 2416 static int init_node_data(struct mlx5_ib_dev *dev) 2417 { 2418 int err; 2419 2420 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2421 if (err) 2422 return err; 2423 2424 dev->mdev->rev_id = dev->mdev->pdev->revision; 2425 2426 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2427 } 2428 2429 static ssize_t fw_pages_show(struct device *device, 2430 struct device_attribute *attr, char *buf) 2431 { 2432 struct mlx5_ib_dev *dev = 2433 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2434 2435 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2436 } 2437 static DEVICE_ATTR_RO(fw_pages); 2438 2439 static ssize_t reg_pages_show(struct device *device, 2440 struct device_attribute *attr, char *buf) 2441 { 2442 struct mlx5_ib_dev *dev = 2443 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2444 2445 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2446 } 2447 static DEVICE_ATTR_RO(reg_pages); 2448 2449 static ssize_t hca_type_show(struct device *device, 2450 struct device_attribute *attr, char *buf) 2451 { 2452 struct mlx5_ib_dev *dev = 2453 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2454 2455 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2456 } 2457 static DEVICE_ATTR_RO(hca_type); 2458 2459 static ssize_t hw_rev_show(struct device *device, 2460 struct device_attribute *attr, char *buf) 2461 { 2462 struct mlx5_ib_dev *dev = 2463 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2464 2465 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2466 } 2467 static DEVICE_ATTR_RO(hw_rev); 2468 2469 static ssize_t board_id_show(struct device *device, 2470 struct device_attribute *attr, char *buf) 2471 { 2472 struct mlx5_ib_dev *dev = 2473 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2474 2475 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2476 dev->mdev->board_id); 2477 } 2478 static DEVICE_ATTR_RO(board_id); 2479 2480 static struct attribute *mlx5_class_attributes[] = { 2481 &dev_attr_hw_rev.attr, 2482 &dev_attr_hca_type.attr, 2483 &dev_attr_board_id.attr, 2484 &dev_attr_fw_pages.attr, 2485 &dev_attr_reg_pages.attr, 2486 NULL, 2487 }; 2488 2489 static const struct attribute_group mlx5_attr_group = { 2490 .attrs = mlx5_class_attributes, 2491 }; 2492 2493 static void pkey_change_handler(struct work_struct *work) 2494 { 2495 struct mlx5_ib_port_resources *ports = 2496 container_of(work, struct mlx5_ib_port_resources, 2497 pkey_change_work); 2498 2499 if (!ports->gsi) 2500 /* 2501 * We got this event before device was fully configured 2502 * and MAD registration code wasn't called/finished yet. 2503 */ 2504 return; 2505 2506 mlx5_ib_gsi_pkey_change(ports->gsi); 2507 } 2508 2509 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2510 { 2511 struct mlx5_ib_qp *mqp; 2512 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2513 struct mlx5_core_cq *mcq; 2514 struct list_head cq_armed_list; 2515 unsigned long flags_qp; 2516 unsigned long flags_cq; 2517 unsigned long flags; 2518 2519 INIT_LIST_HEAD(&cq_armed_list); 2520 2521 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2522 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2523 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2524 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2525 if (mqp->sq.tail != mqp->sq.head) { 2526 send_mcq = to_mcq(mqp->ibqp.send_cq); 2527 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2528 if (send_mcq->mcq.comp && 2529 mqp->ibqp.send_cq->comp_handler) { 2530 if (!send_mcq->mcq.reset_notify_added) { 2531 send_mcq->mcq.reset_notify_added = 1; 2532 list_add_tail(&send_mcq->mcq.reset_notify, 2533 &cq_armed_list); 2534 } 2535 } 2536 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2537 } 2538 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2539 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2540 /* no handling is needed for SRQ */ 2541 if (!mqp->ibqp.srq) { 2542 if (mqp->rq.tail != mqp->rq.head) { 2543 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2544 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2545 if (recv_mcq->mcq.comp && 2546 mqp->ibqp.recv_cq->comp_handler) { 2547 if (!recv_mcq->mcq.reset_notify_added) { 2548 recv_mcq->mcq.reset_notify_added = 1; 2549 list_add_tail(&recv_mcq->mcq.reset_notify, 2550 &cq_armed_list); 2551 } 2552 } 2553 spin_unlock_irqrestore(&recv_mcq->lock, 2554 flags_cq); 2555 } 2556 } 2557 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2558 } 2559 /*At that point all inflight post send were put to be executed as of we 2560 * lock/unlock above locks Now need to arm all involved CQs. 2561 */ 2562 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2563 mcq->comp(mcq, NULL); 2564 } 2565 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2566 } 2567 2568 static void delay_drop_handler(struct work_struct *work) 2569 { 2570 int err; 2571 struct mlx5_ib_delay_drop *delay_drop = 2572 container_of(work, struct mlx5_ib_delay_drop, 2573 delay_drop_work); 2574 2575 atomic_inc(&delay_drop->events_cnt); 2576 2577 mutex_lock(&delay_drop->lock); 2578 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2579 if (err) { 2580 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2581 delay_drop->timeout); 2582 delay_drop->activate = false; 2583 } 2584 mutex_unlock(&delay_drop->lock); 2585 } 2586 2587 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2588 struct ib_event *ibev) 2589 { 2590 u32 port = (eqe->data.port.port >> 4) & 0xf; 2591 2592 switch (eqe->sub_type) { 2593 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2594 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2595 IB_LINK_LAYER_ETHERNET) 2596 schedule_work(&ibdev->delay_drop.delay_drop_work); 2597 break; 2598 default: /* do nothing */ 2599 return; 2600 } 2601 } 2602 2603 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2604 struct ib_event *ibev) 2605 { 2606 u32 port = (eqe->data.port.port >> 4) & 0xf; 2607 2608 ibev->element.port_num = port; 2609 2610 switch (eqe->sub_type) { 2611 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2612 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2613 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2614 /* In RoCE, port up/down events are handled in 2615 * mlx5_netdev_event(). 2616 */ 2617 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2618 IB_LINK_LAYER_ETHERNET) 2619 return -EINVAL; 2620 2621 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2622 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2623 break; 2624 2625 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2626 ibev->event = IB_EVENT_LID_CHANGE; 2627 break; 2628 2629 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2630 ibev->event = IB_EVENT_PKEY_CHANGE; 2631 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2632 break; 2633 2634 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2635 ibev->event = IB_EVENT_GID_CHANGE; 2636 break; 2637 2638 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2639 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2640 break; 2641 default: 2642 return -EINVAL; 2643 } 2644 2645 return 0; 2646 } 2647 2648 static void mlx5_ib_handle_event(struct work_struct *_work) 2649 { 2650 struct mlx5_ib_event_work *work = 2651 container_of(_work, struct mlx5_ib_event_work, work); 2652 struct mlx5_ib_dev *ibdev; 2653 struct ib_event ibev; 2654 bool fatal = false; 2655 2656 if (work->is_slave) { 2657 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2658 if (!ibdev) 2659 goto out; 2660 } else { 2661 ibdev = work->dev; 2662 } 2663 2664 switch (work->event) { 2665 case MLX5_DEV_EVENT_SYS_ERROR: 2666 ibev.event = IB_EVENT_DEVICE_FATAL; 2667 mlx5_ib_handle_internal_error(ibdev); 2668 ibev.element.port_num = (u8)(unsigned long)work->param; 2669 fatal = true; 2670 break; 2671 case MLX5_EVENT_TYPE_PORT_CHANGE: 2672 if (handle_port_change(ibdev, work->param, &ibev)) 2673 goto out; 2674 break; 2675 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2676 handle_general_event(ibdev, work->param, &ibev); 2677 fallthrough; 2678 default: 2679 goto out; 2680 } 2681 2682 ibev.device = &ibdev->ib_dev; 2683 2684 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2685 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2686 goto out; 2687 } 2688 2689 if (ibdev->ib_active) 2690 ib_dispatch_event(&ibev); 2691 2692 if (fatal) 2693 ibdev->ib_active = false; 2694 out: 2695 kfree(work); 2696 } 2697 2698 static int mlx5_ib_event(struct notifier_block *nb, 2699 unsigned long event, void *param) 2700 { 2701 struct mlx5_ib_event_work *work; 2702 2703 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2704 if (!work) 2705 return NOTIFY_DONE; 2706 2707 INIT_WORK(&work->work, mlx5_ib_handle_event); 2708 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2709 work->is_slave = false; 2710 work->param = param; 2711 work->event = event; 2712 2713 queue_work(mlx5_ib_event_wq, &work->work); 2714 2715 return NOTIFY_OK; 2716 } 2717 2718 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2719 unsigned long event, void *param) 2720 { 2721 struct mlx5_ib_event_work *work; 2722 2723 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2724 if (!work) 2725 return NOTIFY_DONE; 2726 2727 INIT_WORK(&work->work, mlx5_ib_handle_event); 2728 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2729 work->is_slave = true; 2730 work->param = param; 2731 work->event = event; 2732 queue_work(mlx5_ib_event_wq, &work->work); 2733 2734 return NOTIFY_OK; 2735 } 2736 2737 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2738 { 2739 struct mlx5_hca_vport_context vport_ctx; 2740 int err; 2741 int port; 2742 2743 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2744 dev->port_caps[port - 1].has_smi = false; 2745 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2746 MLX5_CAP_PORT_TYPE_IB) { 2747 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2748 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2749 port, 0, 2750 &vport_ctx); 2751 if (err) { 2752 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2753 port, err); 2754 return err; 2755 } 2756 dev->port_caps[port - 1].has_smi = 2757 vport_ctx.has_smi; 2758 } else { 2759 dev->port_caps[port - 1].has_smi = true; 2760 } 2761 } 2762 } 2763 return 0; 2764 } 2765 2766 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2767 { 2768 unsigned int port; 2769 2770 rdma_for_each_port (&dev->ib_dev, port) 2771 mlx5_query_ext_port_caps(dev, port); 2772 } 2773 2774 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2775 { 2776 switch (umr_fence_cap) { 2777 case MLX5_CAP_UMR_FENCE_NONE: 2778 return MLX5_FENCE_MODE_NONE; 2779 case MLX5_CAP_UMR_FENCE_SMALL: 2780 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2781 default: 2782 return MLX5_FENCE_MODE_STRONG_ORDERING; 2783 } 2784 } 2785 2786 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2787 { 2788 struct mlx5_ib_resources *devr = &dev->devr; 2789 struct ib_srq_init_attr attr; 2790 struct ib_device *ibdev; 2791 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2792 int port; 2793 int ret = 0; 2794 2795 ibdev = &dev->ib_dev; 2796 2797 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2798 return -EOPNOTSUPP; 2799 2800 devr->p0 = ib_alloc_pd(ibdev, 0); 2801 if (IS_ERR(devr->p0)) 2802 return PTR_ERR(devr->p0); 2803 2804 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2805 if (IS_ERR(devr->c0)) { 2806 ret = PTR_ERR(devr->c0); 2807 goto error1; 2808 } 2809 2810 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2811 if (ret) 2812 goto error2; 2813 2814 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2815 if (ret) 2816 goto error3; 2817 2818 memset(&attr, 0, sizeof(attr)); 2819 attr.attr.max_sge = 1; 2820 attr.attr.max_wr = 1; 2821 attr.srq_type = IB_SRQT_XRC; 2822 attr.ext.cq = devr->c0; 2823 2824 devr->s0 = ib_create_srq(devr->p0, &attr); 2825 if (IS_ERR(devr->s0)) { 2826 ret = PTR_ERR(devr->s0); 2827 goto err_create; 2828 } 2829 2830 memset(&attr, 0, sizeof(attr)); 2831 attr.attr.max_sge = 1; 2832 attr.attr.max_wr = 1; 2833 attr.srq_type = IB_SRQT_BASIC; 2834 2835 devr->s1 = ib_create_srq(devr->p0, &attr); 2836 if (IS_ERR(devr->s1)) { 2837 ret = PTR_ERR(devr->s1); 2838 goto error6; 2839 } 2840 2841 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2842 INIT_WORK(&devr->ports[port].pkey_change_work, 2843 pkey_change_handler); 2844 2845 return 0; 2846 2847 error6: 2848 ib_destroy_srq(devr->s0); 2849 err_create: 2850 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2851 error3: 2852 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2853 error2: 2854 ib_destroy_cq(devr->c0); 2855 error1: 2856 ib_dealloc_pd(devr->p0); 2857 return ret; 2858 } 2859 2860 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2861 { 2862 struct mlx5_ib_resources *devr = &dev->devr; 2863 int port; 2864 2865 /* 2866 * Make sure no change P_Key work items are still executing. 2867 * 2868 * At this stage, the mlx5_ib_event should be unregistered 2869 * and it ensures that no new works are added. 2870 */ 2871 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2872 cancel_work_sync(&devr->ports[port].pkey_change_work); 2873 2874 ib_destroy_srq(devr->s1); 2875 ib_destroy_srq(devr->s0); 2876 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2877 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2878 ib_destroy_cq(devr->c0); 2879 ib_dealloc_pd(devr->p0); 2880 } 2881 2882 static u32 get_core_cap_flags(struct ib_device *ibdev, 2883 struct mlx5_hca_vport_context *rep) 2884 { 2885 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2886 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2887 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2888 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2889 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2890 u32 ret = 0; 2891 2892 if (rep->grh_required) 2893 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2894 2895 if (ll == IB_LINK_LAYER_INFINIBAND) 2896 return ret | RDMA_CORE_PORT_IBA_IB; 2897 2898 if (raw_support) 2899 ret |= RDMA_CORE_PORT_RAW_PACKET; 2900 2901 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2902 return ret; 2903 2904 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2905 return ret; 2906 2907 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2908 ret |= RDMA_CORE_PORT_IBA_ROCE; 2909 2910 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2911 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2912 2913 return ret; 2914 } 2915 2916 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2917 struct ib_port_immutable *immutable) 2918 { 2919 struct ib_port_attr attr; 2920 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2921 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2922 struct mlx5_hca_vport_context rep = {0}; 2923 int err; 2924 2925 err = ib_query_port(ibdev, port_num, &attr); 2926 if (err) 2927 return err; 2928 2929 if (ll == IB_LINK_LAYER_INFINIBAND) { 2930 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2931 &rep); 2932 if (err) 2933 return err; 2934 } 2935 2936 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2937 immutable->gid_tbl_len = attr.gid_tbl_len; 2938 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2939 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2940 2941 return 0; 2942 } 2943 2944 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2945 struct ib_port_immutable *immutable) 2946 { 2947 struct ib_port_attr attr; 2948 int err; 2949 2950 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2951 2952 err = ib_query_port(ibdev, port_num, &attr); 2953 if (err) 2954 return err; 2955 2956 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2957 immutable->gid_tbl_len = attr.gid_tbl_len; 2958 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2959 2960 return 0; 2961 } 2962 2963 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2964 { 2965 struct mlx5_ib_dev *dev = 2966 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2967 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2968 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2969 fw_rev_sub(dev->mdev)); 2970 } 2971 2972 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2973 { 2974 struct mlx5_core_dev *mdev = dev->mdev; 2975 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2976 MLX5_FLOW_NAMESPACE_LAG); 2977 struct mlx5_flow_table *ft; 2978 int err; 2979 2980 if (!ns || !mlx5_lag_is_active(mdev)) 2981 return 0; 2982 2983 err = mlx5_cmd_create_vport_lag(mdev); 2984 if (err) 2985 return err; 2986 2987 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 2988 if (IS_ERR(ft)) { 2989 err = PTR_ERR(ft); 2990 goto err_destroy_vport_lag; 2991 } 2992 2993 dev->flow_db->lag_demux_ft = ft; 2994 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 2995 dev->lag_active = true; 2996 return 0; 2997 2998 err_destroy_vport_lag: 2999 mlx5_cmd_destroy_vport_lag(mdev); 3000 return err; 3001 } 3002 3003 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3004 { 3005 struct mlx5_core_dev *mdev = dev->mdev; 3006 3007 if (dev->lag_active) { 3008 dev->lag_active = false; 3009 3010 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3011 dev->flow_db->lag_demux_ft = NULL; 3012 3013 mlx5_cmd_destroy_vport_lag(mdev); 3014 } 3015 } 3016 3017 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num) 3018 { 3019 int err; 3020 3021 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3022 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3023 if (err) { 3024 dev->port[port_num].roce.nb.notifier_call = NULL; 3025 return err; 3026 } 3027 3028 return 0; 3029 } 3030 3031 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num) 3032 { 3033 if (dev->port[port_num].roce.nb.notifier_call) { 3034 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3035 dev->port[port_num].roce.nb.notifier_call = NULL; 3036 } 3037 } 3038 3039 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3040 { 3041 int err; 3042 3043 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3044 err = mlx5_nic_vport_enable_roce(dev->mdev); 3045 if (err) 3046 return err; 3047 } 3048 3049 err = mlx5_eth_lag_init(dev); 3050 if (err) 3051 goto err_disable_roce; 3052 3053 return 0; 3054 3055 err_disable_roce: 3056 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3057 mlx5_nic_vport_disable_roce(dev->mdev); 3058 3059 return err; 3060 } 3061 3062 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3063 { 3064 mlx5_eth_lag_cleanup(dev); 3065 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3066 mlx5_nic_vport_disable_roce(dev->mdev); 3067 } 3068 3069 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3070 enum rdma_netdev_t type, 3071 struct rdma_netdev_alloc_params *params) 3072 { 3073 if (type != RDMA_NETDEV_IPOIB) 3074 return -EOPNOTSUPP; 3075 3076 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3077 } 3078 3079 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3080 size_t count, loff_t *pos) 3081 { 3082 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3083 char lbuf[20]; 3084 int len; 3085 3086 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3087 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3088 } 3089 3090 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3091 size_t count, loff_t *pos) 3092 { 3093 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3094 u32 timeout; 3095 u32 var; 3096 3097 if (kstrtouint_from_user(buf, count, 0, &var)) 3098 return -EFAULT; 3099 3100 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3101 1000); 3102 if (timeout != var) 3103 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3104 timeout); 3105 3106 delay_drop->timeout = timeout; 3107 3108 return count; 3109 } 3110 3111 static const struct file_operations fops_delay_drop_timeout = { 3112 .owner = THIS_MODULE, 3113 .open = simple_open, 3114 .write = delay_drop_timeout_write, 3115 .read = delay_drop_timeout_read, 3116 }; 3117 3118 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3119 struct mlx5_ib_multiport_info *mpi) 3120 { 3121 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3122 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3123 int comps; 3124 int err; 3125 int i; 3126 3127 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3128 3129 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3130 3131 spin_lock(&port->mp.mpi_lock); 3132 if (!mpi->ibdev) { 3133 spin_unlock(&port->mp.mpi_lock); 3134 return; 3135 } 3136 3137 mpi->ibdev = NULL; 3138 3139 spin_unlock(&port->mp.mpi_lock); 3140 if (mpi->mdev_events.notifier_call) 3141 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3142 mpi->mdev_events.notifier_call = NULL; 3143 mlx5_remove_netdev_notifier(ibdev, port_num); 3144 spin_lock(&port->mp.mpi_lock); 3145 3146 comps = mpi->mdev_refcnt; 3147 if (comps) { 3148 mpi->unaffiliate = true; 3149 init_completion(&mpi->unref_comp); 3150 spin_unlock(&port->mp.mpi_lock); 3151 3152 for (i = 0; i < comps; i++) 3153 wait_for_completion(&mpi->unref_comp); 3154 3155 spin_lock(&port->mp.mpi_lock); 3156 mpi->unaffiliate = false; 3157 } 3158 3159 port->mp.mpi = NULL; 3160 3161 spin_unlock(&port->mp.mpi_lock); 3162 3163 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3164 3165 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3166 /* Log an error, still needed to cleanup the pointers and add 3167 * it back to the list. 3168 */ 3169 if (err) 3170 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3171 port_num + 1); 3172 3173 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3174 } 3175 3176 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3177 struct mlx5_ib_multiport_info *mpi) 3178 { 3179 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3180 int err; 3181 3182 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3183 3184 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3185 if (ibdev->port[port_num].mp.mpi) { 3186 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3187 port_num + 1); 3188 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3189 return false; 3190 } 3191 3192 ibdev->port[port_num].mp.mpi = mpi; 3193 mpi->ibdev = ibdev; 3194 mpi->mdev_events.notifier_call = NULL; 3195 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3196 3197 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3198 if (err) 3199 goto unbind; 3200 3201 err = mlx5_add_netdev_notifier(ibdev, port_num); 3202 if (err) { 3203 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3204 port_num + 1); 3205 goto unbind; 3206 } 3207 3208 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3209 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3210 3211 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3212 3213 return true; 3214 3215 unbind: 3216 mlx5_ib_unbind_slave_port(ibdev, mpi); 3217 return false; 3218 } 3219 3220 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3221 { 3222 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3223 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3224 port_num + 1); 3225 struct mlx5_ib_multiport_info *mpi; 3226 int err; 3227 u32 i; 3228 3229 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3230 return 0; 3231 3232 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3233 &dev->sys_image_guid); 3234 if (err) 3235 return err; 3236 3237 err = mlx5_nic_vport_enable_roce(dev->mdev); 3238 if (err) 3239 return err; 3240 3241 mutex_lock(&mlx5_ib_multiport_mutex); 3242 for (i = 0; i < dev->num_ports; i++) { 3243 bool bound = false; 3244 3245 /* build a stub multiport info struct for the native port. */ 3246 if (i == port_num) { 3247 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3248 if (!mpi) { 3249 mutex_unlock(&mlx5_ib_multiport_mutex); 3250 mlx5_nic_vport_disable_roce(dev->mdev); 3251 return -ENOMEM; 3252 } 3253 3254 mpi->is_master = true; 3255 mpi->mdev = dev->mdev; 3256 mpi->sys_image_guid = dev->sys_image_guid; 3257 dev->port[i].mp.mpi = mpi; 3258 mpi->ibdev = dev; 3259 mpi = NULL; 3260 continue; 3261 } 3262 3263 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3264 list) { 3265 if (dev->sys_image_guid == mpi->sys_image_guid && 3266 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3267 bound = mlx5_ib_bind_slave_port(dev, mpi); 3268 } 3269 3270 if (bound) { 3271 dev_dbg(mpi->mdev->device, 3272 "removing port from unaffiliated list.\n"); 3273 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3274 list_del(&mpi->list); 3275 break; 3276 } 3277 } 3278 if (!bound) 3279 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3280 i + 1); 3281 } 3282 3283 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3284 mutex_unlock(&mlx5_ib_multiport_mutex); 3285 return err; 3286 } 3287 3288 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3289 { 3290 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3291 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3292 port_num + 1); 3293 u32 i; 3294 3295 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3296 return; 3297 3298 mutex_lock(&mlx5_ib_multiport_mutex); 3299 for (i = 0; i < dev->num_ports; i++) { 3300 if (dev->port[i].mp.mpi) { 3301 /* Destroy the native port stub */ 3302 if (i == port_num) { 3303 kfree(dev->port[i].mp.mpi); 3304 dev->port[i].mp.mpi = NULL; 3305 } else { 3306 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3307 i + 1); 3308 list_add_tail(&dev->port[i].mp.mpi->list, 3309 &mlx5_ib_unaffiliated_port_list); 3310 mlx5_ib_unbind_slave_port(dev, 3311 dev->port[i].mp.mpi); 3312 } 3313 } 3314 } 3315 3316 mlx5_ib_dbg(dev, "removing from devlist\n"); 3317 list_del(&dev->ib_dev_list); 3318 mutex_unlock(&mlx5_ib_multiport_mutex); 3319 3320 mlx5_nic_vport_disable_roce(dev->mdev); 3321 } 3322 3323 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3324 enum rdma_remove_reason why, 3325 struct uverbs_attr_bundle *attrs) 3326 { 3327 struct mlx5_user_mmap_entry *obj = uobject->object; 3328 3329 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3330 return 0; 3331 } 3332 3333 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3334 struct mlx5_user_mmap_entry *entry, 3335 size_t length) 3336 { 3337 return rdma_user_mmap_entry_insert_range( 3338 &c->ibucontext, &entry->rdma_entry, length, 3339 (MLX5_IB_MMAP_OFFSET_START << 16), 3340 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3341 } 3342 3343 static struct mlx5_user_mmap_entry * 3344 alloc_var_entry(struct mlx5_ib_ucontext *c) 3345 { 3346 struct mlx5_user_mmap_entry *entry; 3347 struct mlx5_var_table *var_table; 3348 u32 page_idx; 3349 int err; 3350 3351 var_table = &to_mdev(c->ibucontext.device)->var_table; 3352 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3353 if (!entry) 3354 return ERR_PTR(-ENOMEM); 3355 3356 mutex_lock(&var_table->bitmap_lock); 3357 page_idx = find_first_zero_bit(var_table->bitmap, 3358 var_table->num_var_hw_entries); 3359 if (page_idx >= var_table->num_var_hw_entries) { 3360 err = -ENOSPC; 3361 mutex_unlock(&var_table->bitmap_lock); 3362 goto end; 3363 } 3364 3365 set_bit(page_idx, var_table->bitmap); 3366 mutex_unlock(&var_table->bitmap_lock); 3367 3368 entry->address = var_table->hw_start_addr + 3369 (page_idx * var_table->stride_size); 3370 entry->page_idx = page_idx; 3371 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3372 3373 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3374 var_table->stride_size); 3375 if (err) 3376 goto err_insert; 3377 3378 return entry; 3379 3380 err_insert: 3381 mutex_lock(&var_table->bitmap_lock); 3382 clear_bit(page_idx, var_table->bitmap); 3383 mutex_unlock(&var_table->bitmap_lock); 3384 end: 3385 kfree(entry); 3386 return ERR_PTR(err); 3387 } 3388 3389 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3390 struct uverbs_attr_bundle *attrs) 3391 { 3392 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3393 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3394 struct mlx5_ib_ucontext *c; 3395 struct mlx5_user_mmap_entry *entry; 3396 u64 mmap_offset; 3397 u32 length; 3398 int err; 3399 3400 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3401 if (IS_ERR(c)) 3402 return PTR_ERR(c); 3403 3404 entry = alloc_var_entry(c); 3405 if (IS_ERR(entry)) 3406 return PTR_ERR(entry); 3407 3408 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3409 length = entry->rdma_entry.npages * PAGE_SIZE; 3410 uobj->object = entry; 3411 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3412 3413 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3414 &mmap_offset, sizeof(mmap_offset)); 3415 if (err) 3416 return err; 3417 3418 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3419 &entry->page_idx, sizeof(entry->page_idx)); 3420 if (err) 3421 return err; 3422 3423 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3424 &length, sizeof(length)); 3425 return err; 3426 } 3427 3428 DECLARE_UVERBS_NAMED_METHOD( 3429 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3430 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3431 MLX5_IB_OBJECT_VAR, 3432 UVERBS_ACCESS_NEW, 3433 UA_MANDATORY), 3434 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3435 UVERBS_ATTR_TYPE(u32), 3436 UA_MANDATORY), 3437 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3438 UVERBS_ATTR_TYPE(u32), 3439 UA_MANDATORY), 3440 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3441 UVERBS_ATTR_TYPE(u64), 3442 UA_MANDATORY)); 3443 3444 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3445 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3446 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3447 MLX5_IB_OBJECT_VAR, 3448 UVERBS_ACCESS_DESTROY, 3449 UA_MANDATORY)); 3450 3451 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3452 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3453 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3454 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3455 3456 static bool var_is_supported(struct ib_device *device) 3457 { 3458 struct mlx5_ib_dev *dev = to_mdev(device); 3459 3460 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3461 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3462 } 3463 3464 static struct mlx5_user_mmap_entry * 3465 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3466 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3467 { 3468 struct mlx5_user_mmap_entry *entry; 3469 struct mlx5_ib_dev *dev; 3470 u32 uar_index; 3471 int err; 3472 3473 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3474 if (!entry) 3475 return ERR_PTR(-ENOMEM); 3476 3477 dev = to_mdev(c->ibucontext.device); 3478 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3479 if (err) 3480 goto end; 3481 3482 entry->page_idx = uar_index; 3483 entry->address = uar_index2paddress(dev, uar_index); 3484 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3485 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3486 else 3487 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3488 3489 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3490 if (err) 3491 goto err_insert; 3492 3493 return entry; 3494 3495 err_insert: 3496 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3497 end: 3498 kfree(entry); 3499 return ERR_PTR(err); 3500 } 3501 3502 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3503 struct uverbs_attr_bundle *attrs) 3504 { 3505 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3506 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3507 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3508 struct mlx5_ib_ucontext *c; 3509 struct mlx5_user_mmap_entry *entry; 3510 u64 mmap_offset; 3511 u32 length; 3512 int err; 3513 3514 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3515 if (IS_ERR(c)) 3516 return PTR_ERR(c); 3517 3518 err = uverbs_get_const(&alloc_type, attrs, 3519 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3520 if (err) 3521 return err; 3522 3523 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3524 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3525 return -EOPNOTSUPP; 3526 3527 if (!to_mdev(c->ibucontext.device)->wc_support && 3528 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3529 return -EOPNOTSUPP; 3530 3531 entry = alloc_uar_entry(c, alloc_type); 3532 if (IS_ERR(entry)) 3533 return PTR_ERR(entry); 3534 3535 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3536 length = entry->rdma_entry.npages * PAGE_SIZE; 3537 uobj->object = entry; 3538 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3539 3540 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3541 &mmap_offset, sizeof(mmap_offset)); 3542 if (err) 3543 return err; 3544 3545 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3546 &entry->page_idx, sizeof(entry->page_idx)); 3547 if (err) 3548 return err; 3549 3550 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3551 &length, sizeof(length)); 3552 return err; 3553 } 3554 3555 DECLARE_UVERBS_NAMED_METHOD( 3556 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3557 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3558 MLX5_IB_OBJECT_UAR, 3559 UVERBS_ACCESS_NEW, 3560 UA_MANDATORY), 3561 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3562 enum mlx5_ib_uapi_uar_alloc_type, 3563 UA_MANDATORY), 3564 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3565 UVERBS_ATTR_TYPE(u32), 3566 UA_MANDATORY), 3567 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3568 UVERBS_ATTR_TYPE(u32), 3569 UA_MANDATORY), 3570 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3571 UVERBS_ATTR_TYPE(u64), 3572 UA_MANDATORY)); 3573 3574 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3575 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3576 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3577 MLX5_IB_OBJECT_UAR, 3578 UVERBS_ACCESS_DESTROY, 3579 UA_MANDATORY)); 3580 3581 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3582 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3583 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3584 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3585 3586 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3587 mlx5_ib_query_context, 3588 UVERBS_OBJECT_DEVICE, 3589 UVERBS_METHOD_QUERY_CONTEXT, 3590 UVERBS_ATTR_PTR_OUT( 3591 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3592 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3593 dump_fill_mkey), 3594 UA_MANDATORY)); 3595 3596 static const struct uapi_definition mlx5_ib_defs[] = { 3597 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3598 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3599 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3600 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3601 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3602 3603 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3604 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3605 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3606 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3607 {} 3608 }; 3609 3610 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3611 { 3612 mlx5_ib_cleanup_multiport_master(dev); 3613 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3614 mutex_destroy(&dev->cap_mask_mutex); 3615 WARN_ON(!xa_empty(&dev->sig_mrs)); 3616 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3617 } 3618 3619 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3620 { 3621 struct mlx5_core_dev *mdev = dev->mdev; 3622 int err; 3623 int i; 3624 3625 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3626 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3627 dev->ib_dev.phys_port_cnt = dev->num_ports; 3628 dev->ib_dev.dev.parent = mdev->device; 3629 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3630 3631 for (i = 0; i < dev->num_ports; i++) { 3632 spin_lock_init(&dev->port[i].mp.mpi_lock); 3633 rwlock_init(&dev->port[i].roce.netdev_lock); 3634 dev->port[i].roce.dev = dev; 3635 dev->port[i].roce.native_port_num = i + 1; 3636 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3637 } 3638 3639 err = mlx5_ib_init_multiport_master(dev); 3640 if (err) 3641 return err; 3642 3643 err = set_has_smi_cap(dev); 3644 if (err) 3645 goto err_mp; 3646 3647 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3648 if (err) 3649 goto err_mp; 3650 3651 if (mlx5_use_mad_ifc(dev)) 3652 get_ext_port_caps(dev); 3653 3654 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3655 3656 mutex_init(&dev->cap_mask_mutex); 3657 INIT_LIST_HEAD(&dev->qp_list); 3658 spin_lock_init(&dev->reset_flow_resource_lock); 3659 xa_init(&dev->odp_mkeys); 3660 xa_init(&dev->sig_mrs); 3661 atomic_set(&dev->mkey_var, 0); 3662 3663 spin_lock_init(&dev->dm.lock); 3664 dev->dm.dev = mdev; 3665 return 0; 3666 3667 err_mp: 3668 mlx5_ib_cleanup_multiport_master(dev); 3669 return err; 3670 } 3671 3672 static int mlx5_ib_enable_driver(struct ib_device *dev) 3673 { 3674 struct mlx5_ib_dev *mdev = to_mdev(dev); 3675 int ret; 3676 3677 ret = mlx5_ib_test_wc(mdev); 3678 mlx5_ib_dbg(mdev, "Write-Combining %s", 3679 mdev->wc_support ? "supported" : "not supported"); 3680 3681 return ret; 3682 } 3683 3684 static const struct ib_device_ops mlx5_ib_dev_ops = { 3685 .owner = THIS_MODULE, 3686 .driver_id = RDMA_DRIVER_MLX5, 3687 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3688 3689 .add_gid = mlx5_ib_add_gid, 3690 .alloc_mr = mlx5_ib_alloc_mr, 3691 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3692 .alloc_pd = mlx5_ib_alloc_pd, 3693 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3694 .attach_mcast = mlx5_ib_mcg_attach, 3695 .check_mr_status = mlx5_ib_check_mr_status, 3696 .create_ah = mlx5_ib_create_ah, 3697 .create_cq = mlx5_ib_create_cq, 3698 .create_qp = mlx5_ib_create_qp, 3699 .create_srq = mlx5_ib_create_srq, 3700 .create_user_ah = mlx5_ib_create_ah, 3701 .dealloc_pd = mlx5_ib_dealloc_pd, 3702 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3703 .del_gid = mlx5_ib_del_gid, 3704 .dereg_mr = mlx5_ib_dereg_mr, 3705 .destroy_ah = mlx5_ib_destroy_ah, 3706 .destroy_cq = mlx5_ib_destroy_cq, 3707 .destroy_qp = mlx5_ib_destroy_qp, 3708 .destroy_srq = mlx5_ib_destroy_srq, 3709 .detach_mcast = mlx5_ib_mcg_detach, 3710 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3711 .drain_rq = mlx5_ib_drain_rq, 3712 .drain_sq = mlx5_ib_drain_sq, 3713 .device_group = &mlx5_attr_group, 3714 .enable_driver = mlx5_ib_enable_driver, 3715 .get_dev_fw_str = get_dev_fw_str, 3716 .get_dma_mr = mlx5_ib_get_dma_mr, 3717 .get_link_layer = mlx5_ib_port_link_layer, 3718 .map_mr_sg = mlx5_ib_map_mr_sg, 3719 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3720 .mmap = mlx5_ib_mmap, 3721 .mmap_free = mlx5_ib_mmap_free, 3722 .modify_cq = mlx5_ib_modify_cq, 3723 .modify_device = mlx5_ib_modify_device, 3724 .modify_port = mlx5_ib_modify_port, 3725 .modify_qp = mlx5_ib_modify_qp, 3726 .modify_srq = mlx5_ib_modify_srq, 3727 .poll_cq = mlx5_ib_poll_cq, 3728 .post_recv = mlx5_ib_post_recv_nodrain, 3729 .post_send = mlx5_ib_post_send_nodrain, 3730 .post_srq_recv = mlx5_ib_post_srq_recv, 3731 .process_mad = mlx5_ib_process_mad, 3732 .query_ah = mlx5_ib_query_ah, 3733 .query_device = mlx5_ib_query_device, 3734 .query_gid = mlx5_ib_query_gid, 3735 .query_pkey = mlx5_ib_query_pkey, 3736 .query_qp = mlx5_ib_query_qp, 3737 .query_srq = mlx5_ib_query_srq, 3738 .query_ucontext = mlx5_ib_query_ucontext, 3739 .reg_user_mr = mlx5_ib_reg_user_mr, 3740 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3741 .req_notify_cq = mlx5_ib_arm_cq, 3742 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3743 .resize_cq = mlx5_ib_resize_cq, 3744 3745 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3746 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3747 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3748 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3749 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3750 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3751 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3752 }; 3753 3754 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3755 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3756 }; 3757 3758 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3759 .get_vf_config = mlx5_ib_get_vf_config, 3760 .get_vf_guid = mlx5_ib_get_vf_guid, 3761 .get_vf_stats = mlx5_ib_get_vf_stats, 3762 .set_vf_guid = mlx5_ib_set_vf_guid, 3763 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3764 }; 3765 3766 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3767 .alloc_mw = mlx5_ib_alloc_mw, 3768 .dealloc_mw = mlx5_ib_dealloc_mw, 3769 3770 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3771 }; 3772 3773 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3774 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3775 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3776 3777 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3778 }; 3779 3780 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3781 { 3782 struct mlx5_core_dev *mdev = dev->mdev; 3783 struct mlx5_var_table *var_table = &dev->var_table; 3784 u8 log_doorbell_bar_size; 3785 u8 log_doorbell_stride; 3786 u64 bar_size; 3787 3788 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3789 log_doorbell_bar_size); 3790 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3791 log_doorbell_stride); 3792 var_table->hw_start_addr = dev->mdev->bar_addr + 3793 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3794 doorbell_bar_offset); 3795 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3796 var_table->stride_size = 1ULL << log_doorbell_stride; 3797 var_table->num_var_hw_entries = div_u64(bar_size, 3798 var_table->stride_size); 3799 mutex_init(&var_table->bitmap_lock); 3800 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3801 GFP_KERNEL); 3802 return (var_table->bitmap) ? 0 : -ENOMEM; 3803 } 3804 3805 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3806 { 3807 bitmap_free(dev->var_table.bitmap); 3808 } 3809 3810 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3811 { 3812 struct mlx5_core_dev *mdev = dev->mdev; 3813 int err; 3814 3815 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3816 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3817 ib_set_device_ops(&dev->ib_dev, 3818 &mlx5_ib_dev_ipoib_enhanced_ops); 3819 3820 if (mlx5_core_is_pf(mdev)) 3821 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3822 3823 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3824 3825 if (MLX5_CAP_GEN(mdev, imaicl)) 3826 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3827 3828 if (MLX5_CAP_GEN(mdev, xrc)) 3829 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3830 3831 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3832 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3833 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3834 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3835 3836 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3837 3838 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3839 dev->ib_dev.driver_def = mlx5_ib_defs; 3840 3841 err = init_node_data(dev); 3842 if (err) 3843 return err; 3844 3845 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3846 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3847 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3848 mutex_init(&dev->lb.mutex); 3849 3850 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3851 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3852 err = mlx5_ib_init_var_table(dev); 3853 if (err) 3854 return err; 3855 } 3856 3857 dev->ib_dev.use_cq_dim = true; 3858 3859 return 0; 3860 } 3861 3862 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3863 .get_port_immutable = mlx5_port_immutable, 3864 .query_port = mlx5_ib_query_port, 3865 }; 3866 3867 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3868 { 3869 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3870 return 0; 3871 } 3872 3873 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3874 .get_port_immutable = mlx5_port_rep_immutable, 3875 .query_port = mlx5_ib_rep_query_port, 3876 .query_pkey = mlx5_ib_rep_query_pkey, 3877 }; 3878 3879 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3880 { 3881 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3882 return 0; 3883 } 3884 3885 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3886 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3887 .create_wq = mlx5_ib_create_wq, 3888 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3889 .destroy_wq = mlx5_ib_destroy_wq, 3890 .get_netdev = mlx5_ib_get_netdev, 3891 .modify_wq = mlx5_ib_modify_wq, 3892 3893 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3894 ib_rwq_ind_tbl), 3895 }; 3896 3897 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3898 { 3899 struct mlx5_core_dev *mdev = dev->mdev; 3900 enum rdma_link_layer ll; 3901 int port_type_cap; 3902 u32 port_num = 0; 3903 int err; 3904 3905 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3906 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3907 3908 if (ll == IB_LINK_LAYER_ETHERNET) { 3909 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3910 3911 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3912 3913 /* Register only for native ports */ 3914 err = mlx5_add_netdev_notifier(dev, port_num); 3915 if (err) 3916 return err; 3917 3918 err = mlx5_enable_eth(dev); 3919 if (err) 3920 goto cleanup; 3921 } 3922 3923 return 0; 3924 cleanup: 3925 mlx5_remove_netdev_notifier(dev, port_num); 3926 return err; 3927 } 3928 3929 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3930 { 3931 struct mlx5_core_dev *mdev = dev->mdev; 3932 enum rdma_link_layer ll; 3933 int port_type_cap; 3934 u32 port_num; 3935 3936 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3937 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3938 3939 if (ll == IB_LINK_LAYER_ETHERNET) { 3940 mlx5_disable_eth(dev); 3941 3942 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3943 mlx5_remove_netdev_notifier(dev, port_num); 3944 } 3945 } 3946 3947 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3948 { 3949 mlx5_ib_init_cong_debugfs(dev, 3950 mlx5_core_native_port_num(dev->mdev) - 1); 3951 return 0; 3952 } 3953 3954 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 3955 { 3956 mlx5_ib_cleanup_cong_debugfs(dev, 3957 mlx5_core_native_port_num(dev->mdev) - 1); 3958 } 3959 3960 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 3961 { 3962 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3963 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 3964 } 3965 3966 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 3967 { 3968 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3969 } 3970 3971 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 3972 { 3973 int err; 3974 3975 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3976 if (err) 3977 return err; 3978 3979 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3980 if (err) 3981 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3982 3983 return err; 3984 } 3985 3986 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 3987 { 3988 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3989 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3990 } 3991 3992 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 3993 { 3994 const char *name; 3995 3996 if (!mlx5_lag_is_active(dev->mdev)) 3997 name = "mlx5_%d"; 3998 else 3999 name = "mlx5_bond_%d"; 4000 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4001 } 4002 4003 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4004 { 4005 int err; 4006 4007 err = mlx5_mr_cache_cleanup(dev); 4008 if (err) 4009 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4010 4011 if (dev->umrc.qp) 4012 ib_destroy_qp(dev->umrc.qp); 4013 if (dev->umrc.cq) 4014 ib_free_cq(dev->umrc.cq); 4015 if (dev->umrc.pd) 4016 ib_dealloc_pd(dev->umrc.pd); 4017 } 4018 4019 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4020 { 4021 ib_unregister_device(&dev->ib_dev); 4022 } 4023 4024 enum { 4025 MAX_UMR_WR = 128, 4026 }; 4027 4028 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4029 { 4030 struct ib_qp_init_attr *init_attr = NULL; 4031 struct ib_qp_attr *attr = NULL; 4032 struct ib_pd *pd; 4033 struct ib_cq *cq; 4034 struct ib_qp *qp; 4035 int ret; 4036 4037 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4038 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4039 if (!attr || !init_attr) { 4040 ret = -ENOMEM; 4041 goto error_0; 4042 } 4043 4044 pd = ib_alloc_pd(&dev->ib_dev, 0); 4045 if (IS_ERR(pd)) { 4046 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4047 ret = PTR_ERR(pd); 4048 goto error_0; 4049 } 4050 4051 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4052 if (IS_ERR(cq)) { 4053 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4054 ret = PTR_ERR(cq); 4055 goto error_2; 4056 } 4057 4058 init_attr->send_cq = cq; 4059 init_attr->recv_cq = cq; 4060 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4061 init_attr->cap.max_send_wr = MAX_UMR_WR; 4062 init_attr->cap.max_send_sge = 1; 4063 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4064 init_attr->port_num = 1; 4065 qp = ib_create_qp(pd, init_attr); 4066 if (IS_ERR(qp)) { 4067 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4068 ret = PTR_ERR(qp); 4069 goto error_3; 4070 } 4071 4072 attr->qp_state = IB_QPS_INIT; 4073 attr->port_num = 1; 4074 ret = ib_modify_qp(qp, attr, 4075 IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT); 4076 if (ret) { 4077 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4078 goto error_4; 4079 } 4080 4081 memset(attr, 0, sizeof(*attr)); 4082 attr->qp_state = IB_QPS_RTR; 4083 attr->path_mtu = IB_MTU_256; 4084 4085 ret = ib_modify_qp(qp, attr, IB_QP_STATE); 4086 if (ret) { 4087 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4088 goto error_4; 4089 } 4090 4091 memset(attr, 0, sizeof(*attr)); 4092 attr->qp_state = IB_QPS_RTS; 4093 ret = ib_modify_qp(qp, attr, IB_QP_STATE); 4094 if (ret) { 4095 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4096 goto error_4; 4097 } 4098 4099 dev->umrc.qp = qp; 4100 dev->umrc.cq = cq; 4101 dev->umrc.pd = pd; 4102 4103 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4104 ret = mlx5_mr_cache_init(dev); 4105 if (ret) { 4106 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4107 goto error_4; 4108 } 4109 4110 kfree(attr); 4111 kfree(init_attr); 4112 4113 return 0; 4114 4115 error_4: 4116 ib_destroy_qp(qp); 4117 dev->umrc.qp = NULL; 4118 4119 error_3: 4120 ib_free_cq(cq); 4121 dev->umrc.cq = NULL; 4122 4123 error_2: 4124 ib_dealloc_pd(pd); 4125 dev->umrc.pd = NULL; 4126 4127 error_0: 4128 kfree(attr); 4129 kfree(init_attr); 4130 return ret; 4131 } 4132 4133 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4134 { 4135 struct dentry *root; 4136 4137 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4138 return 0; 4139 4140 mutex_init(&dev->delay_drop.lock); 4141 dev->delay_drop.dev = dev; 4142 dev->delay_drop.activate = false; 4143 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4144 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4145 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4146 atomic_set(&dev->delay_drop.events_cnt, 0); 4147 4148 if (!mlx5_debugfs_root) 4149 return 0; 4150 4151 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4152 dev->delay_drop.dir_debugfs = root; 4153 4154 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4155 &dev->delay_drop.events_cnt); 4156 debugfs_create_atomic_t("num_rqs", 0400, root, 4157 &dev->delay_drop.rqs_cnt); 4158 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4159 &fops_delay_drop_timeout); 4160 return 0; 4161 } 4162 4163 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4164 { 4165 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4166 return; 4167 4168 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4169 if (!dev->delay_drop.dir_debugfs) 4170 return; 4171 4172 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4173 dev->delay_drop.dir_debugfs = NULL; 4174 } 4175 4176 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4177 { 4178 dev->mdev_events.notifier_call = mlx5_ib_event; 4179 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4180 return 0; 4181 } 4182 4183 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4184 { 4185 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4186 } 4187 4188 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4189 const struct mlx5_ib_profile *profile, 4190 int stage) 4191 { 4192 dev->ib_active = false; 4193 4194 /* Number of stages to cleanup */ 4195 while (stage) { 4196 stage--; 4197 if (profile->stage[stage].cleanup) 4198 profile->stage[stage].cleanup(dev); 4199 } 4200 4201 kfree(dev->port); 4202 ib_dealloc_device(&dev->ib_dev); 4203 } 4204 4205 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4206 const struct mlx5_ib_profile *profile) 4207 { 4208 int err; 4209 int i; 4210 4211 dev->profile = profile; 4212 4213 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4214 if (profile->stage[i].init) { 4215 err = profile->stage[i].init(dev); 4216 if (err) 4217 goto err_out; 4218 } 4219 } 4220 4221 dev->ib_active = true; 4222 return 0; 4223 4224 err_out: 4225 /* Clean up stages which were initialized */ 4226 while (i) { 4227 i--; 4228 if (profile->stage[i].cleanup) 4229 profile->stage[i].cleanup(dev); 4230 } 4231 return -ENOMEM; 4232 } 4233 4234 static const struct mlx5_ib_profile pf_profile = { 4235 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4236 mlx5_ib_stage_init_init, 4237 mlx5_ib_stage_init_cleanup), 4238 STAGE_CREATE(MLX5_IB_STAGE_FS, 4239 mlx5_ib_fs_init, 4240 mlx5_ib_fs_cleanup), 4241 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4242 mlx5_ib_stage_caps_init, 4243 mlx5_ib_stage_caps_cleanup), 4244 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4245 mlx5_ib_stage_non_default_cb, 4246 NULL), 4247 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4248 mlx5_ib_roce_init, 4249 mlx5_ib_roce_cleanup), 4250 STAGE_CREATE(MLX5_IB_STAGE_QP, 4251 mlx5_init_qp_table, 4252 mlx5_cleanup_qp_table), 4253 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4254 mlx5_init_srq_table, 4255 mlx5_cleanup_srq_table), 4256 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4257 mlx5_ib_dev_res_init, 4258 mlx5_ib_dev_res_cleanup), 4259 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4260 mlx5_ib_stage_dev_notifier_init, 4261 mlx5_ib_stage_dev_notifier_cleanup), 4262 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4263 mlx5_ib_odp_init_one, 4264 mlx5_ib_odp_cleanup_one), 4265 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4266 mlx5_ib_counters_init, 4267 mlx5_ib_counters_cleanup), 4268 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4269 mlx5_ib_stage_cong_debugfs_init, 4270 mlx5_ib_stage_cong_debugfs_cleanup), 4271 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4272 mlx5_ib_stage_uar_init, 4273 mlx5_ib_stage_uar_cleanup), 4274 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4275 mlx5_ib_stage_bfrag_init, 4276 mlx5_ib_stage_bfrag_cleanup), 4277 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4278 NULL, 4279 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4280 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4281 mlx5_ib_devx_init, 4282 mlx5_ib_devx_cleanup), 4283 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4284 mlx5_ib_stage_ib_reg_init, 4285 mlx5_ib_stage_ib_reg_cleanup), 4286 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4287 mlx5_ib_stage_post_ib_reg_umr_init, 4288 NULL), 4289 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4290 mlx5_ib_stage_delay_drop_init, 4291 mlx5_ib_stage_delay_drop_cleanup), 4292 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4293 mlx5_ib_restrack_init, 4294 NULL), 4295 }; 4296 4297 const struct mlx5_ib_profile raw_eth_profile = { 4298 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4299 mlx5_ib_stage_init_init, 4300 mlx5_ib_stage_init_cleanup), 4301 STAGE_CREATE(MLX5_IB_STAGE_FS, 4302 mlx5_ib_fs_init, 4303 mlx5_ib_fs_cleanup), 4304 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4305 mlx5_ib_stage_caps_init, 4306 mlx5_ib_stage_caps_cleanup), 4307 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4308 mlx5_ib_stage_raw_eth_non_default_cb, 4309 NULL), 4310 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4311 mlx5_ib_roce_init, 4312 mlx5_ib_roce_cleanup), 4313 STAGE_CREATE(MLX5_IB_STAGE_QP, 4314 mlx5_init_qp_table, 4315 mlx5_cleanup_qp_table), 4316 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4317 mlx5_init_srq_table, 4318 mlx5_cleanup_srq_table), 4319 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4320 mlx5_ib_dev_res_init, 4321 mlx5_ib_dev_res_cleanup), 4322 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4323 mlx5_ib_stage_dev_notifier_init, 4324 mlx5_ib_stage_dev_notifier_cleanup), 4325 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4326 mlx5_ib_counters_init, 4327 mlx5_ib_counters_cleanup), 4328 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4329 mlx5_ib_stage_cong_debugfs_init, 4330 mlx5_ib_stage_cong_debugfs_cleanup), 4331 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4332 mlx5_ib_stage_uar_init, 4333 mlx5_ib_stage_uar_cleanup), 4334 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4335 mlx5_ib_stage_bfrag_init, 4336 mlx5_ib_stage_bfrag_cleanup), 4337 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4338 NULL, 4339 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4340 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4341 mlx5_ib_devx_init, 4342 mlx5_ib_devx_cleanup), 4343 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4344 mlx5_ib_stage_ib_reg_init, 4345 mlx5_ib_stage_ib_reg_cleanup), 4346 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4347 mlx5_ib_stage_post_ib_reg_umr_init, 4348 NULL), 4349 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4350 mlx5_ib_restrack_init, 4351 NULL), 4352 }; 4353 4354 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4355 const struct auxiliary_device_id *id) 4356 { 4357 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4358 struct mlx5_core_dev *mdev = idev->mdev; 4359 struct mlx5_ib_multiport_info *mpi; 4360 struct mlx5_ib_dev *dev; 4361 bool bound = false; 4362 int err; 4363 4364 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4365 if (!mpi) 4366 return -ENOMEM; 4367 4368 mpi->mdev = mdev; 4369 err = mlx5_query_nic_vport_system_image_guid(mdev, 4370 &mpi->sys_image_guid); 4371 if (err) { 4372 kfree(mpi); 4373 return err; 4374 } 4375 4376 mutex_lock(&mlx5_ib_multiport_mutex); 4377 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4378 if (dev->sys_image_guid == mpi->sys_image_guid) 4379 bound = mlx5_ib_bind_slave_port(dev, mpi); 4380 4381 if (bound) { 4382 rdma_roce_rescan_device(&dev->ib_dev); 4383 mpi->ibdev->ib_active = true; 4384 break; 4385 } 4386 } 4387 4388 if (!bound) { 4389 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4390 dev_dbg(mdev->device, 4391 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4392 } 4393 mutex_unlock(&mlx5_ib_multiport_mutex); 4394 4395 auxiliary_set_drvdata(adev, mpi); 4396 return 0; 4397 } 4398 4399 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4400 { 4401 struct mlx5_ib_multiport_info *mpi; 4402 4403 mpi = auxiliary_get_drvdata(adev); 4404 mutex_lock(&mlx5_ib_multiport_mutex); 4405 if (mpi->ibdev) 4406 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4407 else 4408 list_del(&mpi->list); 4409 mutex_unlock(&mlx5_ib_multiport_mutex); 4410 kfree(mpi); 4411 } 4412 4413 static int mlx5r_probe(struct auxiliary_device *adev, 4414 const struct auxiliary_device_id *id) 4415 { 4416 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4417 struct mlx5_core_dev *mdev = idev->mdev; 4418 const struct mlx5_ib_profile *profile; 4419 int port_type_cap, num_ports, ret; 4420 enum rdma_link_layer ll; 4421 struct mlx5_ib_dev *dev; 4422 4423 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4424 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4425 4426 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4427 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4428 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4429 if (!dev) 4430 return -ENOMEM; 4431 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4432 GFP_KERNEL); 4433 if (!dev->port) { 4434 ib_dealloc_device(&dev->ib_dev); 4435 return -ENOMEM; 4436 } 4437 4438 dev->mdev = mdev; 4439 dev->num_ports = num_ports; 4440 4441 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev)) 4442 profile = &raw_eth_profile; 4443 else 4444 profile = &pf_profile; 4445 4446 ret = __mlx5_ib_add(dev, profile); 4447 if (ret) { 4448 kfree(dev->port); 4449 ib_dealloc_device(&dev->ib_dev); 4450 return ret; 4451 } 4452 4453 auxiliary_set_drvdata(adev, dev); 4454 return 0; 4455 } 4456 4457 static void mlx5r_remove(struct auxiliary_device *adev) 4458 { 4459 struct mlx5_ib_dev *dev; 4460 4461 dev = auxiliary_get_drvdata(adev); 4462 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4463 } 4464 4465 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4466 { .name = MLX5_ADEV_NAME ".multiport", }, 4467 {}, 4468 }; 4469 4470 static const struct auxiliary_device_id mlx5r_id_table[] = { 4471 { .name = MLX5_ADEV_NAME ".rdma", }, 4472 {}, 4473 }; 4474 4475 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4476 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4477 4478 static struct auxiliary_driver mlx5r_mp_driver = { 4479 .name = "multiport", 4480 .probe = mlx5r_mp_probe, 4481 .remove = mlx5r_mp_remove, 4482 .id_table = mlx5r_mp_id_table, 4483 }; 4484 4485 static struct auxiliary_driver mlx5r_driver = { 4486 .name = "rdma", 4487 .probe = mlx5r_probe, 4488 .remove = mlx5r_remove, 4489 .id_table = mlx5r_id_table, 4490 }; 4491 4492 static int __init mlx5_ib_init(void) 4493 { 4494 int ret; 4495 4496 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4497 if (!xlt_emergency_page) 4498 return -ENOMEM; 4499 4500 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4501 if (!mlx5_ib_event_wq) { 4502 free_page((unsigned long)xlt_emergency_page); 4503 return -ENOMEM; 4504 } 4505 4506 mlx5_ib_odp_init(); 4507 ret = mlx5r_rep_init(); 4508 if (ret) 4509 goto rep_err; 4510 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4511 if (ret) 4512 goto mp_err; 4513 ret = auxiliary_driver_register(&mlx5r_driver); 4514 if (ret) 4515 goto drv_err; 4516 return 0; 4517 4518 drv_err: 4519 auxiliary_driver_unregister(&mlx5r_mp_driver); 4520 mp_err: 4521 mlx5r_rep_cleanup(); 4522 rep_err: 4523 destroy_workqueue(mlx5_ib_event_wq); 4524 free_page((unsigned long)xlt_emergency_page); 4525 return ret; 4526 } 4527 4528 static void __exit mlx5_ib_cleanup(void) 4529 { 4530 auxiliary_driver_unregister(&mlx5r_driver); 4531 auxiliary_driver_unregister(&mlx5r_mp_driver); 4532 mlx5r_rep_cleanup(); 4533 4534 destroy_workqueue(mlx5_ib_event_wq); 4535 free_page((unsigned long)xlt_emergency_page); 4536 } 4537 4538 module_init(mlx5_ib_init); 4539 module_exit(mlx5_ib_cleanup); 4540