1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/driver.h> 29 #include <linux/list.h> 30 #include <rdma/ib_smi.h> 31 #include <rdma/ib_umem_odp.h> 32 #include <rdma/lag.h> 33 #include <linux/in.h> 34 #include <linux/etherdevice.h> 35 #include "mlx5_ib.h" 36 #include "ib_rep.h" 37 #include "cmd.h" 38 #include "devx.h" 39 #include "dm.h" 40 #include "fs.h" 41 #include "srq.h" 42 #include "qp.h" 43 #include "wr.h" 44 #include "restrack.h" 45 #include "counters.h" 46 #include "umr.h" 47 #include <rdma/uverbs_std_types.h> 48 #include <rdma/uverbs_ioctl.h> 49 #include <rdma/mlx5_user_ioctl_verbs.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/ib_ucaps.h> 52 #include "macsec.h" 53 #include "data_direct.h" 54 #include "dmah.h" 55 56 #define UVERBS_MODULE_NAME mlx5_ib 57 #include <rdma/uverbs_named_ioctl.h> 58 59 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 60 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 61 MODULE_LICENSE("Dual BSD/GPL"); 62 63 struct mlx5_ib_event_work { 64 struct work_struct work; 65 union { 66 struct mlx5_ib_dev *dev; 67 struct mlx5_ib_multiport_info *mpi; 68 }; 69 bool is_slave; 70 unsigned int event; 71 void *param; 72 }; 73 74 enum { 75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 76 }; 77 78 static struct workqueue_struct *mlx5_ib_event_wq; 79 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 80 static LIST_HEAD(mlx5_ib_dev_list); 81 /* 82 * This mutex should be held when accessing either of the above lists 83 */ 84 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 85 86 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 87 { 88 struct mlx5_ib_dev *dev; 89 90 mutex_lock(&mlx5_ib_multiport_mutex); 91 dev = mpi->ibdev; 92 mutex_unlock(&mlx5_ib_multiport_mutex); 93 return dev; 94 } 95 96 static enum rdma_link_layer 97 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 98 { 99 switch (port_type_cap) { 100 case MLX5_CAP_PORT_TYPE_IB: 101 return IB_LINK_LAYER_INFINIBAND; 102 case MLX5_CAP_PORT_TYPE_ETH: 103 return IB_LINK_LAYER_ETHERNET; 104 default: 105 return IB_LINK_LAYER_UNSPECIFIED; 106 } 107 } 108 109 static enum rdma_link_layer 110 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 111 { 112 struct mlx5_ib_dev *dev = to_mdev(device); 113 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 114 115 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 116 } 117 118 static int get_port_state(struct ib_device *ibdev, 119 u32 port_num, 120 enum ib_port_state *state) 121 { 122 struct ib_port_attr attr; 123 int ret; 124 125 memset(&attr, 0, sizeof(attr)); 126 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 127 if (!ret) 128 *state = attr.state; 129 return ret; 130 } 131 132 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 133 struct net_device *ndev, 134 struct net_device *upper, 135 u32 *port_num) 136 { 137 struct net_device *rep_ndev; 138 struct mlx5_ib_port *port; 139 int i; 140 141 for (i = 0; i < dev->num_ports; i++) { 142 port = &dev->port[i]; 143 if (!port->rep) 144 continue; 145 146 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 147 *port_num = i + 1; 148 return &port->roce; 149 } 150 151 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 152 continue; 153 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 154 if (rep_ndev && rep_ndev == ndev) { 155 dev_put(rep_ndev); 156 *port_num = i + 1; 157 return &port->roce; 158 } 159 160 dev_put(rep_ndev); 161 } 162 163 return NULL; 164 } 165 166 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 167 struct net_device *ndev, 168 struct net_device *upper, 169 struct net_device *ib_ndev) 170 { 171 if (!dev->ib_active) 172 return false; 173 174 /* Event is about our upper device */ 175 if (upper == ndev) 176 return true; 177 178 /* RDMA device is not in lag and not in switchdev */ 179 if (!dev->is_rep && !upper && ndev == ib_ndev) 180 return true; 181 182 /* RDMA devie is in switchdev */ 183 if (dev->is_rep && ndev == ib_ndev) 184 return true; 185 186 return false; 187 } 188 189 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 190 { 191 struct mlx5_ib_port *port; 192 int i; 193 194 for (i = 0; i < ibdev->num_ports; i++) { 195 port = &ibdev->port[i]; 196 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 197 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 198 } 199 } 200 201 return NULL; 202 } 203 204 static int mlx5_netdev_event(struct notifier_block *this, 205 unsigned long event, void *ptr) 206 { 207 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 208 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 209 u32 port_num = roce->native_port_num; 210 struct net_device *ib_ndev = NULL; 211 struct mlx5_core_dev *mdev; 212 struct mlx5_ib_dev *ibdev; 213 214 ibdev = roce->dev; 215 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 216 if (!mdev) 217 return NOTIFY_DONE; 218 219 switch (event) { 220 case NETDEV_REGISTER: 221 /* Should already be registered during the load */ 222 if (ibdev->is_rep) 223 break; 224 225 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 226 /* Exit if already registered */ 227 if (ib_ndev) 228 goto put_ndev; 229 230 if (ndev->dev.parent == mdev->device) 231 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 232 break; 233 234 case NETDEV_UNREGISTER: 235 /* In case of reps, ib device goes away before the netdevs */ 236 if (ibdev->is_rep) 237 break; 238 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 239 if (ib_ndev == ndev) 240 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 241 goto put_ndev; 242 243 case NETDEV_CHANGE: 244 case NETDEV_UP: 245 case NETDEV_DOWN: { 246 struct net_device *upper = NULL; 247 248 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 249 !mlx5_core_mp_enabled(mdev)) 250 return NOTIFY_DONE; 251 252 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 253 struct net_device *lag_ndev; 254 255 if(mlx5_lag_is_roce(mdev)) 256 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 257 else /* sriov lag */ 258 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 259 260 if (lag_ndev) { 261 upper = netdev_master_upper_dev_get(lag_ndev); 262 dev_put(lag_ndev); 263 } else { 264 goto done; 265 } 266 } 267 268 if (ibdev->is_rep) 269 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 270 if (!roce) 271 return NOTIFY_DONE; 272 273 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 274 275 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 276 struct ib_event ibev = { }; 277 enum ib_port_state port_state; 278 279 if (get_port_state(&ibdev->ib_dev, port_num, 280 &port_state)) 281 goto put_ndev; 282 283 if (roce->last_port_state == port_state) 284 goto put_ndev; 285 286 roce->last_port_state = port_state; 287 ibev.device = &ibdev->ib_dev; 288 if (port_state == IB_PORT_DOWN) 289 ibev.event = IB_EVENT_PORT_ERR; 290 else if (port_state == IB_PORT_ACTIVE) 291 ibev.event = IB_EVENT_PORT_ACTIVE; 292 else 293 goto put_ndev; 294 295 ibev.element.port_num = port_num; 296 ib_dispatch_event(&ibev); 297 } 298 break; 299 } 300 301 default: 302 break; 303 } 304 put_ndev: 305 dev_put(ib_ndev); 306 done: 307 mlx5_ib_put_native_port_mdev(ibdev, port_num); 308 return NOTIFY_DONE; 309 } 310 311 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 312 u32 ib_port_num, 313 u32 *native_port_num) 314 { 315 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 316 ib_port_num); 317 struct mlx5_core_dev *mdev = NULL; 318 struct mlx5_ib_multiport_info *mpi; 319 struct mlx5_ib_port *port; 320 321 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 322 if (native_port_num) 323 *native_port_num = smi_to_native_portnum(ibdev, 324 ib_port_num); 325 return ibdev->mdev; 326 327 } 328 329 if (!mlx5_core_mp_enabled(ibdev->mdev) || 330 ll != IB_LINK_LAYER_ETHERNET) { 331 if (native_port_num) 332 *native_port_num = ib_port_num; 333 return ibdev->mdev; 334 } 335 336 if (native_port_num) 337 *native_port_num = 1; 338 339 port = &ibdev->port[ib_port_num - 1]; 340 spin_lock(&port->mp.mpi_lock); 341 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 342 if (mpi && !mpi->unaffiliate) { 343 mdev = mpi->mdev; 344 /* If it's the master no need to refcount, it'll exist 345 * as long as the ib_dev exists. 346 */ 347 if (!mpi->is_master) 348 mpi->mdev_refcnt++; 349 } 350 spin_unlock(&port->mp.mpi_lock); 351 352 return mdev; 353 } 354 355 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 356 { 357 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 358 port_num); 359 struct mlx5_ib_multiport_info *mpi; 360 struct mlx5_ib_port *port; 361 362 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 363 return; 364 365 port = &ibdev->port[port_num - 1]; 366 367 spin_lock(&port->mp.mpi_lock); 368 mpi = ibdev->port[port_num - 1].mp.mpi; 369 if (mpi->is_master) 370 goto out; 371 372 mpi->mdev_refcnt--; 373 if (mpi->unaffiliate) 374 complete(&mpi->unref_comp); 375 out: 376 spin_unlock(&port->mp.mpi_lock); 377 } 378 379 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 380 u16 *active_speed, u8 *active_width) 381 { 382 switch (eth_proto_oper) { 383 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 385 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 386 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 387 *active_width = IB_WIDTH_1X; 388 *active_speed = IB_SPEED_SDR; 389 break; 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 397 *active_width = IB_WIDTH_1X; 398 *active_speed = IB_SPEED_QDR; 399 break; 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_EDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 416 *active_width = IB_WIDTH_1X; 417 *active_speed = IB_SPEED_HDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 420 *active_width = IB_WIDTH_4X; 421 *active_speed = IB_SPEED_FDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 438 u8 *active_width) 439 { 440 switch (eth_proto_oper) { 441 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 442 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 443 *active_width = IB_WIDTH_1X; 444 *active_speed = IB_SPEED_SDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 447 *active_width = IB_WIDTH_1X; 448 *active_speed = IB_SPEED_DDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 451 *active_width = IB_WIDTH_1X; 452 *active_speed = IB_SPEED_QDR; 453 break; 454 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 455 *active_width = IB_WIDTH_4X; 456 *active_speed = IB_SPEED_QDR; 457 break; 458 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 459 *active_width = IB_WIDTH_1X; 460 *active_speed = IB_SPEED_EDR; 461 break; 462 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 463 *active_width = IB_WIDTH_2X; 464 *active_speed = IB_SPEED_EDR; 465 break; 466 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 467 *active_width = IB_WIDTH_1X; 468 *active_speed = IB_SPEED_HDR; 469 break; 470 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 471 *active_width = IB_WIDTH_4X; 472 *active_speed = IB_SPEED_EDR; 473 break; 474 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 475 *active_width = IB_WIDTH_2X; 476 *active_speed = IB_SPEED_HDR; 477 break; 478 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 479 *active_width = IB_WIDTH_1X; 480 *active_speed = IB_SPEED_NDR; 481 break; 482 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 483 *active_width = IB_WIDTH_4X; 484 *active_speed = IB_SPEED_HDR; 485 break; 486 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 487 *active_width = IB_WIDTH_2X; 488 *active_speed = IB_SPEED_NDR; 489 break; 490 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 491 *active_width = IB_WIDTH_1X; 492 *active_speed = IB_SPEED_XDR; 493 break; 494 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 495 *active_width = IB_WIDTH_8X; 496 *active_speed = IB_SPEED_HDR; 497 break; 498 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 499 *active_width = IB_WIDTH_4X; 500 *active_speed = IB_SPEED_NDR; 501 break; 502 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 503 *active_width = IB_WIDTH_2X; 504 *active_speed = IB_SPEED_XDR; 505 break; 506 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 507 *active_width = IB_WIDTH_8X; 508 *active_speed = IB_SPEED_NDR; 509 break; 510 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 511 *active_width = IB_WIDTH_4X; 512 *active_speed = IB_SPEED_XDR; 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 return 0; 519 } 520 521 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 522 u8 *active_width, bool ext) 523 { 524 return ext ? 525 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 526 active_width) : 527 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 528 active_width); 529 } 530 531 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 532 struct ib_port_attr *props) 533 { 534 struct mlx5_ib_dev *dev = to_mdev(device); 535 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 536 struct mlx5_core_dev *mdev; 537 struct net_device *ndev, *upper; 538 enum ib_mtu ndev_ib_mtu; 539 bool put_mdev = true; 540 u32 eth_prot_oper; 541 u32 mdev_port_num; 542 bool ext; 543 int err; 544 545 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 546 if (!mdev) { 547 /* This means the port isn't affiliated yet. Get the 548 * info for the master port instead. 549 */ 550 put_mdev = false; 551 mdev = dev->mdev; 552 mdev_port_num = 1; 553 port_num = 1; 554 } 555 556 /* Possible bad flows are checked before filling out props so in case 557 * of an error it will still be zeroed out. 558 * Use native port in case of reps 559 */ 560 if (dev->is_rep) 561 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 562 1, 0); 563 else 564 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 565 mdev_port_num, 0); 566 if (err) 567 goto out; 568 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 569 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 570 571 props->active_width = IB_WIDTH_4X; 572 props->active_speed = IB_SPEED_QDR; 573 574 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 575 &props->active_width, ext); 576 577 if (!dev->is_rep && dev->mdev->roce.roce_en) { 578 u16 qkey_viol_cntr; 579 580 props->port_cap_flags |= IB_PORT_CM_SUP; 581 props->ip_gids = true; 582 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 583 roce_address_table_size); 584 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 585 props->qkey_viol_cntr = qkey_viol_cntr; 586 } 587 props->max_mtu = IB_MTU_4096; 588 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 589 props->pkey_tbl_len = 1; 590 props->state = IB_PORT_DOWN; 591 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 592 593 /* If this is a stub query for an unaffiliated port stop here */ 594 if (!put_mdev) 595 goto out; 596 597 ndev = ib_device_get_netdev(device, port_num); 598 if (!ndev) 599 goto out; 600 601 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 602 rcu_read_lock(); 603 upper = netdev_master_upper_dev_get_rcu(ndev); 604 if (upper) { 605 dev_put(ndev); 606 ndev = upper; 607 dev_hold(ndev); 608 } 609 rcu_read_unlock(); 610 } 611 612 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 613 props->state = IB_PORT_ACTIVE; 614 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 615 } 616 617 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 618 619 dev_put(ndev); 620 621 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 622 out: 623 if (put_mdev) 624 mlx5_ib_put_native_port_mdev(dev, port_num); 625 return err; 626 } 627 628 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 629 unsigned int index, const union ib_gid *gid, 630 const struct ib_gid_attr *attr) 631 { 632 enum ib_gid_type gid_type; 633 u16 vlan_id = 0xffff; 634 u8 roce_version = 0; 635 u8 roce_l3_type = 0; 636 u8 mac[ETH_ALEN]; 637 int ret; 638 639 gid_type = attr->gid_type; 640 if (gid) { 641 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 642 if (ret) 643 return ret; 644 } 645 646 switch (gid_type) { 647 case IB_GID_TYPE_ROCE: 648 roce_version = MLX5_ROCE_VERSION_1; 649 break; 650 case IB_GID_TYPE_ROCE_UDP_ENCAP: 651 roce_version = MLX5_ROCE_VERSION_2; 652 if (gid && ipv6_addr_v4mapped((void *)gid)) 653 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 654 else 655 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 656 break; 657 658 default: 659 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 660 } 661 662 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 663 roce_l3_type, gid->raw, mac, 664 vlan_id < VLAN_CFI_MASK, vlan_id, 665 port_num); 666 } 667 668 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 669 __always_unused void **context) 670 { 671 int ret; 672 673 ret = mlx5r_add_gid_macsec_operations(attr); 674 if (ret) 675 return ret; 676 677 return set_roce_addr(to_mdev(attr->device), attr->port_num, 678 attr->index, &attr->gid, attr); 679 } 680 681 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 682 __always_unused void **context) 683 { 684 int ret; 685 686 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 687 attr->index, NULL, attr); 688 if (ret) 689 return ret; 690 691 mlx5r_del_gid_macsec_operations(attr); 692 return 0; 693 } 694 695 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 696 const struct ib_gid_attr *attr) 697 { 698 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 699 return 0; 700 701 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 702 } 703 704 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 705 { 706 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 707 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 708 return 0; 709 } 710 711 enum { 712 MLX5_VPORT_ACCESS_METHOD_MAD, 713 MLX5_VPORT_ACCESS_METHOD_HCA, 714 MLX5_VPORT_ACCESS_METHOD_NIC, 715 }; 716 717 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 718 { 719 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 720 return MLX5_VPORT_ACCESS_METHOD_MAD; 721 722 if (mlx5_ib_port_link_layer(ibdev, 1) == 723 IB_LINK_LAYER_ETHERNET) 724 return MLX5_VPORT_ACCESS_METHOD_NIC; 725 726 return MLX5_VPORT_ACCESS_METHOD_HCA; 727 } 728 729 static void get_atomic_caps(struct mlx5_ib_dev *dev, 730 u8 atomic_size_qp, 731 struct ib_device_attr *props) 732 { 733 u8 tmp; 734 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 735 u8 atomic_req_8B_endianness_mode = 736 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 737 738 /* Check if HW supports 8 bytes standard atomic operations and capable 739 * of host endianness respond 740 */ 741 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 742 if (((atomic_operations & tmp) == tmp) && 743 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 744 (atomic_req_8B_endianness_mode)) { 745 props->atomic_cap = IB_ATOMIC_HCA; 746 } else { 747 props->atomic_cap = IB_ATOMIC_NONE; 748 } 749 } 750 751 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 752 struct ib_device_attr *props) 753 { 754 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 755 756 get_atomic_caps(dev, atomic_size_qp, props); 757 } 758 759 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 760 __be64 *sys_image_guid) 761 { 762 struct mlx5_ib_dev *dev = to_mdev(ibdev); 763 struct mlx5_core_dev *mdev = dev->mdev; 764 u64 tmp; 765 int err; 766 767 switch (mlx5_get_vport_access_method(ibdev)) { 768 case MLX5_VPORT_ACCESS_METHOD_MAD: 769 return mlx5_query_mad_ifc_system_image_guid(ibdev, 770 sys_image_guid); 771 772 case MLX5_VPORT_ACCESS_METHOD_HCA: 773 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 774 break; 775 776 case MLX5_VPORT_ACCESS_METHOD_NIC: 777 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 778 break; 779 780 default: 781 return -EINVAL; 782 } 783 784 if (!err) 785 *sys_image_guid = cpu_to_be64(tmp); 786 787 return err; 788 789 } 790 791 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 792 u16 *max_pkeys) 793 { 794 struct mlx5_ib_dev *dev = to_mdev(ibdev); 795 struct mlx5_core_dev *mdev = dev->mdev; 796 797 switch (mlx5_get_vport_access_method(ibdev)) { 798 case MLX5_VPORT_ACCESS_METHOD_MAD: 799 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 800 801 case MLX5_VPORT_ACCESS_METHOD_HCA: 802 case MLX5_VPORT_ACCESS_METHOD_NIC: 803 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 804 pkey_table_size)); 805 return 0; 806 807 default: 808 return -EINVAL; 809 } 810 } 811 812 static int mlx5_query_vendor_id(struct ib_device *ibdev, 813 u32 *vendor_id) 814 { 815 struct mlx5_ib_dev *dev = to_mdev(ibdev); 816 817 switch (mlx5_get_vport_access_method(ibdev)) { 818 case MLX5_VPORT_ACCESS_METHOD_MAD: 819 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 820 821 case MLX5_VPORT_ACCESS_METHOD_HCA: 822 case MLX5_VPORT_ACCESS_METHOD_NIC: 823 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 824 825 default: 826 return -EINVAL; 827 } 828 } 829 830 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 831 __be64 *node_guid) 832 { 833 u64 tmp; 834 int err; 835 836 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 837 case MLX5_VPORT_ACCESS_METHOD_MAD: 838 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 839 840 case MLX5_VPORT_ACCESS_METHOD_HCA: 841 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 842 break; 843 844 case MLX5_VPORT_ACCESS_METHOD_NIC: 845 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 846 break; 847 848 default: 849 return -EINVAL; 850 } 851 852 if (!err) 853 *node_guid = cpu_to_be64(tmp); 854 855 return err; 856 } 857 858 struct mlx5_reg_node_desc { 859 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 860 }; 861 862 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 863 { 864 struct mlx5_reg_node_desc in; 865 866 if (mlx5_use_mad_ifc(dev)) 867 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 868 869 memset(&in, 0, sizeof(in)); 870 871 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 872 sizeof(struct mlx5_reg_node_desc), 873 MLX5_REG_NODE_DESC, 0, 0); 874 } 875 876 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 877 struct mlx5_ib_query_device_resp *resp) 878 { 879 struct mlx5_eswitch *esw = mdev->priv.eswitch; 880 u16 vport = mlx5_eswitch_manager_vport(mdev); 881 882 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 883 vport); 884 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 885 } 886 887 /* 888 * Calculate maximum SQ overhead across all QP types. 889 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 890 * have smaller overhead than the types calculated below, 891 * so they are implicitly included. 892 */ 893 static u32 mlx5_ib_calc_max_sq_overhead(void) 894 { 895 u32 max_overhead_xrc, overhead_ud_lso, a, b; 896 897 /* XRC_INI */ 898 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 899 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 900 a = sizeof(struct mlx5_wqe_atomic_seg) + 901 sizeof(struct mlx5_wqe_raddr_seg); 902 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 903 sizeof(struct mlx5_mkey_seg) + 904 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 905 max_overhead_xrc += max(a, b); 906 907 /* UD with LSO */ 908 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 909 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 910 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 911 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 912 913 return max(max_overhead_xrc, overhead_ud_lso); 914 } 915 916 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 917 { 918 struct mlx5_core_dev *mdev = dev->mdev; 919 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 920 u32 max_wqe_size; 921 /* max QP overhead + 1 SGE, no inline, no special features */ 922 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 923 sizeof(struct mlx5_wqe_data_seg); 924 925 max_wqe_size = roundup_pow_of_two(max_wqe_size); 926 927 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 928 929 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 930 } 931 932 static int mlx5_ib_query_device(struct ib_device *ibdev, 933 struct ib_device_attr *props, 934 struct ib_udata *uhw) 935 { 936 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 937 struct mlx5_ib_dev *dev = to_mdev(ibdev); 938 struct mlx5_core_dev *mdev = dev->mdev; 939 int err = -ENOMEM; 940 int max_sq_desc; 941 int max_rq_sg; 942 int max_sq_sg; 943 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 944 bool raw_support = !mlx5_core_mp_enabled(mdev); 945 struct mlx5_ib_query_device_resp resp = {}; 946 size_t resp_len; 947 u64 max_tso; 948 949 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 950 if (uhw_outlen && uhw_outlen < resp_len) 951 return -EINVAL; 952 953 resp.response_length = resp_len; 954 955 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 956 return -EINVAL; 957 958 memset(props, 0, sizeof(*props)); 959 err = mlx5_query_system_image_guid(ibdev, 960 &props->sys_image_guid); 961 if (err) 962 return err; 963 964 props->max_pkeys = dev->pkey_table_len; 965 966 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 967 if (err) 968 return err; 969 970 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 971 (fw_rev_min(dev->mdev) << 16) | 972 fw_rev_sub(dev->mdev); 973 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 974 IB_DEVICE_PORT_ACTIVE_EVENT | 975 IB_DEVICE_SYS_IMAGE_GUID | 976 IB_DEVICE_RC_RNR_NAK_GEN; 977 978 if (MLX5_CAP_GEN(mdev, pkv)) 979 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 980 if (MLX5_CAP_GEN(mdev, qkv)) 981 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 982 if (MLX5_CAP_GEN(mdev, apm)) 983 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 984 if (MLX5_CAP_GEN(mdev, xrc)) 985 props->device_cap_flags |= IB_DEVICE_XRC; 986 if (MLX5_CAP_GEN(mdev, imaicl)) { 987 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 988 IB_DEVICE_MEM_WINDOW_TYPE_2B; 989 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 990 /* We support 'Gappy' memory registration too */ 991 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 992 } 993 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 994 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 995 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 996 if (MLX5_CAP_GEN(mdev, sho)) { 997 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 998 /* At this stage no support for signature handover */ 999 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1000 IB_PROT_T10DIF_TYPE_2 | 1001 IB_PROT_T10DIF_TYPE_3; 1002 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1003 IB_GUARD_T10DIF_CSUM; 1004 } 1005 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1006 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1007 1008 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1009 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1010 /* Legacy bit to support old userspace libraries */ 1011 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1012 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1013 } 1014 1015 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1016 props->raw_packet_caps |= 1017 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1018 1019 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1020 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1021 if (max_tso) { 1022 resp.tso_caps.max_tso = 1 << max_tso; 1023 resp.tso_caps.supported_qpts |= 1024 1 << IB_QPT_RAW_PACKET; 1025 resp.response_length += sizeof(resp.tso_caps); 1026 } 1027 } 1028 1029 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1030 resp.rss_caps.rx_hash_function = 1031 MLX5_RX_HASH_FUNC_TOEPLITZ; 1032 resp.rss_caps.rx_hash_fields_mask = 1033 MLX5_RX_HASH_SRC_IPV4 | 1034 MLX5_RX_HASH_DST_IPV4 | 1035 MLX5_RX_HASH_SRC_IPV6 | 1036 MLX5_RX_HASH_DST_IPV6 | 1037 MLX5_RX_HASH_SRC_PORT_TCP | 1038 MLX5_RX_HASH_DST_PORT_TCP | 1039 MLX5_RX_HASH_SRC_PORT_UDP | 1040 MLX5_RX_HASH_DST_PORT_UDP | 1041 MLX5_RX_HASH_INNER; 1042 resp.response_length += sizeof(resp.rss_caps); 1043 } 1044 } else { 1045 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1046 resp.response_length += sizeof(resp.tso_caps); 1047 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1048 resp.response_length += sizeof(resp.rss_caps); 1049 } 1050 1051 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1052 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1053 props->kernel_cap_flags |= IBK_UD_TSO; 1054 } 1055 1056 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1057 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1058 raw_support) 1059 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1060 1061 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1062 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1063 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1064 1065 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1066 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1067 raw_support) { 1068 /* Legacy bit to support old userspace libraries */ 1069 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1070 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1071 } 1072 1073 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1074 props->max_dm_size = 1075 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1076 } 1077 1078 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1079 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1080 1081 if (MLX5_CAP_GEN(mdev, end_pad)) 1082 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1083 1084 props->vendor_part_id = mdev->pdev->device; 1085 props->hw_ver = mdev->pdev->revision; 1086 1087 props->max_mr_size = ~0ull; 1088 props->page_size_cap = ~(min_page_size - 1); 1089 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1090 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1091 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1092 sizeof(struct mlx5_wqe_data_seg); 1093 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1094 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1095 sizeof(struct mlx5_wqe_raddr_seg)) / 1096 sizeof(struct mlx5_wqe_data_seg); 1097 props->max_send_sge = max_sq_sg; 1098 props->max_recv_sge = max_rq_sg; 1099 props->max_sge_rd = MLX5_MAX_SGE_RD; 1100 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1101 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1102 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1103 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1104 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1105 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1106 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1107 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1108 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1109 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1110 props->max_srq_sge = max_rq_sg - 1; 1111 props->max_fast_reg_page_list_len = 1112 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1113 props->max_pi_fast_reg_page_list_len = 1114 props->max_fast_reg_page_list_len / 2; 1115 props->max_sgl_rd = 1116 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1117 get_atomic_caps_qp(dev, props); 1118 props->masked_atomic_cap = IB_ATOMIC_NONE; 1119 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1120 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1121 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1122 props->max_mcast_grp; 1123 props->max_ah = INT_MAX; 1124 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1125 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1126 1127 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1128 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1129 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1130 props->odp_caps = dev->odp_caps; 1131 if (!uhw) { 1132 /* ODP for kernel QPs is not implemented for receive 1133 * WQEs and SRQ WQEs 1134 */ 1135 props->odp_caps.per_transport_caps.rc_odp_caps &= 1136 ~(IB_ODP_SUPPORT_READ | 1137 IB_ODP_SUPPORT_SRQ_RECV); 1138 props->odp_caps.per_transport_caps.uc_odp_caps &= 1139 ~(IB_ODP_SUPPORT_READ | 1140 IB_ODP_SUPPORT_SRQ_RECV); 1141 props->odp_caps.per_transport_caps.ud_odp_caps &= 1142 ~(IB_ODP_SUPPORT_READ | 1143 IB_ODP_SUPPORT_SRQ_RECV); 1144 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1145 ~(IB_ODP_SUPPORT_READ | 1146 IB_ODP_SUPPORT_SRQ_RECV); 1147 } 1148 } 1149 1150 if (mlx5_core_is_vf(mdev)) 1151 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1152 1153 if (mlx5_ib_port_link_layer(ibdev, 1) == 1154 IB_LINK_LAYER_ETHERNET && raw_support) { 1155 props->rss_caps.max_rwq_indirection_tables = 1156 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1157 props->rss_caps.max_rwq_indirection_table_size = 1158 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1159 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1160 props->max_wq_type_rq = 1161 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1162 } 1163 1164 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1165 props->tm_caps.max_num_tags = 1166 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1167 props->tm_caps.max_ops = 1168 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1169 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1170 } 1171 1172 if (MLX5_CAP_GEN(mdev, tag_matching) && 1173 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1174 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1175 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1176 } 1177 1178 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1179 props->cq_caps.max_cq_moderation_count = 1180 MLX5_MAX_CQ_COUNT; 1181 props->cq_caps.max_cq_moderation_period = 1182 MLX5_MAX_CQ_PERIOD; 1183 } 1184 1185 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1186 resp.response_length += sizeof(resp.cqe_comp_caps); 1187 1188 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1189 resp.cqe_comp_caps.max_num = 1190 MLX5_CAP_GEN(dev->mdev, 1191 cqe_compression_max_num); 1192 1193 resp.cqe_comp_caps.supported_format = 1194 MLX5_IB_CQE_RES_FORMAT_HASH | 1195 MLX5_IB_CQE_RES_FORMAT_CSUM; 1196 1197 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1198 resp.cqe_comp_caps.supported_format |= 1199 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1200 } 1201 } 1202 1203 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1204 raw_support) { 1205 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1206 MLX5_CAP_GEN(mdev, qos)) { 1207 resp.packet_pacing_caps.qp_rate_limit_max = 1208 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1209 resp.packet_pacing_caps.qp_rate_limit_min = 1210 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1211 resp.packet_pacing_caps.supported_qpts |= 1212 1 << IB_QPT_RAW_PACKET; 1213 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1214 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1215 resp.packet_pacing_caps.cap_flags |= 1216 MLX5_IB_PP_SUPPORT_BURST; 1217 } 1218 resp.response_length += sizeof(resp.packet_pacing_caps); 1219 } 1220 1221 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1222 uhw_outlen) { 1223 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1224 resp.mlx5_ib_support_multi_pkt_send_wqes = 1225 MLX5_IB_ALLOW_MPW; 1226 1227 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1228 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1229 MLX5_IB_SUPPORT_EMPW; 1230 1231 resp.response_length += 1232 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1233 } 1234 1235 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1236 resp.response_length += sizeof(resp.flags); 1237 1238 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1239 resp.flags |= 1240 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1241 1242 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1243 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1244 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1245 resp.flags |= 1246 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1247 1248 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1249 1250 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1251 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1252 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1253 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1254 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1255 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1256 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1257 } 1258 1259 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1260 resp.response_length += sizeof(resp.sw_parsing_caps); 1261 if (MLX5_CAP_ETH(mdev, swp)) { 1262 resp.sw_parsing_caps.sw_parsing_offloads |= 1263 MLX5_IB_SW_PARSING; 1264 1265 if (MLX5_CAP_ETH(mdev, swp_csum)) 1266 resp.sw_parsing_caps.sw_parsing_offloads |= 1267 MLX5_IB_SW_PARSING_CSUM; 1268 1269 if (MLX5_CAP_ETH(mdev, swp_lso)) 1270 resp.sw_parsing_caps.sw_parsing_offloads |= 1271 MLX5_IB_SW_PARSING_LSO; 1272 1273 if (resp.sw_parsing_caps.sw_parsing_offloads) 1274 resp.sw_parsing_caps.supported_qpts = 1275 BIT(IB_QPT_RAW_PACKET); 1276 } 1277 } 1278 1279 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1280 raw_support) { 1281 resp.response_length += sizeof(resp.striding_rq_caps); 1282 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1283 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1284 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1285 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1286 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1287 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1288 resp.striding_rq_caps 1289 .min_single_wqe_log_num_of_strides = 1290 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1291 else 1292 resp.striding_rq_caps 1293 .min_single_wqe_log_num_of_strides = 1294 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1295 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1296 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1297 resp.striding_rq_caps.supported_qpts = 1298 BIT(IB_QPT_RAW_PACKET); 1299 } 1300 } 1301 1302 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1303 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1304 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1305 resp.tunnel_offloads_caps |= 1306 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1307 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1308 resp.tunnel_offloads_caps |= 1309 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1310 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1311 resp.tunnel_offloads_caps |= 1312 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1313 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1314 resp.tunnel_offloads_caps |= 1315 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1316 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1317 resp.tunnel_offloads_caps |= 1318 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1319 } 1320 1321 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1322 resp.response_length += sizeof(resp.dci_streams_caps); 1323 1324 resp.dci_streams_caps.max_log_num_concurent = 1325 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1326 1327 resp.dci_streams_caps.max_log_num_errored = 1328 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1329 } 1330 1331 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1332 resp.response_length += sizeof(resp.reserved); 1333 1334 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1335 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1336 1337 resp.response_length += sizeof(resp.reg_c0); 1338 1339 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1340 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1341 fill_esw_mgr_reg_c0(mdev, &resp); 1342 } 1343 1344 if (uhw_outlen) { 1345 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1346 1347 if (err) 1348 return err; 1349 } 1350 1351 return 0; 1352 } 1353 1354 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1355 u8 *ib_width) 1356 { 1357 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1358 1359 if (active_width & MLX5_PTYS_WIDTH_1X) 1360 *ib_width = IB_WIDTH_1X; 1361 else if (active_width & MLX5_PTYS_WIDTH_2X) 1362 *ib_width = IB_WIDTH_2X; 1363 else if (active_width & MLX5_PTYS_WIDTH_4X) 1364 *ib_width = IB_WIDTH_4X; 1365 else if (active_width & MLX5_PTYS_WIDTH_8X) 1366 *ib_width = IB_WIDTH_8X; 1367 else if (active_width & MLX5_PTYS_WIDTH_12X) 1368 *ib_width = IB_WIDTH_12X; 1369 else { 1370 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1371 active_width); 1372 *ib_width = IB_WIDTH_4X; 1373 } 1374 1375 return; 1376 } 1377 1378 static int mlx5_mtu_to_ib_mtu(int mtu) 1379 { 1380 switch (mtu) { 1381 case 256: return 1; 1382 case 512: return 2; 1383 case 1024: return 3; 1384 case 2048: return 4; 1385 case 4096: return 5; 1386 default: 1387 pr_warn("invalid mtu\n"); 1388 return -1; 1389 } 1390 } 1391 1392 enum ib_max_vl_num { 1393 __IB_MAX_VL_0 = 1, 1394 __IB_MAX_VL_0_1 = 2, 1395 __IB_MAX_VL_0_3 = 3, 1396 __IB_MAX_VL_0_7 = 4, 1397 __IB_MAX_VL_0_14 = 5, 1398 }; 1399 1400 enum mlx5_vl_hw_cap { 1401 MLX5_VL_HW_0 = 1, 1402 MLX5_VL_HW_0_1 = 2, 1403 MLX5_VL_HW_0_2 = 3, 1404 MLX5_VL_HW_0_3 = 4, 1405 MLX5_VL_HW_0_4 = 5, 1406 MLX5_VL_HW_0_5 = 6, 1407 MLX5_VL_HW_0_6 = 7, 1408 MLX5_VL_HW_0_7 = 8, 1409 MLX5_VL_HW_0_14 = 15 1410 }; 1411 1412 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1413 u8 *max_vl_num) 1414 { 1415 switch (vl_hw_cap) { 1416 case MLX5_VL_HW_0: 1417 *max_vl_num = __IB_MAX_VL_0; 1418 break; 1419 case MLX5_VL_HW_0_1: 1420 *max_vl_num = __IB_MAX_VL_0_1; 1421 break; 1422 case MLX5_VL_HW_0_3: 1423 *max_vl_num = __IB_MAX_VL_0_3; 1424 break; 1425 case MLX5_VL_HW_0_7: 1426 *max_vl_num = __IB_MAX_VL_0_7; 1427 break; 1428 case MLX5_VL_HW_0_14: 1429 *max_vl_num = __IB_MAX_VL_0_14; 1430 break; 1431 1432 default: 1433 return -EINVAL; 1434 } 1435 1436 return 0; 1437 } 1438 1439 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1440 struct ib_port_attr *props) 1441 { 1442 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1443 struct mlx5_core_dev *mdev = dev->mdev; 1444 struct mlx5_hca_vport_context *rep; 1445 u8 vl_hw_cap, plane_index = 0; 1446 u16 max_mtu; 1447 u16 oper_mtu; 1448 int err; 1449 u16 ib_link_width_oper; 1450 1451 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1452 if (!rep) { 1453 err = -ENOMEM; 1454 goto out; 1455 } 1456 1457 /* props being zeroed by the caller, avoid zeroing it here */ 1458 1459 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1460 plane_index = port; 1461 port = smi_to_native_portnum(dev, port); 1462 } 1463 1464 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1465 if (err) 1466 goto out; 1467 1468 props->lid = rep->lid; 1469 props->lmc = rep->lmc; 1470 props->sm_lid = rep->sm_lid; 1471 props->sm_sl = rep->sm_sl; 1472 props->state = rep->vport_state; 1473 props->phys_state = rep->port_physical_state; 1474 1475 props->port_cap_flags = rep->cap_mask1; 1476 if (dev->num_plane) { 1477 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1478 props->port_cap_flags &= ~IB_PORT_SM; 1479 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1480 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1481 1482 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1483 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1484 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1485 props->bad_pkey_cntr = rep->pkey_violation_counter; 1486 props->qkey_viol_cntr = rep->qkey_violation_counter; 1487 props->subnet_timeout = rep->subnet_timeout; 1488 props->init_type_reply = rep->init_type_reply; 1489 1490 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1491 props->port_cap_flags2 = rep->cap_mask2; 1492 1493 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1494 &props->active_speed, port, plane_index); 1495 if (err) 1496 goto out; 1497 1498 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1499 1500 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1501 1502 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1503 1504 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1505 1506 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1507 1508 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1509 if (err) 1510 goto out; 1511 1512 err = translate_max_vl_num(ibdev, vl_hw_cap, 1513 &props->max_vl_num); 1514 out: 1515 kfree(rep); 1516 return err; 1517 } 1518 1519 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1520 struct ib_port_attr *props) 1521 { 1522 unsigned int count; 1523 int ret; 1524 1525 switch (mlx5_get_vport_access_method(ibdev)) { 1526 case MLX5_VPORT_ACCESS_METHOD_MAD: 1527 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1528 break; 1529 1530 case MLX5_VPORT_ACCESS_METHOD_HCA: 1531 ret = mlx5_query_hca_port(ibdev, port, props); 1532 break; 1533 1534 case MLX5_VPORT_ACCESS_METHOD_NIC: 1535 ret = mlx5_query_port_roce(ibdev, port, props); 1536 break; 1537 1538 default: 1539 ret = -EINVAL; 1540 } 1541 1542 if (!ret && props) { 1543 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1544 struct mlx5_core_dev *mdev; 1545 bool put_mdev = true; 1546 1547 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1548 if (!mdev) { 1549 /* If the port isn't affiliated yet query the master. 1550 * The master and slave will have the same values. 1551 */ 1552 mdev = dev->mdev; 1553 port = 1; 1554 put_mdev = false; 1555 } 1556 count = mlx5_core_reserved_gids_count(mdev); 1557 if (put_mdev) 1558 mlx5_ib_put_native_port_mdev(dev, port); 1559 props->gid_tbl_len -= count; 1560 } 1561 return ret; 1562 } 1563 1564 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1565 struct ib_port_attr *props) 1566 { 1567 return mlx5_query_port_roce(ibdev, port, props); 1568 } 1569 1570 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1571 u16 *pkey) 1572 { 1573 /* Default special Pkey for representor device port as per the 1574 * IB specification 1.3 section 10.9.1.2. 1575 */ 1576 *pkey = 0xffff; 1577 return 0; 1578 } 1579 1580 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1581 union ib_gid *gid) 1582 { 1583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1584 struct mlx5_core_dev *mdev = dev->mdev; 1585 1586 switch (mlx5_get_vport_access_method(ibdev)) { 1587 case MLX5_VPORT_ACCESS_METHOD_MAD: 1588 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1589 1590 case MLX5_VPORT_ACCESS_METHOD_HCA: 1591 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1592 1593 default: 1594 return -EINVAL; 1595 } 1596 1597 } 1598 1599 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1600 u16 index, u16 *pkey) 1601 { 1602 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1603 struct mlx5_core_dev *mdev; 1604 bool put_mdev = true; 1605 u32 mdev_port_num; 1606 int err; 1607 1608 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1609 if (!mdev) { 1610 /* The port isn't affiliated yet, get the PKey from the master 1611 * port. For RoCE the PKey tables will be the same. 1612 */ 1613 put_mdev = false; 1614 mdev = dev->mdev; 1615 mdev_port_num = 1; 1616 } 1617 1618 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1619 index, pkey); 1620 if (put_mdev) 1621 mlx5_ib_put_native_port_mdev(dev, port); 1622 1623 return err; 1624 } 1625 1626 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1627 u16 *pkey) 1628 { 1629 switch (mlx5_get_vport_access_method(ibdev)) { 1630 case MLX5_VPORT_ACCESS_METHOD_MAD: 1631 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1632 1633 case MLX5_VPORT_ACCESS_METHOD_HCA: 1634 case MLX5_VPORT_ACCESS_METHOD_NIC: 1635 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1636 default: 1637 return -EINVAL; 1638 } 1639 } 1640 1641 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1642 struct ib_device_modify *props) 1643 { 1644 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1645 struct mlx5_reg_node_desc in; 1646 struct mlx5_reg_node_desc out; 1647 int err; 1648 1649 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1650 return -EOPNOTSUPP; 1651 1652 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1653 return 0; 1654 1655 /* 1656 * If possible, pass node desc to FW, so it can generate 1657 * a 144 trap. If cmd fails, just ignore. 1658 */ 1659 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1660 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1661 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1662 if (err) 1663 return err; 1664 1665 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1666 1667 return err; 1668 } 1669 1670 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1671 u32 value) 1672 { 1673 struct mlx5_hca_vport_context ctx = {}; 1674 struct mlx5_core_dev *mdev; 1675 u32 mdev_port_num; 1676 int err; 1677 1678 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1679 if (!mdev) 1680 return -ENODEV; 1681 1682 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1683 if (err) 1684 goto out; 1685 1686 if (~ctx.cap_mask1_perm & mask) { 1687 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1688 mask, ctx.cap_mask1_perm); 1689 err = -EINVAL; 1690 goto out; 1691 } 1692 1693 ctx.cap_mask1 = value; 1694 ctx.cap_mask1_perm = mask; 1695 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1696 0, &ctx); 1697 1698 out: 1699 mlx5_ib_put_native_port_mdev(dev, port_num); 1700 1701 return err; 1702 } 1703 1704 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1705 struct ib_port_modify *props) 1706 { 1707 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1708 struct ib_port_attr attr; 1709 u32 tmp; 1710 int err; 1711 u32 change_mask; 1712 u32 value; 1713 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1714 IB_LINK_LAYER_INFINIBAND); 1715 1716 /* CM layer calls ib_modify_port() regardless of the link layer. For 1717 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1718 */ 1719 if (!is_ib) 1720 return 0; 1721 1722 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1723 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1724 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1725 return set_port_caps_atomic(dev, port, change_mask, value); 1726 } 1727 1728 mutex_lock(&dev->cap_mask_mutex); 1729 1730 err = ib_query_port(ibdev, port, &attr); 1731 if (err) 1732 goto out; 1733 1734 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1735 ~props->clr_port_cap_mask; 1736 1737 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1738 1739 out: 1740 mutex_unlock(&dev->cap_mask_mutex); 1741 return err; 1742 } 1743 1744 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1745 { 1746 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1747 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1748 } 1749 1750 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1751 { 1752 /* Large page with non 4k uar support might limit the dynamic size */ 1753 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1754 return MLX5_MIN_DYN_BFREGS; 1755 1756 return MLX5_MAX_DYN_BFREGS; 1757 } 1758 1759 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1760 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1761 struct mlx5_bfreg_info *bfregi) 1762 { 1763 int uars_per_sys_page; 1764 int bfregs_per_sys_page; 1765 int ref_bfregs = req->total_num_bfregs; 1766 1767 if (req->total_num_bfregs == 0) 1768 return -EINVAL; 1769 1770 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1771 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1772 1773 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1774 return -ENOMEM; 1775 1776 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1777 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1778 /* This holds the required static allocation asked by the user */ 1779 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1780 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1781 return -EINVAL; 1782 1783 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1784 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1785 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1786 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1787 1788 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1789 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1790 lib_uar_4k ? "yes" : "no", ref_bfregs, 1791 req->total_num_bfregs, bfregi->total_num_bfregs, 1792 bfregi->num_sys_pages); 1793 1794 return 0; 1795 } 1796 1797 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1798 { 1799 struct mlx5_bfreg_info *bfregi; 1800 int err; 1801 int i; 1802 1803 bfregi = &context->bfregi; 1804 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1805 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1806 context->devx_uid); 1807 if (err) 1808 goto error; 1809 1810 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1811 } 1812 1813 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1814 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1815 1816 return 0; 1817 1818 error: 1819 for (--i; i >= 0; i--) 1820 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1821 context->devx_uid)) 1822 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1823 1824 return err; 1825 } 1826 1827 static void deallocate_uars(struct mlx5_ib_dev *dev, 1828 struct mlx5_ib_ucontext *context) 1829 { 1830 struct mlx5_bfreg_info *bfregi; 1831 int i; 1832 1833 bfregi = &context->bfregi; 1834 for (i = 0; i < bfregi->num_sys_pages; i++) 1835 if (i < bfregi->num_static_sys_pages || 1836 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1837 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1838 context->devx_uid); 1839 } 1840 1841 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1842 struct mlx5_core_dev *slave, 1843 struct mlx5_ib_lb_state *lb_state) 1844 { 1845 int err; 1846 1847 err = mlx5_nic_vport_update_local_lb(master, true); 1848 if (err) 1849 return err; 1850 1851 err = mlx5_nic_vport_update_local_lb(slave, true); 1852 if (err) 1853 goto out; 1854 1855 lb_state->force_enable = true; 1856 return 0; 1857 1858 out: 1859 mlx5_nic_vport_update_local_lb(master, false); 1860 return err; 1861 } 1862 1863 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 1864 struct mlx5_core_dev *slave, 1865 struct mlx5_ib_lb_state *lb_state) 1866 { 1867 mlx5_nic_vport_update_local_lb(slave, false); 1868 mlx5_nic_vport_update_local_lb(master, false); 1869 1870 lb_state->force_enable = false; 1871 } 1872 1873 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1874 { 1875 int err = 0; 1876 1877 if (dev->lb.force_enable) 1878 return 0; 1879 1880 mutex_lock(&dev->lb.mutex); 1881 if (td) 1882 dev->lb.user_td++; 1883 if (qp) 1884 dev->lb.qps++; 1885 1886 if (dev->lb.user_td == 2 || 1887 dev->lb.qps == 1) { 1888 if (!dev->lb.enabled) { 1889 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1890 dev->lb.enabled = true; 1891 } 1892 } 1893 1894 mutex_unlock(&dev->lb.mutex); 1895 1896 return err; 1897 } 1898 1899 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1900 { 1901 if (dev->lb.force_enable) 1902 return; 1903 1904 mutex_lock(&dev->lb.mutex); 1905 if (td) 1906 dev->lb.user_td--; 1907 if (qp) 1908 dev->lb.qps--; 1909 1910 if (dev->lb.user_td == 1 && 1911 dev->lb.qps == 0) { 1912 if (dev->lb.enabled) { 1913 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1914 dev->lb.enabled = false; 1915 } 1916 } 1917 1918 mutex_unlock(&dev->lb.mutex); 1919 } 1920 1921 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1922 u16 uid) 1923 { 1924 int err; 1925 1926 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1927 return 0; 1928 1929 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1930 if (err) 1931 return err; 1932 1933 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1934 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1935 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1936 return err; 1937 1938 return mlx5_ib_enable_lb(dev, true, false); 1939 } 1940 1941 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1942 u16 uid) 1943 { 1944 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1945 return; 1946 1947 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1948 1949 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1950 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1951 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1952 return; 1953 1954 mlx5_ib_disable_lb(dev, true, false); 1955 } 1956 1957 static int set_ucontext_resp(struct ib_ucontext *uctx, 1958 struct mlx5_ib_alloc_ucontext_resp *resp) 1959 { 1960 struct ib_device *ibdev = uctx->device; 1961 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1962 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1963 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1964 1965 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1966 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1967 resp->comp_mask |= 1968 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1969 } 1970 1971 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1972 if (mlx5_wc_support_get(dev->mdev)) 1973 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1974 log_bf_reg_size); 1975 resp->cache_line_size = cache_line_size(); 1976 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1977 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1978 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1979 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1980 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1981 resp->cqe_version = context->cqe_version; 1982 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1983 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1984 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1985 MLX5_CAP_GEN(dev->mdev, 1986 num_of_uars_per_page) : 1; 1987 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1988 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1989 resp->num_ports = dev->num_ports; 1990 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1991 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1992 1993 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1994 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1995 resp->eth_min_inline++; 1996 } 1997 1998 if (dev->mdev->clock_info) 1999 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2000 2001 /* 2002 * We don't want to expose information from the PCI bar that is located 2003 * after 4096 bytes, so if the arch only supports larger pages, let's 2004 * pretend we don't support reading the HCA's core clock. This is also 2005 * forced by mmap function. 2006 */ 2007 if (PAGE_SIZE <= 4096) { 2008 resp->comp_mask |= 2009 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2010 resp->hca_core_clock_offset = 2011 offsetof(struct mlx5_init_seg, 2012 internal_timer_h) % PAGE_SIZE; 2013 } 2014 2015 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2016 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2017 2018 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2019 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2020 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2021 resp->comp_mask |= 2022 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2023 2024 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2025 2026 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2027 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2028 2029 resp->comp_mask |= 2030 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2031 2032 return 0; 2033 } 2034 2035 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2036 { 2037 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2038 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2039 } 2040 2041 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2042 struct ib_udata *udata) 2043 { 2044 struct ib_device *ibdev = uctx->device; 2045 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2046 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 2047 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2048 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2049 struct mlx5_bfreg_info *bfregi; 2050 int ver; 2051 int err; 2052 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2053 max_cqe_version); 2054 bool lib_uar_4k; 2055 bool lib_uar_dyn; 2056 2057 if (!dev->ib_active) 2058 return -EAGAIN; 2059 2060 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2061 ver = 0; 2062 else if (udata->inlen >= min_req_v2) 2063 ver = 2; 2064 else 2065 return -EINVAL; 2066 2067 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2068 if (err) 2069 return err; 2070 2071 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2072 return -EOPNOTSUPP; 2073 2074 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2075 return -EOPNOTSUPP; 2076 2077 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2078 MLX5_NON_FP_BFREGS_PER_UAR); 2079 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2080 return -EINVAL; 2081 2082 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2083 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2084 if (err < 0) 2085 goto out_ctx; 2086 context->devx_uid = err; 2087 2088 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2089 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2090 context->devx_uid); 2091 if (err) 2092 goto out_devx; 2093 } 2094 } 2095 2096 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2097 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2098 bfregi = &context->bfregi; 2099 2100 if (lib_uar_dyn) { 2101 bfregi->lib_uar_dyn = lib_uar_dyn; 2102 goto uar_done; 2103 } 2104 2105 /* updates req->total_num_bfregs */ 2106 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2107 if (err) 2108 goto out_ucap; 2109 2110 mutex_init(&bfregi->lock); 2111 bfregi->lib_uar_4k = lib_uar_4k; 2112 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2113 GFP_KERNEL); 2114 if (!bfregi->count) { 2115 err = -ENOMEM; 2116 goto out_ucap; 2117 } 2118 2119 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2120 sizeof(*bfregi->sys_pages), 2121 GFP_KERNEL); 2122 if (!bfregi->sys_pages) { 2123 err = -ENOMEM; 2124 goto out_count; 2125 } 2126 2127 err = allocate_uars(dev, context); 2128 if (err) 2129 goto out_sys_pages; 2130 2131 uar_done: 2132 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2133 context->devx_uid); 2134 if (err) 2135 goto out_uars; 2136 2137 INIT_LIST_HEAD(&context->db_page_list); 2138 mutex_init(&context->db_page_mutex); 2139 2140 context->cqe_version = min_t(__u8, 2141 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2142 req.max_cqe_version); 2143 2144 err = set_ucontext_resp(uctx, &resp); 2145 if (err) 2146 goto out_mdev; 2147 2148 resp.response_length = min(udata->outlen, sizeof(resp)); 2149 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2150 if (err) 2151 goto out_mdev; 2152 2153 bfregi->ver = ver; 2154 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2155 context->lib_caps = req.lib_caps; 2156 print_lib_caps(dev, context->lib_caps); 2157 2158 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2159 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2160 2161 atomic_set(&context->tx_port_affinity, 2162 atomic_add_return( 2163 1, &dev->port[port].roce.tx_port_affinity)); 2164 } 2165 2166 return 0; 2167 2168 out_mdev: 2169 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2170 2171 out_uars: 2172 deallocate_uars(dev, context); 2173 2174 out_sys_pages: 2175 kfree(bfregi->sys_pages); 2176 2177 out_count: 2178 kfree(bfregi->count); 2179 2180 out_ucap: 2181 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2182 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2183 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2184 2185 out_devx: 2186 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2187 mlx5_ib_devx_destroy(dev, context->devx_uid); 2188 2189 out_ctx: 2190 return err; 2191 } 2192 2193 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2194 struct uverbs_attr_bundle *attrs) 2195 { 2196 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2197 int ret; 2198 2199 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2200 if (ret) 2201 return ret; 2202 2203 uctx_resp.response_length = 2204 min_t(size_t, 2205 uverbs_attr_get_len(attrs, 2206 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2207 sizeof(uctx_resp)); 2208 2209 ret = uverbs_copy_to_struct_or_zero(attrs, 2210 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2211 &uctx_resp, 2212 sizeof(uctx_resp)); 2213 return ret; 2214 } 2215 2216 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2217 { 2218 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2219 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2220 struct mlx5_bfreg_info *bfregi; 2221 2222 bfregi = &context->bfregi; 2223 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2224 2225 deallocate_uars(dev, context); 2226 kfree(bfregi->sys_pages); 2227 kfree(bfregi->count); 2228 2229 if (context->devx_uid) { 2230 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2231 mlx5_cmd_remove_privileged_uid(dev->mdev, 2232 context->devx_uid); 2233 mlx5_ib_devx_destroy(dev, context->devx_uid); 2234 } 2235 } 2236 2237 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2238 int uar_idx) 2239 { 2240 int fw_uars_per_page; 2241 2242 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2243 2244 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2245 } 2246 2247 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2248 int uar_idx) 2249 { 2250 unsigned int fw_uars_per_page; 2251 2252 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2253 MLX5_UARS_IN_PAGE : 1; 2254 2255 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2256 } 2257 2258 static int get_command(unsigned long offset) 2259 { 2260 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2261 } 2262 2263 static int get_arg(unsigned long offset) 2264 { 2265 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2266 } 2267 2268 static int get_index(unsigned long offset) 2269 { 2270 return get_arg(offset); 2271 } 2272 2273 /* Index resides in an extra byte to enable larger values than 255 */ 2274 static int get_extended_index(unsigned long offset) 2275 { 2276 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2277 } 2278 2279 2280 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2281 { 2282 } 2283 2284 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2285 { 2286 switch (cmd) { 2287 case MLX5_IB_MMAP_WC_PAGE: 2288 return "WC"; 2289 case MLX5_IB_MMAP_REGULAR_PAGE: 2290 return "best effort WC"; 2291 case MLX5_IB_MMAP_NC_PAGE: 2292 return "NC"; 2293 case MLX5_IB_MMAP_DEVICE_MEM: 2294 return "Device Memory"; 2295 default: 2296 return "Unknown"; 2297 } 2298 } 2299 2300 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2301 struct vm_area_struct *vma, 2302 struct mlx5_ib_ucontext *context) 2303 { 2304 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2305 !(vma->vm_flags & VM_SHARED)) 2306 return -EINVAL; 2307 2308 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2309 return -EOPNOTSUPP; 2310 2311 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2312 return -EPERM; 2313 vm_flags_clear(vma, VM_MAYWRITE); 2314 2315 if (!dev->mdev->clock_info) 2316 return -EOPNOTSUPP; 2317 2318 return vm_insert_page(vma, vma->vm_start, 2319 virt_to_page(dev->mdev->clock_info)); 2320 } 2321 2322 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2323 { 2324 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2325 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2326 struct mlx5_var_table *var_table = &dev->var_table; 2327 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2328 2329 switch (mentry->mmap_flag) { 2330 case MLX5_IB_MMAP_TYPE_MEMIC: 2331 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2332 mlx5_ib_dm_mmap_free(dev, mentry); 2333 break; 2334 case MLX5_IB_MMAP_TYPE_VAR: 2335 mutex_lock(&var_table->bitmap_lock); 2336 clear_bit(mentry->page_idx, var_table->bitmap); 2337 mutex_unlock(&var_table->bitmap_lock); 2338 kfree(mentry); 2339 break; 2340 case MLX5_IB_MMAP_TYPE_UAR_WC: 2341 case MLX5_IB_MMAP_TYPE_UAR_NC: 2342 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2343 context->devx_uid); 2344 kfree(mentry); 2345 break; 2346 default: 2347 WARN_ON(true); 2348 } 2349 } 2350 2351 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2352 struct vm_area_struct *vma, 2353 struct mlx5_ib_ucontext *context) 2354 { 2355 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2356 int err; 2357 unsigned long idx; 2358 phys_addr_t pfn; 2359 pgprot_t prot; 2360 u32 bfreg_dyn_idx = 0; 2361 u32 uar_index; 2362 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2363 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2364 bfregi->num_static_sys_pages; 2365 2366 if (bfregi->lib_uar_dyn) 2367 return -EINVAL; 2368 2369 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2370 return -EINVAL; 2371 2372 if (dyn_uar) 2373 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2374 else 2375 idx = get_index(vma->vm_pgoff); 2376 2377 if (idx >= max_valid_idx) { 2378 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2379 idx, max_valid_idx); 2380 return -EINVAL; 2381 } 2382 2383 switch (cmd) { 2384 case MLX5_IB_MMAP_WC_PAGE: 2385 case MLX5_IB_MMAP_ALLOC_WC: 2386 case MLX5_IB_MMAP_REGULAR_PAGE: 2387 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2388 prot = pgprot_writecombine(vma->vm_page_prot); 2389 break; 2390 case MLX5_IB_MMAP_NC_PAGE: 2391 prot = pgprot_noncached(vma->vm_page_prot); 2392 break; 2393 default: 2394 return -EINVAL; 2395 } 2396 2397 if (dyn_uar) { 2398 int uars_per_page; 2399 2400 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2401 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2402 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2403 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2404 bfreg_dyn_idx, bfregi->total_num_bfregs); 2405 return -EINVAL; 2406 } 2407 2408 mutex_lock(&bfregi->lock); 2409 /* Fail if uar already allocated, first bfreg index of each 2410 * page holds its count. 2411 */ 2412 if (bfregi->count[bfreg_dyn_idx]) { 2413 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2414 mutex_unlock(&bfregi->lock); 2415 return -EINVAL; 2416 } 2417 2418 bfregi->count[bfreg_dyn_idx]++; 2419 mutex_unlock(&bfregi->lock); 2420 2421 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2422 context->devx_uid); 2423 if (err) { 2424 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2425 goto free_bfreg; 2426 } 2427 } else { 2428 uar_index = bfregi->sys_pages[idx]; 2429 } 2430 2431 pfn = uar_index2pfn(dev, uar_index); 2432 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2433 2434 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2435 prot, NULL); 2436 if (err) { 2437 mlx5_ib_err(dev, 2438 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2439 err, mmap_cmd2str(cmd)); 2440 goto err; 2441 } 2442 2443 if (dyn_uar) 2444 bfregi->sys_pages[idx] = uar_index; 2445 return 0; 2446 2447 err: 2448 if (!dyn_uar) 2449 return err; 2450 2451 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2452 2453 free_bfreg: 2454 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2455 2456 return err; 2457 } 2458 2459 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2460 { 2461 unsigned long idx; 2462 u8 command; 2463 2464 command = get_command(vma->vm_pgoff); 2465 idx = get_extended_index(vma->vm_pgoff); 2466 2467 return (command << 16 | idx); 2468 } 2469 2470 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2471 struct vm_area_struct *vma, 2472 struct ib_ucontext *ucontext) 2473 { 2474 struct mlx5_user_mmap_entry *mentry; 2475 struct rdma_user_mmap_entry *entry; 2476 unsigned long pgoff; 2477 pgprot_t prot; 2478 phys_addr_t pfn; 2479 int ret; 2480 2481 pgoff = mlx5_vma_to_pgoff(vma); 2482 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2483 if (!entry) 2484 return -EINVAL; 2485 2486 mentry = to_mmmap(entry); 2487 pfn = (mentry->address >> PAGE_SHIFT); 2488 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2489 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2490 prot = pgprot_noncached(vma->vm_page_prot); 2491 else 2492 prot = pgprot_writecombine(vma->vm_page_prot); 2493 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2494 entry->npages * PAGE_SIZE, 2495 prot, 2496 entry); 2497 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2498 return ret; 2499 } 2500 2501 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2502 { 2503 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2504 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2505 2506 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2507 (index & 0xFF)) << PAGE_SHIFT; 2508 } 2509 2510 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2511 { 2512 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2513 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2514 unsigned long command; 2515 phys_addr_t pfn; 2516 2517 command = get_command(vma->vm_pgoff); 2518 switch (command) { 2519 case MLX5_IB_MMAP_WC_PAGE: 2520 case MLX5_IB_MMAP_ALLOC_WC: 2521 if (!mlx5_wc_support_get(dev->mdev)) 2522 return -EPERM; 2523 fallthrough; 2524 case MLX5_IB_MMAP_NC_PAGE: 2525 case MLX5_IB_MMAP_REGULAR_PAGE: 2526 return uar_mmap(dev, command, vma, context); 2527 2528 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2529 return -ENOSYS; 2530 2531 case MLX5_IB_MMAP_CORE_CLOCK: 2532 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2533 return -EINVAL; 2534 2535 if (vma->vm_flags & VM_WRITE) 2536 return -EPERM; 2537 vm_flags_clear(vma, VM_MAYWRITE); 2538 2539 /* Don't expose to user-space information it shouldn't have */ 2540 if (PAGE_SIZE > 4096) 2541 return -EOPNOTSUPP; 2542 2543 pfn = (dev->mdev->iseg_base + 2544 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2545 PAGE_SHIFT; 2546 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2547 PAGE_SIZE, 2548 pgprot_noncached(vma->vm_page_prot), 2549 NULL); 2550 case MLX5_IB_MMAP_CLOCK_INFO: 2551 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2552 2553 default: 2554 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2561 { 2562 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2563 struct ib_device *ibdev = ibpd->device; 2564 struct mlx5_ib_alloc_pd_resp resp; 2565 int err; 2566 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2567 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2568 u16 uid = 0; 2569 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2570 udata, struct mlx5_ib_ucontext, ibucontext); 2571 2572 uid = context ? context->devx_uid : 0; 2573 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2574 MLX5_SET(alloc_pd_in, in, uid, uid); 2575 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2576 if (err) 2577 return err; 2578 2579 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2580 pd->uid = uid; 2581 if (udata) { 2582 resp.pdn = pd->pdn; 2583 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2584 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2585 return -EFAULT; 2586 } 2587 } 2588 2589 return 0; 2590 } 2591 2592 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2593 { 2594 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2595 struct mlx5_ib_pd *mpd = to_mpd(pd); 2596 2597 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2598 } 2599 2600 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2601 { 2602 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2603 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2604 int err; 2605 u16 uid; 2606 2607 uid = ibqp->pd ? 2608 to_mpd(ibqp->pd)->uid : 0; 2609 2610 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2611 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2612 return -EOPNOTSUPP; 2613 } 2614 2615 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2616 if (err) 2617 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2618 ibqp->qp_num, gid->raw); 2619 2620 return err; 2621 } 2622 2623 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2624 { 2625 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2626 int err; 2627 u16 uid; 2628 2629 uid = ibqp->pd ? 2630 to_mpd(ibqp->pd)->uid : 0; 2631 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2632 if (err) 2633 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2634 ibqp->qp_num, gid->raw); 2635 2636 return err; 2637 } 2638 2639 static int init_node_data(struct mlx5_ib_dev *dev) 2640 { 2641 int err; 2642 2643 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2644 if (err) 2645 return err; 2646 2647 dev->mdev->rev_id = dev->mdev->pdev->revision; 2648 2649 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2650 } 2651 2652 static ssize_t fw_pages_show(struct device *device, 2653 struct device_attribute *attr, char *buf) 2654 { 2655 struct mlx5_ib_dev *dev = 2656 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2657 2658 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2659 } 2660 static DEVICE_ATTR_RO(fw_pages); 2661 2662 static ssize_t reg_pages_show(struct device *device, 2663 struct device_attribute *attr, char *buf) 2664 { 2665 struct mlx5_ib_dev *dev = 2666 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2667 2668 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2669 } 2670 static DEVICE_ATTR_RO(reg_pages); 2671 2672 static ssize_t hca_type_show(struct device *device, 2673 struct device_attribute *attr, char *buf) 2674 { 2675 struct mlx5_ib_dev *dev = 2676 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2677 2678 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2679 } 2680 static DEVICE_ATTR_RO(hca_type); 2681 2682 static ssize_t hw_rev_show(struct device *device, 2683 struct device_attribute *attr, char *buf) 2684 { 2685 struct mlx5_ib_dev *dev = 2686 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2687 2688 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2689 } 2690 static DEVICE_ATTR_RO(hw_rev); 2691 2692 static ssize_t board_id_show(struct device *device, 2693 struct device_attribute *attr, char *buf) 2694 { 2695 struct mlx5_ib_dev *dev = 2696 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2697 2698 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2699 dev->mdev->board_id); 2700 } 2701 static DEVICE_ATTR_RO(board_id); 2702 2703 static struct attribute *mlx5_class_attributes[] = { 2704 &dev_attr_hw_rev.attr, 2705 &dev_attr_hca_type.attr, 2706 &dev_attr_board_id.attr, 2707 &dev_attr_fw_pages.attr, 2708 &dev_attr_reg_pages.attr, 2709 NULL, 2710 }; 2711 2712 static const struct attribute_group mlx5_attr_group = { 2713 .attrs = mlx5_class_attributes, 2714 }; 2715 2716 static void pkey_change_handler(struct work_struct *work) 2717 { 2718 struct mlx5_ib_port_resources *ports = 2719 container_of(work, struct mlx5_ib_port_resources, 2720 pkey_change_work); 2721 2722 if (!ports->gsi) 2723 /* 2724 * We got this event before device was fully configured 2725 * and MAD registration code wasn't called/finished yet. 2726 */ 2727 return; 2728 2729 mlx5_ib_gsi_pkey_change(ports->gsi); 2730 } 2731 2732 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2733 { 2734 struct mlx5_ib_qp *mqp; 2735 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2736 struct mlx5_core_cq *mcq; 2737 struct list_head cq_armed_list; 2738 unsigned long flags_qp; 2739 unsigned long flags_cq; 2740 unsigned long flags; 2741 2742 INIT_LIST_HEAD(&cq_armed_list); 2743 2744 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2745 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2746 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2747 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2748 if (mqp->sq.tail != mqp->sq.head) { 2749 send_mcq = to_mcq(mqp->ibqp.send_cq); 2750 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2751 if (send_mcq->mcq.comp && 2752 mqp->ibqp.send_cq->comp_handler) { 2753 if (!send_mcq->mcq.reset_notify_added) { 2754 send_mcq->mcq.reset_notify_added = 1; 2755 list_add_tail(&send_mcq->mcq.reset_notify, 2756 &cq_armed_list); 2757 } 2758 } 2759 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2760 } 2761 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2762 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2763 /* no handling is needed for SRQ */ 2764 if (!mqp->ibqp.srq) { 2765 if (mqp->rq.tail != mqp->rq.head) { 2766 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2767 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2768 if (recv_mcq->mcq.comp && 2769 mqp->ibqp.recv_cq->comp_handler) { 2770 if (!recv_mcq->mcq.reset_notify_added) { 2771 recv_mcq->mcq.reset_notify_added = 1; 2772 list_add_tail(&recv_mcq->mcq.reset_notify, 2773 &cq_armed_list); 2774 } 2775 } 2776 spin_unlock_irqrestore(&recv_mcq->lock, 2777 flags_cq); 2778 } 2779 } 2780 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2781 } 2782 /*At that point all inflight post send were put to be executed as of we 2783 * lock/unlock above locks Now need to arm all involved CQs. 2784 */ 2785 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2786 mcq->comp(mcq, NULL); 2787 } 2788 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2789 } 2790 2791 static void delay_drop_handler(struct work_struct *work) 2792 { 2793 int err; 2794 struct mlx5_ib_delay_drop *delay_drop = 2795 container_of(work, struct mlx5_ib_delay_drop, 2796 delay_drop_work); 2797 2798 atomic_inc(&delay_drop->events_cnt); 2799 2800 mutex_lock(&delay_drop->lock); 2801 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2802 if (err) { 2803 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2804 delay_drop->timeout); 2805 delay_drop->activate = false; 2806 } 2807 mutex_unlock(&delay_drop->lock); 2808 } 2809 2810 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2811 struct ib_event *ibev) 2812 { 2813 u32 port = (eqe->data.port.port >> 4) & 0xf; 2814 2815 switch (eqe->sub_type) { 2816 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2817 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2818 IB_LINK_LAYER_ETHERNET) 2819 schedule_work(&ibdev->delay_drop.delay_drop_work); 2820 break; 2821 default: /* do nothing */ 2822 return; 2823 } 2824 } 2825 2826 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2827 struct ib_event *ibev) 2828 { 2829 u32 port = (eqe->data.port.port >> 4) & 0xf; 2830 2831 ibev->element.port_num = port; 2832 2833 switch (eqe->sub_type) { 2834 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2835 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2836 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2837 /* In RoCE, port up/down events are handled in 2838 * mlx5_netdev_event(). 2839 */ 2840 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2841 IB_LINK_LAYER_ETHERNET) 2842 return -EINVAL; 2843 2844 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2845 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2846 break; 2847 2848 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2849 ibev->event = IB_EVENT_LID_CHANGE; 2850 break; 2851 2852 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2853 ibev->event = IB_EVENT_PKEY_CHANGE; 2854 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2855 break; 2856 2857 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2858 ibev->event = IB_EVENT_GID_CHANGE; 2859 break; 2860 2861 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2862 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2863 break; 2864 default: 2865 return -EINVAL; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static void mlx5_ib_handle_event(struct work_struct *_work) 2872 { 2873 struct mlx5_ib_event_work *work = 2874 container_of(_work, struct mlx5_ib_event_work, work); 2875 struct mlx5_ib_dev *ibdev; 2876 struct ib_event ibev; 2877 bool fatal = false; 2878 2879 if (work->is_slave) { 2880 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2881 if (!ibdev) 2882 goto out; 2883 } else { 2884 ibdev = work->dev; 2885 } 2886 2887 switch (work->event) { 2888 case MLX5_DEV_EVENT_SYS_ERROR: 2889 ibev.event = IB_EVENT_DEVICE_FATAL; 2890 mlx5_ib_handle_internal_error(ibdev); 2891 ibev.element.port_num = (u8)(unsigned long)work->param; 2892 fatal = true; 2893 break; 2894 case MLX5_EVENT_TYPE_PORT_CHANGE: 2895 if (handle_port_change(ibdev, work->param, &ibev)) 2896 goto out; 2897 break; 2898 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2899 handle_general_event(ibdev, work->param, &ibev); 2900 fallthrough; 2901 default: 2902 goto out; 2903 } 2904 2905 ibev.device = &ibdev->ib_dev; 2906 2907 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2908 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2909 goto out; 2910 } 2911 2912 if (ibdev->ib_active) 2913 ib_dispatch_event(&ibev); 2914 2915 if (fatal) 2916 ibdev->ib_active = false; 2917 out: 2918 kfree(work); 2919 } 2920 2921 static int mlx5_ib_event(struct notifier_block *nb, 2922 unsigned long event, void *param) 2923 { 2924 struct mlx5_ib_event_work *work; 2925 2926 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2927 if (!work) 2928 return NOTIFY_DONE; 2929 2930 INIT_WORK(&work->work, mlx5_ib_handle_event); 2931 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2932 work->is_slave = false; 2933 work->param = param; 2934 work->event = event; 2935 2936 queue_work(mlx5_ib_event_wq, &work->work); 2937 2938 return NOTIFY_OK; 2939 } 2940 2941 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2942 unsigned long event, void *param) 2943 { 2944 struct mlx5_ib_event_work *work; 2945 2946 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2947 if (!work) 2948 return NOTIFY_DONE; 2949 2950 INIT_WORK(&work->work, mlx5_ib_handle_event); 2951 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2952 work->is_slave = true; 2953 work->param = param; 2954 work->event = event; 2955 queue_work(mlx5_ib_event_wq, &work->work); 2956 2957 return NOTIFY_OK; 2958 } 2959 2960 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 2961 { 2962 struct mlx5_hca_vport_context vport_ctx; 2963 int err; 2964 2965 *num_plane = 0; 2966 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 2967 return 0; 2968 2969 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 2970 if (err) 2971 return err; 2972 2973 *num_plane = vport_ctx.num_plane; 2974 return 0; 2975 } 2976 2977 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2978 { 2979 struct mlx5_hca_vport_context vport_ctx; 2980 int err; 2981 int port; 2982 2983 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2984 return 0; 2985 2986 for (port = 1; port <= dev->num_ports; port++) { 2987 if (dev->num_plane) { 2988 dev->port_caps[port - 1].has_smi = false; 2989 continue; 2990 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 2991 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 2992 dev->port_caps[port - 1].has_smi = true; 2993 continue; 2994 } 2995 2996 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2997 &vport_ctx); 2998 if (err) { 2999 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3000 port, err); 3001 return err; 3002 } 3003 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3004 } 3005 3006 return 0; 3007 } 3008 3009 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3010 { 3011 unsigned int port; 3012 3013 rdma_for_each_port (&dev->ib_dev, port) 3014 mlx5_query_ext_port_caps(dev, port); 3015 } 3016 3017 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3018 { 3019 switch (umr_fence_cap) { 3020 case MLX5_CAP_UMR_FENCE_NONE: 3021 return MLX5_FENCE_MODE_NONE; 3022 case MLX5_CAP_UMR_FENCE_SMALL: 3023 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3024 default: 3025 return MLX5_FENCE_MODE_STRONG_ORDERING; 3026 } 3027 } 3028 3029 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3030 { 3031 struct mlx5_ib_resources *devr = &dev->devr; 3032 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3033 struct ib_device *ibdev; 3034 struct ib_pd *pd; 3035 struct ib_cq *cq; 3036 int ret = 0; 3037 3038 3039 /* 3040 * devr->c0 is set once, never changed until device unload. 3041 * Avoid taking the mutex if initialization is already done. 3042 */ 3043 if (devr->c0) 3044 return 0; 3045 3046 mutex_lock(&devr->cq_lock); 3047 if (devr->c0) 3048 goto unlock; 3049 3050 ibdev = &dev->ib_dev; 3051 pd = ib_alloc_pd(ibdev, 0); 3052 if (IS_ERR(pd)) { 3053 ret = PTR_ERR(pd); 3054 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret); 3055 goto unlock; 3056 } 3057 3058 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3059 if (IS_ERR(cq)) { 3060 ret = PTR_ERR(cq); 3061 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret); 3062 ib_dealloc_pd(pd); 3063 goto unlock; 3064 } 3065 3066 devr->p0 = pd; 3067 devr->c0 = cq; 3068 3069 unlock: 3070 mutex_unlock(&devr->cq_lock); 3071 return ret; 3072 } 3073 3074 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3075 { 3076 struct mlx5_ib_resources *devr = &dev->devr; 3077 struct ib_srq_init_attr attr; 3078 struct ib_srq *s0, *s1; 3079 int ret = 0; 3080 3081 /* 3082 * devr->s1 is set once, never changed until device unload. 3083 * Avoid taking the mutex if initialization is already done. 3084 */ 3085 if (devr->s1) 3086 return 0; 3087 3088 mutex_lock(&devr->srq_lock); 3089 if (devr->s1) 3090 goto unlock; 3091 3092 ret = mlx5_ib_dev_res_cq_init(dev); 3093 if (ret) 3094 goto unlock; 3095 3096 memset(&attr, 0, sizeof(attr)); 3097 attr.attr.max_sge = 1; 3098 attr.attr.max_wr = 1; 3099 attr.srq_type = IB_SRQT_XRC; 3100 attr.ext.cq = devr->c0; 3101 3102 s0 = ib_create_srq(devr->p0, &attr); 3103 if (IS_ERR(s0)) { 3104 ret = PTR_ERR(s0); 3105 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret); 3106 goto unlock; 3107 } 3108 3109 memset(&attr, 0, sizeof(attr)); 3110 attr.attr.max_sge = 1; 3111 attr.attr.max_wr = 1; 3112 attr.srq_type = IB_SRQT_BASIC; 3113 3114 s1 = ib_create_srq(devr->p0, &attr); 3115 if (IS_ERR(s1)) { 3116 ret = PTR_ERR(s1); 3117 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret); 3118 ib_destroy_srq(s0); 3119 } 3120 3121 devr->s0 = s0; 3122 devr->s1 = s1; 3123 3124 unlock: 3125 mutex_unlock(&devr->srq_lock); 3126 return ret; 3127 } 3128 3129 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3130 { 3131 struct mlx5_ib_resources *devr = &dev->devr; 3132 int ret; 3133 3134 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3135 return -EOPNOTSUPP; 3136 3137 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3138 if (ret) 3139 return ret; 3140 3141 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3142 if (ret) { 3143 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3144 return ret; 3145 } 3146 3147 mutex_init(&devr->cq_lock); 3148 mutex_init(&devr->srq_lock); 3149 3150 return 0; 3151 } 3152 3153 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3154 { 3155 struct mlx5_ib_resources *devr = &dev->devr; 3156 3157 /* After s0/s1 init, they are not unset during the device lifetime. */ 3158 if (devr->s1) { 3159 ib_destroy_srq(devr->s1); 3160 ib_destroy_srq(devr->s0); 3161 } 3162 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3163 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3164 /* After p0/c0 init, they are not unset during the device lifetime. */ 3165 if (devr->c0) { 3166 ib_destroy_cq(devr->c0); 3167 ib_dealloc_pd(devr->p0); 3168 } 3169 mutex_destroy(&devr->cq_lock); 3170 mutex_destroy(&devr->srq_lock); 3171 } 3172 3173 static int 3174 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3175 { 3176 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3177 struct mlx5_core_dev *mdev = dev->mdev; 3178 bool ro_supp = false; 3179 void *mkc; 3180 u32 mkey; 3181 u32 pdn; 3182 u32 *in; 3183 int err; 3184 3185 err = mlx5_core_alloc_pd(mdev, &pdn); 3186 if (err) 3187 return err; 3188 3189 in = kvzalloc(inlen, GFP_KERNEL); 3190 if (!in) { 3191 err = -ENOMEM; 3192 goto err; 3193 } 3194 3195 MLX5_SET(create_mkey_in, in, data_direct, 1); 3196 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3197 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3198 MLX5_SET(mkc, mkc, lw, 1); 3199 MLX5_SET(mkc, mkc, lr, 1); 3200 MLX5_SET(mkc, mkc, rw, 1); 3201 MLX5_SET(mkc, mkc, rr, 1); 3202 MLX5_SET(mkc, mkc, a, 1); 3203 MLX5_SET(mkc, mkc, pd, pdn); 3204 MLX5_SET(mkc, mkc, length64, 1); 3205 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3206 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3207 if (err) 3208 goto err_mkey; 3209 3210 dev->ddr.mkey = mkey; 3211 dev->ddr.pdn = pdn; 3212 3213 /* create another mkey with RO support */ 3214 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { 3215 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 3216 ro_supp = true; 3217 } 3218 3219 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { 3220 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 3221 ro_supp = true; 3222 } 3223 3224 if (ro_supp) { 3225 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3226 /* RO is defined as best effort */ 3227 if (!err) { 3228 dev->ddr.mkey_ro = mkey; 3229 dev->ddr.mkey_ro_valid = true; 3230 } 3231 } 3232 3233 kvfree(in); 3234 return 0; 3235 3236 err_mkey: 3237 kvfree(in); 3238 err: 3239 mlx5_core_dealloc_pd(mdev, pdn); 3240 return err; 3241 } 3242 3243 static void 3244 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3245 { 3246 3247 if (dev->ddr.mkey_ro_valid) 3248 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro); 3249 3250 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3251 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3252 } 3253 3254 static u32 get_core_cap_flags(struct ib_device *ibdev, 3255 struct mlx5_hca_vport_context *rep) 3256 { 3257 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3258 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3259 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3260 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3261 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3262 u32 ret = 0; 3263 3264 if (rep->grh_required) 3265 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3266 3267 if (dev->num_plane) 3268 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3269 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3270 RDMA_CORE_CAP_AF_IB; 3271 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3272 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3273 3274 if (ll == IB_LINK_LAYER_INFINIBAND) 3275 return ret | RDMA_CORE_PORT_IBA_IB; 3276 3277 if (raw_support) 3278 ret |= RDMA_CORE_PORT_RAW_PACKET; 3279 3280 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3281 return ret; 3282 3283 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3284 return ret; 3285 3286 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3287 ret |= RDMA_CORE_PORT_IBA_ROCE; 3288 3289 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3290 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3291 3292 return ret; 3293 } 3294 3295 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3296 struct ib_port_immutable *immutable) 3297 { 3298 struct ib_port_attr attr; 3299 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3300 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3301 struct mlx5_hca_vport_context rep = {0}; 3302 int err; 3303 3304 err = ib_query_port(ibdev, port_num, &attr); 3305 if (err) 3306 return err; 3307 3308 if (ll == IB_LINK_LAYER_INFINIBAND) { 3309 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3310 port_num = smi_to_native_portnum(dev, port_num); 3311 3312 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3313 &rep); 3314 if (err) 3315 return err; 3316 } 3317 3318 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3319 immutable->gid_tbl_len = attr.gid_tbl_len; 3320 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3321 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3322 3323 return 0; 3324 } 3325 3326 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3327 struct ib_port_immutable *immutable) 3328 { 3329 struct ib_port_attr attr; 3330 int err; 3331 3332 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3333 3334 err = ib_query_port(ibdev, port_num, &attr); 3335 if (err) 3336 return err; 3337 3338 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3339 immutable->gid_tbl_len = attr.gid_tbl_len; 3340 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3341 3342 return 0; 3343 } 3344 3345 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3346 { 3347 struct mlx5_ib_dev *dev = 3348 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3349 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3350 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3351 fw_rev_sub(dev->mdev)); 3352 } 3353 3354 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3355 { 3356 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3357 lag_events); 3358 struct mlx5_core_dev *mdev = dev->mdev; 3359 struct ib_device *ibdev = &dev->ib_dev; 3360 struct net_device *old_ndev = NULL; 3361 struct mlx5_ib_port *port; 3362 struct net_device *ndev; 3363 u32 portnum = 0; 3364 int ret = 0; 3365 int i; 3366 3367 switch (event) { 3368 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3369 ndev = data; 3370 if (ndev) { 3371 if (!mlx5_lag_is_roce(mdev)) { 3372 // sriov lag 3373 for (i = 0; i < dev->num_ports; i++) { 3374 port = &dev->port[i]; 3375 if (port->rep && port->rep->vport == 3376 MLX5_VPORT_UPLINK) { 3377 portnum = i; 3378 break; 3379 } 3380 } 3381 } 3382 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3383 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3384 if (ret) 3385 goto out; 3386 3387 if (old_ndev) 3388 roce_del_all_netdev_gids(ibdev, portnum + 1, 3389 old_ndev); 3390 rdma_roce_rescan_port(ibdev, portnum + 1); 3391 } 3392 break; 3393 default: 3394 return NOTIFY_DONE; 3395 } 3396 3397 out: 3398 dev_put(old_ndev); 3399 return notifier_from_errno(ret); 3400 } 3401 3402 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3403 { 3404 dev->lag_events.notifier_call = lag_event; 3405 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3406 &dev->lag_events); 3407 } 3408 3409 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3410 { 3411 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3412 &dev->lag_events); 3413 } 3414 3415 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3416 { 3417 struct mlx5_core_dev *mdev = dev->mdev; 3418 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3419 MLX5_FLOW_NAMESPACE_LAG); 3420 struct mlx5_flow_table *ft; 3421 int err; 3422 3423 if (!ns || !mlx5_lag_is_active(mdev)) 3424 return 0; 3425 3426 err = mlx5_cmd_create_vport_lag(mdev); 3427 if (err) 3428 return err; 3429 3430 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3431 if (IS_ERR(ft)) { 3432 err = PTR_ERR(ft); 3433 goto err_destroy_vport_lag; 3434 } 3435 3436 mlx5e_lag_event_register(dev); 3437 dev->flow_db->lag_demux_ft = ft; 3438 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3439 dev->lag_active = true; 3440 return 0; 3441 3442 err_destroy_vport_lag: 3443 mlx5_cmd_destroy_vport_lag(mdev); 3444 return err; 3445 } 3446 3447 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3448 { 3449 struct mlx5_core_dev *mdev = dev->mdev; 3450 3451 if (dev->lag_active) { 3452 dev->lag_active = false; 3453 3454 mlx5e_lag_event_unregister(dev); 3455 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3456 dev->flow_db->lag_demux_ft = NULL; 3457 3458 mlx5_cmd_destroy_vport_lag(mdev); 3459 } 3460 } 3461 3462 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3463 struct net_device *netdev) 3464 { 3465 int err; 3466 3467 if (roce->tracking_netdev) 3468 return; 3469 roce->tracking_netdev = netdev; 3470 roce->nb.notifier_call = mlx5_netdev_event; 3471 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3472 WARN_ON(err); 3473 } 3474 3475 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3476 { 3477 if (!roce->tracking_netdev) 3478 return; 3479 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3480 &roce->nn); 3481 roce->tracking_netdev = NULL; 3482 } 3483 3484 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3485 unsigned long event, void *data) 3486 { 3487 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3488 struct net_device *netdev = data; 3489 3490 switch (event) { 3491 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3492 if (netdev) 3493 mlx5_netdev_notifier_register(roce, netdev); 3494 else 3495 mlx5_netdev_notifier_unregister(roce); 3496 break; 3497 default: 3498 return NOTIFY_DONE; 3499 } 3500 3501 return NOTIFY_OK; 3502 } 3503 3504 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3505 { 3506 struct mlx5_roce *roce = &dev->port[port_num].roce; 3507 3508 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3509 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3510 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3511 } 3512 3513 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3514 { 3515 struct mlx5_roce *roce = &dev->port[port_num].roce; 3516 3517 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3518 mlx5_netdev_notifier_unregister(roce); 3519 } 3520 3521 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3522 { 3523 int err; 3524 3525 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3526 err = mlx5_nic_vport_enable_roce(dev->mdev); 3527 if (err) 3528 return err; 3529 } 3530 3531 err = mlx5_eth_lag_init(dev); 3532 if (err) 3533 goto err_disable_roce; 3534 3535 return 0; 3536 3537 err_disable_roce: 3538 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3539 mlx5_nic_vport_disable_roce(dev->mdev); 3540 3541 return err; 3542 } 3543 3544 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3545 { 3546 mlx5_eth_lag_cleanup(dev); 3547 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3548 mlx5_nic_vport_disable_roce(dev->mdev); 3549 } 3550 3551 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3552 enum rdma_netdev_t type, 3553 struct rdma_netdev_alloc_params *params) 3554 { 3555 if (type != RDMA_NETDEV_IPOIB) 3556 return -EOPNOTSUPP; 3557 3558 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3559 } 3560 3561 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3562 size_t count, loff_t *pos) 3563 { 3564 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3565 char lbuf[20]; 3566 int len; 3567 3568 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3569 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3570 } 3571 3572 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3573 size_t count, loff_t *pos) 3574 { 3575 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3576 u32 timeout; 3577 u32 var; 3578 3579 if (kstrtouint_from_user(buf, count, 0, &var)) 3580 return -EFAULT; 3581 3582 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3583 1000); 3584 if (timeout != var) 3585 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3586 timeout); 3587 3588 delay_drop->timeout = timeout; 3589 3590 return count; 3591 } 3592 3593 static const struct file_operations fops_delay_drop_timeout = { 3594 .owner = THIS_MODULE, 3595 .open = simple_open, 3596 .write = delay_drop_timeout_write, 3597 .read = delay_drop_timeout_read, 3598 }; 3599 3600 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3601 struct mlx5_ib_multiport_info *mpi) 3602 { 3603 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3604 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3605 int comps; 3606 int err; 3607 int i; 3608 3609 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3610 3611 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3612 3613 mlx5_core_mp_event_replay(ibdev->mdev, 3614 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3615 NULL); 3616 mlx5_core_mp_event_replay(mpi->mdev, 3617 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3618 NULL); 3619 3620 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3621 3622 spin_lock(&port->mp.mpi_lock); 3623 if (!mpi->ibdev) { 3624 spin_unlock(&port->mp.mpi_lock); 3625 return; 3626 } 3627 3628 mpi->ibdev = NULL; 3629 3630 spin_unlock(&port->mp.mpi_lock); 3631 if (mpi->mdev_events.notifier_call) 3632 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3633 mpi->mdev_events.notifier_call = NULL; 3634 mlx5_mdev_netdev_untrack(ibdev, port_num); 3635 spin_lock(&port->mp.mpi_lock); 3636 3637 comps = mpi->mdev_refcnt; 3638 if (comps) { 3639 mpi->unaffiliate = true; 3640 init_completion(&mpi->unref_comp); 3641 spin_unlock(&port->mp.mpi_lock); 3642 3643 for (i = 0; i < comps; i++) 3644 wait_for_completion(&mpi->unref_comp); 3645 3646 spin_lock(&port->mp.mpi_lock); 3647 mpi->unaffiliate = false; 3648 } 3649 3650 port->mp.mpi = NULL; 3651 3652 spin_unlock(&port->mp.mpi_lock); 3653 3654 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3655 3656 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3657 /* Log an error, still needed to cleanup the pointers and add 3658 * it back to the list. 3659 */ 3660 if (err) 3661 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3662 port_num + 1); 3663 3664 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3665 } 3666 3667 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3668 struct mlx5_ib_multiport_info *mpi) 3669 { 3670 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3671 u64 key; 3672 int err; 3673 3674 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3675 3676 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3677 if (ibdev->port[port_num].mp.mpi) { 3678 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3679 port_num + 1); 3680 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3681 return false; 3682 } 3683 3684 ibdev->port[port_num].mp.mpi = mpi; 3685 mpi->ibdev = ibdev; 3686 mpi->mdev_events.notifier_call = NULL; 3687 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3688 3689 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3690 if (err) 3691 goto unbind; 3692 3693 mlx5_mdev_netdev_track(ibdev, port_num); 3694 3695 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3696 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3697 3698 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3699 3700 key = mpi->mdev->priv.adev_idx; 3701 mlx5_core_mp_event_replay(mpi->mdev, 3702 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3703 &key); 3704 mlx5_core_mp_event_replay(ibdev->mdev, 3705 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3706 &key); 3707 3708 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3709 if (err) 3710 goto unbind; 3711 3712 return true; 3713 3714 unbind: 3715 mlx5_ib_unbind_slave_port(ibdev, mpi); 3716 return false; 3717 } 3718 3719 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3720 { 3721 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3722 int ret; 3723 3724 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3725 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3726 return 0; 3727 3728 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3729 if (ret) 3730 return ret; 3731 3732 ret = mlx5_ib_create_data_direct_resources(dev); 3733 if (ret) 3734 return ret; 3735 3736 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3737 ret = mlx5_data_direct_ib_reg(dev, vuid); 3738 if (ret) 3739 mlx5_ib_free_data_direct_resources(dev); 3740 3741 return ret; 3742 } 3743 3744 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3745 { 3746 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3747 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3748 return; 3749 3750 mlx5_data_direct_ib_unreg(dev); 3751 mlx5_ib_free_data_direct_resources(dev); 3752 } 3753 3754 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3755 { 3756 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3757 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3758 port_num + 1); 3759 struct mlx5_ib_multiport_info *mpi; 3760 int err; 3761 u32 i; 3762 3763 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3764 return 0; 3765 3766 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3767 &dev->sys_image_guid); 3768 if (err) 3769 return err; 3770 3771 err = mlx5_nic_vport_enable_roce(dev->mdev); 3772 if (err) 3773 return err; 3774 3775 mutex_lock(&mlx5_ib_multiport_mutex); 3776 for (i = 0; i < dev->num_ports; i++) { 3777 bool bound = false; 3778 3779 /* build a stub multiport info struct for the native port. */ 3780 if (i == port_num) { 3781 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3782 if (!mpi) { 3783 mutex_unlock(&mlx5_ib_multiport_mutex); 3784 mlx5_nic_vport_disable_roce(dev->mdev); 3785 return -ENOMEM; 3786 } 3787 3788 mpi->is_master = true; 3789 mpi->mdev = dev->mdev; 3790 mpi->sys_image_guid = dev->sys_image_guid; 3791 dev->port[i].mp.mpi = mpi; 3792 mpi->ibdev = dev; 3793 mpi = NULL; 3794 continue; 3795 } 3796 3797 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3798 list) { 3799 if (dev->sys_image_guid == mpi->sys_image_guid && 3800 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 3801 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 3802 bound = mlx5_ib_bind_slave_port(dev, mpi); 3803 } 3804 3805 if (bound) { 3806 dev_dbg(mpi->mdev->device, 3807 "removing port from unaffiliated list.\n"); 3808 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3809 list_del(&mpi->list); 3810 break; 3811 } 3812 } 3813 if (!bound) 3814 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3815 i + 1); 3816 } 3817 3818 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3819 mutex_unlock(&mlx5_ib_multiport_mutex); 3820 return err; 3821 } 3822 3823 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3824 { 3825 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3826 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3827 port_num + 1); 3828 u32 i; 3829 3830 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3831 return; 3832 3833 mutex_lock(&mlx5_ib_multiport_mutex); 3834 for (i = 0; i < dev->num_ports; i++) { 3835 if (dev->port[i].mp.mpi) { 3836 /* Destroy the native port stub */ 3837 if (i == port_num) { 3838 kfree(dev->port[i].mp.mpi); 3839 dev->port[i].mp.mpi = NULL; 3840 } else { 3841 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3842 i + 1); 3843 list_add_tail(&dev->port[i].mp.mpi->list, 3844 &mlx5_ib_unaffiliated_port_list); 3845 mlx5_ib_unbind_slave_port(dev, 3846 dev->port[i].mp.mpi); 3847 } 3848 } 3849 } 3850 3851 mlx5_ib_dbg(dev, "removing from devlist\n"); 3852 list_del(&dev->ib_dev_list); 3853 mutex_unlock(&mlx5_ib_multiport_mutex); 3854 3855 mlx5_nic_vport_disable_roce(dev->mdev); 3856 } 3857 3858 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3859 enum rdma_remove_reason why, 3860 struct uverbs_attr_bundle *attrs) 3861 { 3862 struct mlx5_user_mmap_entry *obj = uobject->object; 3863 3864 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3865 return 0; 3866 } 3867 3868 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3869 struct mlx5_user_mmap_entry *entry, 3870 size_t length) 3871 { 3872 return rdma_user_mmap_entry_insert_range( 3873 &c->ibucontext, &entry->rdma_entry, length, 3874 (MLX5_IB_MMAP_OFFSET_START << 16), 3875 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3876 } 3877 3878 static struct mlx5_user_mmap_entry * 3879 alloc_var_entry(struct mlx5_ib_ucontext *c) 3880 { 3881 struct mlx5_user_mmap_entry *entry; 3882 struct mlx5_var_table *var_table; 3883 u32 page_idx; 3884 int err; 3885 3886 var_table = &to_mdev(c->ibucontext.device)->var_table; 3887 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3888 if (!entry) 3889 return ERR_PTR(-ENOMEM); 3890 3891 mutex_lock(&var_table->bitmap_lock); 3892 page_idx = find_first_zero_bit(var_table->bitmap, 3893 var_table->num_var_hw_entries); 3894 if (page_idx >= var_table->num_var_hw_entries) { 3895 err = -ENOSPC; 3896 mutex_unlock(&var_table->bitmap_lock); 3897 goto end; 3898 } 3899 3900 set_bit(page_idx, var_table->bitmap); 3901 mutex_unlock(&var_table->bitmap_lock); 3902 3903 entry->address = var_table->hw_start_addr + 3904 (page_idx * var_table->stride_size); 3905 entry->page_idx = page_idx; 3906 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3907 3908 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3909 var_table->stride_size); 3910 if (err) 3911 goto err_insert; 3912 3913 return entry; 3914 3915 err_insert: 3916 mutex_lock(&var_table->bitmap_lock); 3917 clear_bit(page_idx, var_table->bitmap); 3918 mutex_unlock(&var_table->bitmap_lock); 3919 end: 3920 kfree(entry); 3921 return ERR_PTR(err); 3922 } 3923 3924 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3925 struct uverbs_attr_bundle *attrs) 3926 { 3927 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3928 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3929 struct mlx5_ib_ucontext *c; 3930 struct mlx5_user_mmap_entry *entry; 3931 u64 mmap_offset; 3932 u32 length; 3933 int err; 3934 3935 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3936 if (IS_ERR(c)) 3937 return PTR_ERR(c); 3938 3939 entry = alloc_var_entry(c); 3940 if (IS_ERR(entry)) 3941 return PTR_ERR(entry); 3942 3943 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3944 length = entry->rdma_entry.npages * PAGE_SIZE; 3945 uobj->object = entry; 3946 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3947 3948 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3949 &mmap_offset, sizeof(mmap_offset)); 3950 if (err) 3951 return err; 3952 3953 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3954 &entry->page_idx, sizeof(entry->page_idx)); 3955 if (err) 3956 return err; 3957 3958 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3959 &length, sizeof(length)); 3960 return err; 3961 } 3962 3963 DECLARE_UVERBS_NAMED_METHOD( 3964 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3965 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3966 MLX5_IB_OBJECT_VAR, 3967 UVERBS_ACCESS_NEW, 3968 UA_MANDATORY), 3969 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3970 UVERBS_ATTR_TYPE(u32), 3971 UA_MANDATORY), 3972 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3973 UVERBS_ATTR_TYPE(u32), 3974 UA_MANDATORY), 3975 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3976 UVERBS_ATTR_TYPE(u64), 3977 UA_MANDATORY)); 3978 3979 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3980 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3981 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3982 MLX5_IB_OBJECT_VAR, 3983 UVERBS_ACCESS_DESTROY, 3984 UA_MANDATORY)); 3985 3986 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3987 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3988 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3989 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3990 3991 static bool var_is_supported(struct ib_device *device) 3992 { 3993 struct mlx5_ib_dev *dev = to_mdev(device); 3994 3995 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3996 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3997 } 3998 3999 static struct mlx5_user_mmap_entry * 4000 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4001 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4002 { 4003 struct mlx5_user_mmap_entry *entry; 4004 struct mlx5_ib_dev *dev; 4005 u32 uar_index; 4006 int err; 4007 4008 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 4009 if (!entry) 4010 return ERR_PTR(-ENOMEM); 4011 4012 dev = to_mdev(c->ibucontext.device); 4013 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4014 if (err) 4015 goto end; 4016 4017 entry->page_idx = uar_index; 4018 entry->address = uar_index2paddress(dev, uar_index); 4019 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4020 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4021 else 4022 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4023 4024 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4025 if (err) 4026 goto err_insert; 4027 4028 return entry; 4029 4030 err_insert: 4031 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4032 end: 4033 kfree(entry); 4034 return ERR_PTR(err); 4035 } 4036 4037 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4038 struct uverbs_attr_bundle *attrs) 4039 { 4040 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4041 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4042 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4043 struct mlx5_ib_ucontext *c; 4044 struct mlx5_user_mmap_entry *entry; 4045 u64 mmap_offset; 4046 u32 length; 4047 int err; 4048 4049 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4050 if (IS_ERR(c)) 4051 return PTR_ERR(c); 4052 4053 err = uverbs_get_const(&alloc_type, attrs, 4054 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4055 if (err) 4056 return err; 4057 4058 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4059 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4060 return -EOPNOTSUPP; 4061 4062 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4063 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4064 return -EOPNOTSUPP; 4065 4066 entry = alloc_uar_entry(c, alloc_type); 4067 if (IS_ERR(entry)) 4068 return PTR_ERR(entry); 4069 4070 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4071 length = entry->rdma_entry.npages * PAGE_SIZE; 4072 uobj->object = entry; 4073 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4074 4075 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4076 &mmap_offset, sizeof(mmap_offset)); 4077 if (err) 4078 return err; 4079 4080 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4081 &entry->page_idx, sizeof(entry->page_idx)); 4082 if (err) 4083 return err; 4084 4085 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4086 &length, sizeof(length)); 4087 return err; 4088 } 4089 4090 DECLARE_UVERBS_NAMED_METHOD( 4091 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4092 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4093 MLX5_IB_OBJECT_UAR, 4094 UVERBS_ACCESS_NEW, 4095 UA_MANDATORY), 4096 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4097 enum mlx5_ib_uapi_uar_alloc_type, 4098 UA_MANDATORY), 4099 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4100 UVERBS_ATTR_TYPE(u32), 4101 UA_MANDATORY), 4102 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4103 UVERBS_ATTR_TYPE(u32), 4104 UA_MANDATORY), 4105 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4106 UVERBS_ATTR_TYPE(u64), 4107 UA_MANDATORY)); 4108 4109 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4110 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4111 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4112 MLX5_IB_OBJECT_UAR, 4113 UVERBS_ACCESS_DESTROY, 4114 UA_MANDATORY)); 4115 4116 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4117 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4118 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4119 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4120 4121 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4122 mlx5_ib_query_context, 4123 UVERBS_OBJECT_DEVICE, 4124 UVERBS_METHOD_QUERY_CONTEXT, 4125 UVERBS_ATTR_PTR_OUT( 4126 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4127 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4128 dump_fill_mkey), 4129 UA_MANDATORY)); 4130 4131 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4132 mlx5_ib_reg_dmabuf_mr, 4133 UVERBS_OBJECT_MR, 4134 UVERBS_METHOD_REG_DMABUF_MR, 4135 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4136 enum mlx5_ib_uapi_reg_dmabuf_flags, 4137 UA_OPTIONAL)); 4138 4139 static const struct uapi_definition mlx5_ib_defs[] = { 4140 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4141 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4142 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4143 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4144 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4145 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4146 4147 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4148 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4149 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4150 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4151 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4152 {} 4153 }; 4154 4155 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4156 { 4157 mlx5_ib_data_direct_cleanup(dev); 4158 mlx5_ib_cleanup_multiport_master(dev); 4159 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4160 mutex_destroy(&dev->cap_mask_mutex); 4161 WARN_ON(!xa_empty(&dev->sig_mrs)); 4162 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4163 mlx5r_macsec_dealloc_gids(dev); 4164 } 4165 4166 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4167 { 4168 struct mlx5_core_dev *mdev = dev->mdev; 4169 int err, i; 4170 4171 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4172 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4173 dev->ib_dev.dev.parent = mdev->device; 4174 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4175 4176 for (i = 0; i < dev->num_ports; i++) { 4177 spin_lock_init(&dev->port[i].mp.mpi_lock); 4178 dev->port[i].roce.dev = dev; 4179 dev->port[i].roce.native_port_num = i + 1; 4180 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4181 } 4182 4183 err = mlx5r_cmd_query_special_mkeys(dev); 4184 if (err) 4185 return err; 4186 4187 err = mlx5r_macsec_init_gids_and_devlist(dev); 4188 if (err) 4189 return err; 4190 4191 err = mlx5_ib_init_multiport_master(dev); 4192 if (err) 4193 goto err; 4194 4195 err = set_has_smi_cap(dev); 4196 if (err) 4197 goto err_mp; 4198 4199 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4200 if (err) 4201 goto err_mp; 4202 4203 if (mlx5_use_mad_ifc(dev)) 4204 get_ext_port_caps(dev); 4205 4206 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4207 4208 mutex_init(&dev->cap_mask_mutex); 4209 mutex_init(&dev->data_direct_lock); 4210 INIT_LIST_HEAD(&dev->qp_list); 4211 spin_lock_init(&dev->reset_flow_resource_lock); 4212 xa_init(&dev->odp_mkeys); 4213 xa_init(&dev->sig_mrs); 4214 atomic_set(&dev->mkey_var, 0); 4215 4216 spin_lock_init(&dev->dm.lock); 4217 dev->dm.dev = mdev; 4218 err = mlx5_ib_data_direct_init(dev); 4219 if (err) 4220 goto err_mp; 4221 4222 return 0; 4223 err_mp: 4224 mlx5_ib_cleanup_multiport_master(dev); 4225 err: 4226 mlx5r_macsec_dealloc_gids(dev); 4227 return err; 4228 } 4229 4230 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4231 enum rdma_nl_dev_type type, 4232 const char *name); 4233 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4234 4235 static const struct ib_device_ops mlx5_ib_dev_ops = { 4236 .owner = THIS_MODULE, 4237 .driver_id = RDMA_DRIVER_MLX5, 4238 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4239 4240 .add_gid = mlx5_ib_add_gid, 4241 .add_sub_dev = mlx5_ib_add_sub_dev, 4242 .alloc_mr = mlx5_ib_alloc_mr, 4243 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4244 .alloc_pd = mlx5_ib_alloc_pd, 4245 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4246 .attach_mcast = mlx5_ib_mcg_attach, 4247 .check_mr_status = mlx5_ib_check_mr_status, 4248 .create_ah = mlx5_ib_create_ah, 4249 .create_cq = mlx5_ib_create_cq, 4250 .create_qp = mlx5_ib_create_qp, 4251 .create_srq = mlx5_ib_create_srq, 4252 .create_user_ah = mlx5_ib_create_ah, 4253 .dealloc_pd = mlx5_ib_dealloc_pd, 4254 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4255 .del_gid = mlx5_ib_del_gid, 4256 .del_sub_dev = mlx5_ib_del_sub_dev, 4257 .dereg_mr = mlx5_ib_dereg_mr, 4258 .destroy_ah = mlx5_ib_destroy_ah, 4259 .destroy_cq = mlx5_ib_destroy_cq, 4260 .destroy_qp = mlx5_ib_destroy_qp, 4261 .destroy_srq = mlx5_ib_destroy_srq, 4262 .detach_mcast = mlx5_ib_mcg_detach, 4263 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4264 .drain_rq = mlx5_ib_drain_rq, 4265 .drain_sq = mlx5_ib_drain_sq, 4266 .device_group = &mlx5_attr_group, 4267 .get_dev_fw_str = get_dev_fw_str, 4268 .get_dma_mr = mlx5_ib_get_dma_mr, 4269 .get_link_layer = mlx5_ib_port_link_layer, 4270 .map_mr_sg = mlx5_ib_map_mr_sg, 4271 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4272 .mmap = mlx5_ib_mmap, 4273 .mmap_free = mlx5_ib_mmap_free, 4274 .modify_cq = mlx5_ib_modify_cq, 4275 .modify_device = mlx5_ib_modify_device, 4276 .modify_port = mlx5_ib_modify_port, 4277 .modify_qp = mlx5_ib_modify_qp, 4278 .modify_srq = mlx5_ib_modify_srq, 4279 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4280 .poll_cq = mlx5_ib_poll_cq, 4281 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4282 .post_recv = mlx5_ib_post_recv_nodrain, 4283 .post_send = mlx5_ib_post_send_nodrain, 4284 .post_srq_recv = mlx5_ib_post_srq_recv, 4285 .process_mad = mlx5_ib_process_mad, 4286 .query_ah = mlx5_ib_query_ah, 4287 .query_device = mlx5_ib_query_device, 4288 .query_gid = mlx5_ib_query_gid, 4289 .query_pkey = mlx5_ib_query_pkey, 4290 .query_qp = mlx5_ib_query_qp, 4291 .query_srq = mlx5_ib_query_srq, 4292 .query_ucontext = mlx5_ib_query_ucontext, 4293 .reg_user_mr = mlx5_ib_reg_user_mr, 4294 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4295 .req_notify_cq = mlx5_ib_arm_cq, 4296 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4297 .resize_cq = mlx5_ib_resize_cq, 4298 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4299 4300 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4301 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4302 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4303 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4304 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4305 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4306 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4307 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4308 }; 4309 4310 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4311 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4312 }; 4313 4314 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4315 .get_vf_config = mlx5_ib_get_vf_config, 4316 .get_vf_guid = mlx5_ib_get_vf_guid, 4317 .get_vf_stats = mlx5_ib_get_vf_stats, 4318 .set_vf_guid = mlx5_ib_set_vf_guid, 4319 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4320 }; 4321 4322 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4323 .alloc_mw = mlx5_ib_alloc_mw, 4324 .dealloc_mw = mlx5_ib_dealloc_mw, 4325 4326 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4327 }; 4328 4329 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4330 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4331 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4332 4333 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4334 }; 4335 4336 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4337 { 4338 struct mlx5_core_dev *mdev = dev->mdev; 4339 struct mlx5_var_table *var_table = &dev->var_table; 4340 u8 log_doorbell_bar_size; 4341 u8 log_doorbell_stride; 4342 u64 bar_size; 4343 4344 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4345 log_doorbell_bar_size); 4346 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4347 log_doorbell_stride); 4348 var_table->hw_start_addr = dev->mdev->bar_addr + 4349 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4350 doorbell_bar_offset); 4351 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4352 var_table->stride_size = 1ULL << log_doorbell_stride; 4353 var_table->num_var_hw_entries = div_u64(bar_size, 4354 var_table->stride_size); 4355 mutex_init(&var_table->bitmap_lock); 4356 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4357 GFP_KERNEL); 4358 return (var_table->bitmap) ? 0 : -ENOMEM; 4359 } 4360 4361 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4362 { 4363 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4364 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4365 4366 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4367 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4368 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4369 } 4370 4371 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4372 { 4373 int ret; 4374 4375 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4376 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4377 if (ret) 4378 return ret; 4379 } 4380 4381 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4382 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4383 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4384 if (ret) 4385 goto remove_local; 4386 } 4387 4388 return 0; 4389 4390 remove_local: 4391 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4392 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4393 return ret; 4394 } 4395 4396 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4397 { 4398 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4399 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4400 mlx5_ib_cleanup_ucaps(dev); 4401 4402 bitmap_free(dev->var_table.bitmap); 4403 } 4404 4405 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4406 { 4407 struct mlx5_core_dev *mdev = dev->mdev; 4408 int err; 4409 4410 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4411 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4412 ib_set_device_ops(&dev->ib_dev, 4413 &mlx5_ib_dev_ipoib_enhanced_ops); 4414 4415 if (mlx5_core_is_pf(mdev)) 4416 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4417 4418 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4419 4420 if (MLX5_CAP_GEN(mdev, imaicl)) 4421 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4422 4423 if (MLX5_CAP_GEN(mdev, xrc)) 4424 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4425 4426 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4427 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4428 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4429 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4430 4431 if (mdev->st) 4432 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4433 4434 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4435 4436 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4437 dev->ib_dev.driver_def = mlx5_ib_defs; 4438 4439 err = init_node_data(dev); 4440 if (err) 4441 return err; 4442 4443 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4444 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4445 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4446 mutex_init(&dev->lb.mutex); 4447 4448 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4449 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4450 err = mlx5_ib_init_var_table(dev); 4451 if (err) 4452 return err; 4453 } 4454 4455 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4456 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4457 err = mlx5_ib_init_ucaps(dev); 4458 if (err) 4459 return err; 4460 } 4461 4462 dev->ib_dev.use_cq_dim = true; 4463 4464 return 0; 4465 } 4466 4467 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4468 .get_port_immutable = mlx5_port_immutable, 4469 .query_port = mlx5_ib_query_port, 4470 }; 4471 4472 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4473 { 4474 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4475 return 0; 4476 } 4477 4478 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4479 .get_port_immutable = mlx5_port_rep_immutable, 4480 .query_port = mlx5_ib_rep_query_port, 4481 .query_pkey = mlx5_ib_rep_query_pkey, 4482 }; 4483 4484 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4485 { 4486 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4487 return 0; 4488 } 4489 4490 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4491 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4492 .create_wq = mlx5_ib_create_wq, 4493 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4494 .destroy_wq = mlx5_ib_destroy_wq, 4495 .modify_wq = mlx5_ib_modify_wq, 4496 4497 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4498 ib_rwq_ind_tbl), 4499 }; 4500 4501 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4502 { 4503 struct mlx5_core_dev *mdev = dev->mdev; 4504 enum rdma_link_layer ll; 4505 int port_type_cap; 4506 u32 port_num = 0; 4507 int err; 4508 4509 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4510 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4511 4512 if (ll == IB_LINK_LAYER_ETHERNET) { 4513 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4514 4515 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4516 4517 /* Register only for native ports */ 4518 mlx5_mdev_netdev_track(dev, port_num); 4519 4520 err = mlx5_enable_eth(dev); 4521 if (err) 4522 goto cleanup; 4523 } 4524 4525 return 0; 4526 cleanup: 4527 mlx5_mdev_netdev_untrack(dev, port_num); 4528 return err; 4529 } 4530 4531 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4532 { 4533 struct mlx5_core_dev *mdev = dev->mdev; 4534 enum rdma_link_layer ll; 4535 int port_type_cap; 4536 u32 port_num; 4537 4538 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4539 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4540 4541 if (ll == IB_LINK_LAYER_ETHERNET) { 4542 mlx5_disable_eth(dev); 4543 4544 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4545 mlx5_mdev_netdev_untrack(dev, port_num); 4546 } 4547 } 4548 4549 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4550 { 4551 mlx5_ib_init_cong_debugfs(dev, 4552 mlx5_core_native_port_num(dev->mdev) - 1); 4553 return 0; 4554 } 4555 4556 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4557 { 4558 mlx5_ib_cleanup_cong_debugfs(dev, 4559 mlx5_core_native_port_num(dev->mdev) - 1); 4560 } 4561 4562 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4563 { 4564 int err; 4565 4566 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4567 if (err) 4568 return err; 4569 4570 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4571 if (err) 4572 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4573 4574 return err; 4575 } 4576 4577 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4578 { 4579 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4580 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4581 } 4582 4583 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4584 { 4585 const char *name; 4586 4587 if (dev->sub_dev_name) { 4588 name = dev->sub_dev_name; 4589 ib_mark_name_assigned_by_user(&dev->ib_dev); 4590 } else if (!mlx5_lag_is_active(dev->mdev)) 4591 name = "mlx5_%d"; 4592 else 4593 name = "mlx5_bond_%d"; 4594 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4595 } 4596 4597 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4598 { 4599 mlx5_mkey_cache_cleanup(dev); 4600 mlx5r_umr_resource_cleanup(dev); 4601 mlx5r_umr_cleanup(dev); 4602 } 4603 4604 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4605 { 4606 ib_unregister_device(&dev->ib_dev); 4607 } 4608 4609 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4610 { 4611 int ret; 4612 4613 ret = mlx5r_umr_init(dev); 4614 if (ret) 4615 return ret; 4616 4617 ret = mlx5_mkey_cache_init(dev); 4618 if (ret) 4619 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4620 return ret; 4621 } 4622 4623 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4624 { 4625 struct dentry *root; 4626 4627 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4628 return 0; 4629 4630 mutex_init(&dev->delay_drop.lock); 4631 dev->delay_drop.dev = dev; 4632 dev->delay_drop.activate = false; 4633 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4634 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4635 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4636 atomic_set(&dev->delay_drop.events_cnt, 0); 4637 4638 if (!mlx5_debugfs_root) 4639 return 0; 4640 4641 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4642 dev->delay_drop.dir_debugfs = root; 4643 4644 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4645 &dev->delay_drop.events_cnt); 4646 debugfs_create_atomic_t("num_rqs", 0400, root, 4647 &dev->delay_drop.rqs_cnt); 4648 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4649 &fops_delay_drop_timeout); 4650 return 0; 4651 } 4652 4653 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4654 { 4655 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4656 return; 4657 4658 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4659 if (!dev->delay_drop.dir_debugfs) 4660 return; 4661 4662 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4663 dev->delay_drop.dir_debugfs = NULL; 4664 } 4665 4666 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4667 { 4668 struct mlx5_ib_resources *devr = &dev->devr; 4669 int port; 4670 4671 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4672 INIT_WORK(&devr->ports[port].pkey_change_work, 4673 pkey_change_handler); 4674 4675 dev->mdev_events.notifier_call = mlx5_ib_event; 4676 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4677 4678 mlx5r_macsec_event_register(dev); 4679 4680 return 0; 4681 } 4682 4683 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4684 { 4685 struct mlx5_ib_resources *devr = &dev->devr; 4686 int port; 4687 4688 mlx5r_macsec_event_unregister(dev); 4689 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4690 4691 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4692 cancel_work_sync(&devr->ports[port].pkey_change_work); 4693 } 4694 4695 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4696 struct mlx5_data_direct_dev *dev) 4697 { 4698 mutex_lock(&ibdev->data_direct_lock); 4699 ibdev->data_direct_dev = dev; 4700 mutex_unlock(&ibdev->data_direct_lock); 4701 } 4702 4703 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4704 { 4705 mutex_lock(&ibdev->data_direct_lock); 4706 mlx5_ib_revoke_data_direct_mrs(ibdev); 4707 ibdev->data_direct_dev = NULL; 4708 mutex_unlock(&ibdev->data_direct_lock); 4709 } 4710 4711 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4712 const struct mlx5_ib_profile *profile, 4713 int stage) 4714 { 4715 dev->ib_active = false; 4716 4717 /* Number of stages to cleanup */ 4718 while (stage) { 4719 stage--; 4720 if (profile->stage[stage].cleanup) 4721 profile->stage[stage].cleanup(dev); 4722 } 4723 4724 kfree(dev->port); 4725 ib_dealloc_device(&dev->ib_dev); 4726 } 4727 4728 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4729 const struct mlx5_ib_profile *profile) 4730 { 4731 int err; 4732 int i; 4733 4734 dev->profile = profile; 4735 4736 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4737 if (profile->stage[i].init) { 4738 err = profile->stage[i].init(dev); 4739 if (err) 4740 goto err_out; 4741 } 4742 } 4743 4744 dev->ib_active = true; 4745 return 0; 4746 4747 err_out: 4748 /* Clean up stages which were initialized */ 4749 while (i) { 4750 i--; 4751 if (profile->stage[i].cleanup) 4752 profile->stage[i].cleanup(dev); 4753 } 4754 return -ENOMEM; 4755 } 4756 4757 static const struct mlx5_ib_profile pf_profile = { 4758 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4759 mlx5_ib_stage_init_init, 4760 mlx5_ib_stage_init_cleanup), 4761 STAGE_CREATE(MLX5_IB_STAGE_FS, 4762 mlx5_ib_fs_init, 4763 mlx5_ib_fs_cleanup), 4764 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4765 mlx5_ib_stage_caps_init, 4766 mlx5_ib_stage_caps_cleanup), 4767 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4768 mlx5_ib_stage_non_default_cb, 4769 NULL), 4770 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4771 mlx5_ib_roce_init, 4772 mlx5_ib_roce_cleanup), 4773 STAGE_CREATE(MLX5_IB_STAGE_QP, 4774 mlx5_init_qp_table, 4775 mlx5_cleanup_qp_table), 4776 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4777 mlx5_init_srq_table, 4778 mlx5_cleanup_srq_table), 4779 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4780 mlx5_ib_dev_res_init, 4781 mlx5_ib_dev_res_cleanup), 4782 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4783 mlx5_ib_odp_init_one, 4784 mlx5_ib_odp_cleanup_one), 4785 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4786 mlx5_ib_counters_init, 4787 mlx5_ib_counters_cleanup), 4788 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4789 mlx5_ib_stage_cong_debugfs_init, 4790 mlx5_ib_stage_cong_debugfs_cleanup), 4791 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4792 mlx5_ib_stage_bfrag_init, 4793 mlx5_ib_stage_bfrag_cleanup), 4794 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4795 NULL, 4796 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4797 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4798 mlx5_ib_devx_init, 4799 mlx5_ib_devx_cleanup), 4800 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4801 mlx5_ib_stage_ib_reg_init, 4802 mlx5_ib_stage_ib_reg_cleanup), 4803 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4804 mlx5_ib_stage_dev_notifier_init, 4805 mlx5_ib_stage_dev_notifier_cleanup), 4806 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4807 mlx5_ib_stage_post_ib_reg_umr_init, 4808 NULL), 4809 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4810 mlx5_ib_stage_delay_drop_init, 4811 mlx5_ib_stage_delay_drop_cleanup), 4812 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4813 mlx5_ib_restrack_init, 4814 NULL), 4815 }; 4816 4817 const struct mlx5_ib_profile raw_eth_profile = { 4818 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4819 mlx5_ib_stage_init_init, 4820 mlx5_ib_stage_init_cleanup), 4821 STAGE_CREATE(MLX5_IB_STAGE_FS, 4822 mlx5_ib_fs_init, 4823 mlx5_ib_fs_cleanup), 4824 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4825 mlx5_ib_stage_caps_init, 4826 mlx5_ib_stage_caps_cleanup), 4827 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4828 mlx5_ib_stage_raw_eth_non_default_cb, 4829 NULL), 4830 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4831 mlx5_ib_roce_init, 4832 mlx5_ib_roce_cleanup), 4833 STAGE_CREATE(MLX5_IB_STAGE_QP, 4834 mlx5_init_qp_table, 4835 mlx5_cleanup_qp_table), 4836 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4837 mlx5_init_srq_table, 4838 mlx5_cleanup_srq_table), 4839 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4840 mlx5_ib_dev_res_init, 4841 mlx5_ib_dev_res_cleanup), 4842 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4843 mlx5_ib_counters_init, 4844 mlx5_ib_counters_cleanup), 4845 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4846 mlx5_ib_stage_cong_debugfs_init, 4847 mlx5_ib_stage_cong_debugfs_cleanup), 4848 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4849 mlx5_ib_stage_bfrag_init, 4850 mlx5_ib_stage_bfrag_cleanup), 4851 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4852 NULL, 4853 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4854 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4855 mlx5_ib_devx_init, 4856 mlx5_ib_devx_cleanup), 4857 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4858 mlx5_ib_stage_ib_reg_init, 4859 mlx5_ib_stage_ib_reg_cleanup), 4860 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4861 mlx5_ib_stage_dev_notifier_init, 4862 mlx5_ib_stage_dev_notifier_cleanup), 4863 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4864 mlx5_ib_stage_post_ib_reg_umr_init, 4865 NULL), 4866 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4867 mlx5_ib_stage_delay_drop_init, 4868 mlx5_ib_stage_delay_drop_cleanup), 4869 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4870 mlx5_ib_restrack_init, 4871 NULL), 4872 }; 4873 4874 static const struct mlx5_ib_profile plane_profile = { 4875 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4876 mlx5_ib_stage_init_init, 4877 mlx5_ib_stage_init_cleanup), 4878 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4879 mlx5_ib_stage_caps_init, 4880 mlx5_ib_stage_caps_cleanup), 4881 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4882 mlx5_ib_stage_non_default_cb, 4883 NULL), 4884 STAGE_CREATE(MLX5_IB_STAGE_QP, 4885 mlx5_init_qp_table, 4886 mlx5_cleanup_qp_table), 4887 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4888 mlx5_init_srq_table, 4889 mlx5_cleanup_srq_table), 4890 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4891 mlx5_ib_dev_res_init, 4892 mlx5_ib_dev_res_cleanup), 4893 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4894 mlx5_ib_stage_bfrag_init, 4895 mlx5_ib_stage_bfrag_cleanup), 4896 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4897 mlx5_ib_stage_ib_reg_init, 4898 mlx5_ib_stage_ib_reg_cleanup), 4899 }; 4900 4901 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4902 enum rdma_nl_dev_type type, 4903 const char *name) 4904 { 4905 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 4906 enum rdma_link_layer ll; 4907 int ret; 4908 4909 if (mparent->smi_dev) 4910 return ERR_PTR(-EEXIST); 4911 4912 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 4913 port_type)); 4914 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 4915 ll != IB_LINK_LAYER_INFINIBAND || 4916 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 4917 return ERR_PTR(-EOPNOTSUPP); 4918 4919 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4920 mlx5_core_net(mparent->mdev)); 4921 if (!mplane) 4922 return ERR_PTR(-ENOMEM); 4923 4924 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 4925 sizeof(*mplane->port), GFP_KERNEL); 4926 if (!mplane->port) { 4927 ret = -ENOMEM; 4928 goto fail_kcalloc; 4929 } 4930 4931 mplane->ib_dev.type = type; 4932 mplane->mdev = mparent->mdev; 4933 mplane->num_ports = mparent->num_plane; 4934 mplane->sub_dev_name = name; 4935 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 4936 4937 ret = __mlx5_ib_add(mplane, &plane_profile); 4938 if (ret) 4939 goto fail_ib_add; 4940 4941 mparent->smi_dev = mplane; 4942 return &mplane->ib_dev; 4943 4944 fail_ib_add: 4945 kfree(mplane->port); 4946 fail_kcalloc: 4947 ib_dealloc_device(&mplane->ib_dev); 4948 return ERR_PTR(ret); 4949 } 4950 4951 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 4952 { 4953 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 4954 4955 to_mdev(sub_dev->parent)->smi_dev = NULL; 4956 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 4957 } 4958 4959 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4960 const struct auxiliary_device_id *id) 4961 { 4962 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4963 struct mlx5_core_dev *mdev = idev->mdev; 4964 struct mlx5_ib_multiport_info *mpi; 4965 struct mlx5_ib_dev *dev; 4966 bool bound = false; 4967 int err; 4968 4969 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4970 if (!mpi) 4971 return -ENOMEM; 4972 4973 mpi->mdev = mdev; 4974 err = mlx5_query_nic_vport_system_image_guid(mdev, 4975 &mpi->sys_image_guid); 4976 if (err) { 4977 kfree(mpi); 4978 return err; 4979 } 4980 4981 mutex_lock(&mlx5_ib_multiport_mutex); 4982 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4983 if (dev->sys_image_guid == mpi->sys_image_guid && 4984 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 4985 bound = mlx5_ib_bind_slave_port(dev, mpi); 4986 4987 if (bound) { 4988 rdma_roce_rescan_device(&dev->ib_dev); 4989 mpi->ibdev->ib_active = true; 4990 break; 4991 } 4992 } 4993 4994 if (!bound) { 4995 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4996 dev_dbg(mdev->device, 4997 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4998 } 4999 mutex_unlock(&mlx5_ib_multiport_mutex); 5000 5001 auxiliary_set_drvdata(adev, mpi); 5002 return 0; 5003 } 5004 5005 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5006 { 5007 struct mlx5_ib_multiport_info *mpi; 5008 5009 mpi = auxiliary_get_drvdata(adev); 5010 mutex_lock(&mlx5_ib_multiport_mutex); 5011 if (mpi->ibdev) 5012 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5013 else 5014 list_del(&mpi->list); 5015 mutex_unlock(&mlx5_ib_multiport_mutex); 5016 kfree(mpi); 5017 } 5018 5019 static int mlx5r_probe(struct auxiliary_device *adev, 5020 const struct auxiliary_device_id *id) 5021 { 5022 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5023 struct mlx5_core_dev *mdev = idev->mdev; 5024 const struct mlx5_ib_profile *profile; 5025 int port_type_cap, num_ports, ret; 5026 enum rdma_link_layer ll; 5027 struct mlx5_ib_dev *dev; 5028 5029 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5030 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5031 5032 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5033 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5034 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5035 mlx5_core_net(mdev)); 5036 if (!dev) 5037 return -ENOMEM; 5038 5039 if (ll == IB_LINK_LAYER_INFINIBAND) { 5040 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5041 if (ret) 5042 goto fail; 5043 } 5044 5045 dev->port = kcalloc(num_ports, sizeof(*dev->port), 5046 GFP_KERNEL); 5047 if (!dev->port) { 5048 ret = -ENOMEM; 5049 goto fail; 5050 } 5051 5052 dev->mdev = mdev; 5053 dev->num_ports = num_ports; 5054 dev->ib_dev.phys_port_cnt = num_ports; 5055 5056 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5057 profile = &raw_eth_profile; 5058 else 5059 profile = &pf_profile; 5060 5061 ret = __mlx5_ib_add(dev, profile); 5062 if (ret) 5063 goto fail_ib_add; 5064 5065 auxiliary_set_drvdata(adev, dev); 5066 return 0; 5067 5068 fail_ib_add: 5069 kfree(dev->port); 5070 fail: 5071 ib_dealloc_device(&dev->ib_dev); 5072 return ret; 5073 } 5074 5075 static void mlx5r_remove(struct auxiliary_device *adev) 5076 { 5077 struct mlx5_ib_dev *dev; 5078 5079 dev = auxiliary_get_drvdata(adev); 5080 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5081 } 5082 5083 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5084 { .name = MLX5_ADEV_NAME ".multiport", }, 5085 {}, 5086 }; 5087 5088 static const struct auxiliary_device_id mlx5r_id_table[] = { 5089 { .name = MLX5_ADEV_NAME ".rdma", }, 5090 {}, 5091 }; 5092 5093 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5094 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5095 5096 static struct auxiliary_driver mlx5r_mp_driver = { 5097 .name = "multiport", 5098 .probe = mlx5r_mp_probe, 5099 .remove = mlx5r_mp_remove, 5100 .id_table = mlx5r_mp_id_table, 5101 }; 5102 5103 static struct auxiliary_driver mlx5r_driver = { 5104 .name = "rdma", 5105 .probe = mlx5r_probe, 5106 .remove = mlx5r_remove, 5107 .id_table = mlx5r_id_table, 5108 }; 5109 5110 static int __init mlx5_ib_init(void) 5111 { 5112 int ret; 5113 5114 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 5115 if (!xlt_emergency_page) 5116 return -ENOMEM; 5117 5118 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5119 if (!mlx5_ib_event_wq) { 5120 free_page((unsigned long)xlt_emergency_page); 5121 return -ENOMEM; 5122 } 5123 5124 ret = mlx5_ib_qp_event_init(); 5125 if (ret) 5126 goto qp_event_err; 5127 5128 mlx5_ib_odp_init(); 5129 ret = mlx5r_rep_init(); 5130 if (ret) 5131 goto rep_err; 5132 ret = mlx5_data_direct_driver_register(); 5133 if (ret) 5134 goto dd_err; 5135 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5136 if (ret) 5137 goto mp_err; 5138 ret = auxiliary_driver_register(&mlx5r_driver); 5139 if (ret) 5140 goto drv_err; 5141 5142 return 0; 5143 5144 drv_err: 5145 auxiliary_driver_unregister(&mlx5r_mp_driver); 5146 mp_err: 5147 mlx5_data_direct_driver_unregister(); 5148 dd_err: 5149 mlx5r_rep_cleanup(); 5150 rep_err: 5151 mlx5_ib_qp_event_cleanup(); 5152 qp_event_err: 5153 destroy_workqueue(mlx5_ib_event_wq); 5154 free_page((unsigned long)xlt_emergency_page); 5155 return ret; 5156 } 5157 5158 static void __exit mlx5_ib_cleanup(void) 5159 { 5160 mlx5_data_direct_driver_unregister(); 5161 auxiliary_driver_unregister(&mlx5r_driver); 5162 auxiliary_driver_unregister(&mlx5r_mp_driver); 5163 mlx5r_rep_cleanup(); 5164 5165 mlx5_ib_qp_event_cleanup(); 5166 destroy_workqueue(mlx5_ib_event_wq); 5167 free_page((unsigned long)xlt_emergency_page); 5168 } 5169 5170 module_init(mlx5_ib_init); 5171 module_exit(mlx5_ib_cleanup); 5172