1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/mlx5/driver.h> 28 #include <linux/list.h> 29 #include <rdma/ib_smi.h> 30 #include <rdma/ib_umem_odp.h> 31 #include <rdma/lag.h> 32 #include <linux/in.h> 33 #include <linux/etherdevice.h> 34 #include "mlx5_ib.h" 35 #include "ib_rep.h" 36 #include "cmd.h" 37 #include "devx.h" 38 #include "dm.h" 39 #include "fs.h" 40 #include "srq.h" 41 #include "qp.h" 42 #include "wr.h" 43 #include "restrack.h" 44 #include "counters.h" 45 #include "umr.h" 46 #include <rdma/uverbs_std_types.h> 47 #include <rdma/uverbs_ioctl.h> 48 #include <rdma/mlx5_user_ioctl_verbs.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 #include "macsec.h" 51 52 #define UVERBS_MODULE_NAME mlx5_ib 53 #include <rdma/uverbs_named_ioctl.h> 54 55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 56 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 57 MODULE_LICENSE("Dual BSD/GPL"); 58 59 struct mlx5_ib_event_work { 60 struct work_struct work; 61 union { 62 struct mlx5_ib_dev *dev; 63 struct mlx5_ib_multiport_info *mpi; 64 }; 65 bool is_slave; 66 unsigned int event; 67 void *param; 68 }; 69 70 enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72 }; 73 74 static struct workqueue_struct *mlx5_ib_event_wq; 75 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 76 static LIST_HEAD(mlx5_ib_dev_list); 77 /* 78 * This mutex should be held when accessing either of the above lists 79 */ 80 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 81 82 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 83 { 84 struct mlx5_ib_dev *dev; 85 86 mutex_lock(&mlx5_ib_multiport_mutex); 87 dev = mpi->ibdev; 88 mutex_unlock(&mlx5_ib_multiport_mutex); 89 return dev; 90 } 91 92 static enum rdma_link_layer 93 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 94 { 95 switch (port_type_cap) { 96 case MLX5_CAP_PORT_TYPE_IB: 97 return IB_LINK_LAYER_INFINIBAND; 98 case MLX5_CAP_PORT_TYPE_ETH: 99 return IB_LINK_LAYER_ETHERNET; 100 default: 101 return IB_LINK_LAYER_UNSPECIFIED; 102 } 103 } 104 105 static enum rdma_link_layer 106 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 107 { 108 struct mlx5_ib_dev *dev = to_mdev(device); 109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 110 111 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 112 } 113 114 static int get_port_state(struct ib_device *ibdev, 115 u32 port_num, 116 enum ib_port_state *state) 117 { 118 struct ib_port_attr attr; 119 int ret; 120 121 memset(&attr, 0, sizeof(attr)); 122 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 123 if (!ret) 124 *state = attr.state; 125 return ret; 126 } 127 128 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 129 struct net_device *ndev, 130 struct net_device *upper, 131 u32 *port_num) 132 { 133 struct net_device *rep_ndev; 134 struct mlx5_ib_port *port; 135 int i; 136 137 for (i = 0; i < dev->num_ports; i++) { 138 port = &dev->port[i]; 139 if (!port->rep) 140 continue; 141 142 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 143 *port_num = i + 1; 144 return &port->roce; 145 } 146 147 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 148 continue; 149 150 read_lock(&port->roce.netdev_lock); 151 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 152 port->rep->vport); 153 if (rep_ndev == ndev) { 154 read_unlock(&port->roce.netdev_lock); 155 *port_num = i + 1; 156 return &port->roce; 157 } 158 read_unlock(&port->roce.netdev_lock); 159 } 160 161 return NULL; 162 } 163 164 static int mlx5_netdev_event(struct notifier_block *this, 165 unsigned long event, void *ptr) 166 { 167 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 168 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 169 u32 port_num = roce->native_port_num; 170 struct mlx5_core_dev *mdev; 171 struct mlx5_ib_dev *ibdev; 172 173 ibdev = roce->dev; 174 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 175 if (!mdev) 176 return NOTIFY_DONE; 177 178 switch (event) { 179 case NETDEV_REGISTER: 180 /* Should already be registered during the load */ 181 if (ibdev->is_rep) 182 break; 183 write_lock(&roce->netdev_lock); 184 if (ndev->dev.parent == mdev->device) 185 roce->netdev = ndev; 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_UNREGISTER: 190 /* In case of reps, ib device goes away before the netdevs */ 191 write_lock(&roce->netdev_lock); 192 if (roce->netdev == ndev) 193 roce->netdev = NULL; 194 write_unlock(&roce->netdev_lock); 195 break; 196 197 case NETDEV_CHANGE: 198 case NETDEV_UP: 199 case NETDEV_DOWN: { 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 201 struct net_device *upper = NULL; 202 203 if (lag_ndev) { 204 upper = netdev_master_upper_dev_get(lag_ndev); 205 dev_put(lag_ndev); 206 } 207 208 if (ibdev->is_rep) 209 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 210 if (!roce) 211 return NOTIFY_DONE; 212 if ((upper == ndev || 213 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 214 ibdev->ib_active) { 215 struct ib_event ibev = { }; 216 enum ib_port_state port_state; 217 218 if (get_port_state(&ibdev->ib_dev, port_num, 219 &port_state)) 220 goto done; 221 222 if (roce->last_port_state == port_state) 223 goto done; 224 225 roce->last_port_state = port_state; 226 ibev.device = &ibdev->ib_dev; 227 if (port_state == IB_PORT_DOWN) 228 ibev.event = IB_EVENT_PORT_ERR; 229 else if (port_state == IB_PORT_ACTIVE) 230 ibev.event = IB_EVENT_PORT_ACTIVE; 231 else 232 goto done; 233 234 ibev.element.port_num = port_num; 235 ib_dispatch_event(&ibev); 236 } 237 break; 238 } 239 240 default: 241 break; 242 } 243 done: 244 mlx5_ib_put_native_port_mdev(ibdev, port_num); 245 return NOTIFY_DONE; 246 } 247 248 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 249 u32 port_num) 250 { 251 struct mlx5_ib_dev *ibdev = to_mdev(device); 252 struct net_device *ndev; 253 struct mlx5_core_dev *mdev; 254 255 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 256 if (!mdev) 257 return NULL; 258 259 ndev = mlx5_lag_get_roce_netdev(mdev); 260 if (ndev) 261 goto out; 262 263 /* Ensure ndev does not disappear before we invoke dev_hold() 264 */ 265 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 266 ndev = ibdev->port[port_num - 1].roce.netdev; 267 if (ndev) 268 dev_hold(ndev); 269 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 270 271 out: 272 mlx5_ib_put_native_port_mdev(ibdev, port_num); 273 return ndev; 274 } 275 276 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 277 u32 ib_port_num, 278 u32 *native_port_num) 279 { 280 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 281 ib_port_num); 282 struct mlx5_core_dev *mdev = NULL; 283 struct mlx5_ib_multiport_info *mpi; 284 struct mlx5_ib_port *port; 285 286 if (!mlx5_core_mp_enabled(ibdev->mdev) || 287 ll != IB_LINK_LAYER_ETHERNET) { 288 if (native_port_num) 289 *native_port_num = ib_port_num; 290 return ibdev->mdev; 291 } 292 293 if (native_port_num) 294 *native_port_num = 1; 295 296 port = &ibdev->port[ib_port_num - 1]; 297 spin_lock(&port->mp.mpi_lock); 298 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 299 if (mpi && !mpi->unaffiliate) { 300 mdev = mpi->mdev; 301 /* If it's the master no need to refcount, it'll exist 302 * as long as the ib_dev exists. 303 */ 304 if (!mpi->is_master) 305 mpi->mdev_refcnt++; 306 } 307 spin_unlock(&port->mp.mpi_lock); 308 309 return mdev; 310 } 311 312 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 313 { 314 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 315 port_num); 316 struct mlx5_ib_multiport_info *mpi; 317 struct mlx5_ib_port *port; 318 319 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 320 return; 321 322 port = &ibdev->port[port_num - 1]; 323 324 spin_lock(&port->mp.mpi_lock); 325 mpi = ibdev->port[port_num - 1].mp.mpi; 326 if (mpi->is_master) 327 goto out; 328 329 mpi->mdev_refcnt--; 330 if (mpi->unaffiliate) 331 complete(&mpi->unref_comp); 332 out: 333 spin_unlock(&port->mp.mpi_lock); 334 } 335 336 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 337 u16 *active_speed, u8 *active_width) 338 { 339 switch (eth_proto_oper) { 340 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 342 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 343 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_SDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 352 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 353 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 354 *active_width = IB_WIDTH_1X; 355 *active_speed = IB_SPEED_QDR; 356 break; 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 358 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 359 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 360 *active_width = IB_WIDTH_1X; 361 *active_speed = IB_SPEED_EDR; 362 break; 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 365 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 366 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_QDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 371 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 372 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 373 *active_width = IB_WIDTH_1X; 374 *active_speed = IB_SPEED_HDR; 375 break; 376 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 377 *active_width = IB_WIDTH_4X; 378 *active_speed = IB_SPEED_FDR; 379 break; 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 382 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 383 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 384 *active_width = IB_WIDTH_4X; 385 *active_speed = IB_SPEED_EDR; 386 break; 387 default: 388 return -EINVAL; 389 } 390 391 return 0; 392 } 393 394 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 395 u8 *active_width) 396 { 397 switch (eth_proto_oper) { 398 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 399 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 400 *active_width = IB_WIDTH_1X; 401 *active_speed = IB_SPEED_SDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_DDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 408 *active_width = IB_WIDTH_1X; 409 *active_speed = IB_SPEED_QDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 412 *active_width = IB_WIDTH_4X; 413 *active_speed = IB_SPEED_QDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 416 *active_width = IB_WIDTH_1X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_EDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_HDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_EDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_HDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 436 *active_width = IB_WIDTH_1X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 440 *active_width = IB_WIDTH_4X; 441 *active_speed = IB_SPEED_HDR; 442 break; 443 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 444 *active_width = IB_WIDTH_2X; 445 *active_speed = IB_SPEED_NDR; 446 break; 447 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 448 *active_width = IB_WIDTH_8X; 449 *active_speed = IB_SPEED_HDR; 450 break; 451 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 452 *active_width = IB_WIDTH_4X; 453 *active_speed = IB_SPEED_NDR; 454 break; 455 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 456 *active_width = IB_WIDTH_8X; 457 *active_speed = IB_SPEED_NDR; 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 return 0; 464 } 465 466 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 467 u8 *active_width, bool ext) 468 { 469 return ext ? 470 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 471 active_width) : 472 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 473 active_width); 474 } 475 476 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 477 struct ib_port_attr *props) 478 { 479 struct mlx5_ib_dev *dev = to_mdev(device); 480 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 481 struct mlx5_core_dev *mdev; 482 struct net_device *ndev, *upper; 483 enum ib_mtu ndev_ib_mtu; 484 bool put_mdev = true; 485 u32 eth_prot_oper; 486 u32 mdev_port_num; 487 bool ext; 488 int err; 489 490 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 491 if (!mdev) { 492 /* This means the port isn't affiliated yet. Get the 493 * info for the master port instead. 494 */ 495 put_mdev = false; 496 mdev = dev->mdev; 497 mdev_port_num = 1; 498 port_num = 1; 499 } 500 501 /* Possible bad flows are checked before filling out props so in case 502 * of an error it will still be zeroed out. 503 * Use native port in case of reps 504 */ 505 if (dev->is_rep) 506 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 507 1); 508 else 509 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 510 mdev_port_num); 511 if (err) 512 goto out; 513 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 514 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 515 516 props->active_width = IB_WIDTH_4X; 517 props->active_speed = IB_SPEED_QDR; 518 519 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 520 &props->active_width, ext); 521 522 if (!dev->is_rep && dev->mdev->roce.roce_en) { 523 u16 qkey_viol_cntr; 524 525 props->port_cap_flags |= IB_PORT_CM_SUP; 526 props->ip_gids = true; 527 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 528 roce_address_table_size); 529 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 530 props->qkey_viol_cntr = qkey_viol_cntr; 531 } 532 props->max_mtu = IB_MTU_4096; 533 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 534 props->pkey_tbl_len = 1; 535 props->state = IB_PORT_DOWN; 536 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 537 538 /* If this is a stub query for an unaffiliated port stop here */ 539 if (!put_mdev) 540 goto out; 541 542 ndev = mlx5_ib_get_netdev(device, port_num); 543 if (!ndev) 544 goto out; 545 546 if (dev->lag_active) { 547 rcu_read_lock(); 548 upper = netdev_master_upper_dev_get_rcu(ndev); 549 if (upper) { 550 dev_put(ndev); 551 ndev = upper; 552 dev_hold(ndev); 553 } 554 rcu_read_unlock(); 555 } 556 557 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 558 props->state = IB_PORT_ACTIVE; 559 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 560 } 561 562 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 563 564 dev_put(ndev); 565 566 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 567 out: 568 if (put_mdev) 569 mlx5_ib_put_native_port_mdev(dev, port_num); 570 return err; 571 } 572 573 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 574 unsigned int index, const union ib_gid *gid, 575 const struct ib_gid_attr *attr) 576 { 577 enum ib_gid_type gid_type; 578 u16 vlan_id = 0xffff; 579 u8 roce_version = 0; 580 u8 roce_l3_type = 0; 581 u8 mac[ETH_ALEN]; 582 int ret; 583 584 gid_type = attr->gid_type; 585 if (gid) { 586 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 587 if (ret) 588 return ret; 589 } 590 591 switch (gid_type) { 592 case IB_GID_TYPE_ROCE: 593 roce_version = MLX5_ROCE_VERSION_1; 594 break; 595 case IB_GID_TYPE_ROCE_UDP_ENCAP: 596 roce_version = MLX5_ROCE_VERSION_2; 597 if (gid && ipv6_addr_v4mapped((void *)gid)) 598 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 599 else 600 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 601 break; 602 603 default: 604 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 605 } 606 607 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 608 roce_l3_type, gid->raw, mac, 609 vlan_id < VLAN_CFI_MASK, vlan_id, 610 port_num); 611 } 612 613 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 614 __always_unused void **context) 615 { 616 int ret; 617 618 ret = mlx5r_add_gid_macsec_operations(attr); 619 if (ret) 620 return ret; 621 622 return set_roce_addr(to_mdev(attr->device), attr->port_num, 623 attr->index, &attr->gid, attr); 624 } 625 626 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 627 __always_unused void **context) 628 { 629 int ret; 630 631 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 632 attr->index, NULL, attr); 633 if (ret) 634 return ret; 635 636 mlx5r_del_gid_macsec_operations(attr); 637 return 0; 638 } 639 640 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 641 const struct ib_gid_attr *attr) 642 { 643 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 644 return 0; 645 646 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 647 } 648 649 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 650 { 651 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 652 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 653 return 0; 654 } 655 656 enum { 657 MLX5_VPORT_ACCESS_METHOD_MAD, 658 MLX5_VPORT_ACCESS_METHOD_HCA, 659 MLX5_VPORT_ACCESS_METHOD_NIC, 660 }; 661 662 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 663 { 664 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 665 return MLX5_VPORT_ACCESS_METHOD_MAD; 666 667 if (mlx5_ib_port_link_layer(ibdev, 1) == 668 IB_LINK_LAYER_ETHERNET) 669 return MLX5_VPORT_ACCESS_METHOD_NIC; 670 671 return MLX5_VPORT_ACCESS_METHOD_HCA; 672 } 673 674 static void get_atomic_caps(struct mlx5_ib_dev *dev, 675 u8 atomic_size_qp, 676 struct ib_device_attr *props) 677 { 678 u8 tmp; 679 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 680 u8 atomic_req_8B_endianness_mode = 681 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 682 683 /* Check if HW supports 8 bytes standard atomic operations and capable 684 * of host endianness respond 685 */ 686 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 687 if (((atomic_operations & tmp) == tmp) && 688 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 689 (atomic_req_8B_endianness_mode)) { 690 props->atomic_cap = IB_ATOMIC_HCA; 691 } else { 692 props->atomic_cap = IB_ATOMIC_NONE; 693 } 694 } 695 696 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 697 struct ib_device_attr *props) 698 { 699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 700 701 get_atomic_caps(dev, atomic_size_qp, props); 702 } 703 704 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 705 __be64 *sys_image_guid) 706 { 707 struct mlx5_ib_dev *dev = to_mdev(ibdev); 708 struct mlx5_core_dev *mdev = dev->mdev; 709 u64 tmp; 710 int err; 711 712 switch (mlx5_get_vport_access_method(ibdev)) { 713 case MLX5_VPORT_ACCESS_METHOD_MAD: 714 return mlx5_query_mad_ifc_system_image_guid(ibdev, 715 sys_image_guid); 716 717 case MLX5_VPORT_ACCESS_METHOD_HCA: 718 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 719 break; 720 721 case MLX5_VPORT_ACCESS_METHOD_NIC: 722 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 723 break; 724 725 default: 726 return -EINVAL; 727 } 728 729 if (!err) 730 *sys_image_guid = cpu_to_be64(tmp); 731 732 return err; 733 734 } 735 736 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 737 u16 *max_pkeys) 738 { 739 struct mlx5_ib_dev *dev = to_mdev(ibdev); 740 struct mlx5_core_dev *mdev = dev->mdev; 741 742 switch (mlx5_get_vport_access_method(ibdev)) { 743 case MLX5_VPORT_ACCESS_METHOD_MAD: 744 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 745 746 case MLX5_VPORT_ACCESS_METHOD_HCA: 747 case MLX5_VPORT_ACCESS_METHOD_NIC: 748 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 749 pkey_table_size)); 750 return 0; 751 752 default: 753 return -EINVAL; 754 } 755 } 756 757 static int mlx5_query_vendor_id(struct ib_device *ibdev, 758 u32 *vendor_id) 759 { 760 struct mlx5_ib_dev *dev = to_mdev(ibdev); 761 762 switch (mlx5_get_vport_access_method(ibdev)) { 763 case MLX5_VPORT_ACCESS_METHOD_MAD: 764 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 765 766 case MLX5_VPORT_ACCESS_METHOD_HCA: 767 case MLX5_VPORT_ACCESS_METHOD_NIC: 768 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 769 770 default: 771 return -EINVAL; 772 } 773 } 774 775 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 776 __be64 *node_guid) 777 { 778 u64 tmp; 779 int err; 780 781 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 782 case MLX5_VPORT_ACCESS_METHOD_MAD: 783 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 784 785 case MLX5_VPORT_ACCESS_METHOD_HCA: 786 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 787 break; 788 789 case MLX5_VPORT_ACCESS_METHOD_NIC: 790 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 791 break; 792 793 default: 794 return -EINVAL; 795 } 796 797 if (!err) 798 *node_guid = cpu_to_be64(tmp); 799 800 return err; 801 } 802 803 struct mlx5_reg_node_desc { 804 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 805 }; 806 807 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 808 { 809 struct mlx5_reg_node_desc in; 810 811 if (mlx5_use_mad_ifc(dev)) 812 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 813 814 memset(&in, 0, sizeof(in)); 815 816 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 817 sizeof(struct mlx5_reg_node_desc), 818 MLX5_REG_NODE_DESC, 0, 0); 819 } 820 821 static int mlx5_ib_query_device(struct ib_device *ibdev, 822 struct ib_device_attr *props, 823 struct ib_udata *uhw) 824 { 825 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 826 struct mlx5_ib_dev *dev = to_mdev(ibdev); 827 struct mlx5_core_dev *mdev = dev->mdev; 828 int err = -ENOMEM; 829 int max_sq_desc; 830 int max_rq_sg; 831 int max_sq_sg; 832 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 833 bool raw_support = !mlx5_core_mp_enabled(mdev); 834 struct mlx5_ib_query_device_resp resp = {}; 835 size_t resp_len; 836 u64 max_tso; 837 838 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 839 if (uhw_outlen && uhw_outlen < resp_len) 840 return -EINVAL; 841 842 resp.response_length = resp_len; 843 844 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 845 return -EINVAL; 846 847 memset(props, 0, sizeof(*props)); 848 err = mlx5_query_system_image_guid(ibdev, 849 &props->sys_image_guid); 850 if (err) 851 return err; 852 853 props->max_pkeys = dev->pkey_table_len; 854 855 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 856 if (err) 857 return err; 858 859 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 860 (fw_rev_min(dev->mdev) << 16) | 861 fw_rev_sub(dev->mdev); 862 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 863 IB_DEVICE_PORT_ACTIVE_EVENT | 864 IB_DEVICE_SYS_IMAGE_GUID | 865 IB_DEVICE_RC_RNR_NAK_GEN; 866 867 if (MLX5_CAP_GEN(mdev, pkv)) 868 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 869 if (MLX5_CAP_GEN(mdev, qkv)) 870 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 871 if (MLX5_CAP_GEN(mdev, apm)) 872 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 873 if (MLX5_CAP_GEN(mdev, xrc)) 874 props->device_cap_flags |= IB_DEVICE_XRC; 875 if (MLX5_CAP_GEN(mdev, imaicl)) { 876 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 877 IB_DEVICE_MEM_WINDOW_TYPE_2B; 878 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 879 /* We support 'Gappy' memory registration too */ 880 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 881 } 882 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 883 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 884 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 885 if (MLX5_CAP_GEN(mdev, sho)) { 886 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 887 /* At this stage no support for signature handover */ 888 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 889 IB_PROT_T10DIF_TYPE_2 | 890 IB_PROT_T10DIF_TYPE_3; 891 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 892 IB_GUARD_T10DIF_CSUM; 893 } 894 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 895 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 896 897 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 898 if (MLX5_CAP_ETH(mdev, csum_cap)) { 899 /* Legacy bit to support old userspace libraries */ 900 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 901 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 902 } 903 904 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 905 props->raw_packet_caps |= 906 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 907 908 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 909 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 910 if (max_tso) { 911 resp.tso_caps.max_tso = 1 << max_tso; 912 resp.tso_caps.supported_qpts |= 913 1 << IB_QPT_RAW_PACKET; 914 resp.response_length += sizeof(resp.tso_caps); 915 } 916 } 917 918 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 919 resp.rss_caps.rx_hash_function = 920 MLX5_RX_HASH_FUNC_TOEPLITZ; 921 resp.rss_caps.rx_hash_fields_mask = 922 MLX5_RX_HASH_SRC_IPV4 | 923 MLX5_RX_HASH_DST_IPV4 | 924 MLX5_RX_HASH_SRC_IPV6 | 925 MLX5_RX_HASH_DST_IPV6 | 926 MLX5_RX_HASH_SRC_PORT_TCP | 927 MLX5_RX_HASH_DST_PORT_TCP | 928 MLX5_RX_HASH_SRC_PORT_UDP | 929 MLX5_RX_HASH_DST_PORT_UDP | 930 MLX5_RX_HASH_INNER; 931 resp.response_length += sizeof(resp.rss_caps); 932 } 933 } else { 934 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 935 resp.response_length += sizeof(resp.tso_caps); 936 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 937 resp.response_length += sizeof(resp.rss_caps); 938 } 939 940 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 941 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 942 props->kernel_cap_flags |= IBK_UD_TSO; 943 } 944 945 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 946 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 947 raw_support) 948 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 949 950 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 951 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 952 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 953 954 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 955 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 956 raw_support) { 957 /* Legacy bit to support old userspace libraries */ 958 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 959 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 960 } 961 962 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 963 props->max_dm_size = 964 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 965 } 966 967 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 968 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 969 970 if (MLX5_CAP_GEN(mdev, end_pad)) 971 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 972 973 props->vendor_part_id = mdev->pdev->device; 974 props->hw_ver = mdev->pdev->revision; 975 976 props->max_mr_size = ~0ull; 977 props->page_size_cap = ~(min_page_size - 1); 978 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 979 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 980 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 981 sizeof(struct mlx5_wqe_data_seg); 982 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 983 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 984 sizeof(struct mlx5_wqe_raddr_seg)) / 985 sizeof(struct mlx5_wqe_data_seg); 986 props->max_send_sge = max_sq_sg; 987 props->max_recv_sge = max_rq_sg; 988 props->max_sge_rd = MLX5_MAX_SGE_RD; 989 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 990 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 991 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 992 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 993 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 994 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 995 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 996 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 997 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 998 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 999 props->max_srq_sge = max_rq_sg - 1; 1000 props->max_fast_reg_page_list_len = 1001 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1002 props->max_pi_fast_reg_page_list_len = 1003 props->max_fast_reg_page_list_len / 2; 1004 props->max_sgl_rd = 1005 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1006 get_atomic_caps_qp(dev, props); 1007 props->masked_atomic_cap = IB_ATOMIC_NONE; 1008 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1009 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1010 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1011 props->max_mcast_grp; 1012 props->max_ah = INT_MAX; 1013 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1014 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1015 1016 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1017 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1018 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1019 props->odp_caps = dev->odp_caps; 1020 if (!uhw) { 1021 /* ODP for kernel QPs is not implemented for receive 1022 * WQEs and SRQ WQEs 1023 */ 1024 props->odp_caps.per_transport_caps.rc_odp_caps &= 1025 ~(IB_ODP_SUPPORT_READ | 1026 IB_ODP_SUPPORT_SRQ_RECV); 1027 props->odp_caps.per_transport_caps.uc_odp_caps &= 1028 ~(IB_ODP_SUPPORT_READ | 1029 IB_ODP_SUPPORT_SRQ_RECV); 1030 props->odp_caps.per_transport_caps.ud_odp_caps &= 1031 ~(IB_ODP_SUPPORT_READ | 1032 IB_ODP_SUPPORT_SRQ_RECV); 1033 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1034 ~(IB_ODP_SUPPORT_READ | 1035 IB_ODP_SUPPORT_SRQ_RECV); 1036 } 1037 } 1038 1039 if (mlx5_core_is_vf(mdev)) 1040 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1041 1042 if (mlx5_ib_port_link_layer(ibdev, 1) == 1043 IB_LINK_LAYER_ETHERNET && raw_support) { 1044 props->rss_caps.max_rwq_indirection_tables = 1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1046 props->rss_caps.max_rwq_indirection_table_size = 1047 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1048 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1049 props->max_wq_type_rq = 1050 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1051 } 1052 1053 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1054 props->tm_caps.max_num_tags = 1055 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1056 props->tm_caps.max_ops = 1057 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1058 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1059 } 1060 1061 if (MLX5_CAP_GEN(mdev, tag_matching) && 1062 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1063 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1064 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1065 } 1066 1067 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1068 props->cq_caps.max_cq_moderation_count = 1069 MLX5_MAX_CQ_COUNT; 1070 props->cq_caps.max_cq_moderation_period = 1071 MLX5_MAX_CQ_PERIOD; 1072 } 1073 1074 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1075 resp.response_length += sizeof(resp.cqe_comp_caps); 1076 1077 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1078 resp.cqe_comp_caps.max_num = 1079 MLX5_CAP_GEN(dev->mdev, 1080 cqe_compression_max_num); 1081 1082 resp.cqe_comp_caps.supported_format = 1083 MLX5_IB_CQE_RES_FORMAT_HASH | 1084 MLX5_IB_CQE_RES_FORMAT_CSUM; 1085 1086 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1087 resp.cqe_comp_caps.supported_format |= 1088 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1089 } 1090 } 1091 1092 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1093 raw_support) { 1094 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1095 MLX5_CAP_GEN(mdev, qos)) { 1096 resp.packet_pacing_caps.qp_rate_limit_max = 1097 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1098 resp.packet_pacing_caps.qp_rate_limit_min = 1099 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1100 resp.packet_pacing_caps.supported_qpts |= 1101 1 << IB_QPT_RAW_PACKET; 1102 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1103 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1104 resp.packet_pacing_caps.cap_flags |= 1105 MLX5_IB_PP_SUPPORT_BURST; 1106 } 1107 resp.response_length += sizeof(resp.packet_pacing_caps); 1108 } 1109 1110 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1111 uhw_outlen) { 1112 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1113 resp.mlx5_ib_support_multi_pkt_send_wqes = 1114 MLX5_IB_ALLOW_MPW; 1115 1116 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1117 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1118 MLX5_IB_SUPPORT_EMPW; 1119 1120 resp.response_length += 1121 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1122 } 1123 1124 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1125 resp.response_length += sizeof(resp.flags); 1126 1127 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1128 resp.flags |= 1129 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1130 1131 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1133 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1134 resp.flags |= 1135 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1136 1137 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1138 } 1139 1140 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1141 resp.response_length += sizeof(resp.sw_parsing_caps); 1142 if (MLX5_CAP_ETH(mdev, swp)) { 1143 resp.sw_parsing_caps.sw_parsing_offloads |= 1144 MLX5_IB_SW_PARSING; 1145 1146 if (MLX5_CAP_ETH(mdev, swp_csum)) 1147 resp.sw_parsing_caps.sw_parsing_offloads |= 1148 MLX5_IB_SW_PARSING_CSUM; 1149 1150 if (MLX5_CAP_ETH(mdev, swp_lso)) 1151 resp.sw_parsing_caps.sw_parsing_offloads |= 1152 MLX5_IB_SW_PARSING_LSO; 1153 1154 if (resp.sw_parsing_caps.sw_parsing_offloads) 1155 resp.sw_parsing_caps.supported_qpts = 1156 BIT(IB_QPT_RAW_PACKET); 1157 } 1158 } 1159 1160 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1161 raw_support) { 1162 resp.response_length += sizeof(resp.striding_rq_caps); 1163 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1164 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1165 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1166 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1167 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1168 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1169 resp.striding_rq_caps 1170 .min_single_wqe_log_num_of_strides = 1171 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1172 else 1173 resp.striding_rq_caps 1174 .min_single_wqe_log_num_of_strides = 1175 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1176 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1177 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1178 resp.striding_rq_caps.supported_qpts = 1179 BIT(IB_QPT_RAW_PACKET); 1180 } 1181 } 1182 1183 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1184 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1185 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1186 resp.tunnel_offloads_caps |= 1187 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1188 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1189 resp.tunnel_offloads_caps |= 1190 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1191 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1192 resp.tunnel_offloads_caps |= 1193 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1194 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1195 resp.tunnel_offloads_caps |= 1196 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1197 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1198 resp.tunnel_offloads_caps |= 1199 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1200 } 1201 1202 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1203 resp.response_length += sizeof(resp.dci_streams_caps); 1204 1205 resp.dci_streams_caps.max_log_num_concurent = 1206 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1207 1208 resp.dci_streams_caps.max_log_num_errored = 1209 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1210 } 1211 1212 if (uhw_outlen) { 1213 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1214 1215 if (err) 1216 return err; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1223 u8 *ib_width) 1224 { 1225 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1226 1227 if (active_width & MLX5_PTYS_WIDTH_1X) 1228 *ib_width = IB_WIDTH_1X; 1229 else if (active_width & MLX5_PTYS_WIDTH_2X) 1230 *ib_width = IB_WIDTH_2X; 1231 else if (active_width & MLX5_PTYS_WIDTH_4X) 1232 *ib_width = IB_WIDTH_4X; 1233 else if (active_width & MLX5_PTYS_WIDTH_8X) 1234 *ib_width = IB_WIDTH_8X; 1235 else if (active_width & MLX5_PTYS_WIDTH_12X) 1236 *ib_width = IB_WIDTH_12X; 1237 else { 1238 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1239 active_width); 1240 *ib_width = IB_WIDTH_4X; 1241 } 1242 1243 return; 1244 } 1245 1246 static int mlx5_mtu_to_ib_mtu(int mtu) 1247 { 1248 switch (mtu) { 1249 case 256: return 1; 1250 case 512: return 2; 1251 case 1024: return 3; 1252 case 2048: return 4; 1253 case 4096: return 5; 1254 default: 1255 pr_warn("invalid mtu\n"); 1256 return -1; 1257 } 1258 } 1259 1260 enum ib_max_vl_num { 1261 __IB_MAX_VL_0 = 1, 1262 __IB_MAX_VL_0_1 = 2, 1263 __IB_MAX_VL_0_3 = 3, 1264 __IB_MAX_VL_0_7 = 4, 1265 __IB_MAX_VL_0_14 = 5, 1266 }; 1267 1268 enum mlx5_vl_hw_cap { 1269 MLX5_VL_HW_0 = 1, 1270 MLX5_VL_HW_0_1 = 2, 1271 MLX5_VL_HW_0_2 = 3, 1272 MLX5_VL_HW_0_3 = 4, 1273 MLX5_VL_HW_0_4 = 5, 1274 MLX5_VL_HW_0_5 = 6, 1275 MLX5_VL_HW_0_6 = 7, 1276 MLX5_VL_HW_0_7 = 8, 1277 MLX5_VL_HW_0_14 = 15 1278 }; 1279 1280 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1281 u8 *max_vl_num) 1282 { 1283 switch (vl_hw_cap) { 1284 case MLX5_VL_HW_0: 1285 *max_vl_num = __IB_MAX_VL_0; 1286 break; 1287 case MLX5_VL_HW_0_1: 1288 *max_vl_num = __IB_MAX_VL_0_1; 1289 break; 1290 case MLX5_VL_HW_0_3: 1291 *max_vl_num = __IB_MAX_VL_0_3; 1292 break; 1293 case MLX5_VL_HW_0_7: 1294 *max_vl_num = __IB_MAX_VL_0_7; 1295 break; 1296 case MLX5_VL_HW_0_14: 1297 *max_vl_num = __IB_MAX_VL_0_14; 1298 break; 1299 1300 default: 1301 return -EINVAL; 1302 } 1303 1304 return 0; 1305 } 1306 1307 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1308 struct ib_port_attr *props) 1309 { 1310 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1311 struct mlx5_core_dev *mdev = dev->mdev; 1312 struct mlx5_hca_vport_context *rep; 1313 u16 max_mtu; 1314 u16 oper_mtu; 1315 int err; 1316 u16 ib_link_width_oper; 1317 u8 vl_hw_cap; 1318 1319 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1320 if (!rep) { 1321 err = -ENOMEM; 1322 goto out; 1323 } 1324 1325 /* props being zeroed by the caller, avoid zeroing it here */ 1326 1327 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1328 if (err) 1329 goto out; 1330 1331 props->lid = rep->lid; 1332 props->lmc = rep->lmc; 1333 props->sm_lid = rep->sm_lid; 1334 props->sm_sl = rep->sm_sl; 1335 props->state = rep->vport_state; 1336 props->phys_state = rep->port_physical_state; 1337 props->port_cap_flags = rep->cap_mask1; 1338 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1339 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1340 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1341 props->bad_pkey_cntr = rep->pkey_violation_counter; 1342 props->qkey_viol_cntr = rep->qkey_violation_counter; 1343 props->subnet_timeout = rep->subnet_timeout; 1344 props->init_type_reply = rep->init_type_reply; 1345 1346 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1347 props->port_cap_flags2 = rep->cap_mask2; 1348 1349 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1350 &props->active_speed, port); 1351 if (err) 1352 goto out; 1353 1354 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1355 1356 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1357 1358 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1359 1360 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1361 1362 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1363 1364 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1365 if (err) 1366 goto out; 1367 1368 err = translate_max_vl_num(ibdev, vl_hw_cap, 1369 &props->max_vl_num); 1370 out: 1371 kfree(rep); 1372 return err; 1373 } 1374 1375 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1376 struct ib_port_attr *props) 1377 { 1378 unsigned int count; 1379 int ret; 1380 1381 switch (mlx5_get_vport_access_method(ibdev)) { 1382 case MLX5_VPORT_ACCESS_METHOD_MAD: 1383 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1384 break; 1385 1386 case MLX5_VPORT_ACCESS_METHOD_HCA: 1387 ret = mlx5_query_hca_port(ibdev, port, props); 1388 break; 1389 1390 case MLX5_VPORT_ACCESS_METHOD_NIC: 1391 ret = mlx5_query_port_roce(ibdev, port, props); 1392 break; 1393 1394 default: 1395 ret = -EINVAL; 1396 } 1397 1398 if (!ret && props) { 1399 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1400 struct mlx5_core_dev *mdev; 1401 bool put_mdev = true; 1402 1403 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1404 if (!mdev) { 1405 /* If the port isn't affiliated yet query the master. 1406 * The master and slave will have the same values. 1407 */ 1408 mdev = dev->mdev; 1409 port = 1; 1410 put_mdev = false; 1411 } 1412 count = mlx5_core_reserved_gids_count(mdev); 1413 if (put_mdev) 1414 mlx5_ib_put_native_port_mdev(dev, port); 1415 props->gid_tbl_len -= count; 1416 } 1417 return ret; 1418 } 1419 1420 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1421 struct ib_port_attr *props) 1422 { 1423 return mlx5_query_port_roce(ibdev, port, props); 1424 } 1425 1426 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1427 u16 *pkey) 1428 { 1429 /* Default special Pkey for representor device port as per the 1430 * IB specification 1.3 section 10.9.1.2. 1431 */ 1432 *pkey = 0xffff; 1433 return 0; 1434 } 1435 1436 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1437 union ib_gid *gid) 1438 { 1439 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1440 struct mlx5_core_dev *mdev = dev->mdev; 1441 1442 switch (mlx5_get_vport_access_method(ibdev)) { 1443 case MLX5_VPORT_ACCESS_METHOD_MAD: 1444 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1445 1446 case MLX5_VPORT_ACCESS_METHOD_HCA: 1447 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1448 1449 default: 1450 return -EINVAL; 1451 } 1452 1453 } 1454 1455 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1456 u16 index, u16 *pkey) 1457 { 1458 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1459 struct mlx5_core_dev *mdev; 1460 bool put_mdev = true; 1461 u32 mdev_port_num; 1462 int err; 1463 1464 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1465 if (!mdev) { 1466 /* The port isn't affiliated yet, get the PKey from the master 1467 * port. For RoCE the PKey tables will be the same. 1468 */ 1469 put_mdev = false; 1470 mdev = dev->mdev; 1471 mdev_port_num = 1; 1472 } 1473 1474 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1475 index, pkey); 1476 if (put_mdev) 1477 mlx5_ib_put_native_port_mdev(dev, port); 1478 1479 return err; 1480 } 1481 1482 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1483 u16 *pkey) 1484 { 1485 switch (mlx5_get_vport_access_method(ibdev)) { 1486 case MLX5_VPORT_ACCESS_METHOD_MAD: 1487 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1488 1489 case MLX5_VPORT_ACCESS_METHOD_HCA: 1490 case MLX5_VPORT_ACCESS_METHOD_NIC: 1491 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1492 default: 1493 return -EINVAL; 1494 } 1495 } 1496 1497 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1498 struct ib_device_modify *props) 1499 { 1500 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1501 struct mlx5_reg_node_desc in; 1502 struct mlx5_reg_node_desc out; 1503 int err; 1504 1505 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1506 return -EOPNOTSUPP; 1507 1508 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1509 return 0; 1510 1511 /* 1512 * If possible, pass node desc to FW, so it can generate 1513 * a 144 trap. If cmd fails, just ignore. 1514 */ 1515 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1516 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1517 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1518 if (err) 1519 return err; 1520 1521 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1522 1523 return err; 1524 } 1525 1526 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1527 u32 value) 1528 { 1529 struct mlx5_hca_vport_context ctx = {}; 1530 struct mlx5_core_dev *mdev; 1531 u32 mdev_port_num; 1532 int err; 1533 1534 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1535 if (!mdev) 1536 return -ENODEV; 1537 1538 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1539 if (err) 1540 goto out; 1541 1542 if (~ctx.cap_mask1_perm & mask) { 1543 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1544 mask, ctx.cap_mask1_perm); 1545 err = -EINVAL; 1546 goto out; 1547 } 1548 1549 ctx.cap_mask1 = value; 1550 ctx.cap_mask1_perm = mask; 1551 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1552 0, &ctx); 1553 1554 out: 1555 mlx5_ib_put_native_port_mdev(dev, port_num); 1556 1557 return err; 1558 } 1559 1560 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1561 struct ib_port_modify *props) 1562 { 1563 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1564 struct ib_port_attr attr; 1565 u32 tmp; 1566 int err; 1567 u32 change_mask; 1568 u32 value; 1569 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1570 IB_LINK_LAYER_INFINIBAND); 1571 1572 /* CM layer calls ib_modify_port() regardless of the link layer. For 1573 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1574 */ 1575 if (!is_ib) 1576 return 0; 1577 1578 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1579 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1580 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1581 return set_port_caps_atomic(dev, port, change_mask, value); 1582 } 1583 1584 mutex_lock(&dev->cap_mask_mutex); 1585 1586 err = ib_query_port(ibdev, port, &attr); 1587 if (err) 1588 goto out; 1589 1590 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1591 ~props->clr_port_cap_mask; 1592 1593 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1594 1595 out: 1596 mutex_unlock(&dev->cap_mask_mutex); 1597 return err; 1598 } 1599 1600 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1601 { 1602 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1603 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1604 } 1605 1606 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1607 { 1608 /* Large page with non 4k uar support might limit the dynamic size */ 1609 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1610 return MLX5_MIN_DYN_BFREGS; 1611 1612 return MLX5_MAX_DYN_BFREGS; 1613 } 1614 1615 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1616 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1617 struct mlx5_bfreg_info *bfregi) 1618 { 1619 int uars_per_sys_page; 1620 int bfregs_per_sys_page; 1621 int ref_bfregs = req->total_num_bfregs; 1622 1623 if (req->total_num_bfregs == 0) 1624 return -EINVAL; 1625 1626 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1627 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1628 1629 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1630 return -ENOMEM; 1631 1632 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1633 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1634 /* This holds the required static allocation asked by the user */ 1635 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1636 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1637 return -EINVAL; 1638 1639 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1640 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1641 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1642 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1643 1644 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1645 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1646 lib_uar_4k ? "yes" : "no", ref_bfregs, 1647 req->total_num_bfregs, bfregi->total_num_bfregs, 1648 bfregi->num_sys_pages); 1649 1650 return 0; 1651 } 1652 1653 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1654 { 1655 struct mlx5_bfreg_info *bfregi; 1656 int err; 1657 int i; 1658 1659 bfregi = &context->bfregi; 1660 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1661 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1662 context->devx_uid); 1663 if (err) 1664 goto error; 1665 1666 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1667 } 1668 1669 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1670 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1671 1672 return 0; 1673 1674 error: 1675 for (--i; i >= 0; i--) 1676 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1677 context->devx_uid)) 1678 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1679 1680 return err; 1681 } 1682 1683 static void deallocate_uars(struct mlx5_ib_dev *dev, 1684 struct mlx5_ib_ucontext *context) 1685 { 1686 struct mlx5_bfreg_info *bfregi; 1687 int i; 1688 1689 bfregi = &context->bfregi; 1690 for (i = 0; i < bfregi->num_sys_pages; i++) 1691 if (i < bfregi->num_static_sys_pages || 1692 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1693 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1694 context->devx_uid); 1695 } 1696 1697 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1698 { 1699 int err = 0; 1700 1701 mutex_lock(&dev->lb.mutex); 1702 if (td) 1703 dev->lb.user_td++; 1704 if (qp) 1705 dev->lb.qps++; 1706 1707 if (dev->lb.user_td == 2 || 1708 dev->lb.qps == 1) { 1709 if (!dev->lb.enabled) { 1710 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1711 dev->lb.enabled = true; 1712 } 1713 } 1714 1715 mutex_unlock(&dev->lb.mutex); 1716 1717 return err; 1718 } 1719 1720 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1721 { 1722 mutex_lock(&dev->lb.mutex); 1723 if (td) 1724 dev->lb.user_td--; 1725 if (qp) 1726 dev->lb.qps--; 1727 1728 if (dev->lb.user_td == 1 && 1729 dev->lb.qps == 0) { 1730 if (dev->lb.enabled) { 1731 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1732 dev->lb.enabled = false; 1733 } 1734 } 1735 1736 mutex_unlock(&dev->lb.mutex); 1737 } 1738 1739 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1740 u16 uid) 1741 { 1742 int err; 1743 1744 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1745 return 0; 1746 1747 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1748 if (err) 1749 return err; 1750 1751 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1752 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1753 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1754 return err; 1755 1756 return mlx5_ib_enable_lb(dev, true, false); 1757 } 1758 1759 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1760 u16 uid) 1761 { 1762 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1763 return; 1764 1765 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1766 1767 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1768 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1769 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1770 return; 1771 1772 mlx5_ib_disable_lb(dev, true, false); 1773 } 1774 1775 static int set_ucontext_resp(struct ib_ucontext *uctx, 1776 struct mlx5_ib_alloc_ucontext_resp *resp) 1777 { 1778 struct ib_device *ibdev = uctx->device; 1779 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1780 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1781 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1782 1783 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1784 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1785 resp->comp_mask |= 1786 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1787 } 1788 1789 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1790 if (dev->wc_support) 1791 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1792 log_bf_reg_size); 1793 resp->cache_line_size = cache_line_size(); 1794 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1795 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1796 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1797 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1798 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1799 resp->cqe_version = context->cqe_version; 1800 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1801 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1802 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1803 MLX5_CAP_GEN(dev->mdev, 1804 num_of_uars_per_page) : 1; 1805 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1806 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1807 resp->num_ports = dev->num_ports; 1808 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1809 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1810 1811 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1812 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1813 resp->eth_min_inline++; 1814 } 1815 1816 if (dev->mdev->clock_info) 1817 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1818 1819 /* 1820 * We don't want to expose information from the PCI bar that is located 1821 * after 4096 bytes, so if the arch only supports larger pages, let's 1822 * pretend we don't support reading the HCA's core clock. This is also 1823 * forced by mmap function. 1824 */ 1825 if (PAGE_SIZE <= 4096) { 1826 resp->comp_mask |= 1827 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1828 resp->hca_core_clock_offset = 1829 offsetof(struct mlx5_init_seg, 1830 internal_timer_h) % PAGE_SIZE; 1831 } 1832 1833 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1834 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1835 1836 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1837 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1838 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1839 resp->comp_mask |= 1840 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1841 1842 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1843 1844 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1845 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1846 1847 resp->comp_mask |= 1848 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1849 1850 return 0; 1851 } 1852 1853 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1854 struct ib_udata *udata) 1855 { 1856 struct ib_device *ibdev = uctx->device; 1857 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1858 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1859 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1860 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1861 struct mlx5_bfreg_info *bfregi; 1862 int ver; 1863 int err; 1864 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1865 max_cqe_version); 1866 bool lib_uar_4k; 1867 bool lib_uar_dyn; 1868 1869 if (!dev->ib_active) 1870 return -EAGAIN; 1871 1872 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1873 ver = 0; 1874 else if (udata->inlen >= min_req_v2) 1875 ver = 2; 1876 else 1877 return -EINVAL; 1878 1879 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1880 if (err) 1881 return err; 1882 1883 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1884 return -EOPNOTSUPP; 1885 1886 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1887 return -EOPNOTSUPP; 1888 1889 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1890 MLX5_NON_FP_BFREGS_PER_UAR); 1891 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1892 return -EINVAL; 1893 1894 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1895 err = mlx5_ib_devx_create(dev, true); 1896 if (err < 0) 1897 goto out_ctx; 1898 context->devx_uid = err; 1899 } 1900 1901 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1902 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1903 bfregi = &context->bfregi; 1904 1905 if (lib_uar_dyn) { 1906 bfregi->lib_uar_dyn = lib_uar_dyn; 1907 goto uar_done; 1908 } 1909 1910 /* updates req->total_num_bfregs */ 1911 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1912 if (err) 1913 goto out_devx; 1914 1915 mutex_init(&bfregi->lock); 1916 bfregi->lib_uar_4k = lib_uar_4k; 1917 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1918 GFP_KERNEL); 1919 if (!bfregi->count) { 1920 err = -ENOMEM; 1921 goto out_devx; 1922 } 1923 1924 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1925 sizeof(*bfregi->sys_pages), 1926 GFP_KERNEL); 1927 if (!bfregi->sys_pages) { 1928 err = -ENOMEM; 1929 goto out_count; 1930 } 1931 1932 err = allocate_uars(dev, context); 1933 if (err) 1934 goto out_sys_pages; 1935 1936 uar_done: 1937 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1938 context->devx_uid); 1939 if (err) 1940 goto out_uars; 1941 1942 INIT_LIST_HEAD(&context->db_page_list); 1943 mutex_init(&context->db_page_mutex); 1944 1945 context->cqe_version = min_t(__u8, 1946 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1947 req.max_cqe_version); 1948 1949 err = set_ucontext_resp(uctx, &resp); 1950 if (err) 1951 goto out_mdev; 1952 1953 resp.response_length = min(udata->outlen, sizeof(resp)); 1954 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1955 if (err) 1956 goto out_mdev; 1957 1958 bfregi->ver = ver; 1959 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1960 context->lib_caps = req.lib_caps; 1961 print_lib_caps(dev, context->lib_caps); 1962 1963 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1964 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1965 1966 atomic_set(&context->tx_port_affinity, 1967 atomic_add_return( 1968 1, &dev->port[port].roce.tx_port_affinity)); 1969 } 1970 1971 return 0; 1972 1973 out_mdev: 1974 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1975 1976 out_uars: 1977 deallocate_uars(dev, context); 1978 1979 out_sys_pages: 1980 kfree(bfregi->sys_pages); 1981 1982 out_count: 1983 kfree(bfregi->count); 1984 1985 out_devx: 1986 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1987 mlx5_ib_devx_destroy(dev, context->devx_uid); 1988 1989 out_ctx: 1990 return err; 1991 } 1992 1993 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1994 struct uverbs_attr_bundle *attrs) 1995 { 1996 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1997 int ret; 1998 1999 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2000 if (ret) 2001 return ret; 2002 2003 uctx_resp.response_length = 2004 min_t(size_t, 2005 uverbs_attr_get_len(attrs, 2006 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2007 sizeof(uctx_resp)); 2008 2009 ret = uverbs_copy_to_struct_or_zero(attrs, 2010 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2011 &uctx_resp, 2012 sizeof(uctx_resp)); 2013 return ret; 2014 } 2015 2016 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2017 { 2018 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2019 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2020 struct mlx5_bfreg_info *bfregi; 2021 2022 bfregi = &context->bfregi; 2023 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2024 2025 deallocate_uars(dev, context); 2026 kfree(bfregi->sys_pages); 2027 kfree(bfregi->count); 2028 2029 if (context->devx_uid) 2030 mlx5_ib_devx_destroy(dev, context->devx_uid); 2031 } 2032 2033 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2034 int uar_idx) 2035 { 2036 int fw_uars_per_page; 2037 2038 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2039 2040 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2041 } 2042 2043 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2044 int uar_idx) 2045 { 2046 unsigned int fw_uars_per_page; 2047 2048 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2049 MLX5_UARS_IN_PAGE : 1; 2050 2051 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2052 } 2053 2054 static int get_command(unsigned long offset) 2055 { 2056 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2057 } 2058 2059 static int get_arg(unsigned long offset) 2060 { 2061 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2062 } 2063 2064 static int get_index(unsigned long offset) 2065 { 2066 return get_arg(offset); 2067 } 2068 2069 /* Index resides in an extra byte to enable larger values than 255 */ 2070 static int get_extended_index(unsigned long offset) 2071 { 2072 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2073 } 2074 2075 2076 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2077 { 2078 } 2079 2080 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2081 { 2082 switch (cmd) { 2083 case MLX5_IB_MMAP_WC_PAGE: 2084 return "WC"; 2085 case MLX5_IB_MMAP_REGULAR_PAGE: 2086 return "best effort WC"; 2087 case MLX5_IB_MMAP_NC_PAGE: 2088 return "NC"; 2089 case MLX5_IB_MMAP_DEVICE_MEM: 2090 return "Device Memory"; 2091 default: 2092 return "Unknown"; 2093 } 2094 } 2095 2096 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2097 struct vm_area_struct *vma, 2098 struct mlx5_ib_ucontext *context) 2099 { 2100 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2101 !(vma->vm_flags & VM_SHARED)) 2102 return -EINVAL; 2103 2104 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2105 return -EOPNOTSUPP; 2106 2107 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2108 return -EPERM; 2109 vm_flags_clear(vma, VM_MAYWRITE); 2110 2111 if (!dev->mdev->clock_info) 2112 return -EOPNOTSUPP; 2113 2114 return vm_insert_page(vma, vma->vm_start, 2115 virt_to_page(dev->mdev->clock_info)); 2116 } 2117 2118 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2119 { 2120 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2121 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2122 struct mlx5_var_table *var_table = &dev->var_table; 2123 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2124 2125 switch (mentry->mmap_flag) { 2126 case MLX5_IB_MMAP_TYPE_MEMIC: 2127 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2128 mlx5_ib_dm_mmap_free(dev, mentry); 2129 break; 2130 case MLX5_IB_MMAP_TYPE_VAR: 2131 mutex_lock(&var_table->bitmap_lock); 2132 clear_bit(mentry->page_idx, var_table->bitmap); 2133 mutex_unlock(&var_table->bitmap_lock); 2134 kfree(mentry); 2135 break; 2136 case MLX5_IB_MMAP_TYPE_UAR_WC: 2137 case MLX5_IB_MMAP_TYPE_UAR_NC: 2138 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2139 context->devx_uid); 2140 kfree(mentry); 2141 break; 2142 default: 2143 WARN_ON(true); 2144 } 2145 } 2146 2147 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2148 struct vm_area_struct *vma, 2149 struct mlx5_ib_ucontext *context) 2150 { 2151 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2152 int err; 2153 unsigned long idx; 2154 phys_addr_t pfn; 2155 pgprot_t prot; 2156 u32 bfreg_dyn_idx = 0; 2157 u32 uar_index; 2158 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2159 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2160 bfregi->num_static_sys_pages; 2161 2162 if (bfregi->lib_uar_dyn) 2163 return -EINVAL; 2164 2165 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2166 return -EINVAL; 2167 2168 if (dyn_uar) 2169 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2170 else 2171 idx = get_index(vma->vm_pgoff); 2172 2173 if (idx >= max_valid_idx) { 2174 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2175 idx, max_valid_idx); 2176 return -EINVAL; 2177 } 2178 2179 switch (cmd) { 2180 case MLX5_IB_MMAP_WC_PAGE: 2181 case MLX5_IB_MMAP_ALLOC_WC: 2182 case MLX5_IB_MMAP_REGULAR_PAGE: 2183 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2184 prot = pgprot_writecombine(vma->vm_page_prot); 2185 break; 2186 case MLX5_IB_MMAP_NC_PAGE: 2187 prot = pgprot_noncached(vma->vm_page_prot); 2188 break; 2189 default: 2190 return -EINVAL; 2191 } 2192 2193 if (dyn_uar) { 2194 int uars_per_page; 2195 2196 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2197 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2198 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2199 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2200 bfreg_dyn_idx, bfregi->total_num_bfregs); 2201 return -EINVAL; 2202 } 2203 2204 mutex_lock(&bfregi->lock); 2205 /* Fail if uar already allocated, first bfreg index of each 2206 * page holds its count. 2207 */ 2208 if (bfregi->count[bfreg_dyn_idx]) { 2209 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2210 mutex_unlock(&bfregi->lock); 2211 return -EINVAL; 2212 } 2213 2214 bfregi->count[bfreg_dyn_idx]++; 2215 mutex_unlock(&bfregi->lock); 2216 2217 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2218 context->devx_uid); 2219 if (err) { 2220 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2221 goto free_bfreg; 2222 } 2223 } else { 2224 uar_index = bfregi->sys_pages[idx]; 2225 } 2226 2227 pfn = uar_index2pfn(dev, uar_index); 2228 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2229 2230 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2231 prot, NULL); 2232 if (err) { 2233 mlx5_ib_err(dev, 2234 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2235 err, mmap_cmd2str(cmd)); 2236 goto err; 2237 } 2238 2239 if (dyn_uar) 2240 bfregi->sys_pages[idx] = uar_index; 2241 return 0; 2242 2243 err: 2244 if (!dyn_uar) 2245 return err; 2246 2247 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2248 2249 free_bfreg: 2250 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2251 2252 return err; 2253 } 2254 2255 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2256 { 2257 unsigned long idx; 2258 u8 command; 2259 2260 command = get_command(vma->vm_pgoff); 2261 idx = get_extended_index(vma->vm_pgoff); 2262 2263 return (command << 16 | idx); 2264 } 2265 2266 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2267 struct vm_area_struct *vma, 2268 struct ib_ucontext *ucontext) 2269 { 2270 struct mlx5_user_mmap_entry *mentry; 2271 struct rdma_user_mmap_entry *entry; 2272 unsigned long pgoff; 2273 pgprot_t prot; 2274 phys_addr_t pfn; 2275 int ret; 2276 2277 pgoff = mlx5_vma_to_pgoff(vma); 2278 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2279 if (!entry) 2280 return -EINVAL; 2281 2282 mentry = to_mmmap(entry); 2283 pfn = (mentry->address >> PAGE_SHIFT); 2284 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2285 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2286 prot = pgprot_noncached(vma->vm_page_prot); 2287 else 2288 prot = pgprot_writecombine(vma->vm_page_prot); 2289 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2290 entry->npages * PAGE_SIZE, 2291 prot, 2292 entry); 2293 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2294 return ret; 2295 } 2296 2297 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2298 { 2299 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2300 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2301 2302 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2303 (index & 0xFF)) << PAGE_SHIFT; 2304 } 2305 2306 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2307 { 2308 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2309 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2310 unsigned long command; 2311 phys_addr_t pfn; 2312 2313 command = get_command(vma->vm_pgoff); 2314 switch (command) { 2315 case MLX5_IB_MMAP_WC_PAGE: 2316 case MLX5_IB_MMAP_ALLOC_WC: 2317 if (!dev->wc_support) 2318 return -EPERM; 2319 fallthrough; 2320 case MLX5_IB_MMAP_NC_PAGE: 2321 case MLX5_IB_MMAP_REGULAR_PAGE: 2322 return uar_mmap(dev, command, vma, context); 2323 2324 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2325 return -ENOSYS; 2326 2327 case MLX5_IB_MMAP_CORE_CLOCK: 2328 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2329 return -EINVAL; 2330 2331 if (vma->vm_flags & VM_WRITE) 2332 return -EPERM; 2333 vm_flags_clear(vma, VM_MAYWRITE); 2334 2335 /* Don't expose to user-space information it shouldn't have */ 2336 if (PAGE_SIZE > 4096) 2337 return -EOPNOTSUPP; 2338 2339 pfn = (dev->mdev->iseg_base + 2340 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2341 PAGE_SHIFT; 2342 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2343 PAGE_SIZE, 2344 pgprot_noncached(vma->vm_page_prot), 2345 NULL); 2346 case MLX5_IB_MMAP_CLOCK_INFO: 2347 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2348 2349 default: 2350 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2351 } 2352 2353 return 0; 2354 } 2355 2356 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2357 { 2358 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2359 struct ib_device *ibdev = ibpd->device; 2360 struct mlx5_ib_alloc_pd_resp resp; 2361 int err; 2362 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2363 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2364 u16 uid = 0; 2365 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2366 udata, struct mlx5_ib_ucontext, ibucontext); 2367 2368 uid = context ? context->devx_uid : 0; 2369 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2370 MLX5_SET(alloc_pd_in, in, uid, uid); 2371 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2372 if (err) 2373 return err; 2374 2375 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2376 pd->uid = uid; 2377 if (udata) { 2378 resp.pdn = pd->pdn; 2379 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2380 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2381 return -EFAULT; 2382 } 2383 } 2384 2385 return 0; 2386 } 2387 2388 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2389 { 2390 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2391 struct mlx5_ib_pd *mpd = to_mpd(pd); 2392 2393 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2394 } 2395 2396 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2397 { 2398 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2399 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2400 int err; 2401 u16 uid; 2402 2403 uid = ibqp->pd ? 2404 to_mpd(ibqp->pd)->uid : 0; 2405 2406 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2407 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2408 return -EOPNOTSUPP; 2409 } 2410 2411 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2412 if (err) 2413 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2414 ibqp->qp_num, gid->raw); 2415 2416 return err; 2417 } 2418 2419 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2420 { 2421 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2422 int err; 2423 u16 uid; 2424 2425 uid = ibqp->pd ? 2426 to_mpd(ibqp->pd)->uid : 0; 2427 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2428 if (err) 2429 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2430 ibqp->qp_num, gid->raw); 2431 2432 return err; 2433 } 2434 2435 static int init_node_data(struct mlx5_ib_dev *dev) 2436 { 2437 int err; 2438 2439 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2440 if (err) 2441 return err; 2442 2443 dev->mdev->rev_id = dev->mdev->pdev->revision; 2444 2445 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2446 } 2447 2448 static ssize_t fw_pages_show(struct device *device, 2449 struct device_attribute *attr, char *buf) 2450 { 2451 struct mlx5_ib_dev *dev = 2452 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2453 2454 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2455 } 2456 static DEVICE_ATTR_RO(fw_pages); 2457 2458 static ssize_t reg_pages_show(struct device *device, 2459 struct device_attribute *attr, char *buf) 2460 { 2461 struct mlx5_ib_dev *dev = 2462 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2463 2464 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2465 } 2466 static DEVICE_ATTR_RO(reg_pages); 2467 2468 static ssize_t hca_type_show(struct device *device, 2469 struct device_attribute *attr, char *buf) 2470 { 2471 struct mlx5_ib_dev *dev = 2472 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2473 2474 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2475 } 2476 static DEVICE_ATTR_RO(hca_type); 2477 2478 static ssize_t hw_rev_show(struct device *device, 2479 struct device_attribute *attr, char *buf) 2480 { 2481 struct mlx5_ib_dev *dev = 2482 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2483 2484 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2485 } 2486 static DEVICE_ATTR_RO(hw_rev); 2487 2488 static ssize_t board_id_show(struct device *device, 2489 struct device_attribute *attr, char *buf) 2490 { 2491 struct mlx5_ib_dev *dev = 2492 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2493 2494 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2495 dev->mdev->board_id); 2496 } 2497 static DEVICE_ATTR_RO(board_id); 2498 2499 static struct attribute *mlx5_class_attributes[] = { 2500 &dev_attr_hw_rev.attr, 2501 &dev_attr_hca_type.attr, 2502 &dev_attr_board_id.attr, 2503 &dev_attr_fw_pages.attr, 2504 &dev_attr_reg_pages.attr, 2505 NULL, 2506 }; 2507 2508 static const struct attribute_group mlx5_attr_group = { 2509 .attrs = mlx5_class_attributes, 2510 }; 2511 2512 static void pkey_change_handler(struct work_struct *work) 2513 { 2514 struct mlx5_ib_port_resources *ports = 2515 container_of(work, struct mlx5_ib_port_resources, 2516 pkey_change_work); 2517 2518 if (!ports->gsi) 2519 /* 2520 * We got this event before device was fully configured 2521 * and MAD registration code wasn't called/finished yet. 2522 */ 2523 return; 2524 2525 mlx5_ib_gsi_pkey_change(ports->gsi); 2526 } 2527 2528 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2529 { 2530 struct mlx5_ib_qp *mqp; 2531 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2532 struct mlx5_core_cq *mcq; 2533 struct list_head cq_armed_list; 2534 unsigned long flags_qp; 2535 unsigned long flags_cq; 2536 unsigned long flags; 2537 2538 INIT_LIST_HEAD(&cq_armed_list); 2539 2540 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2541 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2542 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2543 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2544 if (mqp->sq.tail != mqp->sq.head) { 2545 send_mcq = to_mcq(mqp->ibqp.send_cq); 2546 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2547 if (send_mcq->mcq.comp && 2548 mqp->ibqp.send_cq->comp_handler) { 2549 if (!send_mcq->mcq.reset_notify_added) { 2550 send_mcq->mcq.reset_notify_added = 1; 2551 list_add_tail(&send_mcq->mcq.reset_notify, 2552 &cq_armed_list); 2553 } 2554 } 2555 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2556 } 2557 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2558 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2559 /* no handling is needed for SRQ */ 2560 if (!mqp->ibqp.srq) { 2561 if (mqp->rq.tail != mqp->rq.head) { 2562 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2563 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2564 if (recv_mcq->mcq.comp && 2565 mqp->ibqp.recv_cq->comp_handler) { 2566 if (!recv_mcq->mcq.reset_notify_added) { 2567 recv_mcq->mcq.reset_notify_added = 1; 2568 list_add_tail(&recv_mcq->mcq.reset_notify, 2569 &cq_armed_list); 2570 } 2571 } 2572 spin_unlock_irqrestore(&recv_mcq->lock, 2573 flags_cq); 2574 } 2575 } 2576 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2577 } 2578 /*At that point all inflight post send were put to be executed as of we 2579 * lock/unlock above locks Now need to arm all involved CQs. 2580 */ 2581 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2582 mcq->comp(mcq, NULL); 2583 } 2584 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2585 } 2586 2587 static void delay_drop_handler(struct work_struct *work) 2588 { 2589 int err; 2590 struct mlx5_ib_delay_drop *delay_drop = 2591 container_of(work, struct mlx5_ib_delay_drop, 2592 delay_drop_work); 2593 2594 atomic_inc(&delay_drop->events_cnt); 2595 2596 mutex_lock(&delay_drop->lock); 2597 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2598 if (err) { 2599 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2600 delay_drop->timeout); 2601 delay_drop->activate = false; 2602 } 2603 mutex_unlock(&delay_drop->lock); 2604 } 2605 2606 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2607 struct ib_event *ibev) 2608 { 2609 u32 port = (eqe->data.port.port >> 4) & 0xf; 2610 2611 switch (eqe->sub_type) { 2612 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2613 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2614 IB_LINK_LAYER_ETHERNET) 2615 schedule_work(&ibdev->delay_drop.delay_drop_work); 2616 break; 2617 default: /* do nothing */ 2618 return; 2619 } 2620 } 2621 2622 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2623 struct ib_event *ibev) 2624 { 2625 u32 port = (eqe->data.port.port >> 4) & 0xf; 2626 2627 ibev->element.port_num = port; 2628 2629 switch (eqe->sub_type) { 2630 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2631 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2632 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2633 /* In RoCE, port up/down events are handled in 2634 * mlx5_netdev_event(). 2635 */ 2636 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2637 IB_LINK_LAYER_ETHERNET) 2638 return -EINVAL; 2639 2640 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2641 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2642 break; 2643 2644 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2645 ibev->event = IB_EVENT_LID_CHANGE; 2646 break; 2647 2648 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2649 ibev->event = IB_EVENT_PKEY_CHANGE; 2650 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2651 break; 2652 2653 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2654 ibev->event = IB_EVENT_GID_CHANGE; 2655 break; 2656 2657 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2658 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2659 break; 2660 default: 2661 return -EINVAL; 2662 } 2663 2664 return 0; 2665 } 2666 2667 static void mlx5_ib_handle_event(struct work_struct *_work) 2668 { 2669 struct mlx5_ib_event_work *work = 2670 container_of(_work, struct mlx5_ib_event_work, work); 2671 struct mlx5_ib_dev *ibdev; 2672 struct ib_event ibev; 2673 bool fatal = false; 2674 2675 if (work->is_slave) { 2676 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2677 if (!ibdev) 2678 goto out; 2679 } else { 2680 ibdev = work->dev; 2681 } 2682 2683 switch (work->event) { 2684 case MLX5_DEV_EVENT_SYS_ERROR: 2685 ibev.event = IB_EVENT_DEVICE_FATAL; 2686 mlx5_ib_handle_internal_error(ibdev); 2687 ibev.element.port_num = (u8)(unsigned long)work->param; 2688 fatal = true; 2689 break; 2690 case MLX5_EVENT_TYPE_PORT_CHANGE: 2691 if (handle_port_change(ibdev, work->param, &ibev)) 2692 goto out; 2693 break; 2694 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2695 handle_general_event(ibdev, work->param, &ibev); 2696 fallthrough; 2697 default: 2698 goto out; 2699 } 2700 2701 ibev.device = &ibdev->ib_dev; 2702 2703 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2704 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2705 goto out; 2706 } 2707 2708 if (ibdev->ib_active) 2709 ib_dispatch_event(&ibev); 2710 2711 if (fatal) 2712 ibdev->ib_active = false; 2713 out: 2714 kfree(work); 2715 } 2716 2717 static int mlx5_ib_event(struct notifier_block *nb, 2718 unsigned long event, void *param) 2719 { 2720 struct mlx5_ib_event_work *work; 2721 2722 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2723 if (!work) 2724 return NOTIFY_DONE; 2725 2726 INIT_WORK(&work->work, mlx5_ib_handle_event); 2727 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2728 work->is_slave = false; 2729 work->param = param; 2730 work->event = event; 2731 2732 queue_work(mlx5_ib_event_wq, &work->work); 2733 2734 return NOTIFY_OK; 2735 } 2736 2737 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2738 unsigned long event, void *param) 2739 { 2740 struct mlx5_ib_event_work *work; 2741 2742 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2743 if (!work) 2744 return NOTIFY_DONE; 2745 2746 INIT_WORK(&work->work, mlx5_ib_handle_event); 2747 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2748 work->is_slave = true; 2749 work->param = param; 2750 work->event = event; 2751 queue_work(mlx5_ib_event_wq, &work->work); 2752 2753 return NOTIFY_OK; 2754 } 2755 2756 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2757 { 2758 struct mlx5_hca_vport_context vport_ctx; 2759 int err; 2760 int port; 2761 2762 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2763 return 0; 2764 2765 for (port = 1; port <= dev->num_ports; port++) { 2766 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2767 dev->port_caps[port - 1].has_smi = true; 2768 continue; 2769 } 2770 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2771 &vport_ctx); 2772 if (err) { 2773 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2774 port, err); 2775 return err; 2776 } 2777 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2778 } 2779 2780 return 0; 2781 } 2782 2783 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2784 { 2785 unsigned int port; 2786 2787 rdma_for_each_port (&dev->ib_dev, port) 2788 mlx5_query_ext_port_caps(dev, port); 2789 } 2790 2791 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2792 { 2793 switch (umr_fence_cap) { 2794 case MLX5_CAP_UMR_FENCE_NONE: 2795 return MLX5_FENCE_MODE_NONE; 2796 case MLX5_CAP_UMR_FENCE_SMALL: 2797 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2798 default: 2799 return MLX5_FENCE_MODE_STRONG_ORDERING; 2800 } 2801 } 2802 2803 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2804 { 2805 struct mlx5_ib_resources *devr = &dev->devr; 2806 struct ib_srq_init_attr attr; 2807 struct ib_device *ibdev; 2808 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2809 int port; 2810 int ret = 0; 2811 2812 ibdev = &dev->ib_dev; 2813 2814 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2815 return -EOPNOTSUPP; 2816 2817 devr->p0 = ib_alloc_pd(ibdev, 0); 2818 if (IS_ERR(devr->p0)) 2819 return PTR_ERR(devr->p0); 2820 2821 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2822 if (IS_ERR(devr->c0)) { 2823 ret = PTR_ERR(devr->c0); 2824 goto error1; 2825 } 2826 2827 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2828 if (ret) 2829 goto error2; 2830 2831 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2832 if (ret) 2833 goto error3; 2834 2835 memset(&attr, 0, sizeof(attr)); 2836 attr.attr.max_sge = 1; 2837 attr.attr.max_wr = 1; 2838 attr.srq_type = IB_SRQT_XRC; 2839 attr.ext.cq = devr->c0; 2840 2841 devr->s0 = ib_create_srq(devr->p0, &attr); 2842 if (IS_ERR(devr->s0)) { 2843 ret = PTR_ERR(devr->s0); 2844 goto err_create; 2845 } 2846 2847 memset(&attr, 0, sizeof(attr)); 2848 attr.attr.max_sge = 1; 2849 attr.attr.max_wr = 1; 2850 attr.srq_type = IB_SRQT_BASIC; 2851 2852 devr->s1 = ib_create_srq(devr->p0, &attr); 2853 if (IS_ERR(devr->s1)) { 2854 ret = PTR_ERR(devr->s1); 2855 goto error6; 2856 } 2857 2858 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2859 INIT_WORK(&devr->ports[port].pkey_change_work, 2860 pkey_change_handler); 2861 2862 return 0; 2863 2864 error6: 2865 ib_destroy_srq(devr->s0); 2866 err_create: 2867 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2868 error3: 2869 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2870 error2: 2871 ib_destroy_cq(devr->c0); 2872 error1: 2873 ib_dealloc_pd(devr->p0); 2874 return ret; 2875 } 2876 2877 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2878 { 2879 struct mlx5_ib_resources *devr = &dev->devr; 2880 int port; 2881 2882 /* 2883 * Make sure no change P_Key work items are still executing. 2884 * 2885 * At this stage, the mlx5_ib_event should be unregistered 2886 * and it ensures that no new works are added. 2887 */ 2888 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2889 cancel_work_sync(&devr->ports[port].pkey_change_work); 2890 2891 ib_destroy_srq(devr->s1); 2892 ib_destroy_srq(devr->s0); 2893 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2894 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2895 ib_destroy_cq(devr->c0); 2896 ib_dealloc_pd(devr->p0); 2897 } 2898 2899 static u32 get_core_cap_flags(struct ib_device *ibdev, 2900 struct mlx5_hca_vport_context *rep) 2901 { 2902 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2903 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2904 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2905 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2906 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2907 u32 ret = 0; 2908 2909 if (rep->grh_required) 2910 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2911 2912 if (ll == IB_LINK_LAYER_INFINIBAND) 2913 return ret | RDMA_CORE_PORT_IBA_IB; 2914 2915 if (raw_support) 2916 ret |= RDMA_CORE_PORT_RAW_PACKET; 2917 2918 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2919 return ret; 2920 2921 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2922 return ret; 2923 2924 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2925 ret |= RDMA_CORE_PORT_IBA_ROCE; 2926 2927 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2928 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2929 2930 return ret; 2931 } 2932 2933 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2934 struct ib_port_immutable *immutable) 2935 { 2936 struct ib_port_attr attr; 2937 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2938 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2939 struct mlx5_hca_vport_context rep = {0}; 2940 int err; 2941 2942 err = ib_query_port(ibdev, port_num, &attr); 2943 if (err) 2944 return err; 2945 2946 if (ll == IB_LINK_LAYER_INFINIBAND) { 2947 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2948 &rep); 2949 if (err) 2950 return err; 2951 } 2952 2953 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2954 immutable->gid_tbl_len = attr.gid_tbl_len; 2955 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2956 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2957 2958 return 0; 2959 } 2960 2961 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2962 struct ib_port_immutable *immutable) 2963 { 2964 struct ib_port_attr attr; 2965 int err; 2966 2967 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2968 2969 err = ib_query_port(ibdev, port_num, &attr); 2970 if (err) 2971 return err; 2972 2973 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2974 immutable->gid_tbl_len = attr.gid_tbl_len; 2975 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2976 2977 return 0; 2978 } 2979 2980 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2981 { 2982 struct mlx5_ib_dev *dev = 2983 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2984 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2985 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2986 fw_rev_sub(dev->mdev)); 2987 } 2988 2989 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2990 { 2991 struct mlx5_core_dev *mdev = dev->mdev; 2992 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2993 MLX5_FLOW_NAMESPACE_LAG); 2994 struct mlx5_flow_table *ft; 2995 int err; 2996 2997 if (!ns || !mlx5_lag_is_active(mdev)) 2998 return 0; 2999 3000 err = mlx5_cmd_create_vport_lag(mdev); 3001 if (err) 3002 return err; 3003 3004 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3005 if (IS_ERR(ft)) { 3006 err = PTR_ERR(ft); 3007 goto err_destroy_vport_lag; 3008 } 3009 3010 dev->flow_db->lag_demux_ft = ft; 3011 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3012 dev->lag_active = true; 3013 return 0; 3014 3015 err_destroy_vport_lag: 3016 mlx5_cmd_destroy_vport_lag(mdev); 3017 return err; 3018 } 3019 3020 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3021 { 3022 struct mlx5_core_dev *mdev = dev->mdev; 3023 3024 if (dev->lag_active) { 3025 dev->lag_active = false; 3026 3027 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3028 dev->flow_db->lag_demux_ft = NULL; 3029 3030 mlx5_cmd_destroy_vport_lag(mdev); 3031 } 3032 } 3033 3034 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3035 struct net_device *netdev) 3036 { 3037 int err; 3038 3039 if (roce->tracking_netdev) 3040 return; 3041 roce->tracking_netdev = netdev; 3042 roce->nb.notifier_call = mlx5_netdev_event; 3043 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3044 WARN_ON(err); 3045 } 3046 3047 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3048 { 3049 if (!roce->tracking_netdev) 3050 return; 3051 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3052 &roce->nn); 3053 roce->tracking_netdev = NULL; 3054 } 3055 3056 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3057 unsigned long event, void *data) 3058 { 3059 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3060 struct net_device *netdev = data; 3061 3062 switch (event) { 3063 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3064 if (netdev) 3065 mlx5_netdev_notifier_register(roce, netdev); 3066 else 3067 mlx5_netdev_notifier_unregister(roce); 3068 break; 3069 default: 3070 return NOTIFY_DONE; 3071 } 3072 3073 return NOTIFY_OK; 3074 } 3075 3076 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3077 { 3078 struct mlx5_roce *roce = &dev->port[port_num].roce; 3079 3080 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3081 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3082 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3083 } 3084 3085 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3086 { 3087 struct mlx5_roce *roce = &dev->port[port_num].roce; 3088 3089 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3090 mlx5_netdev_notifier_unregister(roce); 3091 } 3092 3093 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3094 { 3095 int err; 3096 3097 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3098 err = mlx5_nic_vport_enable_roce(dev->mdev); 3099 if (err) 3100 return err; 3101 } 3102 3103 err = mlx5_eth_lag_init(dev); 3104 if (err) 3105 goto err_disable_roce; 3106 3107 return 0; 3108 3109 err_disable_roce: 3110 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3111 mlx5_nic_vport_disable_roce(dev->mdev); 3112 3113 return err; 3114 } 3115 3116 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3117 { 3118 mlx5_eth_lag_cleanup(dev); 3119 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3120 mlx5_nic_vport_disable_roce(dev->mdev); 3121 } 3122 3123 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3124 enum rdma_netdev_t type, 3125 struct rdma_netdev_alloc_params *params) 3126 { 3127 if (type != RDMA_NETDEV_IPOIB) 3128 return -EOPNOTSUPP; 3129 3130 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3131 } 3132 3133 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3134 size_t count, loff_t *pos) 3135 { 3136 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3137 char lbuf[20]; 3138 int len; 3139 3140 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3141 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3142 } 3143 3144 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3145 size_t count, loff_t *pos) 3146 { 3147 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3148 u32 timeout; 3149 u32 var; 3150 3151 if (kstrtouint_from_user(buf, count, 0, &var)) 3152 return -EFAULT; 3153 3154 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3155 1000); 3156 if (timeout != var) 3157 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3158 timeout); 3159 3160 delay_drop->timeout = timeout; 3161 3162 return count; 3163 } 3164 3165 static const struct file_operations fops_delay_drop_timeout = { 3166 .owner = THIS_MODULE, 3167 .open = simple_open, 3168 .write = delay_drop_timeout_write, 3169 .read = delay_drop_timeout_read, 3170 }; 3171 3172 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3173 struct mlx5_ib_multiport_info *mpi) 3174 { 3175 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3176 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3177 int comps; 3178 int err; 3179 int i; 3180 3181 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3182 3183 mlx5_core_mp_event_replay(ibdev->mdev, 3184 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3185 NULL); 3186 mlx5_core_mp_event_replay(mpi->mdev, 3187 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3188 NULL); 3189 3190 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3191 3192 spin_lock(&port->mp.mpi_lock); 3193 if (!mpi->ibdev) { 3194 spin_unlock(&port->mp.mpi_lock); 3195 return; 3196 } 3197 3198 mpi->ibdev = NULL; 3199 3200 spin_unlock(&port->mp.mpi_lock); 3201 if (mpi->mdev_events.notifier_call) 3202 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3203 mpi->mdev_events.notifier_call = NULL; 3204 mlx5_mdev_netdev_untrack(ibdev, port_num); 3205 spin_lock(&port->mp.mpi_lock); 3206 3207 comps = mpi->mdev_refcnt; 3208 if (comps) { 3209 mpi->unaffiliate = true; 3210 init_completion(&mpi->unref_comp); 3211 spin_unlock(&port->mp.mpi_lock); 3212 3213 for (i = 0; i < comps; i++) 3214 wait_for_completion(&mpi->unref_comp); 3215 3216 spin_lock(&port->mp.mpi_lock); 3217 mpi->unaffiliate = false; 3218 } 3219 3220 port->mp.mpi = NULL; 3221 3222 spin_unlock(&port->mp.mpi_lock); 3223 3224 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3225 3226 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3227 /* Log an error, still needed to cleanup the pointers and add 3228 * it back to the list. 3229 */ 3230 if (err) 3231 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3232 port_num + 1); 3233 3234 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3235 } 3236 3237 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3238 struct mlx5_ib_multiport_info *mpi) 3239 { 3240 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3241 u64 key; 3242 int err; 3243 3244 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3245 3246 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3247 if (ibdev->port[port_num].mp.mpi) { 3248 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3249 port_num + 1); 3250 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3251 return false; 3252 } 3253 3254 ibdev->port[port_num].mp.mpi = mpi; 3255 mpi->ibdev = ibdev; 3256 mpi->mdev_events.notifier_call = NULL; 3257 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3258 3259 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3260 if (err) 3261 goto unbind; 3262 3263 mlx5_mdev_netdev_track(ibdev, port_num); 3264 3265 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3266 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3267 3268 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3269 3270 key = mpi->mdev->priv.adev_idx; 3271 mlx5_core_mp_event_replay(mpi->mdev, 3272 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3273 &key); 3274 mlx5_core_mp_event_replay(ibdev->mdev, 3275 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3276 &key); 3277 3278 return true; 3279 3280 unbind: 3281 mlx5_ib_unbind_slave_port(ibdev, mpi); 3282 return false; 3283 } 3284 3285 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3286 { 3287 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3288 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3289 port_num + 1); 3290 struct mlx5_ib_multiport_info *mpi; 3291 int err; 3292 u32 i; 3293 3294 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3295 return 0; 3296 3297 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3298 &dev->sys_image_guid); 3299 if (err) 3300 return err; 3301 3302 err = mlx5_nic_vport_enable_roce(dev->mdev); 3303 if (err) 3304 return err; 3305 3306 mutex_lock(&mlx5_ib_multiport_mutex); 3307 for (i = 0; i < dev->num_ports; i++) { 3308 bool bound = false; 3309 3310 /* build a stub multiport info struct for the native port. */ 3311 if (i == port_num) { 3312 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3313 if (!mpi) { 3314 mutex_unlock(&mlx5_ib_multiport_mutex); 3315 mlx5_nic_vport_disable_roce(dev->mdev); 3316 return -ENOMEM; 3317 } 3318 3319 mpi->is_master = true; 3320 mpi->mdev = dev->mdev; 3321 mpi->sys_image_guid = dev->sys_image_guid; 3322 dev->port[i].mp.mpi = mpi; 3323 mpi->ibdev = dev; 3324 mpi = NULL; 3325 continue; 3326 } 3327 3328 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3329 list) { 3330 if (dev->sys_image_guid == mpi->sys_image_guid && 3331 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3332 bound = mlx5_ib_bind_slave_port(dev, mpi); 3333 } 3334 3335 if (bound) { 3336 dev_dbg(mpi->mdev->device, 3337 "removing port from unaffiliated list.\n"); 3338 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3339 list_del(&mpi->list); 3340 break; 3341 } 3342 } 3343 if (!bound) 3344 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3345 i + 1); 3346 } 3347 3348 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3349 mutex_unlock(&mlx5_ib_multiport_mutex); 3350 return err; 3351 } 3352 3353 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3354 { 3355 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3356 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3357 port_num + 1); 3358 u32 i; 3359 3360 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3361 return; 3362 3363 mutex_lock(&mlx5_ib_multiport_mutex); 3364 for (i = 0; i < dev->num_ports; i++) { 3365 if (dev->port[i].mp.mpi) { 3366 /* Destroy the native port stub */ 3367 if (i == port_num) { 3368 kfree(dev->port[i].mp.mpi); 3369 dev->port[i].mp.mpi = NULL; 3370 } else { 3371 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3372 i + 1); 3373 list_add_tail(&dev->port[i].mp.mpi->list, 3374 &mlx5_ib_unaffiliated_port_list); 3375 mlx5_ib_unbind_slave_port(dev, 3376 dev->port[i].mp.mpi); 3377 } 3378 } 3379 } 3380 3381 mlx5_ib_dbg(dev, "removing from devlist\n"); 3382 list_del(&dev->ib_dev_list); 3383 mutex_unlock(&mlx5_ib_multiport_mutex); 3384 3385 mlx5_nic_vport_disable_roce(dev->mdev); 3386 } 3387 3388 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3389 enum rdma_remove_reason why, 3390 struct uverbs_attr_bundle *attrs) 3391 { 3392 struct mlx5_user_mmap_entry *obj = uobject->object; 3393 3394 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3395 return 0; 3396 } 3397 3398 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3399 struct mlx5_user_mmap_entry *entry, 3400 size_t length) 3401 { 3402 return rdma_user_mmap_entry_insert_range( 3403 &c->ibucontext, &entry->rdma_entry, length, 3404 (MLX5_IB_MMAP_OFFSET_START << 16), 3405 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3406 } 3407 3408 static struct mlx5_user_mmap_entry * 3409 alloc_var_entry(struct mlx5_ib_ucontext *c) 3410 { 3411 struct mlx5_user_mmap_entry *entry; 3412 struct mlx5_var_table *var_table; 3413 u32 page_idx; 3414 int err; 3415 3416 var_table = &to_mdev(c->ibucontext.device)->var_table; 3417 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3418 if (!entry) 3419 return ERR_PTR(-ENOMEM); 3420 3421 mutex_lock(&var_table->bitmap_lock); 3422 page_idx = find_first_zero_bit(var_table->bitmap, 3423 var_table->num_var_hw_entries); 3424 if (page_idx >= var_table->num_var_hw_entries) { 3425 err = -ENOSPC; 3426 mutex_unlock(&var_table->bitmap_lock); 3427 goto end; 3428 } 3429 3430 set_bit(page_idx, var_table->bitmap); 3431 mutex_unlock(&var_table->bitmap_lock); 3432 3433 entry->address = var_table->hw_start_addr + 3434 (page_idx * var_table->stride_size); 3435 entry->page_idx = page_idx; 3436 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3437 3438 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3439 var_table->stride_size); 3440 if (err) 3441 goto err_insert; 3442 3443 return entry; 3444 3445 err_insert: 3446 mutex_lock(&var_table->bitmap_lock); 3447 clear_bit(page_idx, var_table->bitmap); 3448 mutex_unlock(&var_table->bitmap_lock); 3449 end: 3450 kfree(entry); 3451 return ERR_PTR(err); 3452 } 3453 3454 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3455 struct uverbs_attr_bundle *attrs) 3456 { 3457 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3458 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3459 struct mlx5_ib_ucontext *c; 3460 struct mlx5_user_mmap_entry *entry; 3461 u64 mmap_offset; 3462 u32 length; 3463 int err; 3464 3465 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3466 if (IS_ERR(c)) 3467 return PTR_ERR(c); 3468 3469 entry = alloc_var_entry(c); 3470 if (IS_ERR(entry)) 3471 return PTR_ERR(entry); 3472 3473 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3474 length = entry->rdma_entry.npages * PAGE_SIZE; 3475 uobj->object = entry; 3476 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3477 3478 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3479 &mmap_offset, sizeof(mmap_offset)); 3480 if (err) 3481 return err; 3482 3483 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3484 &entry->page_idx, sizeof(entry->page_idx)); 3485 if (err) 3486 return err; 3487 3488 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3489 &length, sizeof(length)); 3490 return err; 3491 } 3492 3493 DECLARE_UVERBS_NAMED_METHOD( 3494 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3495 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3496 MLX5_IB_OBJECT_VAR, 3497 UVERBS_ACCESS_NEW, 3498 UA_MANDATORY), 3499 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3500 UVERBS_ATTR_TYPE(u32), 3501 UA_MANDATORY), 3502 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3503 UVERBS_ATTR_TYPE(u32), 3504 UA_MANDATORY), 3505 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3506 UVERBS_ATTR_TYPE(u64), 3507 UA_MANDATORY)); 3508 3509 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3510 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3511 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3512 MLX5_IB_OBJECT_VAR, 3513 UVERBS_ACCESS_DESTROY, 3514 UA_MANDATORY)); 3515 3516 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3517 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3518 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3519 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3520 3521 static bool var_is_supported(struct ib_device *device) 3522 { 3523 struct mlx5_ib_dev *dev = to_mdev(device); 3524 3525 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3526 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3527 } 3528 3529 static struct mlx5_user_mmap_entry * 3530 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3531 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3532 { 3533 struct mlx5_user_mmap_entry *entry; 3534 struct mlx5_ib_dev *dev; 3535 u32 uar_index; 3536 int err; 3537 3538 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3539 if (!entry) 3540 return ERR_PTR(-ENOMEM); 3541 3542 dev = to_mdev(c->ibucontext.device); 3543 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3544 if (err) 3545 goto end; 3546 3547 entry->page_idx = uar_index; 3548 entry->address = uar_index2paddress(dev, uar_index); 3549 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3550 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3551 else 3552 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3553 3554 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3555 if (err) 3556 goto err_insert; 3557 3558 return entry; 3559 3560 err_insert: 3561 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3562 end: 3563 kfree(entry); 3564 return ERR_PTR(err); 3565 } 3566 3567 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3568 struct uverbs_attr_bundle *attrs) 3569 { 3570 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3571 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3572 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3573 struct mlx5_ib_ucontext *c; 3574 struct mlx5_user_mmap_entry *entry; 3575 u64 mmap_offset; 3576 u32 length; 3577 int err; 3578 3579 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3580 if (IS_ERR(c)) 3581 return PTR_ERR(c); 3582 3583 err = uverbs_get_const(&alloc_type, attrs, 3584 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3585 if (err) 3586 return err; 3587 3588 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3589 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3590 return -EOPNOTSUPP; 3591 3592 if (!to_mdev(c->ibucontext.device)->wc_support && 3593 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3594 return -EOPNOTSUPP; 3595 3596 entry = alloc_uar_entry(c, alloc_type); 3597 if (IS_ERR(entry)) 3598 return PTR_ERR(entry); 3599 3600 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3601 length = entry->rdma_entry.npages * PAGE_SIZE; 3602 uobj->object = entry; 3603 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3604 3605 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3606 &mmap_offset, sizeof(mmap_offset)); 3607 if (err) 3608 return err; 3609 3610 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3611 &entry->page_idx, sizeof(entry->page_idx)); 3612 if (err) 3613 return err; 3614 3615 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3616 &length, sizeof(length)); 3617 return err; 3618 } 3619 3620 DECLARE_UVERBS_NAMED_METHOD( 3621 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3622 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3623 MLX5_IB_OBJECT_UAR, 3624 UVERBS_ACCESS_NEW, 3625 UA_MANDATORY), 3626 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3627 enum mlx5_ib_uapi_uar_alloc_type, 3628 UA_MANDATORY), 3629 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3630 UVERBS_ATTR_TYPE(u32), 3631 UA_MANDATORY), 3632 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3633 UVERBS_ATTR_TYPE(u32), 3634 UA_MANDATORY), 3635 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3636 UVERBS_ATTR_TYPE(u64), 3637 UA_MANDATORY)); 3638 3639 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3640 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3641 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3642 MLX5_IB_OBJECT_UAR, 3643 UVERBS_ACCESS_DESTROY, 3644 UA_MANDATORY)); 3645 3646 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3647 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3648 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3649 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3650 3651 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3652 mlx5_ib_query_context, 3653 UVERBS_OBJECT_DEVICE, 3654 UVERBS_METHOD_QUERY_CONTEXT, 3655 UVERBS_ATTR_PTR_OUT( 3656 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3657 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3658 dump_fill_mkey), 3659 UA_MANDATORY)); 3660 3661 static const struct uapi_definition mlx5_ib_defs[] = { 3662 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3663 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3664 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3665 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3666 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3667 3668 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3669 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3670 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3671 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3672 {} 3673 }; 3674 3675 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3676 { 3677 mlx5_ib_cleanup_multiport_master(dev); 3678 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3679 mutex_destroy(&dev->cap_mask_mutex); 3680 WARN_ON(!xa_empty(&dev->sig_mrs)); 3681 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3682 mlx5r_macsec_dealloc_gids(dev); 3683 } 3684 3685 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3686 { 3687 struct mlx5_core_dev *mdev = dev->mdev; 3688 int err, i; 3689 3690 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3691 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3692 dev->ib_dev.phys_port_cnt = dev->num_ports; 3693 dev->ib_dev.dev.parent = mdev->device; 3694 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3695 3696 for (i = 0; i < dev->num_ports; i++) { 3697 spin_lock_init(&dev->port[i].mp.mpi_lock); 3698 rwlock_init(&dev->port[i].roce.netdev_lock); 3699 dev->port[i].roce.dev = dev; 3700 dev->port[i].roce.native_port_num = i + 1; 3701 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3702 } 3703 3704 err = mlx5r_cmd_query_special_mkeys(dev); 3705 if (err) 3706 return err; 3707 3708 err = mlx5r_macsec_init_gids_and_devlist(dev); 3709 if (err) 3710 return err; 3711 3712 err = mlx5_ib_init_multiport_master(dev); 3713 if (err) 3714 goto err; 3715 3716 err = set_has_smi_cap(dev); 3717 if (err) 3718 goto err_mp; 3719 3720 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3721 if (err) 3722 goto err_mp; 3723 3724 if (mlx5_use_mad_ifc(dev)) 3725 get_ext_port_caps(dev); 3726 3727 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 3728 3729 mutex_init(&dev->cap_mask_mutex); 3730 INIT_LIST_HEAD(&dev->qp_list); 3731 spin_lock_init(&dev->reset_flow_resource_lock); 3732 xa_init(&dev->odp_mkeys); 3733 xa_init(&dev->sig_mrs); 3734 atomic_set(&dev->mkey_var, 0); 3735 3736 spin_lock_init(&dev->dm.lock); 3737 dev->dm.dev = mdev; 3738 return 0; 3739 err: 3740 mlx5r_macsec_dealloc_gids(dev); 3741 err_mp: 3742 mlx5_ib_cleanup_multiport_master(dev); 3743 return err; 3744 } 3745 3746 static int mlx5_ib_enable_driver(struct ib_device *dev) 3747 { 3748 struct mlx5_ib_dev *mdev = to_mdev(dev); 3749 int ret; 3750 3751 ret = mlx5_ib_test_wc(mdev); 3752 mlx5_ib_dbg(mdev, "Write-Combining %s", 3753 mdev->wc_support ? "supported" : "not supported"); 3754 3755 return ret; 3756 } 3757 3758 static const struct ib_device_ops mlx5_ib_dev_ops = { 3759 .owner = THIS_MODULE, 3760 .driver_id = RDMA_DRIVER_MLX5, 3761 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3762 3763 .add_gid = mlx5_ib_add_gid, 3764 .alloc_mr = mlx5_ib_alloc_mr, 3765 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3766 .alloc_pd = mlx5_ib_alloc_pd, 3767 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3768 .attach_mcast = mlx5_ib_mcg_attach, 3769 .check_mr_status = mlx5_ib_check_mr_status, 3770 .create_ah = mlx5_ib_create_ah, 3771 .create_cq = mlx5_ib_create_cq, 3772 .create_qp = mlx5_ib_create_qp, 3773 .create_srq = mlx5_ib_create_srq, 3774 .create_user_ah = mlx5_ib_create_ah, 3775 .dealloc_pd = mlx5_ib_dealloc_pd, 3776 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3777 .del_gid = mlx5_ib_del_gid, 3778 .dereg_mr = mlx5_ib_dereg_mr, 3779 .destroy_ah = mlx5_ib_destroy_ah, 3780 .destroy_cq = mlx5_ib_destroy_cq, 3781 .destroy_qp = mlx5_ib_destroy_qp, 3782 .destroy_srq = mlx5_ib_destroy_srq, 3783 .detach_mcast = mlx5_ib_mcg_detach, 3784 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3785 .drain_rq = mlx5_ib_drain_rq, 3786 .drain_sq = mlx5_ib_drain_sq, 3787 .device_group = &mlx5_attr_group, 3788 .enable_driver = mlx5_ib_enable_driver, 3789 .get_dev_fw_str = get_dev_fw_str, 3790 .get_dma_mr = mlx5_ib_get_dma_mr, 3791 .get_link_layer = mlx5_ib_port_link_layer, 3792 .map_mr_sg = mlx5_ib_map_mr_sg, 3793 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3794 .mmap = mlx5_ib_mmap, 3795 .mmap_free = mlx5_ib_mmap_free, 3796 .modify_cq = mlx5_ib_modify_cq, 3797 .modify_device = mlx5_ib_modify_device, 3798 .modify_port = mlx5_ib_modify_port, 3799 .modify_qp = mlx5_ib_modify_qp, 3800 .modify_srq = mlx5_ib_modify_srq, 3801 .poll_cq = mlx5_ib_poll_cq, 3802 .post_recv = mlx5_ib_post_recv_nodrain, 3803 .post_send = mlx5_ib_post_send_nodrain, 3804 .post_srq_recv = mlx5_ib_post_srq_recv, 3805 .process_mad = mlx5_ib_process_mad, 3806 .query_ah = mlx5_ib_query_ah, 3807 .query_device = mlx5_ib_query_device, 3808 .query_gid = mlx5_ib_query_gid, 3809 .query_pkey = mlx5_ib_query_pkey, 3810 .query_qp = mlx5_ib_query_qp, 3811 .query_srq = mlx5_ib_query_srq, 3812 .query_ucontext = mlx5_ib_query_ucontext, 3813 .reg_user_mr = mlx5_ib_reg_user_mr, 3814 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3815 .req_notify_cq = mlx5_ib_arm_cq, 3816 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3817 .resize_cq = mlx5_ib_resize_cq, 3818 3819 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3820 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3821 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3822 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3823 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3824 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3825 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3826 }; 3827 3828 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3829 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3830 }; 3831 3832 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3833 .get_vf_config = mlx5_ib_get_vf_config, 3834 .get_vf_guid = mlx5_ib_get_vf_guid, 3835 .get_vf_stats = mlx5_ib_get_vf_stats, 3836 .set_vf_guid = mlx5_ib_set_vf_guid, 3837 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3838 }; 3839 3840 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3841 .alloc_mw = mlx5_ib_alloc_mw, 3842 .dealloc_mw = mlx5_ib_dealloc_mw, 3843 3844 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3845 }; 3846 3847 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3848 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3849 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3850 3851 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3852 }; 3853 3854 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3855 { 3856 struct mlx5_core_dev *mdev = dev->mdev; 3857 struct mlx5_var_table *var_table = &dev->var_table; 3858 u8 log_doorbell_bar_size; 3859 u8 log_doorbell_stride; 3860 u64 bar_size; 3861 3862 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3863 log_doorbell_bar_size); 3864 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3865 log_doorbell_stride); 3866 var_table->hw_start_addr = dev->mdev->bar_addr + 3867 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3868 doorbell_bar_offset); 3869 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3870 var_table->stride_size = 1ULL << log_doorbell_stride; 3871 var_table->num_var_hw_entries = div_u64(bar_size, 3872 var_table->stride_size); 3873 mutex_init(&var_table->bitmap_lock); 3874 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3875 GFP_KERNEL); 3876 return (var_table->bitmap) ? 0 : -ENOMEM; 3877 } 3878 3879 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3880 { 3881 bitmap_free(dev->var_table.bitmap); 3882 } 3883 3884 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3885 { 3886 struct mlx5_core_dev *mdev = dev->mdev; 3887 int err; 3888 3889 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3890 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3891 ib_set_device_ops(&dev->ib_dev, 3892 &mlx5_ib_dev_ipoib_enhanced_ops); 3893 3894 if (mlx5_core_is_pf(mdev)) 3895 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3896 3897 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3898 3899 if (MLX5_CAP_GEN(mdev, imaicl)) 3900 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3901 3902 if (MLX5_CAP_GEN(mdev, xrc)) 3903 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3904 3905 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3906 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3907 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3908 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3909 3910 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3911 3912 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3913 dev->ib_dev.driver_def = mlx5_ib_defs; 3914 3915 err = init_node_data(dev); 3916 if (err) 3917 return err; 3918 3919 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3920 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3921 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3922 mutex_init(&dev->lb.mutex); 3923 3924 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3925 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3926 err = mlx5_ib_init_var_table(dev); 3927 if (err) 3928 return err; 3929 } 3930 3931 dev->ib_dev.use_cq_dim = true; 3932 3933 return 0; 3934 } 3935 3936 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3937 .get_port_immutable = mlx5_port_immutable, 3938 .query_port = mlx5_ib_query_port, 3939 }; 3940 3941 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3942 { 3943 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3944 return 0; 3945 } 3946 3947 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3948 .get_port_immutable = mlx5_port_rep_immutable, 3949 .query_port = mlx5_ib_rep_query_port, 3950 .query_pkey = mlx5_ib_rep_query_pkey, 3951 }; 3952 3953 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3954 { 3955 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3956 return 0; 3957 } 3958 3959 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3960 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3961 .create_wq = mlx5_ib_create_wq, 3962 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3963 .destroy_wq = mlx5_ib_destroy_wq, 3964 .get_netdev = mlx5_ib_get_netdev, 3965 .modify_wq = mlx5_ib_modify_wq, 3966 3967 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3968 ib_rwq_ind_tbl), 3969 }; 3970 3971 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3972 { 3973 struct mlx5_core_dev *mdev = dev->mdev; 3974 enum rdma_link_layer ll; 3975 int port_type_cap; 3976 u32 port_num = 0; 3977 int err; 3978 3979 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3980 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3981 3982 if (ll == IB_LINK_LAYER_ETHERNET) { 3983 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3984 3985 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3986 3987 /* Register only for native ports */ 3988 mlx5_mdev_netdev_track(dev, port_num); 3989 3990 err = mlx5_enable_eth(dev); 3991 if (err) 3992 goto cleanup; 3993 } 3994 3995 return 0; 3996 cleanup: 3997 mlx5_mdev_netdev_untrack(dev, port_num); 3998 return err; 3999 } 4000 4001 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4002 { 4003 struct mlx5_core_dev *mdev = dev->mdev; 4004 enum rdma_link_layer ll; 4005 int port_type_cap; 4006 u32 port_num; 4007 4008 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4009 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4010 4011 if (ll == IB_LINK_LAYER_ETHERNET) { 4012 mlx5_disable_eth(dev); 4013 4014 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4015 mlx5_mdev_netdev_untrack(dev, port_num); 4016 } 4017 } 4018 4019 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4020 { 4021 mlx5_ib_init_cong_debugfs(dev, 4022 mlx5_core_native_port_num(dev->mdev) - 1); 4023 return 0; 4024 } 4025 4026 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4027 { 4028 mlx5_ib_cleanup_cong_debugfs(dev, 4029 mlx5_core_native_port_num(dev->mdev) - 1); 4030 } 4031 4032 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4033 { 4034 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4035 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4036 } 4037 4038 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4039 { 4040 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4041 } 4042 4043 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4044 { 4045 int err; 4046 4047 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4048 if (err) 4049 return err; 4050 4051 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4052 if (err) 4053 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4054 4055 return err; 4056 } 4057 4058 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4059 { 4060 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4061 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4062 } 4063 4064 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4065 { 4066 const char *name; 4067 4068 if (!mlx5_lag_is_active(dev->mdev)) 4069 name = "mlx5_%d"; 4070 else 4071 name = "mlx5_bond_%d"; 4072 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4073 } 4074 4075 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4076 { 4077 mlx5_mkey_cache_cleanup(dev); 4078 mlx5r_umr_resource_cleanup(dev); 4079 } 4080 4081 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4082 { 4083 ib_unregister_device(&dev->ib_dev); 4084 } 4085 4086 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4087 { 4088 int ret; 4089 4090 ret = mlx5r_umr_resource_init(dev); 4091 if (ret) 4092 return ret; 4093 4094 ret = mlx5_mkey_cache_init(dev); 4095 if (ret) 4096 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4097 return ret; 4098 } 4099 4100 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4101 { 4102 struct dentry *root; 4103 4104 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4105 return 0; 4106 4107 mutex_init(&dev->delay_drop.lock); 4108 dev->delay_drop.dev = dev; 4109 dev->delay_drop.activate = false; 4110 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4111 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4112 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4113 atomic_set(&dev->delay_drop.events_cnt, 0); 4114 4115 if (!mlx5_debugfs_root) 4116 return 0; 4117 4118 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4119 dev->delay_drop.dir_debugfs = root; 4120 4121 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4122 &dev->delay_drop.events_cnt); 4123 debugfs_create_atomic_t("num_rqs", 0400, root, 4124 &dev->delay_drop.rqs_cnt); 4125 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4126 &fops_delay_drop_timeout); 4127 return 0; 4128 } 4129 4130 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4131 { 4132 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4133 return; 4134 4135 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4136 if (!dev->delay_drop.dir_debugfs) 4137 return; 4138 4139 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4140 dev->delay_drop.dir_debugfs = NULL; 4141 } 4142 4143 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4144 { 4145 dev->mdev_events.notifier_call = mlx5_ib_event; 4146 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4147 4148 mlx5r_macsec_event_register(dev); 4149 4150 return 0; 4151 } 4152 4153 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4154 { 4155 mlx5r_macsec_event_unregister(dev); 4156 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4157 } 4158 4159 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4160 const struct mlx5_ib_profile *profile, 4161 int stage) 4162 { 4163 dev->ib_active = false; 4164 4165 /* Number of stages to cleanup */ 4166 while (stage) { 4167 stage--; 4168 if (profile->stage[stage].cleanup) 4169 profile->stage[stage].cleanup(dev); 4170 } 4171 4172 kfree(dev->port); 4173 ib_dealloc_device(&dev->ib_dev); 4174 } 4175 4176 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4177 const struct mlx5_ib_profile *profile) 4178 { 4179 int err; 4180 int i; 4181 4182 dev->profile = profile; 4183 4184 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4185 if (profile->stage[i].init) { 4186 err = profile->stage[i].init(dev); 4187 if (err) 4188 goto err_out; 4189 } 4190 } 4191 4192 dev->ib_active = true; 4193 return 0; 4194 4195 err_out: 4196 /* Clean up stages which were initialized */ 4197 while (i) { 4198 i--; 4199 if (profile->stage[i].cleanup) 4200 profile->stage[i].cleanup(dev); 4201 } 4202 return -ENOMEM; 4203 } 4204 4205 static const struct mlx5_ib_profile pf_profile = { 4206 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4207 mlx5_ib_stage_init_init, 4208 mlx5_ib_stage_init_cleanup), 4209 STAGE_CREATE(MLX5_IB_STAGE_FS, 4210 mlx5_ib_fs_init, 4211 mlx5_ib_fs_cleanup), 4212 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4213 mlx5_ib_stage_caps_init, 4214 mlx5_ib_stage_caps_cleanup), 4215 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4216 mlx5_ib_stage_non_default_cb, 4217 NULL), 4218 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4219 mlx5_ib_roce_init, 4220 mlx5_ib_roce_cleanup), 4221 STAGE_CREATE(MLX5_IB_STAGE_QP, 4222 mlx5_init_qp_table, 4223 mlx5_cleanup_qp_table), 4224 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4225 mlx5_init_srq_table, 4226 mlx5_cleanup_srq_table), 4227 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4228 mlx5_ib_dev_res_init, 4229 mlx5_ib_dev_res_cleanup), 4230 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4231 mlx5_ib_stage_dev_notifier_init, 4232 mlx5_ib_stage_dev_notifier_cleanup), 4233 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4234 mlx5_ib_odp_init_one, 4235 mlx5_ib_odp_cleanup_one), 4236 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4237 mlx5_ib_counters_init, 4238 mlx5_ib_counters_cleanup), 4239 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4240 mlx5_ib_stage_cong_debugfs_init, 4241 mlx5_ib_stage_cong_debugfs_cleanup), 4242 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4243 mlx5_ib_stage_uar_init, 4244 mlx5_ib_stage_uar_cleanup), 4245 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4246 mlx5_ib_stage_bfrag_init, 4247 mlx5_ib_stage_bfrag_cleanup), 4248 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4249 NULL, 4250 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4251 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4252 mlx5_ib_devx_init, 4253 mlx5_ib_devx_cleanup), 4254 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4255 mlx5_ib_stage_ib_reg_init, 4256 mlx5_ib_stage_ib_reg_cleanup), 4257 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4258 mlx5_ib_stage_post_ib_reg_umr_init, 4259 NULL), 4260 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4261 mlx5_ib_stage_delay_drop_init, 4262 mlx5_ib_stage_delay_drop_cleanup), 4263 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4264 mlx5_ib_restrack_init, 4265 NULL), 4266 }; 4267 4268 const struct mlx5_ib_profile raw_eth_profile = { 4269 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4270 mlx5_ib_stage_init_init, 4271 mlx5_ib_stage_init_cleanup), 4272 STAGE_CREATE(MLX5_IB_STAGE_FS, 4273 mlx5_ib_fs_init, 4274 mlx5_ib_fs_cleanup), 4275 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4276 mlx5_ib_stage_caps_init, 4277 mlx5_ib_stage_caps_cleanup), 4278 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4279 mlx5_ib_stage_raw_eth_non_default_cb, 4280 NULL), 4281 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4282 mlx5_ib_roce_init, 4283 mlx5_ib_roce_cleanup), 4284 STAGE_CREATE(MLX5_IB_STAGE_QP, 4285 mlx5_init_qp_table, 4286 mlx5_cleanup_qp_table), 4287 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4288 mlx5_init_srq_table, 4289 mlx5_cleanup_srq_table), 4290 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4291 mlx5_ib_dev_res_init, 4292 mlx5_ib_dev_res_cleanup), 4293 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4294 mlx5_ib_stage_dev_notifier_init, 4295 mlx5_ib_stage_dev_notifier_cleanup), 4296 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4297 mlx5_ib_counters_init, 4298 mlx5_ib_counters_cleanup), 4299 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4300 mlx5_ib_stage_cong_debugfs_init, 4301 mlx5_ib_stage_cong_debugfs_cleanup), 4302 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4303 mlx5_ib_stage_uar_init, 4304 mlx5_ib_stage_uar_cleanup), 4305 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4306 mlx5_ib_stage_bfrag_init, 4307 mlx5_ib_stage_bfrag_cleanup), 4308 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4309 NULL, 4310 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4311 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4312 mlx5_ib_devx_init, 4313 mlx5_ib_devx_cleanup), 4314 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4315 mlx5_ib_stage_ib_reg_init, 4316 mlx5_ib_stage_ib_reg_cleanup), 4317 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4318 mlx5_ib_stage_post_ib_reg_umr_init, 4319 NULL), 4320 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4321 mlx5_ib_stage_delay_drop_init, 4322 mlx5_ib_stage_delay_drop_cleanup), 4323 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4324 mlx5_ib_restrack_init, 4325 NULL), 4326 }; 4327 4328 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4329 const struct auxiliary_device_id *id) 4330 { 4331 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4332 struct mlx5_core_dev *mdev = idev->mdev; 4333 struct mlx5_ib_multiport_info *mpi; 4334 struct mlx5_ib_dev *dev; 4335 bool bound = false; 4336 int err; 4337 4338 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4339 if (!mpi) 4340 return -ENOMEM; 4341 4342 mpi->mdev = mdev; 4343 err = mlx5_query_nic_vport_system_image_guid(mdev, 4344 &mpi->sys_image_guid); 4345 if (err) { 4346 kfree(mpi); 4347 return err; 4348 } 4349 4350 mutex_lock(&mlx5_ib_multiport_mutex); 4351 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4352 if (dev->sys_image_guid == mpi->sys_image_guid) 4353 bound = mlx5_ib_bind_slave_port(dev, mpi); 4354 4355 if (bound) { 4356 rdma_roce_rescan_device(&dev->ib_dev); 4357 mpi->ibdev->ib_active = true; 4358 break; 4359 } 4360 } 4361 4362 if (!bound) { 4363 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4364 dev_dbg(mdev->device, 4365 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4366 } 4367 mutex_unlock(&mlx5_ib_multiport_mutex); 4368 4369 auxiliary_set_drvdata(adev, mpi); 4370 return 0; 4371 } 4372 4373 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4374 { 4375 struct mlx5_ib_multiport_info *mpi; 4376 4377 mpi = auxiliary_get_drvdata(adev); 4378 mutex_lock(&mlx5_ib_multiport_mutex); 4379 if (mpi->ibdev) 4380 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4381 else 4382 list_del(&mpi->list); 4383 mutex_unlock(&mlx5_ib_multiport_mutex); 4384 kfree(mpi); 4385 } 4386 4387 static int mlx5r_probe(struct auxiliary_device *adev, 4388 const struct auxiliary_device_id *id) 4389 { 4390 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4391 struct mlx5_core_dev *mdev = idev->mdev; 4392 const struct mlx5_ib_profile *profile; 4393 int port_type_cap, num_ports, ret; 4394 enum rdma_link_layer ll; 4395 struct mlx5_ib_dev *dev; 4396 4397 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4398 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4399 4400 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4401 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4402 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4403 if (!dev) 4404 return -ENOMEM; 4405 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4406 GFP_KERNEL); 4407 if (!dev->port) { 4408 ib_dealloc_device(&dev->ib_dev); 4409 return -ENOMEM; 4410 } 4411 4412 dev->mdev = mdev; 4413 dev->num_ports = num_ports; 4414 4415 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4416 profile = &raw_eth_profile; 4417 else 4418 profile = &pf_profile; 4419 4420 ret = __mlx5_ib_add(dev, profile); 4421 if (ret) { 4422 kfree(dev->port); 4423 ib_dealloc_device(&dev->ib_dev); 4424 return ret; 4425 } 4426 4427 auxiliary_set_drvdata(adev, dev); 4428 return 0; 4429 } 4430 4431 static void mlx5r_remove(struct auxiliary_device *adev) 4432 { 4433 struct mlx5_ib_dev *dev; 4434 4435 dev = auxiliary_get_drvdata(adev); 4436 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4437 } 4438 4439 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4440 { .name = MLX5_ADEV_NAME ".multiport", }, 4441 {}, 4442 }; 4443 4444 static const struct auxiliary_device_id mlx5r_id_table[] = { 4445 { .name = MLX5_ADEV_NAME ".rdma", }, 4446 {}, 4447 }; 4448 4449 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4450 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4451 4452 static struct auxiliary_driver mlx5r_mp_driver = { 4453 .name = "multiport", 4454 .probe = mlx5r_mp_probe, 4455 .remove = mlx5r_mp_remove, 4456 .id_table = mlx5r_mp_id_table, 4457 }; 4458 4459 static struct auxiliary_driver mlx5r_driver = { 4460 .name = "rdma", 4461 .probe = mlx5r_probe, 4462 .remove = mlx5r_remove, 4463 .id_table = mlx5r_id_table, 4464 }; 4465 4466 static int __init mlx5_ib_init(void) 4467 { 4468 int ret; 4469 4470 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4471 if (!xlt_emergency_page) 4472 return -ENOMEM; 4473 4474 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4475 if (!mlx5_ib_event_wq) { 4476 free_page((unsigned long)xlt_emergency_page); 4477 return -ENOMEM; 4478 } 4479 4480 ret = mlx5_ib_qp_event_init(); 4481 if (ret) 4482 goto qp_event_err; 4483 4484 mlx5_ib_odp_init(); 4485 ret = mlx5r_rep_init(); 4486 if (ret) 4487 goto rep_err; 4488 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4489 if (ret) 4490 goto mp_err; 4491 ret = auxiliary_driver_register(&mlx5r_driver); 4492 if (ret) 4493 goto drv_err; 4494 return 0; 4495 4496 drv_err: 4497 auxiliary_driver_unregister(&mlx5r_mp_driver); 4498 mp_err: 4499 mlx5r_rep_cleanup(); 4500 rep_err: 4501 mlx5_ib_qp_event_cleanup(); 4502 qp_event_err: 4503 destroy_workqueue(mlx5_ib_event_wq); 4504 free_page((unsigned long)xlt_emergency_page); 4505 return ret; 4506 } 4507 4508 static void __exit mlx5_ib_cleanup(void) 4509 { 4510 auxiliary_driver_unregister(&mlx5r_driver); 4511 auxiliary_driver_unregister(&mlx5r_mp_driver); 4512 mlx5r_rep_cleanup(); 4513 4514 mlx5_ib_qp_event_cleanup(); 4515 destroy_workqueue(mlx5_ib_event_wq); 4516 free_page((unsigned long)xlt_emergency_page); 4517 } 4518 4519 module_init(mlx5_ib_init); 4520 module_exit(mlx5_ib_cleanup); 4521