1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/mlx5/driver.h> 28 #include <linux/list.h> 29 #include <rdma/ib_smi.h> 30 #include <rdma/ib_umem_odp.h> 31 #include <rdma/lag.h> 32 #include <linux/in.h> 33 #include <linux/etherdevice.h> 34 #include "mlx5_ib.h" 35 #include "ib_rep.h" 36 #include "cmd.h" 37 #include "devx.h" 38 #include "dm.h" 39 #include "fs.h" 40 #include "srq.h" 41 #include "qp.h" 42 #include "wr.h" 43 #include "restrack.h" 44 #include "counters.h" 45 #include "umr.h" 46 #include <rdma/uverbs_std_types.h> 47 #include <rdma/uverbs_ioctl.h> 48 #include <rdma/mlx5_user_ioctl_verbs.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 #include <rdma/ib_ucaps.h> 51 #include "macsec.h" 52 #include "data_direct.h" 53 #include "dmah.h" 54 55 #define UVERBS_MODULE_NAME mlx5_ib 56 #include <rdma/uverbs_named_ioctl.h> 57 58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 59 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 62 struct mlx5_ib_event_work { 63 struct work_struct work; 64 union { 65 struct mlx5_ib_dev *dev; 66 struct mlx5_ib_multiport_info *mpi; 67 }; 68 bool is_slave; 69 unsigned int event; 70 void *param; 71 }; 72 73 enum { 74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 75 }; 76 77 static struct workqueue_struct *mlx5_ib_event_wq; 78 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 79 static LIST_HEAD(mlx5_ib_dev_list); 80 /* 81 * This mutex should be held when accessing either of the above lists 82 */ 83 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 84 85 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 86 { 87 struct mlx5_ib_dev *dev; 88 89 mutex_lock(&mlx5_ib_multiport_mutex); 90 dev = mpi->ibdev; 91 mutex_unlock(&mlx5_ib_multiport_mutex); 92 return dev; 93 } 94 95 static enum rdma_link_layer 96 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 97 { 98 switch (port_type_cap) { 99 case MLX5_CAP_PORT_TYPE_IB: 100 return IB_LINK_LAYER_INFINIBAND; 101 case MLX5_CAP_PORT_TYPE_ETH: 102 return IB_LINK_LAYER_ETHERNET; 103 default: 104 return IB_LINK_LAYER_UNSPECIFIED; 105 } 106 } 107 108 static enum rdma_link_layer 109 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 110 { 111 struct mlx5_ib_dev *dev = to_mdev(device); 112 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 113 114 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 115 } 116 117 static int get_port_state(struct ib_device *ibdev, 118 u32 port_num, 119 enum ib_port_state *state) 120 { 121 struct ib_port_attr attr; 122 int ret; 123 124 memset(&attr, 0, sizeof(attr)); 125 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 126 if (!ret) 127 *state = attr.state; 128 return ret; 129 } 130 131 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 132 struct net_device *ndev, 133 struct net_device *upper, 134 u32 *port_num) 135 { 136 struct net_device *rep_ndev; 137 struct mlx5_ib_port *port; 138 int i; 139 140 for (i = 0; i < dev->num_ports; i++) { 141 port = &dev->port[i]; 142 if (!port->rep) 143 continue; 144 145 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 146 *port_num = i + 1; 147 return &port->roce; 148 } 149 150 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 151 continue; 152 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 153 if (rep_ndev && rep_ndev == ndev) { 154 dev_put(rep_ndev); 155 *port_num = i + 1; 156 return &port->roce; 157 } 158 159 dev_put(rep_ndev); 160 } 161 162 return NULL; 163 } 164 165 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 166 struct net_device *ndev, 167 struct net_device *upper, 168 struct net_device *ib_ndev) 169 { 170 if (!dev->ib_active) 171 return false; 172 173 /* Event is about our upper device */ 174 if (upper == ndev) 175 return true; 176 177 /* RDMA device is not in lag and not in switchdev */ 178 if (!dev->is_rep && !upper && ndev == ib_ndev) 179 return true; 180 181 /* RDMA devie is in switchdev */ 182 if (dev->is_rep && ndev == ib_ndev) 183 return true; 184 185 return false; 186 } 187 188 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 189 { 190 struct mlx5_ib_port *port; 191 int i; 192 193 for (i = 0; i < ibdev->num_ports; i++) { 194 port = &ibdev->port[i]; 195 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 196 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 197 } 198 } 199 200 return NULL; 201 } 202 203 static int mlx5_netdev_event(struct notifier_block *this, 204 unsigned long event, void *ptr) 205 { 206 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 207 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 208 u32 port_num = roce->native_port_num; 209 struct net_device *ib_ndev = NULL; 210 struct mlx5_core_dev *mdev; 211 struct mlx5_ib_dev *ibdev; 212 213 ibdev = roce->dev; 214 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 215 if (!mdev) 216 return NOTIFY_DONE; 217 218 switch (event) { 219 case NETDEV_REGISTER: 220 /* Should already be registered during the load */ 221 if (ibdev->is_rep) 222 break; 223 224 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 225 /* Exit if already registered */ 226 if (ib_ndev) 227 goto put_ndev; 228 229 if (ndev->dev.parent == mdev->device) 230 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 231 break; 232 233 case NETDEV_UNREGISTER: 234 /* In case of reps, ib device goes away before the netdevs */ 235 if (ibdev->is_rep) 236 break; 237 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 238 if (ib_ndev == ndev) 239 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 240 goto put_ndev; 241 242 case NETDEV_CHANGE: 243 case NETDEV_UP: 244 case NETDEV_DOWN: { 245 struct net_device *upper = NULL; 246 247 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 248 !mlx5_core_mp_enabled(mdev)) 249 return NOTIFY_DONE; 250 251 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 252 struct net_device *lag_ndev; 253 254 if(mlx5_lag_is_roce(mdev)) 255 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 256 else /* sriov lag */ 257 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 258 259 if (lag_ndev) { 260 upper = netdev_master_upper_dev_get(lag_ndev); 261 dev_put(lag_ndev); 262 } else { 263 goto done; 264 } 265 } 266 267 if (ibdev->is_rep) 268 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 269 if (!roce) 270 return NOTIFY_DONE; 271 272 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 273 274 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 275 struct ib_event ibev = { }; 276 enum ib_port_state port_state; 277 278 if (get_port_state(&ibdev->ib_dev, port_num, 279 &port_state)) 280 goto put_ndev; 281 282 if (roce->last_port_state == port_state) 283 goto put_ndev; 284 285 roce->last_port_state = port_state; 286 ibev.device = &ibdev->ib_dev; 287 if (port_state == IB_PORT_DOWN) 288 ibev.event = IB_EVENT_PORT_ERR; 289 else if (port_state == IB_PORT_ACTIVE) 290 ibev.event = IB_EVENT_PORT_ACTIVE; 291 else 292 goto put_ndev; 293 294 ibev.element.port_num = port_num; 295 ib_dispatch_event(&ibev); 296 } 297 break; 298 } 299 300 default: 301 break; 302 } 303 put_ndev: 304 dev_put(ib_ndev); 305 done: 306 mlx5_ib_put_native_port_mdev(ibdev, port_num); 307 return NOTIFY_DONE; 308 } 309 310 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 311 u32 ib_port_num, 312 u32 *native_port_num) 313 { 314 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 315 ib_port_num); 316 struct mlx5_core_dev *mdev = NULL; 317 struct mlx5_ib_multiport_info *mpi; 318 struct mlx5_ib_port *port; 319 320 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 321 if (native_port_num) 322 *native_port_num = smi_to_native_portnum(ibdev, 323 ib_port_num); 324 return ibdev->mdev; 325 326 } 327 328 if (!mlx5_core_mp_enabled(ibdev->mdev) || 329 ll != IB_LINK_LAYER_ETHERNET) { 330 if (native_port_num) 331 *native_port_num = ib_port_num; 332 return ibdev->mdev; 333 } 334 335 if (native_port_num) 336 *native_port_num = 1; 337 338 port = &ibdev->port[ib_port_num - 1]; 339 spin_lock(&port->mp.mpi_lock); 340 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 341 if (mpi && !mpi->unaffiliate) { 342 mdev = mpi->mdev; 343 /* If it's the master no need to refcount, it'll exist 344 * as long as the ib_dev exists. 345 */ 346 if (!mpi->is_master) 347 mpi->mdev_refcnt++; 348 } 349 spin_unlock(&port->mp.mpi_lock); 350 351 return mdev; 352 } 353 354 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 355 { 356 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 357 port_num); 358 struct mlx5_ib_multiport_info *mpi; 359 struct mlx5_ib_port *port; 360 361 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 362 return; 363 364 port = &ibdev->port[port_num - 1]; 365 366 spin_lock(&port->mp.mpi_lock); 367 mpi = ibdev->port[port_num - 1].mp.mpi; 368 if (mpi->is_master) 369 goto out; 370 371 mpi->mdev_refcnt--; 372 if (mpi->unaffiliate) 373 complete(&mpi->unref_comp); 374 out: 375 spin_unlock(&port->mp.mpi_lock); 376 } 377 378 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 379 u16 *active_speed, u8 *active_width) 380 { 381 switch (eth_proto_oper) { 382 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 383 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 384 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 385 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 386 *active_width = IB_WIDTH_1X; 387 *active_speed = IB_SPEED_SDR; 388 break; 389 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_EDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 409 *active_width = IB_WIDTH_4X; 410 *active_speed = IB_SPEED_QDR; 411 break; 412 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 415 *active_width = IB_WIDTH_1X; 416 *active_speed = IB_SPEED_HDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 419 *active_width = IB_WIDTH_4X; 420 *active_speed = IB_SPEED_FDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 return 0; 434 } 435 436 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 437 u8 *active_width) 438 { 439 switch (eth_proto_oper) { 440 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 441 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 442 *active_width = IB_WIDTH_1X; 443 *active_speed = IB_SPEED_SDR; 444 break; 445 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 446 *active_width = IB_WIDTH_1X; 447 *active_speed = IB_SPEED_DDR; 448 break; 449 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 450 *active_width = IB_WIDTH_1X; 451 *active_speed = IB_SPEED_QDR; 452 break; 453 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 454 *active_width = IB_WIDTH_4X; 455 *active_speed = IB_SPEED_QDR; 456 break; 457 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 458 *active_width = IB_WIDTH_1X; 459 *active_speed = IB_SPEED_EDR; 460 break; 461 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 462 *active_width = IB_WIDTH_2X; 463 *active_speed = IB_SPEED_EDR; 464 break; 465 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 466 *active_width = IB_WIDTH_1X; 467 *active_speed = IB_SPEED_HDR; 468 break; 469 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 470 *active_width = IB_WIDTH_4X; 471 *active_speed = IB_SPEED_EDR; 472 break; 473 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 474 *active_width = IB_WIDTH_2X; 475 *active_speed = IB_SPEED_HDR; 476 break; 477 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 478 *active_width = IB_WIDTH_1X; 479 *active_speed = IB_SPEED_NDR; 480 break; 481 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 482 *active_width = IB_WIDTH_4X; 483 *active_speed = IB_SPEED_HDR; 484 break; 485 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 486 *active_width = IB_WIDTH_2X; 487 *active_speed = IB_SPEED_NDR; 488 break; 489 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 490 *active_width = IB_WIDTH_1X; 491 *active_speed = IB_SPEED_XDR; 492 break; 493 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 494 *active_width = IB_WIDTH_8X; 495 *active_speed = IB_SPEED_HDR; 496 break; 497 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 498 *active_width = IB_WIDTH_4X; 499 *active_speed = IB_SPEED_NDR; 500 break; 501 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 502 *active_width = IB_WIDTH_2X; 503 *active_speed = IB_SPEED_XDR; 504 break; 505 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 506 *active_width = IB_WIDTH_8X; 507 *active_speed = IB_SPEED_NDR; 508 break; 509 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 510 *active_width = IB_WIDTH_4X; 511 *active_speed = IB_SPEED_XDR; 512 break; 513 default: 514 return -EINVAL; 515 } 516 517 return 0; 518 } 519 520 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 521 u8 *active_width, bool ext) 522 { 523 return ext ? 524 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 525 active_width) : 526 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 527 active_width); 528 } 529 530 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 531 struct ib_port_attr *props) 532 { 533 struct mlx5_ib_dev *dev = to_mdev(device); 534 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 535 struct mlx5_core_dev *mdev; 536 struct net_device *ndev, *upper; 537 enum ib_mtu ndev_ib_mtu; 538 bool put_mdev = true; 539 u32 eth_prot_oper; 540 u32 mdev_port_num; 541 bool ext; 542 int err; 543 544 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 545 if (!mdev) { 546 /* This means the port isn't affiliated yet. Get the 547 * info for the master port instead. 548 */ 549 put_mdev = false; 550 mdev = dev->mdev; 551 mdev_port_num = 1; 552 port_num = 1; 553 } 554 555 /* Possible bad flows are checked before filling out props so in case 556 * of an error it will still be zeroed out. 557 * Use native port in case of reps 558 */ 559 if (dev->is_rep) 560 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 561 1, 0); 562 else 563 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 564 mdev_port_num, 0); 565 if (err) 566 goto out; 567 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 568 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 569 570 props->active_width = IB_WIDTH_4X; 571 props->active_speed = IB_SPEED_QDR; 572 573 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 574 &props->active_width, ext); 575 576 if (!dev->is_rep && dev->mdev->roce.roce_en) { 577 u16 qkey_viol_cntr; 578 579 props->port_cap_flags |= IB_PORT_CM_SUP; 580 props->ip_gids = true; 581 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 582 roce_address_table_size); 583 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 584 props->qkey_viol_cntr = qkey_viol_cntr; 585 } 586 props->max_mtu = IB_MTU_4096; 587 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 588 props->pkey_tbl_len = 1; 589 props->state = IB_PORT_DOWN; 590 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 591 592 /* If this is a stub query for an unaffiliated port stop here */ 593 if (!put_mdev) 594 goto out; 595 596 ndev = ib_device_get_netdev(device, port_num); 597 if (!ndev) 598 goto out; 599 600 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 601 rcu_read_lock(); 602 upper = netdev_master_upper_dev_get_rcu(ndev); 603 if (upper) { 604 dev_put(ndev); 605 ndev = upper; 606 dev_hold(ndev); 607 } 608 rcu_read_unlock(); 609 } 610 611 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 612 props->state = IB_PORT_ACTIVE; 613 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 614 } 615 616 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 617 618 dev_put(ndev); 619 620 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 621 out: 622 if (put_mdev) 623 mlx5_ib_put_native_port_mdev(dev, port_num); 624 return err; 625 } 626 627 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 628 unsigned int index, const union ib_gid *gid, 629 const struct ib_gid_attr *attr) 630 { 631 enum ib_gid_type gid_type; 632 u16 vlan_id = 0xffff; 633 u8 roce_version = 0; 634 u8 roce_l3_type = 0; 635 u8 mac[ETH_ALEN]; 636 int ret; 637 638 gid_type = attr->gid_type; 639 if (gid) { 640 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 641 if (ret) 642 return ret; 643 } 644 645 switch (gid_type) { 646 case IB_GID_TYPE_ROCE: 647 roce_version = MLX5_ROCE_VERSION_1; 648 break; 649 case IB_GID_TYPE_ROCE_UDP_ENCAP: 650 roce_version = MLX5_ROCE_VERSION_2; 651 if (gid && ipv6_addr_v4mapped((void *)gid)) 652 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 653 else 654 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 655 break; 656 657 default: 658 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 659 } 660 661 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 662 roce_l3_type, gid->raw, mac, 663 vlan_id < VLAN_CFI_MASK, vlan_id, 664 port_num); 665 } 666 667 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 668 __always_unused void **context) 669 { 670 int ret; 671 672 ret = mlx5r_add_gid_macsec_operations(attr); 673 if (ret) 674 return ret; 675 676 return set_roce_addr(to_mdev(attr->device), attr->port_num, 677 attr->index, &attr->gid, attr); 678 } 679 680 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 681 __always_unused void **context) 682 { 683 int ret; 684 685 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 686 attr->index, NULL, attr); 687 if (ret) 688 return ret; 689 690 mlx5r_del_gid_macsec_operations(attr); 691 return 0; 692 } 693 694 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 695 const struct ib_gid_attr *attr) 696 { 697 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 698 return 0; 699 700 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 701 } 702 703 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 704 { 705 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 706 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 707 return 0; 708 } 709 710 enum { 711 MLX5_VPORT_ACCESS_METHOD_MAD, 712 MLX5_VPORT_ACCESS_METHOD_HCA, 713 MLX5_VPORT_ACCESS_METHOD_NIC, 714 }; 715 716 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 717 { 718 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 719 return MLX5_VPORT_ACCESS_METHOD_MAD; 720 721 if (mlx5_ib_port_link_layer(ibdev, 1) == 722 IB_LINK_LAYER_ETHERNET) 723 return MLX5_VPORT_ACCESS_METHOD_NIC; 724 725 return MLX5_VPORT_ACCESS_METHOD_HCA; 726 } 727 728 static void get_atomic_caps(struct mlx5_ib_dev *dev, 729 u8 atomic_size_qp, 730 struct ib_device_attr *props) 731 { 732 u8 tmp; 733 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 734 u8 atomic_req_8B_endianness_mode = 735 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 736 737 /* Check if HW supports 8 bytes standard atomic operations and capable 738 * of host endianness respond 739 */ 740 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 741 if (((atomic_operations & tmp) == tmp) && 742 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 743 (atomic_req_8B_endianness_mode)) { 744 props->atomic_cap = IB_ATOMIC_HCA; 745 } else { 746 props->atomic_cap = IB_ATOMIC_NONE; 747 } 748 } 749 750 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 751 struct ib_device_attr *props) 752 { 753 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 754 755 get_atomic_caps(dev, atomic_size_qp, props); 756 } 757 758 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 759 __be64 *sys_image_guid) 760 { 761 struct mlx5_ib_dev *dev = to_mdev(ibdev); 762 struct mlx5_core_dev *mdev = dev->mdev; 763 u64 tmp; 764 int err; 765 766 switch (mlx5_get_vport_access_method(ibdev)) { 767 case MLX5_VPORT_ACCESS_METHOD_MAD: 768 return mlx5_query_mad_ifc_system_image_guid(ibdev, 769 sys_image_guid); 770 771 case MLX5_VPORT_ACCESS_METHOD_HCA: 772 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 773 break; 774 775 case MLX5_VPORT_ACCESS_METHOD_NIC: 776 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 777 break; 778 779 default: 780 return -EINVAL; 781 } 782 783 if (!err) 784 *sys_image_guid = cpu_to_be64(tmp); 785 786 return err; 787 788 } 789 790 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 791 u16 *max_pkeys) 792 { 793 struct mlx5_ib_dev *dev = to_mdev(ibdev); 794 struct mlx5_core_dev *mdev = dev->mdev; 795 796 switch (mlx5_get_vport_access_method(ibdev)) { 797 case MLX5_VPORT_ACCESS_METHOD_MAD: 798 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 799 800 case MLX5_VPORT_ACCESS_METHOD_HCA: 801 case MLX5_VPORT_ACCESS_METHOD_NIC: 802 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 803 pkey_table_size)); 804 return 0; 805 806 default: 807 return -EINVAL; 808 } 809 } 810 811 static int mlx5_query_vendor_id(struct ib_device *ibdev, 812 u32 *vendor_id) 813 { 814 struct mlx5_ib_dev *dev = to_mdev(ibdev); 815 816 switch (mlx5_get_vport_access_method(ibdev)) { 817 case MLX5_VPORT_ACCESS_METHOD_MAD: 818 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 819 820 case MLX5_VPORT_ACCESS_METHOD_HCA: 821 case MLX5_VPORT_ACCESS_METHOD_NIC: 822 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 823 824 default: 825 return -EINVAL; 826 } 827 } 828 829 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 830 __be64 *node_guid) 831 { 832 u64 tmp; 833 int err; 834 835 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 836 case MLX5_VPORT_ACCESS_METHOD_MAD: 837 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 838 839 case MLX5_VPORT_ACCESS_METHOD_HCA: 840 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 841 break; 842 843 case MLX5_VPORT_ACCESS_METHOD_NIC: 844 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 845 break; 846 847 default: 848 return -EINVAL; 849 } 850 851 if (!err) 852 *node_guid = cpu_to_be64(tmp); 853 854 return err; 855 } 856 857 struct mlx5_reg_node_desc { 858 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 859 }; 860 861 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 862 { 863 struct mlx5_reg_node_desc in; 864 865 if (mlx5_use_mad_ifc(dev)) 866 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 867 868 memset(&in, 0, sizeof(in)); 869 870 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 871 sizeof(struct mlx5_reg_node_desc), 872 MLX5_REG_NODE_DESC, 0, 0); 873 } 874 875 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 876 struct mlx5_ib_query_device_resp *resp) 877 { 878 struct mlx5_eswitch *esw = mdev->priv.eswitch; 879 u16 vport = mlx5_eswitch_manager_vport(mdev); 880 881 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 882 vport); 883 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 884 } 885 886 static int mlx5_ib_query_device(struct ib_device *ibdev, 887 struct ib_device_attr *props, 888 struct ib_udata *uhw) 889 { 890 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 891 struct mlx5_ib_dev *dev = to_mdev(ibdev); 892 struct mlx5_core_dev *mdev = dev->mdev; 893 int err = -ENOMEM; 894 int max_sq_desc; 895 int max_rq_sg; 896 int max_sq_sg; 897 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 898 bool raw_support = !mlx5_core_mp_enabled(mdev); 899 struct mlx5_ib_query_device_resp resp = {}; 900 size_t resp_len; 901 u64 max_tso; 902 903 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 904 if (uhw_outlen && uhw_outlen < resp_len) 905 return -EINVAL; 906 907 resp.response_length = resp_len; 908 909 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 910 return -EINVAL; 911 912 memset(props, 0, sizeof(*props)); 913 err = mlx5_query_system_image_guid(ibdev, 914 &props->sys_image_guid); 915 if (err) 916 return err; 917 918 props->max_pkeys = dev->pkey_table_len; 919 920 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 921 if (err) 922 return err; 923 924 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 925 (fw_rev_min(dev->mdev) << 16) | 926 fw_rev_sub(dev->mdev); 927 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 928 IB_DEVICE_PORT_ACTIVE_EVENT | 929 IB_DEVICE_SYS_IMAGE_GUID | 930 IB_DEVICE_RC_RNR_NAK_GEN; 931 932 if (MLX5_CAP_GEN(mdev, pkv)) 933 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 934 if (MLX5_CAP_GEN(mdev, qkv)) 935 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 936 if (MLX5_CAP_GEN(mdev, apm)) 937 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 938 if (MLX5_CAP_GEN(mdev, xrc)) 939 props->device_cap_flags |= IB_DEVICE_XRC; 940 if (MLX5_CAP_GEN(mdev, imaicl)) { 941 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 942 IB_DEVICE_MEM_WINDOW_TYPE_2B; 943 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 944 /* We support 'Gappy' memory registration too */ 945 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 946 } 947 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 948 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 949 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 950 if (MLX5_CAP_GEN(mdev, sho)) { 951 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 952 /* At this stage no support for signature handover */ 953 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 954 IB_PROT_T10DIF_TYPE_2 | 955 IB_PROT_T10DIF_TYPE_3; 956 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 957 IB_GUARD_T10DIF_CSUM; 958 } 959 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 960 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 961 962 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 963 if (MLX5_CAP_ETH(mdev, csum_cap)) { 964 /* Legacy bit to support old userspace libraries */ 965 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 966 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 967 } 968 969 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 970 props->raw_packet_caps |= 971 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 972 973 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 974 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 975 if (max_tso) { 976 resp.tso_caps.max_tso = 1 << max_tso; 977 resp.tso_caps.supported_qpts |= 978 1 << IB_QPT_RAW_PACKET; 979 resp.response_length += sizeof(resp.tso_caps); 980 } 981 } 982 983 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 984 resp.rss_caps.rx_hash_function = 985 MLX5_RX_HASH_FUNC_TOEPLITZ; 986 resp.rss_caps.rx_hash_fields_mask = 987 MLX5_RX_HASH_SRC_IPV4 | 988 MLX5_RX_HASH_DST_IPV4 | 989 MLX5_RX_HASH_SRC_IPV6 | 990 MLX5_RX_HASH_DST_IPV6 | 991 MLX5_RX_HASH_SRC_PORT_TCP | 992 MLX5_RX_HASH_DST_PORT_TCP | 993 MLX5_RX_HASH_SRC_PORT_UDP | 994 MLX5_RX_HASH_DST_PORT_UDP | 995 MLX5_RX_HASH_INNER; 996 resp.response_length += sizeof(resp.rss_caps); 997 } 998 } else { 999 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1000 resp.response_length += sizeof(resp.tso_caps); 1001 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1002 resp.response_length += sizeof(resp.rss_caps); 1003 } 1004 1005 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1006 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1007 props->kernel_cap_flags |= IBK_UD_TSO; 1008 } 1009 1010 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1011 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1012 raw_support) 1013 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1014 1015 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1016 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1017 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1018 1019 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1020 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1021 raw_support) { 1022 /* Legacy bit to support old userspace libraries */ 1023 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1024 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1025 } 1026 1027 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1028 props->max_dm_size = 1029 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1030 } 1031 1032 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1033 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1034 1035 if (MLX5_CAP_GEN(mdev, end_pad)) 1036 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1037 1038 props->vendor_part_id = mdev->pdev->device; 1039 props->hw_ver = mdev->pdev->revision; 1040 1041 props->max_mr_size = ~0ull; 1042 props->page_size_cap = ~(min_page_size - 1); 1043 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1044 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1045 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1046 sizeof(struct mlx5_wqe_data_seg); 1047 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1048 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1049 sizeof(struct mlx5_wqe_raddr_seg)) / 1050 sizeof(struct mlx5_wqe_data_seg); 1051 props->max_send_sge = max_sq_sg; 1052 props->max_recv_sge = max_rq_sg; 1053 props->max_sge_rd = MLX5_MAX_SGE_RD; 1054 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1055 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1056 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1057 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1058 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1059 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1060 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1061 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1062 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1063 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1064 props->max_srq_sge = max_rq_sg - 1; 1065 props->max_fast_reg_page_list_len = 1066 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1067 props->max_pi_fast_reg_page_list_len = 1068 props->max_fast_reg_page_list_len / 2; 1069 props->max_sgl_rd = 1070 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1071 get_atomic_caps_qp(dev, props); 1072 props->masked_atomic_cap = IB_ATOMIC_NONE; 1073 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1074 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1075 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1076 props->max_mcast_grp; 1077 props->max_ah = INT_MAX; 1078 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1079 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1080 1081 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1082 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1083 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1084 props->odp_caps = dev->odp_caps; 1085 if (!uhw) { 1086 /* ODP for kernel QPs is not implemented for receive 1087 * WQEs and SRQ WQEs 1088 */ 1089 props->odp_caps.per_transport_caps.rc_odp_caps &= 1090 ~(IB_ODP_SUPPORT_READ | 1091 IB_ODP_SUPPORT_SRQ_RECV); 1092 props->odp_caps.per_transport_caps.uc_odp_caps &= 1093 ~(IB_ODP_SUPPORT_READ | 1094 IB_ODP_SUPPORT_SRQ_RECV); 1095 props->odp_caps.per_transport_caps.ud_odp_caps &= 1096 ~(IB_ODP_SUPPORT_READ | 1097 IB_ODP_SUPPORT_SRQ_RECV); 1098 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1099 ~(IB_ODP_SUPPORT_READ | 1100 IB_ODP_SUPPORT_SRQ_RECV); 1101 } 1102 } 1103 1104 if (mlx5_core_is_vf(mdev)) 1105 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1106 1107 if (mlx5_ib_port_link_layer(ibdev, 1) == 1108 IB_LINK_LAYER_ETHERNET && raw_support) { 1109 props->rss_caps.max_rwq_indirection_tables = 1110 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1111 props->rss_caps.max_rwq_indirection_table_size = 1112 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1113 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1114 props->max_wq_type_rq = 1115 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1116 } 1117 1118 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1119 props->tm_caps.max_num_tags = 1120 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1121 props->tm_caps.max_ops = 1122 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1123 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1124 } 1125 1126 if (MLX5_CAP_GEN(mdev, tag_matching) && 1127 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1128 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1129 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1130 } 1131 1132 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1133 props->cq_caps.max_cq_moderation_count = 1134 MLX5_MAX_CQ_COUNT; 1135 props->cq_caps.max_cq_moderation_period = 1136 MLX5_MAX_CQ_PERIOD; 1137 } 1138 1139 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1140 resp.response_length += sizeof(resp.cqe_comp_caps); 1141 1142 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1143 resp.cqe_comp_caps.max_num = 1144 MLX5_CAP_GEN(dev->mdev, 1145 cqe_compression_max_num); 1146 1147 resp.cqe_comp_caps.supported_format = 1148 MLX5_IB_CQE_RES_FORMAT_HASH | 1149 MLX5_IB_CQE_RES_FORMAT_CSUM; 1150 1151 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1152 resp.cqe_comp_caps.supported_format |= 1153 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1154 } 1155 } 1156 1157 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1158 raw_support) { 1159 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1160 MLX5_CAP_GEN(mdev, qos)) { 1161 resp.packet_pacing_caps.qp_rate_limit_max = 1162 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1163 resp.packet_pacing_caps.qp_rate_limit_min = 1164 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1165 resp.packet_pacing_caps.supported_qpts |= 1166 1 << IB_QPT_RAW_PACKET; 1167 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1168 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1169 resp.packet_pacing_caps.cap_flags |= 1170 MLX5_IB_PP_SUPPORT_BURST; 1171 } 1172 resp.response_length += sizeof(resp.packet_pacing_caps); 1173 } 1174 1175 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1176 uhw_outlen) { 1177 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1178 resp.mlx5_ib_support_multi_pkt_send_wqes = 1179 MLX5_IB_ALLOW_MPW; 1180 1181 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1182 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1183 MLX5_IB_SUPPORT_EMPW; 1184 1185 resp.response_length += 1186 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1187 } 1188 1189 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1190 resp.response_length += sizeof(resp.flags); 1191 1192 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1193 resp.flags |= 1194 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1195 1196 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1197 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1198 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1199 resp.flags |= 1200 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1201 1202 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1203 1204 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1205 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1206 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1207 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1208 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1209 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1210 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1211 } 1212 1213 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1214 resp.response_length += sizeof(resp.sw_parsing_caps); 1215 if (MLX5_CAP_ETH(mdev, swp)) { 1216 resp.sw_parsing_caps.sw_parsing_offloads |= 1217 MLX5_IB_SW_PARSING; 1218 1219 if (MLX5_CAP_ETH(mdev, swp_csum)) 1220 resp.sw_parsing_caps.sw_parsing_offloads |= 1221 MLX5_IB_SW_PARSING_CSUM; 1222 1223 if (MLX5_CAP_ETH(mdev, swp_lso)) 1224 resp.sw_parsing_caps.sw_parsing_offloads |= 1225 MLX5_IB_SW_PARSING_LSO; 1226 1227 if (resp.sw_parsing_caps.sw_parsing_offloads) 1228 resp.sw_parsing_caps.supported_qpts = 1229 BIT(IB_QPT_RAW_PACKET); 1230 } 1231 } 1232 1233 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1234 raw_support) { 1235 resp.response_length += sizeof(resp.striding_rq_caps); 1236 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1237 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1238 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1239 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1240 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1241 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1242 resp.striding_rq_caps 1243 .min_single_wqe_log_num_of_strides = 1244 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1245 else 1246 resp.striding_rq_caps 1247 .min_single_wqe_log_num_of_strides = 1248 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1249 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1250 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1251 resp.striding_rq_caps.supported_qpts = 1252 BIT(IB_QPT_RAW_PACKET); 1253 } 1254 } 1255 1256 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1257 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1258 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1259 resp.tunnel_offloads_caps |= 1260 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1261 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1262 resp.tunnel_offloads_caps |= 1263 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1264 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1265 resp.tunnel_offloads_caps |= 1266 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1267 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1268 resp.tunnel_offloads_caps |= 1269 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1270 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1271 resp.tunnel_offloads_caps |= 1272 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1273 } 1274 1275 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1276 resp.response_length += sizeof(resp.dci_streams_caps); 1277 1278 resp.dci_streams_caps.max_log_num_concurent = 1279 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1280 1281 resp.dci_streams_caps.max_log_num_errored = 1282 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1283 } 1284 1285 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1286 resp.response_length += sizeof(resp.reserved); 1287 1288 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1289 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1290 1291 resp.response_length += sizeof(resp.reg_c0); 1292 1293 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1294 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1295 fill_esw_mgr_reg_c0(mdev, &resp); 1296 } 1297 1298 if (uhw_outlen) { 1299 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1300 1301 if (err) 1302 return err; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1309 u8 *ib_width) 1310 { 1311 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1312 1313 if (active_width & MLX5_PTYS_WIDTH_1X) 1314 *ib_width = IB_WIDTH_1X; 1315 else if (active_width & MLX5_PTYS_WIDTH_2X) 1316 *ib_width = IB_WIDTH_2X; 1317 else if (active_width & MLX5_PTYS_WIDTH_4X) 1318 *ib_width = IB_WIDTH_4X; 1319 else if (active_width & MLX5_PTYS_WIDTH_8X) 1320 *ib_width = IB_WIDTH_8X; 1321 else if (active_width & MLX5_PTYS_WIDTH_12X) 1322 *ib_width = IB_WIDTH_12X; 1323 else { 1324 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1325 active_width); 1326 *ib_width = IB_WIDTH_4X; 1327 } 1328 1329 return; 1330 } 1331 1332 static int mlx5_mtu_to_ib_mtu(int mtu) 1333 { 1334 switch (mtu) { 1335 case 256: return 1; 1336 case 512: return 2; 1337 case 1024: return 3; 1338 case 2048: return 4; 1339 case 4096: return 5; 1340 default: 1341 pr_warn("invalid mtu\n"); 1342 return -1; 1343 } 1344 } 1345 1346 enum ib_max_vl_num { 1347 __IB_MAX_VL_0 = 1, 1348 __IB_MAX_VL_0_1 = 2, 1349 __IB_MAX_VL_0_3 = 3, 1350 __IB_MAX_VL_0_7 = 4, 1351 __IB_MAX_VL_0_14 = 5, 1352 }; 1353 1354 enum mlx5_vl_hw_cap { 1355 MLX5_VL_HW_0 = 1, 1356 MLX5_VL_HW_0_1 = 2, 1357 MLX5_VL_HW_0_2 = 3, 1358 MLX5_VL_HW_0_3 = 4, 1359 MLX5_VL_HW_0_4 = 5, 1360 MLX5_VL_HW_0_5 = 6, 1361 MLX5_VL_HW_0_6 = 7, 1362 MLX5_VL_HW_0_7 = 8, 1363 MLX5_VL_HW_0_14 = 15 1364 }; 1365 1366 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1367 u8 *max_vl_num) 1368 { 1369 switch (vl_hw_cap) { 1370 case MLX5_VL_HW_0: 1371 *max_vl_num = __IB_MAX_VL_0; 1372 break; 1373 case MLX5_VL_HW_0_1: 1374 *max_vl_num = __IB_MAX_VL_0_1; 1375 break; 1376 case MLX5_VL_HW_0_3: 1377 *max_vl_num = __IB_MAX_VL_0_3; 1378 break; 1379 case MLX5_VL_HW_0_7: 1380 *max_vl_num = __IB_MAX_VL_0_7; 1381 break; 1382 case MLX5_VL_HW_0_14: 1383 *max_vl_num = __IB_MAX_VL_0_14; 1384 break; 1385 1386 default: 1387 return -EINVAL; 1388 } 1389 1390 return 0; 1391 } 1392 1393 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1394 struct ib_port_attr *props) 1395 { 1396 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1397 struct mlx5_core_dev *mdev = dev->mdev; 1398 struct mlx5_hca_vport_context *rep; 1399 u8 vl_hw_cap, plane_index = 0; 1400 u16 max_mtu; 1401 u16 oper_mtu; 1402 int err; 1403 u16 ib_link_width_oper; 1404 1405 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1406 if (!rep) { 1407 err = -ENOMEM; 1408 goto out; 1409 } 1410 1411 /* props being zeroed by the caller, avoid zeroing it here */ 1412 1413 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1414 plane_index = port; 1415 port = smi_to_native_portnum(dev, port); 1416 } 1417 1418 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1419 if (err) 1420 goto out; 1421 1422 props->lid = rep->lid; 1423 props->lmc = rep->lmc; 1424 props->sm_lid = rep->sm_lid; 1425 props->sm_sl = rep->sm_sl; 1426 props->state = rep->vport_state; 1427 props->phys_state = rep->port_physical_state; 1428 1429 props->port_cap_flags = rep->cap_mask1; 1430 if (dev->num_plane) { 1431 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1432 props->port_cap_flags &= ~IB_PORT_SM; 1433 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1434 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1435 1436 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1437 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1438 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1439 props->bad_pkey_cntr = rep->pkey_violation_counter; 1440 props->qkey_viol_cntr = rep->qkey_violation_counter; 1441 props->subnet_timeout = rep->subnet_timeout; 1442 props->init_type_reply = rep->init_type_reply; 1443 1444 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1445 props->port_cap_flags2 = rep->cap_mask2; 1446 1447 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1448 &props->active_speed, port, plane_index); 1449 if (err) 1450 goto out; 1451 1452 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1453 1454 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1455 1456 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1457 1458 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1459 1460 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1461 1462 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1463 if (err) 1464 goto out; 1465 1466 err = translate_max_vl_num(ibdev, vl_hw_cap, 1467 &props->max_vl_num); 1468 out: 1469 kfree(rep); 1470 return err; 1471 } 1472 1473 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1474 struct ib_port_attr *props) 1475 { 1476 unsigned int count; 1477 int ret; 1478 1479 switch (mlx5_get_vport_access_method(ibdev)) { 1480 case MLX5_VPORT_ACCESS_METHOD_MAD: 1481 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1482 break; 1483 1484 case MLX5_VPORT_ACCESS_METHOD_HCA: 1485 ret = mlx5_query_hca_port(ibdev, port, props); 1486 break; 1487 1488 case MLX5_VPORT_ACCESS_METHOD_NIC: 1489 ret = mlx5_query_port_roce(ibdev, port, props); 1490 break; 1491 1492 default: 1493 ret = -EINVAL; 1494 } 1495 1496 if (!ret && props) { 1497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1498 struct mlx5_core_dev *mdev; 1499 bool put_mdev = true; 1500 1501 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1502 if (!mdev) { 1503 /* If the port isn't affiliated yet query the master. 1504 * The master and slave will have the same values. 1505 */ 1506 mdev = dev->mdev; 1507 port = 1; 1508 put_mdev = false; 1509 } 1510 count = mlx5_core_reserved_gids_count(mdev); 1511 if (put_mdev) 1512 mlx5_ib_put_native_port_mdev(dev, port); 1513 props->gid_tbl_len -= count; 1514 } 1515 return ret; 1516 } 1517 1518 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1519 struct ib_port_attr *props) 1520 { 1521 return mlx5_query_port_roce(ibdev, port, props); 1522 } 1523 1524 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1525 u16 *pkey) 1526 { 1527 /* Default special Pkey for representor device port as per the 1528 * IB specification 1.3 section 10.9.1.2. 1529 */ 1530 *pkey = 0xffff; 1531 return 0; 1532 } 1533 1534 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1535 union ib_gid *gid) 1536 { 1537 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1538 struct mlx5_core_dev *mdev = dev->mdev; 1539 1540 switch (mlx5_get_vport_access_method(ibdev)) { 1541 case MLX5_VPORT_ACCESS_METHOD_MAD: 1542 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1543 1544 case MLX5_VPORT_ACCESS_METHOD_HCA: 1545 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1546 1547 default: 1548 return -EINVAL; 1549 } 1550 1551 } 1552 1553 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1554 u16 index, u16 *pkey) 1555 { 1556 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1557 struct mlx5_core_dev *mdev; 1558 bool put_mdev = true; 1559 u32 mdev_port_num; 1560 int err; 1561 1562 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1563 if (!mdev) { 1564 /* The port isn't affiliated yet, get the PKey from the master 1565 * port. For RoCE the PKey tables will be the same. 1566 */ 1567 put_mdev = false; 1568 mdev = dev->mdev; 1569 mdev_port_num = 1; 1570 } 1571 1572 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1573 index, pkey); 1574 if (put_mdev) 1575 mlx5_ib_put_native_port_mdev(dev, port); 1576 1577 return err; 1578 } 1579 1580 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1581 u16 *pkey) 1582 { 1583 switch (mlx5_get_vport_access_method(ibdev)) { 1584 case MLX5_VPORT_ACCESS_METHOD_MAD: 1585 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1586 1587 case MLX5_VPORT_ACCESS_METHOD_HCA: 1588 case MLX5_VPORT_ACCESS_METHOD_NIC: 1589 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1590 default: 1591 return -EINVAL; 1592 } 1593 } 1594 1595 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1596 struct ib_device_modify *props) 1597 { 1598 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1599 struct mlx5_reg_node_desc in; 1600 struct mlx5_reg_node_desc out; 1601 int err; 1602 1603 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1604 return -EOPNOTSUPP; 1605 1606 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1607 return 0; 1608 1609 /* 1610 * If possible, pass node desc to FW, so it can generate 1611 * a 144 trap. If cmd fails, just ignore. 1612 */ 1613 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1614 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1615 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1616 if (err) 1617 return err; 1618 1619 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1620 1621 return err; 1622 } 1623 1624 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1625 u32 value) 1626 { 1627 struct mlx5_hca_vport_context ctx = {}; 1628 struct mlx5_core_dev *mdev; 1629 u32 mdev_port_num; 1630 int err; 1631 1632 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1633 if (!mdev) 1634 return -ENODEV; 1635 1636 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1637 if (err) 1638 goto out; 1639 1640 if (~ctx.cap_mask1_perm & mask) { 1641 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1642 mask, ctx.cap_mask1_perm); 1643 err = -EINVAL; 1644 goto out; 1645 } 1646 1647 ctx.cap_mask1 = value; 1648 ctx.cap_mask1_perm = mask; 1649 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1650 0, &ctx); 1651 1652 out: 1653 mlx5_ib_put_native_port_mdev(dev, port_num); 1654 1655 return err; 1656 } 1657 1658 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1659 struct ib_port_modify *props) 1660 { 1661 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1662 struct ib_port_attr attr; 1663 u32 tmp; 1664 int err; 1665 u32 change_mask; 1666 u32 value; 1667 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1668 IB_LINK_LAYER_INFINIBAND); 1669 1670 /* CM layer calls ib_modify_port() regardless of the link layer. For 1671 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1672 */ 1673 if (!is_ib) 1674 return 0; 1675 1676 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1677 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1678 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1679 return set_port_caps_atomic(dev, port, change_mask, value); 1680 } 1681 1682 mutex_lock(&dev->cap_mask_mutex); 1683 1684 err = ib_query_port(ibdev, port, &attr); 1685 if (err) 1686 goto out; 1687 1688 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1689 ~props->clr_port_cap_mask; 1690 1691 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1692 1693 out: 1694 mutex_unlock(&dev->cap_mask_mutex); 1695 return err; 1696 } 1697 1698 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1699 { 1700 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1701 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1702 } 1703 1704 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1705 { 1706 /* Large page with non 4k uar support might limit the dynamic size */ 1707 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1708 return MLX5_MIN_DYN_BFREGS; 1709 1710 return MLX5_MAX_DYN_BFREGS; 1711 } 1712 1713 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1714 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1715 struct mlx5_bfreg_info *bfregi) 1716 { 1717 int uars_per_sys_page; 1718 int bfregs_per_sys_page; 1719 int ref_bfregs = req->total_num_bfregs; 1720 1721 if (req->total_num_bfregs == 0) 1722 return -EINVAL; 1723 1724 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1725 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1726 1727 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1728 return -ENOMEM; 1729 1730 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1731 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1732 /* This holds the required static allocation asked by the user */ 1733 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1734 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1735 return -EINVAL; 1736 1737 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1738 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1739 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1740 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1741 1742 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1743 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1744 lib_uar_4k ? "yes" : "no", ref_bfregs, 1745 req->total_num_bfregs, bfregi->total_num_bfregs, 1746 bfregi->num_sys_pages); 1747 1748 return 0; 1749 } 1750 1751 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1752 { 1753 struct mlx5_bfreg_info *bfregi; 1754 int err; 1755 int i; 1756 1757 bfregi = &context->bfregi; 1758 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1759 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1760 context->devx_uid); 1761 if (err) 1762 goto error; 1763 1764 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1765 } 1766 1767 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1768 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1769 1770 return 0; 1771 1772 error: 1773 for (--i; i >= 0; i--) 1774 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1775 context->devx_uid)) 1776 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1777 1778 return err; 1779 } 1780 1781 static void deallocate_uars(struct mlx5_ib_dev *dev, 1782 struct mlx5_ib_ucontext *context) 1783 { 1784 struct mlx5_bfreg_info *bfregi; 1785 int i; 1786 1787 bfregi = &context->bfregi; 1788 for (i = 0; i < bfregi->num_sys_pages; i++) 1789 if (i < bfregi->num_static_sys_pages || 1790 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1791 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1792 context->devx_uid); 1793 } 1794 1795 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1796 struct mlx5_core_dev *slave) 1797 { 1798 int err; 1799 1800 err = mlx5_nic_vport_update_local_lb(master, true); 1801 if (err) 1802 return err; 1803 1804 err = mlx5_nic_vport_update_local_lb(slave, true); 1805 if (err) 1806 goto out; 1807 1808 return 0; 1809 1810 out: 1811 mlx5_nic_vport_update_local_lb(master, false); 1812 return err; 1813 } 1814 1815 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 1816 struct mlx5_core_dev *slave) 1817 { 1818 mlx5_nic_vport_update_local_lb(slave, false); 1819 mlx5_nic_vport_update_local_lb(master, false); 1820 } 1821 1822 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1823 { 1824 int err = 0; 1825 1826 mutex_lock(&dev->lb.mutex); 1827 if (td) 1828 dev->lb.user_td++; 1829 if (qp) 1830 dev->lb.qps++; 1831 1832 if (dev->lb.user_td == 2 || 1833 dev->lb.qps == 1) { 1834 if (!dev->lb.enabled) { 1835 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1836 dev->lb.enabled = true; 1837 } 1838 } 1839 1840 mutex_unlock(&dev->lb.mutex); 1841 1842 return err; 1843 } 1844 1845 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1846 { 1847 mutex_lock(&dev->lb.mutex); 1848 if (td) 1849 dev->lb.user_td--; 1850 if (qp) 1851 dev->lb.qps--; 1852 1853 if (dev->lb.user_td == 1 && 1854 dev->lb.qps == 0) { 1855 if (dev->lb.enabled) { 1856 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1857 dev->lb.enabled = false; 1858 } 1859 } 1860 1861 mutex_unlock(&dev->lb.mutex); 1862 } 1863 1864 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1865 u16 uid) 1866 { 1867 int err; 1868 1869 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1870 return 0; 1871 1872 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1873 if (err) 1874 return err; 1875 1876 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1877 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1878 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1879 return err; 1880 1881 return mlx5_ib_enable_lb(dev, true, false); 1882 } 1883 1884 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1885 u16 uid) 1886 { 1887 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1888 return; 1889 1890 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1891 1892 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1893 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1894 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1895 return; 1896 1897 mlx5_ib_disable_lb(dev, true, false); 1898 } 1899 1900 static int set_ucontext_resp(struct ib_ucontext *uctx, 1901 struct mlx5_ib_alloc_ucontext_resp *resp) 1902 { 1903 struct ib_device *ibdev = uctx->device; 1904 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1905 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1906 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1907 1908 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1909 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1910 resp->comp_mask |= 1911 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1912 } 1913 1914 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1915 if (mlx5_wc_support_get(dev->mdev)) 1916 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1917 log_bf_reg_size); 1918 resp->cache_line_size = cache_line_size(); 1919 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1920 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1921 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1922 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1923 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1924 resp->cqe_version = context->cqe_version; 1925 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1926 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1927 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1928 MLX5_CAP_GEN(dev->mdev, 1929 num_of_uars_per_page) : 1; 1930 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1931 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1932 resp->num_ports = dev->num_ports; 1933 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1934 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1935 1936 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1937 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1938 resp->eth_min_inline++; 1939 } 1940 1941 if (dev->mdev->clock_info) 1942 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1943 1944 /* 1945 * We don't want to expose information from the PCI bar that is located 1946 * after 4096 bytes, so if the arch only supports larger pages, let's 1947 * pretend we don't support reading the HCA's core clock. This is also 1948 * forced by mmap function. 1949 */ 1950 if (PAGE_SIZE <= 4096) { 1951 resp->comp_mask |= 1952 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1953 resp->hca_core_clock_offset = 1954 offsetof(struct mlx5_init_seg, 1955 internal_timer_h) % PAGE_SIZE; 1956 } 1957 1958 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1959 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1960 1961 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1962 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1963 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1964 resp->comp_mask |= 1965 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1966 1967 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1968 1969 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1970 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1971 1972 resp->comp_mask |= 1973 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1974 1975 return 0; 1976 } 1977 1978 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 1979 { 1980 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 1981 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 1982 } 1983 1984 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1985 struct ib_udata *udata) 1986 { 1987 struct ib_device *ibdev = uctx->device; 1988 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1989 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1990 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1991 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1992 struct mlx5_bfreg_info *bfregi; 1993 int ver; 1994 int err; 1995 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1996 max_cqe_version); 1997 bool lib_uar_4k; 1998 bool lib_uar_dyn; 1999 2000 if (!dev->ib_active) 2001 return -EAGAIN; 2002 2003 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2004 ver = 0; 2005 else if (udata->inlen >= min_req_v2) 2006 ver = 2; 2007 else 2008 return -EINVAL; 2009 2010 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2011 if (err) 2012 return err; 2013 2014 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2015 return -EOPNOTSUPP; 2016 2017 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2018 return -EOPNOTSUPP; 2019 2020 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2021 MLX5_NON_FP_BFREGS_PER_UAR); 2022 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2023 return -EINVAL; 2024 2025 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2026 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2027 if (err < 0) 2028 goto out_ctx; 2029 context->devx_uid = err; 2030 2031 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2032 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2033 context->devx_uid); 2034 if (err) 2035 goto out_devx; 2036 } 2037 } 2038 2039 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2040 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2041 bfregi = &context->bfregi; 2042 2043 if (lib_uar_dyn) { 2044 bfregi->lib_uar_dyn = lib_uar_dyn; 2045 goto uar_done; 2046 } 2047 2048 /* updates req->total_num_bfregs */ 2049 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2050 if (err) 2051 goto out_ucap; 2052 2053 mutex_init(&bfregi->lock); 2054 bfregi->lib_uar_4k = lib_uar_4k; 2055 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2056 GFP_KERNEL); 2057 if (!bfregi->count) { 2058 err = -ENOMEM; 2059 goto out_ucap; 2060 } 2061 2062 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2063 sizeof(*bfregi->sys_pages), 2064 GFP_KERNEL); 2065 if (!bfregi->sys_pages) { 2066 err = -ENOMEM; 2067 goto out_count; 2068 } 2069 2070 err = allocate_uars(dev, context); 2071 if (err) 2072 goto out_sys_pages; 2073 2074 uar_done: 2075 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2076 context->devx_uid); 2077 if (err) 2078 goto out_uars; 2079 2080 INIT_LIST_HEAD(&context->db_page_list); 2081 mutex_init(&context->db_page_mutex); 2082 2083 context->cqe_version = min_t(__u8, 2084 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2085 req.max_cqe_version); 2086 2087 err = set_ucontext_resp(uctx, &resp); 2088 if (err) 2089 goto out_mdev; 2090 2091 resp.response_length = min(udata->outlen, sizeof(resp)); 2092 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2093 if (err) 2094 goto out_mdev; 2095 2096 bfregi->ver = ver; 2097 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2098 context->lib_caps = req.lib_caps; 2099 print_lib_caps(dev, context->lib_caps); 2100 2101 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2102 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2103 2104 atomic_set(&context->tx_port_affinity, 2105 atomic_add_return( 2106 1, &dev->port[port].roce.tx_port_affinity)); 2107 } 2108 2109 return 0; 2110 2111 out_mdev: 2112 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2113 2114 out_uars: 2115 deallocate_uars(dev, context); 2116 2117 out_sys_pages: 2118 kfree(bfregi->sys_pages); 2119 2120 out_count: 2121 kfree(bfregi->count); 2122 2123 out_ucap: 2124 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2125 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2126 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2127 2128 out_devx: 2129 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2130 mlx5_ib_devx_destroy(dev, context->devx_uid); 2131 2132 out_ctx: 2133 return err; 2134 } 2135 2136 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2137 struct uverbs_attr_bundle *attrs) 2138 { 2139 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2140 int ret; 2141 2142 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2143 if (ret) 2144 return ret; 2145 2146 uctx_resp.response_length = 2147 min_t(size_t, 2148 uverbs_attr_get_len(attrs, 2149 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2150 sizeof(uctx_resp)); 2151 2152 ret = uverbs_copy_to_struct_or_zero(attrs, 2153 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2154 &uctx_resp, 2155 sizeof(uctx_resp)); 2156 return ret; 2157 } 2158 2159 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2160 { 2161 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2162 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2163 struct mlx5_bfreg_info *bfregi; 2164 2165 bfregi = &context->bfregi; 2166 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2167 2168 deallocate_uars(dev, context); 2169 kfree(bfregi->sys_pages); 2170 kfree(bfregi->count); 2171 2172 if (context->devx_uid) { 2173 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2174 mlx5_cmd_remove_privileged_uid(dev->mdev, 2175 context->devx_uid); 2176 mlx5_ib_devx_destroy(dev, context->devx_uid); 2177 } 2178 } 2179 2180 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2181 int uar_idx) 2182 { 2183 int fw_uars_per_page; 2184 2185 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2186 2187 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2188 } 2189 2190 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2191 int uar_idx) 2192 { 2193 unsigned int fw_uars_per_page; 2194 2195 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2196 MLX5_UARS_IN_PAGE : 1; 2197 2198 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2199 } 2200 2201 static int get_command(unsigned long offset) 2202 { 2203 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2204 } 2205 2206 static int get_arg(unsigned long offset) 2207 { 2208 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2209 } 2210 2211 static int get_index(unsigned long offset) 2212 { 2213 return get_arg(offset); 2214 } 2215 2216 /* Index resides in an extra byte to enable larger values than 255 */ 2217 static int get_extended_index(unsigned long offset) 2218 { 2219 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2220 } 2221 2222 2223 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2224 { 2225 } 2226 2227 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2228 { 2229 switch (cmd) { 2230 case MLX5_IB_MMAP_WC_PAGE: 2231 return "WC"; 2232 case MLX5_IB_MMAP_REGULAR_PAGE: 2233 return "best effort WC"; 2234 case MLX5_IB_MMAP_NC_PAGE: 2235 return "NC"; 2236 case MLX5_IB_MMAP_DEVICE_MEM: 2237 return "Device Memory"; 2238 default: 2239 return "Unknown"; 2240 } 2241 } 2242 2243 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2244 struct vm_area_struct *vma, 2245 struct mlx5_ib_ucontext *context) 2246 { 2247 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2248 !(vma->vm_flags & VM_SHARED)) 2249 return -EINVAL; 2250 2251 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2252 return -EOPNOTSUPP; 2253 2254 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2255 return -EPERM; 2256 vm_flags_clear(vma, VM_MAYWRITE); 2257 2258 if (!dev->mdev->clock_info) 2259 return -EOPNOTSUPP; 2260 2261 return vm_insert_page(vma, vma->vm_start, 2262 virt_to_page(dev->mdev->clock_info)); 2263 } 2264 2265 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2266 { 2267 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2268 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2269 struct mlx5_var_table *var_table = &dev->var_table; 2270 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2271 2272 switch (mentry->mmap_flag) { 2273 case MLX5_IB_MMAP_TYPE_MEMIC: 2274 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2275 mlx5_ib_dm_mmap_free(dev, mentry); 2276 break; 2277 case MLX5_IB_MMAP_TYPE_VAR: 2278 mutex_lock(&var_table->bitmap_lock); 2279 clear_bit(mentry->page_idx, var_table->bitmap); 2280 mutex_unlock(&var_table->bitmap_lock); 2281 kfree(mentry); 2282 break; 2283 case MLX5_IB_MMAP_TYPE_UAR_WC: 2284 case MLX5_IB_MMAP_TYPE_UAR_NC: 2285 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2286 context->devx_uid); 2287 kfree(mentry); 2288 break; 2289 default: 2290 WARN_ON(true); 2291 } 2292 } 2293 2294 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2295 struct vm_area_struct *vma, 2296 struct mlx5_ib_ucontext *context) 2297 { 2298 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2299 int err; 2300 unsigned long idx; 2301 phys_addr_t pfn; 2302 pgprot_t prot; 2303 u32 bfreg_dyn_idx = 0; 2304 u32 uar_index; 2305 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2306 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2307 bfregi->num_static_sys_pages; 2308 2309 if (bfregi->lib_uar_dyn) 2310 return -EINVAL; 2311 2312 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2313 return -EINVAL; 2314 2315 if (dyn_uar) 2316 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2317 else 2318 idx = get_index(vma->vm_pgoff); 2319 2320 if (idx >= max_valid_idx) { 2321 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2322 idx, max_valid_idx); 2323 return -EINVAL; 2324 } 2325 2326 switch (cmd) { 2327 case MLX5_IB_MMAP_WC_PAGE: 2328 case MLX5_IB_MMAP_ALLOC_WC: 2329 case MLX5_IB_MMAP_REGULAR_PAGE: 2330 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2331 prot = pgprot_writecombine(vma->vm_page_prot); 2332 break; 2333 case MLX5_IB_MMAP_NC_PAGE: 2334 prot = pgprot_noncached(vma->vm_page_prot); 2335 break; 2336 default: 2337 return -EINVAL; 2338 } 2339 2340 if (dyn_uar) { 2341 int uars_per_page; 2342 2343 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2344 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2345 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2346 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2347 bfreg_dyn_idx, bfregi->total_num_bfregs); 2348 return -EINVAL; 2349 } 2350 2351 mutex_lock(&bfregi->lock); 2352 /* Fail if uar already allocated, first bfreg index of each 2353 * page holds its count. 2354 */ 2355 if (bfregi->count[bfreg_dyn_idx]) { 2356 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2357 mutex_unlock(&bfregi->lock); 2358 return -EINVAL; 2359 } 2360 2361 bfregi->count[bfreg_dyn_idx]++; 2362 mutex_unlock(&bfregi->lock); 2363 2364 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2365 context->devx_uid); 2366 if (err) { 2367 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2368 goto free_bfreg; 2369 } 2370 } else { 2371 uar_index = bfregi->sys_pages[idx]; 2372 } 2373 2374 pfn = uar_index2pfn(dev, uar_index); 2375 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2376 2377 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2378 prot, NULL); 2379 if (err) { 2380 mlx5_ib_err(dev, 2381 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2382 err, mmap_cmd2str(cmd)); 2383 goto err; 2384 } 2385 2386 if (dyn_uar) 2387 bfregi->sys_pages[idx] = uar_index; 2388 return 0; 2389 2390 err: 2391 if (!dyn_uar) 2392 return err; 2393 2394 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2395 2396 free_bfreg: 2397 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2398 2399 return err; 2400 } 2401 2402 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2403 { 2404 unsigned long idx; 2405 u8 command; 2406 2407 command = get_command(vma->vm_pgoff); 2408 idx = get_extended_index(vma->vm_pgoff); 2409 2410 return (command << 16 | idx); 2411 } 2412 2413 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2414 struct vm_area_struct *vma, 2415 struct ib_ucontext *ucontext) 2416 { 2417 struct mlx5_user_mmap_entry *mentry; 2418 struct rdma_user_mmap_entry *entry; 2419 unsigned long pgoff; 2420 pgprot_t prot; 2421 phys_addr_t pfn; 2422 int ret; 2423 2424 pgoff = mlx5_vma_to_pgoff(vma); 2425 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2426 if (!entry) 2427 return -EINVAL; 2428 2429 mentry = to_mmmap(entry); 2430 pfn = (mentry->address >> PAGE_SHIFT); 2431 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2432 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2433 prot = pgprot_noncached(vma->vm_page_prot); 2434 else 2435 prot = pgprot_writecombine(vma->vm_page_prot); 2436 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2437 entry->npages * PAGE_SIZE, 2438 prot, 2439 entry); 2440 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2441 return ret; 2442 } 2443 2444 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2445 { 2446 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2447 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2448 2449 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2450 (index & 0xFF)) << PAGE_SHIFT; 2451 } 2452 2453 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2454 { 2455 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2456 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2457 unsigned long command; 2458 phys_addr_t pfn; 2459 2460 command = get_command(vma->vm_pgoff); 2461 switch (command) { 2462 case MLX5_IB_MMAP_WC_PAGE: 2463 case MLX5_IB_MMAP_ALLOC_WC: 2464 if (!mlx5_wc_support_get(dev->mdev)) 2465 return -EPERM; 2466 fallthrough; 2467 case MLX5_IB_MMAP_NC_PAGE: 2468 case MLX5_IB_MMAP_REGULAR_PAGE: 2469 return uar_mmap(dev, command, vma, context); 2470 2471 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2472 return -ENOSYS; 2473 2474 case MLX5_IB_MMAP_CORE_CLOCK: 2475 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2476 return -EINVAL; 2477 2478 if (vma->vm_flags & VM_WRITE) 2479 return -EPERM; 2480 vm_flags_clear(vma, VM_MAYWRITE); 2481 2482 /* Don't expose to user-space information it shouldn't have */ 2483 if (PAGE_SIZE > 4096) 2484 return -EOPNOTSUPP; 2485 2486 pfn = (dev->mdev->iseg_base + 2487 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2488 PAGE_SHIFT; 2489 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2490 PAGE_SIZE, 2491 pgprot_noncached(vma->vm_page_prot), 2492 NULL); 2493 case MLX5_IB_MMAP_CLOCK_INFO: 2494 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2495 2496 default: 2497 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2498 } 2499 2500 return 0; 2501 } 2502 2503 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2504 { 2505 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2506 struct ib_device *ibdev = ibpd->device; 2507 struct mlx5_ib_alloc_pd_resp resp; 2508 int err; 2509 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2510 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2511 u16 uid = 0; 2512 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2513 udata, struct mlx5_ib_ucontext, ibucontext); 2514 2515 uid = context ? context->devx_uid : 0; 2516 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2517 MLX5_SET(alloc_pd_in, in, uid, uid); 2518 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2519 if (err) 2520 return err; 2521 2522 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2523 pd->uid = uid; 2524 if (udata) { 2525 resp.pdn = pd->pdn; 2526 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2527 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2528 return -EFAULT; 2529 } 2530 } 2531 2532 return 0; 2533 } 2534 2535 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2536 { 2537 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2538 struct mlx5_ib_pd *mpd = to_mpd(pd); 2539 2540 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2541 } 2542 2543 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2544 { 2545 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2546 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2547 int err; 2548 u16 uid; 2549 2550 uid = ibqp->pd ? 2551 to_mpd(ibqp->pd)->uid : 0; 2552 2553 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2554 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2555 return -EOPNOTSUPP; 2556 } 2557 2558 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2559 if (err) 2560 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2561 ibqp->qp_num, gid->raw); 2562 2563 return err; 2564 } 2565 2566 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2567 { 2568 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2569 int err; 2570 u16 uid; 2571 2572 uid = ibqp->pd ? 2573 to_mpd(ibqp->pd)->uid : 0; 2574 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2575 if (err) 2576 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2577 ibqp->qp_num, gid->raw); 2578 2579 return err; 2580 } 2581 2582 static int init_node_data(struct mlx5_ib_dev *dev) 2583 { 2584 int err; 2585 2586 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2587 if (err) 2588 return err; 2589 2590 dev->mdev->rev_id = dev->mdev->pdev->revision; 2591 2592 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2593 } 2594 2595 static ssize_t fw_pages_show(struct device *device, 2596 struct device_attribute *attr, char *buf) 2597 { 2598 struct mlx5_ib_dev *dev = 2599 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2600 2601 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2602 } 2603 static DEVICE_ATTR_RO(fw_pages); 2604 2605 static ssize_t reg_pages_show(struct device *device, 2606 struct device_attribute *attr, char *buf) 2607 { 2608 struct mlx5_ib_dev *dev = 2609 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2610 2611 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2612 } 2613 static DEVICE_ATTR_RO(reg_pages); 2614 2615 static ssize_t hca_type_show(struct device *device, 2616 struct device_attribute *attr, char *buf) 2617 { 2618 struct mlx5_ib_dev *dev = 2619 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2620 2621 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2622 } 2623 static DEVICE_ATTR_RO(hca_type); 2624 2625 static ssize_t hw_rev_show(struct device *device, 2626 struct device_attribute *attr, char *buf) 2627 { 2628 struct mlx5_ib_dev *dev = 2629 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2630 2631 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2632 } 2633 static DEVICE_ATTR_RO(hw_rev); 2634 2635 static ssize_t board_id_show(struct device *device, 2636 struct device_attribute *attr, char *buf) 2637 { 2638 struct mlx5_ib_dev *dev = 2639 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2640 2641 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2642 dev->mdev->board_id); 2643 } 2644 static DEVICE_ATTR_RO(board_id); 2645 2646 static struct attribute *mlx5_class_attributes[] = { 2647 &dev_attr_hw_rev.attr, 2648 &dev_attr_hca_type.attr, 2649 &dev_attr_board_id.attr, 2650 &dev_attr_fw_pages.attr, 2651 &dev_attr_reg_pages.attr, 2652 NULL, 2653 }; 2654 2655 static const struct attribute_group mlx5_attr_group = { 2656 .attrs = mlx5_class_attributes, 2657 }; 2658 2659 static void pkey_change_handler(struct work_struct *work) 2660 { 2661 struct mlx5_ib_port_resources *ports = 2662 container_of(work, struct mlx5_ib_port_resources, 2663 pkey_change_work); 2664 2665 if (!ports->gsi) 2666 /* 2667 * We got this event before device was fully configured 2668 * and MAD registration code wasn't called/finished yet. 2669 */ 2670 return; 2671 2672 mlx5_ib_gsi_pkey_change(ports->gsi); 2673 } 2674 2675 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2676 { 2677 struct mlx5_ib_qp *mqp; 2678 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2679 struct mlx5_core_cq *mcq; 2680 struct list_head cq_armed_list; 2681 unsigned long flags_qp; 2682 unsigned long flags_cq; 2683 unsigned long flags; 2684 2685 INIT_LIST_HEAD(&cq_armed_list); 2686 2687 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2688 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2689 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2690 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2691 if (mqp->sq.tail != mqp->sq.head) { 2692 send_mcq = to_mcq(mqp->ibqp.send_cq); 2693 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2694 if (send_mcq->mcq.comp && 2695 mqp->ibqp.send_cq->comp_handler) { 2696 if (!send_mcq->mcq.reset_notify_added) { 2697 send_mcq->mcq.reset_notify_added = 1; 2698 list_add_tail(&send_mcq->mcq.reset_notify, 2699 &cq_armed_list); 2700 } 2701 } 2702 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2703 } 2704 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2705 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2706 /* no handling is needed for SRQ */ 2707 if (!mqp->ibqp.srq) { 2708 if (mqp->rq.tail != mqp->rq.head) { 2709 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2710 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2711 if (recv_mcq->mcq.comp && 2712 mqp->ibqp.recv_cq->comp_handler) { 2713 if (!recv_mcq->mcq.reset_notify_added) { 2714 recv_mcq->mcq.reset_notify_added = 1; 2715 list_add_tail(&recv_mcq->mcq.reset_notify, 2716 &cq_armed_list); 2717 } 2718 } 2719 spin_unlock_irqrestore(&recv_mcq->lock, 2720 flags_cq); 2721 } 2722 } 2723 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2724 } 2725 /*At that point all inflight post send were put to be executed as of we 2726 * lock/unlock above locks Now need to arm all involved CQs. 2727 */ 2728 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2729 mcq->comp(mcq, NULL); 2730 } 2731 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2732 } 2733 2734 static void delay_drop_handler(struct work_struct *work) 2735 { 2736 int err; 2737 struct mlx5_ib_delay_drop *delay_drop = 2738 container_of(work, struct mlx5_ib_delay_drop, 2739 delay_drop_work); 2740 2741 atomic_inc(&delay_drop->events_cnt); 2742 2743 mutex_lock(&delay_drop->lock); 2744 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2745 if (err) { 2746 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2747 delay_drop->timeout); 2748 delay_drop->activate = false; 2749 } 2750 mutex_unlock(&delay_drop->lock); 2751 } 2752 2753 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2754 struct ib_event *ibev) 2755 { 2756 u32 port = (eqe->data.port.port >> 4) & 0xf; 2757 2758 switch (eqe->sub_type) { 2759 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2760 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2761 IB_LINK_LAYER_ETHERNET) 2762 schedule_work(&ibdev->delay_drop.delay_drop_work); 2763 break; 2764 default: /* do nothing */ 2765 return; 2766 } 2767 } 2768 2769 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2770 struct ib_event *ibev) 2771 { 2772 u32 port = (eqe->data.port.port >> 4) & 0xf; 2773 2774 ibev->element.port_num = port; 2775 2776 switch (eqe->sub_type) { 2777 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2778 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2779 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2780 /* In RoCE, port up/down events are handled in 2781 * mlx5_netdev_event(). 2782 */ 2783 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2784 IB_LINK_LAYER_ETHERNET) 2785 return -EINVAL; 2786 2787 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2788 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2789 break; 2790 2791 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2792 ibev->event = IB_EVENT_LID_CHANGE; 2793 break; 2794 2795 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2796 ibev->event = IB_EVENT_PKEY_CHANGE; 2797 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2798 break; 2799 2800 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2801 ibev->event = IB_EVENT_GID_CHANGE; 2802 break; 2803 2804 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2805 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2806 break; 2807 default: 2808 return -EINVAL; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static void mlx5_ib_handle_event(struct work_struct *_work) 2815 { 2816 struct mlx5_ib_event_work *work = 2817 container_of(_work, struct mlx5_ib_event_work, work); 2818 struct mlx5_ib_dev *ibdev; 2819 struct ib_event ibev; 2820 bool fatal = false; 2821 2822 if (work->is_slave) { 2823 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2824 if (!ibdev) 2825 goto out; 2826 } else { 2827 ibdev = work->dev; 2828 } 2829 2830 switch (work->event) { 2831 case MLX5_DEV_EVENT_SYS_ERROR: 2832 ibev.event = IB_EVENT_DEVICE_FATAL; 2833 mlx5_ib_handle_internal_error(ibdev); 2834 ibev.element.port_num = (u8)(unsigned long)work->param; 2835 fatal = true; 2836 break; 2837 case MLX5_EVENT_TYPE_PORT_CHANGE: 2838 if (handle_port_change(ibdev, work->param, &ibev)) 2839 goto out; 2840 break; 2841 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2842 handle_general_event(ibdev, work->param, &ibev); 2843 fallthrough; 2844 default: 2845 goto out; 2846 } 2847 2848 ibev.device = &ibdev->ib_dev; 2849 2850 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2851 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2852 goto out; 2853 } 2854 2855 if (ibdev->ib_active) 2856 ib_dispatch_event(&ibev); 2857 2858 if (fatal) 2859 ibdev->ib_active = false; 2860 out: 2861 kfree(work); 2862 } 2863 2864 static int mlx5_ib_event(struct notifier_block *nb, 2865 unsigned long event, void *param) 2866 { 2867 struct mlx5_ib_event_work *work; 2868 2869 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2870 if (!work) 2871 return NOTIFY_DONE; 2872 2873 INIT_WORK(&work->work, mlx5_ib_handle_event); 2874 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2875 work->is_slave = false; 2876 work->param = param; 2877 work->event = event; 2878 2879 queue_work(mlx5_ib_event_wq, &work->work); 2880 2881 return NOTIFY_OK; 2882 } 2883 2884 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2885 unsigned long event, void *param) 2886 { 2887 struct mlx5_ib_event_work *work; 2888 2889 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2890 if (!work) 2891 return NOTIFY_DONE; 2892 2893 INIT_WORK(&work->work, mlx5_ib_handle_event); 2894 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2895 work->is_slave = true; 2896 work->param = param; 2897 work->event = event; 2898 queue_work(mlx5_ib_event_wq, &work->work); 2899 2900 return NOTIFY_OK; 2901 } 2902 2903 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 2904 { 2905 struct mlx5_hca_vport_context vport_ctx; 2906 int err; 2907 2908 *num_plane = 0; 2909 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 2910 return 0; 2911 2912 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 2913 if (err) 2914 return err; 2915 2916 *num_plane = vport_ctx.num_plane; 2917 return 0; 2918 } 2919 2920 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2921 { 2922 struct mlx5_hca_vport_context vport_ctx; 2923 int err; 2924 int port; 2925 2926 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2927 return 0; 2928 2929 for (port = 1; port <= dev->num_ports; port++) { 2930 if (dev->num_plane) { 2931 dev->port_caps[port - 1].has_smi = false; 2932 continue; 2933 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 2934 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 2935 dev->port_caps[port - 1].has_smi = true; 2936 continue; 2937 } 2938 2939 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2940 &vport_ctx); 2941 if (err) { 2942 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2943 port, err); 2944 return err; 2945 } 2946 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2947 } 2948 2949 return 0; 2950 } 2951 2952 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2953 { 2954 unsigned int port; 2955 2956 rdma_for_each_port (&dev->ib_dev, port) 2957 mlx5_query_ext_port_caps(dev, port); 2958 } 2959 2960 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2961 { 2962 switch (umr_fence_cap) { 2963 case MLX5_CAP_UMR_FENCE_NONE: 2964 return MLX5_FENCE_MODE_NONE; 2965 case MLX5_CAP_UMR_FENCE_SMALL: 2966 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2967 default: 2968 return MLX5_FENCE_MODE_STRONG_ORDERING; 2969 } 2970 } 2971 2972 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 2973 { 2974 struct mlx5_ib_resources *devr = &dev->devr; 2975 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2976 struct ib_device *ibdev; 2977 struct ib_pd *pd; 2978 struct ib_cq *cq; 2979 int ret = 0; 2980 2981 2982 /* 2983 * devr->c0 is set once, never changed until device unload. 2984 * Avoid taking the mutex if initialization is already done. 2985 */ 2986 if (devr->c0) 2987 return 0; 2988 2989 mutex_lock(&devr->cq_lock); 2990 if (devr->c0) 2991 goto unlock; 2992 2993 ibdev = &dev->ib_dev; 2994 pd = ib_alloc_pd(ibdev, 0); 2995 if (IS_ERR(pd)) { 2996 ret = PTR_ERR(pd); 2997 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret); 2998 goto unlock; 2999 } 3000 3001 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3002 if (IS_ERR(cq)) { 3003 ret = PTR_ERR(cq); 3004 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret); 3005 ib_dealloc_pd(pd); 3006 goto unlock; 3007 } 3008 3009 devr->p0 = pd; 3010 devr->c0 = cq; 3011 3012 unlock: 3013 mutex_unlock(&devr->cq_lock); 3014 return ret; 3015 } 3016 3017 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3018 { 3019 struct mlx5_ib_resources *devr = &dev->devr; 3020 struct ib_srq_init_attr attr; 3021 struct ib_srq *s0, *s1; 3022 int ret = 0; 3023 3024 /* 3025 * devr->s1 is set once, never changed until device unload. 3026 * Avoid taking the mutex if initialization is already done. 3027 */ 3028 if (devr->s1) 3029 return 0; 3030 3031 mutex_lock(&devr->srq_lock); 3032 if (devr->s1) 3033 goto unlock; 3034 3035 ret = mlx5_ib_dev_res_cq_init(dev); 3036 if (ret) 3037 goto unlock; 3038 3039 memset(&attr, 0, sizeof(attr)); 3040 attr.attr.max_sge = 1; 3041 attr.attr.max_wr = 1; 3042 attr.srq_type = IB_SRQT_XRC; 3043 attr.ext.cq = devr->c0; 3044 3045 s0 = ib_create_srq(devr->p0, &attr); 3046 if (IS_ERR(s0)) { 3047 ret = PTR_ERR(s0); 3048 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret); 3049 goto unlock; 3050 } 3051 3052 memset(&attr, 0, sizeof(attr)); 3053 attr.attr.max_sge = 1; 3054 attr.attr.max_wr = 1; 3055 attr.srq_type = IB_SRQT_BASIC; 3056 3057 s1 = ib_create_srq(devr->p0, &attr); 3058 if (IS_ERR(s1)) { 3059 ret = PTR_ERR(s1); 3060 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret); 3061 ib_destroy_srq(s0); 3062 } 3063 3064 devr->s0 = s0; 3065 devr->s1 = s1; 3066 3067 unlock: 3068 mutex_unlock(&devr->srq_lock); 3069 return ret; 3070 } 3071 3072 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3073 { 3074 struct mlx5_ib_resources *devr = &dev->devr; 3075 int ret; 3076 3077 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3078 return -EOPNOTSUPP; 3079 3080 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3081 if (ret) 3082 return ret; 3083 3084 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3085 if (ret) { 3086 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3087 return ret; 3088 } 3089 3090 mutex_init(&devr->cq_lock); 3091 mutex_init(&devr->srq_lock); 3092 3093 return 0; 3094 } 3095 3096 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3097 { 3098 struct mlx5_ib_resources *devr = &dev->devr; 3099 3100 /* After s0/s1 init, they are not unset during the device lifetime. */ 3101 if (devr->s1) { 3102 ib_destroy_srq(devr->s1); 3103 ib_destroy_srq(devr->s0); 3104 } 3105 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3106 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3107 /* After p0/c0 init, they are not unset during the device lifetime. */ 3108 if (devr->c0) { 3109 ib_destroy_cq(devr->c0); 3110 ib_dealloc_pd(devr->p0); 3111 } 3112 mutex_destroy(&devr->cq_lock); 3113 mutex_destroy(&devr->srq_lock); 3114 } 3115 3116 static int 3117 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3118 { 3119 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3120 struct mlx5_core_dev *mdev = dev->mdev; 3121 void *mkc; 3122 u32 mkey; 3123 u32 pdn; 3124 u32 *in; 3125 int err; 3126 3127 err = mlx5_core_alloc_pd(mdev, &pdn); 3128 if (err) 3129 return err; 3130 3131 in = kvzalloc(inlen, GFP_KERNEL); 3132 if (!in) { 3133 err = -ENOMEM; 3134 goto err; 3135 } 3136 3137 MLX5_SET(create_mkey_in, in, data_direct, 1); 3138 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3139 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3140 MLX5_SET(mkc, mkc, lw, 1); 3141 MLX5_SET(mkc, mkc, lr, 1); 3142 MLX5_SET(mkc, mkc, rw, 1); 3143 MLX5_SET(mkc, mkc, rr, 1); 3144 MLX5_SET(mkc, mkc, a, 1); 3145 MLX5_SET(mkc, mkc, pd, pdn); 3146 MLX5_SET(mkc, mkc, length64, 1); 3147 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3148 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3149 kvfree(in); 3150 if (err) 3151 goto err; 3152 3153 dev->ddr.mkey = mkey; 3154 dev->ddr.pdn = pdn; 3155 return 0; 3156 3157 err: 3158 mlx5_core_dealloc_pd(mdev, pdn); 3159 return err; 3160 } 3161 3162 static void 3163 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3164 { 3165 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3166 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3167 } 3168 3169 static u32 get_core_cap_flags(struct ib_device *ibdev, 3170 struct mlx5_hca_vport_context *rep) 3171 { 3172 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3173 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3174 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3175 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3176 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3177 u32 ret = 0; 3178 3179 if (rep->grh_required) 3180 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3181 3182 if (dev->num_plane) 3183 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3184 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3185 RDMA_CORE_CAP_AF_IB; 3186 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3187 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3188 3189 if (ll == IB_LINK_LAYER_INFINIBAND) 3190 return ret | RDMA_CORE_PORT_IBA_IB; 3191 3192 if (raw_support) 3193 ret |= RDMA_CORE_PORT_RAW_PACKET; 3194 3195 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3196 return ret; 3197 3198 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3199 return ret; 3200 3201 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3202 ret |= RDMA_CORE_PORT_IBA_ROCE; 3203 3204 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3205 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3206 3207 return ret; 3208 } 3209 3210 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3211 struct ib_port_immutable *immutable) 3212 { 3213 struct ib_port_attr attr; 3214 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3215 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3216 struct mlx5_hca_vport_context rep = {0}; 3217 int err; 3218 3219 err = ib_query_port(ibdev, port_num, &attr); 3220 if (err) 3221 return err; 3222 3223 if (ll == IB_LINK_LAYER_INFINIBAND) { 3224 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3225 port_num = smi_to_native_portnum(dev, port_num); 3226 3227 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3228 &rep); 3229 if (err) 3230 return err; 3231 } 3232 3233 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3234 immutable->gid_tbl_len = attr.gid_tbl_len; 3235 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3236 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3237 3238 return 0; 3239 } 3240 3241 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3242 struct ib_port_immutable *immutable) 3243 { 3244 struct ib_port_attr attr; 3245 int err; 3246 3247 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3248 3249 err = ib_query_port(ibdev, port_num, &attr); 3250 if (err) 3251 return err; 3252 3253 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3254 immutable->gid_tbl_len = attr.gid_tbl_len; 3255 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3256 3257 return 0; 3258 } 3259 3260 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3261 { 3262 struct mlx5_ib_dev *dev = 3263 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3264 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3265 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3266 fw_rev_sub(dev->mdev)); 3267 } 3268 3269 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3270 { 3271 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3272 lag_events); 3273 struct mlx5_core_dev *mdev = dev->mdev; 3274 struct ib_device *ibdev = &dev->ib_dev; 3275 struct net_device *old_ndev = NULL; 3276 struct mlx5_ib_port *port; 3277 struct net_device *ndev; 3278 u32 portnum = 0; 3279 int ret = 0; 3280 int i; 3281 3282 switch (event) { 3283 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3284 ndev = data; 3285 if (ndev) { 3286 if (!mlx5_lag_is_roce(mdev)) { 3287 // sriov lag 3288 for (i = 0; i < dev->num_ports; i++) { 3289 port = &dev->port[i]; 3290 if (port->rep && port->rep->vport == 3291 MLX5_VPORT_UPLINK) { 3292 portnum = i; 3293 break; 3294 } 3295 } 3296 } 3297 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3298 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3299 if (ret) 3300 goto out; 3301 3302 if (old_ndev) 3303 roce_del_all_netdev_gids(ibdev, portnum + 1, 3304 old_ndev); 3305 rdma_roce_rescan_port(ibdev, portnum + 1); 3306 } 3307 break; 3308 default: 3309 return NOTIFY_DONE; 3310 } 3311 3312 out: 3313 dev_put(old_ndev); 3314 return notifier_from_errno(ret); 3315 } 3316 3317 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3318 { 3319 dev->lag_events.notifier_call = lag_event; 3320 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3321 &dev->lag_events); 3322 } 3323 3324 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3325 { 3326 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3327 &dev->lag_events); 3328 } 3329 3330 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3331 { 3332 struct mlx5_core_dev *mdev = dev->mdev; 3333 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3334 MLX5_FLOW_NAMESPACE_LAG); 3335 struct mlx5_flow_table *ft; 3336 int err; 3337 3338 if (!ns || !mlx5_lag_is_active(mdev)) 3339 return 0; 3340 3341 err = mlx5_cmd_create_vport_lag(mdev); 3342 if (err) 3343 return err; 3344 3345 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3346 if (IS_ERR(ft)) { 3347 err = PTR_ERR(ft); 3348 goto err_destroy_vport_lag; 3349 } 3350 3351 mlx5e_lag_event_register(dev); 3352 dev->flow_db->lag_demux_ft = ft; 3353 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3354 dev->lag_active = true; 3355 return 0; 3356 3357 err_destroy_vport_lag: 3358 mlx5_cmd_destroy_vport_lag(mdev); 3359 return err; 3360 } 3361 3362 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3363 { 3364 struct mlx5_core_dev *mdev = dev->mdev; 3365 3366 if (dev->lag_active) { 3367 dev->lag_active = false; 3368 3369 mlx5e_lag_event_unregister(dev); 3370 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3371 dev->flow_db->lag_demux_ft = NULL; 3372 3373 mlx5_cmd_destroy_vport_lag(mdev); 3374 } 3375 } 3376 3377 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3378 struct net_device *netdev) 3379 { 3380 int err; 3381 3382 if (roce->tracking_netdev) 3383 return; 3384 roce->tracking_netdev = netdev; 3385 roce->nb.notifier_call = mlx5_netdev_event; 3386 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3387 WARN_ON(err); 3388 } 3389 3390 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3391 { 3392 if (!roce->tracking_netdev) 3393 return; 3394 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3395 &roce->nn); 3396 roce->tracking_netdev = NULL; 3397 } 3398 3399 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3400 unsigned long event, void *data) 3401 { 3402 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3403 struct net_device *netdev = data; 3404 3405 switch (event) { 3406 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3407 if (netdev) 3408 mlx5_netdev_notifier_register(roce, netdev); 3409 else 3410 mlx5_netdev_notifier_unregister(roce); 3411 break; 3412 default: 3413 return NOTIFY_DONE; 3414 } 3415 3416 return NOTIFY_OK; 3417 } 3418 3419 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3420 { 3421 struct mlx5_roce *roce = &dev->port[port_num].roce; 3422 3423 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3424 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3425 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3426 } 3427 3428 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3429 { 3430 struct mlx5_roce *roce = &dev->port[port_num].roce; 3431 3432 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3433 mlx5_netdev_notifier_unregister(roce); 3434 } 3435 3436 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3437 { 3438 int err; 3439 3440 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3441 err = mlx5_nic_vport_enable_roce(dev->mdev); 3442 if (err) 3443 return err; 3444 } 3445 3446 err = mlx5_eth_lag_init(dev); 3447 if (err) 3448 goto err_disable_roce; 3449 3450 return 0; 3451 3452 err_disable_roce: 3453 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3454 mlx5_nic_vport_disable_roce(dev->mdev); 3455 3456 return err; 3457 } 3458 3459 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3460 { 3461 mlx5_eth_lag_cleanup(dev); 3462 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3463 mlx5_nic_vport_disable_roce(dev->mdev); 3464 } 3465 3466 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3467 enum rdma_netdev_t type, 3468 struct rdma_netdev_alloc_params *params) 3469 { 3470 if (type != RDMA_NETDEV_IPOIB) 3471 return -EOPNOTSUPP; 3472 3473 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3474 } 3475 3476 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3477 size_t count, loff_t *pos) 3478 { 3479 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3480 char lbuf[20]; 3481 int len; 3482 3483 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3484 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3485 } 3486 3487 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3488 size_t count, loff_t *pos) 3489 { 3490 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3491 u32 timeout; 3492 u32 var; 3493 3494 if (kstrtouint_from_user(buf, count, 0, &var)) 3495 return -EFAULT; 3496 3497 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3498 1000); 3499 if (timeout != var) 3500 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3501 timeout); 3502 3503 delay_drop->timeout = timeout; 3504 3505 return count; 3506 } 3507 3508 static const struct file_operations fops_delay_drop_timeout = { 3509 .owner = THIS_MODULE, 3510 .open = simple_open, 3511 .write = delay_drop_timeout_write, 3512 .read = delay_drop_timeout_read, 3513 }; 3514 3515 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3516 struct mlx5_ib_multiport_info *mpi) 3517 { 3518 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3519 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3520 int comps; 3521 int err; 3522 int i; 3523 3524 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3525 3526 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev); 3527 3528 mlx5_core_mp_event_replay(ibdev->mdev, 3529 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3530 NULL); 3531 mlx5_core_mp_event_replay(mpi->mdev, 3532 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3533 NULL); 3534 3535 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3536 3537 spin_lock(&port->mp.mpi_lock); 3538 if (!mpi->ibdev) { 3539 spin_unlock(&port->mp.mpi_lock); 3540 return; 3541 } 3542 3543 mpi->ibdev = NULL; 3544 3545 spin_unlock(&port->mp.mpi_lock); 3546 if (mpi->mdev_events.notifier_call) 3547 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3548 mpi->mdev_events.notifier_call = NULL; 3549 mlx5_mdev_netdev_untrack(ibdev, port_num); 3550 spin_lock(&port->mp.mpi_lock); 3551 3552 comps = mpi->mdev_refcnt; 3553 if (comps) { 3554 mpi->unaffiliate = true; 3555 init_completion(&mpi->unref_comp); 3556 spin_unlock(&port->mp.mpi_lock); 3557 3558 for (i = 0; i < comps; i++) 3559 wait_for_completion(&mpi->unref_comp); 3560 3561 spin_lock(&port->mp.mpi_lock); 3562 mpi->unaffiliate = false; 3563 } 3564 3565 port->mp.mpi = NULL; 3566 3567 spin_unlock(&port->mp.mpi_lock); 3568 3569 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3570 3571 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3572 /* Log an error, still needed to cleanup the pointers and add 3573 * it back to the list. 3574 */ 3575 if (err) 3576 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3577 port_num + 1); 3578 3579 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3580 } 3581 3582 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3583 struct mlx5_ib_multiport_info *mpi) 3584 { 3585 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3586 u64 key; 3587 int err; 3588 3589 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3590 3591 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3592 if (ibdev->port[port_num].mp.mpi) { 3593 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3594 port_num + 1); 3595 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3596 return false; 3597 } 3598 3599 ibdev->port[port_num].mp.mpi = mpi; 3600 mpi->ibdev = ibdev; 3601 mpi->mdev_events.notifier_call = NULL; 3602 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3603 3604 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3605 if (err) 3606 goto unbind; 3607 3608 mlx5_mdev_netdev_track(ibdev, port_num); 3609 3610 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3611 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3612 3613 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3614 3615 key = mpi->mdev->priv.adev_idx; 3616 mlx5_core_mp_event_replay(mpi->mdev, 3617 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3618 &key); 3619 mlx5_core_mp_event_replay(ibdev->mdev, 3620 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3621 &key); 3622 3623 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev); 3624 if (err) 3625 goto unbind; 3626 3627 return true; 3628 3629 unbind: 3630 mlx5_ib_unbind_slave_port(ibdev, mpi); 3631 return false; 3632 } 3633 3634 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3635 { 3636 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3637 int ret; 3638 3639 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3640 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3641 return 0; 3642 3643 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3644 if (ret) 3645 return ret; 3646 3647 ret = mlx5_ib_create_data_direct_resources(dev); 3648 if (ret) 3649 return ret; 3650 3651 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3652 ret = mlx5_data_direct_ib_reg(dev, vuid); 3653 if (ret) 3654 mlx5_ib_free_data_direct_resources(dev); 3655 3656 return ret; 3657 } 3658 3659 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3660 { 3661 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3662 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3663 return; 3664 3665 mlx5_data_direct_ib_unreg(dev); 3666 mlx5_ib_free_data_direct_resources(dev); 3667 } 3668 3669 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3670 { 3671 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3672 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3673 port_num + 1); 3674 struct mlx5_ib_multiport_info *mpi; 3675 int err; 3676 u32 i; 3677 3678 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3679 return 0; 3680 3681 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3682 &dev->sys_image_guid); 3683 if (err) 3684 return err; 3685 3686 err = mlx5_nic_vport_enable_roce(dev->mdev); 3687 if (err) 3688 return err; 3689 3690 mutex_lock(&mlx5_ib_multiport_mutex); 3691 for (i = 0; i < dev->num_ports; i++) { 3692 bool bound = false; 3693 3694 /* build a stub multiport info struct for the native port. */ 3695 if (i == port_num) { 3696 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3697 if (!mpi) { 3698 mutex_unlock(&mlx5_ib_multiport_mutex); 3699 mlx5_nic_vport_disable_roce(dev->mdev); 3700 return -ENOMEM; 3701 } 3702 3703 mpi->is_master = true; 3704 mpi->mdev = dev->mdev; 3705 mpi->sys_image_guid = dev->sys_image_guid; 3706 dev->port[i].mp.mpi = mpi; 3707 mpi->ibdev = dev; 3708 mpi = NULL; 3709 continue; 3710 } 3711 3712 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3713 list) { 3714 if (dev->sys_image_guid == mpi->sys_image_guid && 3715 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 3716 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 3717 bound = mlx5_ib_bind_slave_port(dev, mpi); 3718 } 3719 3720 if (bound) { 3721 dev_dbg(mpi->mdev->device, 3722 "removing port from unaffiliated list.\n"); 3723 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3724 list_del(&mpi->list); 3725 break; 3726 } 3727 } 3728 if (!bound) 3729 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3730 i + 1); 3731 } 3732 3733 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3734 mutex_unlock(&mlx5_ib_multiport_mutex); 3735 return err; 3736 } 3737 3738 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3739 { 3740 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3741 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3742 port_num + 1); 3743 u32 i; 3744 3745 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3746 return; 3747 3748 mutex_lock(&mlx5_ib_multiport_mutex); 3749 for (i = 0; i < dev->num_ports; i++) { 3750 if (dev->port[i].mp.mpi) { 3751 /* Destroy the native port stub */ 3752 if (i == port_num) { 3753 kfree(dev->port[i].mp.mpi); 3754 dev->port[i].mp.mpi = NULL; 3755 } else { 3756 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3757 i + 1); 3758 list_add_tail(&dev->port[i].mp.mpi->list, 3759 &mlx5_ib_unaffiliated_port_list); 3760 mlx5_ib_unbind_slave_port(dev, 3761 dev->port[i].mp.mpi); 3762 } 3763 } 3764 } 3765 3766 mlx5_ib_dbg(dev, "removing from devlist\n"); 3767 list_del(&dev->ib_dev_list); 3768 mutex_unlock(&mlx5_ib_multiport_mutex); 3769 3770 mlx5_nic_vport_disable_roce(dev->mdev); 3771 } 3772 3773 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3774 enum rdma_remove_reason why, 3775 struct uverbs_attr_bundle *attrs) 3776 { 3777 struct mlx5_user_mmap_entry *obj = uobject->object; 3778 3779 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3780 return 0; 3781 } 3782 3783 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3784 struct mlx5_user_mmap_entry *entry, 3785 size_t length) 3786 { 3787 return rdma_user_mmap_entry_insert_range( 3788 &c->ibucontext, &entry->rdma_entry, length, 3789 (MLX5_IB_MMAP_OFFSET_START << 16), 3790 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3791 } 3792 3793 static struct mlx5_user_mmap_entry * 3794 alloc_var_entry(struct mlx5_ib_ucontext *c) 3795 { 3796 struct mlx5_user_mmap_entry *entry; 3797 struct mlx5_var_table *var_table; 3798 u32 page_idx; 3799 int err; 3800 3801 var_table = &to_mdev(c->ibucontext.device)->var_table; 3802 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3803 if (!entry) 3804 return ERR_PTR(-ENOMEM); 3805 3806 mutex_lock(&var_table->bitmap_lock); 3807 page_idx = find_first_zero_bit(var_table->bitmap, 3808 var_table->num_var_hw_entries); 3809 if (page_idx >= var_table->num_var_hw_entries) { 3810 err = -ENOSPC; 3811 mutex_unlock(&var_table->bitmap_lock); 3812 goto end; 3813 } 3814 3815 set_bit(page_idx, var_table->bitmap); 3816 mutex_unlock(&var_table->bitmap_lock); 3817 3818 entry->address = var_table->hw_start_addr + 3819 (page_idx * var_table->stride_size); 3820 entry->page_idx = page_idx; 3821 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3822 3823 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3824 var_table->stride_size); 3825 if (err) 3826 goto err_insert; 3827 3828 return entry; 3829 3830 err_insert: 3831 mutex_lock(&var_table->bitmap_lock); 3832 clear_bit(page_idx, var_table->bitmap); 3833 mutex_unlock(&var_table->bitmap_lock); 3834 end: 3835 kfree(entry); 3836 return ERR_PTR(err); 3837 } 3838 3839 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3840 struct uverbs_attr_bundle *attrs) 3841 { 3842 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3843 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3844 struct mlx5_ib_ucontext *c; 3845 struct mlx5_user_mmap_entry *entry; 3846 u64 mmap_offset; 3847 u32 length; 3848 int err; 3849 3850 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3851 if (IS_ERR(c)) 3852 return PTR_ERR(c); 3853 3854 entry = alloc_var_entry(c); 3855 if (IS_ERR(entry)) 3856 return PTR_ERR(entry); 3857 3858 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3859 length = entry->rdma_entry.npages * PAGE_SIZE; 3860 uobj->object = entry; 3861 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3862 3863 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3864 &mmap_offset, sizeof(mmap_offset)); 3865 if (err) 3866 return err; 3867 3868 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3869 &entry->page_idx, sizeof(entry->page_idx)); 3870 if (err) 3871 return err; 3872 3873 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3874 &length, sizeof(length)); 3875 return err; 3876 } 3877 3878 DECLARE_UVERBS_NAMED_METHOD( 3879 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3880 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3881 MLX5_IB_OBJECT_VAR, 3882 UVERBS_ACCESS_NEW, 3883 UA_MANDATORY), 3884 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3885 UVERBS_ATTR_TYPE(u32), 3886 UA_MANDATORY), 3887 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3888 UVERBS_ATTR_TYPE(u32), 3889 UA_MANDATORY), 3890 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3891 UVERBS_ATTR_TYPE(u64), 3892 UA_MANDATORY)); 3893 3894 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3895 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3896 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3897 MLX5_IB_OBJECT_VAR, 3898 UVERBS_ACCESS_DESTROY, 3899 UA_MANDATORY)); 3900 3901 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3902 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3903 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3904 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3905 3906 static bool var_is_supported(struct ib_device *device) 3907 { 3908 struct mlx5_ib_dev *dev = to_mdev(device); 3909 3910 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3911 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3912 } 3913 3914 static struct mlx5_user_mmap_entry * 3915 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3916 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3917 { 3918 struct mlx5_user_mmap_entry *entry; 3919 struct mlx5_ib_dev *dev; 3920 u32 uar_index; 3921 int err; 3922 3923 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3924 if (!entry) 3925 return ERR_PTR(-ENOMEM); 3926 3927 dev = to_mdev(c->ibucontext.device); 3928 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3929 if (err) 3930 goto end; 3931 3932 entry->page_idx = uar_index; 3933 entry->address = uar_index2paddress(dev, uar_index); 3934 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3935 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3936 else 3937 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3938 3939 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3940 if (err) 3941 goto err_insert; 3942 3943 return entry; 3944 3945 err_insert: 3946 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3947 end: 3948 kfree(entry); 3949 return ERR_PTR(err); 3950 } 3951 3952 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3953 struct uverbs_attr_bundle *attrs) 3954 { 3955 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3956 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3957 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3958 struct mlx5_ib_ucontext *c; 3959 struct mlx5_user_mmap_entry *entry; 3960 u64 mmap_offset; 3961 u32 length; 3962 int err; 3963 3964 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3965 if (IS_ERR(c)) 3966 return PTR_ERR(c); 3967 3968 err = uverbs_get_const(&alloc_type, attrs, 3969 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3970 if (err) 3971 return err; 3972 3973 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3974 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3975 return -EOPNOTSUPP; 3976 3977 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 3978 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3979 return -EOPNOTSUPP; 3980 3981 entry = alloc_uar_entry(c, alloc_type); 3982 if (IS_ERR(entry)) 3983 return PTR_ERR(entry); 3984 3985 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3986 length = entry->rdma_entry.npages * PAGE_SIZE; 3987 uobj->object = entry; 3988 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3989 3990 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3991 &mmap_offset, sizeof(mmap_offset)); 3992 if (err) 3993 return err; 3994 3995 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3996 &entry->page_idx, sizeof(entry->page_idx)); 3997 if (err) 3998 return err; 3999 4000 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4001 &length, sizeof(length)); 4002 return err; 4003 } 4004 4005 DECLARE_UVERBS_NAMED_METHOD( 4006 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4007 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4008 MLX5_IB_OBJECT_UAR, 4009 UVERBS_ACCESS_NEW, 4010 UA_MANDATORY), 4011 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4012 enum mlx5_ib_uapi_uar_alloc_type, 4013 UA_MANDATORY), 4014 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4015 UVERBS_ATTR_TYPE(u32), 4016 UA_MANDATORY), 4017 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4018 UVERBS_ATTR_TYPE(u32), 4019 UA_MANDATORY), 4020 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4021 UVERBS_ATTR_TYPE(u64), 4022 UA_MANDATORY)); 4023 4024 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4025 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4026 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4027 MLX5_IB_OBJECT_UAR, 4028 UVERBS_ACCESS_DESTROY, 4029 UA_MANDATORY)); 4030 4031 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4032 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4033 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4034 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4035 4036 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4037 mlx5_ib_query_context, 4038 UVERBS_OBJECT_DEVICE, 4039 UVERBS_METHOD_QUERY_CONTEXT, 4040 UVERBS_ATTR_PTR_OUT( 4041 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4042 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4043 dump_fill_mkey), 4044 UA_MANDATORY)); 4045 4046 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4047 mlx5_ib_reg_dmabuf_mr, 4048 UVERBS_OBJECT_MR, 4049 UVERBS_METHOD_REG_DMABUF_MR, 4050 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4051 enum mlx5_ib_uapi_reg_dmabuf_flags, 4052 UA_OPTIONAL)); 4053 4054 static const struct uapi_definition mlx5_ib_defs[] = { 4055 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4056 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4057 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4058 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4059 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4060 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4061 4062 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4063 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4064 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4065 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4066 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4067 {} 4068 }; 4069 4070 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4071 { 4072 mlx5_ib_data_direct_cleanup(dev); 4073 mlx5_ib_cleanup_multiport_master(dev); 4074 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4075 mutex_destroy(&dev->cap_mask_mutex); 4076 WARN_ON(!xa_empty(&dev->sig_mrs)); 4077 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4078 mlx5r_macsec_dealloc_gids(dev); 4079 } 4080 4081 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4082 { 4083 struct mlx5_core_dev *mdev = dev->mdev; 4084 int err, i; 4085 4086 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4087 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4088 dev->ib_dev.dev.parent = mdev->device; 4089 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4090 4091 for (i = 0; i < dev->num_ports; i++) { 4092 spin_lock_init(&dev->port[i].mp.mpi_lock); 4093 dev->port[i].roce.dev = dev; 4094 dev->port[i].roce.native_port_num = i + 1; 4095 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4096 } 4097 4098 err = mlx5r_cmd_query_special_mkeys(dev); 4099 if (err) 4100 return err; 4101 4102 err = mlx5r_macsec_init_gids_and_devlist(dev); 4103 if (err) 4104 return err; 4105 4106 err = mlx5_ib_init_multiport_master(dev); 4107 if (err) 4108 goto err; 4109 4110 err = set_has_smi_cap(dev); 4111 if (err) 4112 goto err_mp; 4113 4114 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4115 if (err) 4116 goto err_mp; 4117 4118 if (mlx5_use_mad_ifc(dev)) 4119 get_ext_port_caps(dev); 4120 4121 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4122 4123 mutex_init(&dev->cap_mask_mutex); 4124 mutex_init(&dev->data_direct_lock); 4125 INIT_LIST_HEAD(&dev->qp_list); 4126 spin_lock_init(&dev->reset_flow_resource_lock); 4127 xa_init(&dev->odp_mkeys); 4128 xa_init(&dev->sig_mrs); 4129 atomic_set(&dev->mkey_var, 0); 4130 4131 spin_lock_init(&dev->dm.lock); 4132 dev->dm.dev = mdev; 4133 err = mlx5_ib_data_direct_init(dev); 4134 if (err) 4135 goto err_mp; 4136 4137 return 0; 4138 err_mp: 4139 mlx5_ib_cleanup_multiport_master(dev); 4140 err: 4141 mlx5r_macsec_dealloc_gids(dev); 4142 return err; 4143 } 4144 4145 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4146 enum rdma_nl_dev_type type, 4147 const char *name); 4148 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4149 4150 static const struct ib_device_ops mlx5_ib_dev_ops = { 4151 .owner = THIS_MODULE, 4152 .driver_id = RDMA_DRIVER_MLX5, 4153 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4154 4155 .add_gid = mlx5_ib_add_gid, 4156 .add_sub_dev = mlx5_ib_add_sub_dev, 4157 .alloc_mr = mlx5_ib_alloc_mr, 4158 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4159 .alloc_pd = mlx5_ib_alloc_pd, 4160 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4161 .attach_mcast = mlx5_ib_mcg_attach, 4162 .check_mr_status = mlx5_ib_check_mr_status, 4163 .create_ah = mlx5_ib_create_ah, 4164 .create_cq = mlx5_ib_create_cq, 4165 .create_qp = mlx5_ib_create_qp, 4166 .create_srq = mlx5_ib_create_srq, 4167 .create_user_ah = mlx5_ib_create_ah, 4168 .dealloc_pd = mlx5_ib_dealloc_pd, 4169 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4170 .del_gid = mlx5_ib_del_gid, 4171 .del_sub_dev = mlx5_ib_del_sub_dev, 4172 .dereg_mr = mlx5_ib_dereg_mr, 4173 .destroy_ah = mlx5_ib_destroy_ah, 4174 .destroy_cq = mlx5_ib_destroy_cq, 4175 .destroy_qp = mlx5_ib_destroy_qp, 4176 .destroy_srq = mlx5_ib_destroy_srq, 4177 .detach_mcast = mlx5_ib_mcg_detach, 4178 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4179 .drain_rq = mlx5_ib_drain_rq, 4180 .drain_sq = mlx5_ib_drain_sq, 4181 .device_group = &mlx5_attr_group, 4182 .get_dev_fw_str = get_dev_fw_str, 4183 .get_dma_mr = mlx5_ib_get_dma_mr, 4184 .get_link_layer = mlx5_ib_port_link_layer, 4185 .map_mr_sg = mlx5_ib_map_mr_sg, 4186 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4187 .mmap = mlx5_ib_mmap, 4188 .mmap_free = mlx5_ib_mmap_free, 4189 .modify_cq = mlx5_ib_modify_cq, 4190 .modify_device = mlx5_ib_modify_device, 4191 .modify_port = mlx5_ib_modify_port, 4192 .modify_qp = mlx5_ib_modify_qp, 4193 .modify_srq = mlx5_ib_modify_srq, 4194 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4195 .poll_cq = mlx5_ib_poll_cq, 4196 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4197 .post_recv = mlx5_ib_post_recv_nodrain, 4198 .post_send = mlx5_ib_post_send_nodrain, 4199 .post_srq_recv = mlx5_ib_post_srq_recv, 4200 .process_mad = mlx5_ib_process_mad, 4201 .query_ah = mlx5_ib_query_ah, 4202 .query_device = mlx5_ib_query_device, 4203 .query_gid = mlx5_ib_query_gid, 4204 .query_pkey = mlx5_ib_query_pkey, 4205 .query_qp = mlx5_ib_query_qp, 4206 .query_srq = mlx5_ib_query_srq, 4207 .query_ucontext = mlx5_ib_query_ucontext, 4208 .reg_user_mr = mlx5_ib_reg_user_mr, 4209 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4210 .req_notify_cq = mlx5_ib_arm_cq, 4211 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4212 .resize_cq = mlx5_ib_resize_cq, 4213 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4214 4215 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4216 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4217 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4218 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4219 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4220 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4221 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4222 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4223 }; 4224 4225 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4226 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4227 }; 4228 4229 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4230 .get_vf_config = mlx5_ib_get_vf_config, 4231 .get_vf_guid = mlx5_ib_get_vf_guid, 4232 .get_vf_stats = mlx5_ib_get_vf_stats, 4233 .set_vf_guid = mlx5_ib_set_vf_guid, 4234 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4235 }; 4236 4237 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4238 .alloc_mw = mlx5_ib_alloc_mw, 4239 .dealloc_mw = mlx5_ib_dealloc_mw, 4240 4241 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4242 }; 4243 4244 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4245 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4246 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4247 4248 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4249 }; 4250 4251 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4252 { 4253 struct mlx5_core_dev *mdev = dev->mdev; 4254 struct mlx5_var_table *var_table = &dev->var_table; 4255 u8 log_doorbell_bar_size; 4256 u8 log_doorbell_stride; 4257 u64 bar_size; 4258 4259 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4260 log_doorbell_bar_size); 4261 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4262 log_doorbell_stride); 4263 var_table->hw_start_addr = dev->mdev->bar_addr + 4264 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4265 doorbell_bar_offset); 4266 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4267 var_table->stride_size = 1ULL << log_doorbell_stride; 4268 var_table->num_var_hw_entries = div_u64(bar_size, 4269 var_table->stride_size); 4270 mutex_init(&var_table->bitmap_lock); 4271 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4272 GFP_KERNEL); 4273 return (var_table->bitmap) ? 0 : -ENOMEM; 4274 } 4275 4276 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4277 { 4278 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4279 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4280 4281 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4282 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4283 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4284 } 4285 4286 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4287 { 4288 int ret; 4289 4290 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4291 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4292 if (ret) 4293 return ret; 4294 } 4295 4296 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4297 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4298 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4299 if (ret) 4300 goto remove_local; 4301 } 4302 4303 return 0; 4304 4305 remove_local: 4306 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4307 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4308 return ret; 4309 } 4310 4311 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4312 { 4313 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4314 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4315 mlx5_ib_cleanup_ucaps(dev); 4316 4317 bitmap_free(dev->var_table.bitmap); 4318 } 4319 4320 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4321 { 4322 struct mlx5_core_dev *mdev = dev->mdev; 4323 int err; 4324 4325 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4326 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4327 ib_set_device_ops(&dev->ib_dev, 4328 &mlx5_ib_dev_ipoib_enhanced_ops); 4329 4330 if (mlx5_core_is_pf(mdev)) 4331 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4332 4333 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4334 4335 if (MLX5_CAP_GEN(mdev, imaicl)) 4336 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4337 4338 if (MLX5_CAP_GEN(mdev, xrc)) 4339 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4340 4341 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4342 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4343 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4344 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4345 4346 if (mdev->st) 4347 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4348 4349 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4350 4351 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4352 dev->ib_dev.driver_def = mlx5_ib_defs; 4353 4354 err = init_node_data(dev); 4355 if (err) 4356 return err; 4357 4358 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4359 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4360 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4361 mutex_init(&dev->lb.mutex); 4362 4363 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4364 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4365 err = mlx5_ib_init_var_table(dev); 4366 if (err) 4367 return err; 4368 } 4369 4370 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4371 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4372 err = mlx5_ib_init_ucaps(dev); 4373 if (err) 4374 return err; 4375 } 4376 4377 dev->ib_dev.use_cq_dim = true; 4378 4379 return 0; 4380 } 4381 4382 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4383 .get_port_immutable = mlx5_port_immutable, 4384 .query_port = mlx5_ib_query_port, 4385 }; 4386 4387 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4388 { 4389 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4390 return 0; 4391 } 4392 4393 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4394 .get_port_immutable = mlx5_port_rep_immutable, 4395 .query_port = mlx5_ib_rep_query_port, 4396 .query_pkey = mlx5_ib_rep_query_pkey, 4397 }; 4398 4399 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4400 { 4401 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4402 return 0; 4403 } 4404 4405 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4406 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4407 .create_wq = mlx5_ib_create_wq, 4408 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4409 .destroy_wq = mlx5_ib_destroy_wq, 4410 .modify_wq = mlx5_ib_modify_wq, 4411 4412 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4413 ib_rwq_ind_tbl), 4414 }; 4415 4416 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4417 { 4418 struct mlx5_core_dev *mdev = dev->mdev; 4419 enum rdma_link_layer ll; 4420 int port_type_cap; 4421 u32 port_num = 0; 4422 int err; 4423 4424 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4425 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4426 4427 if (ll == IB_LINK_LAYER_ETHERNET) { 4428 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4429 4430 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4431 4432 /* Register only for native ports */ 4433 mlx5_mdev_netdev_track(dev, port_num); 4434 4435 err = mlx5_enable_eth(dev); 4436 if (err) 4437 goto cleanup; 4438 } 4439 4440 return 0; 4441 cleanup: 4442 mlx5_mdev_netdev_untrack(dev, port_num); 4443 return err; 4444 } 4445 4446 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4447 { 4448 struct mlx5_core_dev *mdev = dev->mdev; 4449 enum rdma_link_layer ll; 4450 int port_type_cap; 4451 u32 port_num; 4452 4453 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4454 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4455 4456 if (ll == IB_LINK_LAYER_ETHERNET) { 4457 mlx5_disable_eth(dev); 4458 4459 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4460 mlx5_mdev_netdev_untrack(dev, port_num); 4461 } 4462 } 4463 4464 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4465 { 4466 mlx5_ib_init_cong_debugfs(dev, 4467 mlx5_core_native_port_num(dev->mdev) - 1); 4468 return 0; 4469 } 4470 4471 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4472 { 4473 mlx5_ib_cleanup_cong_debugfs(dev, 4474 mlx5_core_native_port_num(dev->mdev) - 1); 4475 } 4476 4477 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4478 { 4479 int err; 4480 4481 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4482 if (err) 4483 return err; 4484 4485 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4486 if (err) 4487 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4488 4489 return err; 4490 } 4491 4492 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4493 { 4494 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4495 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4496 } 4497 4498 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4499 { 4500 const char *name; 4501 4502 if (dev->sub_dev_name) { 4503 name = dev->sub_dev_name; 4504 ib_mark_name_assigned_by_user(&dev->ib_dev); 4505 } else if (!mlx5_lag_is_active(dev->mdev)) 4506 name = "mlx5_%d"; 4507 else 4508 name = "mlx5_bond_%d"; 4509 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4510 } 4511 4512 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4513 { 4514 mlx5_mkey_cache_cleanup(dev); 4515 mlx5r_umr_resource_cleanup(dev); 4516 mlx5r_umr_cleanup(dev); 4517 } 4518 4519 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4520 { 4521 ib_unregister_device(&dev->ib_dev); 4522 } 4523 4524 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4525 { 4526 int ret; 4527 4528 ret = mlx5r_umr_init(dev); 4529 if (ret) 4530 return ret; 4531 4532 ret = mlx5_mkey_cache_init(dev); 4533 if (ret) 4534 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4535 return ret; 4536 } 4537 4538 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4539 { 4540 struct dentry *root; 4541 4542 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4543 return 0; 4544 4545 mutex_init(&dev->delay_drop.lock); 4546 dev->delay_drop.dev = dev; 4547 dev->delay_drop.activate = false; 4548 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4549 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4550 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4551 atomic_set(&dev->delay_drop.events_cnt, 0); 4552 4553 if (!mlx5_debugfs_root) 4554 return 0; 4555 4556 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4557 dev->delay_drop.dir_debugfs = root; 4558 4559 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4560 &dev->delay_drop.events_cnt); 4561 debugfs_create_atomic_t("num_rqs", 0400, root, 4562 &dev->delay_drop.rqs_cnt); 4563 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4564 &fops_delay_drop_timeout); 4565 return 0; 4566 } 4567 4568 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4569 { 4570 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4571 return; 4572 4573 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4574 if (!dev->delay_drop.dir_debugfs) 4575 return; 4576 4577 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4578 dev->delay_drop.dir_debugfs = NULL; 4579 } 4580 4581 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4582 { 4583 struct mlx5_ib_resources *devr = &dev->devr; 4584 int port; 4585 4586 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4587 INIT_WORK(&devr->ports[port].pkey_change_work, 4588 pkey_change_handler); 4589 4590 dev->mdev_events.notifier_call = mlx5_ib_event; 4591 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4592 4593 mlx5r_macsec_event_register(dev); 4594 4595 return 0; 4596 } 4597 4598 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4599 { 4600 struct mlx5_ib_resources *devr = &dev->devr; 4601 int port; 4602 4603 mlx5r_macsec_event_unregister(dev); 4604 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4605 4606 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4607 cancel_work_sync(&devr->ports[port].pkey_change_work); 4608 } 4609 4610 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4611 struct mlx5_data_direct_dev *dev) 4612 { 4613 mutex_lock(&ibdev->data_direct_lock); 4614 ibdev->data_direct_dev = dev; 4615 mutex_unlock(&ibdev->data_direct_lock); 4616 } 4617 4618 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4619 { 4620 mutex_lock(&ibdev->data_direct_lock); 4621 mlx5_ib_revoke_data_direct_mrs(ibdev); 4622 ibdev->data_direct_dev = NULL; 4623 mutex_unlock(&ibdev->data_direct_lock); 4624 } 4625 4626 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4627 const struct mlx5_ib_profile *profile, 4628 int stage) 4629 { 4630 dev->ib_active = false; 4631 4632 /* Number of stages to cleanup */ 4633 while (stage) { 4634 stage--; 4635 if (profile->stage[stage].cleanup) 4636 profile->stage[stage].cleanup(dev); 4637 } 4638 4639 kfree(dev->port); 4640 ib_dealloc_device(&dev->ib_dev); 4641 } 4642 4643 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4644 const struct mlx5_ib_profile *profile) 4645 { 4646 int err; 4647 int i; 4648 4649 dev->profile = profile; 4650 4651 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4652 if (profile->stage[i].init) { 4653 err = profile->stage[i].init(dev); 4654 if (err) 4655 goto err_out; 4656 } 4657 } 4658 4659 dev->ib_active = true; 4660 return 0; 4661 4662 err_out: 4663 /* Clean up stages which were initialized */ 4664 while (i) { 4665 i--; 4666 if (profile->stage[i].cleanup) 4667 profile->stage[i].cleanup(dev); 4668 } 4669 return -ENOMEM; 4670 } 4671 4672 static const struct mlx5_ib_profile pf_profile = { 4673 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4674 mlx5_ib_stage_init_init, 4675 mlx5_ib_stage_init_cleanup), 4676 STAGE_CREATE(MLX5_IB_STAGE_FS, 4677 mlx5_ib_fs_init, 4678 mlx5_ib_fs_cleanup), 4679 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4680 mlx5_ib_stage_caps_init, 4681 mlx5_ib_stage_caps_cleanup), 4682 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4683 mlx5_ib_stage_non_default_cb, 4684 NULL), 4685 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4686 mlx5_ib_roce_init, 4687 mlx5_ib_roce_cleanup), 4688 STAGE_CREATE(MLX5_IB_STAGE_QP, 4689 mlx5_init_qp_table, 4690 mlx5_cleanup_qp_table), 4691 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4692 mlx5_init_srq_table, 4693 mlx5_cleanup_srq_table), 4694 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4695 mlx5_ib_dev_res_init, 4696 mlx5_ib_dev_res_cleanup), 4697 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4698 mlx5_ib_odp_init_one, 4699 mlx5_ib_odp_cleanup_one), 4700 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4701 mlx5_ib_counters_init, 4702 mlx5_ib_counters_cleanup), 4703 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4704 mlx5_ib_stage_cong_debugfs_init, 4705 mlx5_ib_stage_cong_debugfs_cleanup), 4706 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4707 mlx5_ib_stage_bfrag_init, 4708 mlx5_ib_stage_bfrag_cleanup), 4709 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4710 NULL, 4711 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4712 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4713 mlx5_ib_devx_init, 4714 mlx5_ib_devx_cleanup), 4715 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4716 mlx5_ib_stage_ib_reg_init, 4717 mlx5_ib_stage_ib_reg_cleanup), 4718 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4719 mlx5_ib_stage_dev_notifier_init, 4720 mlx5_ib_stage_dev_notifier_cleanup), 4721 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4722 mlx5_ib_stage_post_ib_reg_umr_init, 4723 NULL), 4724 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4725 mlx5_ib_stage_delay_drop_init, 4726 mlx5_ib_stage_delay_drop_cleanup), 4727 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4728 mlx5_ib_restrack_init, 4729 NULL), 4730 }; 4731 4732 const struct mlx5_ib_profile raw_eth_profile = { 4733 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4734 mlx5_ib_stage_init_init, 4735 mlx5_ib_stage_init_cleanup), 4736 STAGE_CREATE(MLX5_IB_STAGE_FS, 4737 mlx5_ib_fs_init, 4738 mlx5_ib_fs_cleanup), 4739 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4740 mlx5_ib_stage_caps_init, 4741 mlx5_ib_stage_caps_cleanup), 4742 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4743 mlx5_ib_stage_raw_eth_non_default_cb, 4744 NULL), 4745 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4746 mlx5_ib_roce_init, 4747 mlx5_ib_roce_cleanup), 4748 STAGE_CREATE(MLX5_IB_STAGE_QP, 4749 mlx5_init_qp_table, 4750 mlx5_cleanup_qp_table), 4751 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4752 mlx5_init_srq_table, 4753 mlx5_cleanup_srq_table), 4754 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4755 mlx5_ib_dev_res_init, 4756 mlx5_ib_dev_res_cleanup), 4757 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4758 mlx5_ib_counters_init, 4759 mlx5_ib_counters_cleanup), 4760 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4761 mlx5_ib_stage_cong_debugfs_init, 4762 mlx5_ib_stage_cong_debugfs_cleanup), 4763 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4764 mlx5_ib_stage_bfrag_init, 4765 mlx5_ib_stage_bfrag_cleanup), 4766 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4767 NULL, 4768 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4769 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4770 mlx5_ib_devx_init, 4771 mlx5_ib_devx_cleanup), 4772 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4773 mlx5_ib_stage_ib_reg_init, 4774 mlx5_ib_stage_ib_reg_cleanup), 4775 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4776 mlx5_ib_stage_dev_notifier_init, 4777 mlx5_ib_stage_dev_notifier_cleanup), 4778 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4779 mlx5_ib_stage_post_ib_reg_umr_init, 4780 NULL), 4781 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4782 mlx5_ib_stage_delay_drop_init, 4783 mlx5_ib_stage_delay_drop_cleanup), 4784 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4785 mlx5_ib_restrack_init, 4786 NULL), 4787 }; 4788 4789 static const struct mlx5_ib_profile plane_profile = { 4790 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4791 mlx5_ib_stage_init_init, 4792 mlx5_ib_stage_init_cleanup), 4793 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4794 mlx5_ib_stage_caps_init, 4795 mlx5_ib_stage_caps_cleanup), 4796 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4797 mlx5_ib_stage_non_default_cb, 4798 NULL), 4799 STAGE_CREATE(MLX5_IB_STAGE_QP, 4800 mlx5_init_qp_table, 4801 mlx5_cleanup_qp_table), 4802 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4803 mlx5_init_srq_table, 4804 mlx5_cleanup_srq_table), 4805 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4806 mlx5_ib_dev_res_init, 4807 mlx5_ib_dev_res_cleanup), 4808 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4809 mlx5_ib_stage_bfrag_init, 4810 mlx5_ib_stage_bfrag_cleanup), 4811 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4812 mlx5_ib_stage_ib_reg_init, 4813 mlx5_ib_stage_ib_reg_cleanup), 4814 }; 4815 4816 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4817 enum rdma_nl_dev_type type, 4818 const char *name) 4819 { 4820 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 4821 enum rdma_link_layer ll; 4822 int ret; 4823 4824 if (mparent->smi_dev) 4825 return ERR_PTR(-EEXIST); 4826 4827 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 4828 port_type)); 4829 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 4830 ll != IB_LINK_LAYER_INFINIBAND || 4831 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 4832 return ERR_PTR(-EOPNOTSUPP); 4833 4834 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4835 mlx5_core_net(mparent->mdev)); 4836 if (!mplane) 4837 return ERR_PTR(-ENOMEM); 4838 4839 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 4840 sizeof(*mplane->port), GFP_KERNEL); 4841 if (!mplane->port) { 4842 ret = -ENOMEM; 4843 goto fail_kcalloc; 4844 } 4845 4846 mplane->ib_dev.type = type; 4847 mplane->mdev = mparent->mdev; 4848 mplane->num_ports = mparent->num_plane; 4849 mplane->sub_dev_name = name; 4850 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 4851 4852 ret = __mlx5_ib_add(mplane, &plane_profile); 4853 if (ret) 4854 goto fail_ib_add; 4855 4856 mparent->smi_dev = mplane; 4857 return &mplane->ib_dev; 4858 4859 fail_ib_add: 4860 kfree(mplane->port); 4861 fail_kcalloc: 4862 ib_dealloc_device(&mplane->ib_dev); 4863 return ERR_PTR(ret); 4864 } 4865 4866 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 4867 { 4868 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 4869 4870 to_mdev(sub_dev->parent)->smi_dev = NULL; 4871 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 4872 } 4873 4874 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4875 const struct auxiliary_device_id *id) 4876 { 4877 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4878 struct mlx5_core_dev *mdev = idev->mdev; 4879 struct mlx5_ib_multiport_info *mpi; 4880 struct mlx5_ib_dev *dev; 4881 bool bound = false; 4882 int err; 4883 4884 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4885 if (!mpi) 4886 return -ENOMEM; 4887 4888 mpi->mdev = mdev; 4889 err = mlx5_query_nic_vport_system_image_guid(mdev, 4890 &mpi->sys_image_guid); 4891 if (err) { 4892 kfree(mpi); 4893 return err; 4894 } 4895 4896 mutex_lock(&mlx5_ib_multiport_mutex); 4897 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4898 if (dev->sys_image_guid == mpi->sys_image_guid && 4899 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 4900 bound = mlx5_ib_bind_slave_port(dev, mpi); 4901 4902 if (bound) { 4903 rdma_roce_rescan_device(&dev->ib_dev); 4904 mpi->ibdev->ib_active = true; 4905 break; 4906 } 4907 } 4908 4909 if (!bound) { 4910 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4911 dev_dbg(mdev->device, 4912 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4913 } 4914 mutex_unlock(&mlx5_ib_multiport_mutex); 4915 4916 auxiliary_set_drvdata(adev, mpi); 4917 return 0; 4918 } 4919 4920 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4921 { 4922 struct mlx5_ib_multiport_info *mpi; 4923 4924 mpi = auxiliary_get_drvdata(adev); 4925 mutex_lock(&mlx5_ib_multiport_mutex); 4926 if (mpi->ibdev) 4927 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4928 else 4929 list_del(&mpi->list); 4930 mutex_unlock(&mlx5_ib_multiport_mutex); 4931 kfree(mpi); 4932 } 4933 4934 static int mlx5r_probe(struct auxiliary_device *adev, 4935 const struct auxiliary_device_id *id) 4936 { 4937 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4938 struct mlx5_core_dev *mdev = idev->mdev; 4939 const struct mlx5_ib_profile *profile; 4940 int port_type_cap, num_ports, ret; 4941 enum rdma_link_layer ll; 4942 struct mlx5_ib_dev *dev; 4943 4944 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4945 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4946 4947 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4948 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4949 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 4950 mlx5_core_net(mdev)); 4951 if (!dev) 4952 return -ENOMEM; 4953 4954 if (ll == IB_LINK_LAYER_INFINIBAND) { 4955 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 4956 if (ret) 4957 goto fail; 4958 } 4959 4960 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4961 GFP_KERNEL); 4962 if (!dev->port) { 4963 ret = -ENOMEM; 4964 goto fail; 4965 } 4966 4967 dev->mdev = mdev; 4968 dev->num_ports = num_ports; 4969 dev->ib_dev.phys_port_cnt = num_ports; 4970 4971 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4972 profile = &raw_eth_profile; 4973 else 4974 profile = &pf_profile; 4975 4976 ret = __mlx5_ib_add(dev, profile); 4977 if (ret) 4978 goto fail_ib_add; 4979 4980 auxiliary_set_drvdata(adev, dev); 4981 return 0; 4982 4983 fail_ib_add: 4984 kfree(dev->port); 4985 fail: 4986 ib_dealloc_device(&dev->ib_dev); 4987 return ret; 4988 } 4989 4990 static void mlx5r_remove(struct auxiliary_device *adev) 4991 { 4992 struct mlx5_ib_dev *dev; 4993 4994 dev = auxiliary_get_drvdata(adev); 4995 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4996 } 4997 4998 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4999 { .name = MLX5_ADEV_NAME ".multiport", }, 5000 {}, 5001 }; 5002 5003 static const struct auxiliary_device_id mlx5r_id_table[] = { 5004 { .name = MLX5_ADEV_NAME ".rdma", }, 5005 {}, 5006 }; 5007 5008 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5009 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5010 5011 static struct auxiliary_driver mlx5r_mp_driver = { 5012 .name = "multiport", 5013 .probe = mlx5r_mp_probe, 5014 .remove = mlx5r_mp_remove, 5015 .id_table = mlx5r_mp_id_table, 5016 }; 5017 5018 static struct auxiliary_driver mlx5r_driver = { 5019 .name = "rdma", 5020 .probe = mlx5r_probe, 5021 .remove = mlx5r_remove, 5022 .id_table = mlx5r_id_table, 5023 }; 5024 5025 static int __init mlx5_ib_init(void) 5026 { 5027 int ret; 5028 5029 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 5030 if (!xlt_emergency_page) 5031 return -ENOMEM; 5032 5033 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5034 if (!mlx5_ib_event_wq) { 5035 free_page((unsigned long)xlt_emergency_page); 5036 return -ENOMEM; 5037 } 5038 5039 ret = mlx5_ib_qp_event_init(); 5040 if (ret) 5041 goto qp_event_err; 5042 5043 mlx5_ib_odp_init(); 5044 ret = mlx5r_rep_init(); 5045 if (ret) 5046 goto rep_err; 5047 ret = mlx5_data_direct_driver_register(); 5048 if (ret) 5049 goto dd_err; 5050 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5051 if (ret) 5052 goto mp_err; 5053 ret = auxiliary_driver_register(&mlx5r_driver); 5054 if (ret) 5055 goto drv_err; 5056 5057 return 0; 5058 5059 drv_err: 5060 auxiliary_driver_unregister(&mlx5r_mp_driver); 5061 mp_err: 5062 mlx5_data_direct_driver_unregister(); 5063 dd_err: 5064 mlx5r_rep_cleanup(); 5065 rep_err: 5066 mlx5_ib_qp_event_cleanup(); 5067 qp_event_err: 5068 destroy_workqueue(mlx5_ib_event_wq); 5069 free_page((unsigned long)xlt_emergency_page); 5070 return ret; 5071 } 5072 5073 static void __exit mlx5_ib_cleanup(void) 5074 { 5075 mlx5_data_direct_driver_unregister(); 5076 auxiliary_driver_unregister(&mlx5r_driver); 5077 auxiliary_driver_unregister(&mlx5r_mp_driver); 5078 mlx5r_rep_cleanup(); 5079 5080 mlx5_ib_qp_event_cleanup(); 5081 destroy_workqueue(mlx5_ib_event_wq); 5082 free_page((unsigned long)xlt_emergency_page); 5083 } 5084 5085 module_init(mlx5_ib_init); 5086 module_exit(mlx5_ib_cleanup); 5087