1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/delay.h> 45 #include <rdma/ib_user_verbs.h> 46 #include <rdma/ib_addr.h> 47 #include <rdma/ib_cache.h> 48 #include <linux/mlx5/port.h> 49 #include <linux/mlx5/vport.h> 50 #include <linux/list.h> 51 #include <rdma/ib_smi.h> 52 #include <rdma/ib_umem.h> 53 #include <linux/in.h> 54 #include <linux/etherdevice.h> 55 #include <linux/mlx5/fs.h> 56 #include "user.h" 57 #include "mlx5_ib.h" 58 59 #define DRIVER_NAME "mlx5_ib" 60 #define DRIVER_VERSION "2.2-1" 61 #define DRIVER_RELDATE "Feb 2014" 62 63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 65 MODULE_LICENSE("Dual BSD/GPL"); 66 MODULE_VERSION(DRIVER_VERSION); 67 68 static int deprecated_prof_sel = 2; 69 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 70 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 71 72 static char mlx5_version[] = 73 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 74 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 75 76 enum { 77 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 78 }; 79 80 static enum rdma_link_layer 81 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 82 { 83 switch (port_type_cap) { 84 case MLX5_CAP_PORT_TYPE_IB: 85 return IB_LINK_LAYER_INFINIBAND; 86 case MLX5_CAP_PORT_TYPE_ETH: 87 return IB_LINK_LAYER_ETHERNET; 88 default: 89 return IB_LINK_LAYER_UNSPECIFIED; 90 } 91 } 92 93 static enum rdma_link_layer 94 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 95 { 96 struct mlx5_ib_dev *dev = to_mdev(device); 97 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 98 99 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 100 } 101 102 static int mlx5_netdev_event(struct notifier_block *this, 103 unsigned long event, void *ptr) 104 { 105 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 106 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 107 roce.nb); 108 109 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 110 return NOTIFY_DONE; 111 112 write_lock(&ibdev->roce.netdev_lock); 113 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 114 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 115 write_unlock(&ibdev->roce.netdev_lock); 116 117 return NOTIFY_DONE; 118 } 119 120 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 121 u8 port_num) 122 { 123 struct mlx5_ib_dev *ibdev = to_mdev(device); 124 struct net_device *ndev; 125 126 /* Ensure ndev does not disappear before we invoke dev_hold() 127 */ 128 read_lock(&ibdev->roce.netdev_lock); 129 ndev = ibdev->roce.netdev; 130 if (ndev) 131 dev_hold(ndev); 132 read_unlock(&ibdev->roce.netdev_lock); 133 134 return ndev; 135 } 136 137 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 138 struct ib_port_attr *props) 139 { 140 struct mlx5_ib_dev *dev = to_mdev(device); 141 struct net_device *ndev; 142 enum ib_mtu ndev_ib_mtu; 143 u16 qkey_viol_cntr; 144 145 memset(props, 0, sizeof(*props)); 146 147 props->port_cap_flags |= IB_PORT_CM_SUP; 148 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 149 150 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 151 roce_address_table_size); 152 props->max_mtu = IB_MTU_4096; 153 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 154 props->pkey_tbl_len = 1; 155 props->state = IB_PORT_DOWN; 156 props->phys_state = 3; 157 158 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 159 props->qkey_viol_cntr = qkey_viol_cntr; 160 161 ndev = mlx5_ib_get_netdev(device, port_num); 162 if (!ndev) 163 return 0; 164 165 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 166 props->state = IB_PORT_ACTIVE; 167 props->phys_state = 5; 168 } 169 170 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 171 172 dev_put(ndev); 173 174 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 175 176 props->active_width = IB_WIDTH_4X; /* TODO */ 177 props->active_speed = IB_SPEED_QDR; /* TODO */ 178 179 return 0; 180 } 181 182 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 183 const struct ib_gid_attr *attr, 184 void *mlx5_addr) 185 { 186 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 187 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 188 source_l3_address); 189 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 190 source_mac_47_32); 191 192 if (!gid) 193 return; 194 195 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 196 197 if (is_vlan_dev(attr->ndev)) { 198 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 199 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 200 } 201 202 switch (attr->gid_type) { 203 case IB_GID_TYPE_IB: 204 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 205 break; 206 case IB_GID_TYPE_ROCE_UDP_ENCAP: 207 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 208 break; 209 210 default: 211 WARN_ON(true); 212 } 213 214 if (attr->gid_type != IB_GID_TYPE_IB) { 215 if (ipv6_addr_v4mapped((void *)gid)) 216 MLX5_SET_RA(mlx5_addr, roce_l3_type, 217 MLX5_ROCE_L3_TYPE_IPV4); 218 else 219 MLX5_SET_RA(mlx5_addr, roce_l3_type, 220 MLX5_ROCE_L3_TYPE_IPV6); 221 } 222 223 if ((attr->gid_type == IB_GID_TYPE_IB) || 224 !ipv6_addr_v4mapped((void *)gid)) 225 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 226 else 227 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 228 } 229 230 static int set_roce_addr(struct ib_device *device, u8 port_num, 231 unsigned int index, 232 const union ib_gid *gid, 233 const struct ib_gid_attr *attr) 234 { 235 struct mlx5_ib_dev *dev = to_mdev(device); 236 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; 237 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; 238 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 239 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 240 241 if (ll != IB_LINK_LAYER_ETHERNET) 242 return -EINVAL; 243 244 memset(in, 0, sizeof(in)); 245 246 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 247 248 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 249 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 250 251 memset(out, 0, sizeof(out)); 252 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 253 } 254 255 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 256 unsigned int index, const union ib_gid *gid, 257 const struct ib_gid_attr *attr, 258 __always_unused void **context) 259 { 260 return set_roce_addr(device, port_num, index, gid, attr); 261 } 262 263 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 264 unsigned int index, __always_unused void **context) 265 { 266 return set_roce_addr(device, port_num, index, NULL, NULL); 267 } 268 269 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 270 int index) 271 { 272 struct ib_gid_attr attr; 273 union ib_gid gid; 274 275 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 276 return 0; 277 278 if (!attr.ndev) 279 return 0; 280 281 dev_put(attr.ndev); 282 283 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 284 return 0; 285 286 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 287 } 288 289 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 290 { 291 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 292 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 293 return 0; 294 } 295 296 enum { 297 MLX5_VPORT_ACCESS_METHOD_MAD, 298 MLX5_VPORT_ACCESS_METHOD_HCA, 299 MLX5_VPORT_ACCESS_METHOD_NIC, 300 }; 301 302 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 303 { 304 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 305 return MLX5_VPORT_ACCESS_METHOD_MAD; 306 307 if (mlx5_ib_port_link_layer(ibdev, 1) == 308 IB_LINK_LAYER_ETHERNET) 309 return MLX5_VPORT_ACCESS_METHOD_NIC; 310 311 return MLX5_VPORT_ACCESS_METHOD_HCA; 312 } 313 314 static void get_atomic_caps(struct mlx5_ib_dev *dev, 315 struct ib_device_attr *props) 316 { 317 u8 tmp; 318 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 319 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 320 u8 atomic_req_8B_endianness_mode = 321 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 322 323 /* Check if HW supports 8 bytes standard atomic operations and capable 324 * of host endianness respond 325 */ 326 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 327 if (((atomic_operations & tmp) == tmp) && 328 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 329 (atomic_req_8B_endianness_mode)) { 330 props->atomic_cap = IB_ATOMIC_HCA; 331 } else { 332 props->atomic_cap = IB_ATOMIC_NONE; 333 } 334 } 335 336 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 337 __be64 *sys_image_guid) 338 { 339 struct mlx5_ib_dev *dev = to_mdev(ibdev); 340 struct mlx5_core_dev *mdev = dev->mdev; 341 u64 tmp; 342 int err; 343 344 switch (mlx5_get_vport_access_method(ibdev)) { 345 case MLX5_VPORT_ACCESS_METHOD_MAD: 346 return mlx5_query_mad_ifc_system_image_guid(ibdev, 347 sys_image_guid); 348 349 case MLX5_VPORT_ACCESS_METHOD_HCA: 350 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 351 break; 352 353 case MLX5_VPORT_ACCESS_METHOD_NIC: 354 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 355 break; 356 357 default: 358 return -EINVAL; 359 } 360 361 if (!err) 362 *sys_image_guid = cpu_to_be64(tmp); 363 364 return err; 365 366 } 367 368 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 369 u16 *max_pkeys) 370 { 371 struct mlx5_ib_dev *dev = to_mdev(ibdev); 372 struct mlx5_core_dev *mdev = dev->mdev; 373 374 switch (mlx5_get_vport_access_method(ibdev)) { 375 case MLX5_VPORT_ACCESS_METHOD_MAD: 376 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 377 378 case MLX5_VPORT_ACCESS_METHOD_HCA: 379 case MLX5_VPORT_ACCESS_METHOD_NIC: 380 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 381 pkey_table_size)); 382 return 0; 383 384 default: 385 return -EINVAL; 386 } 387 } 388 389 static int mlx5_query_vendor_id(struct ib_device *ibdev, 390 u32 *vendor_id) 391 { 392 struct mlx5_ib_dev *dev = to_mdev(ibdev); 393 394 switch (mlx5_get_vport_access_method(ibdev)) { 395 case MLX5_VPORT_ACCESS_METHOD_MAD: 396 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 397 398 case MLX5_VPORT_ACCESS_METHOD_HCA: 399 case MLX5_VPORT_ACCESS_METHOD_NIC: 400 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 401 402 default: 403 return -EINVAL; 404 } 405 } 406 407 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 408 __be64 *node_guid) 409 { 410 u64 tmp; 411 int err; 412 413 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 414 case MLX5_VPORT_ACCESS_METHOD_MAD: 415 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 416 417 case MLX5_VPORT_ACCESS_METHOD_HCA: 418 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 419 break; 420 421 case MLX5_VPORT_ACCESS_METHOD_NIC: 422 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 423 break; 424 425 default: 426 return -EINVAL; 427 } 428 429 if (!err) 430 *node_guid = cpu_to_be64(tmp); 431 432 return err; 433 } 434 435 struct mlx5_reg_node_desc { 436 u8 desc[64]; 437 }; 438 439 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 440 { 441 struct mlx5_reg_node_desc in; 442 443 if (mlx5_use_mad_ifc(dev)) 444 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 445 446 memset(&in, 0, sizeof(in)); 447 448 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 449 sizeof(struct mlx5_reg_node_desc), 450 MLX5_REG_NODE_DESC, 0, 0); 451 } 452 453 static int mlx5_ib_query_device(struct ib_device *ibdev, 454 struct ib_device_attr *props, 455 struct ib_udata *uhw) 456 { 457 struct mlx5_ib_dev *dev = to_mdev(ibdev); 458 struct mlx5_core_dev *mdev = dev->mdev; 459 int err = -ENOMEM; 460 int max_rq_sg; 461 int max_sq_sg; 462 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 463 struct mlx5_ib_query_device_resp resp = {}; 464 size_t resp_len; 465 u64 max_tso; 466 467 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 468 if (uhw->outlen && uhw->outlen < resp_len) 469 return -EINVAL; 470 else 471 resp.response_length = resp_len; 472 473 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 474 return -EINVAL; 475 476 memset(props, 0, sizeof(*props)); 477 err = mlx5_query_system_image_guid(ibdev, 478 &props->sys_image_guid); 479 if (err) 480 return err; 481 482 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 483 if (err) 484 return err; 485 486 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 487 if (err) 488 return err; 489 490 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 491 (fw_rev_min(dev->mdev) << 16) | 492 fw_rev_sub(dev->mdev); 493 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 494 IB_DEVICE_PORT_ACTIVE_EVENT | 495 IB_DEVICE_SYS_IMAGE_GUID | 496 IB_DEVICE_RC_RNR_NAK_GEN; 497 498 if (MLX5_CAP_GEN(mdev, pkv)) 499 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 500 if (MLX5_CAP_GEN(mdev, qkv)) 501 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 502 if (MLX5_CAP_GEN(mdev, apm)) 503 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 504 if (MLX5_CAP_GEN(mdev, xrc)) 505 props->device_cap_flags |= IB_DEVICE_XRC; 506 if (MLX5_CAP_GEN(mdev, imaicl)) { 507 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 508 IB_DEVICE_MEM_WINDOW_TYPE_2B; 509 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 510 /* We support 'Gappy' memory registration too */ 511 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 512 } 513 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 514 if (MLX5_CAP_GEN(mdev, sho)) { 515 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 516 /* At this stage no support for signature handover */ 517 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 518 IB_PROT_T10DIF_TYPE_2 | 519 IB_PROT_T10DIF_TYPE_3; 520 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 521 IB_GUARD_T10DIF_CSUM; 522 } 523 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 524 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 525 526 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 527 if (MLX5_CAP_ETH(mdev, csum_cap)) 528 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 529 530 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 531 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 532 if (max_tso) { 533 resp.tso_caps.max_tso = 1 << max_tso; 534 resp.tso_caps.supported_qpts |= 535 1 << IB_QPT_RAW_PACKET; 536 resp.response_length += sizeof(resp.tso_caps); 537 } 538 } 539 } 540 541 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 542 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 543 props->device_cap_flags |= IB_DEVICE_UD_TSO; 544 } 545 546 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 547 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 548 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 549 550 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 551 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 552 553 props->vendor_part_id = mdev->pdev->device; 554 props->hw_ver = mdev->pdev->revision; 555 556 props->max_mr_size = ~0ull; 557 props->page_size_cap = ~(min_page_size - 1); 558 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 559 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 560 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 561 sizeof(struct mlx5_wqe_data_seg); 562 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 563 sizeof(struct mlx5_wqe_ctrl_seg)) / 564 sizeof(struct mlx5_wqe_data_seg); 565 props->max_sge = min(max_rq_sg, max_sq_sg); 566 props->max_sge_rd = MLX5_MAX_SGE_RD; 567 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 568 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 569 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 570 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 571 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 572 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 573 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 574 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 575 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 576 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 577 props->max_srq_sge = max_rq_sg - 1; 578 props->max_fast_reg_page_list_len = 579 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 580 get_atomic_caps(dev, props); 581 props->masked_atomic_cap = IB_ATOMIC_NONE; 582 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 583 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 584 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 585 props->max_mcast_grp; 586 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 587 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 588 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 589 590 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 591 if (MLX5_CAP_GEN(mdev, pg)) 592 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 593 props->odp_caps = dev->odp_caps; 594 #endif 595 596 if (MLX5_CAP_GEN(mdev, cd)) 597 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 598 599 if (!mlx5_core_is_pf(mdev)) 600 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 601 602 if (uhw->outlen) { 603 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 604 605 if (err) 606 return err; 607 } 608 609 return 0; 610 } 611 612 enum mlx5_ib_width { 613 MLX5_IB_WIDTH_1X = 1 << 0, 614 MLX5_IB_WIDTH_2X = 1 << 1, 615 MLX5_IB_WIDTH_4X = 1 << 2, 616 MLX5_IB_WIDTH_8X = 1 << 3, 617 MLX5_IB_WIDTH_12X = 1 << 4 618 }; 619 620 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 621 u8 *ib_width) 622 { 623 struct mlx5_ib_dev *dev = to_mdev(ibdev); 624 int err = 0; 625 626 if (active_width & MLX5_IB_WIDTH_1X) { 627 *ib_width = IB_WIDTH_1X; 628 } else if (active_width & MLX5_IB_WIDTH_2X) { 629 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 630 (int)active_width); 631 err = -EINVAL; 632 } else if (active_width & MLX5_IB_WIDTH_4X) { 633 *ib_width = IB_WIDTH_4X; 634 } else if (active_width & MLX5_IB_WIDTH_8X) { 635 *ib_width = IB_WIDTH_8X; 636 } else if (active_width & MLX5_IB_WIDTH_12X) { 637 *ib_width = IB_WIDTH_12X; 638 } else { 639 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 640 (int)active_width); 641 err = -EINVAL; 642 } 643 644 return err; 645 } 646 647 static int mlx5_mtu_to_ib_mtu(int mtu) 648 { 649 switch (mtu) { 650 case 256: return 1; 651 case 512: return 2; 652 case 1024: return 3; 653 case 2048: return 4; 654 case 4096: return 5; 655 default: 656 pr_warn("invalid mtu\n"); 657 return -1; 658 } 659 } 660 661 enum ib_max_vl_num { 662 __IB_MAX_VL_0 = 1, 663 __IB_MAX_VL_0_1 = 2, 664 __IB_MAX_VL_0_3 = 3, 665 __IB_MAX_VL_0_7 = 4, 666 __IB_MAX_VL_0_14 = 5, 667 }; 668 669 enum mlx5_vl_hw_cap { 670 MLX5_VL_HW_0 = 1, 671 MLX5_VL_HW_0_1 = 2, 672 MLX5_VL_HW_0_2 = 3, 673 MLX5_VL_HW_0_3 = 4, 674 MLX5_VL_HW_0_4 = 5, 675 MLX5_VL_HW_0_5 = 6, 676 MLX5_VL_HW_0_6 = 7, 677 MLX5_VL_HW_0_7 = 8, 678 MLX5_VL_HW_0_14 = 15 679 }; 680 681 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 682 u8 *max_vl_num) 683 { 684 switch (vl_hw_cap) { 685 case MLX5_VL_HW_0: 686 *max_vl_num = __IB_MAX_VL_0; 687 break; 688 case MLX5_VL_HW_0_1: 689 *max_vl_num = __IB_MAX_VL_0_1; 690 break; 691 case MLX5_VL_HW_0_3: 692 *max_vl_num = __IB_MAX_VL_0_3; 693 break; 694 case MLX5_VL_HW_0_7: 695 *max_vl_num = __IB_MAX_VL_0_7; 696 break; 697 case MLX5_VL_HW_0_14: 698 *max_vl_num = __IB_MAX_VL_0_14; 699 break; 700 701 default: 702 return -EINVAL; 703 } 704 705 return 0; 706 } 707 708 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 709 struct ib_port_attr *props) 710 { 711 struct mlx5_ib_dev *dev = to_mdev(ibdev); 712 struct mlx5_core_dev *mdev = dev->mdev; 713 struct mlx5_hca_vport_context *rep; 714 u16 max_mtu; 715 u16 oper_mtu; 716 int err; 717 u8 ib_link_width_oper; 718 u8 vl_hw_cap; 719 720 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 721 if (!rep) { 722 err = -ENOMEM; 723 goto out; 724 } 725 726 memset(props, 0, sizeof(*props)); 727 728 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 729 if (err) 730 goto out; 731 732 props->lid = rep->lid; 733 props->lmc = rep->lmc; 734 props->sm_lid = rep->sm_lid; 735 props->sm_sl = rep->sm_sl; 736 props->state = rep->vport_state; 737 props->phys_state = rep->port_physical_state; 738 props->port_cap_flags = rep->cap_mask1; 739 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 740 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 741 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 742 props->bad_pkey_cntr = rep->pkey_violation_counter; 743 props->qkey_viol_cntr = rep->qkey_violation_counter; 744 props->subnet_timeout = rep->subnet_timeout; 745 props->init_type_reply = rep->init_type_reply; 746 props->grh_required = rep->grh_required; 747 748 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 749 if (err) 750 goto out; 751 752 err = translate_active_width(ibdev, ib_link_width_oper, 753 &props->active_width); 754 if (err) 755 goto out; 756 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, 757 port); 758 if (err) 759 goto out; 760 761 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 762 763 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 764 765 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 766 767 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 768 769 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 770 if (err) 771 goto out; 772 773 err = translate_max_vl_num(ibdev, vl_hw_cap, 774 &props->max_vl_num); 775 out: 776 kfree(rep); 777 return err; 778 } 779 780 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 781 struct ib_port_attr *props) 782 { 783 switch (mlx5_get_vport_access_method(ibdev)) { 784 case MLX5_VPORT_ACCESS_METHOD_MAD: 785 return mlx5_query_mad_ifc_port(ibdev, port, props); 786 787 case MLX5_VPORT_ACCESS_METHOD_HCA: 788 return mlx5_query_hca_port(ibdev, port, props); 789 790 case MLX5_VPORT_ACCESS_METHOD_NIC: 791 return mlx5_query_port_roce(ibdev, port, props); 792 793 default: 794 return -EINVAL; 795 } 796 } 797 798 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 799 union ib_gid *gid) 800 { 801 struct mlx5_ib_dev *dev = to_mdev(ibdev); 802 struct mlx5_core_dev *mdev = dev->mdev; 803 804 switch (mlx5_get_vport_access_method(ibdev)) { 805 case MLX5_VPORT_ACCESS_METHOD_MAD: 806 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 807 808 case MLX5_VPORT_ACCESS_METHOD_HCA: 809 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 810 811 default: 812 return -EINVAL; 813 } 814 815 } 816 817 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 818 u16 *pkey) 819 { 820 struct mlx5_ib_dev *dev = to_mdev(ibdev); 821 struct mlx5_core_dev *mdev = dev->mdev; 822 823 switch (mlx5_get_vport_access_method(ibdev)) { 824 case MLX5_VPORT_ACCESS_METHOD_MAD: 825 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 826 827 case MLX5_VPORT_ACCESS_METHOD_HCA: 828 case MLX5_VPORT_ACCESS_METHOD_NIC: 829 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 830 pkey); 831 default: 832 return -EINVAL; 833 } 834 } 835 836 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 837 struct ib_device_modify *props) 838 { 839 struct mlx5_ib_dev *dev = to_mdev(ibdev); 840 struct mlx5_reg_node_desc in; 841 struct mlx5_reg_node_desc out; 842 int err; 843 844 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 845 return -EOPNOTSUPP; 846 847 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 848 return 0; 849 850 /* 851 * If possible, pass node desc to FW, so it can generate 852 * a 144 trap. If cmd fails, just ignore. 853 */ 854 memcpy(&in, props->node_desc, 64); 855 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 856 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 857 if (err) 858 return err; 859 860 memcpy(ibdev->node_desc, props->node_desc, 64); 861 862 return err; 863 } 864 865 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 866 struct ib_port_modify *props) 867 { 868 struct mlx5_ib_dev *dev = to_mdev(ibdev); 869 struct ib_port_attr attr; 870 u32 tmp; 871 int err; 872 873 mutex_lock(&dev->cap_mask_mutex); 874 875 err = mlx5_ib_query_port(ibdev, port, &attr); 876 if (err) 877 goto out; 878 879 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 880 ~props->clr_port_cap_mask; 881 882 err = mlx5_set_port_caps(dev->mdev, port, tmp); 883 884 out: 885 mutex_unlock(&dev->cap_mask_mutex); 886 return err; 887 } 888 889 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 890 struct ib_udata *udata) 891 { 892 struct mlx5_ib_dev *dev = to_mdev(ibdev); 893 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 894 struct mlx5_ib_alloc_ucontext_resp resp = {}; 895 struct mlx5_ib_ucontext *context; 896 struct mlx5_uuar_info *uuari; 897 struct mlx5_uar *uars; 898 int gross_uuars; 899 int num_uars; 900 int ver; 901 int uuarn; 902 int err; 903 int i; 904 size_t reqlen; 905 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 906 max_cqe_version); 907 908 if (!dev->ib_active) 909 return ERR_PTR(-EAGAIN); 910 911 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 912 return ERR_PTR(-EINVAL); 913 914 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 915 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 916 ver = 0; 917 else if (reqlen >= min_req_v2) 918 ver = 2; 919 else 920 return ERR_PTR(-EINVAL); 921 922 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 923 if (err) 924 return ERR_PTR(err); 925 926 if (req.flags) 927 return ERR_PTR(-EINVAL); 928 929 if (req.total_num_uuars > MLX5_MAX_UUARS) 930 return ERR_PTR(-ENOMEM); 931 932 if (req.total_num_uuars == 0) 933 return ERR_PTR(-EINVAL); 934 935 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 936 return ERR_PTR(-EOPNOTSUPP); 937 938 if (reqlen > sizeof(req) && 939 !ib_is_udata_cleared(udata, sizeof(req), 940 reqlen - sizeof(req))) 941 return ERR_PTR(-EOPNOTSUPP); 942 943 req.total_num_uuars = ALIGN(req.total_num_uuars, 944 MLX5_NON_FP_BF_REGS_PER_PAGE); 945 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 946 return ERR_PTR(-EINVAL); 947 948 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 949 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 950 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 951 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 952 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 953 resp.cache_line_size = L1_CACHE_BYTES; 954 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 955 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 956 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 957 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 958 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 959 resp.cqe_version = min_t(__u8, 960 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 961 req.max_cqe_version); 962 resp.response_length = min(offsetof(typeof(resp), response_length) + 963 sizeof(resp.response_length), udata->outlen); 964 965 context = kzalloc(sizeof(*context), GFP_KERNEL); 966 if (!context) 967 return ERR_PTR(-ENOMEM); 968 969 uuari = &context->uuari; 970 mutex_init(&uuari->lock); 971 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 972 if (!uars) { 973 err = -ENOMEM; 974 goto out_ctx; 975 } 976 977 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 978 sizeof(*uuari->bitmap), 979 GFP_KERNEL); 980 if (!uuari->bitmap) { 981 err = -ENOMEM; 982 goto out_uar_ctx; 983 } 984 /* 985 * clear all fast path uuars 986 */ 987 for (i = 0; i < gross_uuars; i++) { 988 uuarn = i & 3; 989 if (uuarn == 2 || uuarn == 3) 990 set_bit(i, uuari->bitmap); 991 } 992 993 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 994 if (!uuari->count) { 995 err = -ENOMEM; 996 goto out_bitmap; 997 } 998 999 for (i = 0; i < num_uars; i++) { 1000 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1001 if (err) 1002 goto out_count; 1003 } 1004 1005 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1006 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1007 #endif 1008 1009 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1010 err = mlx5_core_alloc_transport_domain(dev->mdev, 1011 &context->tdn); 1012 if (err) 1013 goto out_uars; 1014 } 1015 1016 INIT_LIST_HEAD(&context->vma_private_list); 1017 INIT_LIST_HEAD(&context->db_page_list); 1018 mutex_init(&context->db_page_mutex); 1019 1020 resp.tot_uuars = req.total_num_uuars; 1021 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1022 1023 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1024 resp.response_length += sizeof(resp.cqe_version); 1025 1026 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1027 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE; 1028 resp.response_length += sizeof(resp.cmds_supp_uhw); 1029 } 1030 1031 /* 1032 * We don't want to expose information from the PCI bar that is located 1033 * after 4096 bytes, so if the arch only supports larger pages, let's 1034 * pretend we don't support reading the HCA's core clock. This is also 1035 * forced by mmap function. 1036 */ 1037 if (PAGE_SIZE <= 4096 && 1038 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1039 resp.comp_mask |= 1040 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1041 resp.hca_core_clock_offset = 1042 offsetof(struct mlx5_init_seg, internal_timer_h) % 1043 PAGE_SIZE; 1044 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1045 sizeof(resp.reserved2); 1046 } 1047 1048 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1049 if (err) 1050 goto out_td; 1051 1052 uuari->ver = ver; 1053 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1054 uuari->uars = uars; 1055 uuari->num_uars = num_uars; 1056 context->cqe_version = resp.cqe_version; 1057 1058 return &context->ibucontext; 1059 1060 out_td: 1061 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1062 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1063 1064 out_uars: 1065 for (i--; i >= 0; i--) 1066 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1067 out_count: 1068 kfree(uuari->count); 1069 1070 out_bitmap: 1071 kfree(uuari->bitmap); 1072 1073 out_uar_ctx: 1074 kfree(uars); 1075 1076 out_ctx: 1077 kfree(context); 1078 return ERR_PTR(err); 1079 } 1080 1081 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1082 { 1083 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1084 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1085 struct mlx5_uuar_info *uuari = &context->uuari; 1086 int i; 1087 1088 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1089 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1090 1091 for (i = 0; i < uuari->num_uars; i++) { 1092 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1093 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1094 } 1095 1096 kfree(uuari->count); 1097 kfree(uuari->bitmap); 1098 kfree(uuari->uars); 1099 kfree(context); 1100 1101 return 0; 1102 } 1103 1104 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1105 { 1106 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1107 } 1108 1109 static int get_command(unsigned long offset) 1110 { 1111 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1112 } 1113 1114 static int get_arg(unsigned long offset) 1115 { 1116 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1117 } 1118 1119 static int get_index(unsigned long offset) 1120 { 1121 return get_arg(offset); 1122 } 1123 1124 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1125 { 1126 /* vma_open is called when a new VMA is created on top of our VMA. This 1127 * is done through either mremap flow or split_vma (usually due to 1128 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1129 * as this VMA is strongly hardware related. Therefore we set the 1130 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1131 * calling us again and trying to do incorrect actions. We assume that 1132 * the original VMA size is exactly a single page, and therefore all 1133 * "splitting" operation will not happen to it. 1134 */ 1135 area->vm_ops = NULL; 1136 } 1137 1138 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1139 { 1140 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1141 1142 /* It's guaranteed that all VMAs opened on a FD are closed before the 1143 * file itself is closed, therefore no sync is needed with the regular 1144 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1145 * However need a sync with accessing the vma as part of 1146 * mlx5_ib_disassociate_ucontext. 1147 * The close operation is usually called under mm->mmap_sem except when 1148 * process is exiting. 1149 * The exiting case is handled explicitly as part of 1150 * mlx5_ib_disassociate_ucontext. 1151 */ 1152 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1153 1154 /* setting the vma context pointer to null in the mlx5_ib driver's 1155 * private data, to protect a race condition in 1156 * mlx5_ib_disassociate_ucontext(). 1157 */ 1158 mlx5_ib_vma_priv_data->vma = NULL; 1159 list_del(&mlx5_ib_vma_priv_data->list); 1160 kfree(mlx5_ib_vma_priv_data); 1161 } 1162 1163 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1164 .open = mlx5_ib_vma_open, 1165 .close = mlx5_ib_vma_close 1166 }; 1167 1168 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1169 struct mlx5_ib_ucontext *ctx) 1170 { 1171 struct mlx5_ib_vma_private_data *vma_prv; 1172 struct list_head *vma_head = &ctx->vma_private_list; 1173 1174 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1175 if (!vma_prv) 1176 return -ENOMEM; 1177 1178 vma_prv->vma = vma; 1179 vma->vm_private_data = vma_prv; 1180 vma->vm_ops = &mlx5_ib_vm_ops; 1181 1182 list_add(&vma_prv->list, vma_head); 1183 1184 return 0; 1185 } 1186 1187 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1188 { 1189 int ret; 1190 struct vm_area_struct *vma; 1191 struct mlx5_ib_vma_private_data *vma_private, *n; 1192 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1193 struct task_struct *owning_process = NULL; 1194 struct mm_struct *owning_mm = NULL; 1195 1196 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1197 if (!owning_process) 1198 return; 1199 1200 owning_mm = get_task_mm(owning_process); 1201 if (!owning_mm) { 1202 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1203 while (1) { 1204 put_task_struct(owning_process); 1205 usleep_range(1000, 2000); 1206 owning_process = get_pid_task(ibcontext->tgid, 1207 PIDTYPE_PID); 1208 if (!owning_process || 1209 owning_process->state == TASK_DEAD) { 1210 pr_info("disassociate ucontext done, task was terminated\n"); 1211 /* in case task was dead need to release the 1212 * task struct. 1213 */ 1214 if (owning_process) 1215 put_task_struct(owning_process); 1216 return; 1217 } 1218 } 1219 } 1220 1221 /* need to protect from a race on closing the vma as part of 1222 * mlx5_ib_vma_close. 1223 */ 1224 down_read(&owning_mm->mmap_sem); 1225 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1226 list) { 1227 vma = vma_private->vma; 1228 ret = zap_vma_ptes(vma, vma->vm_start, 1229 PAGE_SIZE); 1230 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1231 /* context going to be destroyed, should 1232 * not access ops any more. 1233 */ 1234 vma->vm_ops = NULL; 1235 list_del(&vma_private->list); 1236 kfree(vma_private); 1237 } 1238 up_read(&owning_mm->mmap_sem); 1239 mmput(owning_mm); 1240 put_task_struct(owning_process); 1241 } 1242 1243 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1244 { 1245 switch (cmd) { 1246 case MLX5_IB_MMAP_WC_PAGE: 1247 return "WC"; 1248 case MLX5_IB_MMAP_REGULAR_PAGE: 1249 return "best effort WC"; 1250 case MLX5_IB_MMAP_NC_PAGE: 1251 return "NC"; 1252 default: 1253 return NULL; 1254 } 1255 } 1256 1257 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1258 struct vm_area_struct *vma, 1259 struct mlx5_ib_ucontext *context) 1260 { 1261 struct mlx5_uuar_info *uuari = &context->uuari; 1262 int err; 1263 unsigned long idx; 1264 phys_addr_t pfn, pa; 1265 pgprot_t prot; 1266 1267 switch (cmd) { 1268 case MLX5_IB_MMAP_WC_PAGE: 1269 /* Some architectures don't support WC memory */ 1270 #if defined(CONFIG_X86) 1271 if (!pat_enabled()) 1272 return -EPERM; 1273 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1274 return -EPERM; 1275 #endif 1276 /* fall through */ 1277 case MLX5_IB_MMAP_REGULAR_PAGE: 1278 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1279 prot = pgprot_writecombine(vma->vm_page_prot); 1280 break; 1281 case MLX5_IB_MMAP_NC_PAGE: 1282 prot = pgprot_noncached(vma->vm_page_prot); 1283 break; 1284 default: 1285 return -EINVAL; 1286 } 1287 1288 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1289 return -EINVAL; 1290 1291 idx = get_index(vma->vm_pgoff); 1292 if (idx >= uuari->num_uars) 1293 return -EINVAL; 1294 1295 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1296 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1297 1298 vma->vm_page_prot = prot; 1299 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1300 PAGE_SIZE, vma->vm_page_prot); 1301 if (err) { 1302 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1303 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1304 return -EAGAIN; 1305 } 1306 1307 pa = pfn << PAGE_SHIFT; 1308 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1309 vma->vm_start, &pa); 1310 1311 return mlx5_ib_set_vma_data(vma, context); 1312 } 1313 1314 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1315 { 1316 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1317 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1318 unsigned long command; 1319 phys_addr_t pfn; 1320 1321 command = get_command(vma->vm_pgoff); 1322 switch (command) { 1323 case MLX5_IB_MMAP_WC_PAGE: 1324 case MLX5_IB_MMAP_NC_PAGE: 1325 case MLX5_IB_MMAP_REGULAR_PAGE: 1326 return uar_mmap(dev, command, vma, context); 1327 1328 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1329 return -ENOSYS; 1330 1331 case MLX5_IB_MMAP_CORE_CLOCK: 1332 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1333 return -EINVAL; 1334 1335 if (vma->vm_flags & VM_WRITE) 1336 return -EPERM; 1337 1338 /* Don't expose to user-space information it shouldn't have */ 1339 if (PAGE_SIZE > 4096) 1340 return -EOPNOTSUPP; 1341 1342 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1343 pfn = (dev->mdev->iseg_base + 1344 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1345 PAGE_SHIFT; 1346 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1347 PAGE_SIZE, vma->vm_page_prot)) 1348 return -EAGAIN; 1349 1350 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1351 vma->vm_start, 1352 (unsigned long long)pfn << PAGE_SHIFT); 1353 break; 1354 1355 default: 1356 return -EINVAL; 1357 } 1358 1359 return 0; 1360 } 1361 1362 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1363 struct ib_ucontext *context, 1364 struct ib_udata *udata) 1365 { 1366 struct mlx5_ib_alloc_pd_resp resp; 1367 struct mlx5_ib_pd *pd; 1368 int err; 1369 1370 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1371 if (!pd) 1372 return ERR_PTR(-ENOMEM); 1373 1374 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1375 if (err) { 1376 kfree(pd); 1377 return ERR_PTR(err); 1378 } 1379 1380 if (context) { 1381 resp.pdn = pd->pdn; 1382 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1383 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1384 kfree(pd); 1385 return ERR_PTR(-EFAULT); 1386 } 1387 } 1388 1389 return &pd->ibpd; 1390 } 1391 1392 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1393 { 1394 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1395 struct mlx5_ib_pd *mpd = to_mpd(pd); 1396 1397 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1398 kfree(mpd); 1399 1400 return 0; 1401 } 1402 1403 static bool outer_header_zero(u32 *match_criteria) 1404 { 1405 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1406 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1407 outer_headers); 1408 1409 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1410 outer_headers_c + 1, 1411 size - 1); 1412 } 1413 1414 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1415 union ib_flow_spec *ib_spec) 1416 { 1417 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1418 outer_headers); 1419 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1420 outer_headers); 1421 switch (ib_spec->type) { 1422 case IB_FLOW_SPEC_ETH: 1423 if (ib_spec->size != sizeof(ib_spec->eth)) 1424 return -EINVAL; 1425 1426 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1427 dmac_47_16), 1428 ib_spec->eth.mask.dst_mac); 1429 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1430 dmac_47_16), 1431 ib_spec->eth.val.dst_mac); 1432 1433 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1434 smac_47_16), 1435 ib_spec->eth.mask.src_mac); 1436 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1437 smac_47_16), 1438 ib_spec->eth.val.src_mac); 1439 1440 if (ib_spec->eth.mask.vlan_tag) { 1441 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1442 vlan_tag, 1); 1443 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1444 vlan_tag, 1); 1445 1446 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1447 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1448 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1449 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1450 1451 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1452 first_cfi, 1453 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1454 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1455 first_cfi, 1456 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1457 1458 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1459 first_prio, 1460 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1461 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1462 first_prio, 1463 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1464 } 1465 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1466 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1467 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1468 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1469 break; 1470 case IB_FLOW_SPEC_IPV4: 1471 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1472 return -EINVAL; 1473 1474 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1475 ethertype, 0xffff); 1476 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1477 ethertype, ETH_P_IP); 1478 1479 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1480 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1481 &ib_spec->ipv4.mask.src_ip, 1482 sizeof(ib_spec->ipv4.mask.src_ip)); 1483 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1484 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1485 &ib_spec->ipv4.val.src_ip, 1486 sizeof(ib_spec->ipv4.val.src_ip)); 1487 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1488 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1489 &ib_spec->ipv4.mask.dst_ip, 1490 sizeof(ib_spec->ipv4.mask.dst_ip)); 1491 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1492 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1493 &ib_spec->ipv4.val.dst_ip, 1494 sizeof(ib_spec->ipv4.val.dst_ip)); 1495 break; 1496 case IB_FLOW_SPEC_IPV6: 1497 if (ib_spec->size != sizeof(ib_spec->ipv6)) 1498 return -EINVAL; 1499 1500 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1501 ethertype, 0xffff); 1502 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1503 ethertype, ETH_P_IPV6); 1504 1505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1506 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1507 &ib_spec->ipv6.mask.src_ip, 1508 sizeof(ib_spec->ipv6.mask.src_ip)); 1509 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1510 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1511 &ib_spec->ipv6.val.src_ip, 1512 sizeof(ib_spec->ipv6.val.src_ip)); 1513 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1514 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1515 &ib_spec->ipv6.mask.dst_ip, 1516 sizeof(ib_spec->ipv6.mask.dst_ip)); 1517 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1518 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1519 &ib_spec->ipv6.val.dst_ip, 1520 sizeof(ib_spec->ipv6.val.dst_ip)); 1521 break; 1522 case IB_FLOW_SPEC_TCP: 1523 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1524 return -EINVAL; 1525 1526 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1527 0xff); 1528 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1529 IPPROTO_TCP); 1530 1531 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1532 ntohs(ib_spec->tcp_udp.mask.src_port)); 1533 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1534 ntohs(ib_spec->tcp_udp.val.src_port)); 1535 1536 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1537 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1538 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1539 ntohs(ib_spec->tcp_udp.val.dst_port)); 1540 break; 1541 case IB_FLOW_SPEC_UDP: 1542 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1543 return -EINVAL; 1544 1545 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1546 0xff); 1547 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1548 IPPROTO_UDP); 1549 1550 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1551 ntohs(ib_spec->tcp_udp.mask.src_port)); 1552 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1553 ntohs(ib_spec->tcp_udp.val.src_port)); 1554 1555 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1556 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1557 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1558 ntohs(ib_spec->tcp_udp.val.dst_port)); 1559 break; 1560 default: 1561 return -EINVAL; 1562 } 1563 1564 return 0; 1565 } 1566 1567 /* If a flow could catch both multicast and unicast packets, 1568 * it won't fall into the multicast flow steering table and this rule 1569 * could steal other multicast packets. 1570 */ 1571 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1572 { 1573 struct ib_flow_spec_eth *eth_spec; 1574 1575 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1576 ib_attr->size < sizeof(struct ib_flow_attr) + 1577 sizeof(struct ib_flow_spec_eth) || 1578 ib_attr->num_of_specs < 1) 1579 return false; 1580 1581 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1582 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1583 eth_spec->size != sizeof(*eth_spec)) 1584 return false; 1585 1586 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1587 is_multicast_ether_addr(eth_spec->val.dst_mac); 1588 } 1589 1590 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1591 { 1592 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1593 bool has_ipv4_spec = false; 1594 bool eth_type_ipv4 = true; 1595 unsigned int spec_index; 1596 1597 /* Validate that ethertype is correct */ 1598 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1599 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1600 ib_spec->eth.mask.ether_type) { 1601 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1602 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1603 eth_type_ipv4 = false; 1604 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1605 has_ipv4_spec = true; 1606 } 1607 ib_spec = (void *)ib_spec + ib_spec->size; 1608 } 1609 return !has_ipv4_spec || eth_type_ipv4; 1610 } 1611 1612 static void put_flow_table(struct mlx5_ib_dev *dev, 1613 struct mlx5_ib_flow_prio *prio, bool ft_added) 1614 { 1615 prio->refcount -= !!ft_added; 1616 if (!prio->refcount) { 1617 mlx5_destroy_flow_table(prio->flow_table); 1618 prio->flow_table = NULL; 1619 } 1620 } 1621 1622 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1623 { 1624 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1625 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1626 struct mlx5_ib_flow_handler, 1627 ibflow); 1628 struct mlx5_ib_flow_handler *iter, *tmp; 1629 1630 mutex_lock(&dev->flow_db.lock); 1631 1632 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1633 mlx5_del_flow_rule(iter->rule); 1634 list_del(&iter->list); 1635 kfree(iter); 1636 } 1637 1638 mlx5_del_flow_rule(handler->rule); 1639 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1640 mutex_unlock(&dev->flow_db.lock); 1641 1642 kfree(handler); 1643 1644 return 0; 1645 } 1646 1647 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1648 { 1649 priority *= 2; 1650 if (!dont_trap) 1651 priority++; 1652 return priority; 1653 } 1654 1655 #define MLX5_FS_MAX_TYPES 10 1656 #define MLX5_FS_MAX_ENTRIES 32000UL 1657 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1658 struct ib_flow_attr *flow_attr) 1659 { 1660 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1661 struct mlx5_flow_namespace *ns = NULL; 1662 struct mlx5_ib_flow_prio *prio; 1663 struct mlx5_flow_table *ft; 1664 int num_entries; 1665 int num_groups; 1666 int priority; 1667 int err = 0; 1668 1669 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1670 if (flow_is_multicast_only(flow_attr) && 1671 !dont_trap) 1672 priority = MLX5_IB_FLOW_MCAST_PRIO; 1673 else 1674 priority = ib_prio_to_core_prio(flow_attr->priority, 1675 dont_trap); 1676 ns = mlx5_get_flow_namespace(dev->mdev, 1677 MLX5_FLOW_NAMESPACE_BYPASS); 1678 num_entries = MLX5_FS_MAX_ENTRIES; 1679 num_groups = MLX5_FS_MAX_TYPES; 1680 prio = &dev->flow_db.prios[priority]; 1681 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1682 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1683 ns = mlx5_get_flow_namespace(dev->mdev, 1684 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1685 build_leftovers_ft_param(&priority, 1686 &num_entries, 1687 &num_groups); 1688 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1689 } 1690 1691 if (!ns) 1692 return ERR_PTR(-ENOTSUPP); 1693 1694 ft = prio->flow_table; 1695 if (!ft) { 1696 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1697 num_entries, 1698 num_groups, 1699 0); 1700 1701 if (!IS_ERR(ft)) { 1702 prio->refcount = 0; 1703 prio->flow_table = ft; 1704 } else { 1705 err = PTR_ERR(ft); 1706 } 1707 } 1708 1709 return err ? ERR_PTR(err) : prio; 1710 } 1711 1712 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1713 struct mlx5_ib_flow_prio *ft_prio, 1714 struct ib_flow_attr *flow_attr, 1715 struct mlx5_flow_destination *dst) 1716 { 1717 struct mlx5_flow_table *ft = ft_prio->flow_table; 1718 struct mlx5_ib_flow_handler *handler; 1719 struct mlx5_flow_spec *spec; 1720 void *ib_flow = flow_attr + 1; 1721 unsigned int spec_index; 1722 u32 action; 1723 int err = 0; 1724 1725 if (!is_valid_attr(flow_attr)) 1726 return ERR_PTR(-EINVAL); 1727 1728 spec = mlx5_vzalloc(sizeof(*spec)); 1729 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1730 if (!handler || !spec) { 1731 err = -ENOMEM; 1732 goto free; 1733 } 1734 1735 INIT_LIST_HEAD(&handler->list); 1736 1737 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1738 err = parse_flow_attr(spec->match_criteria, 1739 spec->match_value, ib_flow); 1740 if (err < 0) 1741 goto free; 1742 1743 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1744 } 1745 1746 /* Outer header support only */ 1747 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria)) 1748 << 0; 1749 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1750 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1751 handler->rule = mlx5_add_flow_rule(ft, spec, 1752 action, 1753 MLX5_FS_DEFAULT_FLOW_TAG, 1754 dst); 1755 1756 if (IS_ERR(handler->rule)) { 1757 err = PTR_ERR(handler->rule); 1758 goto free; 1759 } 1760 1761 handler->prio = ft_prio - dev->flow_db.prios; 1762 1763 ft_prio->flow_table = ft; 1764 free: 1765 if (err) 1766 kfree(handler); 1767 kvfree(spec); 1768 return err ? ERR_PTR(err) : handler; 1769 } 1770 1771 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 1772 struct mlx5_ib_flow_prio *ft_prio, 1773 struct ib_flow_attr *flow_attr, 1774 struct mlx5_flow_destination *dst) 1775 { 1776 struct mlx5_ib_flow_handler *handler_dst = NULL; 1777 struct mlx5_ib_flow_handler *handler = NULL; 1778 1779 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 1780 if (!IS_ERR(handler)) { 1781 handler_dst = create_flow_rule(dev, ft_prio, 1782 flow_attr, dst); 1783 if (IS_ERR(handler_dst)) { 1784 mlx5_del_flow_rule(handler->rule); 1785 kfree(handler); 1786 handler = handler_dst; 1787 } else { 1788 list_add(&handler_dst->list, &handler->list); 1789 } 1790 } 1791 1792 return handler; 1793 } 1794 enum { 1795 LEFTOVERS_MC, 1796 LEFTOVERS_UC, 1797 }; 1798 1799 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1800 struct mlx5_ib_flow_prio *ft_prio, 1801 struct ib_flow_attr *flow_attr, 1802 struct mlx5_flow_destination *dst) 1803 { 1804 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1805 struct mlx5_ib_flow_handler *handler = NULL; 1806 1807 static struct { 1808 struct ib_flow_attr flow_attr; 1809 struct ib_flow_spec_eth eth_flow; 1810 } leftovers_specs[] = { 1811 [LEFTOVERS_MC] = { 1812 .flow_attr = { 1813 .num_of_specs = 1, 1814 .size = sizeof(leftovers_specs[0]) 1815 }, 1816 .eth_flow = { 1817 .type = IB_FLOW_SPEC_ETH, 1818 .size = sizeof(struct ib_flow_spec_eth), 1819 .mask = {.dst_mac = {0x1} }, 1820 .val = {.dst_mac = {0x1} } 1821 } 1822 }, 1823 [LEFTOVERS_UC] = { 1824 .flow_attr = { 1825 .num_of_specs = 1, 1826 .size = sizeof(leftovers_specs[0]) 1827 }, 1828 .eth_flow = { 1829 .type = IB_FLOW_SPEC_ETH, 1830 .size = sizeof(struct ib_flow_spec_eth), 1831 .mask = {.dst_mac = {0x1} }, 1832 .val = {.dst_mac = {} } 1833 } 1834 } 1835 }; 1836 1837 handler = create_flow_rule(dev, ft_prio, 1838 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1839 dst); 1840 if (!IS_ERR(handler) && 1841 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1842 handler_ucast = create_flow_rule(dev, ft_prio, 1843 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1844 dst); 1845 if (IS_ERR(handler_ucast)) { 1846 kfree(handler); 1847 handler = handler_ucast; 1848 } else { 1849 list_add(&handler_ucast->list, &handler->list); 1850 } 1851 } 1852 1853 return handler; 1854 } 1855 1856 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1857 struct ib_flow_attr *flow_attr, 1858 int domain) 1859 { 1860 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1861 struct mlx5_ib_qp *mqp = to_mqp(qp); 1862 struct mlx5_ib_flow_handler *handler = NULL; 1863 struct mlx5_flow_destination *dst = NULL; 1864 struct mlx5_ib_flow_prio *ft_prio; 1865 int err; 1866 1867 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1868 return ERR_PTR(-ENOSPC); 1869 1870 if (domain != IB_FLOW_DOMAIN_USER || 1871 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1872 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 1873 return ERR_PTR(-EINVAL); 1874 1875 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1876 if (!dst) 1877 return ERR_PTR(-ENOMEM); 1878 1879 mutex_lock(&dev->flow_db.lock); 1880 1881 ft_prio = get_flow_table(dev, flow_attr); 1882 if (IS_ERR(ft_prio)) { 1883 err = PTR_ERR(ft_prio); 1884 goto unlock; 1885 } 1886 1887 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1888 if (mqp->flags & MLX5_IB_QP_RSS) 1889 dst->tir_num = mqp->rss_qp.tirn; 1890 else 1891 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 1892 1893 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1894 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 1895 handler = create_dont_trap_rule(dev, ft_prio, 1896 flow_attr, dst); 1897 } else { 1898 handler = create_flow_rule(dev, ft_prio, flow_attr, 1899 dst); 1900 } 1901 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1902 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1903 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1904 dst); 1905 } else { 1906 err = -EINVAL; 1907 goto destroy_ft; 1908 } 1909 1910 if (IS_ERR(handler)) { 1911 err = PTR_ERR(handler); 1912 handler = NULL; 1913 goto destroy_ft; 1914 } 1915 1916 ft_prio->refcount++; 1917 mutex_unlock(&dev->flow_db.lock); 1918 kfree(dst); 1919 1920 return &handler->ibflow; 1921 1922 destroy_ft: 1923 put_flow_table(dev, ft_prio, false); 1924 unlock: 1925 mutex_unlock(&dev->flow_db.lock); 1926 kfree(dst); 1927 kfree(handler); 1928 return ERR_PTR(err); 1929 } 1930 1931 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1932 { 1933 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1934 int err; 1935 1936 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1937 if (err) 1938 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1939 ibqp->qp_num, gid->raw); 1940 1941 return err; 1942 } 1943 1944 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1945 { 1946 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1947 int err; 1948 1949 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1950 if (err) 1951 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1952 ibqp->qp_num, gid->raw); 1953 1954 return err; 1955 } 1956 1957 static int init_node_data(struct mlx5_ib_dev *dev) 1958 { 1959 int err; 1960 1961 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1962 if (err) 1963 return err; 1964 1965 dev->mdev->rev_id = dev->mdev->pdev->revision; 1966 1967 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1968 } 1969 1970 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1971 char *buf) 1972 { 1973 struct mlx5_ib_dev *dev = 1974 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1975 1976 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1977 } 1978 1979 static ssize_t show_reg_pages(struct device *device, 1980 struct device_attribute *attr, char *buf) 1981 { 1982 struct mlx5_ib_dev *dev = 1983 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1984 1985 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1986 } 1987 1988 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1989 char *buf) 1990 { 1991 struct mlx5_ib_dev *dev = 1992 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1993 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1994 } 1995 1996 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1997 char *buf) 1998 { 1999 struct mlx5_ib_dev *dev = 2000 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2001 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2002 } 2003 2004 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2005 char *buf) 2006 { 2007 struct mlx5_ib_dev *dev = 2008 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2009 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2010 dev->mdev->board_id); 2011 } 2012 2013 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2014 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2015 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2016 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2017 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2018 2019 static struct device_attribute *mlx5_class_attributes[] = { 2020 &dev_attr_hw_rev, 2021 &dev_attr_hca_type, 2022 &dev_attr_board_id, 2023 &dev_attr_fw_pages, 2024 &dev_attr_reg_pages, 2025 }; 2026 2027 static void pkey_change_handler(struct work_struct *work) 2028 { 2029 struct mlx5_ib_port_resources *ports = 2030 container_of(work, struct mlx5_ib_port_resources, 2031 pkey_change_work); 2032 2033 mutex_lock(&ports->devr->mutex); 2034 mlx5_ib_gsi_pkey_change(ports->gsi); 2035 mutex_unlock(&ports->devr->mutex); 2036 } 2037 2038 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2039 { 2040 struct mlx5_ib_qp *mqp; 2041 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2042 struct mlx5_core_cq *mcq; 2043 struct list_head cq_armed_list; 2044 unsigned long flags_qp; 2045 unsigned long flags_cq; 2046 unsigned long flags; 2047 2048 INIT_LIST_HEAD(&cq_armed_list); 2049 2050 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2051 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2052 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2053 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2054 if (mqp->sq.tail != mqp->sq.head) { 2055 send_mcq = to_mcq(mqp->ibqp.send_cq); 2056 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2057 if (send_mcq->mcq.comp && 2058 mqp->ibqp.send_cq->comp_handler) { 2059 if (!send_mcq->mcq.reset_notify_added) { 2060 send_mcq->mcq.reset_notify_added = 1; 2061 list_add_tail(&send_mcq->mcq.reset_notify, 2062 &cq_armed_list); 2063 } 2064 } 2065 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2066 } 2067 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2068 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2069 /* no handling is needed for SRQ */ 2070 if (!mqp->ibqp.srq) { 2071 if (mqp->rq.tail != mqp->rq.head) { 2072 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2073 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2074 if (recv_mcq->mcq.comp && 2075 mqp->ibqp.recv_cq->comp_handler) { 2076 if (!recv_mcq->mcq.reset_notify_added) { 2077 recv_mcq->mcq.reset_notify_added = 1; 2078 list_add_tail(&recv_mcq->mcq.reset_notify, 2079 &cq_armed_list); 2080 } 2081 } 2082 spin_unlock_irqrestore(&recv_mcq->lock, 2083 flags_cq); 2084 } 2085 } 2086 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2087 } 2088 /*At that point all inflight post send were put to be executed as of we 2089 * lock/unlock above locks Now need to arm all involved CQs. 2090 */ 2091 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2092 mcq->comp(mcq); 2093 } 2094 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2095 } 2096 2097 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2098 enum mlx5_dev_event event, unsigned long param) 2099 { 2100 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2101 struct ib_event ibev; 2102 2103 u8 port = 0; 2104 2105 switch (event) { 2106 case MLX5_DEV_EVENT_SYS_ERROR: 2107 ibdev->ib_active = false; 2108 ibev.event = IB_EVENT_DEVICE_FATAL; 2109 mlx5_ib_handle_internal_error(ibdev); 2110 break; 2111 2112 case MLX5_DEV_EVENT_PORT_UP: 2113 ibev.event = IB_EVENT_PORT_ACTIVE; 2114 port = (u8)param; 2115 break; 2116 2117 case MLX5_DEV_EVENT_PORT_DOWN: 2118 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2119 ibev.event = IB_EVENT_PORT_ERR; 2120 port = (u8)param; 2121 break; 2122 2123 case MLX5_DEV_EVENT_LID_CHANGE: 2124 ibev.event = IB_EVENT_LID_CHANGE; 2125 port = (u8)param; 2126 break; 2127 2128 case MLX5_DEV_EVENT_PKEY_CHANGE: 2129 ibev.event = IB_EVENT_PKEY_CHANGE; 2130 port = (u8)param; 2131 2132 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2133 break; 2134 2135 case MLX5_DEV_EVENT_GUID_CHANGE: 2136 ibev.event = IB_EVENT_GID_CHANGE; 2137 port = (u8)param; 2138 break; 2139 2140 case MLX5_DEV_EVENT_CLIENT_REREG: 2141 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2142 port = (u8)param; 2143 break; 2144 } 2145 2146 ibev.device = &ibdev->ib_dev; 2147 ibev.element.port_num = port; 2148 2149 if (port < 1 || port > ibdev->num_ports) { 2150 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2151 return; 2152 } 2153 2154 if (ibdev->ib_active) 2155 ib_dispatch_event(&ibev); 2156 } 2157 2158 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2159 { 2160 int port; 2161 2162 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2163 mlx5_query_ext_port_caps(dev, port); 2164 } 2165 2166 static int get_port_caps(struct mlx5_ib_dev *dev) 2167 { 2168 struct ib_device_attr *dprops = NULL; 2169 struct ib_port_attr *pprops = NULL; 2170 int err = -ENOMEM; 2171 int port; 2172 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2173 2174 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2175 if (!pprops) 2176 goto out; 2177 2178 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2179 if (!dprops) 2180 goto out; 2181 2182 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2183 if (err) { 2184 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2185 goto out; 2186 } 2187 2188 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2189 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2190 if (err) { 2191 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2192 port, err); 2193 break; 2194 } 2195 dev->mdev->port_caps[port - 1].pkey_table_len = 2196 dprops->max_pkeys; 2197 dev->mdev->port_caps[port - 1].gid_table_len = 2198 pprops->gid_tbl_len; 2199 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2200 dprops->max_pkeys, pprops->gid_tbl_len); 2201 } 2202 2203 out: 2204 kfree(pprops); 2205 kfree(dprops); 2206 2207 return err; 2208 } 2209 2210 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2211 { 2212 int err; 2213 2214 err = mlx5_mr_cache_cleanup(dev); 2215 if (err) 2216 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2217 2218 mlx5_ib_destroy_qp(dev->umrc.qp); 2219 ib_free_cq(dev->umrc.cq); 2220 ib_dealloc_pd(dev->umrc.pd); 2221 } 2222 2223 enum { 2224 MAX_UMR_WR = 128, 2225 }; 2226 2227 static int create_umr_res(struct mlx5_ib_dev *dev) 2228 { 2229 struct ib_qp_init_attr *init_attr = NULL; 2230 struct ib_qp_attr *attr = NULL; 2231 struct ib_pd *pd; 2232 struct ib_cq *cq; 2233 struct ib_qp *qp; 2234 int ret; 2235 2236 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2237 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2238 if (!attr || !init_attr) { 2239 ret = -ENOMEM; 2240 goto error_0; 2241 } 2242 2243 pd = ib_alloc_pd(&dev->ib_dev); 2244 if (IS_ERR(pd)) { 2245 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2246 ret = PTR_ERR(pd); 2247 goto error_0; 2248 } 2249 2250 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2251 if (IS_ERR(cq)) { 2252 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2253 ret = PTR_ERR(cq); 2254 goto error_2; 2255 } 2256 2257 init_attr->send_cq = cq; 2258 init_attr->recv_cq = cq; 2259 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2260 init_attr->cap.max_send_wr = MAX_UMR_WR; 2261 init_attr->cap.max_send_sge = 1; 2262 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2263 init_attr->port_num = 1; 2264 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2265 if (IS_ERR(qp)) { 2266 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2267 ret = PTR_ERR(qp); 2268 goto error_3; 2269 } 2270 qp->device = &dev->ib_dev; 2271 qp->real_qp = qp; 2272 qp->uobject = NULL; 2273 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2274 2275 attr->qp_state = IB_QPS_INIT; 2276 attr->port_num = 1; 2277 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2278 IB_QP_PORT, NULL); 2279 if (ret) { 2280 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2281 goto error_4; 2282 } 2283 2284 memset(attr, 0, sizeof(*attr)); 2285 attr->qp_state = IB_QPS_RTR; 2286 attr->path_mtu = IB_MTU_256; 2287 2288 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2289 if (ret) { 2290 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2291 goto error_4; 2292 } 2293 2294 memset(attr, 0, sizeof(*attr)); 2295 attr->qp_state = IB_QPS_RTS; 2296 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2297 if (ret) { 2298 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2299 goto error_4; 2300 } 2301 2302 dev->umrc.qp = qp; 2303 dev->umrc.cq = cq; 2304 dev->umrc.pd = pd; 2305 2306 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2307 ret = mlx5_mr_cache_init(dev); 2308 if (ret) { 2309 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2310 goto error_4; 2311 } 2312 2313 kfree(attr); 2314 kfree(init_attr); 2315 2316 return 0; 2317 2318 error_4: 2319 mlx5_ib_destroy_qp(qp); 2320 2321 error_3: 2322 ib_free_cq(cq); 2323 2324 error_2: 2325 ib_dealloc_pd(pd); 2326 2327 error_0: 2328 kfree(attr); 2329 kfree(init_attr); 2330 return ret; 2331 } 2332 2333 static int create_dev_resources(struct mlx5_ib_resources *devr) 2334 { 2335 struct ib_srq_init_attr attr; 2336 struct mlx5_ib_dev *dev; 2337 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2338 int port; 2339 int ret = 0; 2340 2341 dev = container_of(devr, struct mlx5_ib_dev, devr); 2342 2343 mutex_init(&devr->mutex); 2344 2345 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2346 if (IS_ERR(devr->p0)) { 2347 ret = PTR_ERR(devr->p0); 2348 goto error0; 2349 } 2350 devr->p0->device = &dev->ib_dev; 2351 devr->p0->uobject = NULL; 2352 atomic_set(&devr->p0->usecnt, 0); 2353 2354 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2355 if (IS_ERR(devr->c0)) { 2356 ret = PTR_ERR(devr->c0); 2357 goto error1; 2358 } 2359 devr->c0->device = &dev->ib_dev; 2360 devr->c0->uobject = NULL; 2361 devr->c0->comp_handler = NULL; 2362 devr->c0->event_handler = NULL; 2363 devr->c0->cq_context = NULL; 2364 atomic_set(&devr->c0->usecnt, 0); 2365 2366 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2367 if (IS_ERR(devr->x0)) { 2368 ret = PTR_ERR(devr->x0); 2369 goto error2; 2370 } 2371 devr->x0->device = &dev->ib_dev; 2372 devr->x0->inode = NULL; 2373 atomic_set(&devr->x0->usecnt, 0); 2374 mutex_init(&devr->x0->tgt_qp_mutex); 2375 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2376 2377 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2378 if (IS_ERR(devr->x1)) { 2379 ret = PTR_ERR(devr->x1); 2380 goto error3; 2381 } 2382 devr->x1->device = &dev->ib_dev; 2383 devr->x1->inode = NULL; 2384 atomic_set(&devr->x1->usecnt, 0); 2385 mutex_init(&devr->x1->tgt_qp_mutex); 2386 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2387 2388 memset(&attr, 0, sizeof(attr)); 2389 attr.attr.max_sge = 1; 2390 attr.attr.max_wr = 1; 2391 attr.srq_type = IB_SRQT_XRC; 2392 attr.ext.xrc.cq = devr->c0; 2393 attr.ext.xrc.xrcd = devr->x0; 2394 2395 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2396 if (IS_ERR(devr->s0)) { 2397 ret = PTR_ERR(devr->s0); 2398 goto error4; 2399 } 2400 devr->s0->device = &dev->ib_dev; 2401 devr->s0->pd = devr->p0; 2402 devr->s0->uobject = NULL; 2403 devr->s0->event_handler = NULL; 2404 devr->s0->srq_context = NULL; 2405 devr->s0->srq_type = IB_SRQT_XRC; 2406 devr->s0->ext.xrc.xrcd = devr->x0; 2407 devr->s0->ext.xrc.cq = devr->c0; 2408 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2409 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2410 atomic_inc(&devr->p0->usecnt); 2411 atomic_set(&devr->s0->usecnt, 0); 2412 2413 memset(&attr, 0, sizeof(attr)); 2414 attr.attr.max_sge = 1; 2415 attr.attr.max_wr = 1; 2416 attr.srq_type = IB_SRQT_BASIC; 2417 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2418 if (IS_ERR(devr->s1)) { 2419 ret = PTR_ERR(devr->s1); 2420 goto error5; 2421 } 2422 devr->s1->device = &dev->ib_dev; 2423 devr->s1->pd = devr->p0; 2424 devr->s1->uobject = NULL; 2425 devr->s1->event_handler = NULL; 2426 devr->s1->srq_context = NULL; 2427 devr->s1->srq_type = IB_SRQT_BASIC; 2428 devr->s1->ext.xrc.cq = devr->c0; 2429 atomic_inc(&devr->p0->usecnt); 2430 atomic_set(&devr->s0->usecnt, 0); 2431 2432 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2433 INIT_WORK(&devr->ports[port].pkey_change_work, 2434 pkey_change_handler); 2435 devr->ports[port].devr = devr; 2436 } 2437 2438 return 0; 2439 2440 error5: 2441 mlx5_ib_destroy_srq(devr->s0); 2442 error4: 2443 mlx5_ib_dealloc_xrcd(devr->x1); 2444 error3: 2445 mlx5_ib_dealloc_xrcd(devr->x0); 2446 error2: 2447 mlx5_ib_destroy_cq(devr->c0); 2448 error1: 2449 mlx5_ib_dealloc_pd(devr->p0); 2450 error0: 2451 return ret; 2452 } 2453 2454 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2455 { 2456 struct mlx5_ib_dev *dev = 2457 container_of(devr, struct mlx5_ib_dev, devr); 2458 int port; 2459 2460 mlx5_ib_destroy_srq(devr->s1); 2461 mlx5_ib_destroy_srq(devr->s0); 2462 mlx5_ib_dealloc_xrcd(devr->x0); 2463 mlx5_ib_dealloc_xrcd(devr->x1); 2464 mlx5_ib_destroy_cq(devr->c0); 2465 mlx5_ib_dealloc_pd(devr->p0); 2466 2467 /* Make sure no change P_Key work items are still executing */ 2468 for (port = 0; port < dev->num_ports; ++port) 2469 cancel_work_sync(&devr->ports[port].pkey_change_work); 2470 } 2471 2472 static u32 get_core_cap_flags(struct ib_device *ibdev) 2473 { 2474 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2475 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2476 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2477 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2478 u32 ret = 0; 2479 2480 if (ll == IB_LINK_LAYER_INFINIBAND) 2481 return RDMA_CORE_PORT_IBA_IB; 2482 2483 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2484 return 0; 2485 2486 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2487 return 0; 2488 2489 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2490 ret |= RDMA_CORE_PORT_IBA_ROCE; 2491 2492 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2493 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2494 2495 return ret; 2496 } 2497 2498 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2499 struct ib_port_immutable *immutable) 2500 { 2501 struct ib_port_attr attr; 2502 int err; 2503 2504 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2505 if (err) 2506 return err; 2507 2508 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2509 immutable->gid_tbl_len = attr.gid_tbl_len; 2510 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2511 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2512 2513 return 0; 2514 } 2515 2516 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2517 size_t str_len) 2518 { 2519 struct mlx5_ib_dev *dev = 2520 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2521 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2522 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2523 } 2524 2525 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2526 { 2527 int err; 2528 2529 dev->roce.nb.notifier_call = mlx5_netdev_event; 2530 err = register_netdevice_notifier(&dev->roce.nb); 2531 if (err) 2532 return err; 2533 2534 err = mlx5_nic_vport_enable_roce(dev->mdev); 2535 if (err) 2536 goto err_unregister_netdevice_notifier; 2537 2538 return 0; 2539 2540 err_unregister_netdevice_notifier: 2541 unregister_netdevice_notifier(&dev->roce.nb); 2542 return err; 2543 } 2544 2545 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2546 { 2547 mlx5_nic_vport_disable_roce(dev->mdev); 2548 unregister_netdevice_notifier(&dev->roce.nb); 2549 } 2550 2551 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2552 { 2553 unsigned int i; 2554 2555 for (i = 0; i < dev->num_ports; i++) 2556 mlx5_core_dealloc_q_counter(dev->mdev, 2557 dev->port[i].q_cnt_id); 2558 } 2559 2560 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2561 { 2562 int i; 2563 int ret; 2564 2565 for (i = 0; i < dev->num_ports; i++) { 2566 ret = mlx5_core_alloc_q_counter(dev->mdev, 2567 &dev->port[i].q_cnt_id); 2568 if (ret) { 2569 mlx5_ib_warn(dev, 2570 "couldn't allocate queue counter for port %d, err %d\n", 2571 i + 1, ret); 2572 goto dealloc_counters; 2573 } 2574 } 2575 2576 return 0; 2577 2578 dealloc_counters: 2579 while (--i >= 0) 2580 mlx5_core_dealloc_q_counter(dev->mdev, 2581 dev->port[i].q_cnt_id); 2582 2583 return ret; 2584 } 2585 2586 static const char * const names[] = { 2587 "rx_write_requests", 2588 "rx_read_requests", 2589 "rx_atomic_requests", 2590 "out_of_buffer", 2591 "out_of_sequence", 2592 "duplicate_request", 2593 "rnr_nak_retry_err", 2594 "packet_seq_err", 2595 "implied_nak_seq_err", 2596 "local_ack_timeout_err", 2597 }; 2598 2599 static const size_t stats_offsets[] = { 2600 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 2601 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 2602 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 2603 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 2604 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 2605 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 2606 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 2607 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 2608 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 2609 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 2610 }; 2611 2612 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 2613 u8 port_num) 2614 { 2615 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 2616 2617 /* We support only per port stats */ 2618 if (port_num == 0) 2619 return NULL; 2620 2621 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 2622 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2623 } 2624 2625 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 2626 struct rdma_hw_stats *stats, 2627 u8 port, int index) 2628 { 2629 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2630 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 2631 void *out; 2632 __be32 val; 2633 int ret; 2634 int i; 2635 2636 if (!port || !stats) 2637 return -ENOSYS; 2638 2639 out = mlx5_vzalloc(outlen); 2640 if (!out) 2641 return -ENOMEM; 2642 2643 ret = mlx5_core_query_q_counter(dev->mdev, 2644 dev->port[port - 1].q_cnt_id, 0, 2645 out, outlen); 2646 if (ret) 2647 goto free; 2648 2649 for (i = 0; i < ARRAY_SIZE(names); i++) { 2650 val = *(__be32 *)(out + stats_offsets[i]); 2651 stats->value[i] = (u64)be32_to_cpu(val); 2652 } 2653 free: 2654 kvfree(out); 2655 return ARRAY_SIZE(names); 2656 } 2657 2658 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2659 { 2660 struct mlx5_ib_dev *dev; 2661 enum rdma_link_layer ll; 2662 int port_type_cap; 2663 int err; 2664 int i; 2665 2666 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2667 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2668 2669 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2670 return NULL; 2671 2672 printk_once(KERN_INFO "%s", mlx5_version); 2673 2674 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2675 if (!dev) 2676 return NULL; 2677 2678 dev->mdev = mdev; 2679 2680 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 2681 GFP_KERNEL); 2682 if (!dev->port) 2683 goto err_dealloc; 2684 2685 rwlock_init(&dev->roce.netdev_lock); 2686 err = get_port_caps(dev); 2687 if (err) 2688 goto err_free_port; 2689 2690 if (mlx5_use_mad_ifc(dev)) 2691 get_ext_port_caps(dev); 2692 2693 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2694 2695 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2696 dev->ib_dev.owner = THIS_MODULE; 2697 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2698 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2699 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2700 dev->ib_dev.phys_port_cnt = dev->num_ports; 2701 dev->ib_dev.num_comp_vectors = 2702 dev->mdev->priv.eq_table.num_comp_vectors; 2703 dev->ib_dev.dma_device = &mdev->pdev->dev; 2704 2705 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2706 dev->ib_dev.uverbs_cmd_mask = 2707 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2708 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2709 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2710 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2711 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2712 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2713 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2714 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2715 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2716 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2717 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2718 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2719 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2720 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2721 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2722 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2723 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2724 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2725 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2726 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2727 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2728 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2729 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2730 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2731 dev->ib_dev.uverbs_ex_cmd_mask = 2732 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2733 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2734 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2735 2736 dev->ib_dev.query_device = mlx5_ib_query_device; 2737 dev->ib_dev.query_port = mlx5_ib_query_port; 2738 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2739 if (ll == IB_LINK_LAYER_ETHERNET) 2740 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2741 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2742 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2743 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2744 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2745 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2746 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2747 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2748 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2749 dev->ib_dev.mmap = mlx5_ib_mmap; 2750 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2751 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2752 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2753 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2754 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2755 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2756 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2757 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2758 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2759 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2760 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2761 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2762 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2763 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2764 dev->ib_dev.post_send = mlx5_ib_post_send; 2765 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2766 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2767 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2768 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2769 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2770 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2771 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2772 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2773 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2774 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 2775 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2776 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2777 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2778 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2779 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2780 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2781 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2782 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2783 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 2784 if (mlx5_core_is_pf(mdev)) { 2785 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 2786 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 2787 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 2788 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 2789 } 2790 2791 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 2792 2793 mlx5_ib_internal_fill_odp_caps(dev); 2794 2795 if (MLX5_CAP_GEN(mdev, imaicl)) { 2796 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 2797 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 2798 dev->ib_dev.uverbs_cmd_mask |= 2799 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2800 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2801 } 2802 2803 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 2804 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 2805 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 2806 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 2807 } 2808 2809 if (MLX5_CAP_GEN(mdev, xrc)) { 2810 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2811 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2812 dev->ib_dev.uverbs_cmd_mask |= 2813 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2814 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2815 } 2816 2817 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2818 IB_LINK_LAYER_ETHERNET) { 2819 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2820 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2821 dev->ib_dev.create_wq = mlx5_ib_create_wq; 2822 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 2823 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 2824 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 2825 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 2826 dev->ib_dev.uverbs_ex_cmd_mask |= 2827 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2828 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 2829 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2830 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2831 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2832 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2833 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2834 } 2835 err = init_node_data(dev); 2836 if (err) 2837 goto err_dealloc; 2838 2839 mutex_init(&dev->flow_db.lock); 2840 mutex_init(&dev->cap_mask_mutex); 2841 INIT_LIST_HEAD(&dev->qp_list); 2842 spin_lock_init(&dev->reset_flow_resource_lock); 2843 2844 if (ll == IB_LINK_LAYER_ETHERNET) { 2845 err = mlx5_enable_roce(dev); 2846 if (err) 2847 goto err_dealloc; 2848 } 2849 2850 err = create_dev_resources(&dev->devr); 2851 if (err) 2852 goto err_disable_roce; 2853 2854 err = mlx5_ib_odp_init_one(dev); 2855 if (err) 2856 goto err_rsrc; 2857 2858 err = mlx5_ib_alloc_q_counters(dev); 2859 if (err) 2860 goto err_odp; 2861 2862 err = ib_register_device(&dev->ib_dev, NULL); 2863 if (err) 2864 goto err_q_cnt; 2865 2866 err = create_umr_res(dev); 2867 if (err) 2868 goto err_dev; 2869 2870 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2871 err = device_create_file(&dev->ib_dev.dev, 2872 mlx5_class_attributes[i]); 2873 if (err) 2874 goto err_umrc; 2875 } 2876 2877 dev->ib_active = true; 2878 2879 return dev; 2880 2881 err_umrc: 2882 destroy_umrc_res(dev); 2883 2884 err_dev: 2885 ib_unregister_device(&dev->ib_dev); 2886 2887 err_q_cnt: 2888 mlx5_ib_dealloc_q_counters(dev); 2889 2890 err_odp: 2891 mlx5_ib_odp_remove_one(dev); 2892 2893 err_rsrc: 2894 destroy_dev_resources(&dev->devr); 2895 2896 err_disable_roce: 2897 if (ll == IB_LINK_LAYER_ETHERNET) 2898 mlx5_disable_roce(dev); 2899 2900 err_free_port: 2901 kfree(dev->port); 2902 2903 err_dealloc: 2904 ib_dealloc_device((struct ib_device *)dev); 2905 2906 return NULL; 2907 } 2908 2909 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2910 { 2911 struct mlx5_ib_dev *dev = context; 2912 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2913 2914 ib_unregister_device(&dev->ib_dev); 2915 mlx5_ib_dealloc_q_counters(dev); 2916 destroy_umrc_res(dev); 2917 mlx5_ib_odp_remove_one(dev); 2918 destroy_dev_resources(&dev->devr); 2919 if (ll == IB_LINK_LAYER_ETHERNET) 2920 mlx5_disable_roce(dev); 2921 kfree(dev->port); 2922 ib_dealloc_device(&dev->ib_dev); 2923 } 2924 2925 static struct mlx5_interface mlx5_ib_interface = { 2926 .add = mlx5_ib_add, 2927 .remove = mlx5_ib_remove, 2928 .event = mlx5_ib_event, 2929 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2930 }; 2931 2932 static int __init mlx5_ib_init(void) 2933 { 2934 int err; 2935 2936 if (deprecated_prof_sel != 2) 2937 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2938 2939 err = mlx5_ib_odp_init(); 2940 if (err) 2941 return err; 2942 2943 err = mlx5_register_interface(&mlx5_ib_interface); 2944 if (err) 2945 goto clean_odp; 2946 2947 return err; 2948 2949 clean_odp: 2950 mlx5_ib_odp_cleanup(); 2951 return err; 2952 } 2953 2954 static void __exit mlx5_ib_cleanup(void) 2955 { 2956 mlx5_unregister_interface(&mlx5_ib_interface); 2957 mlx5_ib_odp_cleanup(); 2958 } 2959 2960 module_init(mlx5_ib_init); 2961 module_exit(mlx5_ib_cleanup); 2962