1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/mlx5/driver.h> 28 #include <linux/list.h> 29 #include <rdma/ib_smi.h> 30 #include <rdma/ib_umem_odp.h> 31 #include <rdma/lag.h> 32 #include <linux/in.h> 33 #include <linux/etherdevice.h> 34 #include "mlx5_ib.h" 35 #include "ib_rep.h" 36 #include "cmd.h" 37 #include "devx.h" 38 #include "dm.h" 39 #include "fs.h" 40 #include "srq.h" 41 #include "qp.h" 42 #include "wr.h" 43 #include "restrack.h" 44 #include "counters.h" 45 #include "umr.h" 46 #include <rdma/uverbs_std_types.h> 47 #include <rdma/uverbs_ioctl.h> 48 #include <rdma/mlx5_user_ioctl_verbs.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 #include <rdma/ib_ucaps.h> 51 #include "macsec.h" 52 #include "data_direct.h" 53 54 #define UVERBS_MODULE_NAME mlx5_ib 55 #include <rdma/uverbs_named_ioctl.h> 56 57 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 58 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 61 struct mlx5_ib_event_work { 62 struct work_struct work; 63 union { 64 struct mlx5_ib_dev *dev; 65 struct mlx5_ib_multiport_info *mpi; 66 }; 67 bool is_slave; 68 unsigned int event; 69 void *param; 70 }; 71 72 enum { 73 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 74 }; 75 76 static struct workqueue_struct *mlx5_ib_event_wq; 77 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 78 static LIST_HEAD(mlx5_ib_dev_list); 79 /* 80 * This mutex should be held when accessing either of the above lists 81 */ 82 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 83 84 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 85 { 86 struct mlx5_ib_dev *dev; 87 88 mutex_lock(&mlx5_ib_multiport_mutex); 89 dev = mpi->ibdev; 90 mutex_unlock(&mlx5_ib_multiport_mutex); 91 return dev; 92 } 93 94 static enum rdma_link_layer 95 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 96 { 97 switch (port_type_cap) { 98 case MLX5_CAP_PORT_TYPE_IB: 99 return IB_LINK_LAYER_INFINIBAND; 100 case MLX5_CAP_PORT_TYPE_ETH: 101 return IB_LINK_LAYER_ETHERNET; 102 default: 103 return IB_LINK_LAYER_UNSPECIFIED; 104 } 105 } 106 107 static enum rdma_link_layer 108 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 109 { 110 struct mlx5_ib_dev *dev = to_mdev(device); 111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 112 113 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 114 } 115 116 static int get_port_state(struct ib_device *ibdev, 117 u32 port_num, 118 enum ib_port_state *state) 119 { 120 struct ib_port_attr attr; 121 int ret; 122 123 memset(&attr, 0, sizeof(attr)); 124 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 125 if (!ret) 126 *state = attr.state; 127 return ret; 128 } 129 130 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 131 struct net_device *ndev, 132 struct net_device *upper, 133 u32 *port_num) 134 { 135 struct net_device *rep_ndev; 136 struct mlx5_ib_port *port; 137 int i; 138 139 for (i = 0; i < dev->num_ports; i++) { 140 port = &dev->port[i]; 141 if (!port->rep) 142 continue; 143 144 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 145 *port_num = i + 1; 146 return &port->roce; 147 } 148 149 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 150 continue; 151 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 152 if (rep_ndev && rep_ndev == ndev) { 153 dev_put(rep_ndev); 154 *port_num = i + 1; 155 return &port->roce; 156 } 157 158 dev_put(rep_ndev); 159 } 160 161 return NULL; 162 } 163 164 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 165 struct net_device *ndev, 166 struct net_device *upper, 167 struct net_device *ib_ndev) 168 { 169 if (!dev->ib_active) 170 return false; 171 172 /* Event is about our upper device */ 173 if (upper == ndev) 174 return true; 175 176 /* RDMA device is not in lag and not in switchdev */ 177 if (!dev->is_rep && !upper && ndev == ib_ndev) 178 return true; 179 180 /* RDMA devie is in switchdev */ 181 if (dev->is_rep && ndev == ib_ndev) 182 return true; 183 184 return false; 185 } 186 187 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 188 { 189 struct mlx5_ib_port *port; 190 int i; 191 192 for (i = 0; i < ibdev->num_ports; i++) { 193 port = &ibdev->port[i]; 194 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 195 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 196 } 197 } 198 199 return NULL; 200 } 201 202 static int mlx5_netdev_event(struct notifier_block *this, 203 unsigned long event, void *ptr) 204 { 205 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 206 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 207 u32 port_num = roce->native_port_num; 208 struct net_device *ib_ndev = NULL; 209 struct mlx5_core_dev *mdev; 210 struct mlx5_ib_dev *ibdev; 211 212 ibdev = roce->dev; 213 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 214 if (!mdev) 215 return NOTIFY_DONE; 216 217 switch (event) { 218 case NETDEV_REGISTER: 219 /* Should already be registered during the load */ 220 if (ibdev->is_rep) 221 break; 222 223 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 224 /* Exit if already registered */ 225 if (ib_ndev) 226 goto put_ndev; 227 228 if (ndev->dev.parent == mdev->device) 229 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 230 break; 231 232 case NETDEV_UNREGISTER: 233 /* In case of reps, ib device goes away before the netdevs */ 234 if (ibdev->is_rep) 235 break; 236 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 237 if (ib_ndev == ndev) 238 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 239 goto put_ndev; 240 241 case NETDEV_CHANGE: 242 case NETDEV_UP: 243 case NETDEV_DOWN: { 244 struct net_device *upper = NULL; 245 246 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 247 !mlx5_core_mp_enabled(mdev)) 248 return NOTIFY_DONE; 249 250 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 251 struct net_device *lag_ndev; 252 253 if(mlx5_lag_is_roce(mdev)) 254 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 255 else /* sriov lag */ 256 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 257 258 if (lag_ndev) { 259 upper = netdev_master_upper_dev_get(lag_ndev); 260 dev_put(lag_ndev); 261 } else { 262 goto done; 263 } 264 } 265 266 if (ibdev->is_rep) 267 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 268 if (!roce) 269 return NOTIFY_DONE; 270 271 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 272 273 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 274 struct ib_event ibev = { }; 275 enum ib_port_state port_state; 276 277 if (get_port_state(&ibdev->ib_dev, port_num, 278 &port_state)) 279 goto put_ndev; 280 281 if (roce->last_port_state == port_state) 282 goto put_ndev; 283 284 roce->last_port_state = port_state; 285 ibev.device = &ibdev->ib_dev; 286 if (port_state == IB_PORT_DOWN) 287 ibev.event = IB_EVENT_PORT_ERR; 288 else if (port_state == IB_PORT_ACTIVE) 289 ibev.event = IB_EVENT_PORT_ACTIVE; 290 else 291 goto put_ndev; 292 293 ibev.element.port_num = port_num; 294 ib_dispatch_event(&ibev); 295 } 296 break; 297 } 298 299 default: 300 break; 301 } 302 put_ndev: 303 dev_put(ib_ndev); 304 done: 305 mlx5_ib_put_native_port_mdev(ibdev, port_num); 306 return NOTIFY_DONE; 307 } 308 309 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 310 u32 ib_port_num, 311 u32 *native_port_num) 312 { 313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 314 ib_port_num); 315 struct mlx5_core_dev *mdev = NULL; 316 struct mlx5_ib_multiport_info *mpi; 317 struct mlx5_ib_port *port; 318 319 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 320 if (native_port_num) 321 *native_port_num = smi_to_native_portnum(ibdev, 322 ib_port_num); 323 return ibdev->mdev; 324 325 } 326 327 if (!mlx5_core_mp_enabled(ibdev->mdev) || 328 ll != IB_LINK_LAYER_ETHERNET) { 329 if (native_port_num) 330 *native_port_num = ib_port_num; 331 return ibdev->mdev; 332 } 333 334 if (native_port_num) 335 *native_port_num = 1; 336 337 port = &ibdev->port[ib_port_num - 1]; 338 spin_lock(&port->mp.mpi_lock); 339 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 340 if (mpi && !mpi->unaffiliate) { 341 mdev = mpi->mdev; 342 /* If it's the master no need to refcount, it'll exist 343 * as long as the ib_dev exists. 344 */ 345 if (!mpi->is_master) 346 mpi->mdev_refcnt++; 347 } 348 spin_unlock(&port->mp.mpi_lock); 349 350 return mdev; 351 } 352 353 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 354 { 355 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 356 port_num); 357 struct mlx5_ib_multiport_info *mpi; 358 struct mlx5_ib_port *port; 359 360 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 361 return; 362 363 port = &ibdev->port[port_num - 1]; 364 365 spin_lock(&port->mp.mpi_lock); 366 mpi = ibdev->port[port_num - 1].mp.mpi; 367 if (mpi->is_master) 368 goto out; 369 370 mpi->mdev_refcnt--; 371 if (mpi->unaffiliate) 372 complete(&mpi->unref_comp); 373 out: 374 spin_unlock(&port->mp.mpi_lock); 375 } 376 377 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 378 u16 *active_speed, u8 *active_width) 379 { 380 switch (eth_proto_oper) { 381 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 382 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 383 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 385 *active_width = IB_WIDTH_1X; 386 *active_speed = IB_SPEED_SDR; 387 break; 388 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 389 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 395 *active_width = IB_WIDTH_1X; 396 *active_speed = IB_SPEED_QDR; 397 break; 398 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 399 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 401 *active_width = IB_WIDTH_1X; 402 *active_speed = IB_SPEED_EDR; 403 break; 404 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 405 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 408 *active_width = IB_WIDTH_4X; 409 *active_speed = IB_SPEED_QDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 412 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_HDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 418 *active_width = IB_WIDTH_4X; 419 *active_speed = IB_SPEED_FDR; 420 break; 421 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 422 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 425 *active_width = IB_WIDTH_4X; 426 *active_speed = IB_SPEED_EDR; 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 return 0; 433 } 434 435 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 436 u8 *active_width) 437 { 438 switch (eth_proto_oper) { 439 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 440 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 441 *active_width = IB_WIDTH_1X; 442 *active_speed = IB_SPEED_SDR; 443 break; 444 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 445 *active_width = IB_WIDTH_1X; 446 *active_speed = IB_SPEED_DDR; 447 break; 448 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 449 *active_width = IB_WIDTH_1X; 450 *active_speed = IB_SPEED_QDR; 451 break; 452 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 453 *active_width = IB_WIDTH_4X; 454 *active_speed = IB_SPEED_QDR; 455 break; 456 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 457 *active_width = IB_WIDTH_1X; 458 *active_speed = IB_SPEED_EDR; 459 break; 460 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 461 *active_width = IB_WIDTH_2X; 462 *active_speed = IB_SPEED_EDR; 463 break; 464 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 465 *active_width = IB_WIDTH_1X; 466 *active_speed = IB_SPEED_HDR; 467 break; 468 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 469 *active_width = IB_WIDTH_4X; 470 *active_speed = IB_SPEED_EDR; 471 break; 472 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 473 *active_width = IB_WIDTH_2X; 474 *active_speed = IB_SPEED_HDR; 475 break; 476 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 477 *active_width = IB_WIDTH_1X; 478 *active_speed = IB_SPEED_NDR; 479 break; 480 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 481 *active_width = IB_WIDTH_4X; 482 *active_speed = IB_SPEED_HDR; 483 break; 484 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 485 *active_width = IB_WIDTH_2X; 486 *active_speed = IB_SPEED_NDR; 487 break; 488 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 489 *active_width = IB_WIDTH_1X; 490 *active_speed = IB_SPEED_XDR; 491 break; 492 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 493 *active_width = IB_WIDTH_8X; 494 *active_speed = IB_SPEED_HDR; 495 break; 496 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 497 *active_width = IB_WIDTH_4X; 498 *active_speed = IB_SPEED_NDR; 499 break; 500 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 501 *active_width = IB_WIDTH_2X; 502 *active_speed = IB_SPEED_XDR; 503 break; 504 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 505 *active_width = IB_WIDTH_8X; 506 *active_speed = IB_SPEED_NDR; 507 break; 508 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 509 *active_width = IB_WIDTH_4X; 510 *active_speed = IB_SPEED_XDR; 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 return 0; 517 } 518 519 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 520 u8 *active_width, bool ext) 521 { 522 return ext ? 523 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 524 active_width) : 525 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 526 active_width); 527 } 528 529 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 530 struct ib_port_attr *props) 531 { 532 struct mlx5_ib_dev *dev = to_mdev(device); 533 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 534 struct mlx5_core_dev *mdev; 535 struct net_device *ndev, *upper; 536 enum ib_mtu ndev_ib_mtu; 537 bool put_mdev = true; 538 u32 eth_prot_oper; 539 u32 mdev_port_num; 540 bool ext; 541 int err; 542 543 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 544 if (!mdev) { 545 /* This means the port isn't affiliated yet. Get the 546 * info for the master port instead. 547 */ 548 put_mdev = false; 549 mdev = dev->mdev; 550 mdev_port_num = 1; 551 port_num = 1; 552 } 553 554 /* Possible bad flows are checked before filling out props so in case 555 * of an error it will still be zeroed out. 556 * Use native port in case of reps 557 */ 558 if (dev->is_rep) 559 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 560 1, 0); 561 else 562 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 563 mdev_port_num, 0); 564 if (err) 565 goto out; 566 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 567 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 568 569 props->active_width = IB_WIDTH_4X; 570 props->active_speed = IB_SPEED_QDR; 571 572 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 573 &props->active_width, ext); 574 575 if (!dev->is_rep && dev->mdev->roce.roce_en) { 576 u16 qkey_viol_cntr; 577 578 props->port_cap_flags |= IB_PORT_CM_SUP; 579 props->ip_gids = true; 580 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 581 roce_address_table_size); 582 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 583 props->qkey_viol_cntr = qkey_viol_cntr; 584 } 585 props->max_mtu = IB_MTU_4096; 586 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 587 props->pkey_tbl_len = 1; 588 props->state = IB_PORT_DOWN; 589 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 590 591 /* If this is a stub query for an unaffiliated port stop here */ 592 if (!put_mdev) 593 goto out; 594 595 ndev = ib_device_get_netdev(device, port_num); 596 if (!ndev) 597 goto out; 598 599 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 600 rcu_read_lock(); 601 upper = netdev_master_upper_dev_get_rcu(ndev); 602 if (upper) { 603 dev_put(ndev); 604 ndev = upper; 605 dev_hold(ndev); 606 } 607 rcu_read_unlock(); 608 } 609 610 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 611 props->state = IB_PORT_ACTIVE; 612 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 613 } 614 615 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 616 617 dev_put(ndev); 618 619 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 620 out: 621 if (put_mdev) 622 mlx5_ib_put_native_port_mdev(dev, port_num); 623 return err; 624 } 625 626 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 627 unsigned int index, const union ib_gid *gid, 628 const struct ib_gid_attr *attr) 629 { 630 enum ib_gid_type gid_type; 631 u16 vlan_id = 0xffff; 632 u8 roce_version = 0; 633 u8 roce_l3_type = 0; 634 u8 mac[ETH_ALEN]; 635 int ret; 636 637 gid_type = attr->gid_type; 638 if (gid) { 639 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 640 if (ret) 641 return ret; 642 } 643 644 switch (gid_type) { 645 case IB_GID_TYPE_ROCE: 646 roce_version = MLX5_ROCE_VERSION_1; 647 break; 648 case IB_GID_TYPE_ROCE_UDP_ENCAP: 649 roce_version = MLX5_ROCE_VERSION_2; 650 if (gid && ipv6_addr_v4mapped((void *)gid)) 651 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 652 else 653 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 654 break; 655 656 default: 657 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 658 } 659 660 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 661 roce_l3_type, gid->raw, mac, 662 vlan_id < VLAN_CFI_MASK, vlan_id, 663 port_num); 664 } 665 666 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 667 __always_unused void **context) 668 { 669 int ret; 670 671 ret = mlx5r_add_gid_macsec_operations(attr); 672 if (ret) 673 return ret; 674 675 return set_roce_addr(to_mdev(attr->device), attr->port_num, 676 attr->index, &attr->gid, attr); 677 } 678 679 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 680 __always_unused void **context) 681 { 682 int ret; 683 684 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 685 attr->index, NULL, attr); 686 if (ret) 687 return ret; 688 689 mlx5r_del_gid_macsec_operations(attr); 690 return 0; 691 } 692 693 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 694 const struct ib_gid_attr *attr) 695 { 696 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 697 return 0; 698 699 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 700 } 701 702 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 703 { 704 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 705 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 706 return 0; 707 } 708 709 enum { 710 MLX5_VPORT_ACCESS_METHOD_MAD, 711 MLX5_VPORT_ACCESS_METHOD_HCA, 712 MLX5_VPORT_ACCESS_METHOD_NIC, 713 }; 714 715 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 716 { 717 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 718 return MLX5_VPORT_ACCESS_METHOD_MAD; 719 720 if (mlx5_ib_port_link_layer(ibdev, 1) == 721 IB_LINK_LAYER_ETHERNET) 722 return MLX5_VPORT_ACCESS_METHOD_NIC; 723 724 return MLX5_VPORT_ACCESS_METHOD_HCA; 725 } 726 727 static void get_atomic_caps(struct mlx5_ib_dev *dev, 728 u8 atomic_size_qp, 729 struct ib_device_attr *props) 730 { 731 u8 tmp; 732 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 733 u8 atomic_req_8B_endianness_mode = 734 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 735 736 /* Check if HW supports 8 bytes standard atomic operations and capable 737 * of host endianness respond 738 */ 739 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 740 if (((atomic_operations & tmp) == tmp) && 741 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 742 (atomic_req_8B_endianness_mode)) { 743 props->atomic_cap = IB_ATOMIC_HCA; 744 } else { 745 props->atomic_cap = IB_ATOMIC_NONE; 746 } 747 } 748 749 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 750 struct ib_device_attr *props) 751 { 752 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 753 754 get_atomic_caps(dev, atomic_size_qp, props); 755 } 756 757 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 758 __be64 *sys_image_guid) 759 { 760 struct mlx5_ib_dev *dev = to_mdev(ibdev); 761 struct mlx5_core_dev *mdev = dev->mdev; 762 u64 tmp; 763 int err; 764 765 switch (mlx5_get_vport_access_method(ibdev)) { 766 case MLX5_VPORT_ACCESS_METHOD_MAD: 767 return mlx5_query_mad_ifc_system_image_guid(ibdev, 768 sys_image_guid); 769 770 case MLX5_VPORT_ACCESS_METHOD_HCA: 771 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 772 break; 773 774 case MLX5_VPORT_ACCESS_METHOD_NIC: 775 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 776 break; 777 778 default: 779 return -EINVAL; 780 } 781 782 if (!err) 783 *sys_image_guid = cpu_to_be64(tmp); 784 785 return err; 786 787 } 788 789 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 790 u16 *max_pkeys) 791 { 792 struct mlx5_ib_dev *dev = to_mdev(ibdev); 793 struct mlx5_core_dev *mdev = dev->mdev; 794 795 switch (mlx5_get_vport_access_method(ibdev)) { 796 case MLX5_VPORT_ACCESS_METHOD_MAD: 797 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 798 799 case MLX5_VPORT_ACCESS_METHOD_HCA: 800 case MLX5_VPORT_ACCESS_METHOD_NIC: 801 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 802 pkey_table_size)); 803 return 0; 804 805 default: 806 return -EINVAL; 807 } 808 } 809 810 static int mlx5_query_vendor_id(struct ib_device *ibdev, 811 u32 *vendor_id) 812 { 813 struct mlx5_ib_dev *dev = to_mdev(ibdev); 814 815 switch (mlx5_get_vport_access_method(ibdev)) { 816 case MLX5_VPORT_ACCESS_METHOD_MAD: 817 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 818 819 case MLX5_VPORT_ACCESS_METHOD_HCA: 820 case MLX5_VPORT_ACCESS_METHOD_NIC: 821 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 822 823 default: 824 return -EINVAL; 825 } 826 } 827 828 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 829 __be64 *node_guid) 830 { 831 u64 tmp; 832 int err; 833 834 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 835 case MLX5_VPORT_ACCESS_METHOD_MAD: 836 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 837 838 case MLX5_VPORT_ACCESS_METHOD_HCA: 839 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 840 break; 841 842 case MLX5_VPORT_ACCESS_METHOD_NIC: 843 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 844 break; 845 846 default: 847 return -EINVAL; 848 } 849 850 if (!err) 851 *node_guid = cpu_to_be64(tmp); 852 853 return err; 854 } 855 856 struct mlx5_reg_node_desc { 857 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 858 }; 859 860 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 861 { 862 struct mlx5_reg_node_desc in; 863 864 if (mlx5_use_mad_ifc(dev)) 865 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 866 867 memset(&in, 0, sizeof(in)); 868 869 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 870 sizeof(struct mlx5_reg_node_desc), 871 MLX5_REG_NODE_DESC, 0, 0); 872 } 873 874 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 875 struct mlx5_ib_query_device_resp *resp) 876 { 877 struct mlx5_eswitch *esw = mdev->priv.eswitch; 878 u16 vport = mlx5_eswitch_manager_vport(mdev); 879 880 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 881 vport); 882 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 883 } 884 885 static int mlx5_ib_query_device(struct ib_device *ibdev, 886 struct ib_device_attr *props, 887 struct ib_udata *uhw) 888 { 889 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 890 struct mlx5_ib_dev *dev = to_mdev(ibdev); 891 struct mlx5_core_dev *mdev = dev->mdev; 892 int err = -ENOMEM; 893 int max_sq_desc; 894 int max_rq_sg; 895 int max_sq_sg; 896 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 897 bool raw_support = !mlx5_core_mp_enabled(mdev); 898 struct mlx5_ib_query_device_resp resp = {}; 899 size_t resp_len; 900 u64 max_tso; 901 902 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 903 if (uhw_outlen && uhw_outlen < resp_len) 904 return -EINVAL; 905 906 resp.response_length = resp_len; 907 908 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 909 return -EINVAL; 910 911 memset(props, 0, sizeof(*props)); 912 err = mlx5_query_system_image_guid(ibdev, 913 &props->sys_image_guid); 914 if (err) 915 return err; 916 917 props->max_pkeys = dev->pkey_table_len; 918 919 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 920 if (err) 921 return err; 922 923 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 924 (fw_rev_min(dev->mdev) << 16) | 925 fw_rev_sub(dev->mdev); 926 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 927 IB_DEVICE_PORT_ACTIVE_EVENT | 928 IB_DEVICE_SYS_IMAGE_GUID | 929 IB_DEVICE_RC_RNR_NAK_GEN; 930 931 if (MLX5_CAP_GEN(mdev, pkv)) 932 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 933 if (MLX5_CAP_GEN(mdev, qkv)) 934 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 935 if (MLX5_CAP_GEN(mdev, apm)) 936 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 937 if (MLX5_CAP_GEN(mdev, xrc)) 938 props->device_cap_flags |= IB_DEVICE_XRC; 939 if (MLX5_CAP_GEN(mdev, imaicl)) { 940 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 941 IB_DEVICE_MEM_WINDOW_TYPE_2B; 942 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 943 /* We support 'Gappy' memory registration too */ 944 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 945 } 946 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 947 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 948 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 949 if (MLX5_CAP_GEN(mdev, sho)) { 950 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 951 /* At this stage no support for signature handover */ 952 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 953 IB_PROT_T10DIF_TYPE_2 | 954 IB_PROT_T10DIF_TYPE_3; 955 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 956 IB_GUARD_T10DIF_CSUM; 957 } 958 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 959 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 960 961 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 962 if (MLX5_CAP_ETH(mdev, csum_cap)) { 963 /* Legacy bit to support old userspace libraries */ 964 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 965 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 966 } 967 968 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 969 props->raw_packet_caps |= 970 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 971 972 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 973 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 974 if (max_tso) { 975 resp.tso_caps.max_tso = 1 << max_tso; 976 resp.tso_caps.supported_qpts |= 977 1 << IB_QPT_RAW_PACKET; 978 resp.response_length += sizeof(resp.tso_caps); 979 } 980 } 981 982 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 983 resp.rss_caps.rx_hash_function = 984 MLX5_RX_HASH_FUNC_TOEPLITZ; 985 resp.rss_caps.rx_hash_fields_mask = 986 MLX5_RX_HASH_SRC_IPV4 | 987 MLX5_RX_HASH_DST_IPV4 | 988 MLX5_RX_HASH_SRC_IPV6 | 989 MLX5_RX_HASH_DST_IPV6 | 990 MLX5_RX_HASH_SRC_PORT_TCP | 991 MLX5_RX_HASH_DST_PORT_TCP | 992 MLX5_RX_HASH_SRC_PORT_UDP | 993 MLX5_RX_HASH_DST_PORT_UDP | 994 MLX5_RX_HASH_INNER; 995 resp.response_length += sizeof(resp.rss_caps); 996 } 997 } else { 998 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 999 resp.response_length += sizeof(resp.tso_caps); 1000 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1001 resp.response_length += sizeof(resp.rss_caps); 1002 } 1003 1004 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1005 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1006 props->kernel_cap_flags |= IBK_UD_TSO; 1007 } 1008 1009 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1010 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1011 raw_support) 1012 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1013 1014 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1015 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1016 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1017 1018 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1019 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1020 raw_support) { 1021 /* Legacy bit to support old userspace libraries */ 1022 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1023 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1024 } 1025 1026 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1027 props->max_dm_size = 1028 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1029 } 1030 1031 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1032 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1033 1034 if (MLX5_CAP_GEN(mdev, end_pad)) 1035 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1036 1037 props->vendor_part_id = mdev->pdev->device; 1038 props->hw_ver = mdev->pdev->revision; 1039 1040 props->max_mr_size = ~0ull; 1041 props->page_size_cap = ~(min_page_size - 1); 1042 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1043 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1044 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1045 sizeof(struct mlx5_wqe_data_seg); 1046 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1047 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1048 sizeof(struct mlx5_wqe_raddr_seg)) / 1049 sizeof(struct mlx5_wqe_data_seg); 1050 props->max_send_sge = max_sq_sg; 1051 props->max_recv_sge = max_rq_sg; 1052 props->max_sge_rd = MLX5_MAX_SGE_RD; 1053 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1054 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1055 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1056 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1057 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1058 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1059 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1060 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1061 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1062 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1063 props->max_srq_sge = max_rq_sg - 1; 1064 props->max_fast_reg_page_list_len = 1065 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1066 props->max_pi_fast_reg_page_list_len = 1067 props->max_fast_reg_page_list_len / 2; 1068 props->max_sgl_rd = 1069 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1070 get_atomic_caps_qp(dev, props); 1071 props->masked_atomic_cap = IB_ATOMIC_NONE; 1072 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1073 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1074 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1075 props->max_mcast_grp; 1076 props->max_ah = INT_MAX; 1077 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1078 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1079 1080 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1081 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1082 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1083 props->odp_caps = dev->odp_caps; 1084 if (!uhw) { 1085 /* ODP for kernel QPs is not implemented for receive 1086 * WQEs and SRQ WQEs 1087 */ 1088 props->odp_caps.per_transport_caps.rc_odp_caps &= 1089 ~(IB_ODP_SUPPORT_READ | 1090 IB_ODP_SUPPORT_SRQ_RECV); 1091 props->odp_caps.per_transport_caps.uc_odp_caps &= 1092 ~(IB_ODP_SUPPORT_READ | 1093 IB_ODP_SUPPORT_SRQ_RECV); 1094 props->odp_caps.per_transport_caps.ud_odp_caps &= 1095 ~(IB_ODP_SUPPORT_READ | 1096 IB_ODP_SUPPORT_SRQ_RECV); 1097 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1098 ~(IB_ODP_SUPPORT_READ | 1099 IB_ODP_SUPPORT_SRQ_RECV); 1100 } 1101 } 1102 1103 if (mlx5_core_is_vf(mdev)) 1104 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1105 1106 if (mlx5_ib_port_link_layer(ibdev, 1) == 1107 IB_LINK_LAYER_ETHERNET && raw_support) { 1108 props->rss_caps.max_rwq_indirection_tables = 1109 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1110 props->rss_caps.max_rwq_indirection_table_size = 1111 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1112 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1113 props->max_wq_type_rq = 1114 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1115 } 1116 1117 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1118 props->tm_caps.max_num_tags = 1119 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1120 props->tm_caps.max_ops = 1121 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1122 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1123 } 1124 1125 if (MLX5_CAP_GEN(mdev, tag_matching) && 1126 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1127 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1128 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1129 } 1130 1131 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1132 props->cq_caps.max_cq_moderation_count = 1133 MLX5_MAX_CQ_COUNT; 1134 props->cq_caps.max_cq_moderation_period = 1135 MLX5_MAX_CQ_PERIOD; 1136 } 1137 1138 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1139 resp.response_length += sizeof(resp.cqe_comp_caps); 1140 1141 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1142 resp.cqe_comp_caps.max_num = 1143 MLX5_CAP_GEN(dev->mdev, 1144 cqe_compression_max_num); 1145 1146 resp.cqe_comp_caps.supported_format = 1147 MLX5_IB_CQE_RES_FORMAT_HASH | 1148 MLX5_IB_CQE_RES_FORMAT_CSUM; 1149 1150 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1151 resp.cqe_comp_caps.supported_format |= 1152 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1153 } 1154 } 1155 1156 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1157 raw_support) { 1158 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1159 MLX5_CAP_GEN(mdev, qos)) { 1160 resp.packet_pacing_caps.qp_rate_limit_max = 1161 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1162 resp.packet_pacing_caps.qp_rate_limit_min = 1163 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1164 resp.packet_pacing_caps.supported_qpts |= 1165 1 << IB_QPT_RAW_PACKET; 1166 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1167 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1168 resp.packet_pacing_caps.cap_flags |= 1169 MLX5_IB_PP_SUPPORT_BURST; 1170 } 1171 resp.response_length += sizeof(resp.packet_pacing_caps); 1172 } 1173 1174 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1175 uhw_outlen) { 1176 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1177 resp.mlx5_ib_support_multi_pkt_send_wqes = 1178 MLX5_IB_ALLOW_MPW; 1179 1180 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1181 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1182 MLX5_IB_SUPPORT_EMPW; 1183 1184 resp.response_length += 1185 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1186 } 1187 1188 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1189 resp.response_length += sizeof(resp.flags); 1190 1191 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1192 resp.flags |= 1193 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1194 1195 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1196 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1197 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1198 resp.flags |= 1199 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1200 1201 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1202 1203 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1204 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1205 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1206 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1207 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1208 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1209 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1210 } 1211 1212 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1213 resp.response_length += sizeof(resp.sw_parsing_caps); 1214 if (MLX5_CAP_ETH(mdev, swp)) { 1215 resp.sw_parsing_caps.sw_parsing_offloads |= 1216 MLX5_IB_SW_PARSING; 1217 1218 if (MLX5_CAP_ETH(mdev, swp_csum)) 1219 resp.sw_parsing_caps.sw_parsing_offloads |= 1220 MLX5_IB_SW_PARSING_CSUM; 1221 1222 if (MLX5_CAP_ETH(mdev, swp_lso)) 1223 resp.sw_parsing_caps.sw_parsing_offloads |= 1224 MLX5_IB_SW_PARSING_LSO; 1225 1226 if (resp.sw_parsing_caps.sw_parsing_offloads) 1227 resp.sw_parsing_caps.supported_qpts = 1228 BIT(IB_QPT_RAW_PACKET); 1229 } 1230 } 1231 1232 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1233 raw_support) { 1234 resp.response_length += sizeof(resp.striding_rq_caps); 1235 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1236 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1237 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1238 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1239 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1240 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1241 resp.striding_rq_caps 1242 .min_single_wqe_log_num_of_strides = 1243 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1244 else 1245 resp.striding_rq_caps 1246 .min_single_wqe_log_num_of_strides = 1247 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1248 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1249 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1250 resp.striding_rq_caps.supported_qpts = 1251 BIT(IB_QPT_RAW_PACKET); 1252 } 1253 } 1254 1255 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1256 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1257 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1258 resp.tunnel_offloads_caps |= 1259 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1260 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1261 resp.tunnel_offloads_caps |= 1262 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1263 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1264 resp.tunnel_offloads_caps |= 1265 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1266 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1267 resp.tunnel_offloads_caps |= 1268 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1269 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1270 resp.tunnel_offloads_caps |= 1271 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1272 } 1273 1274 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1275 resp.response_length += sizeof(resp.dci_streams_caps); 1276 1277 resp.dci_streams_caps.max_log_num_concurent = 1278 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1279 1280 resp.dci_streams_caps.max_log_num_errored = 1281 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1282 } 1283 1284 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1285 resp.response_length += sizeof(resp.reserved); 1286 1287 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1288 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1289 1290 resp.response_length += sizeof(resp.reg_c0); 1291 1292 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1293 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1294 fill_esw_mgr_reg_c0(mdev, &resp); 1295 } 1296 1297 if (uhw_outlen) { 1298 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1299 1300 if (err) 1301 return err; 1302 } 1303 1304 return 0; 1305 } 1306 1307 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1308 u8 *ib_width) 1309 { 1310 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1311 1312 if (active_width & MLX5_PTYS_WIDTH_1X) 1313 *ib_width = IB_WIDTH_1X; 1314 else if (active_width & MLX5_PTYS_WIDTH_2X) 1315 *ib_width = IB_WIDTH_2X; 1316 else if (active_width & MLX5_PTYS_WIDTH_4X) 1317 *ib_width = IB_WIDTH_4X; 1318 else if (active_width & MLX5_PTYS_WIDTH_8X) 1319 *ib_width = IB_WIDTH_8X; 1320 else if (active_width & MLX5_PTYS_WIDTH_12X) 1321 *ib_width = IB_WIDTH_12X; 1322 else { 1323 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1324 active_width); 1325 *ib_width = IB_WIDTH_4X; 1326 } 1327 1328 return; 1329 } 1330 1331 static int mlx5_mtu_to_ib_mtu(int mtu) 1332 { 1333 switch (mtu) { 1334 case 256: return 1; 1335 case 512: return 2; 1336 case 1024: return 3; 1337 case 2048: return 4; 1338 case 4096: return 5; 1339 default: 1340 pr_warn("invalid mtu\n"); 1341 return -1; 1342 } 1343 } 1344 1345 enum ib_max_vl_num { 1346 __IB_MAX_VL_0 = 1, 1347 __IB_MAX_VL_0_1 = 2, 1348 __IB_MAX_VL_0_3 = 3, 1349 __IB_MAX_VL_0_7 = 4, 1350 __IB_MAX_VL_0_14 = 5, 1351 }; 1352 1353 enum mlx5_vl_hw_cap { 1354 MLX5_VL_HW_0 = 1, 1355 MLX5_VL_HW_0_1 = 2, 1356 MLX5_VL_HW_0_2 = 3, 1357 MLX5_VL_HW_0_3 = 4, 1358 MLX5_VL_HW_0_4 = 5, 1359 MLX5_VL_HW_0_5 = 6, 1360 MLX5_VL_HW_0_6 = 7, 1361 MLX5_VL_HW_0_7 = 8, 1362 MLX5_VL_HW_0_14 = 15 1363 }; 1364 1365 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1366 u8 *max_vl_num) 1367 { 1368 switch (vl_hw_cap) { 1369 case MLX5_VL_HW_0: 1370 *max_vl_num = __IB_MAX_VL_0; 1371 break; 1372 case MLX5_VL_HW_0_1: 1373 *max_vl_num = __IB_MAX_VL_0_1; 1374 break; 1375 case MLX5_VL_HW_0_3: 1376 *max_vl_num = __IB_MAX_VL_0_3; 1377 break; 1378 case MLX5_VL_HW_0_7: 1379 *max_vl_num = __IB_MAX_VL_0_7; 1380 break; 1381 case MLX5_VL_HW_0_14: 1382 *max_vl_num = __IB_MAX_VL_0_14; 1383 break; 1384 1385 default: 1386 return -EINVAL; 1387 } 1388 1389 return 0; 1390 } 1391 1392 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1393 struct ib_port_attr *props) 1394 { 1395 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1396 struct mlx5_core_dev *mdev = dev->mdev; 1397 struct mlx5_hca_vport_context *rep; 1398 u8 vl_hw_cap, plane_index = 0; 1399 u16 max_mtu; 1400 u16 oper_mtu; 1401 int err; 1402 u16 ib_link_width_oper; 1403 1404 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1405 if (!rep) { 1406 err = -ENOMEM; 1407 goto out; 1408 } 1409 1410 /* props being zeroed by the caller, avoid zeroing it here */ 1411 1412 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1413 plane_index = port; 1414 port = smi_to_native_portnum(dev, port); 1415 } 1416 1417 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1418 if (err) 1419 goto out; 1420 1421 props->lid = rep->lid; 1422 props->lmc = rep->lmc; 1423 props->sm_lid = rep->sm_lid; 1424 props->sm_sl = rep->sm_sl; 1425 props->state = rep->vport_state; 1426 props->phys_state = rep->port_physical_state; 1427 1428 props->port_cap_flags = rep->cap_mask1; 1429 if (dev->num_plane) { 1430 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1431 props->port_cap_flags &= ~IB_PORT_SM; 1432 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1433 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1434 1435 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1436 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1437 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1438 props->bad_pkey_cntr = rep->pkey_violation_counter; 1439 props->qkey_viol_cntr = rep->qkey_violation_counter; 1440 props->subnet_timeout = rep->subnet_timeout; 1441 props->init_type_reply = rep->init_type_reply; 1442 1443 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1444 props->port_cap_flags2 = rep->cap_mask2; 1445 1446 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1447 &props->active_speed, port, plane_index); 1448 if (err) 1449 goto out; 1450 1451 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1452 1453 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1454 1455 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1456 1457 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1458 1459 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1460 1461 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1462 if (err) 1463 goto out; 1464 1465 err = translate_max_vl_num(ibdev, vl_hw_cap, 1466 &props->max_vl_num); 1467 out: 1468 kfree(rep); 1469 return err; 1470 } 1471 1472 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1473 struct ib_port_attr *props) 1474 { 1475 unsigned int count; 1476 int ret; 1477 1478 switch (mlx5_get_vport_access_method(ibdev)) { 1479 case MLX5_VPORT_ACCESS_METHOD_MAD: 1480 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1481 break; 1482 1483 case MLX5_VPORT_ACCESS_METHOD_HCA: 1484 ret = mlx5_query_hca_port(ibdev, port, props); 1485 break; 1486 1487 case MLX5_VPORT_ACCESS_METHOD_NIC: 1488 ret = mlx5_query_port_roce(ibdev, port, props); 1489 break; 1490 1491 default: 1492 ret = -EINVAL; 1493 } 1494 1495 if (!ret && props) { 1496 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1497 struct mlx5_core_dev *mdev; 1498 bool put_mdev = true; 1499 1500 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1501 if (!mdev) { 1502 /* If the port isn't affiliated yet query the master. 1503 * The master and slave will have the same values. 1504 */ 1505 mdev = dev->mdev; 1506 port = 1; 1507 put_mdev = false; 1508 } 1509 count = mlx5_core_reserved_gids_count(mdev); 1510 if (put_mdev) 1511 mlx5_ib_put_native_port_mdev(dev, port); 1512 props->gid_tbl_len -= count; 1513 } 1514 return ret; 1515 } 1516 1517 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1518 struct ib_port_attr *props) 1519 { 1520 return mlx5_query_port_roce(ibdev, port, props); 1521 } 1522 1523 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1524 u16 *pkey) 1525 { 1526 /* Default special Pkey for representor device port as per the 1527 * IB specification 1.3 section 10.9.1.2. 1528 */ 1529 *pkey = 0xffff; 1530 return 0; 1531 } 1532 1533 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1534 union ib_gid *gid) 1535 { 1536 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1537 struct mlx5_core_dev *mdev = dev->mdev; 1538 1539 switch (mlx5_get_vport_access_method(ibdev)) { 1540 case MLX5_VPORT_ACCESS_METHOD_MAD: 1541 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1542 1543 case MLX5_VPORT_ACCESS_METHOD_HCA: 1544 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1545 1546 default: 1547 return -EINVAL; 1548 } 1549 1550 } 1551 1552 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1553 u16 index, u16 *pkey) 1554 { 1555 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1556 struct mlx5_core_dev *mdev; 1557 bool put_mdev = true; 1558 u32 mdev_port_num; 1559 int err; 1560 1561 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1562 if (!mdev) { 1563 /* The port isn't affiliated yet, get the PKey from the master 1564 * port. For RoCE the PKey tables will be the same. 1565 */ 1566 put_mdev = false; 1567 mdev = dev->mdev; 1568 mdev_port_num = 1; 1569 } 1570 1571 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1572 index, pkey); 1573 if (put_mdev) 1574 mlx5_ib_put_native_port_mdev(dev, port); 1575 1576 return err; 1577 } 1578 1579 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1580 u16 *pkey) 1581 { 1582 switch (mlx5_get_vport_access_method(ibdev)) { 1583 case MLX5_VPORT_ACCESS_METHOD_MAD: 1584 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1585 1586 case MLX5_VPORT_ACCESS_METHOD_HCA: 1587 case MLX5_VPORT_ACCESS_METHOD_NIC: 1588 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1589 default: 1590 return -EINVAL; 1591 } 1592 } 1593 1594 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1595 struct ib_device_modify *props) 1596 { 1597 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1598 struct mlx5_reg_node_desc in; 1599 struct mlx5_reg_node_desc out; 1600 int err; 1601 1602 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1603 return -EOPNOTSUPP; 1604 1605 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1606 return 0; 1607 1608 /* 1609 * If possible, pass node desc to FW, so it can generate 1610 * a 144 trap. If cmd fails, just ignore. 1611 */ 1612 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1613 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1614 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1615 if (err) 1616 return err; 1617 1618 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1619 1620 return err; 1621 } 1622 1623 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1624 u32 value) 1625 { 1626 struct mlx5_hca_vport_context ctx = {}; 1627 struct mlx5_core_dev *mdev; 1628 u32 mdev_port_num; 1629 int err; 1630 1631 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1632 if (!mdev) 1633 return -ENODEV; 1634 1635 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1636 if (err) 1637 goto out; 1638 1639 if (~ctx.cap_mask1_perm & mask) { 1640 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1641 mask, ctx.cap_mask1_perm); 1642 err = -EINVAL; 1643 goto out; 1644 } 1645 1646 ctx.cap_mask1 = value; 1647 ctx.cap_mask1_perm = mask; 1648 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1649 0, &ctx); 1650 1651 out: 1652 mlx5_ib_put_native_port_mdev(dev, port_num); 1653 1654 return err; 1655 } 1656 1657 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1658 struct ib_port_modify *props) 1659 { 1660 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1661 struct ib_port_attr attr; 1662 u32 tmp; 1663 int err; 1664 u32 change_mask; 1665 u32 value; 1666 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1667 IB_LINK_LAYER_INFINIBAND); 1668 1669 /* CM layer calls ib_modify_port() regardless of the link layer. For 1670 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1671 */ 1672 if (!is_ib) 1673 return 0; 1674 1675 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1676 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1677 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1678 return set_port_caps_atomic(dev, port, change_mask, value); 1679 } 1680 1681 mutex_lock(&dev->cap_mask_mutex); 1682 1683 err = ib_query_port(ibdev, port, &attr); 1684 if (err) 1685 goto out; 1686 1687 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1688 ~props->clr_port_cap_mask; 1689 1690 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1691 1692 out: 1693 mutex_unlock(&dev->cap_mask_mutex); 1694 return err; 1695 } 1696 1697 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1698 { 1699 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1700 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1701 } 1702 1703 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1704 { 1705 /* Large page with non 4k uar support might limit the dynamic size */ 1706 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1707 return MLX5_MIN_DYN_BFREGS; 1708 1709 return MLX5_MAX_DYN_BFREGS; 1710 } 1711 1712 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1713 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1714 struct mlx5_bfreg_info *bfregi) 1715 { 1716 int uars_per_sys_page; 1717 int bfregs_per_sys_page; 1718 int ref_bfregs = req->total_num_bfregs; 1719 1720 if (req->total_num_bfregs == 0) 1721 return -EINVAL; 1722 1723 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1724 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1725 1726 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1727 return -ENOMEM; 1728 1729 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1730 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1731 /* This holds the required static allocation asked by the user */ 1732 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1733 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1734 return -EINVAL; 1735 1736 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1737 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1738 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1739 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1740 1741 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1742 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1743 lib_uar_4k ? "yes" : "no", ref_bfregs, 1744 req->total_num_bfregs, bfregi->total_num_bfregs, 1745 bfregi->num_sys_pages); 1746 1747 return 0; 1748 } 1749 1750 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1751 { 1752 struct mlx5_bfreg_info *bfregi; 1753 int err; 1754 int i; 1755 1756 bfregi = &context->bfregi; 1757 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1758 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1759 context->devx_uid); 1760 if (err) 1761 goto error; 1762 1763 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1764 } 1765 1766 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1767 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1768 1769 return 0; 1770 1771 error: 1772 for (--i; i >= 0; i--) 1773 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1774 context->devx_uid)) 1775 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1776 1777 return err; 1778 } 1779 1780 static void deallocate_uars(struct mlx5_ib_dev *dev, 1781 struct mlx5_ib_ucontext *context) 1782 { 1783 struct mlx5_bfreg_info *bfregi; 1784 int i; 1785 1786 bfregi = &context->bfregi; 1787 for (i = 0; i < bfregi->num_sys_pages; i++) 1788 if (i < bfregi->num_static_sys_pages || 1789 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1790 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1791 context->devx_uid); 1792 } 1793 1794 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1795 { 1796 int err = 0; 1797 1798 mutex_lock(&dev->lb.mutex); 1799 if (td) 1800 dev->lb.user_td++; 1801 if (qp) 1802 dev->lb.qps++; 1803 1804 if (dev->lb.user_td == 2 || 1805 dev->lb.qps == 1) { 1806 if (!dev->lb.enabled) { 1807 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1808 dev->lb.enabled = true; 1809 } 1810 } 1811 1812 mutex_unlock(&dev->lb.mutex); 1813 1814 return err; 1815 } 1816 1817 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1818 { 1819 mutex_lock(&dev->lb.mutex); 1820 if (td) 1821 dev->lb.user_td--; 1822 if (qp) 1823 dev->lb.qps--; 1824 1825 if (dev->lb.user_td == 1 && 1826 dev->lb.qps == 0) { 1827 if (dev->lb.enabled) { 1828 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1829 dev->lb.enabled = false; 1830 } 1831 } 1832 1833 mutex_unlock(&dev->lb.mutex); 1834 } 1835 1836 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1837 u16 uid) 1838 { 1839 int err; 1840 1841 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1842 return 0; 1843 1844 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1845 if (err) 1846 return err; 1847 1848 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1849 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1850 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1851 return err; 1852 1853 return mlx5_ib_enable_lb(dev, true, false); 1854 } 1855 1856 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1857 u16 uid) 1858 { 1859 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1860 return; 1861 1862 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1863 1864 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1865 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1866 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1867 return; 1868 1869 mlx5_ib_disable_lb(dev, true, false); 1870 } 1871 1872 static int set_ucontext_resp(struct ib_ucontext *uctx, 1873 struct mlx5_ib_alloc_ucontext_resp *resp) 1874 { 1875 struct ib_device *ibdev = uctx->device; 1876 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1877 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1878 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1879 1880 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1881 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1882 resp->comp_mask |= 1883 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1884 } 1885 1886 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1887 if (mlx5_wc_support_get(dev->mdev)) 1888 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1889 log_bf_reg_size); 1890 resp->cache_line_size = cache_line_size(); 1891 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1892 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1893 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1894 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1895 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1896 resp->cqe_version = context->cqe_version; 1897 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1898 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1899 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1900 MLX5_CAP_GEN(dev->mdev, 1901 num_of_uars_per_page) : 1; 1902 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1903 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1904 resp->num_ports = dev->num_ports; 1905 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1906 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1907 1908 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1909 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1910 resp->eth_min_inline++; 1911 } 1912 1913 if (dev->mdev->clock_info) 1914 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1915 1916 /* 1917 * We don't want to expose information from the PCI bar that is located 1918 * after 4096 bytes, so if the arch only supports larger pages, let's 1919 * pretend we don't support reading the HCA's core clock. This is also 1920 * forced by mmap function. 1921 */ 1922 if (PAGE_SIZE <= 4096) { 1923 resp->comp_mask |= 1924 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1925 resp->hca_core_clock_offset = 1926 offsetof(struct mlx5_init_seg, 1927 internal_timer_h) % PAGE_SIZE; 1928 } 1929 1930 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1931 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1932 1933 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1934 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1935 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1936 resp->comp_mask |= 1937 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1938 1939 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1940 1941 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1942 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1943 1944 resp->comp_mask |= 1945 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1946 1947 return 0; 1948 } 1949 1950 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 1951 { 1952 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 1953 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 1954 } 1955 1956 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1957 struct ib_udata *udata) 1958 { 1959 struct ib_device *ibdev = uctx->device; 1960 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1961 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1962 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1963 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1964 struct mlx5_bfreg_info *bfregi; 1965 int ver; 1966 int err; 1967 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1968 max_cqe_version); 1969 bool lib_uar_4k; 1970 bool lib_uar_dyn; 1971 1972 if (!dev->ib_active) 1973 return -EAGAIN; 1974 1975 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1976 ver = 0; 1977 else if (udata->inlen >= min_req_v2) 1978 ver = 2; 1979 else 1980 return -EINVAL; 1981 1982 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1983 if (err) 1984 return err; 1985 1986 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1987 return -EOPNOTSUPP; 1988 1989 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1990 return -EOPNOTSUPP; 1991 1992 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1993 MLX5_NON_FP_BFREGS_PER_UAR); 1994 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1995 return -EINVAL; 1996 1997 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1998 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 1999 if (err < 0) 2000 goto out_ctx; 2001 context->devx_uid = err; 2002 2003 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2004 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2005 context->devx_uid); 2006 if (err) 2007 goto out_devx; 2008 } 2009 } 2010 2011 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2012 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2013 bfregi = &context->bfregi; 2014 2015 if (lib_uar_dyn) { 2016 bfregi->lib_uar_dyn = lib_uar_dyn; 2017 goto uar_done; 2018 } 2019 2020 /* updates req->total_num_bfregs */ 2021 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2022 if (err) 2023 goto out_ucap; 2024 2025 mutex_init(&bfregi->lock); 2026 bfregi->lib_uar_4k = lib_uar_4k; 2027 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2028 GFP_KERNEL); 2029 if (!bfregi->count) { 2030 err = -ENOMEM; 2031 goto out_ucap; 2032 } 2033 2034 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2035 sizeof(*bfregi->sys_pages), 2036 GFP_KERNEL); 2037 if (!bfregi->sys_pages) { 2038 err = -ENOMEM; 2039 goto out_count; 2040 } 2041 2042 err = allocate_uars(dev, context); 2043 if (err) 2044 goto out_sys_pages; 2045 2046 uar_done: 2047 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2048 context->devx_uid); 2049 if (err) 2050 goto out_uars; 2051 2052 INIT_LIST_HEAD(&context->db_page_list); 2053 mutex_init(&context->db_page_mutex); 2054 2055 context->cqe_version = min_t(__u8, 2056 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2057 req.max_cqe_version); 2058 2059 err = set_ucontext_resp(uctx, &resp); 2060 if (err) 2061 goto out_mdev; 2062 2063 resp.response_length = min(udata->outlen, sizeof(resp)); 2064 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2065 if (err) 2066 goto out_mdev; 2067 2068 bfregi->ver = ver; 2069 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2070 context->lib_caps = req.lib_caps; 2071 print_lib_caps(dev, context->lib_caps); 2072 2073 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2074 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2075 2076 atomic_set(&context->tx_port_affinity, 2077 atomic_add_return( 2078 1, &dev->port[port].roce.tx_port_affinity)); 2079 } 2080 2081 return 0; 2082 2083 out_mdev: 2084 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2085 2086 out_uars: 2087 deallocate_uars(dev, context); 2088 2089 out_sys_pages: 2090 kfree(bfregi->sys_pages); 2091 2092 out_count: 2093 kfree(bfregi->count); 2094 2095 out_ucap: 2096 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2097 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2098 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2099 2100 out_devx: 2101 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2102 mlx5_ib_devx_destroy(dev, context->devx_uid); 2103 2104 out_ctx: 2105 return err; 2106 } 2107 2108 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2109 struct uverbs_attr_bundle *attrs) 2110 { 2111 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2112 int ret; 2113 2114 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2115 if (ret) 2116 return ret; 2117 2118 uctx_resp.response_length = 2119 min_t(size_t, 2120 uverbs_attr_get_len(attrs, 2121 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2122 sizeof(uctx_resp)); 2123 2124 ret = uverbs_copy_to_struct_or_zero(attrs, 2125 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2126 &uctx_resp, 2127 sizeof(uctx_resp)); 2128 return ret; 2129 } 2130 2131 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2132 { 2133 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2134 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2135 struct mlx5_bfreg_info *bfregi; 2136 2137 bfregi = &context->bfregi; 2138 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2139 2140 deallocate_uars(dev, context); 2141 kfree(bfregi->sys_pages); 2142 kfree(bfregi->count); 2143 2144 if (context->devx_uid) { 2145 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2146 mlx5_cmd_remove_privileged_uid(dev->mdev, 2147 context->devx_uid); 2148 mlx5_ib_devx_destroy(dev, context->devx_uid); 2149 } 2150 } 2151 2152 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2153 int uar_idx) 2154 { 2155 int fw_uars_per_page; 2156 2157 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2158 2159 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2160 } 2161 2162 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2163 int uar_idx) 2164 { 2165 unsigned int fw_uars_per_page; 2166 2167 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2168 MLX5_UARS_IN_PAGE : 1; 2169 2170 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2171 } 2172 2173 static int get_command(unsigned long offset) 2174 { 2175 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2176 } 2177 2178 static int get_arg(unsigned long offset) 2179 { 2180 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2181 } 2182 2183 static int get_index(unsigned long offset) 2184 { 2185 return get_arg(offset); 2186 } 2187 2188 /* Index resides in an extra byte to enable larger values than 255 */ 2189 static int get_extended_index(unsigned long offset) 2190 { 2191 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2192 } 2193 2194 2195 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2196 { 2197 } 2198 2199 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2200 { 2201 switch (cmd) { 2202 case MLX5_IB_MMAP_WC_PAGE: 2203 return "WC"; 2204 case MLX5_IB_MMAP_REGULAR_PAGE: 2205 return "best effort WC"; 2206 case MLX5_IB_MMAP_NC_PAGE: 2207 return "NC"; 2208 case MLX5_IB_MMAP_DEVICE_MEM: 2209 return "Device Memory"; 2210 default: 2211 return "Unknown"; 2212 } 2213 } 2214 2215 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2216 struct vm_area_struct *vma, 2217 struct mlx5_ib_ucontext *context) 2218 { 2219 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2220 !(vma->vm_flags & VM_SHARED)) 2221 return -EINVAL; 2222 2223 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2224 return -EOPNOTSUPP; 2225 2226 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2227 return -EPERM; 2228 vm_flags_clear(vma, VM_MAYWRITE); 2229 2230 if (!dev->mdev->clock_info) 2231 return -EOPNOTSUPP; 2232 2233 return vm_insert_page(vma, vma->vm_start, 2234 virt_to_page(dev->mdev->clock_info)); 2235 } 2236 2237 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2238 { 2239 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2240 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2241 struct mlx5_var_table *var_table = &dev->var_table; 2242 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2243 2244 switch (mentry->mmap_flag) { 2245 case MLX5_IB_MMAP_TYPE_MEMIC: 2246 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2247 mlx5_ib_dm_mmap_free(dev, mentry); 2248 break; 2249 case MLX5_IB_MMAP_TYPE_VAR: 2250 mutex_lock(&var_table->bitmap_lock); 2251 clear_bit(mentry->page_idx, var_table->bitmap); 2252 mutex_unlock(&var_table->bitmap_lock); 2253 kfree(mentry); 2254 break; 2255 case MLX5_IB_MMAP_TYPE_UAR_WC: 2256 case MLX5_IB_MMAP_TYPE_UAR_NC: 2257 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2258 context->devx_uid); 2259 kfree(mentry); 2260 break; 2261 default: 2262 WARN_ON(true); 2263 } 2264 } 2265 2266 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2267 struct vm_area_struct *vma, 2268 struct mlx5_ib_ucontext *context) 2269 { 2270 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2271 int err; 2272 unsigned long idx; 2273 phys_addr_t pfn; 2274 pgprot_t prot; 2275 u32 bfreg_dyn_idx = 0; 2276 u32 uar_index; 2277 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2278 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2279 bfregi->num_static_sys_pages; 2280 2281 if (bfregi->lib_uar_dyn) 2282 return -EINVAL; 2283 2284 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2285 return -EINVAL; 2286 2287 if (dyn_uar) 2288 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2289 else 2290 idx = get_index(vma->vm_pgoff); 2291 2292 if (idx >= max_valid_idx) { 2293 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2294 idx, max_valid_idx); 2295 return -EINVAL; 2296 } 2297 2298 switch (cmd) { 2299 case MLX5_IB_MMAP_WC_PAGE: 2300 case MLX5_IB_MMAP_ALLOC_WC: 2301 case MLX5_IB_MMAP_REGULAR_PAGE: 2302 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2303 prot = pgprot_writecombine(vma->vm_page_prot); 2304 break; 2305 case MLX5_IB_MMAP_NC_PAGE: 2306 prot = pgprot_noncached(vma->vm_page_prot); 2307 break; 2308 default: 2309 return -EINVAL; 2310 } 2311 2312 if (dyn_uar) { 2313 int uars_per_page; 2314 2315 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2316 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2317 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2318 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2319 bfreg_dyn_idx, bfregi->total_num_bfregs); 2320 return -EINVAL; 2321 } 2322 2323 mutex_lock(&bfregi->lock); 2324 /* Fail if uar already allocated, first bfreg index of each 2325 * page holds its count. 2326 */ 2327 if (bfregi->count[bfreg_dyn_idx]) { 2328 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2329 mutex_unlock(&bfregi->lock); 2330 return -EINVAL; 2331 } 2332 2333 bfregi->count[bfreg_dyn_idx]++; 2334 mutex_unlock(&bfregi->lock); 2335 2336 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2337 context->devx_uid); 2338 if (err) { 2339 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2340 goto free_bfreg; 2341 } 2342 } else { 2343 uar_index = bfregi->sys_pages[idx]; 2344 } 2345 2346 pfn = uar_index2pfn(dev, uar_index); 2347 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2348 2349 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2350 prot, NULL); 2351 if (err) { 2352 mlx5_ib_err(dev, 2353 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2354 err, mmap_cmd2str(cmd)); 2355 goto err; 2356 } 2357 2358 if (dyn_uar) 2359 bfregi->sys_pages[idx] = uar_index; 2360 return 0; 2361 2362 err: 2363 if (!dyn_uar) 2364 return err; 2365 2366 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2367 2368 free_bfreg: 2369 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2370 2371 return err; 2372 } 2373 2374 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2375 { 2376 unsigned long idx; 2377 u8 command; 2378 2379 command = get_command(vma->vm_pgoff); 2380 idx = get_extended_index(vma->vm_pgoff); 2381 2382 return (command << 16 | idx); 2383 } 2384 2385 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2386 struct vm_area_struct *vma, 2387 struct ib_ucontext *ucontext) 2388 { 2389 struct mlx5_user_mmap_entry *mentry; 2390 struct rdma_user_mmap_entry *entry; 2391 unsigned long pgoff; 2392 pgprot_t prot; 2393 phys_addr_t pfn; 2394 int ret; 2395 2396 pgoff = mlx5_vma_to_pgoff(vma); 2397 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2398 if (!entry) 2399 return -EINVAL; 2400 2401 mentry = to_mmmap(entry); 2402 pfn = (mentry->address >> PAGE_SHIFT); 2403 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2404 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2405 prot = pgprot_noncached(vma->vm_page_prot); 2406 else 2407 prot = pgprot_writecombine(vma->vm_page_prot); 2408 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2409 entry->npages * PAGE_SIZE, 2410 prot, 2411 entry); 2412 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2413 return ret; 2414 } 2415 2416 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2417 { 2418 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2419 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2420 2421 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2422 (index & 0xFF)) << PAGE_SHIFT; 2423 } 2424 2425 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2426 { 2427 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2428 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2429 unsigned long command; 2430 phys_addr_t pfn; 2431 2432 command = get_command(vma->vm_pgoff); 2433 switch (command) { 2434 case MLX5_IB_MMAP_WC_PAGE: 2435 case MLX5_IB_MMAP_ALLOC_WC: 2436 if (!mlx5_wc_support_get(dev->mdev)) 2437 return -EPERM; 2438 fallthrough; 2439 case MLX5_IB_MMAP_NC_PAGE: 2440 case MLX5_IB_MMAP_REGULAR_PAGE: 2441 return uar_mmap(dev, command, vma, context); 2442 2443 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2444 return -ENOSYS; 2445 2446 case MLX5_IB_MMAP_CORE_CLOCK: 2447 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2448 return -EINVAL; 2449 2450 if (vma->vm_flags & VM_WRITE) 2451 return -EPERM; 2452 vm_flags_clear(vma, VM_MAYWRITE); 2453 2454 /* Don't expose to user-space information it shouldn't have */ 2455 if (PAGE_SIZE > 4096) 2456 return -EOPNOTSUPP; 2457 2458 pfn = (dev->mdev->iseg_base + 2459 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2460 PAGE_SHIFT; 2461 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2462 PAGE_SIZE, 2463 pgprot_noncached(vma->vm_page_prot), 2464 NULL); 2465 case MLX5_IB_MMAP_CLOCK_INFO: 2466 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2467 2468 default: 2469 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2476 { 2477 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2478 struct ib_device *ibdev = ibpd->device; 2479 struct mlx5_ib_alloc_pd_resp resp; 2480 int err; 2481 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2482 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2483 u16 uid = 0; 2484 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2485 udata, struct mlx5_ib_ucontext, ibucontext); 2486 2487 uid = context ? context->devx_uid : 0; 2488 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2489 MLX5_SET(alloc_pd_in, in, uid, uid); 2490 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2491 if (err) 2492 return err; 2493 2494 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2495 pd->uid = uid; 2496 if (udata) { 2497 resp.pdn = pd->pdn; 2498 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2499 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2500 return -EFAULT; 2501 } 2502 } 2503 2504 return 0; 2505 } 2506 2507 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2508 { 2509 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2510 struct mlx5_ib_pd *mpd = to_mpd(pd); 2511 2512 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2513 } 2514 2515 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2516 { 2517 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2518 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2519 int err; 2520 u16 uid; 2521 2522 uid = ibqp->pd ? 2523 to_mpd(ibqp->pd)->uid : 0; 2524 2525 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2526 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2527 return -EOPNOTSUPP; 2528 } 2529 2530 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2531 if (err) 2532 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2533 ibqp->qp_num, gid->raw); 2534 2535 return err; 2536 } 2537 2538 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2539 { 2540 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2541 int err; 2542 u16 uid; 2543 2544 uid = ibqp->pd ? 2545 to_mpd(ibqp->pd)->uid : 0; 2546 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2547 if (err) 2548 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2549 ibqp->qp_num, gid->raw); 2550 2551 return err; 2552 } 2553 2554 static int init_node_data(struct mlx5_ib_dev *dev) 2555 { 2556 int err; 2557 2558 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2559 if (err) 2560 return err; 2561 2562 dev->mdev->rev_id = dev->mdev->pdev->revision; 2563 2564 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2565 } 2566 2567 static ssize_t fw_pages_show(struct device *device, 2568 struct device_attribute *attr, char *buf) 2569 { 2570 struct mlx5_ib_dev *dev = 2571 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2572 2573 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2574 } 2575 static DEVICE_ATTR_RO(fw_pages); 2576 2577 static ssize_t reg_pages_show(struct device *device, 2578 struct device_attribute *attr, char *buf) 2579 { 2580 struct mlx5_ib_dev *dev = 2581 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2582 2583 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2584 } 2585 static DEVICE_ATTR_RO(reg_pages); 2586 2587 static ssize_t hca_type_show(struct device *device, 2588 struct device_attribute *attr, char *buf) 2589 { 2590 struct mlx5_ib_dev *dev = 2591 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2592 2593 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2594 } 2595 static DEVICE_ATTR_RO(hca_type); 2596 2597 static ssize_t hw_rev_show(struct device *device, 2598 struct device_attribute *attr, char *buf) 2599 { 2600 struct mlx5_ib_dev *dev = 2601 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2602 2603 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2604 } 2605 static DEVICE_ATTR_RO(hw_rev); 2606 2607 static ssize_t board_id_show(struct device *device, 2608 struct device_attribute *attr, char *buf) 2609 { 2610 struct mlx5_ib_dev *dev = 2611 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2612 2613 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2614 dev->mdev->board_id); 2615 } 2616 static DEVICE_ATTR_RO(board_id); 2617 2618 static struct attribute *mlx5_class_attributes[] = { 2619 &dev_attr_hw_rev.attr, 2620 &dev_attr_hca_type.attr, 2621 &dev_attr_board_id.attr, 2622 &dev_attr_fw_pages.attr, 2623 &dev_attr_reg_pages.attr, 2624 NULL, 2625 }; 2626 2627 static const struct attribute_group mlx5_attr_group = { 2628 .attrs = mlx5_class_attributes, 2629 }; 2630 2631 static void pkey_change_handler(struct work_struct *work) 2632 { 2633 struct mlx5_ib_port_resources *ports = 2634 container_of(work, struct mlx5_ib_port_resources, 2635 pkey_change_work); 2636 2637 if (!ports->gsi) 2638 /* 2639 * We got this event before device was fully configured 2640 * and MAD registration code wasn't called/finished yet. 2641 */ 2642 return; 2643 2644 mlx5_ib_gsi_pkey_change(ports->gsi); 2645 } 2646 2647 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2648 { 2649 struct mlx5_ib_qp *mqp; 2650 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2651 struct mlx5_core_cq *mcq; 2652 struct list_head cq_armed_list; 2653 unsigned long flags_qp; 2654 unsigned long flags_cq; 2655 unsigned long flags; 2656 2657 INIT_LIST_HEAD(&cq_armed_list); 2658 2659 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2660 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2661 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2662 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2663 if (mqp->sq.tail != mqp->sq.head) { 2664 send_mcq = to_mcq(mqp->ibqp.send_cq); 2665 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2666 if (send_mcq->mcq.comp && 2667 mqp->ibqp.send_cq->comp_handler) { 2668 if (!send_mcq->mcq.reset_notify_added) { 2669 send_mcq->mcq.reset_notify_added = 1; 2670 list_add_tail(&send_mcq->mcq.reset_notify, 2671 &cq_armed_list); 2672 } 2673 } 2674 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2675 } 2676 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2677 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2678 /* no handling is needed for SRQ */ 2679 if (!mqp->ibqp.srq) { 2680 if (mqp->rq.tail != mqp->rq.head) { 2681 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2682 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2683 if (recv_mcq->mcq.comp && 2684 mqp->ibqp.recv_cq->comp_handler) { 2685 if (!recv_mcq->mcq.reset_notify_added) { 2686 recv_mcq->mcq.reset_notify_added = 1; 2687 list_add_tail(&recv_mcq->mcq.reset_notify, 2688 &cq_armed_list); 2689 } 2690 } 2691 spin_unlock_irqrestore(&recv_mcq->lock, 2692 flags_cq); 2693 } 2694 } 2695 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2696 } 2697 /*At that point all inflight post send were put to be executed as of we 2698 * lock/unlock above locks Now need to arm all involved CQs. 2699 */ 2700 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2701 mcq->comp(mcq, NULL); 2702 } 2703 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2704 } 2705 2706 static void delay_drop_handler(struct work_struct *work) 2707 { 2708 int err; 2709 struct mlx5_ib_delay_drop *delay_drop = 2710 container_of(work, struct mlx5_ib_delay_drop, 2711 delay_drop_work); 2712 2713 atomic_inc(&delay_drop->events_cnt); 2714 2715 mutex_lock(&delay_drop->lock); 2716 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2717 if (err) { 2718 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2719 delay_drop->timeout); 2720 delay_drop->activate = false; 2721 } 2722 mutex_unlock(&delay_drop->lock); 2723 } 2724 2725 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2726 struct ib_event *ibev) 2727 { 2728 u32 port = (eqe->data.port.port >> 4) & 0xf; 2729 2730 switch (eqe->sub_type) { 2731 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2732 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2733 IB_LINK_LAYER_ETHERNET) 2734 schedule_work(&ibdev->delay_drop.delay_drop_work); 2735 break; 2736 default: /* do nothing */ 2737 return; 2738 } 2739 } 2740 2741 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2742 struct ib_event *ibev) 2743 { 2744 u32 port = (eqe->data.port.port >> 4) & 0xf; 2745 2746 ibev->element.port_num = port; 2747 2748 switch (eqe->sub_type) { 2749 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2750 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2751 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2752 /* In RoCE, port up/down events are handled in 2753 * mlx5_netdev_event(). 2754 */ 2755 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2756 IB_LINK_LAYER_ETHERNET) 2757 return -EINVAL; 2758 2759 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2760 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2761 break; 2762 2763 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2764 ibev->event = IB_EVENT_LID_CHANGE; 2765 break; 2766 2767 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2768 ibev->event = IB_EVENT_PKEY_CHANGE; 2769 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2770 break; 2771 2772 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2773 ibev->event = IB_EVENT_GID_CHANGE; 2774 break; 2775 2776 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2777 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2778 break; 2779 default: 2780 return -EINVAL; 2781 } 2782 2783 return 0; 2784 } 2785 2786 static void mlx5_ib_handle_event(struct work_struct *_work) 2787 { 2788 struct mlx5_ib_event_work *work = 2789 container_of(_work, struct mlx5_ib_event_work, work); 2790 struct mlx5_ib_dev *ibdev; 2791 struct ib_event ibev; 2792 bool fatal = false; 2793 2794 if (work->is_slave) { 2795 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2796 if (!ibdev) 2797 goto out; 2798 } else { 2799 ibdev = work->dev; 2800 } 2801 2802 switch (work->event) { 2803 case MLX5_DEV_EVENT_SYS_ERROR: 2804 ibev.event = IB_EVENT_DEVICE_FATAL; 2805 mlx5_ib_handle_internal_error(ibdev); 2806 ibev.element.port_num = (u8)(unsigned long)work->param; 2807 fatal = true; 2808 break; 2809 case MLX5_EVENT_TYPE_PORT_CHANGE: 2810 if (handle_port_change(ibdev, work->param, &ibev)) 2811 goto out; 2812 break; 2813 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2814 handle_general_event(ibdev, work->param, &ibev); 2815 fallthrough; 2816 default: 2817 goto out; 2818 } 2819 2820 ibev.device = &ibdev->ib_dev; 2821 2822 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2823 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2824 goto out; 2825 } 2826 2827 if (ibdev->ib_active) 2828 ib_dispatch_event(&ibev); 2829 2830 if (fatal) 2831 ibdev->ib_active = false; 2832 out: 2833 kfree(work); 2834 } 2835 2836 static int mlx5_ib_event(struct notifier_block *nb, 2837 unsigned long event, void *param) 2838 { 2839 struct mlx5_ib_event_work *work; 2840 2841 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2842 if (!work) 2843 return NOTIFY_DONE; 2844 2845 INIT_WORK(&work->work, mlx5_ib_handle_event); 2846 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2847 work->is_slave = false; 2848 work->param = param; 2849 work->event = event; 2850 2851 queue_work(mlx5_ib_event_wq, &work->work); 2852 2853 return NOTIFY_OK; 2854 } 2855 2856 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2857 unsigned long event, void *param) 2858 { 2859 struct mlx5_ib_event_work *work; 2860 2861 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2862 if (!work) 2863 return NOTIFY_DONE; 2864 2865 INIT_WORK(&work->work, mlx5_ib_handle_event); 2866 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2867 work->is_slave = true; 2868 work->param = param; 2869 work->event = event; 2870 queue_work(mlx5_ib_event_wq, &work->work); 2871 2872 return NOTIFY_OK; 2873 } 2874 2875 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 2876 { 2877 struct mlx5_hca_vport_context vport_ctx; 2878 int err; 2879 2880 *num_plane = 0; 2881 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 2882 return 0; 2883 2884 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 2885 if (err) 2886 return err; 2887 2888 *num_plane = vport_ctx.num_plane; 2889 return 0; 2890 } 2891 2892 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2893 { 2894 struct mlx5_hca_vport_context vport_ctx; 2895 int err; 2896 int port; 2897 2898 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2899 return 0; 2900 2901 for (port = 1; port <= dev->num_ports; port++) { 2902 if (dev->num_plane) { 2903 dev->port_caps[port - 1].has_smi = false; 2904 continue; 2905 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 2906 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 2907 dev->port_caps[port - 1].has_smi = true; 2908 continue; 2909 } 2910 2911 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2912 &vport_ctx); 2913 if (err) { 2914 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2915 port, err); 2916 return err; 2917 } 2918 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2919 } 2920 2921 return 0; 2922 } 2923 2924 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2925 { 2926 unsigned int port; 2927 2928 rdma_for_each_port (&dev->ib_dev, port) 2929 mlx5_query_ext_port_caps(dev, port); 2930 } 2931 2932 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2933 { 2934 switch (umr_fence_cap) { 2935 case MLX5_CAP_UMR_FENCE_NONE: 2936 return MLX5_FENCE_MODE_NONE; 2937 case MLX5_CAP_UMR_FENCE_SMALL: 2938 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2939 default: 2940 return MLX5_FENCE_MODE_STRONG_ORDERING; 2941 } 2942 } 2943 2944 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 2945 { 2946 struct mlx5_ib_resources *devr = &dev->devr; 2947 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2948 struct ib_device *ibdev; 2949 struct ib_pd *pd; 2950 struct ib_cq *cq; 2951 int ret = 0; 2952 2953 2954 /* 2955 * devr->c0 is set once, never changed until device unload. 2956 * Avoid taking the mutex if initialization is already done. 2957 */ 2958 if (devr->c0) 2959 return 0; 2960 2961 mutex_lock(&devr->cq_lock); 2962 if (devr->c0) 2963 goto unlock; 2964 2965 ibdev = &dev->ib_dev; 2966 pd = ib_alloc_pd(ibdev, 0); 2967 if (IS_ERR(pd)) { 2968 ret = PTR_ERR(pd); 2969 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret); 2970 goto unlock; 2971 } 2972 2973 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2974 if (IS_ERR(cq)) { 2975 ret = PTR_ERR(cq); 2976 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret); 2977 ib_dealloc_pd(pd); 2978 goto unlock; 2979 } 2980 2981 devr->p0 = pd; 2982 devr->c0 = cq; 2983 2984 unlock: 2985 mutex_unlock(&devr->cq_lock); 2986 return ret; 2987 } 2988 2989 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 2990 { 2991 struct mlx5_ib_resources *devr = &dev->devr; 2992 struct ib_srq_init_attr attr; 2993 struct ib_srq *s0, *s1; 2994 int ret = 0; 2995 2996 /* 2997 * devr->s1 is set once, never changed until device unload. 2998 * Avoid taking the mutex if initialization is already done. 2999 */ 3000 if (devr->s1) 3001 return 0; 3002 3003 mutex_lock(&devr->srq_lock); 3004 if (devr->s1) 3005 goto unlock; 3006 3007 ret = mlx5_ib_dev_res_cq_init(dev); 3008 if (ret) 3009 goto unlock; 3010 3011 memset(&attr, 0, sizeof(attr)); 3012 attr.attr.max_sge = 1; 3013 attr.attr.max_wr = 1; 3014 attr.srq_type = IB_SRQT_XRC; 3015 attr.ext.cq = devr->c0; 3016 3017 s0 = ib_create_srq(devr->p0, &attr); 3018 if (IS_ERR(s0)) { 3019 ret = PTR_ERR(s0); 3020 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret); 3021 goto unlock; 3022 } 3023 3024 memset(&attr, 0, sizeof(attr)); 3025 attr.attr.max_sge = 1; 3026 attr.attr.max_wr = 1; 3027 attr.srq_type = IB_SRQT_BASIC; 3028 3029 s1 = ib_create_srq(devr->p0, &attr); 3030 if (IS_ERR(s1)) { 3031 ret = PTR_ERR(s1); 3032 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret); 3033 ib_destroy_srq(s0); 3034 } 3035 3036 devr->s0 = s0; 3037 devr->s1 = s1; 3038 3039 unlock: 3040 mutex_unlock(&devr->srq_lock); 3041 return ret; 3042 } 3043 3044 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3045 { 3046 struct mlx5_ib_resources *devr = &dev->devr; 3047 int ret; 3048 3049 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3050 return -EOPNOTSUPP; 3051 3052 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3053 if (ret) 3054 return ret; 3055 3056 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3057 if (ret) { 3058 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3059 return ret; 3060 } 3061 3062 mutex_init(&devr->cq_lock); 3063 mutex_init(&devr->srq_lock); 3064 3065 return 0; 3066 } 3067 3068 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3069 { 3070 struct mlx5_ib_resources *devr = &dev->devr; 3071 3072 /* After s0/s1 init, they are not unset during the device lifetime. */ 3073 if (devr->s1) { 3074 ib_destroy_srq(devr->s1); 3075 ib_destroy_srq(devr->s0); 3076 } 3077 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3078 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3079 /* After p0/c0 init, they are not unset during the device lifetime. */ 3080 if (devr->c0) { 3081 ib_destroy_cq(devr->c0); 3082 ib_dealloc_pd(devr->p0); 3083 } 3084 mutex_destroy(&devr->cq_lock); 3085 mutex_destroy(&devr->srq_lock); 3086 } 3087 3088 static int 3089 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3090 { 3091 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3092 struct mlx5_core_dev *mdev = dev->mdev; 3093 void *mkc; 3094 u32 mkey; 3095 u32 pdn; 3096 u32 *in; 3097 int err; 3098 3099 err = mlx5_core_alloc_pd(mdev, &pdn); 3100 if (err) 3101 return err; 3102 3103 in = kvzalloc(inlen, GFP_KERNEL); 3104 if (!in) { 3105 err = -ENOMEM; 3106 goto err; 3107 } 3108 3109 MLX5_SET(create_mkey_in, in, data_direct, 1); 3110 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3111 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3112 MLX5_SET(mkc, mkc, lw, 1); 3113 MLX5_SET(mkc, mkc, lr, 1); 3114 MLX5_SET(mkc, mkc, rw, 1); 3115 MLX5_SET(mkc, mkc, rr, 1); 3116 MLX5_SET(mkc, mkc, a, 1); 3117 MLX5_SET(mkc, mkc, pd, pdn); 3118 MLX5_SET(mkc, mkc, length64, 1); 3119 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3120 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3121 kvfree(in); 3122 if (err) 3123 goto err; 3124 3125 dev->ddr.mkey = mkey; 3126 dev->ddr.pdn = pdn; 3127 return 0; 3128 3129 err: 3130 mlx5_core_dealloc_pd(mdev, pdn); 3131 return err; 3132 } 3133 3134 static void 3135 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3136 { 3137 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3138 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3139 } 3140 3141 static u32 get_core_cap_flags(struct ib_device *ibdev, 3142 struct mlx5_hca_vport_context *rep) 3143 { 3144 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3145 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3146 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3147 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3148 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3149 u32 ret = 0; 3150 3151 if (rep->grh_required) 3152 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3153 3154 if (dev->num_plane) 3155 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3156 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3157 RDMA_CORE_CAP_AF_IB; 3158 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3159 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3160 3161 if (ll == IB_LINK_LAYER_INFINIBAND) 3162 return ret | RDMA_CORE_PORT_IBA_IB; 3163 3164 if (raw_support) 3165 ret |= RDMA_CORE_PORT_RAW_PACKET; 3166 3167 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3168 return ret; 3169 3170 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3171 return ret; 3172 3173 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3174 ret |= RDMA_CORE_PORT_IBA_ROCE; 3175 3176 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3177 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3178 3179 return ret; 3180 } 3181 3182 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3183 struct ib_port_immutable *immutable) 3184 { 3185 struct ib_port_attr attr; 3186 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3187 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3188 struct mlx5_hca_vport_context rep = {0}; 3189 int err; 3190 3191 err = ib_query_port(ibdev, port_num, &attr); 3192 if (err) 3193 return err; 3194 3195 if (ll == IB_LINK_LAYER_INFINIBAND) { 3196 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3197 port_num = smi_to_native_portnum(dev, port_num); 3198 3199 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3200 &rep); 3201 if (err) 3202 return err; 3203 } 3204 3205 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3206 immutable->gid_tbl_len = attr.gid_tbl_len; 3207 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3208 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3209 3210 return 0; 3211 } 3212 3213 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3214 struct ib_port_immutable *immutable) 3215 { 3216 struct ib_port_attr attr; 3217 int err; 3218 3219 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3220 3221 err = ib_query_port(ibdev, port_num, &attr); 3222 if (err) 3223 return err; 3224 3225 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3226 immutable->gid_tbl_len = attr.gid_tbl_len; 3227 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3228 3229 return 0; 3230 } 3231 3232 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3233 { 3234 struct mlx5_ib_dev *dev = 3235 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3236 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3237 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3238 fw_rev_sub(dev->mdev)); 3239 } 3240 3241 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3242 { 3243 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3244 lag_events); 3245 struct mlx5_core_dev *mdev = dev->mdev; 3246 struct ib_device *ibdev = &dev->ib_dev; 3247 struct net_device *old_ndev = NULL; 3248 struct mlx5_ib_port *port; 3249 struct net_device *ndev; 3250 u32 portnum = 0; 3251 int ret = 0; 3252 int i; 3253 3254 switch (event) { 3255 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3256 ndev = data; 3257 if (ndev) { 3258 if (!mlx5_lag_is_roce(mdev)) { 3259 // sriov lag 3260 for (i = 0; i < dev->num_ports; i++) { 3261 port = &dev->port[i]; 3262 if (port->rep && port->rep->vport == 3263 MLX5_VPORT_UPLINK) { 3264 portnum = i; 3265 break; 3266 } 3267 } 3268 } 3269 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3270 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3271 if (ret) 3272 goto out; 3273 3274 if (old_ndev) 3275 roce_del_all_netdev_gids(ibdev, portnum + 1, 3276 old_ndev); 3277 rdma_roce_rescan_port(ibdev, portnum + 1); 3278 } 3279 break; 3280 default: 3281 return NOTIFY_DONE; 3282 } 3283 3284 out: 3285 dev_put(old_ndev); 3286 return notifier_from_errno(ret); 3287 } 3288 3289 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3290 { 3291 dev->lag_events.notifier_call = lag_event; 3292 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3293 &dev->lag_events); 3294 } 3295 3296 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3297 { 3298 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3299 &dev->lag_events); 3300 } 3301 3302 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3303 { 3304 struct mlx5_core_dev *mdev = dev->mdev; 3305 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3306 MLX5_FLOW_NAMESPACE_LAG); 3307 struct mlx5_flow_table *ft; 3308 int err; 3309 3310 if (!ns || !mlx5_lag_is_active(mdev)) 3311 return 0; 3312 3313 err = mlx5_cmd_create_vport_lag(mdev); 3314 if (err) 3315 return err; 3316 3317 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3318 if (IS_ERR(ft)) { 3319 err = PTR_ERR(ft); 3320 goto err_destroy_vport_lag; 3321 } 3322 3323 mlx5e_lag_event_register(dev); 3324 dev->flow_db->lag_demux_ft = ft; 3325 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3326 dev->lag_active = true; 3327 return 0; 3328 3329 err_destroy_vport_lag: 3330 mlx5_cmd_destroy_vport_lag(mdev); 3331 return err; 3332 } 3333 3334 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3335 { 3336 struct mlx5_core_dev *mdev = dev->mdev; 3337 3338 if (dev->lag_active) { 3339 dev->lag_active = false; 3340 3341 mlx5e_lag_event_unregister(dev); 3342 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3343 dev->flow_db->lag_demux_ft = NULL; 3344 3345 mlx5_cmd_destroy_vport_lag(mdev); 3346 } 3347 } 3348 3349 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3350 struct net_device *netdev) 3351 { 3352 int err; 3353 3354 if (roce->tracking_netdev) 3355 return; 3356 roce->tracking_netdev = netdev; 3357 roce->nb.notifier_call = mlx5_netdev_event; 3358 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3359 WARN_ON(err); 3360 } 3361 3362 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3363 { 3364 if (!roce->tracking_netdev) 3365 return; 3366 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3367 &roce->nn); 3368 roce->tracking_netdev = NULL; 3369 } 3370 3371 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3372 unsigned long event, void *data) 3373 { 3374 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3375 struct net_device *netdev = data; 3376 3377 switch (event) { 3378 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3379 if (netdev) 3380 mlx5_netdev_notifier_register(roce, netdev); 3381 else 3382 mlx5_netdev_notifier_unregister(roce); 3383 break; 3384 default: 3385 return NOTIFY_DONE; 3386 } 3387 3388 return NOTIFY_OK; 3389 } 3390 3391 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3392 { 3393 struct mlx5_roce *roce = &dev->port[port_num].roce; 3394 3395 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3396 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3397 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3398 } 3399 3400 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3401 { 3402 struct mlx5_roce *roce = &dev->port[port_num].roce; 3403 3404 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3405 mlx5_netdev_notifier_unregister(roce); 3406 } 3407 3408 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3409 { 3410 int err; 3411 3412 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3413 err = mlx5_nic_vport_enable_roce(dev->mdev); 3414 if (err) 3415 return err; 3416 } 3417 3418 err = mlx5_eth_lag_init(dev); 3419 if (err) 3420 goto err_disable_roce; 3421 3422 return 0; 3423 3424 err_disable_roce: 3425 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3426 mlx5_nic_vport_disable_roce(dev->mdev); 3427 3428 return err; 3429 } 3430 3431 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3432 { 3433 mlx5_eth_lag_cleanup(dev); 3434 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3435 mlx5_nic_vport_disable_roce(dev->mdev); 3436 } 3437 3438 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3439 enum rdma_netdev_t type, 3440 struct rdma_netdev_alloc_params *params) 3441 { 3442 if (type != RDMA_NETDEV_IPOIB) 3443 return -EOPNOTSUPP; 3444 3445 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3446 } 3447 3448 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3449 size_t count, loff_t *pos) 3450 { 3451 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3452 char lbuf[20]; 3453 int len; 3454 3455 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3456 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3457 } 3458 3459 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3460 size_t count, loff_t *pos) 3461 { 3462 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3463 u32 timeout; 3464 u32 var; 3465 3466 if (kstrtouint_from_user(buf, count, 0, &var)) 3467 return -EFAULT; 3468 3469 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3470 1000); 3471 if (timeout != var) 3472 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3473 timeout); 3474 3475 delay_drop->timeout = timeout; 3476 3477 return count; 3478 } 3479 3480 static const struct file_operations fops_delay_drop_timeout = { 3481 .owner = THIS_MODULE, 3482 .open = simple_open, 3483 .write = delay_drop_timeout_write, 3484 .read = delay_drop_timeout_read, 3485 }; 3486 3487 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3488 struct mlx5_ib_multiport_info *mpi) 3489 { 3490 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3491 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3492 int comps; 3493 int err; 3494 int i; 3495 3496 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3497 3498 mlx5_core_mp_event_replay(ibdev->mdev, 3499 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3500 NULL); 3501 mlx5_core_mp_event_replay(mpi->mdev, 3502 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3503 NULL); 3504 3505 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3506 3507 spin_lock(&port->mp.mpi_lock); 3508 if (!mpi->ibdev) { 3509 spin_unlock(&port->mp.mpi_lock); 3510 return; 3511 } 3512 3513 mpi->ibdev = NULL; 3514 3515 spin_unlock(&port->mp.mpi_lock); 3516 if (mpi->mdev_events.notifier_call) 3517 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3518 mpi->mdev_events.notifier_call = NULL; 3519 mlx5_mdev_netdev_untrack(ibdev, port_num); 3520 spin_lock(&port->mp.mpi_lock); 3521 3522 comps = mpi->mdev_refcnt; 3523 if (comps) { 3524 mpi->unaffiliate = true; 3525 init_completion(&mpi->unref_comp); 3526 spin_unlock(&port->mp.mpi_lock); 3527 3528 for (i = 0; i < comps; i++) 3529 wait_for_completion(&mpi->unref_comp); 3530 3531 spin_lock(&port->mp.mpi_lock); 3532 mpi->unaffiliate = false; 3533 } 3534 3535 port->mp.mpi = NULL; 3536 3537 spin_unlock(&port->mp.mpi_lock); 3538 3539 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3540 3541 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3542 /* Log an error, still needed to cleanup the pointers and add 3543 * it back to the list. 3544 */ 3545 if (err) 3546 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3547 port_num + 1); 3548 3549 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3550 } 3551 3552 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3553 struct mlx5_ib_multiport_info *mpi) 3554 { 3555 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3556 u64 key; 3557 int err; 3558 3559 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3560 3561 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3562 if (ibdev->port[port_num].mp.mpi) { 3563 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3564 port_num + 1); 3565 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3566 return false; 3567 } 3568 3569 ibdev->port[port_num].mp.mpi = mpi; 3570 mpi->ibdev = ibdev; 3571 mpi->mdev_events.notifier_call = NULL; 3572 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3573 3574 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3575 if (err) 3576 goto unbind; 3577 3578 mlx5_mdev_netdev_track(ibdev, port_num); 3579 3580 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3581 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3582 3583 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3584 3585 key = mpi->mdev->priv.adev_idx; 3586 mlx5_core_mp_event_replay(mpi->mdev, 3587 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3588 &key); 3589 mlx5_core_mp_event_replay(ibdev->mdev, 3590 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3591 &key); 3592 3593 return true; 3594 3595 unbind: 3596 mlx5_ib_unbind_slave_port(ibdev, mpi); 3597 return false; 3598 } 3599 3600 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3601 { 3602 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3603 int ret; 3604 3605 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3606 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3607 return 0; 3608 3609 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3610 if (ret) 3611 return ret; 3612 3613 ret = mlx5_ib_create_data_direct_resources(dev); 3614 if (ret) 3615 return ret; 3616 3617 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3618 ret = mlx5_data_direct_ib_reg(dev, vuid); 3619 if (ret) 3620 mlx5_ib_free_data_direct_resources(dev); 3621 3622 return ret; 3623 } 3624 3625 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3626 { 3627 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3628 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3629 return; 3630 3631 mlx5_data_direct_ib_unreg(dev); 3632 mlx5_ib_free_data_direct_resources(dev); 3633 } 3634 3635 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3636 { 3637 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3638 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3639 port_num + 1); 3640 struct mlx5_ib_multiport_info *mpi; 3641 int err; 3642 u32 i; 3643 3644 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3645 return 0; 3646 3647 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3648 &dev->sys_image_guid); 3649 if (err) 3650 return err; 3651 3652 err = mlx5_nic_vport_enable_roce(dev->mdev); 3653 if (err) 3654 return err; 3655 3656 mutex_lock(&mlx5_ib_multiport_mutex); 3657 for (i = 0; i < dev->num_ports; i++) { 3658 bool bound = false; 3659 3660 /* build a stub multiport info struct for the native port. */ 3661 if (i == port_num) { 3662 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3663 if (!mpi) { 3664 mutex_unlock(&mlx5_ib_multiport_mutex); 3665 mlx5_nic_vport_disable_roce(dev->mdev); 3666 return -ENOMEM; 3667 } 3668 3669 mpi->is_master = true; 3670 mpi->mdev = dev->mdev; 3671 mpi->sys_image_guid = dev->sys_image_guid; 3672 dev->port[i].mp.mpi = mpi; 3673 mpi->ibdev = dev; 3674 mpi = NULL; 3675 continue; 3676 } 3677 3678 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3679 list) { 3680 if (dev->sys_image_guid == mpi->sys_image_guid && 3681 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 3682 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 3683 bound = mlx5_ib_bind_slave_port(dev, mpi); 3684 } 3685 3686 if (bound) { 3687 dev_dbg(mpi->mdev->device, 3688 "removing port from unaffiliated list.\n"); 3689 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3690 list_del(&mpi->list); 3691 break; 3692 } 3693 } 3694 if (!bound) 3695 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3696 i + 1); 3697 } 3698 3699 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3700 mutex_unlock(&mlx5_ib_multiport_mutex); 3701 return err; 3702 } 3703 3704 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3705 { 3706 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3707 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3708 port_num + 1); 3709 u32 i; 3710 3711 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3712 return; 3713 3714 mutex_lock(&mlx5_ib_multiport_mutex); 3715 for (i = 0; i < dev->num_ports; i++) { 3716 if (dev->port[i].mp.mpi) { 3717 /* Destroy the native port stub */ 3718 if (i == port_num) { 3719 kfree(dev->port[i].mp.mpi); 3720 dev->port[i].mp.mpi = NULL; 3721 } else { 3722 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3723 i + 1); 3724 list_add_tail(&dev->port[i].mp.mpi->list, 3725 &mlx5_ib_unaffiliated_port_list); 3726 mlx5_ib_unbind_slave_port(dev, 3727 dev->port[i].mp.mpi); 3728 } 3729 } 3730 } 3731 3732 mlx5_ib_dbg(dev, "removing from devlist\n"); 3733 list_del(&dev->ib_dev_list); 3734 mutex_unlock(&mlx5_ib_multiport_mutex); 3735 3736 mlx5_nic_vport_disable_roce(dev->mdev); 3737 } 3738 3739 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3740 enum rdma_remove_reason why, 3741 struct uverbs_attr_bundle *attrs) 3742 { 3743 struct mlx5_user_mmap_entry *obj = uobject->object; 3744 3745 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3746 return 0; 3747 } 3748 3749 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3750 struct mlx5_user_mmap_entry *entry, 3751 size_t length) 3752 { 3753 return rdma_user_mmap_entry_insert_range( 3754 &c->ibucontext, &entry->rdma_entry, length, 3755 (MLX5_IB_MMAP_OFFSET_START << 16), 3756 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3757 } 3758 3759 static struct mlx5_user_mmap_entry * 3760 alloc_var_entry(struct mlx5_ib_ucontext *c) 3761 { 3762 struct mlx5_user_mmap_entry *entry; 3763 struct mlx5_var_table *var_table; 3764 u32 page_idx; 3765 int err; 3766 3767 var_table = &to_mdev(c->ibucontext.device)->var_table; 3768 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3769 if (!entry) 3770 return ERR_PTR(-ENOMEM); 3771 3772 mutex_lock(&var_table->bitmap_lock); 3773 page_idx = find_first_zero_bit(var_table->bitmap, 3774 var_table->num_var_hw_entries); 3775 if (page_idx >= var_table->num_var_hw_entries) { 3776 err = -ENOSPC; 3777 mutex_unlock(&var_table->bitmap_lock); 3778 goto end; 3779 } 3780 3781 set_bit(page_idx, var_table->bitmap); 3782 mutex_unlock(&var_table->bitmap_lock); 3783 3784 entry->address = var_table->hw_start_addr + 3785 (page_idx * var_table->stride_size); 3786 entry->page_idx = page_idx; 3787 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3788 3789 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3790 var_table->stride_size); 3791 if (err) 3792 goto err_insert; 3793 3794 return entry; 3795 3796 err_insert: 3797 mutex_lock(&var_table->bitmap_lock); 3798 clear_bit(page_idx, var_table->bitmap); 3799 mutex_unlock(&var_table->bitmap_lock); 3800 end: 3801 kfree(entry); 3802 return ERR_PTR(err); 3803 } 3804 3805 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3806 struct uverbs_attr_bundle *attrs) 3807 { 3808 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3809 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3810 struct mlx5_ib_ucontext *c; 3811 struct mlx5_user_mmap_entry *entry; 3812 u64 mmap_offset; 3813 u32 length; 3814 int err; 3815 3816 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3817 if (IS_ERR(c)) 3818 return PTR_ERR(c); 3819 3820 entry = alloc_var_entry(c); 3821 if (IS_ERR(entry)) 3822 return PTR_ERR(entry); 3823 3824 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3825 length = entry->rdma_entry.npages * PAGE_SIZE; 3826 uobj->object = entry; 3827 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3828 3829 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3830 &mmap_offset, sizeof(mmap_offset)); 3831 if (err) 3832 return err; 3833 3834 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3835 &entry->page_idx, sizeof(entry->page_idx)); 3836 if (err) 3837 return err; 3838 3839 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3840 &length, sizeof(length)); 3841 return err; 3842 } 3843 3844 DECLARE_UVERBS_NAMED_METHOD( 3845 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3846 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3847 MLX5_IB_OBJECT_VAR, 3848 UVERBS_ACCESS_NEW, 3849 UA_MANDATORY), 3850 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3851 UVERBS_ATTR_TYPE(u32), 3852 UA_MANDATORY), 3853 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3854 UVERBS_ATTR_TYPE(u32), 3855 UA_MANDATORY), 3856 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3857 UVERBS_ATTR_TYPE(u64), 3858 UA_MANDATORY)); 3859 3860 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3861 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3862 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3863 MLX5_IB_OBJECT_VAR, 3864 UVERBS_ACCESS_DESTROY, 3865 UA_MANDATORY)); 3866 3867 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3868 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3869 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3870 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3871 3872 static bool var_is_supported(struct ib_device *device) 3873 { 3874 struct mlx5_ib_dev *dev = to_mdev(device); 3875 3876 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3877 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3878 } 3879 3880 static struct mlx5_user_mmap_entry * 3881 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3882 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3883 { 3884 struct mlx5_user_mmap_entry *entry; 3885 struct mlx5_ib_dev *dev; 3886 u32 uar_index; 3887 int err; 3888 3889 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3890 if (!entry) 3891 return ERR_PTR(-ENOMEM); 3892 3893 dev = to_mdev(c->ibucontext.device); 3894 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3895 if (err) 3896 goto end; 3897 3898 entry->page_idx = uar_index; 3899 entry->address = uar_index2paddress(dev, uar_index); 3900 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3901 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3902 else 3903 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3904 3905 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3906 if (err) 3907 goto err_insert; 3908 3909 return entry; 3910 3911 err_insert: 3912 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3913 end: 3914 kfree(entry); 3915 return ERR_PTR(err); 3916 } 3917 3918 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3919 struct uverbs_attr_bundle *attrs) 3920 { 3921 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3922 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3923 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3924 struct mlx5_ib_ucontext *c; 3925 struct mlx5_user_mmap_entry *entry; 3926 u64 mmap_offset; 3927 u32 length; 3928 int err; 3929 3930 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3931 if (IS_ERR(c)) 3932 return PTR_ERR(c); 3933 3934 err = uverbs_get_const(&alloc_type, attrs, 3935 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3936 if (err) 3937 return err; 3938 3939 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3940 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3941 return -EOPNOTSUPP; 3942 3943 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 3944 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3945 return -EOPNOTSUPP; 3946 3947 entry = alloc_uar_entry(c, alloc_type); 3948 if (IS_ERR(entry)) 3949 return PTR_ERR(entry); 3950 3951 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3952 length = entry->rdma_entry.npages * PAGE_SIZE; 3953 uobj->object = entry; 3954 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3955 3956 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3957 &mmap_offset, sizeof(mmap_offset)); 3958 if (err) 3959 return err; 3960 3961 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3962 &entry->page_idx, sizeof(entry->page_idx)); 3963 if (err) 3964 return err; 3965 3966 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3967 &length, sizeof(length)); 3968 return err; 3969 } 3970 3971 DECLARE_UVERBS_NAMED_METHOD( 3972 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3973 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3974 MLX5_IB_OBJECT_UAR, 3975 UVERBS_ACCESS_NEW, 3976 UA_MANDATORY), 3977 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3978 enum mlx5_ib_uapi_uar_alloc_type, 3979 UA_MANDATORY), 3980 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3981 UVERBS_ATTR_TYPE(u32), 3982 UA_MANDATORY), 3983 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3984 UVERBS_ATTR_TYPE(u32), 3985 UA_MANDATORY), 3986 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3987 UVERBS_ATTR_TYPE(u64), 3988 UA_MANDATORY)); 3989 3990 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3991 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3992 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3993 MLX5_IB_OBJECT_UAR, 3994 UVERBS_ACCESS_DESTROY, 3995 UA_MANDATORY)); 3996 3997 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3998 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3999 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4000 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4001 4002 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4003 mlx5_ib_query_context, 4004 UVERBS_OBJECT_DEVICE, 4005 UVERBS_METHOD_QUERY_CONTEXT, 4006 UVERBS_ATTR_PTR_OUT( 4007 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4008 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4009 dump_fill_mkey), 4010 UA_MANDATORY)); 4011 4012 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4013 mlx5_ib_reg_dmabuf_mr, 4014 UVERBS_OBJECT_MR, 4015 UVERBS_METHOD_REG_DMABUF_MR, 4016 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4017 enum mlx5_ib_uapi_reg_dmabuf_flags, 4018 UA_OPTIONAL)); 4019 4020 static const struct uapi_definition mlx5_ib_defs[] = { 4021 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4022 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4023 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4024 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4025 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4026 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4027 4028 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4029 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4030 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4031 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4032 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4033 {} 4034 }; 4035 4036 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4037 { 4038 mlx5_ib_data_direct_cleanup(dev); 4039 mlx5_ib_cleanup_multiport_master(dev); 4040 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4041 mutex_destroy(&dev->cap_mask_mutex); 4042 WARN_ON(!xa_empty(&dev->sig_mrs)); 4043 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4044 mlx5r_macsec_dealloc_gids(dev); 4045 } 4046 4047 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4048 { 4049 struct mlx5_core_dev *mdev = dev->mdev; 4050 int err, i; 4051 4052 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4053 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4054 dev->ib_dev.dev.parent = mdev->device; 4055 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4056 4057 for (i = 0; i < dev->num_ports; i++) { 4058 spin_lock_init(&dev->port[i].mp.mpi_lock); 4059 dev->port[i].roce.dev = dev; 4060 dev->port[i].roce.native_port_num = i + 1; 4061 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4062 } 4063 4064 err = mlx5r_cmd_query_special_mkeys(dev); 4065 if (err) 4066 return err; 4067 4068 err = mlx5r_macsec_init_gids_and_devlist(dev); 4069 if (err) 4070 return err; 4071 4072 err = mlx5_ib_init_multiport_master(dev); 4073 if (err) 4074 goto err; 4075 4076 err = set_has_smi_cap(dev); 4077 if (err) 4078 goto err_mp; 4079 4080 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4081 if (err) 4082 goto err_mp; 4083 4084 if (mlx5_use_mad_ifc(dev)) 4085 get_ext_port_caps(dev); 4086 4087 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4088 4089 mutex_init(&dev->cap_mask_mutex); 4090 mutex_init(&dev->data_direct_lock); 4091 INIT_LIST_HEAD(&dev->qp_list); 4092 spin_lock_init(&dev->reset_flow_resource_lock); 4093 xa_init(&dev->odp_mkeys); 4094 xa_init(&dev->sig_mrs); 4095 atomic_set(&dev->mkey_var, 0); 4096 4097 spin_lock_init(&dev->dm.lock); 4098 dev->dm.dev = mdev; 4099 err = mlx5_ib_data_direct_init(dev); 4100 if (err) 4101 goto err_mp; 4102 4103 return 0; 4104 err_mp: 4105 mlx5_ib_cleanup_multiport_master(dev); 4106 err: 4107 mlx5r_macsec_dealloc_gids(dev); 4108 return err; 4109 } 4110 4111 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4112 enum rdma_nl_dev_type type, 4113 const char *name); 4114 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4115 4116 static const struct ib_device_ops mlx5_ib_dev_ops = { 4117 .owner = THIS_MODULE, 4118 .driver_id = RDMA_DRIVER_MLX5, 4119 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4120 4121 .add_gid = mlx5_ib_add_gid, 4122 .add_sub_dev = mlx5_ib_add_sub_dev, 4123 .alloc_mr = mlx5_ib_alloc_mr, 4124 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4125 .alloc_pd = mlx5_ib_alloc_pd, 4126 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4127 .attach_mcast = mlx5_ib_mcg_attach, 4128 .check_mr_status = mlx5_ib_check_mr_status, 4129 .create_ah = mlx5_ib_create_ah, 4130 .create_cq = mlx5_ib_create_cq, 4131 .create_qp = mlx5_ib_create_qp, 4132 .create_srq = mlx5_ib_create_srq, 4133 .create_user_ah = mlx5_ib_create_ah, 4134 .dealloc_pd = mlx5_ib_dealloc_pd, 4135 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4136 .del_gid = mlx5_ib_del_gid, 4137 .del_sub_dev = mlx5_ib_del_sub_dev, 4138 .dereg_mr = mlx5_ib_dereg_mr, 4139 .destroy_ah = mlx5_ib_destroy_ah, 4140 .destroy_cq = mlx5_ib_destroy_cq, 4141 .destroy_qp = mlx5_ib_destroy_qp, 4142 .destroy_srq = mlx5_ib_destroy_srq, 4143 .detach_mcast = mlx5_ib_mcg_detach, 4144 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4145 .drain_rq = mlx5_ib_drain_rq, 4146 .drain_sq = mlx5_ib_drain_sq, 4147 .device_group = &mlx5_attr_group, 4148 .get_dev_fw_str = get_dev_fw_str, 4149 .get_dma_mr = mlx5_ib_get_dma_mr, 4150 .get_link_layer = mlx5_ib_port_link_layer, 4151 .map_mr_sg = mlx5_ib_map_mr_sg, 4152 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4153 .mmap = mlx5_ib_mmap, 4154 .mmap_free = mlx5_ib_mmap_free, 4155 .modify_cq = mlx5_ib_modify_cq, 4156 .modify_device = mlx5_ib_modify_device, 4157 .modify_port = mlx5_ib_modify_port, 4158 .modify_qp = mlx5_ib_modify_qp, 4159 .modify_srq = mlx5_ib_modify_srq, 4160 .poll_cq = mlx5_ib_poll_cq, 4161 .post_recv = mlx5_ib_post_recv_nodrain, 4162 .post_send = mlx5_ib_post_send_nodrain, 4163 .post_srq_recv = mlx5_ib_post_srq_recv, 4164 .process_mad = mlx5_ib_process_mad, 4165 .query_ah = mlx5_ib_query_ah, 4166 .query_device = mlx5_ib_query_device, 4167 .query_gid = mlx5_ib_query_gid, 4168 .query_pkey = mlx5_ib_query_pkey, 4169 .query_qp = mlx5_ib_query_qp, 4170 .query_srq = mlx5_ib_query_srq, 4171 .query_ucontext = mlx5_ib_query_ucontext, 4172 .reg_user_mr = mlx5_ib_reg_user_mr, 4173 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4174 .req_notify_cq = mlx5_ib_arm_cq, 4175 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4176 .resize_cq = mlx5_ib_resize_cq, 4177 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4178 4179 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4180 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4181 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4182 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4183 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4184 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4185 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4186 }; 4187 4188 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4189 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4190 }; 4191 4192 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4193 .get_vf_config = mlx5_ib_get_vf_config, 4194 .get_vf_guid = mlx5_ib_get_vf_guid, 4195 .get_vf_stats = mlx5_ib_get_vf_stats, 4196 .set_vf_guid = mlx5_ib_set_vf_guid, 4197 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4198 }; 4199 4200 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4201 .alloc_mw = mlx5_ib_alloc_mw, 4202 .dealloc_mw = mlx5_ib_dealloc_mw, 4203 4204 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4205 }; 4206 4207 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4208 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4209 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4210 4211 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4212 }; 4213 4214 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4215 { 4216 struct mlx5_core_dev *mdev = dev->mdev; 4217 struct mlx5_var_table *var_table = &dev->var_table; 4218 u8 log_doorbell_bar_size; 4219 u8 log_doorbell_stride; 4220 u64 bar_size; 4221 4222 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4223 log_doorbell_bar_size); 4224 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4225 log_doorbell_stride); 4226 var_table->hw_start_addr = dev->mdev->bar_addr + 4227 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4228 doorbell_bar_offset); 4229 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4230 var_table->stride_size = 1ULL << log_doorbell_stride; 4231 var_table->num_var_hw_entries = div_u64(bar_size, 4232 var_table->stride_size); 4233 mutex_init(&var_table->bitmap_lock); 4234 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4235 GFP_KERNEL); 4236 return (var_table->bitmap) ? 0 : -ENOMEM; 4237 } 4238 4239 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4240 { 4241 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4242 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4243 4244 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4245 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4246 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4247 } 4248 4249 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4250 { 4251 int ret; 4252 4253 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4254 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4255 if (ret) 4256 return ret; 4257 } 4258 4259 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4260 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4261 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4262 if (ret) 4263 goto remove_local; 4264 } 4265 4266 return 0; 4267 4268 remove_local: 4269 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4270 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4271 return ret; 4272 } 4273 4274 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4275 { 4276 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4277 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4278 mlx5_ib_cleanup_ucaps(dev); 4279 4280 bitmap_free(dev->var_table.bitmap); 4281 } 4282 4283 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4284 { 4285 struct mlx5_core_dev *mdev = dev->mdev; 4286 int err; 4287 4288 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4289 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4290 ib_set_device_ops(&dev->ib_dev, 4291 &mlx5_ib_dev_ipoib_enhanced_ops); 4292 4293 if (mlx5_core_is_pf(mdev)) 4294 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4295 4296 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4297 4298 if (MLX5_CAP_GEN(mdev, imaicl)) 4299 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4300 4301 if (MLX5_CAP_GEN(mdev, xrc)) 4302 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4303 4304 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4305 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4306 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4307 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4308 4309 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4310 4311 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4312 dev->ib_dev.driver_def = mlx5_ib_defs; 4313 4314 err = init_node_data(dev); 4315 if (err) 4316 return err; 4317 4318 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4319 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4320 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4321 mutex_init(&dev->lb.mutex); 4322 4323 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4324 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4325 err = mlx5_ib_init_var_table(dev); 4326 if (err) 4327 return err; 4328 } 4329 4330 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4331 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4332 err = mlx5_ib_init_ucaps(dev); 4333 if (err) 4334 return err; 4335 } 4336 4337 dev->ib_dev.use_cq_dim = true; 4338 4339 return 0; 4340 } 4341 4342 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4343 .get_port_immutable = mlx5_port_immutable, 4344 .query_port = mlx5_ib_query_port, 4345 }; 4346 4347 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4348 { 4349 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4350 return 0; 4351 } 4352 4353 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4354 .get_port_immutable = mlx5_port_rep_immutable, 4355 .query_port = mlx5_ib_rep_query_port, 4356 .query_pkey = mlx5_ib_rep_query_pkey, 4357 }; 4358 4359 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4360 { 4361 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4362 return 0; 4363 } 4364 4365 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4366 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4367 .create_wq = mlx5_ib_create_wq, 4368 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4369 .destroy_wq = mlx5_ib_destroy_wq, 4370 .modify_wq = mlx5_ib_modify_wq, 4371 4372 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4373 ib_rwq_ind_tbl), 4374 }; 4375 4376 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4377 { 4378 struct mlx5_core_dev *mdev = dev->mdev; 4379 enum rdma_link_layer ll; 4380 int port_type_cap; 4381 u32 port_num = 0; 4382 int err; 4383 4384 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4385 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4386 4387 if (ll == IB_LINK_LAYER_ETHERNET) { 4388 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4389 4390 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4391 4392 /* Register only for native ports */ 4393 mlx5_mdev_netdev_track(dev, port_num); 4394 4395 err = mlx5_enable_eth(dev); 4396 if (err) 4397 goto cleanup; 4398 } 4399 4400 return 0; 4401 cleanup: 4402 mlx5_mdev_netdev_untrack(dev, port_num); 4403 return err; 4404 } 4405 4406 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4407 { 4408 struct mlx5_core_dev *mdev = dev->mdev; 4409 enum rdma_link_layer ll; 4410 int port_type_cap; 4411 u32 port_num; 4412 4413 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4414 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4415 4416 if (ll == IB_LINK_LAYER_ETHERNET) { 4417 mlx5_disable_eth(dev); 4418 4419 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4420 mlx5_mdev_netdev_untrack(dev, port_num); 4421 } 4422 } 4423 4424 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4425 { 4426 mlx5_ib_init_cong_debugfs(dev, 4427 mlx5_core_native_port_num(dev->mdev) - 1); 4428 return 0; 4429 } 4430 4431 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4432 { 4433 mlx5_ib_cleanup_cong_debugfs(dev, 4434 mlx5_core_native_port_num(dev->mdev) - 1); 4435 } 4436 4437 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4438 { 4439 int err; 4440 4441 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4442 if (err) 4443 return err; 4444 4445 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4446 if (err) 4447 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4448 4449 return err; 4450 } 4451 4452 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4453 { 4454 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4455 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4456 } 4457 4458 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4459 { 4460 const char *name; 4461 4462 if (dev->sub_dev_name) { 4463 name = dev->sub_dev_name; 4464 ib_mark_name_assigned_by_user(&dev->ib_dev); 4465 } else if (!mlx5_lag_is_active(dev->mdev)) 4466 name = "mlx5_%d"; 4467 else 4468 name = "mlx5_bond_%d"; 4469 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4470 } 4471 4472 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4473 { 4474 mlx5_mkey_cache_cleanup(dev); 4475 mlx5r_umr_resource_cleanup(dev); 4476 mlx5r_umr_cleanup(dev); 4477 } 4478 4479 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4480 { 4481 ib_unregister_device(&dev->ib_dev); 4482 } 4483 4484 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4485 { 4486 int ret; 4487 4488 ret = mlx5r_umr_init(dev); 4489 if (ret) 4490 return ret; 4491 4492 ret = mlx5_mkey_cache_init(dev); 4493 if (ret) 4494 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4495 return ret; 4496 } 4497 4498 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4499 { 4500 struct dentry *root; 4501 4502 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4503 return 0; 4504 4505 mutex_init(&dev->delay_drop.lock); 4506 dev->delay_drop.dev = dev; 4507 dev->delay_drop.activate = false; 4508 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4509 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4510 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4511 atomic_set(&dev->delay_drop.events_cnt, 0); 4512 4513 if (!mlx5_debugfs_root) 4514 return 0; 4515 4516 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4517 dev->delay_drop.dir_debugfs = root; 4518 4519 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4520 &dev->delay_drop.events_cnt); 4521 debugfs_create_atomic_t("num_rqs", 0400, root, 4522 &dev->delay_drop.rqs_cnt); 4523 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4524 &fops_delay_drop_timeout); 4525 return 0; 4526 } 4527 4528 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4529 { 4530 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4531 return; 4532 4533 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4534 if (!dev->delay_drop.dir_debugfs) 4535 return; 4536 4537 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4538 dev->delay_drop.dir_debugfs = NULL; 4539 } 4540 4541 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4542 { 4543 struct mlx5_ib_resources *devr = &dev->devr; 4544 int port; 4545 4546 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4547 INIT_WORK(&devr->ports[port].pkey_change_work, 4548 pkey_change_handler); 4549 4550 dev->mdev_events.notifier_call = mlx5_ib_event; 4551 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4552 4553 mlx5r_macsec_event_register(dev); 4554 4555 return 0; 4556 } 4557 4558 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4559 { 4560 struct mlx5_ib_resources *devr = &dev->devr; 4561 int port; 4562 4563 mlx5r_macsec_event_unregister(dev); 4564 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4565 4566 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4567 cancel_work_sync(&devr->ports[port].pkey_change_work); 4568 } 4569 4570 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4571 struct mlx5_data_direct_dev *dev) 4572 { 4573 mutex_lock(&ibdev->data_direct_lock); 4574 ibdev->data_direct_dev = dev; 4575 mutex_unlock(&ibdev->data_direct_lock); 4576 } 4577 4578 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4579 { 4580 mutex_lock(&ibdev->data_direct_lock); 4581 mlx5_ib_revoke_data_direct_mrs(ibdev); 4582 ibdev->data_direct_dev = NULL; 4583 mutex_unlock(&ibdev->data_direct_lock); 4584 } 4585 4586 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4587 const struct mlx5_ib_profile *profile, 4588 int stage) 4589 { 4590 dev->ib_active = false; 4591 4592 /* Number of stages to cleanup */ 4593 while (stage) { 4594 stage--; 4595 if (profile->stage[stage].cleanup) 4596 profile->stage[stage].cleanup(dev); 4597 } 4598 4599 kfree(dev->port); 4600 ib_dealloc_device(&dev->ib_dev); 4601 } 4602 4603 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4604 const struct mlx5_ib_profile *profile) 4605 { 4606 int err; 4607 int i; 4608 4609 dev->profile = profile; 4610 4611 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4612 if (profile->stage[i].init) { 4613 err = profile->stage[i].init(dev); 4614 if (err) 4615 goto err_out; 4616 } 4617 } 4618 4619 dev->ib_active = true; 4620 return 0; 4621 4622 err_out: 4623 /* Clean up stages which were initialized */ 4624 while (i) { 4625 i--; 4626 if (profile->stage[i].cleanup) 4627 profile->stage[i].cleanup(dev); 4628 } 4629 return -ENOMEM; 4630 } 4631 4632 static const struct mlx5_ib_profile pf_profile = { 4633 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4634 mlx5_ib_stage_init_init, 4635 mlx5_ib_stage_init_cleanup), 4636 STAGE_CREATE(MLX5_IB_STAGE_FS, 4637 mlx5_ib_fs_init, 4638 mlx5_ib_fs_cleanup), 4639 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4640 mlx5_ib_stage_caps_init, 4641 mlx5_ib_stage_caps_cleanup), 4642 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4643 mlx5_ib_stage_non_default_cb, 4644 NULL), 4645 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4646 mlx5_ib_roce_init, 4647 mlx5_ib_roce_cleanup), 4648 STAGE_CREATE(MLX5_IB_STAGE_QP, 4649 mlx5_init_qp_table, 4650 mlx5_cleanup_qp_table), 4651 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4652 mlx5_init_srq_table, 4653 mlx5_cleanup_srq_table), 4654 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4655 mlx5_ib_dev_res_init, 4656 mlx5_ib_dev_res_cleanup), 4657 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4658 mlx5_ib_odp_init_one, 4659 mlx5_ib_odp_cleanup_one), 4660 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4661 mlx5_ib_counters_init, 4662 mlx5_ib_counters_cleanup), 4663 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4664 mlx5_ib_stage_cong_debugfs_init, 4665 mlx5_ib_stage_cong_debugfs_cleanup), 4666 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4667 mlx5_ib_stage_bfrag_init, 4668 mlx5_ib_stage_bfrag_cleanup), 4669 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4670 NULL, 4671 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4672 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4673 mlx5_ib_devx_init, 4674 mlx5_ib_devx_cleanup), 4675 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4676 mlx5_ib_stage_ib_reg_init, 4677 mlx5_ib_stage_ib_reg_cleanup), 4678 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4679 mlx5_ib_stage_dev_notifier_init, 4680 mlx5_ib_stage_dev_notifier_cleanup), 4681 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4682 mlx5_ib_stage_post_ib_reg_umr_init, 4683 NULL), 4684 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4685 mlx5_ib_stage_delay_drop_init, 4686 mlx5_ib_stage_delay_drop_cleanup), 4687 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4688 mlx5_ib_restrack_init, 4689 NULL), 4690 }; 4691 4692 const struct mlx5_ib_profile raw_eth_profile = { 4693 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4694 mlx5_ib_stage_init_init, 4695 mlx5_ib_stage_init_cleanup), 4696 STAGE_CREATE(MLX5_IB_STAGE_FS, 4697 mlx5_ib_fs_init, 4698 mlx5_ib_fs_cleanup), 4699 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4700 mlx5_ib_stage_caps_init, 4701 mlx5_ib_stage_caps_cleanup), 4702 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4703 mlx5_ib_stage_raw_eth_non_default_cb, 4704 NULL), 4705 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4706 mlx5_ib_roce_init, 4707 mlx5_ib_roce_cleanup), 4708 STAGE_CREATE(MLX5_IB_STAGE_QP, 4709 mlx5_init_qp_table, 4710 mlx5_cleanup_qp_table), 4711 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4712 mlx5_init_srq_table, 4713 mlx5_cleanup_srq_table), 4714 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4715 mlx5_ib_dev_res_init, 4716 mlx5_ib_dev_res_cleanup), 4717 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4718 mlx5_ib_counters_init, 4719 mlx5_ib_counters_cleanup), 4720 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4721 mlx5_ib_stage_cong_debugfs_init, 4722 mlx5_ib_stage_cong_debugfs_cleanup), 4723 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4724 mlx5_ib_stage_bfrag_init, 4725 mlx5_ib_stage_bfrag_cleanup), 4726 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4727 NULL, 4728 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4729 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4730 mlx5_ib_devx_init, 4731 mlx5_ib_devx_cleanup), 4732 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4733 mlx5_ib_stage_ib_reg_init, 4734 mlx5_ib_stage_ib_reg_cleanup), 4735 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4736 mlx5_ib_stage_dev_notifier_init, 4737 mlx5_ib_stage_dev_notifier_cleanup), 4738 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4739 mlx5_ib_stage_post_ib_reg_umr_init, 4740 NULL), 4741 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4742 mlx5_ib_stage_delay_drop_init, 4743 mlx5_ib_stage_delay_drop_cleanup), 4744 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4745 mlx5_ib_restrack_init, 4746 NULL), 4747 }; 4748 4749 static const struct mlx5_ib_profile plane_profile = { 4750 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4751 mlx5_ib_stage_init_init, 4752 mlx5_ib_stage_init_cleanup), 4753 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4754 mlx5_ib_stage_caps_init, 4755 mlx5_ib_stage_caps_cleanup), 4756 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4757 mlx5_ib_stage_non_default_cb, 4758 NULL), 4759 STAGE_CREATE(MLX5_IB_STAGE_QP, 4760 mlx5_init_qp_table, 4761 mlx5_cleanup_qp_table), 4762 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4763 mlx5_init_srq_table, 4764 mlx5_cleanup_srq_table), 4765 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4766 mlx5_ib_dev_res_init, 4767 mlx5_ib_dev_res_cleanup), 4768 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4769 mlx5_ib_stage_bfrag_init, 4770 mlx5_ib_stage_bfrag_cleanup), 4771 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4772 mlx5_ib_stage_ib_reg_init, 4773 mlx5_ib_stage_ib_reg_cleanup), 4774 }; 4775 4776 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4777 enum rdma_nl_dev_type type, 4778 const char *name) 4779 { 4780 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 4781 enum rdma_link_layer ll; 4782 int ret; 4783 4784 if (mparent->smi_dev) 4785 return ERR_PTR(-EEXIST); 4786 4787 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 4788 port_type)); 4789 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 4790 ll != IB_LINK_LAYER_INFINIBAND || 4791 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 4792 return ERR_PTR(-EOPNOTSUPP); 4793 4794 mplane = ib_alloc_device(mlx5_ib_dev, ib_dev); 4795 if (!mplane) 4796 return ERR_PTR(-ENOMEM); 4797 4798 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 4799 sizeof(*mplane->port), GFP_KERNEL); 4800 if (!mplane->port) { 4801 ret = -ENOMEM; 4802 goto fail_kcalloc; 4803 } 4804 4805 mplane->ib_dev.type = type; 4806 mplane->mdev = mparent->mdev; 4807 mplane->num_ports = mparent->num_plane; 4808 mplane->sub_dev_name = name; 4809 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 4810 4811 ret = __mlx5_ib_add(mplane, &plane_profile); 4812 if (ret) 4813 goto fail_ib_add; 4814 4815 mparent->smi_dev = mplane; 4816 return &mplane->ib_dev; 4817 4818 fail_ib_add: 4819 kfree(mplane->port); 4820 fail_kcalloc: 4821 ib_dealloc_device(&mplane->ib_dev); 4822 return ERR_PTR(ret); 4823 } 4824 4825 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 4826 { 4827 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 4828 4829 to_mdev(sub_dev->parent)->smi_dev = NULL; 4830 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 4831 } 4832 4833 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4834 const struct auxiliary_device_id *id) 4835 { 4836 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4837 struct mlx5_core_dev *mdev = idev->mdev; 4838 struct mlx5_ib_multiport_info *mpi; 4839 struct mlx5_ib_dev *dev; 4840 bool bound = false; 4841 int err; 4842 4843 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4844 if (!mpi) 4845 return -ENOMEM; 4846 4847 mpi->mdev = mdev; 4848 err = mlx5_query_nic_vport_system_image_guid(mdev, 4849 &mpi->sys_image_guid); 4850 if (err) { 4851 kfree(mpi); 4852 return err; 4853 } 4854 4855 mutex_lock(&mlx5_ib_multiport_mutex); 4856 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4857 if (dev->sys_image_guid == mpi->sys_image_guid && 4858 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 4859 bound = mlx5_ib_bind_slave_port(dev, mpi); 4860 4861 if (bound) { 4862 rdma_roce_rescan_device(&dev->ib_dev); 4863 mpi->ibdev->ib_active = true; 4864 break; 4865 } 4866 } 4867 4868 if (!bound) { 4869 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4870 dev_dbg(mdev->device, 4871 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4872 } 4873 mutex_unlock(&mlx5_ib_multiport_mutex); 4874 4875 auxiliary_set_drvdata(adev, mpi); 4876 return 0; 4877 } 4878 4879 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4880 { 4881 struct mlx5_ib_multiport_info *mpi; 4882 4883 mpi = auxiliary_get_drvdata(adev); 4884 mutex_lock(&mlx5_ib_multiport_mutex); 4885 if (mpi->ibdev) 4886 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4887 else 4888 list_del(&mpi->list); 4889 mutex_unlock(&mlx5_ib_multiport_mutex); 4890 kfree(mpi); 4891 } 4892 4893 static int mlx5r_probe(struct auxiliary_device *adev, 4894 const struct auxiliary_device_id *id) 4895 { 4896 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4897 struct mlx5_core_dev *mdev = idev->mdev; 4898 const struct mlx5_ib_profile *profile; 4899 int port_type_cap, num_ports, ret; 4900 enum rdma_link_layer ll; 4901 struct mlx5_ib_dev *dev; 4902 4903 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4904 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4905 4906 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4907 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4908 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4909 if (!dev) 4910 return -ENOMEM; 4911 4912 if (ll == IB_LINK_LAYER_INFINIBAND) { 4913 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 4914 if (ret) 4915 goto fail; 4916 } 4917 4918 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4919 GFP_KERNEL); 4920 if (!dev->port) { 4921 ret = -ENOMEM; 4922 goto fail; 4923 } 4924 4925 dev->mdev = mdev; 4926 dev->num_ports = num_ports; 4927 dev->ib_dev.phys_port_cnt = num_ports; 4928 4929 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4930 profile = &raw_eth_profile; 4931 else 4932 profile = &pf_profile; 4933 4934 ret = __mlx5_ib_add(dev, profile); 4935 if (ret) 4936 goto fail_ib_add; 4937 4938 auxiliary_set_drvdata(adev, dev); 4939 return 0; 4940 4941 fail_ib_add: 4942 kfree(dev->port); 4943 fail: 4944 ib_dealloc_device(&dev->ib_dev); 4945 return ret; 4946 } 4947 4948 static void mlx5r_remove(struct auxiliary_device *adev) 4949 { 4950 struct mlx5_ib_dev *dev; 4951 4952 dev = auxiliary_get_drvdata(adev); 4953 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4954 } 4955 4956 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4957 { .name = MLX5_ADEV_NAME ".multiport", }, 4958 {}, 4959 }; 4960 4961 static const struct auxiliary_device_id mlx5r_id_table[] = { 4962 { .name = MLX5_ADEV_NAME ".rdma", }, 4963 {}, 4964 }; 4965 4966 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4967 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4968 4969 static struct auxiliary_driver mlx5r_mp_driver = { 4970 .name = "multiport", 4971 .probe = mlx5r_mp_probe, 4972 .remove = mlx5r_mp_remove, 4973 .id_table = mlx5r_mp_id_table, 4974 }; 4975 4976 static struct auxiliary_driver mlx5r_driver = { 4977 .name = "rdma", 4978 .probe = mlx5r_probe, 4979 .remove = mlx5r_remove, 4980 .id_table = mlx5r_id_table, 4981 }; 4982 4983 static int __init mlx5_ib_init(void) 4984 { 4985 int ret; 4986 4987 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4988 if (!xlt_emergency_page) 4989 return -ENOMEM; 4990 4991 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4992 if (!mlx5_ib_event_wq) { 4993 free_page((unsigned long)xlt_emergency_page); 4994 return -ENOMEM; 4995 } 4996 4997 ret = mlx5_ib_qp_event_init(); 4998 if (ret) 4999 goto qp_event_err; 5000 5001 mlx5_ib_odp_init(); 5002 ret = mlx5r_rep_init(); 5003 if (ret) 5004 goto rep_err; 5005 ret = mlx5_data_direct_driver_register(); 5006 if (ret) 5007 goto dd_err; 5008 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5009 if (ret) 5010 goto mp_err; 5011 ret = auxiliary_driver_register(&mlx5r_driver); 5012 if (ret) 5013 goto drv_err; 5014 5015 return 0; 5016 5017 drv_err: 5018 auxiliary_driver_unregister(&mlx5r_mp_driver); 5019 mp_err: 5020 mlx5_data_direct_driver_unregister(); 5021 dd_err: 5022 mlx5r_rep_cleanup(); 5023 rep_err: 5024 mlx5_ib_qp_event_cleanup(); 5025 qp_event_err: 5026 destroy_workqueue(mlx5_ib_event_wq); 5027 free_page((unsigned long)xlt_emergency_page); 5028 return ret; 5029 } 5030 5031 static void __exit mlx5_ib_cleanup(void) 5032 { 5033 mlx5_data_direct_driver_unregister(); 5034 auxiliary_driver_unregister(&mlx5r_driver); 5035 auxiliary_driver_unregister(&mlx5r_mp_driver); 5036 mlx5r_rep_cleanup(); 5037 5038 mlx5_ib_qp_event_cleanup(); 5039 destroy_workqueue(mlx5_ib_event_wq); 5040 free_page((unsigned long)xlt_emergency_page); 5041 } 5042 5043 module_init(mlx5_ib_init); 5044 module_exit(mlx5_ib_cleanup); 5045