1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. 4 */ 5 6 #include <rdma/ib_user_verbs.h> 7 #include <rdma/ib_verbs.h> 8 #include <rdma/uverbs_types.h> 9 #include <rdma/uverbs_ioctl.h> 10 #include <rdma/mlx5_user_ioctl_cmds.h> 11 #include <rdma/mlx5_user_ioctl_verbs.h> 12 #include <rdma/ib_umem.h> 13 #include <rdma/uverbs_std_types.h> 14 #include <linux/mlx5/driver.h> 15 #include <linux/mlx5/fs.h> 16 #include <rdma/ib_ucaps.h> 17 #include "mlx5_ib.h" 18 #include "devx.h" 19 #include "qp.h" 20 #include <linux/xarray.h> 21 22 #define UVERBS_MODULE_NAME mlx5_ib 23 #include <rdma/uverbs_named_ioctl.h> 24 25 static void dispatch_event_fd(struct list_head *fd_list, const void *data); 26 27 enum devx_obj_flags { 28 DEVX_OBJ_FLAGS_INDIRECT_MKEY = 1 << 0, 29 DEVX_OBJ_FLAGS_DCT = 1 << 1, 30 DEVX_OBJ_FLAGS_CQ = 1 << 2, 31 DEVX_OBJ_FLAGS_HW_FREED = 1 << 3, 32 }; 33 34 #define MAX_ASYNC_CMDS 8 35 36 struct mlx5_async_cmd { 37 struct ib_uobject *uobject; 38 void *in; 39 int in_size; 40 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 41 int err; 42 struct mlx5_async_work cb_work; 43 struct completion comp; 44 }; 45 46 struct devx_async_data { 47 struct mlx5_ib_dev *mdev; 48 struct list_head list; 49 struct devx_async_cmd_event_file *ev_file; 50 struct mlx5_async_work cb_work; 51 u16 cmd_out_len; 52 /* must be last field in this structure */ 53 struct mlx5_ib_uapi_devx_async_cmd_hdr hdr; 54 }; 55 56 struct devx_async_event_data { 57 struct list_head list; /* headed in ev_file->event_list */ 58 struct mlx5_ib_uapi_devx_async_event_hdr hdr; 59 }; 60 61 /* first level XA value data structure */ 62 struct devx_event { 63 struct xarray object_ids; /* second XA level, Key = object id */ 64 struct list_head unaffiliated_list; 65 }; 66 67 /* second level XA value data structure */ 68 struct devx_obj_event { 69 struct rcu_head rcu; 70 struct list_head obj_sub_list; 71 }; 72 73 struct devx_event_subscription { 74 struct list_head file_list; /* headed in ev_file-> 75 * subscribed_events_list 76 */ 77 struct list_head xa_list; /* headed in devx_event->unaffiliated_list or 78 * devx_obj_event->obj_sub_list 79 */ 80 struct list_head obj_list; /* headed in devx_object */ 81 struct list_head event_list; /* headed in ev_file->event_list or in 82 * temp list via subscription 83 */ 84 85 u8 is_cleaned:1; 86 u32 xa_key_level1; 87 u32 xa_key_level2; 88 struct rcu_head rcu; 89 u64 cookie; 90 struct devx_async_event_file *ev_file; 91 struct eventfd_ctx *eventfd; 92 }; 93 94 struct devx_async_event_file { 95 struct ib_uobject uobj; 96 /* Head of events that are subscribed to this FD */ 97 struct list_head subscribed_events_list; 98 spinlock_t lock; 99 wait_queue_head_t poll_wait; 100 struct list_head event_list; 101 struct mlx5_ib_dev *dev; 102 u8 omit_data:1; 103 u8 is_overflow_err:1; 104 u8 is_destroyed:1; 105 }; 106 107 struct devx_umem { 108 struct mlx5_core_dev *mdev; 109 struct ib_umem *umem; 110 u32 dinlen; 111 u32 dinbox[MLX5_ST_SZ_DW(destroy_umem_in)]; 112 }; 113 114 struct devx_umem_reg_cmd { 115 void *in; 116 u32 inlen; 117 u32 out[MLX5_ST_SZ_DW(create_umem_out)]; 118 }; 119 120 static struct mlx5_ib_ucontext * 121 devx_ufile2uctx(const struct uverbs_attr_bundle *attrs) 122 { 123 return to_mucontext(ib_uverbs_get_ucontext(attrs)); 124 } 125 126 static int set_uctx_ucaps(struct mlx5_ib_dev *dev, u64 req_ucaps, u32 *cap) 127 { 128 if (UCAP_ENABLED(req_ucaps, RDMA_UCAP_MLX5_CTRL_LOCAL)) { 129 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 130 *cap |= MLX5_UCTX_CAP_RDMA_CTRL; 131 else 132 return -EOPNOTSUPP; 133 } 134 135 if (UCAP_ENABLED(req_ucaps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA)) { 136 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 137 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 138 *cap |= MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA; 139 else 140 return -EOPNOTSUPP; 141 } 142 143 return 0; 144 } 145 146 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user, u64 req_ucaps) 147 { 148 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {}; 149 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; 150 void *uctx; 151 int err; 152 u16 uid; 153 u32 cap = 0; 154 155 /* 0 means not supported */ 156 if (!MLX5_CAP_GEN(dev->mdev, log_max_uctx)) 157 return -EINVAL; 158 159 uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx); 160 if (is_user && 161 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RAW_TX) && 162 rdma_dev_has_raw_cap(&dev->ib_dev)) 163 cap |= MLX5_UCTX_CAP_RAW_TX; 164 if (is_user && 165 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 166 MLX5_UCTX_CAP_INTERNAL_DEV_RES) && 167 capable(CAP_SYS_RAWIO)) 168 cap |= MLX5_UCTX_CAP_INTERNAL_DEV_RES; 169 170 if (req_ucaps) { 171 err = set_uctx_ucaps(dev, req_ucaps, &cap); 172 if (err) 173 return err; 174 } 175 176 MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX); 177 MLX5_SET(uctx, uctx, cap, cap); 178 179 err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 180 if (err) 181 return err; 182 183 uid = MLX5_GET(create_uctx_out, out, uid); 184 return uid; 185 } 186 187 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) 188 { 189 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; 190 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {}; 191 192 MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX); 193 MLX5_SET(destroy_uctx_in, in, uid, uid); 194 195 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 196 } 197 198 static bool is_legacy_unaffiliated_event_num(u16 event_num) 199 { 200 switch (event_num) { 201 case MLX5_EVENT_TYPE_PORT_CHANGE: 202 return true; 203 default: 204 return false; 205 } 206 } 207 208 static bool is_legacy_obj_event_num(u16 event_num) 209 { 210 switch (event_num) { 211 case MLX5_EVENT_TYPE_PATH_MIG: 212 case MLX5_EVENT_TYPE_COMM_EST: 213 case MLX5_EVENT_TYPE_SQ_DRAINED: 214 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 215 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 216 case MLX5_EVENT_TYPE_CQ_ERROR: 217 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 218 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 219 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 220 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 221 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 222 case MLX5_EVENT_TYPE_DCT_DRAINED: 223 case MLX5_EVENT_TYPE_COMP: 224 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 225 case MLX5_EVENT_TYPE_XRQ_ERROR: 226 return true; 227 default: 228 return false; 229 } 230 } 231 232 static u16 get_legacy_obj_type(u16 opcode) 233 { 234 switch (opcode) { 235 case MLX5_CMD_OP_CREATE_RQ: 236 case MLX5_CMD_OP_CREATE_RMP: 237 return MLX5_EVENT_QUEUE_TYPE_RQ; 238 case MLX5_CMD_OP_CREATE_QP: 239 return MLX5_EVENT_QUEUE_TYPE_QP; 240 case MLX5_CMD_OP_CREATE_SQ: 241 return MLX5_EVENT_QUEUE_TYPE_SQ; 242 case MLX5_CMD_OP_CREATE_DCT: 243 return MLX5_EVENT_QUEUE_TYPE_DCT; 244 default: 245 return 0; 246 } 247 } 248 249 static u16 get_dec_obj_type(struct devx_obj *obj, u16 event_num) 250 { 251 u16 opcode; 252 253 opcode = (obj->obj_id >> 32) & 0xffff; 254 255 if (is_legacy_obj_event_num(event_num)) 256 return get_legacy_obj_type(opcode); 257 258 switch (opcode) { 259 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 260 return (obj->obj_id >> 48); 261 case MLX5_CMD_OP_CREATE_RQ: 262 return MLX5_OBJ_TYPE_RQ; 263 case MLX5_CMD_OP_CREATE_QP: 264 return MLX5_OBJ_TYPE_QP; 265 case MLX5_CMD_OP_CREATE_SQ: 266 return MLX5_OBJ_TYPE_SQ; 267 case MLX5_CMD_OP_CREATE_DCT: 268 return MLX5_OBJ_TYPE_DCT; 269 case MLX5_CMD_OP_CREATE_TIR: 270 return MLX5_OBJ_TYPE_TIR; 271 case MLX5_CMD_OP_CREATE_TIS: 272 return MLX5_OBJ_TYPE_TIS; 273 case MLX5_CMD_OP_CREATE_PSV: 274 return MLX5_OBJ_TYPE_PSV; 275 case MLX5_OBJ_TYPE_MKEY: 276 return MLX5_OBJ_TYPE_MKEY; 277 case MLX5_CMD_OP_CREATE_RMP: 278 return MLX5_OBJ_TYPE_RMP; 279 case MLX5_CMD_OP_CREATE_XRC_SRQ: 280 return MLX5_OBJ_TYPE_XRC_SRQ; 281 case MLX5_CMD_OP_CREATE_XRQ: 282 return MLX5_OBJ_TYPE_XRQ; 283 case MLX5_CMD_OP_CREATE_RQT: 284 return MLX5_OBJ_TYPE_RQT; 285 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 286 return MLX5_OBJ_TYPE_FLOW_COUNTER; 287 case MLX5_CMD_OP_CREATE_CQ: 288 return MLX5_OBJ_TYPE_CQ; 289 default: 290 return 0; 291 } 292 } 293 294 static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe) 295 { 296 switch (event_type) { 297 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 298 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 299 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 300 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 301 case MLX5_EVENT_TYPE_PATH_MIG: 302 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 303 case MLX5_EVENT_TYPE_COMM_EST: 304 case MLX5_EVENT_TYPE_SQ_DRAINED: 305 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 306 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 307 return eqe->data.qp_srq.type; 308 case MLX5_EVENT_TYPE_CQ_ERROR: 309 case MLX5_EVENT_TYPE_XRQ_ERROR: 310 return 0; 311 case MLX5_EVENT_TYPE_DCT_DRAINED: 312 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 313 return MLX5_EVENT_QUEUE_TYPE_DCT; 314 default: 315 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type); 316 } 317 } 318 319 static u32 get_dec_obj_id(u64 obj_id) 320 { 321 return (obj_id & 0xffffffff); 322 } 323 324 /* 325 * As the obj_id in the firmware is not globally unique the object type 326 * must be considered upon checking for a valid object id. 327 * For that the opcode of the creator command is encoded as part of the obj_id. 328 */ 329 static u64 get_enc_obj_id(u32 opcode, u32 obj_id) 330 { 331 return ((u64)opcode << 32) | obj_id; 332 } 333 334 static u32 devx_get_created_obj_id(const void *in, const void *out, u16 opcode) 335 { 336 switch (opcode) { 337 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 338 return MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 339 case MLX5_CMD_OP_CREATE_UMEM: 340 return MLX5_GET(create_umem_out, out, umem_id); 341 case MLX5_CMD_OP_CREATE_MKEY: 342 return MLX5_GET(create_mkey_out, out, mkey_index); 343 case MLX5_CMD_OP_CREATE_CQ: 344 return MLX5_GET(create_cq_out, out, cqn); 345 case MLX5_CMD_OP_ALLOC_PD: 346 return MLX5_GET(alloc_pd_out, out, pd); 347 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 348 return MLX5_GET(alloc_transport_domain_out, out, 349 transport_domain); 350 case MLX5_CMD_OP_CREATE_RMP: 351 return MLX5_GET(create_rmp_out, out, rmpn); 352 case MLX5_CMD_OP_CREATE_SQ: 353 return MLX5_GET(create_sq_out, out, sqn); 354 case MLX5_CMD_OP_CREATE_RQ: 355 return MLX5_GET(create_rq_out, out, rqn); 356 case MLX5_CMD_OP_CREATE_RQT: 357 return MLX5_GET(create_rqt_out, out, rqtn); 358 case MLX5_CMD_OP_CREATE_TIR: 359 return MLX5_GET(create_tir_out, out, tirn); 360 case MLX5_CMD_OP_CREATE_TIS: 361 return MLX5_GET(create_tis_out, out, tisn); 362 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 363 return MLX5_GET(alloc_q_counter_out, out, counter_set_id); 364 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 365 return MLX5_GET(create_flow_table_out, out, table_id); 366 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 367 return MLX5_GET(create_flow_group_out, out, group_id); 368 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 369 return MLX5_GET(set_fte_in, in, flow_index); 370 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 371 return MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 372 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 373 return MLX5_GET(alloc_packet_reformat_context_out, out, 374 packet_reformat_id); 375 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 376 return MLX5_GET(alloc_modify_header_context_out, out, 377 modify_header_id); 378 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 379 return MLX5_GET(create_scheduling_element_out, out, 380 scheduling_element_id); 381 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 382 return MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port); 383 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 384 return MLX5_GET(set_l2_table_entry_in, in, table_index); 385 case MLX5_CMD_OP_CREATE_QP: 386 return MLX5_GET(create_qp_out, out, qpn); 387 case MLX5_CMD_OP_CREATE_SRQ: 388 return MLX5_GET(create_srq_out, out, srqn); 389 case MLX5_CMD_OP_CREATE_XRC_SRQ: 390 return MLX5_GET(create_xrc_srq_out, out, xrc_srqn); 391 case MLX5_CMD_OP_CREATE_DCT: 392 return MLX5_GET(create_dct_out, out, dctn); 393 case MLX5_CMD_OP_CREATE_XRQ: 394 return MLX5_GET(create_xrq_out, out, xrqn); 395 case MLX5_CMD_OP_ATTACH_TO_MCG: 396 return MLX5_GET(attach_to_mcg_in, in, qpn); 397 case MLX5_CMD_OP_ALLOC_XRCD: 398 return MLX5_GET(alloc_xrcd_out, out, xrcd); 399 case MLX5_CMD_OP_CREATE_PSV: 400 return MLX5_GET(create_psv_out, out, psv0_index); 401 default: 402 /* The entry must match to one of the devx_is_obj_create_cmd */ 403 WARN_ON(true); 404 return 0; 405 } 406 } 407 408 static u64 devx_get_obj_id(const void *in) 409 { 410 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 411 u64 obj_id; 412 413 switch (opcode) { 414 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT: 415 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT: 416 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_GENERAL_OBJECT | 417 MLX5_GET(general_obj_in_cmd_hdr, in, 418 obj_type) << 16, 419 MLX5_GET(general_obj_in_cmd_hdr, in, 420 obj_id)); 421 break; 422 case MLX5_CMD_OP_QUERY_MKEY: 423 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_MKEY, 424 MLX5_GET(query_mkey_in, in, 425 mkey_index)); 426 break; 427 case MLX5_CMD_OP_QUERY_CQ: 428 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 429 MLX5_GET(query_cq_in, in, cqn)); 430 break; 431 case MLX5_CMD_OP_MODIFY_CQ: 432 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 433 MLX5_GET(modify_cq_in, in, cqn)); 434 break; 435 case MLX5_CMD_OP_QUERY_SQ: 436 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 437 MLX5_GET(query_sq_in, in, sqn)); 438 break; 439 case MLX5_CMD_OP_MODIFY_SQ: 440 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 441 MLX5_GET(modify_sq_in, in, sqn)); 442 break; 443 case MLX5_CMD_OP_QUERY_RQ: 444 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 445 MLX5_GET(query_rq_in, in, rqn)); 446 break; 447 case MLX5_CMD_OP_MODIFY_RQ: 448 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 449 MLX5_GET(modify_rq_in, in, rqn)); 450 break; 451 case MLX5_CMD_OP_QUERY_RMP: 452 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 453 MLX5_GET(query_rmp_in, in, rmpn)); 454 break; 455 case MLX5_CMD_OP_MODIFY_RMP: 456 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 457 MLX5_GET(modify_rmp_in, in, rmpn)); 458 break; 459 case MLX5_CMD_OP_QUERY_RQT: 460 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 461 MLX5_GET(query_rqt_in, in, rqtn)); 462 break; 463 case MLX5_CMD_OP_MODIFY_RQT: 464 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 465 MLX5_GET(modify_rqt_in, in, rqtn)); 466 break; 467 case MLX5_CMD_OP_QUERY_TIR: 468 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 469 MLX5_GET(query_tir_in, in, tirn)); 470 break; 471 case MLX5_CMD_OP_MODIFY_TIR: 472 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 473 MLX5_GET(modify_tir_in, in, tirn)); 474 break; 475 case MLX5_CMD_OP_QUERY_TIS: 476 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 477 MLX5_GET(query_tis_in, in, tisn)); 478 break; 479 case MLX5_CMD_OP_MODIFY_TIS: 480 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 481 MLX5_GET(modify_tis_in, in, tisn)); 482 break; 483 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 484 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 485 MLX5_GET(query_flow_table_in, in, 486 table_id)); 487 break; 488 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 489 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 490 MLX5_GET(modify_flow_table_in, in, 491 table_id)); 492 break; 493 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 494 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_GROUP, 495 MLX5_GET(query_flow_group_in, in, 496 group_id)); 497 break; 498 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 499 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 500 MLX5_GET(query_fte_in, in, 501 flow_index)); 502 break; 503 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 504 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 505 MLX5_GET(set_fte_in, in, flow_index)); 506 break; 507 case MLX5_CMD_OP_QUERY_Q_COUNTER: 508 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_Q_COUNTER, 509 MLX5_GET(query_q_counter_in, in, 510 counter_set_id)); 511 break; 512 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 513 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_FLOW_COUNTER, 514 MLX5_GET(query_flow_counter_in, in, 515 flow_counter_id)); 516 break; 517 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 518 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT, 519 MLX5_GET(query_modify_header_context_in, 520 in, modify_header_id)); 521 break; 522 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 523 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 524 MLX5_GET(query_scheduling_element_in, 525 in, scheduling_element_id)); 526 break; 527 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 528 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 529 MLX5_GET(modify_scheduling_element_in, 530 in, scheduling_element_id)); 531 break; 532 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 533 obj_id = get_enc_obj_id(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT, 534 MLX5_GET(add_vxlan_udp_dport_in, in, 535 vxlan_udp_port)); 536 break; 537 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 538 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 539 MLX5_GET(query_l2_table_entry_in, in, 540 table_index)); 541 break; 542 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 543 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 544 MLX5_GET(set_l2_table_entry_in, in, 545 table_index)); 546 break; 547 case MLX5_CMD_OP_QUERY_QP: 548 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 549 MLX5_GET(query_qp_in, in, qpn)); 550 break; 551 case MLX5_CMD_OP_RST2INIT_QP: 552 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 553 MLX5_GET(rst2init_qp_in, in, qpn)); 554 break; 555 case MLX5_CMD_OP_INIT2INIT_QP: 556 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 557 MLX5_GET(init2init_qp_in, in, qpn)); 558 break; 559 case MLX5_CMD_OP_INIT2RTR_QP: 560 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 561 MLX5_GET(init2rtr_qp_in, in, qpn)); 562 break; 563 case MLX5_CMD_OP_RTR2RTS_QP: 564 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 565 MLX5_GET(rtr2rts_qp_in, in, qpn)); 566 break; 567 case MLX5_CMD_OP_RTS2RTS_QP: 568 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 569 MLX5_GET(rts2rts_qp_in, in, qpn)); 570 break; 571 case MLX5_CMD_OP_SQERR2RTS_QP: 572 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 573 MLX5_GET(sqerr2rts_qp_in, in, qpn)); 574 break; 575 case MLX5_CMD_OP_2ERR_QP: 576 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 577 MLX5_GET(qp_2err_in, in, qpn)); 578 break; 579 case MLX5_CMD_OP_2RST_QP: 580 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 581 MLX5_GET(qp_2rst_in, in, qpn)); 582 break; 583 case MLX5_CMD_OP_QUERY_DCT: 584 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 585 MLX5_GET(query_dct_in, in, dctn)); 586 break; 587 case MLX5_CMD_OP_QUERY_XRQ: 588 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 589 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 590 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 591 MLX5_GET(query_xrq_in, in, xrqn)); 592 break; 593 case MLX5_CMD_OP_QUERY_XRC_SRQ: 594 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 595 MLX5_GET(query_xrc_srq_in, in, 596 xrc_srqn)); 597 break; 598 case MLX5_CMD_OP_ARM_XRC_SRQ: 599 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 600 MLX5_GET(arm_xrc_srq_in, in, xrc_srqn)); 601 break; 602 case MLX5_CMD_OP_QUERY_SRQ: 603 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SRQ, 604 MLX5_GET(query_srq_in, in, srqn)); 605 break; 606 case MLX5_CMD_OP_ARM_RQ: 607 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 608 MLX5_GET(arm_rq_in, in, srq_number)); 609 break; 610 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 611 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 612 MLX5_GET(drain_dct_in, in, dctn)); 613 break; 614 case MLX5_CMD_OP_ARM_XRQ: 615 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 616 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 617 case MLX5_CMD_OP_MODIFY_XRQ: 618 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 619 MLX5_GET(arm_xrq_in, in, xrqn)); 620 break; 621 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 622 obj_id = get_enc_obj_id 623 (MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT, 624 MLX5_GET(query_packet_reformat_context_in, 625 in, packet_reformat_id)); 626 break; 627 default: 628 obj_id = 0; 629 } 630 631 return obj_id; 632 } 633 634 static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs, 635 struct ib_uobject *uobj, const void *in) 636 { 637 struct mlx5_ib_dev *dev = mlx5_udata_to_mdev(&attrs->driver_udata); 638 u64 obj_id = devx_get_obj_id(in); 639 640 if (!obj_id) 641 return false; 642 643 switch (uobj_get_object_id(uobj)) { 644 case UVERBS_OBJECT_CQ: 645 return get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 646 to_mcq(uobj->object)->mcq.cqn) == 647 obj_id; 648 649 case UVERBS_OBJECT_SRQ: 650 { 651 struct mlx5_core_srq *srq = &(to_msrq(uobj->object)->msrq); 652 u16 opcode; 653 654 switch (srq->common.res) { 655 case MLX5_RES_XSRQ: 656 opcode = MLX5_CMD_OP_CREATE_XRC_SRQ; 657 break; 658 case MLX5_RES_XRQ: 659 opcode = MLX5_CMD_OP_CREATE_XRQ; 660 break; 661 default: 662 if (!dev->mdev->issi) 663 opcode = MLX5_CMD_OP_CREATE_SRQ; 664 else 665 opcode = MLX5_CMD_OP_CREATE_RMP; 666 } 667 668 return get_enc_obj_id(opcode, 669 to_msrq(uobj->object)->msrq.srqn) == 670 obj_id; 671 } 672 673 case UVERBS_OBJECT_QP: 674 { 675 struct mlx5_ib_qp *qp = to_mqp(uobj->object); 676 677 if (qp->type == IB_QPT_RAW_PACKET || 678 (qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 679 struct mlx5_ib_raw_packet_qp *raw_packet_qp = 680 &qp->raw_packet_qp; 681 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 682 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 683 684 return (get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 685 rq->base.mqp.qpn) == obj_id || 686 get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 687 sq->base.mqp.qpn) == obj_id || 688 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 689 rq->tirn) == obj_id || 690 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 691 sq->tisn) == obj_id); 692 } 693 694 if (qp->type == MLX5_IB_QPT_DCT) 695 return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 696 qp->dct.mdct.mqp.qpn) == obj_id; 697 return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 698 qp->ibqp.qp_num) == obj_id; 699 } 700 701 case UVERBS_OBJECT_WQ: 702 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 703 to_mrwq(uobj->object)->core_qp.qpn) == 704 obj_id; 705 706 case UVERBS_OBJECT_RWQ_IND_TBL: 707 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 708 to_mrwq_ind_table(uobj->object)->rqtn) == 709 obj_id; 710 711 case MLX5_IB_OBJECT_DEVX_OBJ: 712 { 713 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 714 struct devx_obj *devx_uobj = uobj->object; 715 716 if (opcode == MLX5_CMD_OP_QUERY_FLOW_COUNTER && 717 devx_uobj->flow_counter_bulk_size) { 718 u64 end; 719 720 end = devx_uobj->obj_id + 721 devx_uobj->flow_counter_bulk_size; 722 return devx_uobj->obj_id <= obj_id && end > obj_id; 723 } 724 725 return devx_uobj->obj_id == obj_id; 726 } 727 728 default: 729 return false; 730 } 731 } 732 733 static void devx_set_umem_valid(const void *in) 734 { 735 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 736 737 switch (opcode) { 738 case MLX5_CMD_OP_CREATE_MKEY: 739 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 740 break; 741 case MLX5_CMD_OP_CREATE_CQ: 742 { 743 void *cqc; 744 745 MLX5_SET(create_cq_in, in, cq_umem_valid, 1); 746 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 747 MLX5_SET(cqc, cqc, dbr_umem_valid, 1); 748 break; 749 } 750 case MLX5_CMD_OP_CREATE_QP: 751 { 752 void *qpc; 753 754 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 755 MLX5_SET(qpc, qpc, dbr_umem_valid, 1); 756 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 757 break; 758 } 759 760 case MLX5_CMD_OP_CREATE_RQ: 761 { 762 void *rqc, *wq; 763 764 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 765 wq = MLX5_ADDR_OF(rqc, rqc, wq); 766 MLX5_SET(wq, wq, dbr_umem_valid, 1); 767 MLX5_SET(wq, wq, wq_umem_valid, 1); 768 break; 769 } 770 771 case MLX5_CMD_OP_CREATE_SQ: 772 { 773 void *sqc, *wq; 774 775 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 776 wq = MLX5_ADDR_OF(sqc, sqc, wq); 777 MLX5_SET(wq, wq, dbr_umem_valid, 1); 778 MLX5_SET(wq, wq, wq_umem_valid, 1); 779 break; 780 } 781 782 case MLX5_CMD_OP_MODIFY_CQ: 783 MLX5_SET(modify_cq_in, in, cq_umem_valid, 1); 784 break; 785 786 case MLX5_CMD_OP_CREATE_RMP: 787 { 788 void *rmpc, *wq; 789 790 rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx); 791 wq = MLX5_ADDR_OF(rmpc, rmpc, wq); 792 MLX5_SET(wq, wq, dbr_umem_valid, 1); 793 MLX5_SET(wq, wq, wq_umem_valid, 1); 794 break; 795 } 796 797 case MLX5_CMD_OP_CREATE_XRQ: 798 { 799 void *xrqc, *wq; 800 801 xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context); 802 wq = MLX5_ADDR_OF(xrqc, xrqc, wq); 803 MLX5_SET(wq, wq, dbr_umem_valid, 1); 804 MLX5_SET(wq, wq, wq_umem_valid, 1); 805 break; 806 } 807 808 case MLX5_CMD_OP_CREATE_XRC_SRQ: 809 { 810 void *xrc_srqc; 811 812 MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1); 813 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in, 814 xrc_srq_context_entry); 815 MLX5_SET(xrc_srqc, xrc_srqc, dbr_umem_valid, 1); 816 break; 817 } 818 819 default: 820 return; 821 } 822 } 823 824 static bool devx_is_obj_create_cmd(const void *in, u16 *opcode) 825 { 826 *opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 827 828 switch (*opcode) { 829 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 830 case MLX5_CMD_OP_CREATE_MKEY: 831 case MLX5_CMD_OP_CREATE_CQ: 832 case MLX5_CMD_OP_ALLOC_PD: 833 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 834 case MLX5_CMD_OP_CREATE_RMP: 835 case MLX5_CMD_OP_CREATE_SQ: 836 case MLX5_CMD_OP_CREATE_RQ: 837 case MLX5_CMD_OP_CREATE_RQT: 838 case MLX5_CMD_OP_CREATE_TIR: 839 case MLX5_CMD_OP_CREATE_TIS: 840 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 841 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 842 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 843 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 844 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 845 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 846 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 847 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 848 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 849 case MLX5_CMD_OP_CREATE_QP: 850 case MLX5_CMD_OP_CREATE_SRQ: 851 case MLX5_CMD_OP_CREATE_XRC_SRQ: 852 case MLX5_CMD_OP_CREATE_DCT: 853 case MLX5_CMD_OP_CREATE_XRQ: 854 case MLX5_CMD_OP_ATTACH_TO_MCG: 855 case MLX5_CMD_OP_ALLOC_XRCD: 856 return true; 857 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 858 { 859 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 860 if (op_mod == 0) 861 return true; 862 return false; 863 } 864 case MLX5_CMD_OP_CREATE_PSV: 865 { 866 u8 num_psv = MLX5_GET(create_psv_in, in, num_psv); 867 868 if (num_psv == 1) 869 return true; 870 return false; 871 } 872 default: 873 return false; 874 } 875 } 876 877 static bool devx_is_obj_modify_cmd(const void *in) 878 { 879 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 880 881 switch (opcode) { 882 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT: 883 case MLX5_CMD_OP_MODIFY_CQ: 884 case MLX5_CMD_OP_MODIFY_RMP: 885 case MLX5_CMD_OP_MODIFY_SQ: 886 case MLX5_CMD_OP_MODIFY_RQ: 887 case MLX5_CMD_OP_MODIFY_RQT: 888 case MLX5_CMD_OP_MODIFY_TIR: 889 case MLX5_CMD_OP_MODIFY_TIS: 890 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 891 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 892 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 893 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 894 case MLX5_CMD_OP_RST2INIT_QP: 895 case MLX5_CMD_OP_INIT2RTR_QP: 896 case MLX5_CMD_OP_INIT2INIT_QP: 897 case MLX5_CMD_OP_RTR2RTS_QP: 898 case MLX5_CMD_OP_RTS2RTS_QP: 899 case MLX5_CMD_OP_SQERR2RTS_QP: 900 case MLX5_CMD_OP_2ERR_QP: 901 case MLX5_CMD_OP_2RST_QP: 902 case MLX5_CMD_OP_ARM_XRC_SRQ: 903 case MLX5_CMD_OP_ARM_RQ: 904 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 905 case MLX5_CMD_OP_ARM_XRQ: 906 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 907 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 908 case MLX5_CMD_OP_MODIFY_XRQ: 909 return true; 910 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 911 { 912 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 913 914 if (op_mod == 1) 915 return true; 916 return false; 917 } 918 default: 919 return false; 920 } 921 } 922 923 static bool devx_is_obj_query_cmd(const void *in) 924 { 925 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 926 927 switch (opcode) { 928 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT: 929 case MLX5_CMD_OP_QUERY_MKEY: 930 case MLX5_CMD_OP_QUERY_CQ: 931 case MLX5_CMD_OP_QUERY_RMP: 932 case MLX5_CMD_OP_QUERY_SQ: 933 case MLX5_CMD_OP_QUERY_RQ: 934 case MLX5_CMD_OP_QUERY_RQT: 935 case MLX5_CMD_OP_QUERY_TIR: 936 case MLX5_CMD_OP_QUERY_TIS: 937 case MLX5_CMD_OP_QUERY_Q_COUNTER: 938 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 939 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 940 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 941 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 942 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 943 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 944 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 945 case MLX5_CMD_OP_QUERY_QP: 946 case MLX5_CMD_OP_QUERY_SRQ: 947 case MLX5_CMD_OP_QUERY_XRC_SRQ: 948 case MLX5_CMD_OP_QUERY_DCT: 949 case MLX5_CMD_OP_QUERY_XRQ: 950 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 951 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 952 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 953 return true; 954 default: 955 return false; 956 } 957 } 958 959 static bool devx_is_whitelist_cmd(void *in) 960 { 961 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 962 963 switch (opcode) { 964 case MLX5_CMD_OP_QUERY_HCA_CAP: 965 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 966 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 967 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS: 968 return true; 969 default: 970 return false; 971 } 972 } 973 974 static int devx_get_uid(struct mlx5_ib_ucontext *c, void *cmd_in) 975 { 976 if (devx_is_whitelist_cmd(cmd_in)) { 977 struct mlx5_ib_dev *dev; 978 979 if (c->devx_uid) 980 return c->devx_uid; 981 982 dev = to_mdev(c->ibucontext.device); 983 if (dev->devx_whitelist_uid) 984 return dev->devx_whitelist_uid; 985 986 return -EOPNOTSUPP; 987 } 988 989 if (!c->devx_uid) 990 return -EINVAL; 991 992 return c->devx_uid; 993 } 994 995 static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev) 996 { 997 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 998 999 /* Pass all cmds for vhca_tunnel as general, tracking is done in FW */ 1000 if ((MLX5_CAP_GEN_64(dev->mdev, vhca_tunnel_commands) && 1001 MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) || 1002 (opcode >= MLX5_CMD_OP_GENERAL_START && 1003 opcode < MLX5_CMD_OP_GENERAL_END)) 1004 return true; 1005 1006 switch (opcode) { 1007 case MLX5_CMD_OP_QUERY_HCA_CAP: 1008 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 1009 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 1010 case MLX5_CMD_OP_QUERY_VPORT_STATE: 1011 case MLX5_CMD_OP_QUERY_ADAPTER: 1012 case MLX5_CMD_OP_QUERY_ISSI: 1013 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 1014 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 1015 case MLX5_CMD_OP_QUERY_VNIC_ENV: 1016 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 1017 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 1018 case MLX5_CMD_OP_NOP: 1019 case MLX5_CMD_OP_QUERY_CONG_STATUS: 1020 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 1021 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 1022 case MLX5_CMD_OP_QUERY_LAG: 1023 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS: 1024 return true; 1025 default: 1026 return false; 1027 } 1028 } 1029 1030 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)( 1031 struct uverbs_attr_bundle *attrs) 1032 { 1033 struct mlx5_ib_ucontext *c; 1034 struct mlx5_ib_dev *dev; 1035 int user_vector; 1036 int dev_eqn; 1037 int err; 1038 1039 if (uverbs_copy_from(&user_vector, attrs, 1040 MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC)) 1041 return -EFAULT; 1042 1043 c = devx_ufile2uctx(attrs); 1044 if (IS_ERR(c)) 1045 return PTR_ERR(c); 1046 dev = to_mdev(c->ibucontext.device); 1047 1048 err = mlx5_comp_eqn_get(dev->mdev, user_vector, &dev_eqn); 1049 if (err < 0) 1050 return err; 1051 1052 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 1053 &dev_eqn, sizeof(dev_eqn))) 1054 return -EFAULT; 1055 1056 return 0; 1057 } 1058 1059 /* 1060 *Security note: 1061 * The hardware protection mechanism works like this: Each device object that 1062 * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in 1063 * the device specification manual) upon its creation. Then upon doorbell, 1064 * hardware fetches the object context for which the doorbell was rang, and 1065 * validates that the UAR through which the DB was rang matches the UAR ID 1066 * of the object. 1067 * If no match the doorbell is silently ignored by the hardware. Of course, 1068 * the user cannot ring a doorbell on a UAR that was not mapped to it. 1069 * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command 1070 * mailboxes (except tagging them with UID), we expose to the user its UAR 1071 * ID, so it can embed it in these objects in the expected specification 1072 * format. So the only thing the user can do is hurt itself by creating a 1073 * QP/SQ/CQ with a UAR ID other than his, and then in this case other users 1074 * may ring a doorbell on its objects. 1075 * The consequence of that will be that another user can schedule a QP/SQ 1076 * of the buggy user for execution (just insert it to the hardware schedule 1077 * queue or arm its CQ for event generation), no further harm is expected. 1078 */ 1079 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_UAR)( 1080 struct uverbs_attr_bundle *attrs) 1081 { 1082 struct mlx5_ib_ucontext *c; 1083 struct mlx5_ib_dev *dev; 1084 u32 user_idx; 1085 s32 dev_idx; 1086 1087 c = devx_ufile2uctx(attrs); 1088 if (IS_ERR(c)) 1089 return PTR_ERR(c); 1090 dev = to_mdev(c->ibucontext.device); 1091 1092 if (uverbs_copy_from(&user_idx, attrs, 1093 MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX)) 1094 return -EFAULT; 1095 1096 dev_idx = bfregn_to_uar_index(dev, &c->bfregi, user_idx, true); 1097 if (dev_idx < 0) 1098 return dev_idx; 1099 1100 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 1101 &dev_idx, sizeof(dev_idx))) 1102 return -EFAULT; 1103 1104 return 0; 1105 } 1106 1107 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OTHER)( 1108 struct uverbs_attr_bundle *attrs) 1109 { 1110 struct mlx5_ib_ucontext *c; 1111 struct mlx5_ib_dev *dev; 1112 void *cmd_in = uverbs_attr_get_alloced_ptr( 1113 attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN); 1114 int cmd_out_len = uverbs_attr_get_len(attrs, 1115 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT); 1116 void *cmd_out; 1117 int err, err2; 1118 int uid; 1119 1120 c = devx_ufile2uctx(attrs); 1121 if (IS_ERR(c)) 1122 return PTR_ERR(c); 1123 dev = to_mdev(c->ibucontext.device); 1124 1125 uid = devx_get_uid(c, cmd_in); 1126 if (uid < 0) 1127 return uid; 1128 1129 /* Only white list of some general HCA commands are allowed for this method. */ 1130 if (!devx_is_general_cmd(cmd_in, dev)) 1131 return -EINVAL; 1132 1133 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1134 if (IS_ERR(cmd_out)) 1135 return PTR_ERR(cmd_out); 1136 1137 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1138 err = mlx5_cmd_do(dev->mdev, cmd_in, 1139 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN), 1140 cmd_out, cmd_out_len); 1141 if (err && err != -EREMOTEIO) 1142 return err; 1143 1144 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, cmd_out, 1145 cmd_out_len); 1146 1147 return err2 ?: err; 1148 } 1149 1150 static void devx_obj_build_destroy_cmd(void *in, void *out, void *din, 1151 u32 *dinlen, 1152 u32 *obj_id) 1153 { 1154 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 1155 u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid); 1156 1157 *obj_id = devx_get_created_obj_id(in, out, opcode); 1158 *dinlen = MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr); 1159 MLX5_SET(general_obj_in_cmd_hdr, din, uid, uid); 1160 1161 switch (opcode) { 1162 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 1163 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT); 1164 MLX5_SET(general_obj_in_cmd_hdr, din, obj_id, *obj_id); 1165 MLX5_SET(general_obj_in_cmd_hdr, din, obj_type, 1166 MLX5_GET(general_obj_in_cmd_hdr, in, obj_type)); 1167 break; 1168 1169 case MLX5_CMD_OP_CREATE_UMEM: 1170 MLX5_SET(destroy_umem_in, din, opcode, 1171 MLX5_CMD_OP_DESTROY_UMEM); 1172 MLX5_SET(destroy_umem_in, din, umem_id, *obj_id); 1173 break; 1174 case MLX5_CMD_OP_CREATE_MKEY: 1175 MLX5_SET(destroy_mkey_in, din, opcode, 1176 MLX5_CMD_OP_DESTROY_MKEY); 1177 MLX5_SET(destroy_mkey_in, din, mkey_index, *obj_id); 1178 break; 1179 case MLX5_CMD_OP_CREATE_CQ: 1180 MLX5_SET(destroy_cq_in, din, opcode, MLX5_CMD_OP_DESTROY_CQ); 1181 MLX5_SET(destroy_cq_in, din, cqn, *obj_id); 1182 break; 1183 case MLX5_CMD_OP_ALLOC_PD: 1184 MLX5_SET(dealloc_pd_in, din, opcode, MLX5_CMD_OP_DEALLOC_PD); 1185 MLX5_SET(dealloc_pd_in, din, pd, *obj_id); 1186 break; 1187 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 1188 MLX5_SET(dealloc_transport_domain_in, din, opcode, 1189 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN); 1190 MLX5_SET(dealloc_transport_domain_in, din, transport_domain, 1191 *obj_id); 1192 break; 1193 case MLX5_CMD_OP_CREATE_RMP: 1194 MLX5_SET(destroy_rmp_in, din, opcode, MLX5_CMD_OP_DESTROY_RMP); 1195 MLX5_SET(destroy_rmp_in, din, rmpn, *obj_id); 1196 break; 1197 case MLX5_CMD_OP_CREATE_SQ: 1198 MLX5_SET(destroy_sq_in, din, opcode, MLX5_CMD_OP_DESTROY_SQ); 1199 MLX5_SET(destroy_sq_in, din, sqn, *obj_id); 1200 break; 1201 case MLX5_CMD_OP_CREATE_RQ: 1202 MLX5_SET(destroy_rq_in, din, opcode, MLX5_CMD_OP_DESTROY_RQ); 1203 MLX5_SET(destroy_rq_in, din, rqn, *obj_id); 1204 break; 1205 case MLX5_CMD_OP_CREATE_RQT: 1206 MLX5_SET(destroy_rqt_in, din, opcode, MLX5_CMD_OP_DESTROY_RQT); 1207 MLX5_SET(destroy_rqt_in, din, rqtn, *obj_id); 1208 break; 1209 case MLX5_CMD_OP_CREATE_TIR: 1210 MLX5_SET(destroy_tir_in, din, opcode, MLX5_CMD_OP_DESTROY_TIR); 1211 MLX5_SET(destroy_tir_in, din, tirn, *obj_id); 1212 break; 1213 case MLX5_CMD_OP_CREATE_TIS: 1214 MLX5_SET(destroy_tis_in, din, opcode, MLX5_CMD_OP_DESTROY_TIS); 1215 MLX5_SET(destroy_tis_in, din, tisn, *obj_id); 1216 break; 1217 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 1218 MLX5_SET(dealloc_q_counter_in, din, opcode, 1219 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 1220 MLX5_SET(dealloc_q_counter_in, din, counter_set_id, *obj_id); 1221 break; 1222 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 1223 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_table_in); 1224 MLX5_SET(destroy_flow_table_in, din, other_vport, 1225 MLX5_GET(create_flow_table_in, in, other_vport)); 1226 MLX5_SET(destroy_flow_table_in, din, vport_number, 1227 MLX5_GET(create_flow_table_in, in, vport_number)); 1228 MLX5_SET(destroy_flow_table_in, din, table_type, 1229 MLX5_GET(create_flow_table_in, in, table_type)); 1230 MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id); 1231 MLX5_SET(destroy_flow_table_in, din, opcode, 1232 MLX5_CMD_OP_DESTROY_FLOW_TABLE); 1233 break; 1234 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 1235 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_group_in); 1236 MLX5_SET(destroy_flow_group_in, din, other_vport, 1237 MLX5_GET(create_flow_group_in, in, other_vport)); 1238 MLX5_SET(destroy_flow_group_in, din, vport_number, 1239 MLX5_GET(create_flow_group_in, in, vport_number)); 1240 MLX5_SET(destroy_flow_group_in, din, table_type, 1241 MLX5_GET(create_flow_group_in, in, table_type)); 1242 MLX5_SET(destroy_flow_group_in, din, table_id, 1243 MLX5_GET(create_flow_group_in, in, table_id)); 1244 MLX5_SET(destroy_flow_group_in, din, group_id, *obj_id); 1245 MLX5_SET(destroy_flow_group_in, din, opcode, 1246 MLX5_CMD_OP_DESTROY_FLOW_GROUP); 1247 break; 1248 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 1249 *dinlen = MLX5_ST_SZ_BYTES(delete_fte_in); 1250 MLX5_SET(delete_fte_in, din, other_vport, 1251 MLX5_GET(set_fte_in, in, other_vport)); 1252 MLX5_SET(delete_fte_in, din, vport_number, 1253 MLX5_GET(set_fte_in, in, vport_number)); 1254 MLX5_SET(delete_fte_in, din, table_type, 1255 MLX5_GET(set_fte_in, in, table_type)); 1256 MLX5_SET(delete_fte_in, din, table_id, 1257 MLX5_GET(set_fte_in, in, table_id)); 1258 MLX5_SET(delete_fte_in, din, flow_index, *obj_id); 1259 MLX5_SET(delete_fte_in, din, opcode, 1260 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY); 1261 break; 1262 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 1263 MLX5_SET(dealloc_flow_counter_in, din, opcode, 1264 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER); 1265 MLX5_SET(dealloc_flow_counter_in, din, flow_counter_id, 1266 *obj_id); 1267 break; 1268 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 1269 MLX5_SET(dealloc_packet_reformat_context_in, din, opcode, 1270 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT); 1271 MLX5_SET(dealloc_packet_reformat_context_in, din, 1272 packet_reformat_id, *obj_id); 1273 break; 1274 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 1275 MLX5_SET(dealloc_modify_header_context_in, din, opcode, 1276 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT); 1277 MLX5_SET(dealloc_modify_header_context_in, din, 1278 modify_header_id, *obj_id); 1279 break; 1280 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 1281 *dinlen = MLX5_ST_SZ_BYTES(destroy_scheduling_element_in); 1282 MLX5_SET(destroy_scheduling_element_in, din, 1283 scheduling_hierarchy, 1284 MLX5_GET(create_scheduling_element_in, in, 1285 scheduling_hierarchy)); 1286 MLX5_SET(destroy_scheduling_element_in, din, 1287 scheduling_element_id, *obj_id); 1288 MLX5_SET(destroy_scheduling_element_in, din, opcode, 1289 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT); 1290 break; 1291 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 1292 *dinlen = MLX5_ST_SZ_BYTES(delete_vxlan_udp_dport_in); 1293 MLX5_SET(delete_vxlan_udp_dport_in, din, vxlan_udp_port, *obj_id); 1294 MLX5_SET(delete_vxlan_udp_dport_in, din, opcode, 1295 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT); 1296 break; 1297 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 1298 *dinlen = MLX5_ST_SZ_BYTES(delete_l2_table_entry_in); 1299 MLX5_SET(delete_l2_table_entry_in, din, table_index, *obj_id); 1300 MLX5_SET(delete_l2_table_entry_in, din, opcode, 1301 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); 1302 break; 1303 case MLX5_CMD_OP_CREATE_QP: 1304 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP); 1305 MLX5_SET(destroy_qp_in, din, qpn, *obj_id); 1306 break; 1307 case MLX5_CMD_OP_CREATE_SRQ: 1308 MLX5_SET(destroy_srq_in, din, opcode, MLX5_CMD_OP_DESTROY_SRQ); 1309 MLX5_SET(destroy_srq_in, din, srqn, *obj_id); 1310 break; 1311 case MLX5_CMD_OP_CREATE_XRC_SRQ: 1312 MLX5_SET(destroy_xrc_srq_in, din, opcode, 1313 MLX5_CMD_OP_DESTROY_XRC_SRQ); 1314 MLX5_SET(destroy_xrc_srq_in, din, xrc_srqn, *obj_id); 1315 break; 1316 case MLX5_CMD_OP_CREATE_DCT: 1317 MLX5_SET(destroy_dct_in, din, opcode, MLX5_CMD_OP_DESTROY_DCT); 1318 MLX5_SET(destroy_dct_in, din, dctn, *obj_id); 1319 break; 1320 case MLX5_CMD_OP_CREATE_XRQ: 1321 MLX5_SET(destroy_xrq_in, din, opcode, MLX5_CMD_OP_DESTROY_XRQ); 1322 MLX5_SET(destroy_xrq_in, din, xrqn, *obj_id); 1323 break; 1324 case MLX5_CMD_OP_ATTACH_TO_MCG: 1325 *dinlen = MLX5_ST_SZ_BYTES(detach_from_mcg_in); 1326 MLX5_SET(detach_from_mcg_in, din, qpn, 1327 MLX5_GET(attach_to_mcg_in, in, qpn)); 1328 memcpy(MLX5_ADDR_OF(detach_from_mcg_in, din, multicast_gid), 1329 MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid), 1330 MLX5_FLD_SZ_BYTES(attach_to_mcg_in, multicast_gid)); 1331 MLX5_SET(detach_from_mcg_in, din, opcode, 1332 MLX5_CMD_OP_DETACH_FROM_MCG); 1333 MLX5_SET(detach_from_mcg_in, din, qpn, *obj_id); 1334 break; 1335 case MLX5_CMD_OP_ALLOC_XRCD: 1336 MLX5_SET(dealloc_xrcd_in, din, opcode, 1337 MLX5_CMD_OP_DEALLOC_XRCD); 1338 MLX5_SET(dealloc_xrcd_in, din, xrcd, *obj_id); 1339 break; 1340 case MLX5_CMD_OP_CREATE_PSV: 1341 MLX5_SET(destroy_psv_in, din, opcode, 1342 MLX5_CMD_OP_DESTROY_PSV); 1343 MLX5_SET(destroy_psv_in, din, psvn, *obj_id); 1344 break; 1345 default: 1346 /* The entry must match to one of the devx_is_obj_create_cmd */ 1347 WARN_ON(true); 1348 break; 1349 } 1350 } 1351 1352 static int devx_handle_mkey_indirect(struct devx_obj *obj, 1353 struct mlx5_ib_dev *dev, 1354 void *in, void *out) 1355 { 1356 struct mlx5_ib_mkey *mkey = &obj->mkey; 1357 void *mkc; 1358 u8 key; 1359 1360 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1361 key = MLX5_GET(mkc, mkc, mkey_7_0); 1362 mkey->key = mlx5_idx_to_mkey( 1363 MLX5_GET(create_mkey_out, out, mkey_index)) | key; 1364 mkey->type = MLX5_MKEY_INDIRECT_DEVX; 1365 mkey->ndescs = MLX5_GET(mkc, mkc, translations_octword_size); 1366 init_waitqueue_head(&mkey->wait); 1367 1368 return mlx5r_store_odp_mkey(dev, mkey); 1369 } 1370 1371 static int devx_handle_mkey_create(struct mlx5_ib_dev *dev, 1372 struct devx_obj *obj, 1373 void *in, int in_len) 1374 { 1375 int min_len = MLX5_BYTE_OFF(create_mkey_in, memory_key_mkey_entry) + 1376 MLX5_FLD_SZ_BYTES(create_mkey_in, 1377 memory_key_mkey_entry); 1378 void *mkc; 1379 u8 access_mode; 1380 1381 if (in_len < min_len) 1382 return -EINVAL; 1383 1384 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1385 1386 access_mode = MLX5_GET(mkc, mkc, access_mode_1_0); 1387 access_mode |= MLX5_GET(mkc, mkc, access_mode_4_2) << 2; 1388 1389 if (access_mode == MLX5_MKC_ACCESS_MODE_KLMS || 1390 access_mode == MLX5_MKC_ACCESS_MODE_KSM) { 1391 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) 1392 obj->flags |= DEVX_OBJ_FLAGS_INDIRECT_MKEY; 1393 return 0; 1394 } 1395 1396 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 1397 /* TPH is not allowed to bypass the regular kernel's verbs flow */ 1398 MLX5_SET(mkc, mkc, pcie_tph_en, 0); 1399 MLX5_SET(mkc, mkc, pcie_tph_steering_tag_index, 1400 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX); 1401 return 0; 1402 } 1403 1404 static void devx_cleanup_subscription(struct mlx5_ib_dev *dev, 1405 struct devx_event_subscription *sub) 1406 { 1407 struct devx_event *event; 1408 struct devx_obj_event *xa_val_level2; 1409 1410 if (sub->is_cleaned) 1411 return; 1412 1413 sub->is_cleaned = 1; 1414 list_del_rcu(&sub->xa_list); 1415 1416 if (list_empty(&sub->obj_list)) 1417 return; 1418 1419 list_del_rcu(&sub->obj_list); 1420 /* check whether key level 1 for this obj_sub_list is empty */ 1421 event = xa_load(&dev->devx_event_table.event_xa, 1422 sub->xa_key_level1); 1423 WARN_ON(!event); 1424 1425 xa_val_level2 = xa_load(&event->object_ids, sub->xa_key_level2); 1426 if (list_empty(&xa_val_level2->obj_sub_list)) { 1427 xa_erase(&event->object_ids, 1428 sub->xa_key_level2); 1429 kfree_rcu(xa_val_level2, rcu); 1430 } 1431 } 1432 1433 static int devx_obj_cleanup(struct ib_uobject *uobject, 1434 enum rdma_remove_reason why, 1435 struct uverbs_attr_bundle *attrs) 1436 { 1437 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1438 struct mlx5_devx_event_table *devx_event_table; 1439 struct devx_obj *obj = uobject->object; 1440 struct devx_event_subscription *sub_entry, *tmp; 1441 struct mlx5_ib_dev *dev; 1442 int ret; 1443 1444 dev = mlx5_udata_to_mdev(&attrs->driver_udata); 1445 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY && 1446 xa_erase(&obj->ib_dev->odp_mkeys, 1447 mlx5_base_mkey(obj->mkey.key))) 1448 /* 1449 * The pagefault_single_data_segment() does commands against 1450 * the mmkey, we must wait for that to stop before freeing the 1451 * mkey, as another allocation could get the same mkey #. 1452 */ 1453 mlx5r_deref_wait_odp_mkey(&obj->mkey); 1454 1455 if (obj->flags & DEVX_OBJ_FLAGS_HW_FREED) 1456 ret = 0; 1457 else if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1458 ret = mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct); 1459 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1460 ret = mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1461 else 1462 ret = mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, 1463 obj->dinlen, out, sizeof(out)); 1464 if (ret) 1465 return ret; 1466 1467 devx_event_table = &dev->devx_event_table; 1468 1469 mutex_lock(&devx_event_table->event_xa_lock); 1470 list_for_each_entry_safe(sub_entry, tmp, &obj->event_sub, obj_list) 1471 devx_cleanup_subscription(dev, sub_entry); 1472 mutex_unlock(&devx_event_table->event_xa_lock); 1473 1474 kfree(obj); 1475 return ret; 1476 } 1477 1478 static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) 1479 { 1480 struct devx_obj *obj = container_of(mcq, struct devx_obj, core_cq); 1481 struct mlx5_devx_event_table *table; 1482 struct devx_event *event; 1483 struct devx_obj_event *obj_event; 1484 u32 obj_id = mcq->cqn; 1485 1486 table = &obj->ib_dev->devx_event_table; 1487 rcu_read_lock(); 1488 event = xa_load(&table->event_xa, MLX5_EVENT_TYPE_COMP); 1489 if (!event) 1490 goto out; 1491 1492 obj_event = xa_load(&event->object_ids, obj_id); 1493 if (!obj_event) 1494 goto out; 1495 1496 dispatch_event_fd(&obj_event->obj_sub_list, eqe); 1497 out: 1498 rcu_read_unlock(); 1499 } 1500 1501 static bool is_apu_cq(struct mlx5_ib_dev *dev, const void *in) 1502 { 1503 if (!MLX5_CAP_GEN(dev->mdev, apu) || 1504 !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq)) 1505 return false; 1506 1507 return true; 1508 } 1509 1510 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)( 1511 struct uverbs_attr_bundle *attrs) 1512 { 1513 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1514 int cmd_out_len = uverbs_attr_get_len(attrs, 1515 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT); 1516 int cmd_in_len = uverbs_attr_get_len(attrs, 1517 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1518 void *cmd_out; 1519 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1520 attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE); 1521 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1522 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1523 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1524 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1525 struct devx_obj *obj; 1526 u16 obj_type = 0; 1527 int err, err2 = 0; 1528 int uid; 1529 u32 obj_id; 1530 u16 opcode; 1531 1532 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1533 return -EINVAL; 1534 1535 uid = devx_get_uid(c, cmd_in); 1536 if (uid < 0) 1537 return uid; 1538 1539 if (!devx_is_obj_create_cmd(cmd_in, &opcode)) 1540 return -EINVAL; 1541 1542 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1543 if (IS_ERR(cmd_out)) 1544 return PTR_ERR(cmd_out); 1545 1546 obj = kzalloc(sizeof(struct devx_obj), GFP_KERNEL); 1547 if (!obj) 1548 return -ENOMEM; 1549 1550 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1551 if (opcode == MLX5_CMD_OP_CREATE_MKEY) { 1552 err = devx_handle_mkey_create(dev, obj, cmd_in, cmd_in_len); 1553 if (err) 1554 goto obj_free; 1555 } else { 1556 devx_set_umem_valid(cmd_in); 1557 } 1558 1559 if (opcode == MLX5_CMD_OP_CREATE_DCT) { 1560 obj->flags |= DEVX_OBJ_FLAGS_DCT; 1561 err = mlx5_core_create_dct(dev, &obj->core_dct, cmd_in, 1562 cmd_in_len, cmd_out, cmd_out_len); 1563 } else if (opcode == MLX5_CMD_OP_CREATE_CQ && 1564 !is_apu_cq(dev, cmd_in)) { 1565 obj->flags |= DEVX_OBJ_FLAGS_CQ; 1566 obj->core_cq.comp = devx_cq_comp; 1567 err = mlx5_create_cq(dev->mdev, &obj->core_cq, 1568 cmd_in, cmd_in_len, cmd_out, 1569 cmd_out_len); 1570 } else { 1571 err = mlx5_cmd_do(dev->mdev, cmd_in, cmd_in_len, 1572 cmd_out, cmd_out_len); 1573 } 1574 1575 if (err == -EREMOTEIO) 1576 err2 = uverbs_copy_to(attrs, 1577 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, 1578 cmd_out, cmd_out_len); 1579 if (err) 1580 goto obj_free; 1581 1582 if (opcode == MLX5_CMD_OP_ALLOC_FLOW_COUNTER) { 1583 u32 bulk = MLX5_GET(alloc_flow_counter_in, 1584 cmd_in, 1585 flow_counter_bulk_log_size); 1586 1587 if (bulk) 1588 bulk = 1 << bulk; 1589 else 1590 bulk = 128UL * MLX5_GET(alloc_flow_counter_in, 1591 cmd_in, 1592 flow_counter_bulk); 1593 obj->flow_counter_bulk_size = bulk; 1594 } 1595 1596 uobj->object = obj; 1597 INIT_LIST_HEAD(&obj->event_sub); 1598 obj->ib_dev = dev; 1599 devx_obj_build_destroy_cmd(cmd_in, cmd_out, obj->dinbox, &obj->dinlen, 1600 &obj_id); 1601 WARN_ON(obj->dinlen > MLX5_MAX_DESTROY_INBOX_SIZE_DW * sizeof(u32)); 1602 1603 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, cmd_out, cmd_out_len); 1604 if (err) 1605 goto obj_destroy; 1606 1607 if (opcode == MLX5_CMD_OP_CREATE_GENERAL_OBJECT) 1608 obj_type = MLX5_GET(general_obj_in_cmd_hdr, cmd_in, obj_type); 1609 obj->obj_id = get_enc_obj_id(opcode | obj_type << 16, obj_id); 1610 1611 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY) { 1612 err = devx_handle_mkey_indirect(obj, dev, cmd_in, cmd_out); 1613 if (err) 1614 goto obj_destroy; 1615 } 1616 return 0; 1617 1618 obj_destroy: 1619 if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1620 mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct); 1621 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1622 mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1623 else 1624 mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, obj->dinlen, out, 1625 sizeof(out)); 1626 obj_free: 1627 kfree(obj); 1628 return err2 ?: err; 1629 } 1630 1631 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_MODIFY)( 1632 struct uverbs_attr_bundle *attrs) 1633 { 1634 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN); 1635 int cmd_out_len = uverbs_attr_get_len(attrs, 1636 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT); 1637 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1638 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE); 1639 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1640 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1641 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1642 void *cmd_out; 1643 int err, err2; 1644 int uid; 1645 1646 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1647 return -EINVAL; 1648 1649 uid = devx_get_uid(c, cmd_in); 1650 if (uid < 0) 1651 return uid; 1652 1653 if (!devx_is_obj_modify_cmd(cmd_in)) 1654 return -EINVAL; 1655 1656 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1657 return -EINVAL; 1658 1659 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1660 if (IS_ERR(cmd_out)) 1661 return PTR_ERR(cmd_out); 1662 1663 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1664 devx_set_umem_valid(cmd_in); 1665 1666 err = mlx5_cmd_do(mdev->mdev, cmd_in, 1667 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN), 1668 cmd_out, cmd_out_len); 1669 if (err && err != -EREMOTEIO) 1670 return err; 1671 1672 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 1673 cmd_out, cmd_out_len); 1674 1675 return err2 ?: err; 1676 } 1677 1678 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_QUERY)( 1679 struct uverbs_attr_bundle *attrs) 1680 { 1681 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN); 1682 int cmd_out_len = uverbs_attr_get_len(attrs, 1683 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT); 1684 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1685 MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE); 1686 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1687 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1688 void *cmd_out; 1689 int err, err2; 1690 int uid; 1691 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1692 1693 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1694 return -EINVAL; 1695 1696 uid = devx_get_uid(c, cmd_in); 1697 if (uid < 0) 1698 return uid; 1699 1700 if (!devx_is_obj_query_cmd(cmd_in)) 1701 return -EINVAL; 1702 1703 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1704 return -EINVAL; 1705 1706 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1707 if (IS_ERR(cmd_out)) 1708 return PTR_ERR(cmd_out); 1709 1710 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1711 err = mlx5_cmd_do(mdev->mdev, cmd_in, 1712 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN), 1713 cmd_out, cmd_out_len); 1714 if (err && err != -EREMOTEIO) 1715 return err; 1716 1717 err2 = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 1718 cmd_out, cmd_out_len); 1719 1720 return err2 ?: err; 1721 } 1722 1723 struct devx_async_event_queue { 1724 spinlock_t lock; 1725 wait_queue_head_t poll_wait; 1726 struct list_head event_list; 1727 atomic_t bytes_in_use; 1728 u8 is_destroyed:1; 1729 }; 1730 1731 struct devx_async_cmd_event_file { 1732 struct ib_uobject uobj; 1733 struct devx_async_event_queue ev_queue; 1734 struct mlx5_async_ctx async_ctx; 1735 }; 1736 1737 static void devx_init_event_queue(struct devx_async_event_queue *ev_queue) 1738 { 1739 spin_lock_init(&ev_queue->lock); 1740 INIT_LIST_HEAD(&ev_queue->event_list); 1741 init_waitqueue_head(&ev_queue->poll_wait); 1742 atomic_set(&ev_queue->bytes_in_use, 0); 1743 ev_queue->is_destroyed = 0; 1744 } 1745 1746 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)( 1747 struct uverbs_attr_bundle *attrs) 1748 { 1749 struct devx_async_cmd_event_file *ev_file; 1750 1751 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1752 attrs, MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE); 1753 struct mlx5_ib_dev *mdev = mlx5_udata_to_mdev(&attrs->driver_udata); 1754 1755 ev_file = container_of(uobj, struct devx_async_cmd_event_file, 1756 uobj); 1757 devx_init_event_queue(&ev_file->ev_queue); 1758 mlx5_cmd_init_async_ctx(mdev->mdev, &ev_file->async_ctx); 1759 return 0; 1760 } 1761 1762 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)( 1763 struct uverbs_attr_bundle *attrs) 1764 { 1765 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1766 attrs, MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE); 1767 struct devx_async_event_file *ev_file; 1768 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1769 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1770 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1771 u32 flags; 1772 int err; 1773 1774 err = uverbs_get_flags32(&flags, attrs, 1775 MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 1776 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA); 1777 1778 if (err) 1779 return err; 1780 1781 ev_file = container_of(uobj, struct devx_async_event_file, 1782 uobj); 1783 spin_lock_init(&ev_file->lock); 1784 INIT_LIST_HEAD(&ev_file->event_list); 1785 init_waitqueue_head(&ev_file->poll_wait); 1786 if (flags & MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA) 1787 ev_file->omit_data = 1; 1788 INIT_LIST_HEAD(&ev_file->subscribed_events_list); 1789 ev_file->dev = dev; 1790 get_device(&dev->ib_dev.dev); 1791 return 0; 1792 } 1793 1794 static void devx_query_callback(int status, struct mlx5_async_work *context) 1795 { 1796 struct devx_async_data *async_data = 1797 container_of(context, struct devx_async_data, cb_work); 1798 struct devx_async_cmd_event_file *ev_file = async_data->ev_file; 1799 struct devx_async_event_queue *ev_queue = &ev_file->ev_queue; 1800 unsigned long flags; 1801 1802 /* 1803 * Note that if the struct devx_async_cmd_event_file uobj begins to be 1804 * destroyed it will block at mlx5_cmd_cleanup_async_ctx() until this 1805 * routine returns, ensuring that it always remains valid here. 1806 */ 1807 spin_lock_irqsave(&ev_queue->lock, flags); 1808 list_add_tail(&async_data->list, &ev_queue->event_list); 1809 spin_unlock_irqrestore(&ev_queue->lock, flags); 1810 1811 wake_up_interruptible(&ev_queue->poll_wait); 1812 } 1813 1814 #define MAX_ASYNC_BYTES_IN_USE (1024 * 1024) /* 1MB */ 1815 1816 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)( 1817 struct uverbs_attr_bundle *attrs) 1818 { 1819 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, 1820 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN); 1821 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1822 attrs, 1823 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE); 1824 u16 cmd_out_len; 1825 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1826 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1827 struct ib_uobject *fd_uobj; 1828 int err; 1829 int uid; 1830 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1831 struct devx_async_cmd_event_file *ev_file; 1832 struct devx_async_data *async_data; 1833 1834 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1835 return -EINVAL; 1836 1837 uid = devx_get_uid(c, cmd_in); 1838 if (uid < 0) 1839 return uid; 1840 1841 if (!devx_is_obj_query_cmd(cmd_in)) 1842 return -EINVAL; 1843 1844 err = uverbs_get_const(&cmd_out_len, attrs, 1845 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN); 1846 if (err) 1847 return err; 1848 1849 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1850 return -EINVAL; 1851 1852 fd_uobj = uverbs_attr_get_uobject(attrs, 1853 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD); 1854 if (IS_ERR(fd_uobj)) 1855 return PTR_ERR(fd_uobj); 1856 1857 ev_file = container_of(fd_uobj, struct devx_async_cmd_event_file, 1858 uobj); 1859 1860 if (atomic_add_return(cmd_out_len, &ev_file->ev_queue.bytes_in_use) > 1861 MAX_ASYNC_BYTES_IN_USE) { 1862 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1863 return -EAGAIN; 1864 } 1865 1866 async_data = kvzalloc(struct_size(async_data, hdr.out_data, 1867 cmd_out_len), GFP_KERNEL); 1868 if (!async_data) { 1869 err = -ENOMEM; 1870 goto sub_bytes; 1871 } 1872 1873 err = uverbs_copy_from(&async_data->hdr.wr_id, attrs, 1874 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID); 1875 if (err) 1876 goto free_async; 1877 1878 async_data->cmd_out_len = cmd_out_len; 1879 async_data->mdev = mdev; 1880 async_data->ev_file = ev_file; 1881 1882 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1883 err = mlx5_cmd_exec_cb(&ev_file->async_ctx, cmd_in, 1884 uverbs_attr_get_len(attrs, 1885 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN), 1886 async_data->hdr.out_data, 1887 async_data->cmd_out_len, 1888 devx_query_callback, &async_data->cb_work); 1889 1890 if (err) 1891 goto free_async; 1892 1893 return 0; 1894 1895 free_async: 1896 kvfree(async_data); 1897 sub_bytes: 1898 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1899 return err; 1900 } 1901 1902 static void 1903 subscribe_event_xa_dealloc(struct mlx5_devx_event_table *devx_event_table, 1904 u32 key_level1, 1905 bool is_level2, 1906 u32 key_level2) 1907 { 1908 struct devx_event *event; 1909 struct devx_obj_event *xa_val_level2; 1910 1911 /* Level 1 is valid for future use, no need to free */ 1912 if (!is_level2) 1913 return; 1914 1915 event = xa_load(&devx_event_table->event_xa, key_level1); 1916 WARN_ON(!event); 1917 1918 xa_val_level2 = xa_load(&event->object_ids, 1919 key_level2); 1920 if (list_empty(&xa_val_level2->obj_sub_list)) { 1921 xa_erase(&event->object_ids, 1922 key_level2); 1923 kfree_rcu(xa_val_level2, rcu); 1924 } 1925 } 1926 1927 static int 1928 subscribe_event_xa_alloc(struct mlx5_devx_event_table *devx_event_table, 1929 u32 key_level1, 1930 bool is_level2, 1931 u32 key_level2) 1932 { 1933 struct devx_obj_event *obj_event; 1934 struct devx_event *event; 1935 int err; 1936 1937 event = xa_load(&devx_event_table->event_xa, key_level1); 1938 if (!event) { 1939 event = kzalloc(sizeof(*event), GFP_KERNEL); 1940 if (!event) 1941 return -ENOMEM; 1942 1943 INIT_LIST_HEAD(&event->unaffiliated_list); 1944 xa_init(&event->object_ids); 1945 1946 err = xa_insert(&devx_event_table->event_xa, 1947 key_level1, 1948 event, 1949 GFP_KERNEL); 1950 if (err) { 1951 kfree(event); 1952 return err; 1953 } 1954 } 1955 1956 if (!is_level2) 1957 return 0; 1958 1959 obj_event = xa_load(&event->object_ids, key_level2); 1960 if (!obj_event) { 1961 obj_event = kzalloc(sizeof(*obj_event), GFP_KERNEL); 1962 if (!obj_event) 1963 /* Level1 is valid for future use, no need to free */ 1964 return -ENOMEM; 1965 1966 INIT_LIST_HEAD(&obj_event->obj_sub_list); 1967 err = xa_insert(&event->object_ids, 1968 key_level2, 1969 obj_event, 1970 GFP_KERNEL); 1971 if (err) { 1972 kfree(obj_event); 1973 return err; 1974 } 1975 } 1976 1977 return 0; 1978 } 1979 1980 static bool is_valid_events_legacy(int num_events, u16 *event_type_num_list, 1981 struct devx_obj *obj) 1982 { 1983 int i; 1984 1985 for (i = 0; i < num_events; i++) { 1986 if (obj) { 1987 if (!is_legacy_obj_event_num(event_type_num_list[i])) 1988 return false; 1989 } else if (!is_legacy_unaffiliated_event_num( 1990 event_type_num_list[i])) { 1991 return false; 1992 } 1993 } 1994 1995 return true; 1996 } 1997 1998 #define MAX_SUPP_EVENT_NUM 255 1999 static bool is_valid_events(struct mlx5_core_dev *dev, 2000 int num_events, u16 *event_type_num_list, 2001 struct devx_obj *obj) 2002 { 2003 __be64 *aff_events; 2004 __be64 *unaff_events; 2005 int mask_entry; 2006 int mask_bit; 2007 int i; 2008 2009 if (MLX5_CAP_GEN(dev, event_cap)) { 2010 aff_events = MLX5_CAP_DEV_EVENT(dev, 2011 user_affiliated_events); 2012 unaff_events = MLX5_CAP_DEV_EVENT(dev, 2013 user_unaffiliated_events); 2014 } else { 2015 return is_valid_events_legacy(num_events, event_type_num_list, 2016 obj); 2017 } 2018 2019 for (i = 0; i < num_events; i++) { 2020 if (event_type_num_list[i] > MAX_SUPP_EVENT_NUM) 2021 return false; 2022 2023 mask_entry = event_type_num_list[i] / 64; 2024 mask_bit = event_type_num_list[i] % 64; 2025 2026 if (obj) { 2027 /* CQ completion */ 2028 if (event_type_num_list[i] == 0) 2029 continue; 2030 2031 if (!(be64_to_cpu(aff_events[mask_entry]) & 2032 (1ull << mask_bit))) 2033 return false; 2034 2035 continue; 2036 } 2037 2038 if (!(be64_to_cpu(unaff_events[mask_entry]) & 2039 (1ull << mask_bit))) 2040 return false; 2041 } 2042 2043 return true; 2044 } 2045 2046 #define MAX_NUM_EVENTS 16 2047 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)( 2048 struct uverbs_attr_bundle *attrs) 2049 { 2050 struct ib_uobject *devx_uobj = uverbs_attr_get_uobject( 2051 attrs, 2052 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE); 2053 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 2054 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2055 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 2056 struct ib_uobject *fd_uobj; 2057 struct devx_obj *obj = NULL; 2058 struct devx_async_event_file *ev_file; 2059 struct mlx5_devx_event_table *devx_event_table = &dev->devx_event_table; 2060 u16 *event_type_num_list; 2061 struct devx_event_subscription *event_sub, *tmp_sub; 2062 struct list_head sub_list; 2063 int redirect_fd; 2064 bool use_eventfd = false; 2065 int num_events; 2066 u16 obj_type = 0; 2067 u64 cookie = 0; 2068 u32 obj_id = 0; 2069 int err; 2070 int i; 2071 2072 if (!c->devx_uid) 2073 return -EINVAL; 2074 2075 if (!IS_ERR(devx_uobj)) { 2076 obj = (struct devx_obj *)devx_uobj->object; 2077 if (obj) 2078 obj_id = get_dec_obj_id(obj->obj_id); 2079 } 2080 2081 fd_uobj = uverbs_attr_get_uobject(attrs, 2082 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE); 2083 if (IS_ERR(fd_uobj)) 2084 return PTR_ERR(fd_uobj); 2085 2086 ev_file = container_of(fd_uobj, struct devx_async_event_file, 2087 uobj); 2088 2089 if (uverbs_attr_is_valid(attrs, 2090 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM)) { 2091 err = uverbs_copy_from(&redirect_fd, attrs, 2092 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM); 2093 if (err) 2094 return err; 2095 2096 use_eventfd = true; 2097 } 2098 2099 if (uverbs_attr_is_valid(attrs, 2100 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE)) { 2101 if (use_eventfd) 2102 return -EINVAL; 2103 2104 err = uverbs_copy_from(&cookie, attrs, 2105 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE); 2106 if (err) 2107 return err; 2108 } 2109 2110 num_events = uverbs_attr_ptr_get_array_size( 2111 attrs, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 2112 sizeof(u16)); 2113 2114 if (num_events < 0) 2115 return num_events; 2116 2117 if (num_events > MAX_NUM_EVENTS) 2118 return -EINVAL; 2119 2120 event_type_num_list = uverbs_attr_get_alloced_ptr(attrs, 2121 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST); 2122 2123 if (!is_valid_events(dev->mdev, num_events, event_type_num_list, obj)) 2124 return -EINVAL; 2125 2126 INIT_LIST_HEAD(&sub_list); 2127 2128 /* Protect from concurrent subscriptions to same XA entries to allow 2129 * both to succeed 2130 */ 2131 mutex_lock(&devx_event_table->event_xa_lock); 2132 for (i = 0; i < num_events; i++) { 2133 u32 key_level1; 2134 2135 if (obj) 2136 obj_type = get_dec_obj_type(obj, 2137 event_type_num_list[i]); 2138 key_level1 = event_type_num_list[i] | obj_type << 16; 2139 2140 err = subscribe_event_xa_alloc(devx_event_table, 2141 key_level1, 2142 obj, 2143 obj_id); 2144 if (err) 2145 goto err; 2146 2147 event_sub = kzalloc(sizeof(*event_sub), GFP_KERNEL); 2148 if (!event_sub) { 2149 err = -ENOMEM; 2150 goto err; 2151 } 2152 2153 list_add_tail(&event_sub->event_list, &sub_list); 2154 uverbs_uobject_get(&ev_file->uobj); 2155 if (use_eventfd) { 2156 event_sub->eventfd = 2157 eventfd_ctx_fdget(redirect_fd); 2158 2159 if (IS_ERR(event_sub->eventfd)) { 2160 err = PTR_ERR(event_sub->eventfd); 2161 event_sub->eventfd = NULL; 2162 goto err; 2163 } 2164 } 2165 2166 event_sub->cookie = cookie; 2167 event_sub->ev_file = ev_file; 2168 /* May be needed upon cleanup the devx object/subscription */ 2169 event_sub->xa_key_level1 = key_level1; 2170 event_sub->xa_key_level2 = obj_id; 2171 INIT_LIST_HEAD(&event_sub->obj_list); 2172 } 2173 2174 /* Once all the allocations and the XA data insertions were done we 2175 * can go ahead and add all the subscriptions to the relevant lists 2176 * without concern of a failure. 2177 */ 2178 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2179 struct devx_event *event; 2180 struct devx_obj_event *obj_event; 2181 2182 list_del_init(&event_sub->event_list); 2183 2184 spin_lock_irq(&ev_file->lock); 2185 list_add_tail_rcu(&event_sub->file_list, 2186 &ev_file->subscribed_events_list); 2187 spin_unlock_irq(&ev_file->lock); 2188 2189 event = xa_load(&devx_event_table->event_xa, 2190 event_sub->xa_key_level1); 2191 WARN_ON(!event); 2192 2193 if (!obj) { 2194 list_add_tail_rcu(&event_sub->xa_list, 2195 &event->unaffiliated_list); 2196 continue; 2197 } 2198 2199 obj_event = xa_load(&event->object_ids, obj_id); 2200 WARN_ON(!obj_event); 2201 list_add_tail_rcu(&event_sub->xa_list, 2202 &obj_event->obj_sub_list); 2203 list_add_tail_rcu(&event_sub->obj_list, 2204 &obj->event_sub); 2205 } 2206 2207 mutex_unlock(&devx_event_table->event_xa_lock); 2208 return 0; 2209 2210 err: 2211 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2212 list_del(&event_sub->event_list); 2213 2214 subscribe_event_xa_dealloc(devx_event_table, 2215 event_sub->xa_key_level1, 2216 obj, 2217 obj_id); 2218 2219 if (event_sub->eventfd) 2220 eventfd_ctx_put(event_sub->eventfd); 2221 uverbs_uobject_put(&event_sub->ev_file->uobj); 2222 kfree(event_sub); 2223 } 2224 2225 mutex_unlock(&devx_event_table->event_xa_lock); 2226 return err; 2227 } 2228 2229 static int devx_umem_get(struct mlx5_ib_dev *dev, struct ib_ucontext *ucontext, 2230 struct uverbs_attr_bundle *attrs, 2231 struct devx_umem *obj, u32 access_flags) 2232 { 2233 u64 addr; 2234 size_t size; 2235 int err; 2236 2237 if (uverbs_copy_from(&addr, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR) || 2238 uverbs_copy_from(&size, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN)) 2239 return -EFAULT; 2240 2241 err = ib_check_mr_access(&dev->ib_dev, access_flags); 2242 if (err) 2243 return err; 2244 2245 if (uverbs_attr_is_valid(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD)) { 2246 struct ib_umem_dmabuf *umem_dmabuf; 2247 int dmabuf_fd; 2248 2249 err = uverbs_get_raw_fd(&dmabuf_fd, attrs, 2250 MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD); 2251 if (err) 2252 return -EFAULT; 2253 2254 umem_dmabuf = ib_umem_dmabuf_get_pinned( 2255 &dev->ib_dev, addr, size, dmabuf_fd, access_flags); 2256 if (IS_ERR(umem_dmabuf)) 2257 return PTR_ERR(umem_dmabuf); 2258 obj->umem = &umem_dmabuf->umem; 2259 } else { 2260 obj->umem = ib_umem_get(&dev->ib_dev, addr, size, access_flags); 2261 if (IS_ERR(obj->umem)) 2262 return PTR_ERR(obj->umem); 2263 } 2264 return 0; 2265 } 2266 2267 static unsigned int devx_umem_find_best_pgsize(struct ib_umem *umem, 2268 unsigned long pgsz_bitmap) 2269 { 2270 unsigned long page_size; 2271 2272 /* Don't bother checking larger page sizes as offset must be zero and 2273 * total DEVX umem length must be equal to total umem length. 2274 */ 2275 pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length), 2276 PAGE_SHIFT), 2277 MLX5_ADAPTER_PAGE_SHIFT); 2278 if (!pgsz_bitmap) 2279 return 0; 2280 2281 page_size = ib_umem_find_best_pgoff(umem, pgsz_bitmap, U64_MAX); 2282 if (!page_size) 2283 return 0; 2284 2285 /* If the page_size is less than the CPU page size then we can use the 2286 * offset and create a umem which is a subset of the page list. 2287 * For larger page sizes we can't be sure the DMA list reflects the 2288 * VA so we must ensure that the umem extent is exactly equal to the 2289 * page list. Reduce the page size until one of these cases is true. 2290 */ 2291 while ((ib_umem_dma_offset(umem, page_size) != 0 || 2292 (umem->length % page_size) != 0) && 2293 page_size > PAGE_SIZE) 2294 page_size /= 2; 2295 2296 return page_size; 2297 } 2298 2299 static int devx_umem_reg_cmd_alloc(struct mlx5_ib_dev *dev, 2300 struct uverbs_attr_bundle *attrs, 2301 struct devx_umem *obj, 2302 struct devx_umem_reg_cmd *cmd, 2303 int access) 2304 { 2305 unsigned long pgsz_bitmap; 2306 unsigned int page_size; 2307 __be64 *mtt; 2308 void *umem; 2309 int ret; 2310 2311 /* 2312 * If the user does not pass in pgsz_bitmap then the user promises not 2313 * to use umem_offset!=0 in any commands that allocate on top of the 2314 * umem. 2315 * 2316 * If the user wants to use a umem_offset then it must pass in 2317 * pgsz_bitmap which guides the maximum page size and thus maximum 2318 * object alignment inside the umem. See the PRM. 2319 * 2320 * Users are not allowed to use IOVA here, mkeys are not supported on 2321 * umem. 2322 */ 2323 ret = uverbs_get_const_default(&pgsz_bitmap, attrs, 2324 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, 2325 GENMASK_ULL(63, 2326 min(PAGE_SHIFT, MLX5_ADAPTER_PAGE_SHIFT))); 2327 if (ret) 2328 return ret; 2329 2330 page_size = devx_umem_find_best_pgsize(obj->umem, pgsz_bitmap); 2331 if (!page_size) 2332 return -EINVAL; 2333 2334 cmd->inlen = MLX5_ST_SZ_BYTES(create_umem_in) + 2335 (MLX5_ST_SZ_BYTES(mtt) * 2336 ib_umem_num_dma_blocks(obj->umem, page_size)); 2337 cmd->in = uverbs_zalloc(attrs, cmd->inlen); 2338 if (IS_ERR(cmd->in)) 2339 return PTR_ERR(cmd->in); 2340 2341 umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem); 2342 mtt = (__be64 *)MLX5_ADDR_OF(umem, umem, mtt); 2343 2344 MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM); 2345 MLX5_SET64(umem, umem, num_of_mtt, 2346 ib_umem_num_dma_blocks(obj->umem, page_size)); 2347 MLX5_SET(umem, umem, log_page_size, 2348 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 2349 MLX5_SET(umem, umem, page_offset, 2350 ib_umem_dma_offset(obj->umem, page_size)); 2351 2352 if (mlx5_umem_needs_ats(dev, obj->umem, access)) 2353 MLX5_SET(umem, umem, ats, 1); 2354 2355 mlx5_ib_populate_pas(obj->umem, page_size, mtt, 2356 (obj->umem->writable ? MLX5_IB_MTT_WRITE : 0) | 2357 MLX5_IB_MTT_READ); 2358 return 0; 2359 } 2360 2361 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_UMEM_REG)( 2362 struct uverbs_attr_bundle *attrs) 2363 { 2364 struct devx_umem_reg_cmd cmd; 2365 struct devx_umem *obj; 2366 struct ib_uobject *uobj = uverbs_attr_get_uobject( 2367 attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE); 2368 u32 obj_id; 2369 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 2370 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2371 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 2372 int access_flags; 2373 int err; 2374 2375 if (!c->devx_uid) 2376 return -EINVAL; 2377 2378 err = uverbs_get_flags32(&access_flags, attrs, 2379 MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 2380 IB_ACCESS_LOCAL_WRITE | 2381 IB_ACCESS_REMOTE_WRITE | 2382 IB_ACCESS_REMOTE_READ | 2383 IB_ACCESS_RELAXED_ORDERING); 2384 if (err) 2385 return err; 2386 2387 obj = kzalloc(sizeof(struct devx_umem), GFP_KERNEL); 2388 if (!obj) 2389 return -ENOMEM; 2390 2391 err = devx_umem_get(dev, &c->ibucontext, attrs, obj, access_flags); 2392 if (err) 2393 goto err_obj_free; 2394 2395 err = devx_umem_reg_cmd_alloc(dev, attrs, obj, &cmd, access_flags); 2396 if (err) 2397 goto err_umem_release; 2398 2399 MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid); 2400 err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out, 2401 sizeof(cmd.out)); 2402 if (err) 2403 goto err_umem_release; 2404 2405 obj->mdev = dev->mdev; 2406 uobj->object = obj; 2407 devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id); 2408 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE); 2409 2410 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, &obj_id, 2411 sizeof(obj_id)); 2412 return err; 2413 2414 err_umem_release: 2415 ib_umem_release(obj->umem); 2416 err_obj_free: 2417 kfree(obj); 2418 return err; 2419 } 2420 2421 static int devx_umem_cleanup(struct ib_uobject *uobject, 2422 enum rdma_remove_reason why, 2423 struct uverbs_attr_bundle *attrs) 2424 { 2425 struct devx_umem *obj = uobject->object; 2426 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2427 int err; 2428 2429 err = mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, out, sizeof(out)); 2430 if (err) 2431 return err; 2432 2433 ib_umem_release(obj->umem); 2434 kfree(obj); 2435 return 0; 2436 } 2437 2438 static bool is_unaffiliated_event(struct mlx5_core_dev *dev, 2439 unsigned long event_type) 2440 { 2441 __be64 *unaff_events; 2442 int mask_entry; 2443 int mask_bit; 2444 2445 if (!MLX5_CAP_GEN(dev, event_cap)) 2446 return is_legacy_unaffiliated_event_num(event_type); 2447 2448 unaff_events = MLX5_CAP_DEV_EVENT(dev, 2449 user_unaffiliated_events); 2450 WARN_ON(event_type > MAX_SUPP_EVENT_NUM); 2451 2452 mask_entry = event_type / 64; 2453 mask_bit = event_type % 64; 2454 2455 if (!(be64_to_cpu(unaff_events[mask_entry]) & (1ull << mask_bit))) 2456 return false; 2457 2458 return true; 2459 } 2460 2461 static u32 devx_get_obj_id_from_event(unsigned long event_type, void *data) 2462 { 2463 struct mlx5_eqe *eqe = data; 2464 u32 obj_id = 0; 2465 2466 switch (event_type) { 2467 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 2468 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 2469 case MLX5_EVENT_TYPE_PATH_MIG: 2470 case MLX5_EVENT_TYPE_COMM_EST: 2471 case MLX5_EVENT_TYPE_SQ_DRAINED: 2472 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 2473 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 2474 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 2475 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 2476 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 2477 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 2478 break; 2479 case MLX5_EVENT_TYPE_XRQ_ERROR: 2480 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff; 2481 break; 2482 case MLX5_EVENT_TYPE_DCT_DRAINED: 2483 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 2484 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; 2485 break; 2486 case MLX5_EVENT_TYPE_CQ_ERROR: 2487 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 2488 break; 2489 default: 2490 obj_id = MLX5_GET(affiliated_event_header, &eqe->data, obj_id); 2491 break; 2492 } 2493 2494 return obj_id; 2495 } 2496 2497 static int deliver_event(struct devx_event_subscription *event_sub, 2498 const void *data) 2499 { 2500 struct devx_async_event_file *ev_file; 2501 struct devx_async_event_data *event_data; 2502 unsigned long flags; 2503 2504 ev_file = event_sub->ev_file; 2505 2506 if (ev_file->omit_data) { 2507 spin_lock_irqsave(&ev_file->lock, flags); 2508 if (!list_empty(&event_sub->event_list) || 2509 ev_file->is_destroyed) { 2510 spin_unlock_irqrestore(&ev_file->lock, flags); 2511 return 0; 2512 } 2513 2514 list_add_tail(&event_sub->event_list, &ev_file->event_list); 2515 spin_unlock_irqrestore(&ev_file->lock, flags); 2516 wake_up_interruptible(&ev_file->poll_wait); 2517 return 0; 2518 } 2519 2520 event_data = kzalloc(sizeof(*event_data) + sizeof(struct mlx5_eqe), 2521 GFP_ATOMIC); 2522 if (!event_data) { 2523 spin_lock_irqsave(&ev_file->lock, flags); 2524 ev_file->is_overflow_err = 1; 2525 spin_unlock_irqrestore(&ev_file->lock, flags); 2526 return -ENOMEM; 2527 } 2528 2529 event_data->hdr.cookie = event_sub->cookie; 2530 memcpy(event_data->hdr.out_data, data, sizeof(struct mlx5_eqe)); 2531 2532 spin_lock_irqsave(&ev_file->lock, flags); 2533 if (!ev_file->is_destroyed) 2534 list_add_tail(&event_data->list, &ev_file->event_list); 2535 else 2536 kfree(event_data); 2537 spin_unlock_irqrestore(&ev_file->lock, flags); 2538 wake_up_interruptible(&ev_file->poll_wait); 2539 2540 return 0; 2541 } 2542 2543 static void dispatch_event_fd(struct list_head *fd_list, 2544 const void *data) 2545 { 2546 struct devx_event_subscription *item; 2547 2548 list_for_each_entry_rcu(item, fd_list, xa_list) { 2549 if (item->eventfd) 2550 eventfd_signal(item->eventfd); 2551 else 2552 deliver_event(item, data); 2553 } 2554 } 2555 2556 static int devx_event_notifier(struct notifier_block *nb, 2557 unsigned long event_type, void *data) 2558 { 2559 struct mlx5_devx_event_table *table; 2560 struct mlx5_ib_dev *dev; 2561 struct devx_event *event; 2562 struct devx_obj_event *obj_event; 2563 u16 obj_type = 0; 2564 bool is_unaffiliated; 2565 u32 obj_id; 2566 2567 /* Explicit filtering to kernel events which may occur frequently */ 2568 if (event_type == MLX5_EVENT_TYPE_CMD || 2569 event_type == MLX5_EVENT_TYPE_PAGE_REQUEST) 2570 return NOTIFY_OK; 2571 2572 table = container_of(nb, struct mlx5_devx_event_table, devx_nb.nb); 2573 dev = container_of(table, struct mlx5_ib_dev, devx_event_table); 2574 is_unaffiliated = is_unaffiliated_event(dev->mdev, event_type); 2575 2576 if (!is_unaffiliated) 2577 obj_type = get_event_obj_type(event_type, data); 2578 2579 rcu_read_lock(); 2580 event = xa_load(&table->event_xa, event_type | (obj_type << 16)); 2581 if (!event) { 2582 rcu_read_unlock(); 2583 return NOTIFY_DONE; 2584 } 2585 2586 if (is_unaffiliated) { 2587 dispatch_event_fd(&event->unaffiliated_list, data); 2588 rcu_read_unlock(); 2589 return NOTIFY_OK; 2590 } 2591 2592 obj_id = devx_get_obj_id_from_event(event_type, data); 2593 obj_event = xa_load(&event->object_ids, obj_id); 2594 if (!obj_event) { 2595 rcu_read_unlock(); 2596 return NOTIFY_DONE; 2597 } 2598 2599 dispatch_event_fd(&obj_event->obj_sub_list, data); 2600 2601 rcu_read_unlock(); 2602 return NOTIFY_OK; 2603 } 2604 2605 int mlx5_ib_devx_init(struct mlx5_ib_dev *dev) 2606 { 2607 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2608 int uid; 2609 2610 uid = mlx5_ib_devx_create(dev, false, 0); 2611 if (uid > 0) { 2612 dev->devx_whitelist_uid = uid; 2613 xa_init(&table->event_xa); 2614 mutex_init(&table->event_xa_lock); 2615 MLX5_NB_INIT(&table->devx_nb, devx_event_notifier, NOTIFY_ANY); 2616 mlx5_eq_notifier_register(dev->mdev, &table->devx_nb); 2617 } 2618 2619 return 0; 2620 } 2621 2622 void mlx5_ib_devx_cleanup(struct mlx5_ib_dev *dev) 2623 { 2624 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2625 struct devx_event_subscription *sub, *tmp; 2626 struct devx_event *event; 2627 void *entry; 2628 unsigned long id; 2629 2630 if (dev->devx_whitelist_uid) { 2631 mlx5_eq_notifier_unregister(dev->mdev, &table->devx_nb); 2632 mutex_lock(&dev->devx_event_table.event_xa_lock); 2633 xa_for_each(&table->event_xa, id, entry) { 2634 event = entry; 2635 list_for_each_entry_safe( 2636 sub, tmp, &event->unaffiliated_list, xa_list) 2637 devx_cleanup_subscription(dev, sub); 2638 kfree(entry); 2639 } 2640 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2641 xa_destroy(&table->event_xa); 2642 2643 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 2644 } 2645 } 2646 2647 static void devx_async_destroy_cb(int status, struct mlx5_async_work *context) 2648 { 2649 struct mlx5_async_cmd *devx_out = container_of(context, 2650 struct mlx5_async_cmd, cb_work); 2651 struct devx_obj *obj = devx_out->uobject->object; 2652 2653 if (!status) 2654 obj->flags |= DEVX_OBJ_FLAGS_HW_FREED; 2655 2656 complete(&devx_out->comp); 2657 } 2658 2659 static void devx_async_destroy(struct mlx5_ib_dev *dev, 2660 struct mlx5_async_cmd *cmd) 2661 { 2662 init_completion(&cmd->comp); 2663 cmd->err = mlx5_cmd_exec_cb(&dev->async_ctx, cmd->in, cmd->in_size, 2664 &cmd->out, sizeof(cmd->out), 2665 devx_async_destroy_cb, &cmd->cb_work); 2666 } 2667 2668 static void devx_wait_async_destroy(struct mlx5_async_cmd *cmd) 2669 { 2670 if (!cmd->err) 2671 wait_for_completion(&cmd->comp); 2672 atomic_set(&cmd->uobject->usecnt, 0); 2673 } 2674 2675 void mlx5_ib_ufile_hw_cleanup(struct ib_uverbs_file *ufile) 2676 { 2677 struct mlx5_async_cmd *async_cmd; 2678 struct ib_ucontext *ucontext = ufile->ucontext; 2679 struct ib_device *device = ucontext->device; 2680 struct mlx5_ib_dev *dev = to_mdev(device); 2681 struct ib_uobject *uobject; 2682 struct devx_obj *obj; 2683 int head = 0; 2684 int tail = 0; 2685 2686 async_cmd = kcalloc(MAX_ASYNC_CMDS, sizeof(*async_cmd), GFP_KERNEL); 2687 if (!async_cmd) 2688 return; 2689 2690 list_for_each_entry(uobject, &ufile->uobjects, list) { 2691 WARN_ON(uverbs_try_lock_object(uobject, UVERBS_LOOKUP_WRITE)); 2692 2693 /* 2694 * Currently we only support QP destruction, if other objects 2695 * are to be destroyed need to add type synchronization to the 2696 * cleanup algorithm and handle pre/post FW cleanup for the 2697 * new types if needed. 2698 */ 2699 if (uobj_get_object_id(uobject) != MLX5_IB_OBJECT_DEVX_OBJ || 2700 (get_dec_obj_type(uobject->object, MLX5_EVENT_TYPE_MAX) != 2701 MLX5_OBJ_TYPE_QP)) { 2702 atomic_set(&uobject->usecnt, 0); 2703 continue; 2704 } 2705 2706 obj = uobject->object; 2707 2708 async_cmd[tail % MAX_ASYNC_CMDS].in = obj->dinbox; 2709 async_cmd[tail % MAX_ASYNC_CMDS].in_size = obj->dinlen; 2710 async_cmd[tail % MAX_ASYNC_CMDS].uobject = uobject; 2711 2712 devx_async_destroy(dev, &async_cmd[tail % MAX_ASYNC_CMDS]); 2713 tail++; 2714 2715 if (tail - head == MAX_ASYNC_CMDS) { 2716 devx_wait_async_destroy(&async_cmd[head % MAX_ASYNC_CMDS]); 2717 head++; 2718 } 2719 } 2720 2721 while (head != tail) { 2722 devx_wait_async_destroy(&async_cmd[head % MAX_ASYNC_CMDS]); 2723 head++; 2724 } 2725 2726 kfree(async_cmd); 2727 } 2728 2729 static ssize_t devx_async_cmd_event_read(struct file *filp, char __user *buf, 2730 size_t count, loff_t *pos) 2731 { 2732 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2733 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2734 struct devx_async_data *event; 2735 int ret = 0; 2736 size_t eventsz; 2737 2738 spin_lock_irq(&ev_queue->lock); 2739 2740 while (list_empty(&ev_queue->event_list)) { 2741 spin_unlock_irq(&ev_queue->lock); 2742 2743 if (filp->f_flags & O_NONBLOCK) 2744 return -EAGAIN; 2745 2746 if (wait_event_interruptible( 2747 ev_queue->poll_wait, 2748 (!list_empty(&ev_queue->event_list) || 2749 ev_queue->is_destroyed))) { 2750 return -ERESTARTSYS; 2751 } 2752 2753 spin_lock_irq(&ev_queue->lock); 2754 if (ev_queue->is_destroyed) { 2755 spin_unlock_irq(&ev_queue->lock); 2756 return -EIO; 2757 } 2758 } 2759 2760 event = list_entry(ev_queue->event_list.next, 2761 struct devx_async_data, list); 2762 eventsz = event->cmd_out_len + 2763 sizeof(struct mlx5_ib_uapi_devx_async_cmd_hdr); 2764 2765 if (eventsz > count) { 2766 spin_unlock_irq(&ev_queue->lock); 2767 return -ENOSPC; 2768 } 2769 2770 list_del(ev_queue->event_list.next); 2771 spin_unlock_irq(&ev_queue->lock); 2772 2773 if (copy_to_user(buf, &event->hdr, eventsz)) 2774 ret = -EFAULT; 2775 else 2776 ret = eventsz; 2777 2778 atomic_sub(event->cmd_out_len, &ev_queue->bytes_in_use); 2779 kvfree(event); 2780 return ret; 2781 } 2782 2783 static __poll_t devx_async_cmd_event_poll(struct file *filp, 2784 struct poll_table_struct *wait) 2785 { 2786 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2787 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2788 __poll_t pollflags = 0; 2789 2790 poll_wait(filp, &ev_queue->poll_wait, wait); 2791 2792 spin_lock_irq(&ev_queue->lock); 2793 if (ev_queue->is_destroyed) 2794 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; 2795 else if (!list_empty(&ev_queue->event_list)) 2796 pollflags = EPOLLIN | EPOLLRDNORM; 2797 spin_unlock_irq(&ev_queue->lock); 2798 2799 return pollflags; 2800 } 2801 2802 static const struct file_operations devx_async_cmd_event_fops = { 2803 .owner = THIS_MODULE, 2804 .read = devx_async_cmd_event_read, 2805 .poll = devx_async_cmd_event_poll, 2806 .release = uverbs_uobject_fd_release, 2807 }; 2808 2809 static ssize_t devx_async_event_read(struct file *filp, char __user *buf, 2810 size_t count, loff_t *pos) 2811 { 2812 struct devx_async_event_file *ev_file = filp->private_data; 2813 struct devx_event_subscription *event_sub; 2814 struct devx_async_event_data *event; 2815 int ret = 0; 2816 size_t eventsz; 2817 bool omit_data; 2818 void *event_data; 2819 2820 omit_data = ev_file->omit_data; 2821 2822 spin_lock_irq(&ev_file->lock); 2823 2824 if (ev_file->is_overflow_err) { 2825 ev_file->is_overflow_err = 0; 2826 spin_unlock_irq(&ev_file->lock); 2827 return -EOVERFLOW; 2828 } 2829 2830 2831 while (list_empty(&ev_file->event_list)) { 2832 spin_unlock_irq(&ev_file->lock); 2833 2834 if (filp->f_flags & O_NONBLOCK) 2835 return -EAGAIN; 2836 2837 if (wait_event_interruptible(ev_file->poll_wait, 2838 (!list_empty(&ev_file->event_list) || 2839 ev_file->is_destroyed))) { 2840 return -ERESTARTSYS; 2841 } 2842 2843 spin_lock_irq(&ev_file->lock); 2844 if (ev_file->is_destroyed) { 2845 spin_unlock_irq(&ev_file->lock); 2846 return -EIO; 2847 } 2848 } 2849 2850 if (omit_data) { 2851 event_sub = list_first_entry(&ev_file->event_list, 2852 struct devx_event_subscription, 2853 event_list); 2854 eventsz = sizeof(event_sub->cookie); 2855 event_data = &event_sub->cookie; 2856 } else { 2857 event = list_first_entry(&ev_file->event_list, 2858 struct devx_async_event_data, list); 2859 eventsz = sizeof(struct mlx5_eqe) + 2860 sizeof(struct mlx5_ib_uapi_devx_async_event_hdr); 2861 event_data = &event->hdr; 2862 } 2863 2864 if (eventsz > count) { 2865 spin_unlock_irq(&ev_file->lock); 2866 return -EINVAL; 2867 } 2868 2869 if (omit_data) 2870 list_del_init(&event_sub->event_list); 2871 else 2872 list_del(&event->list); 2873 2874 spin_unlock_irq(&ev_file->lock); 2875 2876 if (copy_to_user(buf, event_data, eventsz)) 2877 /* This points to an application issue, not a kernel concern */ 2878 ret = -EFAULT; 2879 else 2880 ret = eventsz; 2881 2882 if (!omit_data) 2883 kfree(event); 2884 return ret; 2885 } 2886 2887 static __poll_t devx_async_event_poll(struct file *filp, 2888 struct poll_table_struct *wait) 2889 { 2890 struct devx_async_event_file *ev_file = filp->private_data; 2891 __poll_t pollflags = 0; 2892 2893 poll_wait(filp, &ev_file->poll_wait, wait); 2894 2895 spin_lock_irq(&ev_file->lock); 2896 if (ev_file->is_destroyed) 2897 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; 2898 else if (!list_empty(&ev_file->event_list)) 2899 pollflags = EPOLLIN | EPOLLRDNORM; 2900 spin_unlock_irq(&ev_file->lock); 2901 2902 return pollflags; 2903 } 2904 2905 static void devx_free_subscription(struct rcu_head *rcu) 2906 { 2907 struct devx_event_subscription *event_sub = 2908 container_of(rcu, struct devx_event_subscription, rcu); 2909 2910 if (event_sub->eventfd) 2911 eventfd_ctx_put(event_sub->eventfd); 2912 uverbs_uobject_put(&event_sub->ev_file->uobj); 2913 kfree(event_sub); 2914 } 2915 2916 static const struct file_operations devx_async_event_fops = { 2917 .owner = THIS_MODULE, 2918 .read = devx_async_event_read, 2919 .poll = devx_async_event_poll, 2920 .release = uverbs_uobject_fd_release, 2921 }; 2922 2923 static void devx_async_cmd_event_destroy_uobj(struct ib_uobject *uobj, 2924 enum rdma_remove_reason why) 2925 { 2926 struct devx_async_cmd_event_file *comp_ev_file = 2927 container_of(uobj, struct devx_async_cmd_event_file, 2928 uobj); 2929 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2930 struct devx_async_data *entry, *tmp; 2931 2932 spin_lock_irq(&ev_queue->lock); 2933 ev_queue->is_destroyed = 1; 2934 spin_unlock_irq(&ev_queue->lock); 2935 wake_up_interruptible(&ev_queue->poll_wait); 2936 2937 mlx5_cmd_cleanup_async_ctx(&comp_ev_file->async_ctx); 2938 2939 spin_lock_irq(&comp_ev_file->ev_queue.lock); 2940 list_for_each_entry_safe(entry, tmp, 2941 &comp_ev_file->ev_queue.event_list, list) { 2942 list_del(&entry->list); 2943 kvfree(entry); 2944 } 2945 spin_unlock_irq(&comp_ev_file->ev_queue.lock); 2946 }; 2947 2948 static void devx_async_event_destroy_uobj(struct ib_uobject *uobj, 2949 enum rdma_remove_reason why) 2950 { 2951 struct devx_async_event_file *ev_file = 2952 container_of(uobj, struct devx_async_event_file, 2953 uobj); 2954 struct devx_event_subscription *event_sub, *event_sub_tmp; 2955 struct mlx5_ib_dev *dev = ev_file->dev; 2956 2957 spin_lock_irq(&ev_file->lock); 2958 ev_file->is_destroyed = 1; 2959 2960 /* free the pending events allocation */ 2961 if (ev_file->omit_data) { 2962 struct devx_event_subscription *event_sub, *tmp; 2963 2964 list_for_each_entry_safe(event_sub, tmp, &ev_file->event_list, 2965 event_list) 2966 list_del_init(&event_sub->event_list); 2967 2968 } else { 2969 struct devx_async_event_data *entry, *tmp; 2970 2971 list_for_each_entry_safe(entry, tmp, &ev_file->event_list, 2972 list) { 2973 list_del(&entry->list); 2974 kfree(entry); 2975 } 2976 } 2977 2978 spin_unlock_irq(&ev_file->lock); 2979 wake_up_interruptible(&ev_file->poll_wait); 2980 2981 mutex_lock(&dev->devx_event_table.event_xa_lock); 2982 /* delete the subscriptions which are related to this FD */ 2983 list_for_each_entry_safe(event_sub, event_sub_tmp, 2984 &ev_file->subscribed_events_list, file_list) { 2985 devx_cleanup_subscription(dev, event_sub); 2986 list_del_rcu(&event_sub->file_list); 2987 /* subscription may not be used by the read API any more */ 2988 call_rcu(&event_sub->rcu, devx_free_subscription); 2989 } 2990 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2991 2992 put_device(&dev->ib_dev.dev); 2993 }; 2994 2995 DECLARE_UVERBS_NAMED_METHOD( 2996 MLX5_IB_METHOD_DEVX_UMEM_REG, 2997 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE, 2998 MLX5_IB_OBJECT_DEVX_UMEM, 2999 UVERBS_ACCESS_NEW, 3000 UA_MANDATORY), 3001 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR, 3002 UVERBS_ATTR_TYPE(u64), 3003 UA_MANDATORY), 3004 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_LEN, 3005 UVERBS_ATTR_TYPE(u64), 3006 UA_MANDATORY), 3007 UVERBS_ATTR_RAW_FD(MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD, 3008 UA_OPTIONAL), 3009 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 3010 enum ib_access_flags), 3011 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, 3012 u64), 3013 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, 3014 UVERBS_ATTR_TYPE(u32), 3015 UA_MANDATORY)); 3016 3017 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3018 MLX5_IB_METHOD_DEVX_UMEM_DEREG, 3019 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE, 3020 MLX5_IB_OBJECT_DEVX_UMEM, 3021 UVERBS_ACCESS_DESTROY, 3022 UA_MANDATORY)); 3023 3024 DECLARE_UVERBS_NAMED_METHOD( 3025 MLX5_IB_METHOD_DEVX_QUERY_EQN, 3026 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC, 3027 UVERBS_ATTR_TYPE(u32), 3028 UA_MANDATORY), 3029 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 3030 UVERBS_ATTR_TYPE(u32), 3031 UA_MANDATORY)); 3032 3033 DECLARE_UVERBS_NAMED_METHOD( 3034 MLX5_IB_METHOD_DEVX_QUERY_UAR, 3035 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX, 3036 UVERBS_ATTR_TYPE(u32), 3037 UA_MANDATORY), 3038 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 3039 UVERBS_ATTR_TYPE(u32), 3040 UA_MANDATORY)); 3041 3042 DECLARE_UVERBS_NAMED_METHOD( 3043 MLX5_IB_METHOD_DEVX_OTHER, 3044 UVERBS_ATTR_PTR_IN( 3045 MLX5_IB_ATTR_DEVX_OTHER_CMD_IN, 3046 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 3047 UA_MANDATORY, 3048 UA_ALLOC_AND_COPY), 3049 UVERBS_ATTR_PTR_OUT( 3050 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, 3051 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 3052 UA_MANDATORY)); 3053 3054 DECLARE_UVERBS_NAMED_METHOD( 3055 MLX5_IB_METHOD_DEVX_OBJ_CREATE, 3056 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE, 3057 MLX5_IB_OBJECT_DEVX_OBJ, 3058 UVERBS_ACCESS_NEW, 3059 UA_MANDATORY), 3060 UVERBS_ATTR_PTR_IN( 3061 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN, 3062 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 3063 UA_MANDATORY, 3064 UA_ALLOC_AND_COPY), 3065 UVERBS_ATTR_PTR_OUT( 3066 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, 3067 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 3068 UA_MANDATORY)); 3069 3070 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3071 MLX5_IB_METHOD_DEVX_OBJ_DESTROY, 3072 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE, 3073 MLX5_IB_OBJECT_DEVX_OBJ, 3074 UVERBS_ACCESS_DESTROY, 3075 UA_MANDATORY)); 3076 3077 DECLARE_UVERBS_NAMED_METHOD( 3078 MLX5_IB_METHOD_DEVX_OBJ_MODIFY, 3079 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE, 3080 UVERBS_IDR_ANY_OBJECT, 3081 UVERBS_ACCESS_READ, 3082 UA_MANDATORY), 3083 UVERBS_ATTR_PTR_IN( 3084 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN, 3085 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 3086 UA_MANDATORY, 3087 UA_ALLOC_AND_COPY), 3088 UVERBS_ATTR_PTR_OUT( 3089 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 3090 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 3091 UA_MANDATORY)); 3092 3093 DECLARE_UVERBS_NAMED_METHOD( 3094 MLX5_IB_METHOD_DEVX_OBJ_QUERY, 3095 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 3096 UVERBS_IDR_ANY_OBJECT, 3097 UVERBS_ACCESS_READ, 3098 UA_MANDATORY), 3099 UVERBS_ATTR_PTR_IN( 3100 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 3101 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 3102 UA_MANDATORY, 3103 UA_ALLOC_AND_COPY), 3104 UVERBS_ATTR_PTR_OUT( 3105 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 3106 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 3107 UA_MANDATORY)); 3108 3109 DECLARE_UVERBS_NAMED_METHOD( 3110 MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY, 3111 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 3112 UVERBS_IDR_ANY_OBJECT, 3113 UVERBS_ACCESS_READ, 3114 UA_MANDATORY), 3115 UVERBS_ATTR_PTR_IN( 3116 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 3117 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 3118 UA_MANDATORY, 3119 UA_ALLOC_AND_COPY), 3120 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN, 3121 u16, UA_MANDATORY), 3122 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD, 3123 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3124 UVERBS_ACCESS_READ, 3125 UA_MANDATORY), 3126 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID, 3127 UVERBS_ATTR_TYPE(u64), 3128 UA_MANDATORY)); 3129 3130 DECLARE_UVERBS_NAMED_METHOD( 3131 MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT, 3132 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE, 3133 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3134 UVERBS_ACCESS_READ, 3135 UA_MANDATORY), 3136 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE, 3137 MLX5_IB_OBJECT_DEVX_OBJ, 3138 UVERBS_ACCESS_READ, 3139 UA_OPTIONAL), 3140 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 3141 UVERBS_ATTR_MIN_SIZE(sizeof(u16)), 3142 UA_MANDATORY, 3143 UA_ALLOC_AND_COPY), 3144 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE, 3145 UVERBS_ATTR_TYPE(u64), 3146 UA_OPTIONAL), 3147 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM, 3148 UVERBS_ATTR_TYPE(u32), 3149 UA_OPTIONAL)); 3150 3151 DECLARE_UVERBS_GLOBAL_METHODS(MLX5_IB_OBJECT_DEVX, 3152 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OTHER), 3153 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_UAR), 3154 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_EQN), 3155 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)); 3156 3157 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_OBJ, 3158 UVERBS_TYPE_ALLOC_IDR(devx_obj_cleanup), 3159 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_CREATE), 3160 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_DESTROY), 3161 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_MODIFY), 3162 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_QUERY), 3163 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)); 3164 3165 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_UMEM, 3166 UVERBS_TYPE_ALLOC_IDR(devx_umem_cleanup), 3167 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_REG), 3168 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_DEREG)); 3169 3170 3171 DECLARE_UVERBS_NAMED_METHOD( 3172 MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC, 3173 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE, 3174 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3175 UVERBS_ACCESS_NEW, 3176 UA_MANDATORY)); 3177 3178 DECLARE_UVERBS_NAMED_OBJECT( 3179 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3180 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_cmd_event_file), 3181 devx_async_cmd_event_destroy_uobj, 3182 &devx_async_cmd_event_fops, "[devx_async_cmd]", 3183 O_RDONLY), 3184 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)); 3185 3186 DECLARE_UVERBS_NAMED_METHOD( 3187 MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC, 3188 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE, 3189 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3190 UVERBS_ACCESS_NEW, 3191 UA_MANDATORY), 3192 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 3193 enum mlx5_ib_uapi_devx_create_event_channel_flags, 3194 UA_MANDATORY)); 3195 3196 DECLARE_UVERBS_NAMED_OBJECT( 3197 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3198 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_event_file), 3199 devx_async_event_destroy_uobj, 3200 &devx_async_event_fops, "[devx_async_event]", 3201 O_RDONLY), 3202 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)); 3203 3204 static bool devx_is_supported(struct ib_device *device) 3205 { 3206 struct mlx5_ib_dev *dev = to_mdev(device); 3207 3208 return MLX5_CAP_GEN(dev->mdev, log_max_uctx); 3209 } 3210 3211 const struct uapi_definition mlx5_ib_devx_defs[] = { 3212 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3213 MLX5_IB_OBJECT_DEVX, 3214 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3215 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3216 MLX5_IB_OBJECT_DEVX_OBJ, 3217 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3218 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3219 MLX5_IB_OBJECT_DEVX_UMEM, 3220 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3221 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3222 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3223 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3224 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3225 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3226 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3227 {}, 3228 }; 3229