1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_mad.h> 34 #include <rdma/ib_smi.h> 35 #include <rdma/ib_sa.h> 36 #include <rdma/ib_cache.h> 37 38 #include <linux/random.h> 39 #include <linux/mlx4/cmd.h> 40 #include <linux/gfp.h> 41 #include <rdma/ib_pma.h> 42 43 #include <linux/mlx4/driver.h> 44 #include "mlx4_ib.h" 45 46 enum { 47 MLX4_IB_VENDOR_CLASS1 = 0x9, 48 MLX4_IB_VENDOR_CLASS2 = 0xa 49 }; 50 51 #define MLX4_TUN_SEND_WRID_SHIFT 34 52 #define MLX4_TUN_QPN_SHIFT 32 53 #define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT) 54 #define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT) 55 56 #define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1) 57 #define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3) 58 59 /* Port mgmt change event handling */ 60 61 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr) 62 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask) 63 #define NUM_IDX_IN_PKEY_TBL_BLK 32 64 #define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */ 65 #define GUID_TBL_BLK_NUM_ENTRIES 8 66 #define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES) 67 68 struct mlx4_mad_rcv_buf { 69 struct ib_grh grh; 70 u8 payload[256]; 71 } __packed; 72 73 struct mlx4_mad_snd_buf { 74 u8 payload[256]; 75 } __packed; 76 77 struct mlx4_tunnel_mad { 78 struct ib_grh grh; 79 struct mlx4_ib_tunnel_header hdr; 80 struct ib_mad mad; 81 } __packed; 82 83 struct mlx4_rcv_tunnel_mad { 84 struct mlx4_rcv_tunnel_hdr hdr; 85 struct ib_grh grh; 86 struct ib_mad mad; 87 } __packed; 88 89 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num); 90 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num); 91 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 92 int block, u32 change_bitmap); 93 94 __be64 mlx4_ib_gen_node_guid(void) 95 { 96 #define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40)) 97 return cpu_to_be64(NODE_GUID_HI | prandom_u32()); 98 } 99 100 __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx) 101 { 102 return cpu_to_be64(atomic_inc_return(&ctx->tid)) | 103 cpu_to_be64(0xff00000000000000LL); 104 } 105 106 int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, 107 int port, const struct ib_wc *in_wc, 108 const struct ib_grh *in_grh, 109 const void *in_mad, void *response_mad) 110 { 111 struct mlx4_cmd_mailbox *inmailbox, *outmailbox; 112 void *inbox; 113 int err; 114 u32 in_modifier = port; 115 u8 op_modifier = 0; 116 117 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 118 if (IS_ERR(inmailbox)) 119 return PTR_ERR(inmailbox); 120 inbox = inmailbox->buf; 121 122 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 123 if (IS_ERR(outmailbox)) { 124 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 125 return PTR_ERR(outmailbox); 126 } 127 128 memcpy(inbox, in_mad, 256); 129 130 /* 131 * Key check traps can't be generated unless we have in_wc to 132 * tell us where to send the trap. 133 */ 134 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc) 135 op_modifier |= 0x1; 136 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc) 137 op_modifier |= 0x2; 138 if (mlx4_is_mfunc(dev->dev) && 139 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc)) 140 op_modifier |= 0x8; 141 142 if (in_wc) { 143 struct { 144 __be32 my_qpn; 145 u32 reserved1; 146 __be32 rqpn; 147 u8 sl; 148 u8 g_path; 149 u16 reserved2[2]; 150 __be16 pkey; 151 u32 reserved3[11]; 152 u8 grh[40]; 153 } *ext_info; 154 155 memset(inbox + 256, 0, 256); 156 ext_info = inbox + 256; 157 158 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num); 159 ext_info->rqpn = cpu_to_be32(in_wc->src_qp); 160 ext_info->sl = in_wc->sl << 4; 161 ext_info->g_path = in_wc->dlid_path_bits | 162 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 163 ext_info->pkey = cpu_to_be16(in_wc->pkey_index); 164 165 if (in_grh) 166 memcpy(ext_info->grh, in_grh, 40); 167 168 op_modifier |= 0x4; 169 170 in_modifier |= in_wc->slid << 16; 171 } 172 173 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier, 174 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier, 175 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, 176 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED); 177 178 if (!err) 179 memcpy(response_mad, outmailbox->buf, 256); 180 181 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 182 mlx4_free_cmd_mailbox(dev->dev, outmailbox); 183 184 return err; 185 } 186 187 static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl) 188 { 189 struct ib_ah *new_ah; 190 struct ib_ah_attr ah_attr; 191 unsigned long flags; 192 193 if (!dev->send_agent[port_num - 1][0]) 194 return; 195 196 memset(&ah_attr, 0, sizeof ah_attr); 197 ah_attr.dlid = lid; 198 ah_attr.sl = sl; 199 ah_attr.port_num = port_num; 200 201 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd, 202 &ah_attr); 203 if (IS_ERR(new_ah)) 204 return; 205 206 spin_lock_irqsave(&dev->sm_lock, flags); 207 if (dev->sm_ah[port_num - 1]) 208 ib_destroy_ah(dev->sm_ah[port_num - 1]); 209 dev->sm_ah[port_num - 1] = new_ah; 210 spin_unlock_irqrestore(&dev->sm_lock, flags); 211 } 212 213 /* 214 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can 215 * synthesize LID change, Client-Rereg, GID change, and P_Key change events. 216 */ 217 static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad, 218 u16 prev_lid) 219 { 220 struct ib_port_info *pinfo; 221 u16 lid; 222 __be16 *base; 223 u32 bn, pkey_change_bitmap; 224 int i; 225 226 227 struct mlx4_ib_dev *dev = to_mdev(ibdev); 228 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 229 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 230 mad->mad_hdr.method == IB_MGMT_METHOD_SET) 231 switch (mad->mad_hdr.attr_id) { 232 case IB_SMP_ATTR_PORT_INFO: 233 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data; 234 lid = be16_to_cpu(pinfo->lid); 235 236 update_sm_ah(dev, port_num, 237 be16_to_cpu(pinfo->sm_lid), 238 pinfo->neighbormtu_mastersmsl & 0xf); 239 240 if (pinfo->clientrereg_resv_subnetto & 0x80) 241 handle_client_rereg_event(dev, port_num); 242 243 if (prev_lid != lid) 244 handle_lid_change_event(dev, port_num); 245 break; 246 247 case IB_SMP_ATTR_PKEY_TABLE: 248 if (!mlx4_is_mfunc(dev->dev)) { 249 mlx4_ib_dispatch_event(dev, port_num, 250 IB_EVENT_PKEY_CHANGE); 251 break; 252 } 253 254 /* at this point, we are running in the master. 255 * Slaves do not receive SMPs. 256 */ 257 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF; 258 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]); 259 pkey_change_bitmap = 0; 260 for (i = 0; i < 32; i++) { 261 pr_debug("PKEY[%d] = x%x\n", 262 i + bn*32, be16_to_cpu(base[i])); 263 if (be16_to_cpu(base[i]) != 264 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) { 265 pkey_change_bitmap |= (1 << i); 266 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] = 267 be16_to_cpu(base[i]); 268 } 269 } 270 pr_debug("PKEY Change event: port=%d, " 271 "block=0x%x, change_bitmap=0x%x\n", 272 port_num, bn, pkey_change_bitmap); 273 274 if (pkey_change_bitmap) { 275 mlx4_ib_dispatch_event(dev, port_num, 276 IB_EVENT_PKEY_CHANGE); 277 if (!dev->sriov.is_going_down) 278 __propagate_pkey_ev(dev, port_num, bn, 279 pkey_change_bitmap); 280 } 281 break; 282 283 case IB_SMP_ATTR_GUID_INFO: 284 /* paravirtualized master's guid is guid 0 -- does not change */ 285 if (!mlx4_is_master(dev->dev)) 286 mlx4_ib_dispatch_event(dev, port_num, 287 IB_EVENT_GID_CHANGE); 288 /*if master, notify relevant slaves*/ 289 if (mlx4_is_master(dev->dev) && 290 !dev->sriov.is_going_down) { 291 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod); 292 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num, 293 (u8 *)(&((struct ib_smp *)mad)->data)); 294 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num, 295 (u8 *)(&((struct ib_smp *)mad)->data)); 296 } 297 break; 298 299 default: 300 break; 301 } 302 } 303 304 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 305 int block, u32 change_bitmap) 306 { 307 int i, ix, slave, err; 308 int have_event = 0; 309 310 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) { 311 if (slave == mlx4_master_func_num(dev->dev)) 312 continue; 313 if (!mlx4_is_slave_active(dev->dev, slave)) 314 continue; 315 316 have_event = 0; 317 for (i = 0; i < 32; i++) { 318 if (!(change_bitmap & (1 << i))) 319 continue; 320 for (ix = 0; 321 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) { 322 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1] 323 [ix] == i + 32 * block) { 324 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num); 325 pr_debug("propagate_pkey_ev: slave %d," 326 " port %d, ix %d (%d)\n", 327 slave, port_num, ix, err); 328 have_event = 1; 329 break; 330 } 331 } 332 if (have_event) 333 break; 334 } 335 } 336 } 337 338 static void node_desc_override(struct ib_device *dev, 339 struct ib_mad *mad) 340 { 341 unsigned long flags; 342 343 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 344 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 345 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP && 346 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) { 347 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags); 348 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64); 349 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags); 350 } 351 } 352 353 static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad) 354 { 355 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED; 356 struct ib_mad_send_buf *send_buf; 357 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn]; 358 int ret; 359 unsigned long flags; 360 361 if (agent) { 362 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 363 IB_MGMT_MAD_DATA, GFP_ATOMIC, 364 IB_MGMT_BASE_VERSION); 365 if (IS_ERR(send_buf)) 366 return; 367 /* 368 * We rely here on the fact that MLX QPs don't use the 369 * address handle after the send is posted (this is 370 * wrong following the IB spec strictly, but we know 371 * it's OK for our devices). 372 */ 373 spin_lock_irqsave(&dev->sm_lock, flags); 374 memcpy(send_buf->mad, mad, sizeof *mad); 375 if ((send_buf->ah = dev->sm_ah[port_num - 1])) 376 ret = ib_post_send_mad(send_buf, NULL); 377 else 378 ret = -EINVAL; 379 spin_unlock_irqrestore(&dev->sm_lock, flags); 380 381 if (ret) 382 ib_free_send_mad(send_buf); 383 } 384 } 385 386 static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave, 387 struct ib_sa_mad *sa_mad) 388 { 389 int ret = 0; 390 391 /* dispatch to different sa handlers */ 392 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 393 case IB_SA_ATTR_MC_MEMBER_REC: 394 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad); 395 break; 396 default: 397 break; 398 } 399 return ret; 400 } 401 402 int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid) 403 { 404 struct mlx4_ib_dev *dev = to_mdev(ibdev); 405 int i; 406 407 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 408 if (dev->sriov.demux[port - 1].guid_cache[i] == guid) 409 return i; 410 } 411 return -1; 412 } 413 414 415 static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave, 416 u8 port, u16 pkey, u16 *ix) 417 { 418 int i, ret; 419 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF; 420 u16 slot_pkey; 421 422 if (slave == mlx4_master_func_num(dev->dev)) 423 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix); 424 425 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1; 426 427 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) { 428 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix) 429 continue; 430 431 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i]; 432 433 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey); 434 if (ret) 435 continue; 436 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) { 437 if (slot_pkey & 0x8000) { 438 *ix = (u16) pkey_ix; 439 return 0; 440 } else { 441 /* take first partial pkey index found */ 442 if (partial_ix == 0xFF) 443 partial_ix = pkey_ix; 444 } 445 } 446 } 447 448 if (partial_ix < 0xFF) { 449 *ix = (u16) partial_ix; 450 return 0; 451 } 452 453 return -EINVAL; 454 } 455 456 int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, 457 enum ib_qp_type dest_qpt, struct ib_wc *wc, 458 struct ib_grh *grh, struct ib_mad *mad) 459 { 460 struct ib_sge list; 461 struct ib_ud_wr wr; 462 struct ib_send_wr *bad_wr; 463 struct mlx4_ib_demux_pv_ctx *tun_ctx; 464 struct mlx4_ib_demux_pv_qp *tun_qp; 465 struct mlx4_rcv_tunnel_mad *tun_mad; 466 struct ib_ah_attr attr; 467 struct ib_ah *ah; 468 struct ib_qp *src_qp = NULL; 469 unsigned tun_tx_ix = 0; 470 int dqpn; 471 int ret = 0; 472 u16 tun_pkey_ix; 473 u16 cached_pkey; 474 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 475 476 if (dest_qpt > IB_QPT_GSI) 477 return -EINVAL; 478 479 tun_ctx = dev->sriov.demux[port-1].tun[slave]; 480 481 /* check if proxy qp created */ 482 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE) 483 return -EAGAIN; 484 485 if (!dest_qpt) 486 tun_qp = &tun_ctx->qp[0]; 487 else 488 tun_qp = &tun_ctx->qp[1]; 489 490 /* compute P_Key index to put in tunnel header for slave */ 491 if (dest_qpt) { 492 u16 pkey_ix; 493 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey); 494 if (ret) 495 return -EINVAL; 496 497 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix); 498 if (ret) 499 return -EINVAL; 500 tun_pkey_ix = pkey_ix; 501 } else 502 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 503 504 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1; 505 506 /* get tunnel tx data buf for slave */ 507 src_qp = tun_qp->qp; 508 509 /* create ah. Just need an empty one with the port num for the post send. 510 * The driver will set the force loopback bit in post_send */ 511 memset(&attr, 0, sizeof attr); 512 attr.port_num = port; 513 if (is_eth) { 514 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16); 515 attr.ah_flags = IB_AH_GRH; 516 } 517 ah = ib_create_ah(tun_ctx->pd, &attr); 518 if (IS_ERR(ah)) 519 return -ENOMEM; 520 521 /* allocate tunnel tx buf after pass failure returns */ 522 spin_lock(&tun_qp->tx_lock); 523 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >= 524 (MLX4_NUM_TUNNEL_BUFS - 1)) 525 ret = -EAGAIN; 526 else 527 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 528 spin_unlock(&tun_qp->tx_lock); 529 if (ret) 530 goto out; 531 532 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr); 533 if (tun_qp->tx_ring[tun_tx_ix].ah) 534 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah); 535 tun_qp->tx_ring[tun_tx_ix].ah = ah; 536 ib_dma_sync_single_for_cpu(&dev->ib_dev, 537 tun_qp->tx_ring[tun_tx_ix].buf.map, 538 sizeof (struct mlx4_rcv_tunnel_mad), 539 DMA_TO_DEVICE); 540 541 /* copy over to tunnel buffer */ 542 if (grh) 543 memcpy(&tun_mad->grh, grh, sizeof *grh); 544 memcpy(&tun_mad->mad, mad, sizeof *mad); 545 546 /* adjust tunnel data */ 547 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix); 548 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF); 549 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0; 550 551 if (is_eth) { 552 u16 vlan = 0; 553 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan, 554 NULL)) { 555 /* VST mode */ 556 if (vlan != wc->vlan_id) 557 /* Packet vlan is not the VST-assigned vlan. 558 * Drop the packet. 559 */ 560 goto out; 561 else 562 /* Remove the vlan tag before forwarding 563 * the packet to the VF. 564 */ 565 vlan = 0xffff; 566 } else { 567 vlan = wc->vlan_id; 568 } 569 570 tun_mad->hdr.sl_vid = cpu_to_be16(vlan); 571 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4); 572 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2); 573 } else { 574 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12); 575 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid); 576 } 577 578 ib_dma_sync_single_for_device(&dev->ib_dev, 579 tun_qp->tx_ring[tun_tx_ix].buf.map, 580 sizeof (struct mlx4_rcv_tunnel_mad), 581 DMA_TO_DEVICE); 582 583 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map; 584 list.length = sizeof (struct mlx4_rcv_tunnel_mad); 585 list.lkey = tun_ctx->pd->local_dma_lkey; 586 587 wr.ah = ah; 588 wr.port_num = port; 589 wr.remote_qkey = IB_QP_SET_QKEY; 590 wr.remote_qpn = dqpn; 591 wr.wr.next = NULL; 592 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt); 593 wr.wr.sg_list = &list; 594 wr.wr.num_sge = 1; 595 wr.wr.opcode = IB_WR_SEND; 596 wr.wr.send_flags = IB_SEND_SIGNALED; 597 598 ret = ib_post_send(src_qp, &wr.wr, &bad_wr); 599 out: 600 if (ret) 601 ib_destroy_ah(ah); 602 return ret; 603 } 604 605 static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, 606 struct ib_wc *wc, struct ib_grh *grh, 607 struct ib_mad *mad) 608 { 609 struct mlx4_ib_dev *dev = to_mdev(ibdev); 610 int err, other_port; 611 int slave = -1; 612 u8 *slave_id; 613 int is_eth = 0; 614 615 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND) 616 is_eth = 0; 617 else 618 is_eth = 1; 619 620 if (is_eth) { 621 if (!(wc->wc_flags & IB_WC_GRH)) { 622 mlx4_ib_warn(ibdev, "RoCE grh not present.\n"); 623 return -EINVAL; 624 } 625 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) { 626 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); 627 return -EINVAL; 628 } 629 err = mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave); 630 if (err && mlx4_is_mf_bonded(dev->dev)) { 631 other_port = (port == 1) ? 2 : 1; 632 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, grh->dgid.raw, &slave); 633 if (!err) { 634 port = other_port; 635 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n", 636 slave, grh->dgid.raw, port, other_port); 637 } 638 } 639 if (err) { 640 mlx4_ib_warn(ibdev, "failed matching grh\n"); 641 return -ENOENT; 642 } 643 if (slave >= dev->dev->caps.sqp_demux) { 644 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 645 slave, dev->dev->caps.sqp_demux); 646 return -ENOENT; 647 } 648 649 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad)) 650 return 0; 651 652 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 653 if (err) 654 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 655 slave, err); 656 return 0; 657 } 658 659 /* Initially assume that this mad is for us */ 660 slave = mlx4_master_func_num(dev->dev); 661 662 /* See if the slave id is encoded in a response mad */ 663 if (mad->mad_hdr.method & 0x80) { 664 slave_id = (u8 *) &mad->mad_hdr.tid; 665 slave = *slave_id; 666 if (slave != 255) /*255 indicates the dom0*/ 667 *slave_id = 0; /* remap tid */ 668 } 669 670 /* If a grh is present, we demux according to it */ 671 if (wc->wc_flags & IB_WC_GRH) { 672 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id); 673 if (slave < 0) { 674 mlx4_ib_warn(ibdev, "failed matching grh\n"); 675 return -ENOENT; 676 } 677 } 678 /* Class-specific handling */ 679 switch (mad->mad_hdr.mgmt_class) { 680 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 681 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 682 /* 255 indicates the dom0 */ 683 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) { 684 if (!mlx4_vf_smi_enabled(dev->dev, slave, port)) 685 return -EPERM; 686 /* for a VF. drop unsolicited MADs */ 687 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) { 688 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n", 689 slave, mad->mad_hdr.mgmt_class, 690 mad->mad_hdr.method); 691 return -EINVAL; 692 } 693 } 694 break; 695 case IB_MGMT_CLASS_SUBN_ADM: 696 if (mlx4_ib_demux_sa_handler(ibdev, port, slave, 697 (struct ib_sa_mad *) mad)) 698 return 0; 699 break; 700 case IB_MGMT_CLASS_CM: 701 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad)) 702 return 0; 703 break; 704 case IB_MGMT_CLASS_DEVICE_MGMT: 705 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP) 706 return 0; 707 break; 708 default: 709 /* Drop unsupported classes for slaves in tunnel mode */ 710 if (slave != mlx4_master_func_num(dev->dev)) { 711 pr_debug("dropping unsupported ingress mad from class:%d " 712 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave); 713 return 0; 714 } 715 } 716 /*make sure that no slave==255 was not handled yet.*/ 717 if (slave >= dev->dev->caps.sqp_demux) { 718 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 719 slave, dev->dev->caps.sqp_demux); 720 return -ENOENT; 721 } 722 723 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 724 if (err) 725 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 726 slave, err); 727 return 0; 728 } 729 730 static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 731 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 732 const struct ib_mad *in_mad, struct ib_mad *out_mad) 733 { 734 u16 slid, prev_lid = 0; 735 int err; 736 struct ib_port_attr pattr; 737 738 if (in_wc && in_wc->qp->qp_num) { 739 pr_debug("received MAD: slid:%d sqpn:%d " 740 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n", 741 in_wc->slid, in_wc->src_qp, 742 in_wc->dlid_path_bits, 743 in_wc->qp->qp_num, 744 in_wc->wc_flags, 745 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method, 746 be16_to_cpu(in_mad->mad_hdr.attr_id)); 747 if (in_wc->wc_flags & IB_WC_GRH) { 748 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n", 749 be64_to_cpu(in_grh->sgid.global.subnet_prefix), 750 be64_to_cpu(in_grh->sgid.global.interface_id)); 751 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n", 752 be64_to_cpu(in_grh->dgid.global.subnet_prefix), 753 be64_to_cpu(in_grh->dgid.global.interface_id)); 754 } 755 } 756 757 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE); 758 759 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) { 760 forward_trap(to_mdev(ibdev), port_num, in_mad); 761 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 762 } 763 764 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 765 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) { 766 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 767 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET && 768 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS) 769 return IB_MAD_RESULT_SUCCESS; 770 771 /* 772 * Don't process SMInfo queries -- the SMA can't handle them. 773 */ 774 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO) 775 return IB_MAD_RESULT_SUCCESS; 776 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT || 777 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 || 778 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 || 779 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) { 780 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 781 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET) 782 return IB_MAD_RESULT_SUCCESS; 783 } else 784 return IB_MAD_RESULT_SUCCESS; 785 786 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 787 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 788 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET && 789 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO && 790 !ib_query_port(ibdev, port_num, &pattr)) 791 prev_lid = pattr.lid; 792 793 err = mlx4_MAD_IFC(to_mdev(ibdev), 794 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) | 795 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) | 796 MLX4_MAD_IFC_NET_VIEW, 797 port_num, in_wc, in_grh, in_mad, out_mad); 798 if (err) 799 return IB_MAD_RESULT_FAILURE; 800 801 if (!out_mad->mad_hdr.status) { 802 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)) 803 smp_snoop(ibdev, port_num, in_mad, prev_lid); 804 /* slaves get node desc from FW */ 805 if (!mlx4_is_slave(to_mdev(ibdev)->dev)) 806 node_desc_override(ibdev, out_mad); 807 } 808 809 /* set return bit in status of directed route responses */ 810 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) 811 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15); 812 813 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) 814 /* no response for trap repress */ 815 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 816 817 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 818 } 819 820 static void edit_counter(struct mlx4_counter *cnt, void *counters, 821 __be16 attr_id) 822 { 823 switch (attr_id) { 824 case IB_PMA_PORT_COUNTERS: 825 { 826 struct ib_pma_portcounters *pma_cnt = 827 (struct ib_pma_portcounters *)counters; 828 829 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data, 830 (be64_to_cpu(cnt->tx_bytes) >> 2)); 831 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data, 832 (be64_to_cpu(cnt->rx_bytes) >> 2)); 833 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets, 834 be64_to_cpu(cnt->tx_frames)); 835 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets, 836 be64_to_cpu(cnt->rx_frames)); 837 break; 838 } 839 case IB_PMA_PORT_COUNTERS_EXT: 840 { 841 struct ib_pma_portcounters_ext *pma_cnt_ext = 842 (struct ib_pma_portcounters_ext *)counters; 843 844 pma_cnt_ext->port_xmit_data = 845 cpu_to_be64(be64_to_cpu(cnt->tx_bytes) >> 2); 846 pma_cnt_ext->port_rcv_data = 847 cpu_to_be64(be64_to_cpu(cnt->rx_bytes) >> 2); 848 pma_cnt_ext->port_xmit_packets = cnt->tx_frames; 849 pma_cnt_ext->port_rcv_packets = cnt->rx_frames; 850 break; 851 } 852 } 853 } 854 855 static int iboe_process_mad_port_info(void *out_mad) 856 { 857 struct ib_class_port_info cpi = {}; 858 859 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 860 memcpy(out_mad, &cpi, sizeof(cpi)); 861 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 862 } 863 864 static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 865 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 866 const struct ib_mad *in_mad, struct ib_mad *out_mad) 867 { 868 struct mlx4_counter counter_stats; 869 struct mlx4_ib_dev *dev = to_mdev(ibdev); 870 struct counter_index *tmp_counter; 871 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0; 872 873 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 874 return -EINVAL; 875 876 if (in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO) 877 return iboe_process_mad_port_info((void *)(out_mad->data + 40)); 878 879 memset(&counter_stats, 0, sizeof(counter_stats)); 880 mutex_lock(&dev->counters_table[port_num - 1].mutex); 881 list_for_each_entry(tmp_counter, 882 &dev->counters_table[port_num - 1].counters_list, 883 list) { 884 err = mlx4_get_counter_stats(dev->dev, 885 tmp_counter->index, 886 &counter_stats, 0); 887 if (err) { 888 err = IB_MAD_RESULT_FAILURE; 889 stats_avail = 0; 890 break; 891 } 892 stats_avail = 1; 893 } 894 mutex_unlock(&dev->counters_table[port_num - 1].mutex); 895 if (stats_avail) { 896 memset(out_mad->data, 0, sizeof out_mad->data); 897 switch (counter_stats.counter_mode & 0xf) { 898 case 0: 899 edit_counter(&counter_stats, 900 (void *)(out_mad->data + 40), 901 in_mad->mad_hdr.attr_id); 902 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 903 break; 904 default: 905 err = IB_MAD_RESULT_FAILURE; 906 } 907 } 908 909 return err; 910 } 911 912 int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 913 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 914 const struct ib_mad_hdr *in, size_t in_mad_size, 915 struct ib_mad_hdr *out, size_t *out_mad_size, 916 u16 *out_mad_pkey_index) 917 { 918 struct mlx4_ib_dev *dev = to_mdev(ibdev); 919 const struct ib_mad *in_mad = (const struct ib_mad *)in; 920 struct ib_mad *out_mad = (struct ib_mad *)out; 921 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num); 922 923 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) || 924 *out_mad_size != sizeof(*out_mad))) 925 return IB_MAD_RESULT_FAILURE; 926 927 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA 928 * queries, should be called only by VFs and for that specific purpose 929 */ 930 if (link == IB_LINK_LAYER_INFINIBAND) { 931 if (mlx4_is_slave(dev->dev) && 932 (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT && 933 (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS || 934 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT || 935 in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO))) 936 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 937 in_grh, in_mad, out_mad); 938 939 return ib_process_mad(ibdev, mad_flags, port_num, in_wc, 940 in_grh, in_mad, out_mad); 941 } 942 943 if (link == IB_LINK_LAYER_ETHERNET) 944 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 945 in_grh, in_mad, out_mad); 946 947 return -EINVAL; 948 } 949 950 static void send_handler(struct ib_mad_agent *agent, 951 struct ib_mad_send_wc *mad_send_wc) 952 { 953 if (mad_send_wc->send_buf->context[0]) 954 ib_destroy_ah(mad_send_wc->send_buf->context[0]); 955 ib_free_send_mad(mad_send_wc->send_buf); 956 } 957 958 int mlx4_ib_mad_init(struct mlx4_ib_dev *dev) 959 { 960 struct ib_mad_agent *agent; 961 int p, q; 962 int ret; 963 enum rdma_link_layer ll; 964 965 for (p = 0; p < dev->num_ports; ++p) { 966 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1); 967 for (q = 0; q <= 1; ++q) { 968 if (ll == IB_LINK_LAYER_INFINIBAND) { 969 agent = ib_register_mad_agent(&dev->ib_dev, p + 1, 970 q ? IB_QPT_GSI : IB_QPT_SMI, 971 NULL, 0, send_handler, 972 NULL, NULL, 0); 973 if (IS_ERR(agent)) { 974 ret = PTR_ERR(agent); 975 goto err; 976 } 977 dev->send_agent[p][q] = agent; 978 } else 979 dev->send_agent[p][q] = NULL; 980 } 981 } 982 983 return 0; 984 985 err: 986 for (p = 0; p < dev->num_ports; ++p) 987 for (q = 0; q <= 1; ++q) 988 if (dev->send_agent[p][q]) 989 ib_unregister_mad_agent(dev->send_agent[p][q]); 990 991 return ret; 992 } 993 994 void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev) 995 { 996 struct ib_mad_agent *agent; 997 int p, q; 998 999 for (p = 0; p < dev->num_ports; ++p) { 1000 for (q = 0; q <= 1; ++q) { 1001 agent = dev->send_agent[p][q]; 1002 if (agent) { 1003 dev->send_agent[p][q] = NULL; 1004 ib_unregister_mad_agent(agent); 1005 } 1006 } 1007 1008 if (dev->sm_ah[p]) 1009 ib_destroy_ah(dev->sm_ah[p]); 1010 } 1011 } 1012 1013 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num) 1014 { 1015 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE); 1016 1017 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1018 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1019 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK); 1020 } 1021 1022 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num) 1023 { 1024 /* re-configure the alias-guid and mcg's */ 1025 if (mlx4_is_master(dev->dev)) { 1026 mlx4_ib_invalidate_all_guid_record(dev, port_num); 1027 1028 if (!dev->sriov.is_going_down) { 1029 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0); 1030 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1031 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK); 1032 } 1033 } 1034 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER); 1035 } 1036 1037 static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 1038 struct mlx4_eqe *eqe) 1039 { 1040 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe), 1041 GET_MASK_FROM_EQE(eqe)); 1042 } 1043 1044 static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num, 1045 u32 guid_tbl_blk_num, u32 change_bitmap) 1046 { 1047 struct ib_smp *in_mad = NULL; 1048 struct ib_smp *out_mad = NULL; 1049 u16 i; 1050 1051 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev)) 1052 return; 1053 1054 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL); 1055 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 1056 if (!in_mad || !out_mad) { 1057 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n"); 1058 goto out; 1059 } 1060 1061 guid_tbl_blk_num *= 4; 1062 1063 for (i = 0; i < 4; i++) { 1064 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff))) 1065 continue; 1066 memset(in_mad, 0, sizeof *in_mad); 1067 memset(out_mad, 0, sizeof *out_mad); 1068 1069 in_mad->base_version = 1; 1070 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1071 in_mad->class_version = 1; 1072 in_mad->method = IB_MGMT_METHOD_GET; 1073 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 1074 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i); 1075 1076 if (mlx4_MAD_IFC(dev, 1077 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW, 1078 port_num, NULL, NULL, in_mad, out_mad)) { 1079 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n"); 1080 goto out; 1081 } 1082 1083 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i, 1084 port_num, 1085 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1086 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i, 1087 port_num, 1088 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1089 } 1090 1091 out: 1092 kfree(in_mad); 1093 kfree(out_mad); 1094 return; 1095 } 1096 1097 void handle_port_mgmt_change_event(struct work_struct *work) 1098 { 1099 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 1100 struct mlx4_ib_dev *dev = ew->ib_dev; 1101 struct mlx4_eqe *eqe = &(ew->ib_eqe); 1102 u8 port = eqe->event.port_mgmt_change.port; 1103 u32 changed_attr; 1104 u32 tbl_block; 1105 u32 change_bitmap; 1106 1107 switch (eqe->subtype) { 1108 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO: 1109 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr); 1110 1111 /* Update the SM ah - This should be done before handling 1112 the other changed attributes so that MADs can be sent to the SM */ 1113 if (changed_attr & MSTR_SM_CHANGE_MASK) { 1114 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid); 1115 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf; 1116 update_sm_ah(dev, port, lid, sl); 1117 } 1118 1119 /* Check if it is a lid change event */ 1120 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK) 1121 handle_lid_change_event(dev, port); 1122 1123 /* Generate GUID changed event */ 1124 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) { 1125 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1126 /*if master, notify all slaves*/ 1127 if (mlx4_is_master(dev->dev)) 1128 mlx4_gen_slaves_port_mgt_ev(dev->dev, port, 1129 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK); 1130 } 1131 1132 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK) 1133 handle_client_rereg_event(dev, port); 1134 break; 1135 1136 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE: 1137 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE); 1138 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1139 propagate_pkey_ev(dev, port, eqe); 1140 break; 1141 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO: 1142 /* paravirtualized master's guid is guid 0 -- does not change */ 1143 if (!mlx4_is_master(dev->dev)) 1144 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1145 /*if master, notify relevant slaves*/ 1146 else if (!dev->sriov.is_going_down) { 1147 tbl_block = GET_BLK_PTR_FROM_EQE(eqe); 1148 change_bitmap = GET_MASK_FROM_EQE(eqe); 1149 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap); 1150 } 1151 break; 1152 default: 1153 pr_warn("Unsupported subtype 0x%x for " 1154 "Port Management Change event\n", eqe->subtype); 1155 } 1156 1157 kfree(ew); 1158 } 1159 1160 void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, 1161 enum ib_event_type type) 1162 { 1163 struct ib_event event; 1164 1165 event.device = &dev->ib_dev; 1166 event.element.port_num = port_num; 1167 event.event = type; 1168 1169 ib_dispatch_event(&event); 1170 } 1171 1172 static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg) 1173 { 1174 unsigned long flags; 1175 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context; 1176 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1177 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 1178 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE) 1179 queue_work(ctx->wq, &ctx->work); 1180 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 1181 } 1182 1183 static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx, 1184 struct mlx4_ib_demux_pv_qp *tun_qp, 1185 int index) 1186 { 1187 struct ib_sge sg_list; 1188 struct ib_recv_wr recv_wr, *bad_recv_wr; 1189 int size; 1190 1191 size = (tun_qp->qp->qp_type == IB_QPT_UD) ? 1192 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf); 1193 1194 sg_list.addr = tun_qp->ring[index].map; 1195 sg_list.length = size; 1196 sg_list.lkey = ctx->pd->local_dma_lkey; 1197 1198 recv_wr.next = NULL; 1199 recv_wr.sg_list = &sg_list; 1200 recv_wr.num_sge = 1; 1201 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV | 1202 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt); 1203 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map, 1204 size, DMA_FROM_DEVICE); 1205 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr); 1206 } 1207 1208 static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port, 1209 int slave, struct ib_sa_mad *sa_mad) 1210 { 1211 int ret = 0; 1212 1213 /* dispatch to different sa handlers */ 1214 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 1215 case IB_SA_ATTR_MC_MEMBER_REC: 1216 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad); 1217 break; 1218 default: 1219 break; 1220 } 1221 return ret; 1222 } 1223 1224 static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave) 1225 { 1226 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave; 1227 1228 return (qpn >= proxy_start && qpn <= proxy_start + 1); 1229 } 1230 1231 1232 int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, 1233 enum ib_qp_type dest_qpt, u16 pkey_index, 1234 u32 remote_qpn, u32 qkey, struct ib_ah_attr *attr, 1235 u8 *s_mac, u16 vlan_id, struct ib_mad *mad) 1236 { 1237 struct ib_sge list; 1238 struct ib_ud_wr wr; 1239 struct ib_send_wr *bad_wr; 1240 struct mlx4_ib_demux_pv_ctx *sqp_ctx; 1241 struct mlx4_ib_demux_pv_qp *sqp; 1242 struct mlx4_mad_snd_buf *sqp_mad; 1243 struct ib_ah *ah; 1244 struct ib_qp *send_qp = NULL; 1245 unsigned wire_tx_ix = 0; 1246 int ret = 0; 1247 u16 wire_pkey_ix; 1248 int src_qpnum; 1249 u8 sgid_index; 1250 1251 1252 sqp_ctx = dev->sriov.sqps[port-1]; 1253 1254 /* check if proxy qp created */ 1255 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE) 1256 return -EAGAIN; 1257 1258 if (dest_qpt == IB_QPT_SMI) { 1259 src_qpnum = 0; 1260 sqp = &sqp_ctx->qp[0]; 1261 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 1262 } else { 1263 src_qpnum = 1; 1264 sqp = &sqp_ctx->qp[1]; 1265 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index]; 1266 } 1267 1268 send_qp = sqp->qp; 1269 1270 /* create ah */ 1271 sgid_index = attr->grh.sgid_index; 1272 attr->grh.sgid_index = 0; 1273 ah = ib_create_ah(sqp_ctx->pd, attr); 1274 if (IS_ERR(ah)) 1275 return -ENOMEM; 1276 attr->grh.sgid_index = sgid_index; 1277 to_mah(ah)->av.ib.gid_index = sgid_index; 1278 /* get rid of force-loopback bit */ 1279 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF); 1280 spin_lock(&sqp->tx_lock); 1281 if (sqp->tx_ix_head - sqp->tx_ix_tail >= 1282 (MLX4_NUM_TUNNEL_BUFS - 1)) 1283 ret = -EAGAIN; 1284 else 1285 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 1286 spin_unlock(&sqp->tx_lock); 1287 if (ret) 1288 goto out; 1289 1290 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr); 1291 if (sqp->tx_ring[wire_tx_ix].ah) 1292 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah); 1293 sqp->tx_ring[wire_tx_ix].ah = ah; 1294 ib_dma_sync_single_for_cpu(&dev->ib_dev, 1295 sqp->tx_ring[wire_tx_ix].buf.map, 1296 sizeof (struct mlx4_mad_snd_buf), 1297 DMA_TO_DEVICE); 1298 1299 memcpy(&sqp_mad->payload, mad, sizeof *mad); 1300 1301 ib_dma_sync_single_for_device(&dev->ib_dev, 1302 sqp->tx_ring[wire_tx_ix].buf.map, 1303 sizeof (struct mlx4_mad_snd_buf), 1304 DMA_TO_DEVICE); 1305 1306 list.addr = sqp->tx_ring[wire_tx_ix].buf.map; 1307 list.length = sizeof (struct mlx4_mad_snd_buf); 1308 list.lkey = sqp_ctx->pd->local_dma_lkey; 1309 1310 wr.ah = ah; 1311 wr.port_num = port; 1312 wr.pkey_index = wire_pkey_ix; 1313 wr.remote_qkey = qkey; 1314 wr.remote_qpn = remote_qpn; 1315 wr.wr.next = NULL; 1316 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum); 1317 wr.wr.sg_list = &list; 1318 wr.wr.num_sge = 1; 1319 wr.wr.opcode = IB_WR_SEND; 1320 wr.wr.send_flags = IB_SEND_SIGNALED; 1321 if (s_mac) 1322 memcpy(to_mah(ah)->av.eth.s_mac, s_mac, 6); 1323 if (vlan_id < 0x1000) 1324 vlan_id |= (attr->sl & 7) << 13; 1325 to_mah(ah)->av.eth.vlan = cpu_to_be16(vlan_id); 1326 1327 1328 ret = ib_post_send(send_qp, &wr.wr, &bad_wr); 1329 out: 1330 if (ret) 1331 ib_destroy_ah(ah); 1332 return ret; 1333 } 1334 1335 static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port) 1336 { 1337 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1338 return slave; 1339 return mlx4_get_base_gid_ix(dev->dev, slave, port); 1340 } 1341 1342 static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port, 1343 struct ib_ah_attr *ah_attr) 1344 { 1345 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1346 ah_attr->grh.sgid_index = slave; 1347 else 1348 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port); 1349 } 1350 1351 static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc) 1352 { 1353 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1354 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)]; 1355 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1); 1356 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr; 1357 struct mlx4_ib_ah ah; 1358 struct ib_ah_attr ah_attr; 1359 u8 *slave_id; 1360 int slave; 1361 int port; 1362 u16 vlan_id; 1363 1364 /* Get slave that sent this packet */ 1365 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn || 1366 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX || 1367 (wc->src_qp & 0x1) != ctx->port - 1 || 1368 wc->src_qp & 0x4) { 1369 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp); 1370 return; 1371 } 1372 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8; 1373 if (slave != ctx->slave) { 1374 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: " 1375 "belongs to another slave\n", wc->src_qp); 1376 return; 1377 } 1378 1379 /* Map transaction ID */ 1380 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map, 1381 sizeof (struct mlx4_tunnel_mad), 1382 DMA_FROM_DEVICE); 1383 switch (tunnel->mad.mad_hdr.method) { 1384 case IB_MGMT_METHOD_SET: 1385 case IB_MGMT_METHOD_GET: 1386 case IB_MGMT_METHOD_REPORT: 1387 case IB_SA_METHOD_GET_TABLE: 1388 case IB_SA_METHOD_DELETE: 1389 case IB_SA_METHOD_GET_MULTI: 1390 case IB_SA_METHOD_GET_TRACE_TBL: 1391 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid; 1392 if (*slave_id) { 1393 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d " 1394 "class:%d slave:%d\n", *slave_id, 1395 tunnel->mad.mad_hdr.mgmt_class, slave); 1396 return; 1397 } else 1398 *slave_id = slave; 1399 default: 1400 /* nothing */; 1401 } 1402 1403 /* Class-specific handling */ 1404 switch (tunnel->mad.mad_hdr.mgmt_class) { 1405 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 1406 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 1407 if (slave != mlx4_master_func_num(dev->dev) && 1408 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port)) 1409 return; 1410 break; 1411 case IB_MGMT_CLASS_SUBN_ADM: 1412 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave, 1413 (struct ib_sa_mad *) &tunnel->mad)) 1414 return; 1415 break; 1416 case IB_MGMT_CLASS_CM: 1417 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave, 1418 (struct ib_mad *) &tunnel->mad)) 1419 return; 1420 break; 1421 case IB_MGMT_CLASS_DEVICE_MGMT: 1422 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET && 1423 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET) 1424 return; 1425 break; 1426 default: 1427 /* Drop unsupported classes for slaves in tunnel mode */ 1428 if (slave != mlx4_master_func_num(dev->dev)) { 1429 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d " 1430 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave); 1431 return; 1432 } 1433 } 1434 1435 /* We are using standard ib_core services to send the mad, so generate a 1436 * stadard address handle by decoding the tunnelled mlx4_ah fields */ 1437 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av)); 1438 ah.ibah.device = ctx->ib_dev; 1439 1440 port = be32_to_cpu(ah.av.ib.port_pd) >> 24; 1441 port = mlx4_slave_convert_port(dev->dev, slave, port); 1442 if (port < 0) 1443 return; 1444 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff)); 1445 1446 mlx4_ib_query_ah(&ah.ibah, &ah_attr); 1447 if (ah_attr.ah_flags & IB_AH_GRH) 1448 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr); 1449 1450 memcpy(ah_attr.dmac, tunnel->hdr.mac, 6); 1451 vlan_id = be16_to_cpu(tunnel->hdr.vlan); 1452 /* if slave have default vlan use it */ 1453 mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave, 1454 &vlan_id, &ah_attr.sl); 1455 1456 mlx4_ib_send_to_wire(dev, slave, ctx->port, 1457 is_proxy_qp0(dev, wc->src_qp, slave) ? 1458 IB_QPT_SMI : IB_QPT_GSI, 1459 be16_to_cpu(tunnel->hdr.pkey_index), 1460 be32_to_cpu(tunnel->hdr.remote_qpn), 1461 be32_to_cpu(tunnel->hdr.qkey), 1462 &ah_attr, wc->smac, vlan_id, &tunnel->mad); 1463 } 1464 1465 static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1466 enum ib_qp_type qp_type, int is_tun) 1467 { 1468 int i; 1469 struct mlx4_ib_demux_pv_qp *tun_qp; 1470 int rx_buf_size, tx_buf_size; 1471 1472 if (qp_type > IB_QPT_GSI) 1473 return -EINVAL; 1474 1475 tun_qp = &ctx->qp[qp_type]; 1476 1477 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS, 1478 GFP_KERNEL); 1479 if (!tun_qp->ring) 1480 return -ENOMEM; 1481 1482 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS, 1483 sizeof (struct mlx4_ib_tun_tx_buf), 1484 GFP_KERNEL); 1485 if (!tun_qp->tx_ring) { 1486 kfree(tun_qp->ring); 1487 tun_qp->ring = NULL; 1488 return -ENOMEM; 1489 } 1490 1491 if (is_tun) { 1492 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1493 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1494 } else { 1495 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1496 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1497 } 1498 1499 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1500 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL); 1501 if (!tun_qp->ring[i].addr) 1502 goto err; 1503 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev, 1504 tun_qp->ring[i].addr, 1505 rx_buf_size, 1506 DMA_FROM_DEVICE); 1507 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) { 1508 kfree(tun_qp->ring[i].addr); 1509 goto err; 1510 } 1511 } 1512 1513 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1514 tun_qp->tx_ring[i].buf.addr = 1515 kmalloc(tx_buf_size, GFP_KERNEL); 1516 if (!tun_qp->tx_ring[i].buf.addr) 1517 goto tx_err; 1518 tun_qp->tx_ring[i].buf.map = 1519 ib_dma_map_single(ctx->ib_dev, 1520 tun_qp->tx_ring[i].buf.addr, 1521 tx_buf_size, 1522 DMA_TO_DEVICE); 1523 if (ib_dma_mapping_error(ctx->ib_dev, 1524 tun_qp->tx_ring[i].buf.map)) { 1525 kfree(tun_qp->tx_ring[i].buf.addr); 1526 goto tx_err; 1527 } 1528 tun_qp->tx_ring[i].ah = NULL; 1529 } 1530 spin_lock_init(&tun_qp->tx_lock); 1531 tun_qp->tx_ix_head = 0; 1532 tun_qp->tx_ix_tail = 0; 1533 tun_qp->proxy_qpt = qp_type; 1534 1535 return 0; 1536 1537 tx_err: 1538 while (i > 0) { 1539 --i; 1540 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1541 tx_buf_size, DMA_TO_DEVICE); 1542 kfree(tun_qp->tx_ring[i].buf.addr); 1543 } 1544 kfree(tun_qp->tx_ring); 1545 tun_qp->tx_ring = NULL; 1546 i = MLX4_NUM_TUNNEL_BUFS; 1547 err: 1548 while (i > 0) { 1549 --i; 1550 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1551 rx_buf_size, DMA_FROM_DEVICE); 1552 kfree(tun_qp->ring[i].addr); 1553 } 1554 kfree(tun_qp->ring); 1555 tun_qp->ring = NULL; 1556 return -ENOMEM; 1557 } 1558 1559 static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1560 enum ib_qp_type qp_type, int is_tun) 1561 { 1562 int i; 1563 struct mlx4_ib_demux_pv_qp *tun_qp; 1564 int rx_buf_size, tx_buf_size; 1565 1566 if (qp_type > IB_QPT_GSI) 1567 return; 1568 1569 tun_qp = &ctx->qp[qp_type]; 1570 if (is_tun) { 1571 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1572 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1573 } else { 1574 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1575 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1576 } 1577 1578 1579 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1580 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1581 rx_buf_size, DMA_FROM_DEVICE); 1582 kfree(tun_qp->ring[i].addr); 1583 } 1584 1585 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1586 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1587 tx_buf_size, DMA_TO_DEVICE); 1588 kfree(tun_qp->tx_ring[i].buf.addr); 1589 if (tun_qp->tx_ring[i].ah) 1590 ib_destroy_ah(tun_qp->tx_ring[i].ah); 1591 } 1592 kfree(tun_qp->tx_ring); 1593 kfree(tun_qp->ring); 1594 } 1595 1596 static void mlx4_ib_tunnel_comp_worker(struct work_struct *work) 1597 { 1598 struct mlx4_ib_demux_pv_ctx *ctx; 1599 struct mlx4_ib_demux_pv_qp *tun_qp; 1600 struct ib_wc wc; 1601 int ret; 1602 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1603 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1604 1605 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1606 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1607 if (wc.status == IB_WC_SUCCESS) { 1608 switch (wc.opcode) { 1609 case IB_WC_RECV: 1610 mlx4_ib_multiplex_mad(ctx, &wc); 1611 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, 1612 wc.wr_id & 1613 (MLX4_NUM_TUNNEL_BUFS - 1)); 1614 if (ret) 1615 pr_err("Failed reposting tunnel " 1616 "buf:%lld\n", wc.wr_id); 1617 break; 1618 case IB_WC_SEND: 1619 pr_debug("received tunnel send completion:" 1620 "wrid=0x%llx, status=0x%x\n", 1621 wc.wr_id, wc.status); 1622 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1623 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1624 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1625 = NULL; 1626 spin_lock(&tun_qp->tx_lock); 1627 tun_qp->tx_ix_tail++; 1628 spin_unlock(&tun_qp->tx_lock); 1629 1630 break; 1631 default: 1632 break; 1633 } 1634 } else { 1635 pr_debug("mlx4_ib: completion error in tunnel: %d." 1636 " status = %d, wrid = 0x%llx\n", 1637 ctx->slave, wc.status, wc.wr_id); 1638 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1639 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1640 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1641 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1642 = NULL; 1643 spin_lock(&tun_qp->tx_lock); 1644 tun_qp->tx_ix_tail++; 1645 spin_unlock(&tun_qp->tx_lock); 1646 } 1647 } 1648 } 1649 } 1650 1651 static void pv_qp_event_handler(struct ib_event *event, void *qp_context) 1652 { 1653 struct mlx4_ib_demux_pv_ctx *sqp = qp_context; 1654 1655 /* It's worse than that! He's dead, Jim! */ 1656 pr_err("Fatal error (%d) on a MAD QP on port %d\n", 1657 event->event, sqp->port); 1658 } 1659 1660 static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx, 1661 enum ib_qp_type qp_type, int create_tun) 1662 { 1663 int i, ret; 1664 struct mlx4_ib_demux_pv_qp *tun_qp; 1665 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr; 1666 struct ib_qp_attr attr; 1667 int qp_attr_mask_INIT; 1668 1669 if (qp_type > IB_QPT_GSI) 1670 return -EINVAL; 1671 1672 tun_qp = &ctx->qp[qp_type]; 1673 1674 memset(&qp_init_attr, 0, sizeof qp_init_attr); 1675 qp_init_attr.init_attr.send_cq = ctx->cq; 1676 qp_init_attr.init_attr.recv_cq = ctx->cq; 1677 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 1678 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS; 1679 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS; 1680 qp_init_attr.init_attr.cap.max_send_sge = 1; 1681 qp_init_attr.init_attr.cap.max_recv_sge = 1; 1682 if (create_tun) { 1683 qp_init_attr.init_attr.qp_type = IB_QPT_UD; 1684 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP; 1685 qp_init_attr.port = ctx->port; 1686 qp_init_attr.slave = ctx->slave; 1687 qp_init_attr.proxy_qp_type = qp_type; 1688 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | 1689 IB_QP_QKEY | IB_QP_PORT; 1690 } else { 1691 qp_init_attr.init_attr.qp_type = qp_type; 1692 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP; 1693 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY; 1694 } 1695 qp_init_attr.init_attr.port_num = ctx->port; 1696 qp_init_attr.init_attr.qp_context = ctx; 1697 qp_init_attr.init_attr.event_handler = pv_qp_event_handler; 1698 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr); 1699 if (IS_ERR(tun_qp->qp)) { 1700 ret = PTR_ERR(tun_qp->qp); 1701 tun_qp->qp = NULL; 1702 pr_err("Couldn't create %s QP (%d)\n", 1703 create_tun ? "tunnel" : "special", ret); 1704 return ret; 1705 } 1706 1707 memset(&attr, 0, sizeof attr); 1708 attr.qp_state = IB_QPS_INIT; 1709 ret = 0; 1710 if (create_tun) 1711 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave, 1712 ctx->port, IB_DEFAULT_PKEY_FULL, 1713 &attr.pkey_index); 1714 if (ret || !create_tun) 1715 attr.pkey_index = 1716 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0]; 1717 attr.qkey = IB_QP1_QKEY; 1718 attr.port_num = ctx->port; 1719 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT); 1720 if (ret) { 1721 pr_err("Couldn't change %s qp state to INIT (%d)\n", 1722 create_tun ? "tunnel" : "special", ret); 1723 goto err_qp; 1724 } 1725 attr.qp_state = IB_QPS_RTR; 1726 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE); 1727 if (ret) { 1728 pr_err("Couldn't change %s qp state to RTR (%d)\n", 1729 create_tun ? "tunnel" : "special", ret); 1730 goto err_qp; 1731 } 1732 attr.qp_state = IB_QPS_RTS; 1733 attr.sq_psn = 0; 1734 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN); 1735 if (ret) { 1736 pr_err("Couldn't change %s qp state to RTS (%d)\n", 1737 create_tun ? "tunnel" : "special", ret); 1738 goto err_qp; 1739 } 1740 1741 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1742 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i); 1743 if (ret) { 1744 pr_err(" mlx4_ib_post_pv_buf error" 1745 " (err = %d, i = %d)\n", ret, i); 1746 goto err_qp; 1747 } 1748 } 1749 return 0; 1750 1751 err_qp: 1752 ib_destroy_qp(tun_qp->qp); 1753 tun_qp->qp = NULL; 1754 return ret; 1755 } 1756 1757 /* 1758 * IB MAD completion callback for real SQPs 1759 */ 1760 static void mlx4_ib_sqp_comp_worker(struct work_struct *work) 1761 { 1762 struct mlx4_ib_demux_pv_ctx *ctx; 1763 struct mlx4_ib_demux_pv_qp *sqp; 1764 struct ib_wc wc; 1765 struct ib_grh *grh; 1766 struct ib_mad *mad; 1767 1768 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1769 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1770 1771 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1772 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1773 if (wc.status == IB_WC_SUCCESS) { 1774 switch (wc.opcode) { 1775 case IB_WC_SEND: 1776 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1777 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1778 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1779 = NULL; 1780 spin_lock(&sqp->tx_lock); 1781 sqp->tx_ix_tail++; 1782 spin_unlock(&sqp->tx_lock); 1783 break; 1784 case IB_WC_RECV: 1785 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *) 1786 (sqp->ring[wc.wr_id & 1787 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload); 1788 grh = &(((struct mlx4_mad_rcv_buf *) 1789 (sqp->ring[wc.wr_id & 1790 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh); 1791 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad); 1792 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id & 1793 (MLX4_NUM_TUNNEL_BUFS - 1))) 1794 pr_err("Failed reposting SQP " 1795 "buf:%lld\n", wc.wr_id); 1796 break; 1797 default: 1798 BUG_ON(1); 1799 break; 1800 } 1801 } else { 1802 pr_debug("mlx4_ib: completion error in tunnel: %d." 1803 " status = %d, wrid = 0x%llx\n", 1804 ctx->slave, wc.status, wc.wr_id); 1805 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1806 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1807 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1808 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1809 = NULL; 1810 spin_lock(&sqp->tx_lock); 1811 sqp->tx_ix_tail++; 1812 spin_unlock(&sqp->tx_lock); 1813 } 1814 } 1815 } 1816 } 1817 1818 static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port, 1819 struct mlx4_ib_demux_pv_ctx **ret_ctx) 1820 { 1821 struct mlx4_ib_demux_pv_ctx *ctx; 1822 1823 *ret_ctx = NULL; 1824 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL); 1825 if (!ctx) { 1826 pr_err("failed allocating pv resource context " 1827 "for port %d, slave %d\n", port, slave); 1828 return -ENOMEM; 1829 } 1830 1831 ctx->ib_dev = &dev->ib_dev; 1832 ctx->port = port; 1833 ctx->slave = slave; 1834 *ret_ctx = ctx; 1835 return 0; 1836 } 1837 1838 static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port) 1839 { 1840 if (dev->sriov.demux[port - 1].tun[slave]) { 1841 kfree(dev->sriov.demux[port - 1].tun[slave]); 1842 dev->sriov.demux[port - 1].tun[slave] = NULL; 1843 } 1844 } 1845 1846 static int create_pv_resources(struct ib_device *ibdev, int slave, int port, 1847 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx) 1848 { 1849 int ret, cq_size; 1850 struct ib_cq_init_attr cq_attr = {}; 1851 1852 if (ctx->state != DEMUX_PV_STATE_DOWN) 1853 return -EEXIST; 1854 1855 ctx->state = DEMUX_PV_STATE_STARTING; 1856 /* have QP0 only if link layer is IB */ 1857 if (rdma_port_get_link_layer(ibdev, ctx->port) == 1858 IB_LINK_LAYER_INFINIBAND) 1859 ctx->has_smi = 1; 1860 1861 if (ctx->has_smi) { 1862 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun); 1863 if (ret) { 1864 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret); 1865 goto err_out; 1866 } 1867 } 1868 1869 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun); 1870 if (ret) { 1871 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret); 1872 goto err_out_qp0; 1873 } 1874 1875 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS; 1876 if (ctx->has_smi) 1877 cq_size *= 2; 1878 1879 cq_attr.cqe = cq_size; 1880 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler, 1881 NULL, ctx, &cq_attr); 1882 if (IS_ERR(ctx->cq)) { 1883 ret = PTR_ERR(ctx->cq); 1884 pr_err("Couldn't create tunnel CQ (%d)\n", ret); 1885 goto err_buf; 1886 } 1887 1888 ctx->pd = ib_alloc_pd(ctx->ib_dev); 1889 if (IS_ERR(ctx->pd)) { 1890 ret = PTR_ERR(ctx->pd); 1891 pr_err("Couldn't create tunnel PD (%d)\n", ret); 1892 goto err_cq; 1893 } 1894 1895 if (ctx->has_smi) { 1896 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun); 1897 if (ret) { 1898 pr_err("Couldn't create %s QP0 (%d)\n", 1899 create_tun ? "tunnel for" : "", ret); 1900 goto err_pd; 1901 } 1902 } 1903 1904 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun); 1905 if (ret) { 1906 pr_err("Couldn't create %s QP1 (%d)\n", 1907 create_tun ? "tunnel for" : "", ret); 1908 goto err_qp0; 1909 } 1910 1911 if (create_tun) 1912 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker); 1913 else 1914 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker); 1915 1916 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq; 1917 1918 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1919 if (ret) { 1920 pr_err("Couldn't arm tunnel cq (%d)\n", ret); 1921 goto err_wq; 1922 } 1923 ctx->state = DEMUX_PV_STATE_ACTIVE; 1924 return 0; 1925 1926 err_wq: 1927 ctx->wq = NULL; 1928 ib_destroy_qp(ctx->qp[1].qp); 1929 ctx->qp[1].qp = NULL; 1930 1931 1932 err_qp0: 1933 if (ctx->has_smi) 1934 ib_destroy_qp(ctx->qp[0].qp); 1935 ctx->qp[0].qp = NULL; 1936 1937 err_pd: 1938 ib_dealloc_pd(ctx->pd); 1939 ctx->pd = NULL; 1940 1941 err_cq: 1942 ib_destroy_cq(ctx->cq); 1943 ctx->cq = NULL; 1944 1945 err_buf: 1946 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun); 1947 1948 err_out_qp0: 1949 if (ctx->has_smi) 1950 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun); 1951 err_out: 1952 ctx->state = DEMUX_PV_STATE_DOWN; 1953 return ret; 1954 } 1955 1956 static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port, 1957 struct mlx4_ib_demux_pv_ctx *ctx, int flush) 1958 { 1959 if (!ctx) 1960 return; 1961 if (ctx->state > DEMUX_PV_STATE_DOWN) { 1962 ctx->state = DEMUX_PV_STATE_DOWNING; 1963 if (flush) 1964 flush_workqueue(ctx->wq); 1965 if (ctx->has_smi) { 1966 ib_destroy_qp(ctx->qp[0].qp); 1967 ctx->qp[0].qp = NULL; 1968 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1); 1969 } 1970 ib_destroy_qp(ctx->qp[1].qp); 1971 ctx->qp[1].qp = NULL; 1972 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1); 1973 ib_dealloc_pd(ctx->pd); 1974 ctx->pd = NULL; 1975 ib_destroy_cq(ctx->cq); 1976 ctx->cq = NULL; 1977 ctx->state = DEMUX_PV_STATE_DOWN; 1978 } 1979 } 1980 1981 static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave, 1982 int port, int do_init) 1983 { 1984 int ret = 0; 1985 1986 if (!do_init) { 1987 clean_vf_mcast(&dev->sriov.demux[port - 1], slave); 1988 /* for master, destroy real sqp resources */ 1989 if (slave == mlx4_master_func_num(dev->dev)) 1990 destroy_pv_resources(dev, slave, port, 1991 dev->sriov.sqps[port - 1], 1); 1992 /* destroy the tunnel qp resources */ 1993 destroy_pv_resources(dev, slave, port, 1994 dev->sriov.demux[port - 1].tun[slave], 1); 1995 return 0; 1996 } 1997 1998 /* create the tunnel qp resources */ 1999 ret = create_pv_resources(&dev->ib_dev, slave, port, 1, 2000 dev->sriov.demux[port - 1].tun[slave]); 2001 2002 /* for master, create the real sqp resources */ 2003 if (!ret && slave == mlx4_master_func_num(dev->dev)) 2004 ret = create_pv_resources(&dev->ib_dev, slave, port, 0, 2005 dev->sriov.sqps[port - 1]); 2006 return ret; 2007 } 2008 2009 void mlx4_ib_tunnels_update_work(struct work_struct *work) 2010 { 2011 struct mlx4_ib_demux_work *dmxw; 2012 2013 dmxw = container_of(work, struct mlx4_ib_demux_work, work); 2014 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port, 2015 dmxw->do_init); 2016 kfree(dmxw); 2017 return; 2018 } 2019 2020 static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev, 2021 struct mlx4_ib_demux_ctx *ctx, 2022 int port) 2023 { 2024 char name[12]; 2025 int ret = 0; 2026 int i; 2027 2028 ctx->tun = kcalloc(dev->dev->caps.sqp_demux, 2029 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL); 2030 if (!ctx->tun) 2031 return -ENOMEM; 2032 2033 ctx->dev = dev; 2034 ctx->port = port; 2035 ctx->ib_dev = &dev->ib_dev; 2036 2037 for (i = 0; 2038 i < min(dev->dev->caps.sqp_demux, 2039 (u16)(dev->dev->persist->num_vfs + 1)); 2040 i++) { 2041 struct mlx4_active_ports actv_ports = 2042 mlx4_get_active_ports(dev->dev, i); 2043 2044 if (!test_bit(port - 1, actv_ports.ports)) 2045 continue; 2046 2047 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]); 2048 if (ret) { 2049 ret = -ENOMEM; 2050 goto err_mcg; 2051 } 2052 } 2053 2054 ret = mlx4_ib_mcg_port_init(ctx); 2055 if (ret) { 2056 pr_err("Failed initializing mcg para-virt (%d)\n", ret); 2057 goto err_mcg; 2058 } 2059 2060 snprintf(name, sizeof name, "mlx4_ibt%d", port); 2061 ctx->wq = create_singlethread_workqueue(name); 2062 if (!ctx->wq) { 2063 pr_err("Failed to create tunnelling WQ for port %d\n", port); 2064 ret = -ENOMEM; 2065 goto err_wq; 2066 } 2067 2068 snprintf(name, sizeof name, "mlx4_ibud%d", port); 2069 ctx->ud_wq = create_singlethread_workqueue(name); 2070 if (!ctx->ud_wq) { 2071 pr_err("Failed to create up/down WQ for port %d\n", port); 2072 ret = -ENOMEM; 2073 goto err_udwq; 2074 } 2075 2076 return 0; 2077 2078 err_udwq: 2079 destroy_workqueue(ctx->wq); 2080 ctx->wq = NULL; 2081 2082 err_wq: 2083 mlx4_ib_mcg_port_cleanup(ctx, 1); 2084 err_mcg: 2085 for (i = 0; i < dev->dev->caps.sqp_demux; i++) 2086 free_pv_object(dev, i, port); 2087 kfree(ctx->tun); 2088 ctx->tun = NULL; 2089 return ret; 2090 } 2091 2092 static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx) 2093 { 2094 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) { 2095 sqp_ctx->state = DEMUX_PV_STATE_DOWNING; 2096 flush_workqueue(sqp_ctx->wq); 2097 if (sqp_ctx->has_smi) { 2098 ib_destroy_qp(sqp_ctx->qp[0].qp); 2099 sqp_ctx->qp[0].qp = NULL; 2100 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0); 2101 } 2102 ib_destroy_qp(sqp_ctx->qp[1].qp); 2103 sqp_ctx->qp[1].qp = NULL; 2104 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0); 2105 ib_dealloc_pd(sqp_ctx->pd); 2106 sqp_ctx->pd = NULL; 2107 ib_destroy_cq(sqp_ctx->cq); 2108 sqp_ctx->cq = NULL; 2109 sqp_ctx->state = DEMUX_PV_STATE_DOWN; 2110 } 2111 } 2112 2113 static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx) 2114 { 2115 int i; 2116 if (ctx) { 2117 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 2118 mlx4_ib_mcg_port_cleanup(ctx, 1); 2119 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2120 if (!ctx->tun[i]) 2121 continue; 2122 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN) 2123 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING; 2124 } 2125 flush_workqueue(ctx->wq); 2126 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2127 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0); 2128 free_pv_object(dev, i, ctx->port); 2129 } 2130 kfree(ctx->tun); 2131 destroy_workqueue(ctx->ud_wq); 2132 destroy_workqueue(ctx->wq); 2133 } 2134 } 2135 2136 static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init) 2137 { 2138 int i; 2139 2140 if (!mlx4_is_master(dev->dev)) 2141 return; 2142 /* initialize or tear down tunnel QPs for the master */ 2143 for (i = 0; i < dev->dev->caps.num_ports; i++) 2144 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init); 2145 return; 2146 } 2147 2148 int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev) 2149 { 2150 int i = 0; 2151 int err; 2152 2153 if (!mlx4_is_mfunc(dev->dev)) 2154 return 0; 2155 2156 dev->sriov.is_going_down = 0; 2157 spin_lock_init(&dev->sriov.going_down_lock); 2158 mlx4_ib_cm_paravirt_init(dev); 2159 2160 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n"); 2161 2162 if (mlx4_is_slave(dev->dev)) { 2163 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n"); 2164 return 0; 2165 } 2166 2167 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2168 if (i == mlx4_master_func_num(dev->dev)) 2169 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid); 2170 else 2171 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid()); 2172 } 2173 2174 err = mlx4_ib_init_alias_guid_service(dev); 2175 if (err) { 2176 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n"); 2177 goto paravirt_err; 2178 } 2179 err = mlx4_ib_device_register_sysfs(dev); 2180 if (err) { 2181 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n"); 2182 goto sysfs_err; 2183 } 2184 2185 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n", 2186 dev->dev->caps.sqp_demux); 2187 for (i = 0; i < dev->num_ports; i++) { 2188 union ib_gid gid; 2189 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1); 2190 if (err) 2191 goto demux_err; 2192 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id; 2193 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1, 2194 &dev->sriov.sqps[i]); 2195 if (err) 2196 goto demux_err; 2197 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1); 2198 if (err) 2199 goto free_pv; 2200 } 2201 mlx4_ib_master_tunnels(dev, 1); 2202 return 0; 2203 2204 free_pv: 2205 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2206 demux_err: 2207 while (--i >= 0) { 2208 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2209 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2210 } 2211 mlx4_ib_device_unregister_sysfs(dev); 2212 2213 sysfs_err: 2214 mlx4_ib_destroy_alias_guid_service(dev); 2215 2216 paravirt_err: 2217 mlx4_ib_cm_paravirt_clean(dev, -1); 2218 2219 return err; 2220 } 2221 2222 void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev) 2223 { 2224 int i; 2225 unsigned long flags; 2226 2227 if (!mlx4_is_mfunc(dev->dev)) 2228 return; 2229 2230 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 2231 dev->sriov.is_going_down = 1; 2232 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 2233 if (mlx4_is_master(dev->dev)) { 2234 for (i = 0; i < dev->num_ports; i++) { 2235 flush_workqueue(dev->sriov.demux[i].ud_wq); 2236 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]); 2237 kfree(dev->sriov.sqps[i]); 2238 dev->sriov.sqps[i] = NULL; 2239 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2240 } 2241 2242 mlx4_ib_cm_paravirt_clean(dev, -1); 2243 mlx4_ib_destroy_alias_guid_service(dev); 2244 mlx4_ib_device_unregister_sysfs(dev); 2245 } 2246 } 2247