1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/mlx4/qp.h> 36 #include <linux/mlx4/srq.h> 37 #include <linux/slab.h> 38 39 #include "mlx4_ib.h" 40 #include <rdma/mlx4-abi.h> 41 #include <rdma/uverbs_ioctl.h> 42 43 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 44 { 45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 46 ibcq->comp_handler(ibcq, ibcq->cq_context); 47 } 48 49 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 50 { 51 struct ib_event event; 52 struct ib_cq *ibcq; 53 54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 55 pr_warn("Unexpected event type %d " 56 "on CQ %06x\n", type, cq->cqn); 57 return; 58 } 59 60 ibcq = &to_mibcq(cq)->ibcq; 61 if (ibcq->event_handler) { 62 event.device = ibcq->device; 63 event.event = IB_EVENT_CQ_ERR; 64 event.element.cq = ibcq; 65 ibcq->event_handler(&event, ibcq->cq_context); 66 } 67 } 68 69 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 70 { 71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 72 } 73 74 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 75 { 76 return get_cqe_from_buf(&cq->buf, n); 77 } 78 79 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 80 { 81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 83 84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 86 } 87 88 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 89 { 90 return get_sw_cqe(cq, cq->mcq.cons_index); 91 } 92 93 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 94 { 95 struct mlx4_ib_cq *mcq = to_mcq(cq); 96 struct mlx4_ib_dev *dev = to_mdev(cq->device); 97 98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 99 } 100 101 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 102 { 103 int err; 104 105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 106 PAGE_SIZE * 2, &buf->buf); 107 108 if (err) 109 goto out; 110 111 buf->entry_size = dev->dev->caps.cqe_size; 112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 113 &buf->mtt); 114 if (err) 115 goto err_buf; 116 117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); 118 if (err) 119 goto err_mtt; 120 121 return 0; 122 123 err_mtt: 124 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 125 126 err_buf: 127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 128 129 out: 130 return err; 131 } 132 133 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 134 { 135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 136 } 137 138 #define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION 139 int mlx4_ib_create_user_cq(struct ib_cq *ibcq, 140 const struct ib_cq_init_attr *attr, 141 struct uverbs_attr_bundle *attrs) 142 { 143 struct ib_udata *udata = &attrs->driver_udata; 144 struct ib_device *ibdev = ibcq->device; 145 struct mlx4_ib_create_cq_resp uresp = {}; 146 int entries = attr->cqe; 147 int vector = attr->comp_vector; 148 struct mlx4_ib_dev *dev = to_mdev(ibdev); 149 struct mlx4_ib_cq *cq = to_mcq(ibcq); 150 struct mlx4_ib_create_cq ucmd; 151 int cqe_size = dev->dev->caps.cqe_size; 152 void *buf_addr; 153 int shift; 154 int n; 155 int err; 156 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 157 udata, struct mlx4_ib_ucontext, ibucontext); 158 159 if (attr->cqe > dev->dev->caps.max_cqes) 160 return -EINVAL; 161 162 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 163 return -EINVAL; 164 165 entries = roundup_pow_of_two(entries + 1); 166 cq->ibcq.cqe = entries - 1; 167 mutex_init(&cq->resize_mutex); 168 spin_lock_init(&cq->lock); 169 INIT_LIST_HEAD(&cq->send_qp_list); 170 INIT_LIST_HEAD(&cq->recv_qp_list); 171 172 err = ib_copy_validate_udata_in(udata, ucmd, db_addr); 173 if (err) 174 goto err_cq; 175 176 cq->umem = ib_umem_get_cq_buf(&dev->ib_dev, attrs, entries * cqe_size, 177 IB_ACCESS_LOCAL_WRITE); 178 if (IS_ERR(cq->umem)) { 179 err = PTR_ERR(cq->umem); 180 goto err_cq; 181 } 182 if (cq->umem) { 183 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SW_CQ_INIT) { 184 err = -EOPNOTSUPP; 185 goto err_umem; 186 } 187 } else { 188 cq->umem = ib_umem_get_va(&dev->ib_dev, ucmd.buf_addr, 189 entries * cqe_size, 190 IB_ACCESS_LOCAL_WRITE); 191 if (IS_ERR(cq->umem)) { 192 err = PTR_ERR(cq->umem); 193 goto err_cq; 194 } 195 } 196 197 buf_addr = (void *)(unsigned long)ucmd.buf_addr; 198 199 shift = mlx4_ib_umem_calc_optimal_mtt_size(cq->umem, 0, &n); 200 if (shift < 0) { 201 err = shift; 202 goto err_umem; 203 } 204 205 err = mlx4_mtt_init(dev->dev, n, shift, &cq->buf.mtt); 206 if (err) 207 goto err_umem; 208 209 err = mlx4_ib_umem_write_mtt(dev, &cq->buf.mtt, cq->umem); 210 if (err) 211 goto err_mtt; 212 213 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &cq->db); 214 if (err) 215 goto err_mtt; 216 217 if (dev->eq_table) 218 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 219 220 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, &context->uar, 221 cq->db.dma, &cq->mcq, vector, 0, 222 attr->flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION, 223 buf_addr, true); 224 if (err) 225 goto err_dbmap; 226 227 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp; 228 cq->mcq.event = mlx4_ib_cq_event; 229 cq->mcq.usage = MLX4_RES_USAGE_USER_VERBS; 230 231 uresp.cqn = cq->mcq.cqn; 232 err = ib_respond_udata(udata, uresp); 233 if (err) 234 goto err_cq_free; 235 236 return 0; 237 238 err_cq_free: 239 mlx4_cq_free(dev->dev, &cq->mcq); 240 241 err_dbmap: 242 mlx4_ib_db_unmap_user(context, &cq->db); 243 244 err_mtt: 245 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 246 247 err_umem: 248 ib_umem_release(cq->umem); 249 250 err_cq: 251 return err; 252 } 253 254 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 255 struct uverbs_attr_bundle *attrs) 256 { 257 struct ib_device *ibdev = ibcq->device; 258 int entries = attr->cqe; 259 int vector = attr->comp_vector; 260 struct mlx4_ib_dev *dev = to_mdev(ibdev); 261 struct mlx4_ib_cq *cq = to_mcq(ibcq); 262 void *buf_addr; 263 int err; 264 265 if (attr->cqe > dev->dev->caps.max_cqes) 266 return -EINVAL; 267 268 entries = roundup_pow_of_two(entries + 1); 269 cq->ibcq.cqe = entries - 1; 270 mutex_init(&cq->resize_mutex); 271 spin_lock_init(&cq->lock); 272 INIT_LIST_HEAD(&cq->send_qp_list); 273 INIT_LIST_HEAD(&cq->recv_qp_list); 274 275 err = mlx4_db_alloc(dev->dev, &cq->db, 1); 276 if (err) 277 return err; 278 279 cq->mcq.set_ci_db = cq->db.db; 280 cq->mcq.arm_db = cq->db.db + 1; 281 *cq->mcq.set_ci_db = 0; 282 *cq->mcq.arm_db = 0; 283 284 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 285 if (err) 286 goto err_db; 287 288 buf_addr = &cq->buf.buf; 289 290 if (dev->eq_table) 291 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 292 293 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, &dev->priv_uar, 294 cq->db.dma, &cq->mcq, vector, 0, 0, 295 buf_addr, false); 296 if (err) 297 goto err_buf; 298 299 cq->mcq.comp = mlx4_ib_cq_comp; 300 cq->mcq.event = mlx4_ib_cq_event; 301 cq->mcq.usage = MLX4_RES_USAGE_DRIVER; 302 303 return 0; 304 305 err_buf: 306 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 307 308 err_db: 309 mlx4_db_free(dev->dev, &cq->db); 310 return err; 311 } 312 313 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 314 int entries) 315 { 316 int err; 317 318 if (cq->resize_buf) 319 return -EBUSY; 320 321 cq->resize_buf = kmalloc_obj(*cq->resize_buf); 322 if (!cq->resize_buf) 323 return -ENOMEM; 324 325 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 326 if (err) { 327 kfree(cq->resize_buf); 328 cq->resize_buf = NULL; 329 return err; 330 } 331 332 cq->resize_buf->cqe = entries - 1; 333 334 return 0; 335 } 336 337 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 338 int entries, struct ib_udata *udata) 339 { 340 struct mlx4_ib_resize_cq ucmd; 341 int cqe_size = dev->dev->caps.cqe_size; 342 int shift; 343 int n; 344 int err; 345 346 if (cq->resize_umem) 347 return -EBUSY; 348 349 err = ib_copy_validate_udata_in(udata, ucmd, buf_addr); 350 if (err) 351 return err; 352 353 cq->resize_buf = kmalloc_obj(*cq->resize_buf); 354 if (!cq->resize_buf) 355 return -ENOMEM; 356 357 cq->resize_umem = ib_umem_get_va(&dev->ib_dev, ucmd.buf_addr, 358 entries * cqe_size, 359 IB_ACCESS_LOCAL_WRITE); 360 if (IS_ERR(cq->resize_umem)) { 361 err = PTR_ERR(cq->resize_umem); 362 goto err_buf; 363 } 364 365 shift = mlx4_ib_umem_calc_optimal_mtt_size(cq->resize_umem, 0, &n); 366 if (shift < 0) { 367 err = shift; 368 goto err_umem; 369 } 370 371 err = mlx4_mtt_init(dev->dev, n, shift, &cq->resize_buf->buf.mtt); 372 if (err) 373 goto err_umem; 374 375 err = mlx4_ib_umem_write_mtt(dev, &cq->resize_buf->buf.mtt, 376 cq->resize_umem); 377 if (err) 378 goto err_mtt; 379 380 cq->resize_buf->cqe = entries - 1; 381 382 return 0; 383 384 err_mtt: 385 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 386 387 err_umem: 388 ib_umem_release(cq->resize_umem); 389 390 err_buf: 391 kfree(cq->resize_buf); 392 cq->resize_buf = NULL; 393 return err; 394 } 395 396 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 397 { 398 u32 i; 399 400 i = cq->mcq.cons_index; 401 while (get_sw_cqe(cq, i)) 402 ++i; 403 404 return i - cq->mcq.cons_index; 405 } 406 407 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 408 { 409 struct mlx4_cqe *cqe, *new_cqe; 410 int i; 411 int cqe_size = cq->buf.entry_size; 412 int cqe_inc = cqe_size == 64 ? 1 : 0; 413 414 i = cq->mcq.cons_index; 415 cqe = get_cqe(cq, i & cq->ibcq.cqe); 416 cqe += cqe_inc; 417 418 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 419 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 420 (i + 1) & cq->resize_buf->cqe); 421 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 422 new_cqe += cqe_inc; 423 424 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 425 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 426 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 427 cqe += cqe_inc; 428 } 429 ++cq->mcq.cons_index; 430 } 431 432 int mlx4_ib_resize_cq(struct ib_cq *ibcq, unsigned int entries, 433 struct ib_udata *udata) 434 { 435 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 436 struct mlx4_ib_cq *cq = to_mcq(ibcq); 437 struct mlx4_mtt mtt; 438 int outst_cqe; 439 int err; 440 441 mutex_lock(&cq->resize_mutex); 442 if (entries > dev->dev->caps.max_cqes) { 443 err = -EINVAL; 444 goto out; 445 } 446 447 entries = roundup_pow_of_two(entries + 1); 448 if (entries == ibcq->cqe + 1) { 449 err = 0; 450 goto out; 451 } 452 453 if (entries > dev->dev->caps.max_cqes + 1) { 454 err = -EINVAL; 455 goto out; 456 } 457 458 if (ibcq->uobject) { 459 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 460 if (err) 461 goto out; 462 } else { 463 /* Can't be smaller than the number of outstanding CQEs */ 464 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 465 if (entries < outst_cqe + 1) { 466 err = -EINVAL; 467 goto out; 468 } 469 470 err = mlx4_alloc_resize_buf(dev, cq, entries); 471 if (err) 472 goto out; 473 } 474 475 mtt = cq->buf.mtt; 476 477 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 478 if (err) 479 goto err_buf; 480 481 mlx4_mtt_cleanup(dev->dev, &mtt); 482 if (ibcq->uobject) { 483 cq->buf = cq->resize_buf->buf; 484 cq->ibcq.cqe = cq->resize_buf->cqe; 485 ib_umem_release(cq->umem); 486 cq->umem = cq->resize_umem; 487 488 kfree(cq->resize_buf); 489 cq->resize_buf = NULL; 490 cq->resize_umem = NULL; 491 } else { 492 struct mlx4_ib_cq_buf tmp_buf; 493 int tmp_cqe = 0; 494 495 spin_lock_irq(&cq->lock); 496 if (cq->resize_buf) { 497 mlx4_ib_cq_resize_copy_cqes(cq); 498 tmp_buf = cq->buf; 499 tmp_cqe = cq->ibcq.cqe; 500 cq->buf = cq->resize_buf->buf; 501 cq->ibcq.cqe = cq->resize_buf->cqe; 502 503 kfree(cq->resize_buf); 504 cq->resize_buf = NULL; 505 } 506 spin_unlock_irq(&cq->lock); 507 508 if (tmp_cqe) 509 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 510 } 511 512 goto out; 513 514 err_buf: 515 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 516 if (!ibcq->uobject) 517 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 518 cq->resize_buf->cqe); 519 520 kfree(cq->resize_buf); 521 cq->resize_buf = NULL; 522 523 ib_umem_release(cq->resize_umem); 524 cq->resize_umem = NULL; 525 out: 526 mutex_unlock(&cq->resize_mutex); 527 528 return err; 529 } 530 531 int mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 532 { 533 struct mlx4_ib_dev *dev = to_mdev(cq->device); 534 struct mlx4_ib_cq *mcq = to_mcq(cq); 535 536 mlx4_cq_free(dev->dev, &mcq->mcq); 537 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 538 539 if (udata) { 540 mlx4_ib_db_unmap_user( 541 rdma_udata_to_drv_context( 542 udata, 543 struct mlx4_ib_ucontext, 544 ibucontext), 545 &mcq->db); 546 ib_umem_release(mcq->umem); 547 } else { 548 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 549 mlx4_db_free(dev->dev, &mcq->db); 550 } 551 return 0; 552 } 553 554 static void dump_cqe(void *cqe) 555 { 556 __be32 *buf = cqe; 557 558 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 559 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 560 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 561 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 562 } 563 564 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 565 struct ib_wc *wc) 566 { 567 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 568 pr_debug("local QP operation err " 569 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 570 "opcode = %02x)\n", 571 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 572 cqe->vendor_err_syndrome, 573 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 574 dump_cqe(cqe); 575 } 576 577 switch (cqe->syndrome) { 578 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 579 wc->status = IB_WC_LOC_LEN_ERR; 580 break; 581 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 582 wc->status = IB_WC_LOC_QP_OP_ERR; 583 break; 584 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 585 wc->status = IB_WC_LOC_PROT_ERR; 586 break; 587 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 588 wc->status = IB_WC_WR_FLUSH_ERR; 589 break; 590 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 591 wc->status = IB_WC_MW_BIND_ERR; 592 break; 593 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 594 wc->status = IB_WC_BAD_RESP_ERR; 595 break; 596 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 597 wc->status = IB_WC_LOC_ACCESS_ERR; 598 break; 599 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 600 wc->status = IB_WC_REM_INV_REQ_ERR; 601 break; 602 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 603 wc->status = IB_WC_REM_ACCESS_ERR; 604 break; 605 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 606 wc->status = IB_WC_REM_OP_ERR; 607 break; 608 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 609 wc->status = IB_WC_RETRY_EXC_ERR; 610 break; 611 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 612 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 613 break; 614 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 615 wc->status = IB_WC_REM_ABORT_ERR; 616 break; 617 default: 618 wc->status = IB_WC_GENERAL_ERR; 619 break; 620 } 621 622 wc->vendor_err = cqe->vendor_err_syndrome; 623 } 624 625 static int mlx4_ib_ipoib_csum_ok(__be16 status, u8 badfcs_enc, __be16 checksum) 626 { 627 return ((badfcs_enc & MLX4_CQE_STATUS_L4_CSUM) || 628 ((status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && 629 (status & cpu_to_be16(MLX4_CQE_STATUS_TCP | 630 MLX4_CQE_STATUS_UDP)) && 631 (checksum == cpu_to_be16(0xffff)))); 632 } 633 634 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 635 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 636 { 637 struct mlx4_ib_proxy_sqp_hdr *hdr; 638 639 ib_dma_sync_single_for_cpu(qp->ibqp.device, 640 qp->sqp_proxy_rcv[tail].map, 641 sizeof (struct mlx4_ib_proxy_sqp_hdr), 642 DMA_FROM_DEVICE); 643 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 644 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 645 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 646 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 647 wc->dlid_path_bits = 0; 648 649 if (is_eth) { 650 wc->slid = 0; 651 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 652 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 653 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 654 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 655 } else { 656 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 657 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 658 } 659 } 660 661 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 662 struct ib_wc *wc, int *npolled, int is_send) 663 { 664 struct mlx4_ib_wq *wq; 665 unsigned cur; 666 int i; 667 668 wq = is_send ? &qp->sq : &qp->rq; 669 cur = wq->head - wq->tail; 670 671 if (cur == 0) 672 return; 673 674 for (i = 0; i < cur && *npolled < num_entries; i++) { 675 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 676 wc->status = IB_WC_WR_FLUSH_ERR; 677 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 678 wq->tail++; 679 (*npolled)++; 680 wc->qp = &qp->ibqp; 681 wc++; 682 } 683 } 684 685 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 686 struct ib_wc *wc, int *npolled) 687 { 688 struct mlx4_ib_qp *qp; 689 690 *npolled = 0; 691 /* Find uncompleted WQEs belonging to that cq and return 692 * simulated FLUSH_ERR completions 693 */ 694 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 695 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 696 if (*npolled >= num_entries) 697 goto out; 698 } 699 700 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 701 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 702 if (*npolled >= num_entries) 703 goto out; 704 } 705 706 out: 707 return; 708 } 709 710 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 711 struct mlx4_ib_qp **cur_qp, 712 struct ib_wc *wc) 713 { 714 struct mlx4_cqe *cqe; 715 struct mlx4_qp *mqp; 716 struct mlx4_ib_wq *wq; 717 struct mlx4_ib_srq *srq; 718 struct mlx4_srq *msrq = NULL; 719 int is_send; 720 int is_error; 721 int is_eth; 722 u32 g_mlpath_rqpn; 723 u16 wqe_ctr; 724 unsigned tail = 0; 725 726 repoll: 727 cqe = next_cqe_sw(cq); 728 if (!cqe) 729 return -EAGAIN; 730 731 if (cq->buf.entry_size == 64) 732 cqe++; 733 734 ++cq->mcq.cons_index; 735 736 /* 737 * Make sure we read CQ entry contents after we've checked the 738 * ownership bit. 739 */ 740 rmb(); 741 742 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 743 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 744 MLX4_CQE_OPCODE_ERROR; 745 746 /* Resize CQ in progress */ 747 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 748 if (cq->resize_buf) { 749 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 750 751 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 752 cq->buf = cq->resize_buf->buf; 753 cq->ibcq.cqe = cq->resize_buf->cqe; 754 755 kfree(cq->resize_buf); 756 cq->resize_buf = NULL; 757 } 758 759 goto repoll; 760 } 761 762 if (!*cur_qp || 763 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 764 /* 765 * We do not have to take the QP table lock here, 766 * because CQs will be locked while QPs are removed 767 * from the table. 768 */ 769 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 770 be32_to_cpu(cqe->vlan_my_qpn)); 771 *cur_qp = to_mibqp(mqp); 772 } 773 774 wc->qp = &(*cur_qp)->ibqp; 775 776 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 777 u32 srq_num; 778 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 779 srq_num = g_mlpath_rqpn & 0xffffff; 780 /* SRQ is also in the radix tree */ 781 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 782 srq_num); 783 } 784 785 if (is_send) { 786 wq = &(*cur_qp)->sq; 787 if (!(*cur_qp)->sq_signal_bits) { 788 wqe_ctr = be16_to_cpu(cqe->wqe_index); 789 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 790 } 791 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 792 ++wq->tail; 793 } else if ((*cur_qp)->ibqp.srq) { 794 srq = to_msrq((*cur_qp)->ibqp.srq); 795 wqe_ctr = be16_to_cpu(cqe->wqe_index); 796 wc->wr_id = srq->wrid[wqe_ctr]; 797 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 798 } else if (msrq) { 799 srq = to_mibsrq(msrq); 800 wqe_ctr = be16_to_cpu(cqe->wqe_index); 801 wc->wr_id = srq->wrid[wqe_ctr]; 802 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 803 } else { 804 wq = &(*cur_qp)->rq; 805 tail = wq->tail & (wq->wqe_cnt - 1); 806 wc->wr_id = wq->wrid[tail]; 807 ++wq->tail; 808 } 809 810 if (unlikely(is_error)) { 811 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 812 return 0; 813 } 814 815 wc->status = IB_WC_SUCCESS; 816 817 if (is_send) { 818 wc->wc_flags = 0; 819 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 820 case MLX4_OPCODE_RDMA_WRITE_IMM: 821 wc->wc_flags |= IB_WC_WITH_IMM; 822 fallthrough; 823 case MLX4_OPCODE_RDMA_WRITE: 824 wc->opcode = IB_WC_RDMA_WRITE; 825 break; 826 case MLX4_OPCODE_SEND_IMM: 827 wc->wc_flags |= IB_WC_WITH_IMM; 828 fallthrough; 829 case MLX4_OPCODE_SEND: 830 case MLX4_OPCODE_SEND_INVAL: 831 wc->opcode = IB_WC_SEND; 832 break; 833 case MLX4_OPCODE_RDMA_READ: 834 wc->opcode = IB_WC_RDMA_READ; 835 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 836 break; 837 case MLX4_OPCODE_ATOMIC_CS: 838 wc->opcode = IB_WC_COMP_SWAP; 839 wc->byte_len = 8; 840 break; 841 case MLX4_OPCODE_ATOMIC_FA: 842 wc->opcode = IB_WC_FETCH_ADD; 843 wc->byte_len = 8; 844 break; 845 case MLX4_OPCODE_MASKED_ATOMIC_CS: 846 wc->opcode = IB_WC_MASKED_COMP_SWAP; 847 wc->byte_len = 8; 848 break; 849 case MLX4_OPCODE_MASKED_ATOMIC_FA: 850 wc->opcode = IB_WC_MASKED_FETCH_ADD; 851 wc->byte_len = 8; 852 break; 853 case MLX4_OPCODE_LSO: 854 wc->opcode = IB_WC_LSO; 855 break; 856 case MLX4_OPCODE_FMR: 857 wc->opcode = IB_WC_REG_MR; 858 break; 859 case MLX4_OPCODE_LOCAL_INVAL: 860 wc->opcode = IB_WC_LOCAL_INV; 861 break; 862 } 863 } else { 864 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 865 866 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 867 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 868 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 869 wc->wc_flags = IB_WC_WITH_IMM; 870 wc->ex.imm_data = cqe->immed_rss_invalid; 871 break; 872 case MLX4_RECV_OPCODE_SEND_INVAL: 873 wc->opcode = IB_WC_RECV; 874 wc->wc_flags = IB_WC_WITH_INVALIDATE; 875 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 876 break; 877 case MLX4_RECV_OPCODE_SEND: 878 wc->opcode = IB_WC_RECV; 879 wc->wc_flags = 0; 880 break; 881 case MLX4_RECV_OPCODE_SEND_IMM: 882 wc->opcode = IB_WC_RECV; 883 wc->wc_flags = IB_WC_WITH_IMM; 884 wc->ex.imm_data = cqe->immed_rss_invalid; 885 break; 886 } 887 888 is_eth = (rdma_port_get_link_layer(wc->qp->device, 889 (*cur_qp)->port) == 890 IB_LINK_LAYER_ETHERNET); 891 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 892 if ((*cur_qp)->mlx4_ib_qp_type & 893 (MLX4_IB_QPT_PROXY_SMI_OWNER | 894 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 895 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 896 is_eth); 897 return 0; 898 } 899 } 900 901 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 902 wc->src_qp = g_mlpath_rqpn & 0xffffff; 903 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 904 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 905 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 906 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 907 cqe->badfcs_enc, 908 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 909 if (is_eth) { 910 wc->slid = 0; 911 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 912 if (be32_to_cpu(cqe->vlan_my_qpn) & 913 MLX4_CQE_CVLAN_PRESENT_MASK) { 914 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 915 MLX4_CQE_VID_MASK; 916 } else { 917 wc->vlan_id = 0xffff; 918 } 919 memcpy(wc->smac, cqe->smac, ETH_ALEN); 920 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 921 } else { 922 wc->slid = be16_to_cpu(cqe->rlid); 923 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 924 wc->vlan_id = 0xffff; 925 } 926 } 927 928 return 0; 929 } 930 931 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 932 { 933 struct mlx4_ib_cq *cq = to_mcq(ibcq); 934 struct mlx4_ib_qp *cur_qp = NULL; 935 unsigned long flags; 936 int npolled; 937 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 938 939 spin_lock_irqsave(&cq->lock, flags); 940 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 941 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 942 goto out; 943 } 944 945 for (npolled = 0; npolled < num_entries; ++npolled) { 946 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 947 break; 948 } 949 950 mlx4_cq_set_ci(&cq->mcq); 951 952 out: 953 spin_unlock_irqrestore(&cq->lock, flags); 954 955 return npolled; 956 } 957 958 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 959 { 960 mlx4_cq_arm(&to_mcq(ibcq)->mcq, 961 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 962 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 963 to_mdev(ibcq->device)->uar_map, 964 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); 965 966 return 0; 967 } 968 969 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 970 { 971 u32 prod_index; 972 int nfreed = 0; 973 struct mlx4_cqe *cqe, *dest; 974 u8 owner_bit; 975 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 976 977 /* 978 * First we need to find the current producer index, so we 979 * know where to start cleaning from. It doesn't matter if HW 980 * adds new entries after this loop -- the QP we're worried 981 * about is already in RESET, so the new entries won't come 982 * from our QP and therefore don't need to be checked. 983 */ 984 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 985 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 986 break; 987 988 /* 989 * Now sweep backwards through the CQ, removing CQ entries 990 * that match our QP by copying older entries on top of them. 991 */ 992 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 993 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 994 cqe += cqe_inc; 995 996 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 997 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 998 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 999 ++nfreed; 1000 } else if (nfreed) { 1001 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1002 dest += cqe_inc; 1003 1004 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 1005 memcpy(dest, cqe, sizeof *cqe); 1006 dest->owner_sr_opcode = owner_bit | 1007 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 1008 } 1009 } 1010 1011 if (nfreed) { 1012 cq->mcq.cons_index += nfreed; 1013 /* 1014 * Make sure update of buffer contents is done before 1015 * updating consumer index. 1016 */ 1017 wmb(); 1018 mlx4_cq_set_ci(&cq->mcq); 1019 } 1020 } 1021 1022 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 1023 { 1024 spin_lock_irq(&cq->lock); 1025 __mlx4_ib_cq_clean(cq, qpn, srq); 1026 spin_unlock_irq(&cq->lock); 1027 } 1028